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net/mlx5e: Move function mlx5e_create_umr_mkey
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
9bcc8606
SD		 87 priv->params.mpwqe_log_stride_sz =
88 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
2fc4bfb7
SM		 89 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90 MLX5_MPWRQ_LOG_STRIDE_SIZE;
91 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 priv->params.mpwqe_log_stride_sz;
93 break;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
95 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96 }
97 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
98 BIT(priv->params.log_rq_size));
99
100 mlx5_core_info(priv->mdev,
101 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
102 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
103 BIT(priv->params.log_rq_size),
104 BIT(priv->params.mpwqe_log_stride_sz),
9bcc8606 105 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 106}
107
108static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
109{
86994156
RS		 110 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
111 !priv->xdp_prog ?
2fc4bfb7
SM		 112 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
113 MLX5_WQ_TYPE_LINKED_LIST;
114 mlx5e_set_rq_type_params(priv, rq_type);
115}
116
f62b8bb8
AV		 117static void mlx5e_update_carrier(struct mlx5e_priv *priv)
118{
119 struct mlx5_core_dev *mdev = priv->mdev;
120 u8 port_state;
121
122 port_state = mlx5_query_vport_state(mdev,
e7546514 123 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 124
87424ad5
SD		 125 if (port_state == VPORT_STATE_UP) {
126 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 127 netif_carrier_on(priv->netdev);
87424ad5
SD		 128 } else {
129 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 130 netif_carrier_off(priv->netdev);
87424ad5 131 }
f62b8bb8
AV		 132}
133
134static void mlx5e_update_carrier_work(struct work_struct *work)
135{
136 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
137 update_carrier_work);
138
139 mutex_lock(&priv->state_lock);
140 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
141 mlx5e_update_carrier(priv);
142 mutex_unlock(&priv->state_lock);
143}
144
3947ca18
DJ		 145static void mlx5e_tx_timeout_work(struct work_struct *work)
146{
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 tx_timeout_work);
149 int err;
150
151 rtnl_lock();
152 mutex_lock(&priv->state_lock);
153 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
154 goto unlock;
155 mlx5e_close_locked(priv->netdev);
156 err = mlx5e_open_locked(priv->netdev);
157 if (err)
158 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
159 err);
160unlock:
161 mutex_unlock(&priv->state_lock);
162 rtnl_unlock();
163}
164
9218b44d 165static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 166{
9218b44d 167 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 168 struct mlx5e_rq_stats *rq_stats;
169 struct mlx5e_sq_stats *sq_stats;
9218b44d 170 u64 tx_offload_none = 0;
f62b8bb8
AV		 171 int i, j;
172
9218b44d 173 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 174 for (i = 0; i < priv->params.num_channels; i++) {
175 rq_stats = &priv->channel[i]->rq.stats;
176
faf4478b
GP		 177 s->rx_packets += rq_stats->packets;
178 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 179 s->rx_lro_packets += rq_stats->lro_packets;
180 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 181 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 182 s->rx_csum_complete += rq_stats->csum_complete;
183 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 184 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 185 s->rx_xdp_tx += rq_stats->xdp_tx;
186 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 187 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 188 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 189 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 190 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
191 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 192 s->rx_cache_reuse += rq_stats->cache_reuse;
193 s->rx_cache_full += rq_stats->cache_full;
194 s->rx_cache_empty += rq_stats->cache_empty;
195 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 196
a4418a6c 197 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 198 sq_stats = &priv->channel[i]->sq[j].stats;
199
faf4478b
GP		 200 s->tx_packets += sq_stats->packets;
201 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 202 s->tx_tso_packets += sq_stats->tso_packets;
203 s->tx_tso_bytes += sq_stats->tso_bytes;
204 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
205 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 206 s->tx_queue_stopped += sq_stats->stopped;
207 s->tx_queue_wake += sq_stats->wake;
208 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 209 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 210 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
211 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 212 }
213 }
214
9218b44d 215 /* Update calculated offload counters */
bfe6d8d1
GP		 216 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
217 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 218
bfe6d8d1 219 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 220 priv->stats.pport.phy_counters,
221 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 222}
223
224static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
225{
226 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
227 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 228 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 229 struct mlx5_core_dev *mdev = priv->mdev;
230
f62b8bb8
AV		 231 MLX5_SET(query_vport_counter_in, in, opcode,
232 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
233 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
234 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
235
236 memset(out, 0, outlen);
9218b44d
GP		 237 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
238}
239
240static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
241{
242 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
243 struct mlx5_core_dev *mdev = priv->mdev;
244 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 245 int prio;
9218b44d
GP		 246 void *out;
247 u32 *in;
248
249 in = mlx5_vzalloc(sz);
250 if (!in)
f62b8bb8
AV		 251 goto free_out;
252
9218b44d 253 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 254
9218b44d
GP		 255 out = pstats->IEEE_802_3_counters;
256 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
257 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 258
9218b44d
GP		 259 out = pstats->RFC_2863_counters;
260 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
261 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
262
263 out = pstats->RFC_2819_counters;
264 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
265 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 266
121fcdc8
GP		 267 out = pstats->phy_counters;
268 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
269 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
270
cf678570
GP		 271 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
272 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
273 out = pstats->per_prio_counters[prio];
274 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
275 mlx5_core_access_reg(mdev, in, sz, out, sz,
276 MLX5_REG_PPCNT, 0, 0);
277 }
278
f62b8bb8 279free_out:
9218b44d
GP		 280 kvfree(in);
281}
282
283static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
284{
285 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
286
287 if (!priv->q_counter)
288 return;
289
290 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
291 &qcnt->rx_out_of_buffer);
292}
293
9c726239
GP		 294static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
295{
296 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
297 struct mlx5_core_dev *mdev = priv->mdev;
298 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
299 void *out;
300 u32 *in;
301
302 in = mlx5_vzalloc(sz);
303 if (!in)
304 return;
305
306 out = pcie_stats->pcie_perf_counters;
307 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
308 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
309
310 out = pcie_stats->pcie_tas_counters;
311 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
312 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
313
314 kvfree(in);
315}
316
9218b44d
GP		 317void mlx5e_update_stats(struct mlx5e_priv *priv)
318{
9218b44d
GP		 319 mlx5e_update_q_counter(priv);
320 mlx5e_update_vport_counters(priv);
321 mlx5e_update_pport_counters(priv);
121fcdc8 322 mlx5e_update_sw_counters(priv);
9c726239 323 mlx5e_update_pcie_counters(priv);
f62b8bb8
AV		 324}
325
cb67b832 326void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 327{
328 struct delayed_work *dwork = to_delayed_work(work);
329 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
330 update_stats_work);
331 mutex_lock(&priv->state_lock);
332 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 333 priv->profile->update_stats(priv);
7bb29755
MF		 334 queue_delayed_work(priv->wq, dwork,
335 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 336 }
337 mutex_unlock(&priv->state_lock);
338}
339
daa21560
TT		 340static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
341 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 342{
daa21560
TT		 343 struct mlx5e_priv *priv = vpriv;
344
e0f46eb9 345 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 346 return;
347
f62b8bb8
AV		 348 switch (event) {
349 case MLX5_DEV_EVENT_PORT_UP:
350 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 351 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 352 break;
353
354 default:
355 break;
356 }
357}
358
f62b8bb8
AV		 359static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
360{
e0f46eb9 361 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 362}
363
364static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
365{
e0f46eb9 366 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 367 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 368}
369
facc9699
SM		 370#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
371#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
372
7e426671
TT		 373static inline int mlx5e_get_wqe_mtt_sz(void)
374{
375 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
376 * To avoid copying garbage after the mtt array, we allocate
377 * a little more.
378 */
379 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
380 MLX5_UMR_MTT_ALIGNMENT);
381}
382
383static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
384 struct mlx5e_umr_wqe *wqe, u16 ix)
385{
386 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
387 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
388 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 389 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 390 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
391 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
392
393 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
394 ds_cnt);
395 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
396 cseg->imm = rq->mkey_be;
397
398 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
399 ucseg->klm_octowords =
400 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
401 ucseg->bsf_octowords =
402 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
403 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
404
405 dseg->lkey = sq->mkey_be;
406 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
407}
408
409static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
410 struct mlx5e_channel *c)
411{
412 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
413 int mtt_sz = mlx5e_get_wqe_mtt_sz();
414 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
415 int i;
416
21c59685
SM		 417 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
418 GFP_KERNEL, cpu_to_node(c->cpu));
419 if (!rq->mpwqe.info)
7e426671
TT		 420 goto err_out;
421
422 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 423 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 424 cpu_to_node(c->cpu));
21c59685 425 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 426 goto err_free_wqe_info;
427
428 for (i = 0; i < wq_sz; i++) {
21c59685 429 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 430
21c59685 431 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 432 MLX5_UMR_ALIGN);
433 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
434 PCI_DMA_TODEVICE);
435 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
436 goto err_unmap_mtts;
437
438 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
439 }
440
441 return 0;
442
443err_unmap_mtts:
444 while (--i >= 0) {
21c59685 445 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 446
447 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
448 PCI_DMA_TODEVICE);
449 }
21c59685 450 kfree(rq->mpwqe.mtt_no_align);
7e426671 451err_free_wqe_info:
21c59685 452 kfree(rq->mpwqe.info);
7e426671
TT		 453
454err_out:
455 return -ENOMEM;
456}
457
458static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
459{
460 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
461 int mtt_sz = mlx5e_get_wqe_mtt_sz();
462 int i;
463
464 for (i = 0; i < wq_sz; i++) {
21c59685 465 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 466
467 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
468 PCI_DMA_TODEVICE);
469 }
21c59685
SM		 470 kfree(rq->mpwqe.mtt_no_align);
471 kfree(rq->mpwqe.info);
7e426671
TT		 472}
473
3608ae77
TT		 474static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
475{
476 struct mlx5_core_dev *mdev = priv->mdev;
477 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
478 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
479 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
480 void *mkc;
481 u32 *in;
482 int err;
483
484 in = mlx5_vzalloc(inlen);
485 if (!in)
486 return -ENOMEM;
487
488 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
489
490 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
491
492 MLX5_SET(mkc, mkc, free, 1);
493 MLX5_SET(mkc, mkc, umr_en, 1);
494 MLX5_SET(mkc, mkc, lw, 1);
495 MLX5_SET(mkc, mkc, lr, 1);
496 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
497
498 MLX5_SET(mkc, mkc, qpn, 0xffffff);
499 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
500 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
501 MLX5_SET(mkc, mkc, translations_octword_size,
502 MLX5_MTT_OCTW(npages));
503 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
504
505 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
506
507 kvfree(in);
508 return err;
509}
510
f62b8bb8
AV		 511static int mlx5e_create_rq(struct mlx5e_channel *c,
512 struct mlx5e_rq_param *param,
513 struct mlx5e_rq *rq)
514{
515 struct mlx5e_priv *priv = c->priv;
516 struct mlx5_core_dev *mdev = priv->mdev;
517 void *rqc = param->rqc;
518 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 519 u32 byte_count;
1bfecfca
SM		 520 u32 frag_sz;
521 int npages;
f62b8bb8
AV		 522 int wq_sz;
523 int err;
524 int i;
525
311c7c71
SM		 526 param->wq.db_numa_node = cpu_to_node(c->cpu);
527
f62b8bb8
AV		 528 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
529 &rq->wq_ctrl);
530 if (err)
531 return err;
532
533 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
534
535 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 536
7e426671
TT		 537 rq->wq_type = priv->params.rq_wq_type;
538 rq->pdev = c->pdev;
539 rq->netdev = c->netdev;
540 rq->tstamp = &priv->tstamp;
541 rq->channel = c;
542 rq->ix = c->ix;
543 rq->priv = c->priv;
97bc402d
DB		 544
545 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
546 if (IS_ERR(rq->xdp_prog)) {
547 err = PTR_ERR(rq->xdp_prog);
548 rq->xdp_prog = NULL;
549 goto err_rq_wq_destroy;
550 }
7e426671 551
b5503b99
SM		 552 rq->buff.map_dir = DMA_FROM_DEVICE;
553 if (rq->xdp_prog)
554 rq->buff.map_dir = DMA_BIDIRECTIONAL;
555
461017cb
TT		 556 switch (priv->params.rq_wq_type) {
557 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 558 if (mlx5e_is_vf_vport_rep(priv)) {
559 err = -EINVAL;
560 goto err_rq_wq_destroy;
561 }
562
461017cb
TT		 563 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
564 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 565 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 566
21c59685 567 rq->mpwqe.mtt_offset = c->ix *
fe4c988b
SM		 568 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
569
d9d9f156
TT		 570 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
571 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 572
573 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
574 byte_count = rq->buff.wqe_sz;
7e426671
TT		 575 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
576 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
577 if (err)
578 goto err_rq_wq_destroy;
461017cb
TT		 579 break;
580 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 581 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
582 GFP_KERNEL, cpu_to_node(c->cpu));
583 if (!rq->dma_info) {
461017cb
TT		 584 err = -ENOMEM;
585 goto err_rq_wq_destroy;
586 }
1bfecfca 587
f5f82476
OG		 588 if (mlx5e_is_vf_vport_rep(priv))
589 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
590 else
591 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
592
461017cb 593 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 594 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 595
1bfecfca 596 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 597 priv->params.lro_wqe_sz :
598 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 599 byte_count = rq->buff.wqe_sz;
600
601 /* calc the required page order */
602 frag_sz = MLX5_RX_HEADROOM +
603 byte_count /* packet data */ +
604 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
605 frag_sz = SKB_DATA_ALIGN(frag_sz);
606
607 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
608 rq->buff.page_order = order_base_2(npages);
609
461017cb 610 byte_count |= MLX5_HW_START_PADDING;
7e426671 611 rq->mkey_be = c->mkey_be;
461017cb 612 }
f62b8bb8
AV		 613
614 for (i = 0; i < wq_sz; i++) {
615 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
616
461017cb 617 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 618 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 619 }
620
cb3c7fd4
GR		 621 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
622 rq->am.mode = priv->params.rx_cq_period_mode;
623
4415a031
TT		 624 rq->page_cache.head = 0;
625 rq->page_cache.tail = 0;
626
f62b8bb8
AV		 627 return 0;
628
629err_rq_wq_destroy:
97bc402d
DB		 630 if (rq->xdp_prog)
631 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 632 mlx5_wq_destroy(&rq->wq_ctrl);
633
634 return err;
635}
636
637static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
638{
4415a031
TT		 639 int i;
640
86994156
RS		 641 if (rq->xdp_prog)
642 bpf_prog_put(rq->xdp_prog);
643
461017cb
TT		 644 switch (rq->wq_type) {
645 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 646 mlx5e_rq_free_mpwqe_info(rq);
461017cb
TT		 647 break;
648 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 649 kfree(rq->dma_info);
461017cb
TT		 650 }
651
4415a031
TT		 652 for (i = rq->page_cache.head; i != rq->page_cache.tail;
653 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
654 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
655
656 mlx5e_page_release(rq, dma_info, false);
657 }
f62b8bb8
AV		 658 mlx5_wq_destroy(&rq->wq_ctrl);
659}
660
661static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
662{
50cfa25a 663 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 664 struct mlx5_core_dev *mdev = priv->mdev;
665
666 void *in;
667 void *rqc;
668 void *wq;
669 int inlen;
670 int err;
671
672 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
673 sizeof(u64) * rq->wq_ctrl.buf.npages;
674 in = mlx5_vzalloc(inlen);
675 if (!in)
676 return -ENOMEM;
677
678 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
679 wq = MLX5_ADDR_OF(rqc, rqc, wq);
680
681 memcpy(rqc, param->rqc, sizeof(param->rqc));
682
97de9f31 683 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 684 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 685 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 686 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 687 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 688 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
689
690 mlx5_fill_page_array(&rq->wq_ctrl.buf,
691 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
692
7db22ffb 693 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 694
695 kvfree(in);
696
697 return err;
698}
699
36350114
GP		 700static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
701 int next_state)
f62b8bb8
AV		 702{
703 struct mlx5e_channel *c = rq->channel;
704 struct mlx5e_priv *priv = c->priv;
705 struct mlx5_core_dev *mdev = priv->mdev;
706
707 void *in;
708 void *rqc;
709 int inlen;
710 int err;
711
712 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
713 in = mlx5_vzalloc(inlen);
714 if (!in)
715 return -ENOMEM;
716
717 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
718
719 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
720 MLX5_SET(rqc, rqc, state, next_state);
721
7db22ffb 722 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 723
724 kvfree(in);
725
726 return err;
727}
728
36350114
GP		 729static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
730{
731 struct mlx5e_channel *c = rq->channel;
732 struct mlx5e_priv *priv = c->priv;
733 struct mlx5_core_dev *mdev = priv->mdev;
734
735 void *in;
736 void *rqc;
737 int inlen;
738 int err;
739
740 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
741 in = mlx5_vzalloc(inlen);
742 if (!in)
743 return -ENOMEM;
744
745 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
746
747 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 748 MLX5_SET64(modify_rq_in, in, modify_bitmask,
749 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 750 MLX5_SET(rqc, rqc, vsd, vsd);
751 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
752
753 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
754
755 kvfree(in);
756
757 return err;
758}
759
f62b8bb8
AV		 760static void mlx5e_disable_rq(struct mlx5e_rq *rq)
761{
50cfa25a 762 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 763}
764
765static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
766{
01c196a2 767 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 768 struct mlx5e_channel *c = rq->channel;
769 struct mlx5e_priv *priv = c->priv;
770 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 771
01c196a2 772 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 773 if (wq->cur_sz >= priv->params.min_rx_wqes)
774 return 0;
775
776 msleep(20);
777 }
778
779 return -ETIMEDOUT;
780}
781
f2fde18c
SM		 782static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
783{
784 struct mlx5_wq_ll *wq = &rq->wq;
785 struct mlx5e_rx_wqe *wqe;
786 __be16 wqe_ix_be;
787 u16 wqe_ix;
788
8484f9ed
SM		 789 /* UMR WQE (if in progress) is always at wq->head */
790 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 791 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 792
f2fde18c
SM		 793 while (!mlx5_wq_ll_is_empty(wq)) {
794 wqe_ix_be = *wq->tail_next;
795 wqe_ix = be16_to_cpu(wqe_ix_be);
796 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
797 rq->dealloc_wqe(rq, wqe_ix);
798 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
799 &wqe->next.next_wqe_index);
800 }
801}
802
f62b8bb8
AV		 803static int mlx5e_open_rq(struct mlx5e_channel *c,
804 struct mlx5e_rq_param *param,
805 struct mlx5e_rq *rq)
806{
d3c9bc27
TT		 807 struct mlx5e_sq *sq = &c->icosq;
808 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 809 int err;
810
811 err = mlx5e_create_rq(c, param, rq);
812 if (err)
813 return err;
814
815 err = mlx5e_enable_rq(rq, param);
816 if (err)
817 goto err_destroy_rq;
818
36350114 819 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 820 if (err)
821 goto err_disable_rq;
822
cb3c7fd4
GR		 823 if (param->am_enabled)
824 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
825
f10b7cc7
SM		 826 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
827 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 828 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 829
830 return 0;
831
832err_disable_rq:
833 mlx5e_disable_rq(rq);
834err_destroy_rq:
835 mlx5e_destroy_rq(rq);
836
837 return err;
838}
839
840static void mlx5e_close_rq(struct mlx5e_rq *rq)
841{
f2fde18c 842 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
f62b8bb8 843 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 844 cancel_work_sync(&rq->am.work);
845
f62b8bb8 846 mlx5e_disable_rq(rq);
6cd392a0 847 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 848 mlx5e_destroy_rq(rq);
849}
850
b5503b99
SM		 851static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
852{
853 kfree(sq->db.xdp.di);
854 kfree(sq->db.xdp.wqe_info);
855}
856
857static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
858{
859 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
860
861 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
862 GFP_KERNEL, numa);
863 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
864 GFP_KERNEL, numa);
865 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
866 mlx5e_free_sq_xdp_db(sq);
867 return -ENOMEM;
868 }
869
870 return 0;
871}
872
f10b7cc7 873static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 874{
f10b7cc7 875 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 876}
877
f10b7cc7
SM		 878static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
879{
880 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
881
882 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
883 GFP_KERNEL, numa);
884 if (!sq->db.ico_wqe)
885 return -ENOMEM;
886
887 return 0;
888}
889
890static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
891{
892 kfree(sq->db.txq.wqe_info);
893 kfree(sq->db.txq.dma_fifo);
894 kfree(sq->db.txq.skb);
895}
896
897static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 898{
899 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
900 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
901
f10b7cc7
SM		 902 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
903 GFP_KERNEL, numa);
904 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
905 GFP_KERNEL, numa);
906 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
907 GFP_KERNEL, numa);
908 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
909 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 910 return -ENOMEM;
911 }
912
913 sq->dma_fifo_mask = df_sz - 1;
914
915 return 0;
916}
917
f10b7cc7
SM		 918static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
919{
920 switch (sq->type) {
921 case MLX5E_SQ_TXQ:
922 mlx5e_free_sq_txq_db(sq);
923 break;
924 case MLX5E_SQ_ICO:
925 mlx5e_free_sq_ico_db(sq);
926 break;
b5503b99
SM		 927 case MLX5E_SQ_XDP:
928 mlx5e_free_sq_xdp_db(sq);
929 break;
f10b7cc7
SM		 930 }
931}
932
933static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
934{
935 switch (sq->type) {
936 case MLX5E_SQ_TXQ:
937 return mlx5e_alloc_sq_txq_db(sq, numa);
938 case MLX5E_SQ_ICO:
939 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 940 case MLX5E_SQ_XDP:
941 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 942 }
943
944 return 0;
945}
946
b5503b99
SM		 947static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
948{
949 switch (sq_type) {
950 case MLX5E_SQ_ICO:
951 return MLX5E_ICOSQ_MAX_WQEBBS;
952 case MLX5E_SQ_XDP:
953 return MLX5E_XDP_TX_WQEBBS;
954 }
955 return MLX5_SEND_WQE_MAX_WQEBBS;
956}
957
f62b8bb8
AV		 958static int mlx5e_create_sq(struct mlx5e_channel *c,
959 int tc,
960 struct mlx5e_sq_param *param,
961 struct mlx5e_sq *sq)
962{
963 struct mlx5e_priv *priv = c->priv;
964 struct mlx5_core_dev *mdev = priv->mdev;
965
966 void *sqc = param->sqc;
967 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
968 int err;
969
f10b7cc7
SM		 970 sq->type = param->type;
971 sq->pdev = c->pdev;
972 sq->tstamp = &priv->tstamp;
973 sq->mkey_be = c->mkey_be;
974 sq->channel = c;
975 sq->tc = tc;
976
fd4782c2 977 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 978 if (err)
979 return err;
980
311c7c71
SM		 981 param->wq.db_numa_node = cpu_to_node(c->cpu);
982
f62b8bb8
AV		 983 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
984 &sq->wq_ctrl);
985 if (err)
986 goto err_unmap_free_uar;
987
988 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 989 if (sq->uar.bf_map) {
990 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
991 sq->uar_map = sq->uar.bf_map;
992 } else {
993 sq->uar_map = sq->uar.map;
994 }
f62b8bb8 995 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 996 sq->max_inline = param->max_inline;
cff92d7c 997 sq->min_inline_mode =
34e4e990 998 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
cff92d7c 999 param->min_inline_mode : 0;
f62b8bb8 1000
7ec0bb22
DC		 1001 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1002 if (err)
f62b8bb8
AV		 1003 goto err_sq_wq_destroy;
1004
f10b7cc7 1005 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 1006 int txq_ix;
1007
1008 txq_ix = c->ix + tc * priv->params.num_channels;
1009 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1010 priv->txq_to_sq_map[txq_ix] = sq;
1011 }
f62b8bb8 1012
b5503b99 1013 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 1014 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 1015
1016 return 0;
1017
1018err_sq_wq_destroy:
1019 mlx5_wq_destroy(&sq->wq_ctrl);
1020
1021err_unmap_free_uar:
1022 mlx5_unmap_free_uar(mdev, &sq->uar);
1023
1024 return err;
1025}
1026
1027static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1028{
1029 struct mlx5e_channel *c = sq->channel;
1030 struct mlx5e_priv *priv = c->priv;
1031
1032 mlx5e_free_sq_db(sq);
1033 mlx5_wq_destroy(&sq->wq_ctrl);
1034 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1035}
1036
1037static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1038{
1039 struct mlx5e_channel *c = sq->channel;
1040 struct mlx5e_priv *priv = c->priv;
1041 struct mlx5_core_dev *mdev = priv->mdev;
1042
1043 void *in;
1044 void *sqc;
1045 void *wq;
1046 int inlen;
1047 int err;
1048
1049 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1050 sizeof(u64) * sq->wq_ctrl.buf.npages;
1051 in = mlx5_vzalloc(inlen);
1052 if (!in)
1053 return -ENOMEM;
1054
1055 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1056 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1057
1058 memcpy(sqc, param->sqc, sizeof(param->sqc));
1059
f10b7cc7
SM		 1060 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1061 0 : priv->tisn[sq->tc]);
d3c9bc27 1062 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1063 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1064 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1065 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1066 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1067
1068 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1069 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1070 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1071 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1072 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1073
1074 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1075 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1076
7db22ffb 1077 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1078
1079 kvfree(in);
1080
1081 return err;
1082}
1083
507f0c81
YP		 1084static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1085 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1086{
1087 struct mlx5e_channel *c = sq->channel;
1088 struct mlx5e_priv *priv = c->priv;
1089 struct mlx5_core_dev *mdev = priv->mdev;
1090
1091 void *in;
1092 void *sqc;
1093 int inlen;
1094 int err;
1095
1096 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1097 in = mlx5_vzalloc(inlen);
1098 if (!in)
1099 return -ENOMEM;
1100
1101 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1102
1103 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1104 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1105 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1106 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1107 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1108 }
f62b8bb8 1109
7db22ffb 1110 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1111
1112 kvfree(in);
1113
1114 return err;
1115}
1116
1117static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1118{
1119 struct mlx5e_channel *c = sq->channel;
1120 struct mlx5e_priv *priv = c->priv;
1121 struct mlx5_core_dev *mdev = priv->mdev;
1122
7db22ffb 1123 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1124 if (sq->rate_limit)
1125 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1126}
1127
1128static int mlx5e_open_sq(struct mlx5e_channel *c,
1129 int tc,
1130 struct mlx5e_sq_param *param,
1131 struct mlx5e_sq *sq)
1132{
1133 int err;
1134
1135 err = mlx5e_create_sq(c, tc, param, sq);
1136 if (err)
1137 return err;
1138
1139 err = mlx5e_enable_sq(sq, param);
1140 if (err)
1141 goto err_destroy_sq;
1142
507f0c81
YP		 1143 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1144 false, 0);
f62b8bb8
AV		 1145 if (err)
1146 goto err_disable_sq;
1147
d3c9bc27 1148 if (sq->txq) {
d3c9bc27
TT		 1149 netdev_tx_reset_queue(sq->txq);
1150 netif_tx_start_queue(sq->txq);
1151 }
f62b8bb8
AV		 1152
1153 return 0;
1154
1155err_disable_sq:
1156 mlx5e_disable_sq(sq);
1157err_destroy_sq:
1158 mlx5e_destroy_sq(sq);
1159
1160 return err;
1161}
1162
1163static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1164{
1165 __netif_tx_lock_bh(txq);
1166 netif_tx_stop_queue(txq);
1167 __netif_tx_unlock_bh(txq);
1168}
1169
1170static void mlx5e_close_sq(struct mlx5e_sq *sq)
1171{
6e8dd6d6
SM		 1172 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1173 /* prevent netif_tx_wake_queue */
1174 napi_synchronize(&sq->channel->napi);
29429f33 1175
d3c9bc27 1176 if (sq->txq) {
d3c9bc27 1177 netif_tx_disable_queue(sq->txq);
f62b8bb8 1178
6e8dd6d6 1179 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1180 if (mlx5e_sq_has_room_for(sq, 1)) {
1181 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1182 mlx5e_send_nop(sq, true);
f10b7cc7 1183 }
29429f33 1184 }
f62b8bb8 1185
f62b8bb8 1186 mlx5e_disable_sq(sq);
b5503b99 1187 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1188 mlx5e_destroy_sq(sq);
1189}
1190
1191static int mlx5e_create_cq(struct mlx5e_channel *c,
1192 struct mlx5e_cq_param *param,
1193 struct mlx5e_cq *cq)
1194{
1195 struct mlx5e_priv *priv = c->priv;
1196 struct mlx5_core_dev *mdev = priv->mdev;
1197 struct mlx5_core_cq *mcq = &cq->mcq;
1198 int eqn_not_used;
0b6e26ce 1199 unsigned int irqn;
f62b8bb8
AV		 1200 int err;
1201 u32 i;
1202
311c7c71
SM		 1203 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1204 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1205 param->eq_ix = c->ix;
1206
1207 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1208 &cq->wq_ctrl);
1209 if (err)
1210 return err;
1211
1212 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1213
1214 cq->napi = &c->napi;
1215
1216 mcq->cqe_sz = 64;
1217 mcq->set_ci_db = cq->wq_ctrl.db.db;
1218 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1219 *mcq->set_ci_db = 0;
1220 *mcq->arm_db = 0;
1221 mcq->vector = param->eq_ix;
1222 mcq->comp = mlx5e_completion_event;
1223 mcq->event = mlx5e_cq_error_event;
1224 mcq->irqn = irqn;
b50d292b 1225 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 1226
1227 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1228 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1229
1230 cqe->op_own = 0xf1;
1231 }
1232
1233 cq->channel = c;
50cfa25a 1234 cq->priv = priv;
f62b8bb8
AV		 1235
1236 return 0;
1237}
1238
1239static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1240{
1c1b5228 1241 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1242}
1243
1244static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1245{
50cfa25a 1246 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1247 struct mlx5_core_dev *mdev = priv->mdev;
1248 struct mlx5_core_cq *mcq = &cq->mcq;
1249
1250 void *in;
1251 void *cqc;
1252 int inlen;
0b6e26ce 1253 unsigned int irqn_not_used;
f62b8bb8
AV		 1254 int eqn;
1255 int err;
1256
1257 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1258 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1259 in = mlx5_vzalloc(inlen);
1260 if (!in)
1261 return -ENOMEM;
1262
1263 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1264
1265 memcpy(cqc, param->cqc, sizeof(param->cqc));
1266
1c1b5228
TT		 1267 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1268 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1269
1270 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1271
9908aa29 1272 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 1273 MLX5_SET(cqc, cqc, c_eqn, eqn);
1274 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1c1b5228 1275 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1276 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1277 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1278
1279 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1280
1281 kvfree(in);
1282
1283 if (err)
1284 return err;
1285
1286 mlx5e_cq_arm(cq);
1287
1288 return 0;
1289}
1290
1291static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1292{
50cfa25a 1293 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1294 struct mlx5_core_dev *mdev = priv->mdev;
1295
1296 mlx5_core_destroy_cq(mdev, &cq->mcq);
1297}
1298
1299static int mlx5e_open_cq(struct mlx5e_channel *c,
1300 struct mlx5e_cq_param *param,
1301 struct mlx5e_cq *cq,
9908aa29 1302 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1303{
1304 int err;
1305 struct mlx5e_priv *priv = c->priv;
1306 struct mlx5_core_dev *mdev = priv->mdev;
1307
1308 err = mlx5e_create_cq(c, param, cq);
1309 if (err)
1310 return err;
1311
1312 err = mlx5e_enable_cq(cq, param);
1313 if (err)
1314 goto err_destroy_cq;
1315
7524a5d8
GP		 1316 if (MLX5_CAP_GEN(mdev, cq_moderation))
1317 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1318 moderation.usec,
1319 moderation.pkts);
f62b8bb8
AV		 1320 return 0;
1321
1322err_destroy_cq:
1323 mlx5e_destroy_cq(cq);
1324
1325 return err;
1326}
1327
1328static void mlx5e_close_cq(struct mlx5e_cq *cq)
1329{
1330 mlx5e_disable_cq(cq);
1331 mlx5e_destroy_cq(cq);
1332}
1333
1334static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1335{
1336 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1337}
1338
1339static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1340 struct mlx5e_channel_param *cparam)
1341{
1342 struct mlx5e_priv *priv = c->priv;
1343 int err;
1344 int tc;
1345
1346 for (tc = 0; tc < c->num_tc; tc++) {
1347 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1348 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1349 if (err)
1350 goto err_close_tx_cqs;
f62b8bb8
AV		 1351 }
1352
1353 return 0;
1354
1355err_close_tx_cqs:
1356 for (tc--; tc >= 0; tc--)
1357 mlx5e_close_cq(&c->sq[tc].cq);
1358
1359 return err;
1360}
1361
1362static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1363{
1364 int tc;
1365
1366 for (tc = 0; tc < c->num_tc; tc++)
1367 mlx5e_close_cq(&c->sq[tc].cq);
1368}
1369
1370static int mlx5e_open_sqs(struct mlx5e_channel *c,
1371 struct mlx5e_channel_param *cparam)
1372{
1373 int err;
1374 int tc;
1375
1376 for (tc = 0; tc < c->num_tc; tc++) {
1377 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1378 if (err)
1379 goto err_close_sqs;
1380 }
1381
1382 return 0;
1383
1384err_close_sqs:
1385 for (tc--; tc >= 0; tc--)
1386 mlx5e_close_sq(&c->sq[tc]);
1387
1388 return err;
1389}
1390
1391static void mlx5e_close_sqs(struct mlx5e_channel *c)
1392{
1393 int tc;
1394
1395 for (tc = 0; tc < c->num_tc; tc++)
1396 mlx5e_close_sq(&c->sq[tc]);
1397}
1398
5283af89 1399static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1400{
1401 int i;
1402
6bfd390b 1403 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1404 priv->channeltc_to_txq_map[ix][i] =
1405 ix + i * priv->params.num_channels;
03289b88
SM		 1406}
1407
507f0c81
YP		 1408static int mlx5e_set_sq_maxrate(struct net_device *dev,
1409 struct mlx5e_sq *sq, u32 rate)
1410{
1411 struct mlx5e_priv *priv = netdev_priv(dev);
1412 struct mlx5_core_dev *mdev = priv->mdev;
1413 u16 rl_index = 0;
1414 int err;
1415
1416 if (rate == sq->rate_limit)
1417 /* nothing to do */
1418 return 0;
1419
1420 if (sq->rate_limit)
1421 /* remove current rl index to free space to next ones */
1422 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1423
1424 sq->rate_limit = 0;
1425
1426 if (rate) {
1427 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1428 if (err) {
1429 netdev_err(dev, "Failed configuring rate %u: %d\n",
1430 rate, err);
1431 return err;
1432 }
1433 }
1434
1435 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1436 MLX5_SQC_STATE_RDY, true, rl_index);
1437 if (err) {
1438 netdev_err(dev, "Failed configuring rate %u: %d\n",
1439 rate, err);
1440 /* remove the rate from the table */
1441 if (rate)
1442 mlx5_rl_remove_rate(mdev, rate);
1443 return err;
1444 }
1445
1446 sq->rate_limit = rate;
1447 return 0;
1448}
1449
1450static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1451{
1452 struct mlx5e_priv *priv = netdev_priv(dev);
1453 struct mlx5_core_dev *mdev = priv->mdev;
1454 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1455 int err = 0;
1456
1457 if (!mlx5_rl_is_supported(mdev)) {
1458 netdev_err(dev, "Rate limiting is not supported on this device\n");
1459 return -EINVAL;
1460 }
1461
1462 /* rate is given in Mb/sec, HW config is in Kb/sec */
1463 rate = rate << 10;
1464
1465 /* Check whether rate in valid range, 0 is always valid */
1466 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1467 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1468 return -ERANGE;
1469 }
1470
1471 mutex_lock(&priv->state_lock);
1472 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1473 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1474 if (!err)
1475 priv->tx_rates[index] = rate;
1476 mutex_unlock(&priv->state_lock);
1477
1478 return err;
1479}
1480
f62b8bb8
AV		 1481static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1482 struct mlx5e_channel_param *cparam,
1483 struct mlx5e_channel **cp)
1484{
9908aa29 1485 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1486 struct net_device *netdev = priv->netdev;
cb3c7fd4 1487 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1488 int cpu = mlx5e_get_cpu(priv, ix);
1489 struct mlx5e_channel *c;
507f0c81 1490 struct mlx5e_sq *sq;
f62b8bb8 1491 int err;
507f0c81 1492 int i;
f62b8bb8
AV		 1493
1494 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1495 if (!c)
1496 return -ENOMEM;
1497
1498 c->priv = priv;
1499 c->ix = ix;
1500 c->cpu = cpu;
1501 c->pdev = &priv->mdev->pdev->dev;
1502 c->netdev = priv->netdev;
b50d292b 1503 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1504 c->num_tc = priv->params.num_tc;
d7a0ecab 1505 c->xdp = !!priv->xdp_prog;
f62b8bb8 1506
cb3c7fd4
GR		 1507 if (priv->params.rx_am_enabled)
1508 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1509 else
1510 rx_cq_profile = priv->params.rx_cq_moderation;
1511
5283af89 1512 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1513
f62b8bb8
AV		 1514 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1515
9908aa29 1516 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1517 if (err)
1518 goto err_napi_del;
1519
d3c9bc27
TT		 1520 err = mlx5e_open_tx_cqs(c, cparam);
1521 if (err)
1522 goto err_close_icosq_cq;
1523
f62b8bb8 1524 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1525 rx_cq_profile);
f62b8bb8
AV		 1526 if (err)
1527 goto err_close_tx_cqs;
f62b8bb8 1528
d7a0ecab
SM		 1529 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1530 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1531 priv->params.tx_cq_moderation) : 0;
1532 if (err)
1533 goto err_close_rx_cq;
1534
f62b8bb8
AV		 1535 napi_enable(&c->napi);
1536
d3c9bc27 1537 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1538 if (err)
1539 goto err_disable_napi;
1540
d3c9bc27
TT		 1541 err = mlx5e_open_sqs(c, cparam);
1542 if (err)
1543 goto err_close_icosq;
1544
507f0c81
YP		 1545 for (i = 0; i < priv->params.num_tc; i++) {
1546 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1547
1548 if (priv->tx_rates[txq_ix]) {
1549 sq = priv->txq_to_sq_map[txq_ix];
1550 mlx5e_set_sq_maxrate(priv->netdev, sq,
1551 priv->tx_rates[txq_ix]);
1552 }
1553 }
1554
d7a0ecab
SM		 1555 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1556 if (err)
1557 goto err_close_sqs;
b5503b99 1558
f62b8bb8
AV		 1559 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1560 if (err)
b5503b99 1561 goto err_close_xdp_sq;
f62b8bb8
AV		 1562
1563 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1564 *cp = c;
1565
1566 return 0;
b5503b99 1567err_close_xdp_sq:
d7a0ecab 1568 if (c->xdp)
87dc0255 1569 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1570
1571err_close_sqs:
1572 mlx5e_close_sqs(c);
1573
d3c9bc27
TT		 1574err_close_icosq:
1575 mlx5e_close_sq(&c->icosq);
1576
f62b8bb8
AV		 1577err_disable_napi:
1578 napi_disable(&c->napi);
d7a0ecab
SM		 1579 if (c->xdp)
1580 mlx5e_close_cq(&c->xdp_sq.cq);
1581
1582err_close_rx_cq:
f62b8bb8
AV		 1583 mlx5e_close_cq(&c->rq.cq);
1584
1585err_close_tx_cqs:
1586 mlx5e_close_tx_cqs(c);
1587
d3c9bc27
TT		 1588err_close_icosq_cq:
1589 mlx5e_close_cq(&c->icosq.cq);
1590
f62b8bb8
AV		 1591err_napi_del:
1592 netif_napi_del(&c->napi);
1593 kfree(c);
1594
1595 return err;
1596}
1597
1598static void mlx5e_close_channel(struct mlx5e_channel *c)
1599{
1600 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1601 if (c->xdp)
1602 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1603 mlx5e_close_sqs(c);
d3c9bc27 1604 mlx5e_close_sq(&c->icosq);
f62b8bb8 1605 napi_disable(&c->napi);
b5503b99
SM		 1606 if (c->xdp)
1607 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1608 mlx5e_close_cq(&c->rq.cq);
1609 mlx5e_close_tx_cqs(c);
d3c9bc27 1610 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1611 netif_napi_del(&c->napi);
7ae92ae5 1612
f62b8bb8
AV		 1613 kfree(c);
1614}
1615
1616static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1617 struct mlx5e_rq_param *param)
1618{
1619 void *rqc = param->rqc;
1620 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1621
461017cb
TT		 1622 switch (priv->params.rq_wq_type) {
1623 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1624 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1625 priv->params.mpwqe_log_num_strides - 9);
461017cb 1626 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1627 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1628 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1629 break;
1630 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1631 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1632 }
1633
f62b8bb8
AV		 1634 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1635 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1636 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1637 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1638 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1639
311c7c71 1640 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1641 param->wq.linear = 1;
cb3c7fd4
GR		 1642
1643 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1644}
1645
556dd1b9
TT		 1646static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1647{
1648 void *rqc = param->rqc;
1649 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1650
1651 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1652 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1653}
1654
d3c9bc27
TT		 1655static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1656 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1657{
1658 void *sqc = param->sqc;
1659 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1660
f62b8bb8 1661 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1662 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1663
311c7c71 1664 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1665}
1666
1667static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1668 struct mlx5e_sq_param *param)
1669{
1670 void *sqc = param->sqc;
1671 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1672
1673 mlx5e_build_sq_param_common(priv, param);
1674 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1675
58d52291 1676 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1677 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1678 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1679}
1680
1681static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1682 struct mlx5e_cq_param *param)
1683{
1684 void *cqc = param->cqc;
1685
b50d292b 1686 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1687}
1688
1689static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1690 struct mlx5e_cq_param *param)
1691{
1692 void *cqc = param->cqc;
461017cb 1693 u8 log_cq_size;
f62b8bb8 1694
461017cb
TT		 1695 switch (priv->params.rq_wq_type) {
1696 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1697 log_cq_size = priv->params.log_rq_size +
d9d9f156 1698 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1699 break;
1700 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1701 log_cq_size = priv->params.log_rq_size;
1702 }
1703
1704 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
9bcc8606 1705 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1706 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1707 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1708 }
f62b8bb8
AV		 1709
1710 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1711
1712 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1713}
1714
1715static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1716 struct mlx5e_cq_param *param)
1717{
1718 void *cqc = param->cqc;
1719
d3c9bc27 1720 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1721
1722 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1723
1724 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1725}
1726
d3c9bc27
TT		 1727static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1728 struct mlx5e_cq_param *param,
1729 u8 log_wq_size)
1730{
1731 void *cqc = param->cqc;
1732
1733 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1734
1735 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1736
1737 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1738}
1739
1740static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1741 struct mlx5e_sq_param *param,
1742 u8 log_wq_size)
1743{
1744 void *sqc = param->sqc;
1745 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1746
1747 mlx5e_build_sq_param_common(priv, param);
1748
1749 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1750 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1751
f10b7cc7 1752 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1753}
1754
b5503b99
SM		 1755static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1756 struct mlx5e_sq_param *param)
1757{
1758 void *sqc = param->sqc;
1759 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1760
1761 mlx5e_build_sq_param_common(priv, param);
1762 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1763
1764 param->max_inline = priv->params.tx_max_inline;
1765 /* FOR XDP SQs will support only L2 inline mode */
1766 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1767 param->type = MLX5E_SQ_XDP;
1768}
1769
6b87663f 1770static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1771{
bc77b240 1772 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1773
f62b8bb8
AV		 1774 mlx5e_build_rq_param(priv, &cparam->rq);
1775 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1776 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1777 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1778 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1779 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1780 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1781}
1782
1783static int mlx5e_open_channels(struct mlx5e_priv *priv)
1784{
6b87663f 1785 struct mlx5e_channel_param *cparam;
a4418a6c 1786 int nch = priv->params.num_channels;
03289b88 1787 int err = -ENOMEM;
f62b8bb8
AV		 1788 int i;
1789 int j;
1790
a4418a6c
AS		 1791 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1792 GFP_KERNEL);
03289b88 1793
a4418a6c 1794 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1795 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1796
6b87663f
AB		 1797 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1798
1799 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1800 goto err_free_txq_to_sq_map;
f62b8bb8 1801
6b87663f
AB		 1802 mlx5e_build_channel_param(priv, cparam);
1803
a4418a6c 1804 for (i = 0; i < nch; i++) {
6b87663f 1805 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1806 if (err)
1807 goto err_close_channels;
1808 }
1809
a4418a6c 1810 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1811 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1812 if (err)
1813 goto err_close_channels;
1814 }
1815
c3b7c5c9
MHY		 1816 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1817 * polling for inactive tx queues.
1818 */
1819 netif_tx_start_all_queues(priv->netdev);
1820
6b87663f 1821 kfree(cparam);
f62b8bb8
AV		 1822 return 0;
1823
1824err_close_channels:
1825 for (i--; i >= 0; i--)
1826 mlx5e_close_channel(priv->channel[i]);
1827
03289b88
SM		 1828err_free_txq_to_sq_map:
1829 kfree(priv->txq_to_sq_map);
f62b8bb8 1830 kfree(priv->channel);
6b87663f 1831 kfree(cparam);
f62b8bb8
AV		 1832
1833 return err;
1834}
1835
1836static void mlx5e_close_channels(struct mlx5e_priv *priv)
1837{
1838 int i;
1839
c3b7c5c9
MHY		 1840 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1841 * polling for inactive tx queues.
1842 */
1843 netif_tx_stop_all_queues(priv->netdev);
1844 netif_tx_disable(priv->netdev);
1845
f62b8bb8
AV		 1846 for (i = 0; i < priv->params.num_channels; i++)
1847 mlx5e_close_channel(priv->channel[i]);
1848
03289b88 1849 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1850 kfree(priv->channel);
1851}
1852
2be6967c
SM		 1853static int mlx5e_rx_hash_fn(int hfunc)
1854{
1855 return (hfunc == ETH_RSS_HASH_TOP) ?
1856 MLX5_RX_HASH_FN_TOEPLITZ :
1857 MLX5_RX_HASH_FN_INVERTED_XOR8;
1858}
1859
1860static int mlx5e_bits_invert(unsigned long a, int size)
1861{
1862 int inv = 0;
1863 int i;
1864
1865 for (i = 0; i < size; i++)
1866 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1867
1868 return inv;
1869}
1870
936896e9
AS		 1871static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1872{
1873 int i;
1874
1875 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1876 int ix = i;
1da36696 1877 u32 rqn;
936896e9
AS		 1878
1879 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1880 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1881
2d75b2bc 1882 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1883 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1884 priv->channel[ix]->rq.rqn :
1885 priv->drop_rq.rqn;
1886 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1887 }
1888}
1889
1da36696
TT		 1890static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1891 int ix)
4cbeaff5 1892{
1da36696
TT		 1893 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1894 priv->channel[ix]->rq.rqn :
1895 priv->drop_rq.rqn;
4cbeaff5 1896
1da36696 1897 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1898}
1899
398f3351
HHZ		 1900static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1901 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1902{
1903 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1904 void *rqtc;
1905 int inlen;
1906 int err;
1da36696 1907 u32 *in;
f62b8bb8 1908
f62b8bb8
AV		 1909 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1910 in = mlx5_vzalloc(inlen);
1911 if (!in)
1912 return -ENOMEM;
1913
1914 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1915
1916 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1917 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1918
1da36696
TT		 1919 if (sz > 1) /* RSS */
1920 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1921 else
1922 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1923
398f3351
HHZ		 1924 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1925 if (!err)
1926 rqt->enabled = true;
f62b8bb8
AV		 1927
1928 kvfree(in);
1da36696
TT		 1929 return err;
1930}
1931
cb67b832 1932void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1933{
398f3351
HHZ		 1934 rqt->enabled = false;
1935 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1936}
1937
6bfd390b
HHZ		 1938static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1939{
1940 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1941
1942 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1943}
1944
cb67b832 1945int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1946{
398f3351 1947 struct mlx5e_rqt *rqt;
1da36696
TT		 1948 int err;
1949 int ix;
1950
6bfd390b 1951 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1952 rqt = &priv->direct_tir[ix].rqt;
1953 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1954 if (err)
1955 goto err_destroy_rqts;
1956 }
1957
1958 return 0;
1959
1960err_destroy_rqts:
1961 for (ix--; ix >= 0; ix--)
398f3351 1962 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1963
f62b8bb8
AV		 1964 return err;
1965}
1966
1da36696 1967int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1968{
1969 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1970 void *rqtc;
1971 int inlen;
1da36696 1972 u32 *in;
5c50368f
AS		 1973 int err;
1974
5c50368f
AS		 1975 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1976 in = mlx5_vzalloc(inlen);
1977 if (!in)
1978 return -ENOMEM;
1979
1980 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1981
1982 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1983 if (sz > 1) /* RSS */
1984 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1985 else
1986 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1987
1988 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1989
1da36696 1990 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1991
1992 kvfree(in);
1993
1994 return err;
1995}
1996
40ab6a6e
AS		 1997static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1998{
1da36696
TT		 1999 u32 rqtn;
2000 int ix;
2001
398f3351
HHZ		 2002 if (priv->indir_rqt.enabled) {
2003 rqtn = priv->indir_rqt.rqtn;
2004 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2005 }
2006
1da36696 2007 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 2008 if (!priv->direct_tir[ix].rqt.enabled)
2009 continue;
2010 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 2011 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2012 }
40ab6a6e
AS		 2013}
2014
5c50368f
AS		 2015static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2016{
2017 if (!priv->params.lro_en)
2018 return;
2019
2020#define ROUGH_MAX_L2_L3_HDR_SZ 256
2021
2022 MLX5_SET(tirc, tirc, lro_enable_mask,
2023 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2024 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2025 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2026 (priv->params.lro_wqe_sz -
2027 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 2028 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 2029}
2030
bdfc028d
TT		 2031void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2032{
2033 MLX5_SET(tirc, tirc, rx_hash_fn,
2034 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2035 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2036 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2037 rx_hash_toeplitz_key);
2038 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2039 rx_hash_toeplitz_key);
2040
2041 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2042 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2043 }
2044}
2045
ab0394fe 2046static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2047{
2048 struct mlx5_core_dev *mdev = priv->mdev;
2049
2050 void *in;
2051 void *tirc;
2052 int inlen;
2053 int err;
ab0394fe 2054 int tt;
1da36696 2055 int ix;
5c50368f
AS		 2056
2057 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2058 in = mlx5_vzalloc(inlen);
2059 if (!in)
2060 return -ENOMEM;
2061
2062 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2063 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2064
2065 mlx5e_build_tir_ctx_lro(tirc, priv);
2066
1da36696 2067 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2068 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2069 inlen);
ab0394fe 2070 if (err)
1da36696 2071 goto free_in;
ab0394fe 2072 }
5c50368f 2073
6bfd390b 2074 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2075 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2076 in, inlen);
2077 if (err)
2078 goto free_in;
2079 }
2080
2081free_in:
5c50368f
AS		 2082 kvfree(in);
2083
2084 return err;
2085}
2086
cd255eff 2087static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2088{
40ab6a6e 2089 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2090 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2091 int err;
2092
cd255eff 2093 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2094 if (err)
2095 return err;
2096
cd255eff
SM		 2097 /* Update vport context MTU */
2098 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2099 return 0;
2100}
40ab6a6e 2101
cd255eff
SM		 2102static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2103{
2104 struct mlx5_core_dev *mdev = priv->mdev;
2105 u16 hw_mtu = 0;
2106 int err;
40ab6a6e 2107
cd255eff
SM		 2108 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2109 if (err || !hw_mtu) /* fallback to port oper mtu */
2110 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2111
2112 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2113}
2114
2115static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2116{
2117 struct mlx5e_priv *priv = netdev_priv(netdev);
2118 u16 mtu;
2119 int err;
2120
2121 err = mlx5e_set_mtu(priv, netdev->mtu);
2122 if (err)
2123 return err;
40ab6a6e 2124
cd255eff
SM		 2125 mlx5e_query_mtu(priv, &mtu);
2126 if (mtu != netdev->mtu)
2127 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2128 __func__, mtu, netdev->mtu);
40ab6a6e 2129
cd255eff 2130 netdev->mtu = mtu;
40ab6a6e
AS		 2131 return 0;
2132}
2133
08fb1dac
SM		 2134static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2135{
2136 struct mlx5e_priv *priv = netdev_priv(netdev);
2137 int nch = priv->params.num_channels;
2138 int ntc = priv->params.num_tc;
2139 int tc;
2140
2141 netdev_reset_tc(netdev);
2142
2143 if (ntc == 1)
2144 return;
2145
2146 netdev_set_num_tc(netdev, ntc);
2147
7ccdd084
RS		 2148 /* Map netdev TCs to offset 0
2149 * We have our own UP to TXQ mapping for QoS
2150 */
08fb1dac 2151 for (tc = 0; tc < ntc; tc++)
7ccdd084 2152 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2153}
2154
40ab6a6e
AS		 2155int mlx5e_open_locked(struct net_device *netdev)
2156{
2157 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2158 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2159 int num_txqs;
2160 int err;
2161
2162 set_bit(MLX5E_STATE_OPENED, &priv->state);
2163
08fb1dac
SM		 2164 mlx5e_netdev_set_tcs(netdev);
2165
40ab6a6e
AS		 2166 num_txqs = priv->params.num_channels * priv->params.num_tc;
2167 netif_set_real_num_tx_queues(netdev, num_txqs);
2168 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2169
40ab6a6e
AS		 2170 err = mlx5e_open_channels(priv);
2171 if (err) {
2172 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2173 __func__, err);
343b29f3 2174 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2175 }
2176
0952da79 2177 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
66189961
TT		 2178 if (err) {
2179 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2180 __func__, err);
2181 goto err_close_channels;
2182 }
2183
40ab6a6e 2184 mlx5e_redirect_rqts(priv);
ce89ef36 2185 mlx5e_update_carrier(priv);
ef9814de 2186 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2187#ifdef CONFIG_RFS_ACCEL
2188 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2189#endif
cb67b832
HHZ		 2190 if (priv->profile->update_stats)
2191 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2192
cb67b832
HHZ		 2193 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2194 err = mlx5e_add_sqs_fwd_rules(priv);
2195 if (err)
2196 goto err_close_channels;
2197 }
9b37b07f 2198 return 0;
343b29f3 2199
66189961
TT		 2200err_close_channels:
2201 mlx5e_close_channels(priv);
343b29f3
AS		 2202err_clear_state_opened_flag:
2203 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2204 return err;
40ab6a6e
AS		 2205}
2206
cb67b832 2207int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2208{
2209 struct mlx5e_priv *priv = netdev_priv(netdev);
2210 int err;
2211
2212 mutex_lock(&priv->state_lock);
2213 err = mlx5e_open_locked(netdev);
2214 mutex_unlock(&priv->state_lock);
2215
2216 return err;
2217}
2218
2219int mlx5e_close_locked(struct net_device *netdev)
2220{
2221 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2222 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2223
a1985740
AS		 2224 /* May already be CLOSED in case a previous configuration operation
2225 * (e.g RX/TX queue size change) that involves close&open failed.
2226 */
2227 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2228 return 0;
2229
40ab6a6e
AS		 2230 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2231
cb67b832
HHZ		 2232 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2233 mlx5e_remove_sqs_fwd_rules(priv);
2234
ef9814de 2235 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2236 netif_carrier_off(priv->netdev);
ce89ef36 2237 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2238 mlx5e_close_channels(priv);
2239
2240 return 0;
2241}
2242
cb67b832 2243int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2244{
2245 struct mlx5e_priv *priv = netdev_priv(netdev);
2246 int err;
2247
26e59d80
MHY		 2248 if (!netif_device_present(netdev))
2249 return -ENODEV;
2250
40ab6a6e
AS		 2251 mutex_lock(&priv->state_lock);
2252 err = mlx5e_close_locked(netdev);
2253 mutex_unlock(&priv->state_lock);
2254
2255 return err;
2256}
2257
2258static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2259 struct mlx5e_rq *rq,
2260 struct mlx5e_rq_param *param)
2261{
2262 struct mlx5_core_dev *mdev = priv->mdev;
2263 void *rqc = param->rqc;
2264 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2265 int err;
2266
2267 param->wq.db_numa_node = param->wq.buf_numa_node;
2268
2269 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2270 &rq->wq_ctrl);
2271 if (err)
2272 return err;
2273
2274 rq->priv = priv;
2275
2276 return 0;
2277}
2278
2279static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2280 struct mlx5e_cq *cq,
2281 struct mlx5e_cq_param *param)
2282{
2283 struct mlx5_core_dev *mdev = priv->mdev;
2284 struct mlx5_core_cq *mcq = &cq->mcq;
2285 int eqn_not_used;
0b6e26ce 2286 unsigned int irqn;
40ab6a6e
AS		 2287 int err;
2288
2289 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2290 &cq->wq_ctrl);
2291 if (err)
2292 return err;
2293
2294 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2295
2296 mcq->cqe_sz = 64;
2297 mcq->set_ci_db = cq->wq_ctrl.db.db;
2298 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2299 *mcq->set_ci_db = 0;
2300 *mcq->arm_db = 0;
2301 mcq->vector = param->eq_ix;
2302 mcq->comp = mlx5e_completion_event;
2303 mcq->event = mlx5e_cq_error_event;
2304 mcq->irqn = irqn;
b50d292b 2305 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 2306
2307 cq->priv = priv;
2308
2309 return 0;
2310}
2311
2312static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2313{
2314 struct mlx5e_cq_param cq_param;
2315 struct mlx5e_rq_param rq_param;
2316 struct mlx5e_rq *rq = &priv->drop_rq;
2317 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2318 int err;
2319
2320 memset(&cq_param, 0, sizeof(cq_param));
2321 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2322 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2323
2324 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2325 if (err)
2326 return err;
2327
2328 err = mlx5e_enable_cq(cq, &cq_param);
2329 if (err)
2330 goto err_destroy_cq;
2331
2332 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2333 if (err)
2334 goto err_disable_cq;
2335
2336 err = mlx5e_enable_rq(rq, &rq_param);
2337 if (err)
2338 goto err_destroy_rq;
2339
2340 return 0;
2341
2342err_destroy_rq:
2343 mlx5e_destroy_rq(&priv->drop_rq);
2344
2345err_disable_cq:
2346 mlx5e_disable_cq(&priv->drop_rq.cq);
2347
2348err_destroy_cq:
2349 mlx5e_destroy_cq(&priv->drop_rq.cq);
2350
2351 return err;
2352}
2353
2354static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2355{
2356 mlx5e_disable_rq(&priv->drop_rq);
2357 mlx5e_destroy_rq(&priv->drop_rq);
2358 mlx5e_disable_cq(&priv->drop_rq.cq);
2359 mlx5e_destroy_cq(&priv->drop_rq.cq);
2360}
2361
2362static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2363{
2364 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2365 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2366 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2367
08fb1dac 2368 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2369 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2370
2371 if (mlx5_lag_is_lacp_owner(mdev))
2372 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2373
40ab6a6e
AS		 2374 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2375}
2376
2377static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2378{
2379 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2380}
2381
cb67b832 2382int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2383{
2384 int err;
2385 int tc;
2386
6bfd390b 2387 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2388 err = mlx5e_create_tis(priv, tc);
2389 if (err)
2390 goto err_close_tises;
2391 }
2392
2393 return 0;
2394
2395err_close_tises:
2396 for (tc--; tc >= 0; tc--)
2397 mlx5e_destroy_tis(priv, tc);
2398
2399 return err;
2400}
2401
cb67b832 2402void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2403{
2404 int tc;
2405
6bfd390b 2406 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2407 mlx5e_destroy_tis(priv, tc);
2408}
2409
1da36696
TT		 2410static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2411 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2412{
2413 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2414
b50d292b 2415 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2416
5a6f8aef
AS		 2417#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2418 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2419
5a6f8aef
AS		 2420#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2421 MLX5_HASH_FIELD_SEL_DST_IP |\
2422 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2423 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2424
a741749f
AS		 2425#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2426 MLX5_HASH_FIELD_SEL_DST_IP |\
2427 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2428
5c50368f 2429 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2430
4cbeaff5 2431 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2432 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2433 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2434
2435 switch (tt) {
2436 case MLX5E_TT_IPV4_TCP:
2437 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2438 MLX5_L3_PROT_TYPE_IPV4);
2439 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2440 MLX5_L4_PROT_TYPE_TCP);
2441 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2442 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2443 break;
2444
2445 case MLX5E_TT_IPV6_TCP:
2446 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2447 MLX5_L3_PROT_TYPE_IPV6);
2448 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2449 MLX5_L4_PROT_TYPE_TCP);
2450 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2451 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2452 break;
2453
2454 case MLX5E_TT_IPV4_UDP:
2455 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2456 MLX5_L3_PROT_TYPE_IPV4);
2457 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2458 MLX5_L4_PROT_TYPE_UDP);
2459 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2460 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2461 break;
2462
2463 case MLX5E_TT_IPV6_UDP:
2464 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2465 MLX5_L3_PROT_TYPE_IPV6);
2466 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2467 MLX5_L4_PROT_TYPE_UDP);
2468 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2469 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2470 break;
2471
a741749f
AS		 2472 case MLX5E_TT_IPV4_IPSEC_AH:
2473 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2474 MLX5_L3_PROT_TYPE_IPV4);
2475 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2476 MLX5_HASH_IP_IPSEC_SPI);
2477 break;
2478
2479 case MLX5E_TT_IPV6_IPSEC_AH:
2480 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2481 MLX5_L3_PROT_TYPE_IPV6);
2482 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2483 MLX5_HASH_IP_IPSEC_SPI);
2484 break;
2485
2486 case MLX5E_TT_IPV4_IPSEC_ESP:
2487 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2488 MLX5_L3_PROT_TYPE_IPV4);
2489 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2490 MLX5_HASH_IP_IPSEC_SPI);
2491 break;
2492
2493 case MLX5E_TT_IPV6_IPSEC_ESP:
2494 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2495 MLX5_L3_PROT_TYPE_IPV6);
2496 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2497 MLX5_HASH_IP_IPSEC_SPI);
2498 break;
2499
f62b8bb8
AV		 2500 case MLX5E_TT_IPV4:
2501 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2502 MLX5_L3_PROT_TYPE_IPV4);
2503 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2504 MLX5_HASH_IP);
2505 break;
2506
2507 case MLX5E_TT_IPV6:
2508 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2509 MLX5_L3_PROT_TYPE_IPV6);
2510 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2511 MLX5_HASH_IP);
2512 break;
1da36696
TT		 2513 default:
2514 WARN_ONCE(true,
2515 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2516 }
2517}
2518
1da36696
TT		 2519static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2520 u32 rqtn)
f62b8bb8 2521{
b50d292b 2522 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2523
2524 mlx5e_build_tir_ctx_lro(tirc, priv);
2525
2526 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2527 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2528 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2529}
2530
6bfd390b 2531static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2532{
724b2aa1 2533 struct mlx5e_tir *tir;
f62b8bb8
AV		 2534 void *tirc;
2535 int inlen;
2536 int err;
1da36696 2537 u32 *in;
1da36696 2538 int tt;
f62b8bb8
AV		 2539
2540 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2541 in = mlx5_vzalloc(inlen);
2542 if (!in)
2543 return -ENOMEM;
2544
1da36696
TT		 2545 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2546 memset(in, 0, inlen);
724b2aa1 2547 tir = &priv->indir_tir[tt];
1da36696
TT		 2548 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2549 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2550 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2551 if (err)
40ab6a6e 2552 goto err_destroy_tirs;
f62b8bb8
AV		 2553 }
2554
6bfd390b
HHZ		 2555 kvfree(in);
2556
2557 return 0;
2558
2559err_destroy_tirs:
2560 for (tt--; tt >= 0; tt--)
2561 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2562
2563 kvfree(in);
2564
2565 return err;
2566}
2567
cb67b832 2568int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2569{
2570 int nch = priv->profile->max_nch(priv->mdev);
2571 struct mlx5e_tir *tir;
2572 void *tirc;
2573 int inlen;
2574 int err;
2575 u32 *in;
2576 int ix;
2577
2578 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2579 in = mlx5_vzalloc(inlen);
2580 if (!in)
2581 return -ENOMEM;
2582
1da36696
TT		 2583 for (ix = 0; ix < nch; ix++) {
2584 memset(in, 0, inlen);
724b2aa1 2585 tir = &priv->direct_tir[ix];
1da36696
TT		 2586 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2587 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2588 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2589 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2590 if (err)
2591 goto err_destroy_ch_tirs;
2592 }
2593
2594 kvfree(in);
2595
f62b8bb8
AV		 2596 return 0;
2597
1da36696
TT		 2598err_destroy_ch_tirs:
2599 for (ix--; ix >= 0; ix--)
724b2aa1 2600 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2601
1da36696 2602 kvfree(in);
f62b8bb8
AV		 2603
2604 return err;
2605}
2606
6bfd390b 2607static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2608{
2609 int i;
2610
1da36696 2611 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2612 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2613}
2614
cb67b832 2615void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2616{
2617 int nch = priv->profile->max_nch(priv->mdev);
2618 int i;
2619
2620 for (i = 0; i < nch; i++)
2621 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2622}
2623
36350114
GP		 2624int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2625{
2626 int err = 0;
2627 int i;
2628
2629 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2630 return 0;
2631
2632 for (i = 0; i < priv->params.num_channels; i++) {
2633 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2634 if (err)
2635 return err;
2636 }
2637
2638 return 0;
2639}
2640
08fb1dac
SM		 2641static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2642{
2643 struct mlx5e_priv *priv = netdev_priv(netdev);
2644 bool was_opened;
2645 int err = 0;
2646
2647 if (tc && tc != MLX5E_MAX_NUM_TC)
2648 return -EINVAL;
2649
2650 mutex_lock(&priv->state_lock);
2651
2652 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2653 if (was_opened)
2654 mlx5e_close_locked(priv->netdev);
2655
2656 priv->params.num_tc = tc ? tc : 1;
2657
2658 if (was_opened)
2659 err = mlx5e_open_locked(priv->netdev);
2660
2661 mutex_unlock(&priv->state_lock);
2662
2663 return err;
2664}
2665
2666static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2667 __be16 proto, struct tc_to_netdev *tc)
2668{
e8f887ac
AV		 2669 struct mlx5e_priv *priv = netdev_priv(dev);
2670
2671 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2672 goto mqprio;
2673
2674 switch (tc->type) {
e3a2b7ed
AV		 2675 case TC_SETUP_CLSFLOWER:
2676 switch (tc->cls_flower->command) {
2677 case TC_CLSFLOWER_REPLACE:
2678 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2679 case TC_CLSFLOWER_DESTROY:
2680 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2681 case TC_CLSFLOWER_STATS:
2682 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2683 }
e8f887ac
AV		 2684 default:
2685 return -EOPNOTSUPP;
2686 }
2687
2688mqprio:
67ba422e 2689 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2690 return -EINVAL;
2691
2692 return mlx5e_setup_tc(dev, tc->tc);
2693}
2694
370bad0f 2695static struct rtnl_link_stats64 *
f62b8bb8
AV		 2696mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2697{
2698 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2699 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2700 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2701 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2702
370bad0f
OG		 2703 if (mlx5e_is_uplink_rep(priv)) {
2704 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2705 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2706 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2707 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2708 } else {
2709 stats->rx_packets = sstats->rx_packets;
2710 stats->rx_bytes = sstats->rx_bytes;
2711 stats->tx_packets = sstats->tx_packets;
2712 stats->tx_bytes = sstats->tx_bytes;
2713 stats->tx_dropped = sstats->tx_queue_dropped;
2714 }
269e6b3a
GP		 2715
2716 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2717
2718 stats->rx_length_errors =
9218b44d
GP		 2719 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2720 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2721 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2722 stats->rx_crc_errors =
9218b44d
GP		 2723 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2724 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2725 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2726 stats->tx_carrier_errors =
9218b44d 2727 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2728 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2729 stats->rx_frame_errors;
2730 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2731
2732 /* vport multicast also counts packets that are dropped due to steering
2733 * or rx out of buffer
2734 */
9218b44d
GP		 2735 stats->multicast =
2736 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2737
2738 return stats;
2739}
2740
2741static void mlx5e_set_rx_mode(struct net_device *dev)
2742{
2743 struct mlx5e_priv *priv = netdev_priv(dev);
2744
7bb29755 2745 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2746}
2747
2748static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2749{
2750 struct mlx5e_priv *priv = netdev_priv(netdev);
2751 struct sockaddr *saddr = addr;
2752
2753 if (!is_valid_ether_addr(saddr->sa_data))
2754 return -EADDRNOTAVAIL;
2755
2756 netif_addr_lock_bh(netdev);
2757 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2758 netif_addr_unlock_bh(netdev);
2759
7bb29755 2760 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2761
2762 return 0;
2763}
2764
0e405443
GP		 2765#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2766 do { \
2767 if (enable) \
2768 netdev->features |= feature; \
2769 else \
2770 netdev->features &= ~feature; \
2771 } while (0)
2772
2773typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2774
2775static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2776{
2777 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2778 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2779 int err;
f62b8bb8
AV		 2780
2781 mutex_lock(&priv->state_lock);
f62b8bb8 2782
0e405443
GP		 2783 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2784 mlx5e_close_locked(priv->netdev);
98e81b0a 2785
0e405443
GP		 2786 priv->params.lro_en = enable;
2787 err = mlx5e_modify_tirs_lro(priv);
2788 if (err) {
2789 netdev_err(netdev, "lro modify failed, %d\n", err);
2790 priv->params.lro_en = !enable;
98e81b0a 2791 }
f62b8bb8 2792
0e405443
GP		 2793 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2794 mlx5e_open_locked(priv->netdev);
2795
9b37b07f
AS		 2796 mutex_unlock(&priv->state_lock);
2797
0e405443
GP		 2798 return err;
2799}
2800
2801static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2802{
2803 struct mlx5e_priv *priv = netdev_priv(netdev);
2804
2805 if (enable)
2806 mlx5e_enable_vlan_filter(priv);
2807 else
2808 mlx5e_disable_vlan_filter(priv);
2809
2810 return 0;
2811}
2812
2813static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2814{
2815 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2816
0e405443 2817 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2818 netdev_err(netdev,
2819 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2820 return -EINVAL;
2821 }
2822
0e405443
GP		 2823 return 0;
2824}
2825
94cb1ebb
EBE		 2826static int set_feature_rx_all(struct net_device *netdev, bool enable)
2827{
2828 struct mlx5e_priv *priv = netdev_priv(netdev);
2829 struct mlx5_core_dev *mdev = priv->mdev;
2830
2831 return mlx5_set_port_fcs(mdev, !enable);
2832}
2833
36350114
GP		 2834static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2835{
2836 struct mlx5e_priv *priv = netdev_priv(netdev);
2837 int err;
2838
2839 mutex_lock(&priv->state_lock);
2840
2841 priv->params.vlan_strip_disable = !enable;
2842 err = mlx5e_modify_rqs_vsd(priv, !enable);
2843 if (err)
2844 priv->params.vlan_strip_disable = enable;
2845
2846 mutex_unlock(&priv->state_lock);
2847
2848 return err;
2849}
2850
45bf454a
MG		 2851#ifdef CONFIG_RFS_ACCEL
2852static int set_feature_arfs(struct net_device *netdev, bool enable)
2853{
2854 struct mlx5e_priv *priv = netdev_priv(netdev);
2855 int err;
2856
2857 if (enable)
2858 err = mlx5e_arfs_enable(priv);
2859 else
2860 err = mlx5e_arfs_disable(priv);
2861
2862 return err;
2863}
2864#endif
2865
0e405443
GP		 2866static int mlx5e_handle_feature(struct net_device *netdev,
2867 netdev_features_t wanted_features,
2868 netdev_features_t feature,
2869 mlx5e_feature_handler feature_handler)
2870{
2871 netdev_features_t changes = wanted_features ^ netdev->features;
2872 bool enable = !!(wanted_features & feature);
2873 int err;
2874
2875 if (!(changes & feature))
2876 return 0;
2877
2878 err = feature_handler(netdev, enable);
2879 if (err) {
2880 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2881 enable ? "Enable" : "Disable", feature, err);
2882 return err;
2883 }
2884
2885 MLX5E_SET_FEATURE(netdev, feature, enable);
2886 return 0;
2887}
2888
2889static int mlx5e_set_features(struct net_device *netdev,
2890 netdev_features_t features)
2891{
2892 int err;
2893
2894 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2895 set_feature_lro);
2896 err |= mlx5e_handle_feature(netdev, features,
2897 NETIF_F_HW_VLAN_CTAG_FILTER,
2898 set_feature_vlan_filter);
2899 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2900 set_feature_tc_num_filters);
94cb1ebb
EBE		 2901 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2902 set_feature_rx_all);
36350114
GP		 2903 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2904 set_feature_rx_vlan);
45bf454a
MG		 2905#ifdef CONFIG_RFS_ACCEL
2906 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2907 set_feature_arfs);
2908#endif
0e405443
GP		 2909
2910 return err ? -EINVAL : 0;
f62b8bb8
AV		 2911}
2912
2913static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2914{
2915 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2916 bool was_opened;
98e81b0a 2917 int err = 0;
506753b0 2918 bool reset;
f62b8bb8 2919
f62b8bb8 2920 mutex_lock(&priv->state_lock);
98e81b0a 2921
506753b0
TT		 2922 reset = !priv->params.lro_en &&
2923 (priv->params.rq_wq_type !=
2924 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2925
98e81b0a 2926 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2927 if (was_opened && reset)
98e81b0a
AS		 2928 mlx5e_close_locked(netdev);
2929
f62b8bb8 2930 netdev->mtu = new_mtu;
13f9bba7 2931 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2932
506753b0 2933 if (was_opened && reset)
98e81b0a
AS		 2934 err = mlx5e_open_locked(netdev);
2935
f62b8bb8
AV		 2936 mutex_unlock(&priv->state_lock);
2937
2938 return err;
2939}
2940
ef9814de
EBE		 2941static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2942{
2943 switch (cmd) {
2944 case SIOCSHWTSTAMP:
2945 return mlx5e_hwstamp_set(dev, ifr);
2946 case SIOCGHWTSTAMP:
2947 return mlx5e_hwstamp_get(dev, ifr);
2948 default:
2949 return -EOPNOTSUPP;
2950 }
2951}
2952
66e49ded
SM		 2953static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2954{
2955 struct mlx5e_priv *priv = netdev_priv(dev);
2956 struct mlx5_core_dev *mdev = priv->mdev;
2957
2958 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2959}
2960
79aab093
MS		 2961static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2962 __be16 vlan_proto)
66e49ded
SM		 2963{
2964 struct mlx5e_priv *priv = netdev_priv(dev);
2965 struct mlx5_core_dev *mdev = priv->mdev;
2966
79aab093
MS		 2967 if (vlan_proto != htons(ETH_P_8021Q))
2968 return -EPROTONOSUPPORT;
2969
66e49ded
SM		 2970 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2971 vlan, qos);
2972}
2973
f942380c
MHY		 2974static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2975{
2976 struct mlx5e_priv *priv = netdev_priv(dev);
2977 struct mlx5_core_dev *mdev = priv->mdev;
2978
2979 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2980}
2981
1edc57e2
MHY		 2982static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2983{
2984 struct mlx5e_priv *priv = netdev_priv(dev);
2985 struct mlx5_core_dev *mdev = priv->mdev;
2986
2987 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2988}
bd77bf1c
MHY		 2989
2990static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2991 int max_tx_rate)
2992{
2993 struct mlx5e_priv *priv = netdev_priv(dev);
2994 struct mlx5_core_dev *mdev = priv->mdev;
2995
2996 if (min_tx_rate)
2997 return -EOPNOTSUPP;
2998
2999 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3000 max_tx_rate);
3001}
3002
66e49ded
SM		 3003static int mlx5_vport_link2ifla(u8 esw_link)
3004{
3005 switch (esw_link) {
3006 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3007 return IFLA_VF_LINK_STATE_DISABLE;
3008 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3009 return IFLA_VF_LINK_STATE_ENABLE;
3010 }
3011 return IFLA_VF_LINK_STATE_AUTO;
3012}
3013
3014static int mlx5_ifla_link2vport(u8 ifla_link)
3015{
3016 switch (ifla_link) {
3017 case IFLA_VF_LINK_STATE_DISABLE:
3018 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3019 case IFLA_VF_LINK_STATE_ENABLE:
3020 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3021 }
3022 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3023}
3024
3025static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3026 int link_state)
3027{
3028 struct mlx5e_priv *priv = netdev_priv(dev);
3029 struct mlx5_core_dev *mdev = priv->mdev;
3030
3031 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3032 mlx5_ifla_link2vport(link_state));
3033}
3034
3035static int mlx5e_get_vf_config(struct net_device *dev,
3036 int vf, struct ifla_vf_info *ivi)
3037{
3038 struct mlx5e_priv *priv = netdev_priv(dev);
3039 struct mlx5_core_dev *mdev = priv->mdev;
3040 int err;
3041
3042 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3043 if (err)
3044 return err;
3045 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3046 return 0;
3047}
3048
3049static int mlx5e_get_vf_stats(struct net_device *dev,
3050 int vf, struct ifla_vf_stats *vf_stats)
3051{
3052 struct mlx5e_priv *priv = netdev_priv(dev);
3053 struct mlx5_core_dev *mdev = priv->mdev;
3054
3055 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3056 vf_stats);
3057}
3058
4a25730e
HHZ		 3059void mlx5e_add_vxlan_port(struct net_device *netdev,
3060 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3061{
3062 struct mlx5e_priv *priv = netdev_priv(netdev);
3063
974c3f30
AD		 3064 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3065 return;
3066
b3f63c3d
MF		 3067 if (!mlx5e_vxlan_allowed(priv->mdev))
3068 return;
3069
974c3f30 3070 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3071}
3072
4a25730e
HHZ		 3073void mlx5e_del_vxlan_port(struct net_device *netdev,
3074 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3075{
3076 struct mlx5e_priv *priv = netdev_priv(netdev);
3077
974c3f30
AD		 3078 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3079 return;
3080
b3f63c3d
MF		 3081 if (!mlx5e_vxlan_allowed(priv->mdev))
3082 return;
3083
974c3f30 3084 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3085}
3086
3087static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3088 struct sk_buff *skb,
3089 netdev_features_t features)
3090{
3091 struct udphdr *udph;
3092 u16 proto;
3093 u16 port = 0;
3094
3095 switch (vlan_get_protocol(skb)) {
3096 case htons(ETH_P_IP):
3097 proto = ip_hdr(skb)->protocol;
3098 break;
3099 case htons(ETH_P_IPV6):
3100 proto = ipv6_hdr(skb)->nexthdr;
3101 break;
3102 default:
3103 goto out;
3104 }
3105
3106 if (proto == IPPROTO_UDP) {
3107 udph = udp_hdr(skb);
3108 port = be16_to_cpu(udph->dest);
3109 }
3110
3111 /* Verify if UDP port is being offloaded by HW */
3112 if (port && mlx5e_vxlan_lookup_port(priv, port))
3113 return features;
3114
3115out:
3116 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3117 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3118}
3119
3120static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3121 struct net_device *netdev,
3122 netdev_features_t features)
3123{
3124 struct mlx5e_priv *priv = netdev_priv(netdev);
3125
3126 features = vlan_features_check(skb, features);
3127 features = vxlan_features_check(skb, features);
3128
3129 /* Validate if the tunneled packet is being offloaded by HW */
3130 if (skb->encapsulation &&
3131 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3132 return mlx5e_vxlan_features_check(priv, skb, features);
3133
3134 return features;
3135}
3136
3947ca18
DJ		 3137static void mlx5e_tx_timeout(struct net_device *dev)
3138{
3139 struct mlx5e_priv *priv = netdev_priv(dev);
3140 bool sched_work = false;
3141 int i;
3142
3143 netdev_err(dev, "TX timeout detected\n");
3144
3145 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3146 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3147
2c1ccc99 3148 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3149 continue;
3150 sched_work = true;
6e8dd6d6 3151 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3947ca18
DJ		 3152 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3153 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3154 }
3155
3156 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3157 schedule_work(&priv->tx_timeout_work);
3158}
3159
86994156
RS		 3160static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3161{
3162 struct mlx5e_priv *priv = netdev_priv(netdev);
3163 struct bpf_prog *old_prog;
3164 int err = 0;
3165 bool reset, was_opened;
3166 int i;
3167
3168 mutex_lock(&priv->state_lock);
3169
3170 if ((netdev->features & NETIF_F_LRO) && prog) {
3171 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3172 err = -EINVAL;
3173 goto unlock;
3174 }
3175
3176 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3177 /* no need for full reset when exchanging programs */
3178 reset = (!priv->xdp_prog || !prog);
3179
3180 if (was_opened && reset)
3181 mlx5e_close_locked(netdev);
c54c0629
DB		 3182 if (was_opened && !reset) {
3183 /* num_channels is invariant here, so we can take the
3184 * batched reference right upfront.
3185 */
3186 prog = bpf_prog_add(prog, priv->params.num_channels);
3187 if (IS_ERR(prog)) {
3188 err = PTR_ERR(prog);
3189 goto unlock;
3190 }
3191 }
86994156 3192
c54c0629
DB		 3193 /* exchange programs, extra prog reference we got from caller
3194 * as long as we don't fail from this point onwards.
3195 */
86994156 3196 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3197 if (old_prog)
3198 bpf_prog_put(old_prog);
3199
3200 if (reset) /* change RQ type according to priv->xdp_prog */
3201 mlx5e_set_rq_priv_params(priv);
3202
3203 if (was_opened && reset)
3204 mlx5e_open_locked(netdev);
3205
3206 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3207 goto unlock;
3208
3209 /* exchanging programs w/o reset, we update ref counts on behalf
3210 * of the channels RQs here.
3211 */
86994156
RS		 3212 for (i = 0; i < priv->params.num_channels; i++) {
3213 struct mlx5e_channel *c = priv->channel[i];
3214
3215 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3216 napi_synchronize(&c->napi);
3217 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3218
3219 old_prog = xchg(&c->rq.xdp_prog, prog);
3220
3221 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3222 /* napi_schedule in case we have missed anything */
3223 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3224 napi_schedule(&c->napi);
3225
3226 if (old_prog)
3227 bpf_prog_put(old_prog);
3228 }
3229
3230unlock:
3231 mutex_unlock(&priv->state_lock);
3232 return err;
3233}
3234
3235static bool mlx5e_xdp_attached(struct net_device *dev)
3236{
3237 struct mlx5e_priv *priv = netdev_priv(dev);
3238
3239 return !!priv->xdp_prog;
3240}
3241
3242static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3243{
3244 switch (xdp->command) {
3245 case XDP_SETUP_PROG:
3246 return mlx5e_xdp_set(dev, xdp->prog);
3247 case XDP_QUERY_PROG:
3248 xdp->prog_attached = mlx5e_xdp_attached(dev);
3249 return 0;
3250 default:
3251 return -EINVAL;
3252 }
3253}
3254
80378384
CO		 3255#ifdef CONFIG_NET_POLL_CONTROLLER
3256/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3257 * reenabling interrupts.
3258 */
3259static void mlx5e_netpoll(struct net_device *dev)
3260{
3261 struct mlx5e_priv *priv = netdev_priv(dev);
3262 int i;
3263
3264 for (i = 0; i < priv->params.num_channels; i++)
3265 napi_schedule(&priv->channel[i]->napi);
3266}
3267#endif
3268
b0eed40e 3269static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3270 .ndo_open = mlx5e_open,
3271 .ndo_stop = mlx5e_close,
3272 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3273 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3274 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3275 .ndo_get_stats64 = mlx5e_get_stats,
3276 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3277 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3278 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3279 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3280 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3281 .ndo_change_mtu = mlx5e_change_mtu,
3282 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3283 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3284#ifdef CONFIG_RFS_ACCEL
3285 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3286#endif
3947ca18 3287 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3288 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3289#ifdef CONFIG_NET_POLL_CONTROLLER
3290 .ndo_poll_controller = mlx5e_netpoll,
3291#endif
b0eed40e
SM		 3292};
3293
3294static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3295 .ndo_open = mlx5e_open,
3296 .ndo_stop = mlx5e_close,
3297 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3298 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3299 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3300 .ndo_get_stats64 = mlx5e_get_stats,
3301 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3302 .ndo_set_mac_address = mlx5e_set_mac,
3303 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3304 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3305 .ndo_set_features = mlx5e_set_features,
3306 .ndo_change_mtu = mlx5e_change_mtu,
3307 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3308 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3309 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3310 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3311 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3312#ifdef CONFIG_RFS_ACCEL
3313 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3314#endif
b0eed40e
SM		 3315 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3316 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3317 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3318 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3319 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3320 .ndo_get_vf_config = mlx5e_get_vf_config,
3321 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3322 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3323 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3324 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3325#ifdef CONFIG_NET_POLL_CONTROLLER
3326 .ndo_poll_controller = mlx5e_netpoll,
3327#endif
370bad0f
OG		 3328 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3329 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3330};
3331
3332static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3333{
3334 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3335 return -ENOTSUPP;
3336 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3337 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3338 !MLX5_CAP_ETH(mdev, csum_cap) ||
3339 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3340 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3341 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3342 MLX5_CAP_FLOWTABLE(mdev,
3343 flow_table_properties_nic_receive.max_ft_level)
3344 < 3) {
f62b8bb8
AV		 3345 mlx5_core_warn(mdev,
3346 "Not creating net device, some required device capabilities are missing\n");
3347 return -ENOTSUPP;
3348 }
66189961
TT		 3349 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3350 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3351 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3352 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3353
f62b8bb8
AV		 3354 return 0;
3355}
3356
58d52291
AS		 3357u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3358{
3359 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3360
3361 return bf_buf_size -
3362 sizeof(struct mlx5e_tx_wqe) +
3363 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3364}
3365
d8c9660d
TT		 3366void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3367 u32 *indirection_rqt, int len,
85082dba
TT		 3368 int num_channels)
3369{
d8c9660d
TT		 3370 int node = mdev->priv.numa_node;
3371 int node_num_of_cores;
85082dba
TT		 3372 int i;
3373
d8c9660d
TT		 3374 if (node == -1)
3375 node = first_online_node;
3376
3377 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3378
3379 if (node_num_of_cores)
3380 num_channels = min_t(int, num_channels, node_num_of_cores);
3381
85082dba
TT		 3382 for (i = 0; i < len; i++)
3383 indirection_rqt[i] = i % num_channels;
3384}
3385
b797a684
SM		 3386static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3387{
3388 enum pcie_link_width width;
3389 enum pci_bus_speed speed;
3390 int err = 0;
3391
3392 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3393 if (err)
3394 return err;
3395
3396 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3397 return -EINVAL;
3398
3399 switch (speed) {
3400 case PCIE_SPEED_2_5GT:
3401 *pci_bw = 2500 * width;
3402 break;
3403 case PCIE_SPEED_5_0GT:
3404 *pci_bw = 5000 * width;
3405 break;
3406 case PCIE_SPEED_8_0GT:
3407 *pci_bw = 8000 * width;
3408 break;
3409 default:
3410 return -EINVAL;
3411 }
3412
3413 return 0;
3414}
3415
3416static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3417{
3418 return (link_speed && pci_bw &&
3419 (pci_bw < 40000) && (pci_bw < link_speed));
3420}
3421
9908aa29
TT		 3422void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3423{
3424 params->rx_cq_period_mode = cq_period_mode;
3425
3426 params->rx_cq_moderation.pkts =
3427 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3428 params->rx_cq_moderation.usec =
3429 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3430
3431 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3432 params->rx_cq_moderation.usec =
3433 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3434}
3435
cff92d7c
HHZ		 3436static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3437 u8 *min_inline_mode)
3438{
3439 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
34e4e990 3440 case MLX5_CAP_INLINE_MODE_L2:
cff92d7c
HHZ		 3441 *min_inline_mode = MLX5_INLINE_MODE_L2;
3442 break;
34e4e990
RD		 3443 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3444 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
cff92d7c 3445 break;
34e4e990 3446 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
cff92d7c
HHZ		 3447 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3448 break;
3449 }
3450}
3451
2b029556
SM		 3452u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3453{
3454 int i;
3455
3456 /* The supported periods are organized in ascending order */
3457 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3458 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3459 break;
3460
3461 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3462}
3463
6bfd390b
HHZ		 3464static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3465 struct net_device *netdev,
127ea380
HHZ		 3466 const struct mlx5e_profile *profile,
3467 void *ppriv)
f62b8bb8
AV		 3468{
3469 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3470 u32 link_speed = 0;
3471 u32 pci_bw = 0;
cb3c7fd4
GR		 3472 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3473 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3474 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3475
2fc4bfb7
SM		 3476 priv->mdev = mdev;
3477 priv->netdev = netdev;
3478 priv->params.num_channels = profile->max_nch(mdev);
3479 priv->profile = profile;
3480 priv->ppriv = ppriv;
3481
2b029556
SM		 3482 priv->params.lro_timeout =
3483 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3484
2fc4bfb7 3485 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3486
b797a684 3487 /* set CQE compression */
9bcc8606 3488 priv->params.rx_cqe_compress_def = false;
b797a684
SM		 3489 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3490 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3491 mlx5e_get_max_linkspeed(mdev, &link_speed);
3492 mlx5e_get_pci_bw(mdev, &pci_bw);
3493 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3494 link_speed, pci_bw);
9bcc8606 3495 priv->params.rx_cqe_compress_def =
b797a684
SM		 3496 cqe_compress_heuristic(link_speed, pci_bw);
3497 }
b797a684 3498
2fc4bfb7
SM		 3499 mlx5e_set_rq_priv_params(priv);
3500 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3501 priv->params.lro_en = true;
9908aa29 3502
cb3c7fd4
GR		 3503 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3504 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3505
3506 priv->params.tx_cq_moderation.usec =
f62b8bb8 3507 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3508 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3509 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3510 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3511 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3512 priv->params.num_tc = 1;
2be6967c 3513 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3514
57afead5
AS		 3515 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3516 sizeof(priv->params.toeplitz_hash_key));
3517
d8c9660d 3518 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3519 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3520
e4b85508
SM		 3521 priv->params.lro_wqe_sz =
3522 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3523 /* Extra room needed for build_skb */
3524 MLX5_RX_HEADROOM -
3525 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3526
9908aa29 3527 /* Initialize pflags */
59ece1c9
SD		 3528 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3529 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9bcc8606 3530 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
9908aa29 3531
f62b8bb8
AV		 3532 mutex_init(&priv->state_lock);
3533
3534 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3535 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3536 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3537 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3538}
3539
3540static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3541{
3542 struct mlx5e_priv *priv = netdev_priv(netdev);
3543
e1d7d349 3544 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3545 if (is_zero_ether_addr(netdev->dev_addr) &&
3546 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3547 eth_hw_addr_random(netdev);
3548 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3549 }
f62b8bb8
AV		 3550}
3551
cb67b832
HHZ		 3552static const struct switchdev_ops mlx5e_switchdev_ops = {
3553 .switchdev_port_attr_get = mlx5e_attr_get,
3554};
3555
6bfd390b 3556static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3557{
3558 struct mlx5e_priv *priv = netdev_priv(netdev);
3559 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3560 bool fcs_supported;
3561 bool fcs_enabled;
f62b8bb8
AV		 3562
3563 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3564
08fb1dac 3565 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3566 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3567#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3568 if (MLX5_CAP_GEN(mdev, qos))
3569 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3570#endif
3571 } else {
b0eed40e 3572 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3573 }
66e49ded 3574
f62b8bb8
AV		 3575 netdev->watchdog_timeo = 15 * HZ;
3576
3577 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3578
12be4b21 3579 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3580 netdev->vlan_features |= NETIF_F_IP_CSUM;
3581 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3582 netdev->vlan_features |= NETIF_F_GRO;
3583 netdev->vlan_features |= NETIF_F_TSO;
3584 netdev->vlan_features |= NETIF_F_TSO6;
3585 netdev->vlan_features |= NETIF_F_RXCSUM;
3586 netdev->vlan_features |= NETIF_F_RXHASH;
3587
3588 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3589 netdev->vlan_features |= NETIF_F_LRO;
3590
3591 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3592 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3593 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3594 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3595
b3f63c3d 3596 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3597 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3598 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3599 NETIF_F_GSO_PARTIAL;
b3f63c3d 3600 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3601 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3602 netdev->hw_enc_features |= NETIF_F_TSO;
3603 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3604 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3605 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3606 NETIF_F_GSO_PARTIAL;
3607 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3608 }
3609
94cb1ebb
EBE		 3610 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3611
3612 if (fcs_supported)
3613 netdev->hw_features |= NETIF_F_RXALL;
3614
f62b8bb8
AV		 3615 netdev->features = netdev->hw_features;
3616 if (!priv->params.lro_en)
3617 netdev->features &= ~NETIF_F_LRO;
3618
94cb1ebb
EBE		 3619 if (fcs_enabled)
3620 netdev->features &= ~NETIF_F_RXALL;
3621
e8f887ac
AV		 3622#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3623 if (FT_CAP(flow_modify_en) &&
3624 FT_CAP(modify_root) &&
3625 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3626 FT_CAP(flow_table_modify)) {
3627 netdev->hw_features |= NETIF_F_HW_TC;
3628#ifdef CONFIG_RFS_ACCEL
3629 netdev->hw_features |= NETIF_F_NTUPLE;
3630#endif
3631 }
e8f887ac 3632
f62b8bb8
AV		 3633 netdev->features |= NETIF_F_HIGHDMA;
3634
3635 netdev->priv_flags |= IFF_UNICAST_FLT;
3636
3637 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3638
3639#ifdef CONFIG_NET_SWITCHDEV
3640 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3641 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3642#endif
f62b8bb8
AV		 3643}
3644
593cf338
RS		 3645static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3646{
3647 struct mlx5_core_dev *mdev = priv->mdev;
3648 int err;
3649
3650 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3651 if (err) {
3652 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3653 priv->q_counter = 0;
3654 }
3655}
3656
3657static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3658{
3659 if (!priv->q_counter)
3660 return;
3661
3662 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3663}
3664
6bfd390b
HHZ		 3665static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3666 struct net_device *netdev,
127ea380
HHZ		 3667 const struct mlx5e_profile *profile,
3668 void *ppriv)
6bfd390b
HHZ		 3669{
3670 struct mlx5e_priv *priv = netdev_priv(netdev);
3671
127ea380 3672 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3673 mlx5e_build_nic_netdev(netdev);
3674 mlx5e_vxlan_init(priv);
3675}
3676
3677static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3678{
127ea380
HHZ		 3679 struct mlx5_core_dev *mdev = priv->mdev;
3680 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3681
6bfd390b 3682 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3683
3684 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3685 mlx5_eswitch_unregister_vport_rep(esw, 0);
a055c19b
DB		 3686
3687 if (priv->xdp_prog)
3688 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3689}
3690
3691static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3692{
3693 struct mlx5_core_dev *mdev = priv->mdev;
3694 int err;
3695 int i;
3696
3697 err = mlx5e_create_indirect_rqts(priv);
3698 if (err) {
3699 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3700 return err;
3701 }
3702
3703 err = mlx5e_create_direct_rqts(priv);
3704 if (err) {
3705 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3706 goto err_destroy_indirect_rqts;
3707 }
3708
3709 err = mlx5e_create_indirect_tirs(priv);
3710 if (err) {
3711 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3712 goto err_destroy_direct_rqts;
3713 }
3714
3715 err = mlx5e_create_direct_tirs(priv);
3716 if (err) {
3717 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3718 goto err_destroy_indirect_tirs;
3719 }
3720
3721 err = mlx5e_create_flow_steering(priv);
3722 if (err) {
3723 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3724 goto err_destroy_direct_tirs;
3725 }
3726
3727 err = mlx5e_tc_init(priv);
3728 if (err)
3729 goto err_destroy_flow_steering;
3730
3731 return 0;
3732
3733err_destroy_flow_steering:
3734 mlx5e_destroy_flow_steering(priv);
3735err_destroy_direct_tirs:
3736 mlx5e_destroy_direct_tirs(priv);
3737err_destroy_indirect_tirs:
3738 mlx5e_destroy_indirect_tirs(priv);
3739err_destroy_direct_rqts:
3740 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3741 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3742err_destroy_indirect_rqts:
3743 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3744 return err;
3745}
3746
3747static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3748{
3749 int i;
3750
3751 mlx5e_tc_cleanup(priv);
3752 mlx5e_destroy_flow_steering(priv);
3753 mlx5e_destroy_direct_tirs(priv);
3754 mlx5e_destroy_indirect_tirs(priv);
3755 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3756 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3757 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3758}
3759
3760static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3761{
3762 int err;
3763
3764 err = mlx5e_create_tises(priv);
3765 if (err) {
3766 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3767 return err;
3768 }
3769
3770#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 3771 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 3772#endif
3773 return 0;
3774}
3775
3776static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3777{
3778 struct net_device *netdev = priv->netdev;
3779 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3780 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3781 struct mlx5_eswitch_rep rep;
6bfd390b 3782
7907f23a
AH		 3783 mlx5_lag_add(mdev, netdev);
3784
6bfd390b
HHZ		 3785 if (mlx5e_vxlan_allowed(mdev)) {
3786 rtnl_lock();
3787 udp_tunnel_get_rx_info(netdev);
3788 rtnl_unlock();
3789 }
3790
3791 mlx5e_enable_async_events(priv);
3792 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3793
3794 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3795 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3796 rep.load = mlx5e_nic_rep_load;
3797 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3798 rep.vport = FDB_UPLINK_VPORT;
127ea380 3799 rep.priv_data = priv;
9deb2241 3800 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3801 }
6bfd390b
HHZ		 3802}
3803
3804static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3805{
3806 queue_work(priv->wq, &priv->set_rx_mode_work);
3807 mlx5e_disable_async_events(priv);
7907f23a 3808 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3809}
3810
3811static const struct mlx5e_profile mlx5e_nic_profile = {
3812 .init = mlx5e_nic_init,
3813 .cleanup = mlx5e_nic_cleanup,
3814 .init_rx = mlx5e_init_nic_rx,
3815 .cleanup_rx = mlx5e_cleanup_nic_rx,
3816 .init_tx = mlx5e_init_nic_tx,
3817 .cleanup_tx = mlx5e_cleanup_nic_tx,
3818 .enable = mlx5e_nic_enable,
3819 .disable = mlx5e_nic_disable,
3820 .update_stats = mlx5e_update_stats,
3821 .max_nch = mlx5e_get_max_num_channels,
3822 .max_tc = MLX5E_MAX_NUM_TC,
3823};
3824
26e59d80
MHY		 3825struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3826 const struct mlx5e_profile *profile,
3827 void *ppriv)
f62b8bb8 3828{
26e59d80 3829 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3830 struct net_device *netdev;
3831 struct mlx5e_priv *priv;
f62b8bb8 3832
08fb1dac 3833 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3834 nch * profile->max_tc,
08fb1dac 3835 nch);
f62b8bb8
AV		 3836 if (!netdev) {
3837 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3838 return NULL;
3839 }
3840
127ea380 3841 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3842
3843 netif_carrier_off(netdev);
3844
3845 priv = netdev_priv(netdev);
3846
7bb29755
MF		 3847 priv->wq = create_singlethread_workqueue("mlx5e");
3848 if (!priv->wq)
26e59d80
MHY		 3849 goto err_cleanup_nic;
3850
3851 return netdev;
3852
3853err_cleanup_nic:
3854 profile->cleanup(priv);
3855 free_netdev(netdev);
3856
3857 return NULL;
3858}
3859
3860int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3861{
3862 const struct mlx5e_profile *profile;
3863 struct mlx5e_priv *priv;
b80f71f5 3864 u16 max_mtu;
26e59d80
MHY		 3865 int err;
3866
3867 priv = netdev_priv(netdev);
3868 profile = priv->profile;
3869 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3870
bc77b240
TT		 3871 err = mlx5e_create_umr_mkey(priv);
3872 if (err) {
3873 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
26e59d80 3874 goto out;
bc77b240
TT		 3875 }
3876
6bfd390b
HHZ		 3877 err = profile->init_tx(priv);
3878 if (err)
bc77b240 3879 goto err_destroy_umr_mkey;
5c50368f
AS		 3880
3881 err = mlx5e_open_drop_rq(priv);
3882 if (err) {
3883 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3884 goto err_cleanup_tx;
5c50368f
AS		 3885 }
3886
6bfd390b
HHZ		 3887 err = profile->init_rx(priv);
3888 if (err)
5c50368f 3889 goto err_close_drop_rq;
5c50368f 3890
593cf338
RS		 3891 mlx5e_create_q_counter(priv);
3892
33cfaaa8 3893 mlx5e_init_l2_addr(priv);
5c50368f 3894
b80f71f5
JW		 3895 /* MTU range: 68 - hw-specific max */
3896 netdev->min_mtu = ETH_MIN_MTU;
3897 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3898 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3899
13f9bba7
SM		 3900 mlx5e_set_dev_port_mtu(netdev);
3901
6bfd390b
HHZ		 3902 if (profile->enable)
3903 profile->enable(priv);
f62b8bb8 3904
26e59d80
MHY		 3905 rtnl_lock();
3906 if (netif_running(netdev))
3907 mlx5e_open(netdev);
3908 netif_device_attach(netdev);
3909 rtnl_unlock();
f62b8bb8 3910
26e59d80 3911 return 0;
5c50368f
AS		 3912
3913err_close_drop_rq:
3914 mlx5e_close_drop_rq(priv);
3915
6bfd390b
HHZ		 3916err_cleanup_tx:
3917 profile->cleanup_tx(priv);
5c50368f 3918
bc77b240
TT		 3919err_destroy_umr_mkey:
3920 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3921
26e59d80
MHY		 3922out:
3923 return err;
f62b8bb8
AV		 3924}
3925
127ea380
HHZ		 3926static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3927{
3928 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3929 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3930 int vport;
dbe413e3 3931 u8 mac[ETH_ALEN];
127ea380
HHZ		 3932
3933 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3934 return;
3935
dbe413e3
HHZ		 3936 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3937
127ea380
HHZ		 3938 for (vport = 1; vport < total_vfs; vport++) {
3939 struct mlx5_eswitch_rep rep;
3940
cb67b832
HHZ		 3941 rep.load = mlx5e_vport_rep_load;
3942 rep.unload = mlx5e_vport_rep_unload;
127ea380 3943 rep.vport = vport;
dbe413e3 3944 ether_addr_copy(rep.hw_id, mac);
9deb2241 3945 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3946 }
3947}
3948
26e59d80
MHY		 3949void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3950{
3951 struct mlx5e_priv *priv = netdev_priv(netdev);
3952 const struct mlx5e_profile *profile = priv->profile;
3953
3954 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3955 if (profile->disable)
3956 profile->disable(priv);
3957
3958 flush_workqueue(priv->wq);
3959
3960 rtnl_lock();
3961 if (netif_running(netdev))
3962 mlx5e_close(netdev);
3963 netif_device_detach(netdev);
3964 rtnl_unlock();
3965
3966 mlx5e_destroy_q_counter(priv);
3967 profile->cleanup_rx(priv);
3968 mlx5e_close_drop_rq(priv);
3969 profile->cleanup_tx(priv);
3970 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3971 cancel_delayed_work_sync(&priv->update_stats_work);
3972}
3973
3974/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3975 * hardware contexts and to connect it to the current netdev.
3976 */
3977static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3978{
3979 struct mlx5e_priv *priv = vpriv;
3980 struct net_device *netdev = priv->netdev;
3981 int err;
3982
3983 if (netif_device_present(netdev))
3984 return 0;
3985
3986 err = mlx5e_create_mdev_resources(mdev);
3987 if (err)
3988 return err;
3989
3990 err = mlx5e_attach_netdev(mdev, netdev);
3991 if (err) {
3992 mlx5e_destroy_mdev_resources(mdev);
3993 return err;
3994 }
3995
3996 return 0;
3997}
3998
3999static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4000{
4001 struct mlx5e_priv *priv = vpriv;
4002 struct net_device *netdev = priv->netdev;
4003
4004 if (!netif_device_present(netdev))
4005 return;
4006
4007 mlx5e_detach_netdev(mdev, netdev);
4008 mlx5e_destroy_mdev_resources(mdev);
4009}
4010
b50d292b
HHZ		 4011static void *mlx5e_add(struct mlx5_core_dev *mdev)
4012{
127ea380 4013 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4014 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4015 void *ppriv = NULL;
26e59d80
MHY		 4016 void *priv;
4017 int vport;
4018 int err;
4019 struct net_device *netdev;
b50d292b 4020
26e59d80
MHY		 4021 err = mlx5e_check_required_hca_cap(mdev);
4022 if (err)
b50d292b
HHZ		 4023 return NULL;
4024
127ea380
HHZ		 4025 mlx5e_register_vport_rep(mdev);
4026
4027 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4028 ppriv = &esw->offloads.vport_reps[0];
4029
26e59d80
MHY		 4030 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4031 if (!netdev) {
4032 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4033 goto err_unregister_reps;
4034 }
4035
4036 priv = netdev_priv(netdev);
4037
4038 err = mlx5e_attach(mdev, priv);
4039 if (err) {
4040 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4041 goto err_destroy_netdev;
4042 }
4043
4044 err = register_netdev(netdev);
4045 if (err) {
4046 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4047 goto err_detach;
b50d292b 4048 }
26e59d80
MHY		 4049
4050 return priv;
4051
4052err_detach:
4053 mlx5e_detach(mdev, priv);
4054
4055err_destroy_netdev:
4056 mlx5e_destroy_netdev(mdev, priv);
4057
4058err_unregister_reps:
4059 for (vport = 1; vport < total_vfs; vport++)
4060 mlx5_eswitch_unregister_vport_rep(esw, vport);
4061
4062 return NULL;
b50d292b
HHZ		 4063}
4064
cb67b832 4065void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4066{
6bfd390b 4067 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4068 struct net_device *netdev = priv->netdev;
4069
7bb29755 4070 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4071 if (profile->cleanup)
4072 profile->cleanup(priv);
26e59d80 4073 free_netdev(netdev);
f62b8bb8
AV		 4074}
4075
b50d292b
HHZ		 4076static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4077{
127ea380
HHZ		 4078 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4079 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4080 struct mlx5e_priv *priv = vpriv;
127ea380 4081 int vport;
b50d292b 4082
127ea380
HHZ		 4083 for (vport = 1; vport < total_vfs; vport++)
4084 mlx5_eswitch_unregister_vport_rep(esw, vport);
4085
5e1e93c7 4086 unregister_netdev(priv->netdev);
26e59d80
MHY		 4087 mlx5e_detach(mdev, vpriv);
4088 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4089}
4090
f62b8bb8
AV		 4091static void *mlx5e_get_netdev(void *vpriv)
4092{
4093 struct mlx5e_priv *priv = vpriv;
4094
4095 return priv->netdev;
4096}
4097
4098static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4099 .add = mlx5e_add,
4100 .remove = mlx5e_remove,
26e59d80
MHY		 4101 .attach = mlx5e_attach,
4102 .detach = mlx5e_detach,
f62b8bb8
AV		 4103 .event = mlx5e_async_event,
4104 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4105 .get_dev = mlx5e_get_netdev,
4106};
4107
4108void mlx5e_init(void)
4109{
665bc539 4110 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4111 mlx5_register_interface(&mlx5e_interface);
4112}
4113
4114void mlx5e_cleanup(void)
4115{
4116 mlx5_unregister_interface(&mlx5e_interface);
4117}
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