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net/mlx5e: Proper names for SQ/RQ/CQ functions
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac 33#include <net/tc_act/tc_gact.h>
b4e029da 34#include <linux/crash_dump.h>
e8f887ac 35#include <net/pkt_cls.h>
86d722ad 36#include <linux/mlx5/fs.h>
b3f63c3d 37#include <net/vxlan.h>
86994156 38#include <linux/bpf.h>
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
66e49ded 41#include "eswitch.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
47 bool am_enabled;
f62b8bb8
AV		 48};
49
50struct mlx5e_sq_param {
51 u32 sqc[MLX5_ST_SZ_DW(sqc)];
52 struct mlx5_wq_param wq;
58d52291 53 u16 max_inline;
cff92d7c 54 u8 min_inline_mode;
f10b7cc7 55 enum mlx5e_sq_type type;
f62b8bb8
AV		 56};
57
58struct mlx5e_cq_param {
59 u32 cqc[MLX5_ST_SZ_DW(cqc)];
60 struct mlx5_wq_param wq;
61 u16 eq_ix;
9908aa29 62 u8 cq_period_mode;
f62b8bb8
AV		 63};
64
65struct mlx5e_channel_param {
66 struct mlx5e_rq_param rq;
67 struct mlx5e_sq_param sq;
b5503b99 68 struct mlx5e_sq_param xdp_sq;
d3c9bc27 69 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 70 struct mlx5e_cq_param rx_cq;
71 struct mlx5e_cq_param tx_cq;
d3c9bc27 72 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 73};
74
2fc4bfb7
SM		 75static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
76{
77 return MLX5_CAP_GEN(mdev, striding_rq) &&
78 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
79 MLX5_CAP_ETH(mdev, reg_umr_sq);
80}
81
6dc4b54e 82void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
2fc4bfb7
SM		 83{
84 priv->params.rq_wq_type = rq_type;
4078e637 85 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2fc4bfb7
SM		 86 switch (priv->params.rq_wq_type) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
b4e029da
KH		 88 priv->params.log_rq_size = is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
9bcc8606
SD		 91 priv->params.mpwqe_log_stride_sz =
92 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
f32f5bd2
DJ		 93 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(priv->mdev) :
94 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(priv->mdev);
2fc4bfb7
SM		 95 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
96 priv->params.mpwqe_log_stride_sz;
97 break;
98 default: /* MLX5_WQ_TYPE_LINKED_LIST */
b4e029da
KH		 99 priv->params.log_rq_size = is_kdump_kernel() ?
100 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
101 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 102
103 /* Extra room needed for build_skb */
104 priv->params.lro_wqe_sz -= MLX5_RX_HEADROOM +
105 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7
SM		 106 }
107 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
108 BIT(priv->params.log_rq_size));
109
110 mlx5_core_info(priv->mdev,
111 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
112 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
113 BIT(priv->params.log_rq_size),
114 BIT(priv->params.mpwqe_log_stride_sz),
9bcc8606 115 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 116}
117
118static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
119{
86994156
RS		 120 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
121 !priv->xdp_prog ?
2fc4bfb7
SM		 122 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
123 MLX5_WQ_TYPE_LINKED_LIST;
124 mlx5e_set_rq_type_params(priv, rq_type);
125}
126
f62b8bb8
AV		 127static void mlx5e_update_carrier(struct mlx5e_priv *priv)
128{
129 struct mlx5_core_dev *mdev = priv->mdev;
130 u8 port_state;
131
132 port_state = mlx5_query_vport_state(mdev,
e7546514 133 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 134
87424ad5
SD		 135 if (port_state == VPORT_STATE_UP) {
136 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 137 netif_carrier_on(priv->netdev);
87424ad5
SD		 138 } else {
139 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 140 netif_carrier_off(priv->netdev);
87424ad5 141 }
f62b8bb8
AV		 142}
143
144static void mlx5e_update_carrier_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 update_carrier_work);
148
149 mutex_lock(&priv->state_lock);
150 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
151 mlx5e_update_carrier(priv);
152 mutex_unlock(&priv->state_lock);
153}
154
3947ca18
DJ		 155static void mlx5e_tx_timeout_work(struct work_struct *work)
156{
157 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
158 tx_timeout_work);
159 int err;
160
161 rtnl_lock();
162 mutex_lock(&priv->state_lock);
163 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
164 goto unlock;
165 mlx5e_close_locked(priv->netdev);
166 err = mlx5e_open_locked(priv->netdev);
167 if (err)
168 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
169 err);
170unlock:
171 mutex_unlock(&priv->state_lock);
172 rtnl_unlock();
173}
174
9218b44d 175static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 176{
9218b44d 177 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 178 struct mlx5e_rq_stats *rq_stats;
179 struct mlx5e_sq_stats *sq_stats;
9218b44d 180 u64 tx_offload_none = 0;
f62b8bb8
AV		 181 int i, j;
182
9218b44d 183 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 184 for (i = 0; i < priv->params.num_channels; i++) {
185 rq_stats = &priv->channel[i]->rq.stats;
186
faf4478b
GP		 187 s->rx_packets += rq_stats->packets;
188 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 189 s->rx_lro_packets += rq_stats->lro_packets;
190 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 191 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 192 s->rx_csum_complete += rq_stats->csum_complete;
193 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 194 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 195 s->rx_xdp_tx += rq_stats->xdp_tx;
196 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 197 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 198 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 199 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 200 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
201 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 202 s->rx_cache_reuse += rq_stats->cache_reuse;
203 s->rx_cache_full += rq_stats->cache_full;
204 s->rx_cache_empty += rq_stats->cache_empty;
205 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 206
a4418a6c 207 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 208 sq_stats = &priv->channel[i]->sq[j].stats;
209
faf4478b
GP		 210 s->tx_packets += sq_stats->packets;
211 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 212 s->tx_tso_packets += sq_stats->tso_packets;
213 s->tx_tso_bytes += sq_stats->tso_bytes;
214 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
215 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 216 s->tx_queue_stopped += sq_stats->stopped;
217 s->tx_queue_wake += sq_stats->wake;
218 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 219 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 220 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
221 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 222 }
223 }
224
9218b44d 225 /* Update calculated offload counters */
bfe6d8d1
GP		 226 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
227 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 228
bfe6d8d1 229 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 230 priv->stats.pport.phy_counters,
231 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 232}
233
234static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
235{
236 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
237 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 238 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 239 struct mlx5_core_dev *mdev = priv->mdev;
240
f62b8bb8
AV		 241 MLX5_SET(query_vport_counter_in, in, opcode,
242 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
243 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
244 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
245
246 memset(out, 0, outlen);
9218b44d
GP		 247 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
248}
249
250static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
251{
252 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
253 struct mlx5_core_dev *mdev = priv->mdev;
254 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 255 int prio;
9218b44d
GP		 256 void *out;
257 u32 *in;
258
259 in = mlx5_vzalloc(sz);
260 if (!in)
f62b8bb8
AV		 261 goto free_out;
262
9218b44d 263 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->IEEE_802_3_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 268
9218b44d
GP		 269 out = pstats->RFC_2863_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
272
273 out = pstats->RFC_2819_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 276
121fcdc8
GP		 277 out = pstats->phy_counters;
278 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
280
5db0a4f6
GP		 281 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
282 out = pstats->phy_statistical_counters;
283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
284 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
285 }
286
cf678570
GP		 287 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
288 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
289 out = pstats->per_prio_counters[prio];
290 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
291 mlx5_core_access_reg(mdev, in, sz, out, sz,
292 MLX5_REG_PPCNT, 0, 0);
293 }
294
f62b8bb8 295free_out:
9218b44d
GP		 296 kvfree(in);
297}
298
299static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
300{
301 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
302
303 if (!priv->q_counter)
304 return;
305
306 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
307 &qcnt->rx_out_of_buffer);
308}
309
0f7f3481
GP		 310static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
311{
312 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
313 struct mlx5_core_dev *mdev = priv->mdev;
314 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
315 void *out;
316 u32 *in;
317
318 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
319 return;
320
321 in = mlx5_vzalloc(sz);
322 if (!in)
323 return;
324
325 out = pcie_stats->pcie_perf_counters;
326 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
327 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
328
329 kvfree(in);
330}
331
9218b44d
GP		 332void mlx5e_update_stats(struct mlx5e_priv *priv)
333{
3dd69e3d 334 mlx5e_update_pcie_counters(priv);
9218b44d 335 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 336 mlx5e_update_vport_counters(priv);
337 mlx5e_update_q_counter(priv);
121fcdc8 338 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 339}
340
cb67b832 341void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 342{
343 struct delayed_work *dwork = to_delayed_work(work);
344 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
345 update_stats_work);
346 mutex_lock(&priv->state_lock);
347 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 348 priv->profile->update_stats(priv);
7bb29755
MF		 349 queue_delayed_work(priv->wq, dwork,
350 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 351 }
352 mutex_unlock(&priv->state_lock);
353}
354
daa21560
TT		 355static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
356 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 357{
daa21560 358 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 359 struct ptp_clock_event ptp_event;
360 struct mlx5_eqe *eqe = NULL;
daa21560 361
e0f46eb9 362 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 363 return;
364
f62b8bb8
AV		 365 switch (event) {
366 case MLX5_DEV_EVENT_PORT_UP:
367 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 368 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 369 break;
ee7f1220
EE		 370 case MLX5_DEV_EVENT_PPS:
371 eqe = (struct mlx5_eqe *)param;
372 ptp_event.type = PTP_CLOCK_EXTTS;
373 ptp_event.index = eqe->data.pps.pin;
374 ptp_event.timestamp =
375 timecounter_cyc2time(&priv->tstamp.clock,
376 be64_to_cpu(eqe->data.pps.time_stamp));
377 mlx5e_pps_event_handler(vpriv, &ptp_event);
378 break;
f62b8bb8
AV		 379 default:
380 break;
381 }
382}
383
f62b8bb8
AV		 384static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
385{
e0f46eb9 386 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 387}
388
389static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
390{
e0f46eb9 391 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 392 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 393}
394
7e426671
TT		 395static inline int mlx5e_get_wqe_mtt_sz(void)
396{
397 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
398 * To avoid copying garbage after the mtt array, we allocate
399 * a little more.
400 */
401 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
402 MLX5_UMR_MTT_ALIGNMENT);
403}
404
405static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
406 struct mlx5e_umr_wqe *wqe, u16 ix)
407{
408 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
409 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
410 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 411 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 412 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
413 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
414
415 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
416 ds_cnt);
417 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
418 cseg->imm = rq->mkey_be;
419
420 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 421 ucseg->xlt_octowords =
7e426671
TT		 422 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
423 ucseg->bsf_octowords =
424 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
425 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
426
427 dseg->lkey = sq->mkey_be;
428 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
429}
430
431static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
432 struct mlx5e_channel *c)
433{
434 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
435 int mtt_sz = mlx5e_get_wqe_mtt_sz();
436 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
437 int i;
438
21c59685
SM		 439 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
440 GFP_KERNEL, cpu_to_node(c->cpu));
441 if (!rq->mpwqe.info)
7e426671
TT		 442 goto err_out;
443
444 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 445 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 446 cpu_to_node(c->cpu));
21c59685 447 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 448 goto err_free_wqe_info;
449
450 for (i = 0; i < wq_sz; i++) {
21c59685 451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 452
21c59685 453 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 454 MLX5_UMR_ALIGN);
455 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
456 PCI_DMA_TODEVICE);
457 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
458 goto err_unmap_mtts;
459
460 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
461 }
462
463 return 0;
464
465err_unmap_mtts:
466 while (--i >= 0) {
21c59685 467 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 468
469 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
470 PCI_DMA_TODEVICE);
471 }
21c59685 472 kfree(rq->mpwqe.mtt_no_align);
7e426671 473err_free_wqe_info:
21c59685 474 kfree(rq->mpwqe.info);
7e426671
TT		 475
476err_out:
477 return -ENOMEM;
478}
479
480static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
481{
482 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
483 int mtt_sz = mlx5e_get_wqe_mtt_sz();
484 int i;
485
486 for (i = 0; i < wq_sz; i++) {
21c59685 487 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 488
489 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
490 PCI_DMA_TODEVICE);
491 }
21c59685
SM		 492 kfree(rq->mpwqe.mtt_no_align);
493 kfree(rq->mpwqe.info);
7e426671
TT		 494}
495
ec8b9981
TT		 496static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
497 u64 npages, u8 page_shift,
498 struct mlx5_core_mkey *umr_mkey)
3608ae77
TT		 499{
500 struct mlx5_core_dev *mdev = priv->mdev;
3608ae77
TT		 501 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
502 void *mkc;
503 u32 *in;
504 int err;
505
ec8b9981
TT		 506 if (!MLX5E_VALID_NUM_MTTS(npages))
507 return -EINVAL;
508
3608ae77
TT		 509 in = mlx5_vzalloc(inlen);
510 if (!in)
511 return -ENOMEM;
512
513 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
514
3608ae77
TT		 515 MLX5_SET(mkc, mkc, free, 1);
516 MLX5_SET(mkc, mkc, umr_en, 1);
517 MLX5_SET(mkc, mkc, lw, 1);
518 MLX5_SET(mkc, mkc, lr, 1);
519 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
520
521 MLX5_SET(mkc, mkc, qpn, 0xffffff);
522 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 523 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 524 MLX5_SET(mkc, mkc, translations_octword_size,
525 MLX5_MTT_OCTW(npages));
ec8b9981 526 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 527
ec8b9981 528 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 529
530 kvfree(in);
531 return err;
532}
533
ec8b9981
TT		 534static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
535{
536 struct mlx5e_priv *priv = rq->priv;
537 u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
538
539 return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
540}
541
3b77235b
SM		 542static int mlx5e_alloc_rq(struct mlx5e_channel *c,
543 struct mlx5e_rq_param *param,
544 struct mlx5e_rq *rq)
f62b8bb8
AV		 545{
546 struct mlx5e_priv *priv = c->priv;
547 struct mlx5_core_dev *mdev = priv->mdev;
548 void *rqc = param->rqc;
549 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 550 u32 byte_count;
1bfecfca
SM		 551 u32 frag_sz;
552 int npages;
f62b8bb8
AV		 553 int wq_sz;
554 int err;
555 int i;
556
311c7c71
SM		 557 param->wq.db_numa_node = cpu_to_node(c->cpu);
558
f62b8bb8
AV		 559 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
560 &rq->wq_ctrl);
561 if (err)
562 return err;
563
564 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
565
566 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 567
7e426671
TT		 568 rq->wq_type = priv->params.rq_wq_type;
569 rq->pdev = c->pdev;
570 rq->netdev = c->netdev;
571 rq->tstamp = &priv->tstamp;
572 rq->channel = c;
573 rq->ix = c->ix;
574 rq->priv = c->priv;
97bc402d
DB		 575
576 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
577 if (IS_ERR(rq->xdp_prog)) {
578 err = PTR_ERR(rq->xdp_prog);
579 rq->xdp_prog = NULL;
580 goto err_rq_wq_destroy;
581 }
7e426671 582
d8bec2b2 583 if (rq->xdp_prog) {
b5503b99 584 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 585 rq->rx_headroom = XDP_PACKET_HEADROOM;
586 } else {
587 rq->buff.map_dir = DMA_FROM_DEVICE;
588 rq->rx_headroom = MLX5_RX_HEADROOM;
589 }
b5503b99 590
461017cb
TT		 591 switch (priv->params.rq_wq_type) {
592 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 593 if (mlx5e_is_vf_vport_rep(priv)) {
594 err = -EINVAL;
595 goto err_rq_wq_destroy;
596 }
597
461017cb
TT		 598 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
599 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 600 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 601
d9d9f156
TT		 602 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
603 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 604
605 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
606 byte_count = rq->buff.wqe_sz;
ec8b9981
TT		 607
608 err = mlx5e_create_rq_umr_mkey(rq);
7e426671
TT		 609 if (err)
610 goto err_rq_wq_destroy;
ec8b9981
TT		 611 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
612
613 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
614 if (err)
615 goto err_destroy_umr_mkey;
461017cb
TT		 616 break;
617 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 618 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
619 GFP_KERNEL, cpu_to_node(c->cpu));
620 if (!rq->dma_info) {
461017cb
TT		 621 err = -ENOMEM;
622 goto err_rq_wq_destroy;
623 }
1bfecfca 624
f5f82476
OG		 625 if (mlx5e_is_vf_vport_rep(priv))
626 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
627 else
628 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
629
461017cb 630 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 631 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 632
1bfecfca 633 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 634 priv->params.lro_wqe_sz :
635 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 636 byte_count = rq->buff.wqe_sz;
637
638 /* calc the required page order */
d8bec2b2 639 frag_sz = rq->rx_headroom +
1bfecfca
SM		 640 byte_count /* packet data */ +
641 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
642 frag_sz = SKB_DATA_ALIGN(frag_sz);
643
644 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
645 rq->buff.page_order = order_base_2(npages);
646
461017cb 647 byte_count |= MLX5_HW_START_PADDING;
7e426671 648 rq->mkey_be = c->mkey_be;
461017cb 649 }
f62b8bb8
AV		 650
651 for (i = 0; i < wq_sz; i++) {
652 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
653
461017cb 654 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 655 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 656 }
657
cb3c7fd4
GR		 658 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
659 rq->am.mode = priv->params.rx_cq_period_mode;
660
4415a031
TT		 661 rq->page_cache.head = 0;
662 rq->page_cache.tail = 0;
663
f62b8bb8
AV		 664 return 0;
665
ec8b9981
TT		 666err_destroy_umr_mkey:
667 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
668
f62b8bb8 669err_rq_wq_destroy:
97bc402d
DB		 670 if (rq->xdp_prog)
671 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 672 mlx5_wq_destroy(&rq->wq_ctrl);
673
674 return err;
675}
676
3b77235b 677static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 678{
4415a031
TT		 679 int i;
680
86994156
RS		 681 if (rq->xdp_prog)
682 bpf_prog_put(rq->xdp_prog);
683
461017cb
TT		 684 switch (rq->wq_type) {
685 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 686 mlx5e_rq_free_mpwqe_info(rq);
ec8b9981 687 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
461017cb
TT		 688 break;
689 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 690 kfree(rq->dma_info);
461017cb
TT		 691 }
692
4415a031
TT		 693 for (i = rq->page_cache.head; i != rq->page_cache.tail;
694 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
695 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
696
697 mlx5e_page_release(rq, dma_info, false);
698 }
f62b8bb8
AV		 699 mlx5_wq_destroy(&rq->wq_ctrl);
700}
701
3b77235b 702static int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
f62b8bb8 703{
50cfa25a 704 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 705 struct mlx5_core_dev *mdev = priv->mdev;
706
707 void *in;
708 void *rqc;
709 void *wq;
710 int inlen;
711 int err;
712
713 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
714 sizeof(u64) * rq->wq_ctrl.buf.npages;
715 in = mlx5_vzalloc(inlen);
716 if (!in)
717 return -ENOMEM;
718
719 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
720 wq = MLX5_ADDR_OF(rqc, rqc, wq);
721
722 memcpy(rqc, param->rqc, sizeof(param->rqc));
723
97de9f31 724 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 725 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 726 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 727 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 728 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 729 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
730
731 mlx5_fill_page_array(&rq->wq_ctrl.buf,
732 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
733
7db22ffb 734 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 735
736 kvfree(in);
737
738 return err;
739}
740
36350114
GP		 741static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
742 int next_state)
f62b8bb8
AV		 743{
744 struct mlx5e_channel *c = rq->channel;
745 struct mlx5e_priv *priv = c->priv;
746 struct mlx5_core_dev *mdev = priv->mdev;
747
748 void *in;
749 void *rqc;
750 int inlen;
751 int err;
752
753 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
754 in = mlx5_vzalloc(inlen);
755 if (!in)
756 return -ENOMEM;
757
758 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
759
760 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
761 MLX5_SET(rqc, rqc, state, next_state);
762
7db22ffb 763 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 764
765 kvfree(in);
766
767 return err;
768}
769
36350114
GP		 770static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
771{
772 struct mlx5e_channel *c = rq->channel;
773 struct mlx5e_priv *priv = c->priv;
774 struct mlx5_core_dev *mdev = priv->mdev;
775
776 void *in;
777 void *rqc;
778 int inlen;
779 int err;
780
781 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
782 in = mlx5_vzalloc(inlen);
783 if (!in)
784 return -ENOMEM;
785
786 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
787
788 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 789 MLX5_SET64(modify_rq_in, in, modify_bitmask,
790 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 791 MLX5_SET(rqc, rqc, vsd, vsd);
792 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
793
794 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
795
796 kvfree(in);
797
798 return err;
799}
800
3b77235b 801static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 802{
50cfa25a 803 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 804}
805
806static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
807{
01c196a2 808 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 809 struct mlx5e_channel *c = rq->channel;
810 struct mlx5e_priv *priv = c->priv;
811 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 812
01c196a2 813 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 814 if (wq->cur_sz >= priv->params.min_rx_wqes)
815 return 0;
816
817 msleep(20);
818 }
819
820 return -ETIMEDOUT;
821}
822
f2fde18c
SM		 823static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
824{
825 struct mlx5_wq_ll *wq = &rq->wq;
826 struct mlx5e_rx_wqe *wqe;
827 __be16 wqe_ix_be;
828 u16 wqe_ix;
829
8484f9ed
SM		 830 /* UMR WQE (if in progress) is always at wq->head */
831 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 832 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 833
f2fde18c
SM		 834 while (!mlx5_wq_ll_is_empty(wq)) {
835 wqe_ix_be = *wq->tail_next;
836 wqe_ix = be16_to_cpu(wqe_ix_be);
837 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
838 rq->dealloc_wqe(rq, wqe_ix);
839 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
840 &wqe->next.next_wqe_index);
841 }
842}
843
f62b8bb8
AV		 844static int mlx5e_open_rq(struct mlx5e_channel *c,
845 struct mlx5e_rq_param *param,
846 struct mlx5e_rq *rq)
847{
d3c9bc27
TT		 848 struct mlx5e_sq *sq = &c->icosq;
849 u16 pi = sq->pc & sq->wq.sz_m1;
864b2d71 850 struct mlx5e_tx_wqe *nopwqe;
f62b8bb8
AV		 851 int err;
852
3b77235b 853 err = mlx5e_alloc_rq(c, param, rq);
f62b8bb8
AV		 854 if (err)
855 return err;
856
3b77235b 857 err = mlx5e_create_rq(rq, param);
f62b8bb8 858 if (err)
3b77235b 859 goto err_free_rq;
f62b8bb8 860
c0f1147d 861 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
36350114 862 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 863 if (err)
3b77235b 864 goto err_destroy_rq;
f62b8bb8 865
cb3c7fd4
GR		 866 if (param->am_enabled)
867 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
868
f10b7cc7
SM		 869 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
870 sq->db.ico_wqe[pi].num_wqebbs = 1;
864b2d71
SM		 871 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
872 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
873 sq->stats.nop++; /* TODO no need for SQ stats in ico */
f62b8bb8
AV		 874 return 0;
875
f62b8bb8 876err_destroy_rq:
3b77235b 877 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 878 mlx5e_destroy_rq(rq);
3b77235b
SM		 879err_free_rq:
880 mlx5e_free_rq(rq);
f62b8bb8
AV		 881
882 return err;
883}
884
885static void mlx5e_close_rq(struct mlx5e_rq *rq)
886{
c0f1147d 887 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 888 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 889 cancel_work_sync(&rq->am.work);
890
f62b8bb8 891 mlx5e_destroy_rq(rq);
3b77235b
SM		 892 mlx5e_free_rx_descs(rq);
893 mlx5e_free_rq(rq);
f62b8bb8
AV		 894}
895
b5503b99
SM		 896static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
897{
898 kfree(sq->db.xdp.di);
b5503b99
SM		 899}
900
901static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
902{
903 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
904
905 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
906 GFP_KERNEL, numa);
2239185c 907 if (!sq->db.xdp.di) {
b5503b99
SM		 908 mlx5e_free_sq_xdp_db(sq);
909 return -ENOMEM;
910 }
911
912 return 0;
913}
914
f10b7cc7 915static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 916{
f10b7cc7 917 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 918}
919
f10b7cc7
SM		 920static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
921{
922 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
923
924 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
925 GFP_KERNEL, numa);
926 if (!sq->db.ico_wqe)
927 return -ENOMEM;
928
929 return 0;
930}
931
932static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
933{
934 kfree(sq->db.txq.wqe_info);
935 kfree(sq->db.txq.dma_fifo);
936 kfree(sq->db.txq.skb);
937}
938
939static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 940{
941 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
942 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
943
f10b7cc7
SM		 944 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
945 GFP_KERNEL, numa);
946 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
947 GFP_KERNEL, numa);
948 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
949 GFP_KERNEL, numa);
950 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
951 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 952 return -ENOMEM;
953 }
954
955 sq->dma_fifo_mask = df_sz - 1;
956
957 return 0;
958}
959
f10b7cc7
SM		 960static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
961{
962 switch (sq->type) {
963 case MLX5E_SQ_TXQ:
964 mlx5e_free_sq_txq_db(sq);
965 break;
966 case MLX5E_SQ_ICO:
967 mlx5e_free_sq_ico_db(sq);
968 break;
b5503b99
SM		 969 case MLX5E_SQ_XDP:
970 mlx5e_free_sq_xdp_db(sq);
971 break;
f10b7cc7
SM		 972 }
973}
974
975static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
976{
977 switch (sq->type) {
978 case MLX5E_SQ_TXQ:
979 return mlx5e_alloc_sq_txq_db(sq, numa);
980 case MLX5E_SQ_ICO:
981 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 982 case MLX5E_SQ_XDP:
983 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 984 }
985
986 return 0;
987}
988
b5503b99
SM		 989static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
990{
991 switch (sq_type) {
992 case MLX5E_SQ_ICO:
993 return MLX5E_ICOSQ_MAX_WQEBBS;
994 case MLX5E_SQ_XDP:
2239185c 995 return 1;
b5503b99
SM		 996 }
997 return MLX5_SEND_WQE_MAX_WQEBBS;
998}
999
3b77235b
SM		 1000static int mlx5e_alloc_sq(struct mlx5e_channel *c,
1001 int tc,
1002 struct mlx5e_sq_param *param,
1003 struct mlx5e_sq *sq)
f62b8bb8
AV		 1004{
1005 struct mlx5e_priv *priv = c->priv;
1006 struct mlx5_core_dev *mdev = priv->mdev;
1007
1008 void *sqc = param->sqc;
1009 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1010 int err;
1011
f10b7cc7
SM		 1012 sq->type = param->type;
1013 sq->pdev = c->pdev;
1014 sq->tstamp = &priv->tstamp;
1015 sq->mkey_be = c->mkey_be;
1016 sq->channel = c;
1017 sq->tc = tc;
aff26157 1018 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f10b7cc7 1019
311c7c71
SM		 1020 param->wq.db_numa_node = cpu_to_node(c->cpu);
1021
f62b8bb8
AV		 1022 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1023 &sq->wq_ctrl);
1024 if (err)
aff26157 1025 return err;
f62b8bb8
AV		 1026
1027 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
30aa60b3 1028
58d52291 1029 sq->max_inline = param->max_inline;
a6f402e4 1030 sq->min_inline_mode = param->min_inline_mode;
f62b8bb8 1031
7ec0bb22
DC		 1032 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1033 if (err)
f62b8bb8
AV		 1034 goto err_sq_wq_destroy;
1035
f10b7cc7 1036 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 1037 int txq_ix;
1038
1039 txq_ix = c->ix + tc * priv->params.num_channels;
1040 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1041 priv->txq_to_sq_map[txq_ix] = sq;
1042 }
f62b8bb8 1043
b5503b99 1044 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
f62b8bb8
AV		 1045
1046 return 0;
1047
1048err_sq_wq_destroy:
1049 mlx5_wq_destroy(&sq->wq_ctrl);
1050
f62b8bb8
AV		 1051 return err;
1052}
1053
3b77235b 1054static void mlx5e_free_sq(struct mlx5e_sq *sq)
f62b8bb8 1055{
f62b8bb8
AV		 1056 mlx5e_free_sq_db(sq);
1057 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1058}
1059
3b77235b 1060static int mlx5e_create_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
f62b8bb8
AV		 1061{
1062 struct mlx5e_channel *c = sq->channel;
1063 struct mlx5e_priv *priv = c->priv;
1064 struct mlx5_core_dev *mdev = priv->mdev;
1065
1066 void *in;
1067 void *sqc;
1068 void *wq;
1069 int inlen;
1070 int err;
1071
1072 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1073 sizeof(u64) * sq->wq_ctrl.buf.npages;
1074 in = mlx5_vzalloc(inlen);
1075 if (!in)
1076 return -ENOMEM;
1077
1078 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1079 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1080
1081 memcpy(sqc, param->sqc, sizeof(param->sqc));
1082
f10b7cc7
SM		 1083 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1084 0 : priv->tisn[sq->tc]);
d3c9bc27 1085 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
a6f402e4
SM		 1086
1087 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1088 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
1089
f62b8bb8 1090 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1091 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1092
1093 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
aff26157 1094 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
f62b8bb8 1095 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1096 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1097 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1098
1099 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1100 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1101
7db22ffb 1102 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1103
1104 kvfree(in);
1105
1106 return err;
1107}
1108
507f0c81
YP		 1109static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1110 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1111{
1112 struct mlx5e_channel *c = sq->channel;
1113 struct mlx5e_priv *priv = c->priv;
1114 struct mlx5_core_dev *mdev = priv->mdev;
1115
1116 void *in;
1117 void *sqc;
1118 int inlen;
1119 int err;
1120
1121 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1122 in = mlx5_vzalloc(inlen);
1123 if (!in)
1124 return -ENOMEM;
1125
1126 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1127
1128 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1129 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1130 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1131 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1132 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1133 }
f62b8bb8 1134
7db22ffb 1135 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1136
1137 kvfree(in);
1138
1139 return err;
1140}
1141
3b77235b 1142static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
f62b8bb8
AV		 1143{
1144 struct mlx5e_channel *c = sq->channel;
1145 struct mlx5e_priv *priv = c->priv;
1146 struct mlx5_core_dev *mdev = priv->mdev;
1147
7db22ffb 1148 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1149 if (sq->rate_limit)
1150 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1151}
1152
1153static int mlx5e_open_sq(struct mlx5e_channel *c,
1154 int tc,
1155 struct mlx5e_sq_param *param,
1156 struct mlx5e_sq *sq)
1157{
1158 int err;
1159
3b77235b 1160 err = mlx5e_alloc_sq(c, tc, param, sq);
f62b8bb8
AV		 1161 if (err)
1162 return err;
1163
3b77235b 1164 err = mlx5e_create_sq(sq, param);
f62b8bb8 1165 if (err)
3b77235b 1166 goto err_free_sq;
f62b8bb8 1167
c0f1147d 1168 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
507f0c81
YP		 1169 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1170 false, 0);
f62b8bb8 1171 if (err)
3b77235b 1172 goto err_destroy_sq;
f62b8bb8 1173
d3c9bc27 1174 if (sq->txq) {
d3c9bc27
TT		 1175 netdev_tx_reset_queue(sq->txq);
1176 netif_tx_start_queue(sq->txq);
1177 }
f62b8bb8
AV		 1178
1179 return 0;
1180
f62b8bb8 1181err_destroy_sq:
3b77235b 1182 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
f62b8bb8 1183 mlx5e_destroy_sq(sq);
3b77235b
SM		 1184err_free_sq:
1185 mlx5e_free_sq(sq);
f62b8bb8
AV		 1186
1187 return err;
1188}
1189
1190static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1191{
1192 __netif_tx_lock_bh(txq);
1193 netif_tx_stop_queue(txq);
1194 __netif_tx_unlock_bh(txq);
1195}
1196
1197static void mlx5e_close_sq(struct mlx5e_sq *sq)
1198{
c0f1147d 1199 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6
SM		 1200 /* prevent netif_tx_wake_queue */
1201 napi_synchronize(&sq->channel->napi);
29429f33 1202
d3c9bc27 1203 if (sq->txq) {
d3c9bc27 1204 netif_tx_disable_queue(sq->txq);
f62b8bb8 1205
6e8dd6d6 1206 /* last doorbell out, godspeed .. */
864b2d71
SM		 1207 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1208 struct mlx5e_tx_wqe *nop;
1209
f10b7cc7 1210 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
864b2d71
SM		 1211 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1212 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
f10b7cc7 1213 }
29429f33 1214 }
f62b8bb8 1215
f62b8bb8 1216 mlx5e_destroy_sq(sq);
3b77235b
SM		 1217 mlx5e_free_sq_descs(sq);
1218 mlx5e_free_sq(sq);
f62b8bb8
AV		 1219}
1220
3b77235b
SM		 1221static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1222 struct mlx5e_cq_param *param,
1223 struct mlx5e_cq *cq)
f62b8bb8
AV		 1224{
1225 struct mlx5e_priv *priv = c->priv;
1226 struct mlx5_core_dev *mdev = priv->mdev;
1227 struct mlx5_core_cq *mcq = &cq->mcq;
1228 int eqn_not_used;
0b6e26ce 1229 unsigned int irqn;
f62b8bb8
AV		 1230 int err;
1231 u32 i;
1232
311c7c71
SM		 1233 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1234 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1235 param->eq_ix = c->ix;
1236
1237 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1238 &cq->wq_ctrl);
1239 if (err)
1240 return err;
1241
1242 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1243
1244 cq->napi = &c->napi;
1245
1246 mcq->cqe_sz = 64;
1247 mcq->set_ci_db = cq->wq_ctrl.db.db;
1248 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1249 *mcq->set_ci_db = 0;
1250 *mcq->arm_db = 0;
1251 mcq->vector = param->eq_ix;
1252 mcq->comp = mlx5e_completion_event;
1253 mcq->event = mlx5e_cq_error_event;
1254 mcq->irqn = irqn;
f62b8bb8
AV		 1255
1256 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1257 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1258
1259 cqe->op_own = 0xf1;
1260 }
1261
1262 cq->channel = c;
50cfa25a 1263 cq->priv = priv;
f62b8bb8
AV		 1264
1265 return 0;
1266}
1267
3b77235b 1268static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1269{
1c1b5228 1270 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1271}
1272
3b77235b 1273static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1274{
50cfa25a 1275 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1276 struct mlx5_core_dev *mdev = priv->mdev;
1277 struct mlx5_core_cq *mcq = &cq->mcq;
1278
1279 void *in;
1280 void *cqc;
1281 int inlen;
0b6e26ce 1282 unsigned int irqn_not_used;
f62b8bb8
AV		 1283 int eqn;
1284 int err;
1285
1286 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1287 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1288 in = mlx5_vzalloc(inlen);
1289 if (!in)
1290 return -ENOMEM;
1291
1292 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1293
1294 memcpy(cqc, param->cqc, sizeof(param->cqc));
1295
1c1b5228
TT		 1296 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1297 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1298
1299 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1300
9908aa29 1301 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1302 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1303 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1304 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1305 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1306 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1307
1308 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1309
1310 kvfree(in);
1311
1312 if (err)
1313 return err;
1314
1315 mlx5e_cq_arm(cq);
1316
1317 return 0;
1318}
1319
3b77235b 1320static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1321{
50cfa25a 1322 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1323 struct mlx5_core_dev *mdev = priv->mdev;
1324
1325 mlx5_core_destroy_cq(mdev, &cq->mcq);
1326}
1327
1328static int mlx5e_open_cq(struct mlx5e_channel *c,
1329 struct mlx5e_cq_param *param,
1330 struct mlx5e_cq *cq,
9908aa29 1331 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1332{
1333 int err;
1334 struct mlx5e_priv *priv = c->priv;
1335 struct mlx5_core_dev *mdev = priv->mdev;
1336
3b77235b 1337 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1338 if (err)
1339 return err;
1340
3b77235b 1341 err = mlx5e_create_cq(cq, param);
f62b8bb8 1342 if (err)
3b77235b 1343 goto err_free_cq;
f62b8bb8 1344
7524a5d8
GP		 1345 if (MLX5_CAP_GEN(mdev, cq_moderation))
1346 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1347 moderation.usec,
1348 moderation.pkts);
f62b8bb8
AV		 1349 return 0;
1350
3b77235b
SM		 1351err_free_cq:
1352 mlx5e_free_cq(cq);
f62b8bb8
AV		 1353
1354 return err;
1355}
1356
1357static void mlx5e_close_cq(struct mlx5e_cq *cq)
1358{
f62b8bb8 1359 mlx5e_destroy_cq(cq);
3b77235b 1360 mlx5e_free_cq(cq);
f62b8bb8
AV		 1361}
1362
1363static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1364{
1365 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1366}
1367
1368static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1369 struct mlx5e_channel_param *cparam)
1370{
1371 struct mlx5e_priv *priv = c->priv;
1372 int err;
1373 int tc;
1374
1375 for (tc = 0; tc < c->num_tc; tc++) {
1376 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1377 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1378 if (err)
1379 goto err_close_tx_cqs;
f62b8bb8
AV		 1380 }
1381
1382 return 0;
1383
1384err_close_tx_cqs:
1385 for (tc--; tc >= 0; tc--)
1386 mlx5e_close_cq(&c->sq[tc].cq);
1387
1388 return err;
1389}
1390
1391static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1392{
1393 int tc;
1394
1395 for (tc = 0; tc < c->num_tc; tc++)
1396 mlx5e_close_cq(&c->sq[tc].cq);
1397}
1398
1399static int mlx5e_open_sqs(struct mlx5e_channel *c,
1400 struct mlx5e_channel_param *cparam)
1401{
1402 int err;
1403 int tc;
1404
1405 for (tc = 0; tc < c->num_tc; tc++) {
1406 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1407 if (err)
1408 goto err_close_sqs;
1409 }
1410
1411 return 0;
1412
1413err_close_sqs:
1414 for (tc--; tc >= 0; tc--)
1415 mlx5e_close_sq(&c->sq[tc]);
1416
1417 return err;
1418}
1419
1420static void mlx5e_close_sqs(struct mlx5e_channel *c)
1421{
1422 int tc;
1423
1424 for (tc = 0; tc < c->num_tc; tc++)
1425 mlx5e_close_sq(&c->sq[tc]);
1426}
1427
5283af89 1428static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1429{
1430 int i;
1431
6bfd390b 1432 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1433 priv->channeltc_to_txq_map[ix][i] =
1434 ix + i * priv->params.num_channels;
03289b88
SM		 1435}
1436
507f0c81
YP		 1437static int mlx5e_set_sq_maxrate(struct net_device *dev,
1438 struct mlx5e_sq *sq, u32 rate)
1439{
1440 struct mlx5e_priv *priv = netdev_priv(dev);
1441 struct mlx5_core_dev *mdev = priv->mdev;
1442 u16 rl_index = 0;
1443 int err;
1444
1445 if (rate == sq->rate_limit)
1446 /* nothing to do */
1447 return 0;
1448
1449 if (sq->rate_limit)
1450 /* remove current rl index to free space to next ones */
1451 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1452
1453 sq->rate_limit = 0;
1454
1455 if (rate) {
1456 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1457 if (err) {
1458 netdev_err(dev, "Failed configuring rate %u: %d\n",
1459 rate, err);
1460 return err;
1461 }
1462 }
1463
1464 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1465 MLX5_SQC_STATE_RDY, true, rl_index);
1466 if (err) {
1467 netdev_err(dev, "Failed configuring rate %u: %d\n",
1468 rate, err);
1469 /* remove the rate from the table */
1470 if (rate)
1471 mlx5_rl_remove_rate(mdev, rate);
1472 return err;
1473 }
1474
1475 sq->rate_limit = rate;
1476 return 0;
1477}
1478
1479static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1480{
1481 struct mlx5e_priv *priv = netdev_priv(dev);
1482 struct mlx5_core_dev *mdev = priv->mdev;
1483 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1484 int err = 0;
1485
1486 if (!mlx5_rl_is_supported(mdev)) {
1487 netdev_err(dev, "Rate limiting is not supported on this device\n");
1488 return -EINVAL;
1489 }
1490
1491 /* rate is given in Mb/sec, HW config is in Kb/sec */
1492 rate = rate << 10;
1493
1494 /* Check whether rate in valid range, 0 is always valid */
1495 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1496 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1497 return -ERANGE;
1498 }
1499
1500 mutex_lock(&priv->state_lock);
1501 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1502 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1503 if (!err)
1504 priv->tx_rates[index] = rate;
1505 mutex_unlock(&priv->state_lock);
1506
1507 return err;
1508}
1509
b4e029da
KH		 1510static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1511{
1512 return is_kdump_kernel() ?
1513 MLX5E_MIN_NUM_CHANNELS :
1514 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1515 MLX5E_MAX_NUM_CHANNELS);
1516}
1517
2239185c
SM		 1518static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1519 struct mlx5e_sq_param *param,
1520 struct mlx5e_sq *sq)
1521{
1522 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1523 unsigned int inline_hdr_sz = 0;
1524 int err;
1525 int i;
1526
1527 err = mlx5e_open_sq(c, 0, param, sq);
1528 if (err)
1529 return err;
1530
1531 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1532 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1533 ds_cnt++;
1534 }
1535
1536 /* Pre initialize fixed WQE fields */
1537 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1538 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1539 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1540 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1541 struct mlx5_wqe_data_seg *dseg;
1542
1543 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1544 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1545
1546 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1547 dseg->lkey = sq->mkey_be;
1548 }
1549 return 0;
1550}
1551
f62b8bb8
AV		 1552static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1553 struct mlx5e_channel_param *cparam,
1554 struct mlx5e_channel **cp)
1555{
9908aa29 1556 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1557 struct net_device *netdev = priv->netdev;
cb3c7fd4 1558 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1559 int cpu = mlx5e_get_cpu(priv, ix);
1560 struct mlx5e_channel *c;
507f0c81 1561 struct mlx5e_sq *sq;
f62b8bb8 1562 int err;
507f0c81 1563 int i;
f62b8bb8
AV		 1564
1565 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1566 if (!c)
1567 return -ENOMEM;
1568
1569 c->priv = priv;
1570 c->ix = ix;
1571 c->cpu = cpu;
1572 c->pdev = &priv->mdev->pdev->dev;
1573 c->netdev = priv->netdev;
b50d292b 1574 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1575 c->num_tc = priv->params.num_tc;
d7a0ecab 1576 c->xdp = !!priv->xdp_prog;
f62b8bb8 1577
cb3c7fd4
GR		 1578 if (priv->params.rx_am_enabled)
1579 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1580 else
1581 rx_cq_profile = priv->params.rx_cq_moderation;
1582
5283af89 1583 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1584
f62b8bb8
AV		 1585 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1586
9908aa29 1587 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1588 if (err)
1589 goto err_napi_del;
1590
d3c9bc27
TT		 1591 err = mlx5e_open_tx_cqs(c, cparam);
1592 if (err)
1593 goto err_close_icosq_cq;
1594
f62b8bb8 1595 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1596 rx_cq_profile);
f62b8bb8
AV		 1597 if (err)
1598 goto err_close_tx_cqs;
f62b8bb8 1599
d7a0ecab 1600 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
31871f87 1601 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->rq.xdpsq.cq,
d7a0ecab
SM		 1602 priv->params.tx_cq_moderation) : 0;
1603 if (err)
1604 goto err_close_rx_cq;
1605
f62b8bb8
AV		 1606 napi_enable(&c->napi);
1607
d3c9bc27 1608 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1609 if (err)
1610 goto err_disable_napi;
1611
d3c9bc27
TT		 1612 err = mlx5e_open_sqs(c, cparam);
1613 if (err)
1614 goto err_close_icosq;
1615
507f0c81
YP		 1616 for (i = 0; i < priv->params.num_tc; i++) {
1617 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1618
1619 if (priv->tx_rates[txq_ix]) {
1620 sq = priv->txq_to_sq_map[txq_ix];
1621 mlx5e_set_sq_maxrate(priv->netdev, sq,
1622 priv->tx_rates[txq_ix]);
1623 }
1624 }
1625
2239185c 1626 err = c->xdp ? mlx5e_open_xdpsq(c, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1627 if (err)
1628 goto err_close_sqs;
b5503b99 1629
f62b8bb8
AV		 1630 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1631 if (err)
b5503b99 1632 goto err_close_xdp_sq;
f62b8bb8
AV		 1633
1634 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1635 *cp = c;
1636
1637 return 0;
b5503b99 1638err_close_xdp_sq:
d7a0ecab 1639 if (c->xdp)
31871f87 1640 mlx5e_close_sq(&c->rq.xdpsq);
f62b8bb8
AV		 1641
1642err_close_sqs:
1643 mlx5e_close_sqs(c);
1644
d3c9bc27
TT		 1645err_close_icosq:
1646 mlx5e_close_sq(&c->icosq);
1647
f62b8bb8
AV		 1648err_disable_napi:
1649 napi_disable(&c->napi);
d7a0ecab 1650 if (c->xdp)
31871f87 1651 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1652
1653err_close_rx_cq:
f62b8bb8
AV		 1654 mlx5e_close_cq(&c->rq.cq);
1655
1656err_close_tx_cqs:
1657 mlx5e_close_tx_cqs(c);
1658
d3c9bc27
TT		 1659err_close_icosq_cq:
1660 mlx5e_close_cq(&c->icosq.cq);
1661
f62b8bb8
AV		 1662err_napi_del:
1663 netif_napi_del(&c->napi);
1664 kfree(c);
1665
1666 return err;
1667}
1668
1669static void mlx5e_close_channel(struct mlx5e_channel *c)
1670{
1671 mlx5e_close_rq(&c->rq);
b5503b99 1672 if (c->xdp)
31871f87 1673 mlx5e_close_sq(&c->rq.xdpsq);
f62b8bb8 1674 mlx5e_close_sqs(c);
d3c9bc27 1675 mlx5e_close_sq(&c->icosq);
f62b8bb8 1676 napi_disable(&c->napi);
b5503b99 1677 if (c->xdp)
31871f87 1678 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1679 mlx5e_close_cq(&c->rq.cq);
1680 mlx5e_close_tx_cqs(c);
d3c9bc27 1681 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1682 netif_napi_del(&c->napi);
7ae92ae5 1683
f62b8bb8
AV		 1684 kfree(c);
1685}
1686
1687static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1688 struct mlx5e_rq_param *param)
1689{
1690 void *rqc = param->rqc;
1691 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1692
461017cb
TT		 1693 switch (priv->params.rq_wq_type) {
1694 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1695 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1696 priv->params.mpwqe_log_num_strides - 9);
461017cb 1697 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1698 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1699 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1700 break;
1701 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1702 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1703 }
1704
f62b8bb8
AV		 1705 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1706 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1707 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1708 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1709 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1710
311c7c71 1711 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1712 param->wq.linear = 1;
cb3c7fd4
GR		 1713
1714 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1715}
1716
556dd1b9
TT		 1717static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1718{
1719 void *rqc = param->rqc;
1720 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1721
1722 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1723 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1724}
1725
d3c9bc27
TT		 1726static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1727 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1728{
1729 void *sqc = param->sqc;
1730 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1731
f62b8bb8 1732 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1733 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1734
311c7c71 1735 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1736}
1737
1738static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1739 struct mlx5e_sq_param *param)
1740{
1741 void *sqc = param->sqc;
1742 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1743
1744 mlx5e_build_sq_param_common(priv, param);
1745 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1746
58d52291 1747 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1748 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1749 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1750}
1751
1752static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1753 struct mlx5e_cq_param *param)
1754{
1755 void *cqc = param->cqc;
1756
30aa60b3 1757 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1758}
1759
1760static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1761 struct mlx5e_cq_param *param)
1762{
1763 void *cqc = param->cqc;
461017cb 1764 u8 log_cq_size;
f62b8bb8 1765
461017cb
TT		 1766 switch (priv->params.rq_wq_type) {
1767 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1768 log_cq_size = priv->params.log_rq_size +
d9d9f156 1769 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1770 break;
1771 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1772 log_cq_size = priv->params.log_rq_size;
1773 }
1774
1775 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
9bcc8606 1776 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1777 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1778 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1779 }
f62b8bb8
AV		 1780
1781 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1782
1783 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1784}
1785
1786static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1787 struct mlx5e_cq_param *param)
1788{
1789 void *cqc = param->cqc;
1790
d3c9bc27 1791 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1792
1793 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1794
1795 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1796}
1797
d3c9bc27
TT		 1798static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1799 struct mlx5e_cq_param *param,
1800 u8 log_wq_size)
1801{
1802 void *cqc = param->cqc;
1803
1804 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1805
1806 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1807
1808 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1809}
1810
1811static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1812 struct mlx5e_sq_param *param,
1813 u8 log_wq_size)
1814{
1815 void *sqc = param->sqc;
1816 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1817
1818 mlx5e_build_sq_param_common(priv, param);
1819
1820 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1821 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1822
f10b7cc7 1823 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1824}
1825
b5503b99
SM		 1826static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1827 struct mlx5e_sq_param *param)
1828{
1829 void *sqc = param->sqc;
1830 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1831
1832 mlx5e_build_sq_param_common(priv, param);
1833 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1834
1835 param->max_inline = priv->params.tx_max_inline;
b70149dd 1836 param->min_inline_mode = priv->params.tx_min_inline_mode;
b5503b99
SM		 1837 param->type = MLX5E_SQ_XDP;
1838}
1839
6b87663f 1840static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1841{
bc77b240 1842 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1843
f62b8bb8
AV		 1844 mlx5e_build_rq_param(priv, &cparam->rq);
1845 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1846 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1847 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1848 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1849 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1850 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1851}
1852
1853static int mlx5e_open_channels(struct mlx5e_priv *priv)
1854{
6b87663f 1855 struct mlx5e_channel_param *cparam;
a4418a6c 1856 int nch = priv->params.num_channels;
03289b88 1857 int err = -ENOMEM;
f62b8bb8
AV		 1858 int i;
1859 int j;
1860
a4418a6c
AS		 1861 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1862 GFP_KERNEL);
03289b88 1863
a4418a6c 1864 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1865 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1866
6b87663f
AB		 1867 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1868
1869 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1870 goto err_free_txq_to_sq_map;
f62b8bb8 1871
6b87663f
AB		 1872 mlx5e_build_channel_param(priv, cparam);
1873
a4418a6c 1874 for (i = 0; i < nch; i++) {
6b87663f 1875 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1876 if (err)
1877 goto err_close_channels;
1878 }
1879
a4418a6c 1880 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1881 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1882 if (err)
1883 goto err_close_channels;
1884 }
1885
c3b7c5c9
MHY		 1886 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1887 * polling for inactive tx queues.
1888 */
1889 netif_tx_start_all_queues(priv->netdev);
1890
6b87663f 1891 kfree(cparam);
f62b8bb8
AV		 1892 return 0;
1893
1894err_close_channels:
1895 for (i--; i >= 0; i--)
1896 mlx5e_close_channel(priv->channel[i]);
1897
03289b88
SM		 1898err_free_txq_to_sq_map:
1899 kfree(priv->txq_to_sq_map);
f62b8bb8 1900 kfree(priv->channel);
6b87663f 1901 kfree(cparam);
f62b8bb8
AV		 1902
1903 return err;
1904}
1905
1906static void mlx5e_close_channels(struct mlx5e_priv *priv)
1907{
1908 int i;
1909
c3b7c5c9
MHY		 1910 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1911 * polling for inactive tx queues.
1912 */
1913 netif_tx_stop_all_queues(priv->netdev);
1914 netif_tx_disable(priv->netdev);
1915
f62b8bb8
AV		 1916 for (i = 0; i < priv->params.num_channels; i++)
1917 mlx5e_close_channel(priv->channel[i]);
1918
03289b88 1919 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1920 kfree(priv->channel);
1921}
1922
2be6967c
SM		 1923static int mlx5e_rx_hash_fn(int hfunc)
1924{
1925 return (hfunc == ETH_RSS_HASH_TOP) ?
1926 MLX5_RX_HASH_FN_TOEPLITZ :
1927 MLX5_RX_HASH_FN_INVERTED_XOR8;
1928}
1929
1930static int mlx5e_bits_invert(unsigned long a, int size)
1931{
1932 int inv = 0;
1933 int i;
1934
1935 for (i = 0; i < size; i++)
1936 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1937
1938 return inv;
1939}
1940
936896e9
AS		 1941static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1942{
1943 int i;
1944
1945 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1946 int ix = i;
1da36696 1947 u32 rqn;
936896e9
AS		 1948
1949 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1950 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1951
2d75b2bc 1952 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1953 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1954 priv->channel[ix]->rq.rqn :
1955 priv->drop_rq.rqn;
1956 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1957 }
1958}
1959
1da36696
TT		 1960static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1961 int ix)
4cbeaff5 1962{
1da36696
TT		 1963 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1964 priv->channel[ix]->rq.rqn :
1965 priv->drop_rq.rqn;
4cbeaff5 1966
1da36696 1967 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1968}
1969
398f3351
HHZ		 1970static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1971 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1972{
1973 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1974 void *rqtc;
1975 int inlen;
1976 int err;
1da36696 1977 u32 *in;
f62b8bb8 1978
f62b8bb8
AV		 1979 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1980 in = mlx5_vzalloc(inlen);
1981 if (!in)
1982 return -ENOMEM;
1983
1984 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1985
1986 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1987 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1988
1da36696
TT		 1989 if (sz > 1) /* RSS */
1990 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1991 else
1992 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1993
398f3351
HHZ		 1994 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1995 if (!err)
1996 rqt->enabled = true;
f62b8bb8
AV		 1997
1998 kvfree(in);
1da36696
TT		 1999 return err;
2000}
2001
cb67b832 2002void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2003{
398f3351
HHZ		 2004 rqt->enabled = false;
2005 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2006}
2007
6bfd390b
HHZ		 2008static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
2009{
2010 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2011
2012 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
2013}
2014
cb67b832 2015int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2016{
398f3351 2017 struct mlx5e_rqt *rqt;
1da36696
TT		 2018 int err;
2019 int ix;
2020
6bfd390b 2021 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 2022 rqt = &priv->direct_tir[ix].rqt;
2023 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 2024 if (err)
2025 goto err_destroy_rqts;
2026 }
2027
2028 return 0;
2029
2030err_destroy_rqts:
2031 for (ix--; ix >= 0; ix--)
398f3351 2032 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2033
f62b8bb8
AV		 2034 return err;
2035}
2036
1da36696 2037int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 2038{
2039 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2040 void *rqtc;
2041 int inlen;
1da36696 2042 u32 *in;
5c50368f
AS		 2043 int err;
2044
5c50368f
AS		 2045 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2046 in = mlx5_vzalloc(inlen);
2047 if (!in)
2048 return -ENOMEM;
2049
2050 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2051
2052 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 2053 if (sz > 1) /* RSS */
2054 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2055 else
2056 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 2057
2058 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2059
1da36696 2060 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2061
2062 kvfree(in);
2063
2064 return err;
2065}
2066
40ab6a6e
AS		 2067static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2068{
1da36696
TT		 2069 u32 rqtn;
2070 int ix;
2071
398f3351
HHZ		 2072 if (priv->indir_rqt.enabled) {
2073 rqtn = priv->indir_rqt.rqtn;
2074 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2075 }
2076
1da36696 2077 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 2078 if (!priv->direct_tir[ix].rqt.enabled)
2079 continue;
2080 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 2081 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2082 }
40ab6a6e
AS		 2083}
2084
5c50368f
AS		 2085static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2086{
2087 if (!priv->params.lro_en)
2088 return;
2089
2090#define ROUGH_MAX_L2_L3_HDR_SZ 256
2091
2092 MLX5_SET(tirc, tirc, lro_enable_mask,
2093 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2094 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2095 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2096 (priv->params.lro_wqe_sz -
2097 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 2098 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 2099}
2100
a100ff3e
GP		 2101void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
2102 enum mlx5e_traffic_types tt)
bdfc028d 2103{
a100ff3e
GP		 2104 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2105
2106#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2107 MLX5_HASH_FIELD_SEL_DST_IP)
2108
2109#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2110 MLX5_HASH_FIELD_SEL_DST_IP |\
2111 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2112 MLX5_HASH_FIELD_SEL_L4_DPORT)
2113
2114#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2115 MLX5_HASH_FIELD_SEL_DST_IP |\
2116 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2117
bdfc028d
TT		 2118 MLX5_SET(tirc, tirc, rx_hash_fn,
2119 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2120 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2121 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2122 rx_hash_toeplitz_key);
2123 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2124 rx_hash_toeplitz_key);
2125
2126 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2127 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2128 }
a100ff3e
GP		 2129
2130 switch (tt) {
2131 case MLX5E_TT_IPV4_TCP:
2132 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2133 MLX5_L3_PROT_TYPE_IPV4);
2134 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2135 MLX5_L4_PROT_TYPE_TCP);
2136 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2137 MLX5_HASH_IP_L4PORTS);
2138 break;
2139
2140 case MLX5E_TT_IPV6_TCP:
2141 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2142 MLX5_L3_PROT_TYPE_IPV6);
2143 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2144 MLX5_L4_PROT_TYPE_TCP);
2145 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2146 MLX5_HASH_IP_L4PORTS);
2147 break;
2148
2149 case MLX5E_TT_IPV4_UDP:
2150 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2151 MLX5_L3_PROT_TYPE_IPV4);
2152 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2153 MLX5_L4_PROT_TYPE_UDP);
2154 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2155 MLX5_HASH_IP_L4PORTS);
2156 break;
2157
2158 case MLX5E_TT_IPV6_UDP:
2159 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2160 MLX5_L3_PROT_TYPE_IPV6);
2161 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2162 MLX5_L4_PROT_TYPE_UDP);
2163 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2164 MLX5_HASH_IP_L4PORTS);
2165 break;
2166
2167 case MLX5E_TT_IPV4_IPSEC_AH:
2168 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2169 MLX5_L3_PROT_TYPE_IPV4);
2170 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2171 MLX5_HASH_IP_IPSEC_SPI);
2172 break;
2173
2174 case MLX5E_TT_IPV6_IPSEC_AH:
2175 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2176 MLX5_L3_PROT_TYPE_IPV6);
2177 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2178 MLX5_HASH_IP_IPSEC_SPI);
2179 break;
2180
2181 case MLX5E_TT_IPV4_IPSEC_ESP:
2182 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2183 MLX5_L3_PROT_TYPE_IPV4);
2184 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2185 MLX5_HASH_IP_IPSEC_SPI);
2186 break;
2187
2188 case MLX5E_TT_IPV6_IPSEC_ESP:
2189 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2190 MLX5_L3_PROT_TYPE_IPV6);
2191 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2192 MLX5_HASH_IP_IPSEC_SPI);
2193 break;
2194
2195 case MLX5E_TT_IPV4:
2196 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2197 MLX5_L3_PROT_TYPE_IPV4);
2198 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2199 MLX5_HASH_IP);
2200 break;
2201
2202 case MLX5E_TT_IPV6:
2203 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2204 MLX5_L3_PROT_TYPE_IPV6);
2205 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2206 MLX5_HASH_IP);
2207 break;
2208 default:
2209 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2210 }
bdfc028d
TT		 2211}
2212
ab0394fe 2213static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2214{
2215 struct mlx5_core_dev *mdev = priv->mdev;
2216
2217 void *in;
2218 void *tirc;
2219 int inlen;
2220 int err;
ab0394fe 2221 int tt;
1da36696 2222 int ix;
5c50368f
AS		 2223
2224 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2225 in = mlx5_vzalloc(inlen);
2226 if (!in)
2227 return -ENOMEM;
2228
2229 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2230 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2231
2232 mlx5e_build_tir_ctx_lro(tirc, priv);
2233
1da36696 2234 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2235 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2236 inlen);
ab0394fe 2237 if (err)
1da36696 2238 goto free_in;
ab0394fe 2239 }
5c50368f 2240
6bfd390b 2241 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2242 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2243 in, inlen);
2244 if (err)
2245 goto free_in;
2246 }
2247
2248free_in:
5c50368f
AS		 2249 kvfree(in);
2250
2251 return err;
2252}
2253
cd255eff 2254static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2255{
40ab6a6e 2256 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2257 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2258 int err;
2259
cd255eff 2260 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2261 if (err)
2262 return err;
2263
cd255eff
SM		 2264 /* Update vport context MTU */
2265 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2266 return 0;
2267}
40ab6a6e 2268
cd255eff
SM		 2269static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2270{
2271 struct mlx5_core_dev *mdev = priv->mdev;
2272 u16 hw_mtu = 0;
2273 int err;
40ab6a6e 2274
cd255eff
SM		 2275 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2276 if (err || !hw_mtu) /* fallback to port oper mtu */
2277 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2278
2279 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2280}
2281
2282static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2283{
2284 struct mlx5e_priv *priv = netdev_priv(netdev);
2285 u16 mtu;
2286 int err;
2287
2288 err = mlx5e_set_mtu(priv, netdev->mtu);
2289 if (err)
2290 return err;
40ab6a6e 2291
cd255eff
SM		 2292 mlx5e_query_mtu(priv, &mtu);
2293 if (mtu != netdev->mtu)
2294 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2295 __func__, mtu, netdev->mtu);
40ab6a6e 2296
cd255eff 2297 netdev->mtu = mtu;
40ab6a6e
AS		 2298 return 0;
2299}
2300
08fb1dac
SM		 2301static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2302{
2303 struct mlx5e_priv *priv = netdev_priv(netdev);
2304 int nch = priv->params.num_channels;
2305 int ntc = priv->params.num_tc;
2306 int tc;
2307
2308 netdev_reset_tc(netdev);
2309
2310 if (ntc == 1)
2311 return;
2312
2313 netdev_set_num_tc(netdev, ntc);
2314
7ccdd084
RS		 2315 /* Map netdev TCs to offset 0
2316 * We have our own UP to TXQ mapping for QoS
2317 */
08fb1dac 2318 for (tc = 0; tc < ntc; tc++)
7ccdd084 2319 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2320}
2321
40ab6a6e
AS		 2322int mlx5e_open_locked(struct net_device *netdev)
2323{
2324 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2325 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2326 int num_txqs;
2327 int err;
2328
2329 set_bit(MLX5E_STATE_OPENED, &priv->state);
2330
08fb1dac
SM		 2331 mlx5e_netdev_set_tcs(netdev);
2332
40ab6a6e
AS		 2333 num_txqs = priv->params.num_channels * priv->params.num_tc;
2334 netif_set_real_num_tx_queues(netdev, num_txqs);
2335 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2336
40ab6a6e
AS		 2337 err = mlx5e_open_channels(priv);
2338 if (err) {
2339 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2340 __func__, err);
343b29f3 2341 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2342 }
2343
0952da79 2344 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
66189961
TT		 2345 if (err) {
2346 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2347 __func__, err);
2348 goto err_close_channels;
2349 }
2350
40ab6a6e 2351 mlx5e_redirect_rqts(priv);
ce89ef36 2352 mlx5e_update_carrier(priv);
ef9814de 2353 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2354#ifdef CONFIG_RFS_ACCEL
2355 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2356#endif
cb67b832
HHZ		 2357 if (priv->profile->update_stats)
2358 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2359
cb67b832
HHZ		 2360 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2361 err = mlx5e_add_sqs_fwd_rules(priv);
2362 if (err)
2363 goto err_close_channels;
2364 }
9b37b07f 2365 return 0;
343b29f3 2366
66189961
TT		 2367err_close_channels:
2368 mlx5e_close_channels(priv);
343b29f3
AS		 2369err_clear_state_opened_flag:
2370 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2371 return err;
40ab6a6e
AS		 2372}
2373
cb67b832 2374int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2375{
2376 struct mlx5e_priv *priv = netdev_priv(netdev);
2377 int err;
2378
2379 mutex_lock(&priv->state_lock);
2380 err = mlx5e_open_locked(netdev);
2381 mutex_unlock(&priv->state_lock);
2382
2383 return err;
2384}
2385
2386int mlx5e_close_locked(struct net_device *netdev)
2387{
2388 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2389 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2390
a1985740
AS		 2391 /* May already be CLOSED in case a previous configuration operation
2392 * (e.g RX/TX queue size change) that involves close&open failed.
2393 */
2394 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2395 return 0;
2396
40ab6a6e
AS		 2397 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2398
cb67b832
HHZ		 2399 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2400 mlx5e_remove_sqs_fwd_rules(priv);
2401
ef9814de 2402 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2403 netif_carrier_off(priv->netdev);
ce89ef36 2404 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2405 mlx5e_close_channels(priv);
2406
2407 return 0;
2408}
2409
cb67b832 2410int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2411{
2412 struct mlx5e_priv *priv = netdev_priv(netdev);
2413 int err;
2414
26e59d80
MHY		 2415 if (!netif_device_present(netdev))
2416 return -ENODEV;
2417
40ab6a6e
AS		 2418 mutex_lock(&priv->state_lock);
2419 err = mlx5e_close_locked(netdev);
2420 mutex_unlock(&priv->state_lock);
2421
2422 return err;
2423}
2424
3b77235b
SM		 2425static int mlx5e_alloc_drop_rq(struct mlx5e_priv *priv,
2426 struct mlx5e_rq *rq,
2427 struct mlx5e_rq_param *param)
40ab6a6e
AS		 2428{
2429 struct mlx5_core_dev *mdev = priv->mdev;
2430 void *rqc = param->rqc;
2431 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2432 int err;
2433
2434 param->wq.db_numa_node = param->wq.buf_numa_node;
2435
2436 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2437 &rq->wq_ctrl);
2438 if (err)
2439 return err;
2440
2441 rq->priv = priv;
2442
2443 return 0;
2444}
2445
3b77235b
SM		 2446static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2447 struct mlx5e_cq *cq,
2448 struct mlx5e_cq_param *param)
40ab6a6e
AS		 2449{
2450 struct mlx5_core_dev *mdev = priv->mdev;
2451 struct mlx5_core_cq *mcq = &cq->mcq;
2452 int eqn_not_used;
0b6e26ce 2453 unsigned int irqn;
40ab6a6e
AS		 2454 int err;
2455
2456 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2457 &cq->wq_ctrl);
2458 if (err)
2459 return err;
2460
2461 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2462
2463 mcq->cqe_sz = 64;
2464 mcq->set_ci_db = cq->wq_ctrl.db.db;
2465 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2466 *mcq->set_ci_db = 0;
2467 *mcq->arm_db = 0;
2468 mcq->vector = param->eq_ix;
2469 mcq->comp = mlx5e_completion_event;
2470 mcq->event = mlx5e_cq_error_event;
2471 mcq->irqn = irqn;
40ab6a6e
AS		 2472
2473 cq->priv = priv;
2474
2475 return 0;
2476}
2477
2478static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2479{
2480 struct mlx5e_cq_param cq_param;
2481 struct mlx5e_rq_param rq_param;
2482 struct mlx5e_rq *rq = &priv->drop_rq;
2483 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2484 int err;
2485
2486 memset(&cq_param, 0, sizeof(cq_param));
2487 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2488 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2489
3b77235b 2490 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
40ab6a6e
AS		 2491 if (err)
2492 return err;
2493
3b77235b 2494 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2495 if (err)
3b77235b 2496 goto err_free_cq;
40ab6a6e 2497
3b77235b 2498 err = mlx5e_alloc_drop_rq(priv, rq, &rq_param);
40ab6a6e 2499 if (err)
3b77235b 2500 goto err_destroy_cq;
40ab6a6e 2501
3b77235b 2502 err = mlx5e_create_rq(rq, &rq_param);
40ab6a6e 2503 if (err)
3b77235b 2504 goto err_free_rq;
40ab6a6e
AS		 2505
2506 return 0;
2507
3b77235b
SM		 2508err_free_rq:
2509 mlx5e_free_rq(&priv->drop_rq);
40ab6a6e
AS		 2510
2511err_destroy_cq:
2512 mlx5e_destroy_cq(&priv->drop_rq.cq);
2513
3b77235b
SM		 2514err_free_cq:
2515 mlx5e_free_cq(&priv->drop_rq.cq);
2516
40ab6a6e
AS		 2517 return err;
2518}
2519
2520static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2521{
40ab6a6e 2522 mlx5e_destroy_rq(&priv->drop_rq);
3b77235b 2523 mlx5e_free_rq(&priv->drop_rq);
40ab6a6e 2524 mlx5e_destroy_cq(&priv->drop_rq.cq);
3b77235b 2525 mlx5e_free_cq(&priv->drop_rq.cq);
40ab6a6e
AS		 2526}
2527
2528static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2529{
2530 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2531 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2532 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2533
08fb1dac 2534 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2535 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2536
2537 if (mlx5_lag_is_lacp_owner(mdev))
2538 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2539
40ab6a6e
AS		 2540 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2541}
2542
2543static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2544{
2545 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2546}
2547
cb67b832 2548int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2549{
2550 int err;
2551 int tc;
2552
6bfd390b 2553 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2554 err = mlx5e_create_tis(priv, tc);
2555 if (err)
2556 goto err_close_tises;
2557 }
2558
2559 return 0;
2560
2561err_close_tises:
2562 for (tc--; tc >= 0; tc--)
2563 mlx5e_destroy_tis(priv, tc);
2564
2565 return err;
2566}
2567
cb67b832 2568void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2569{
2570 int tc;
2571
6bfd390b 2572 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2573 mlx5e_destroy_tis(priv, tc);
2574}
2575
1da36696
TT		 2576static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2577 enum mlx5e_traffic_types tt)
f62b8bb8 2578{
b50d292b 2579 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2580
5c50368f 2581 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2582
4cbeaff5 2583 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2584 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
a100ff3e 2585 mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
f62b8bb8
AV		 2586}
2587
1da36696
TT		 2588static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2589 u32 rqtn)
f62b8bb8 2590{
b50d292b 2591 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2592
2593 mlx5e_build_tir_ctx_lro(tirc, priv);
2594
2595 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2596 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2597 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2598}
2599
6bfd390b 2600static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2601{
724b2aa1 2602 struct mlx5e_tir *tir;
f62b8bb8
AV		 2603 void *tirc;
2604 int inlen;
2605 int err;
1da36696 2606 u32 *in;
1da36696 2607 int tt;
f62b8bb8
AV		 2608
2609 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2610 in = mlx5_vzalloc(inlen);
2611 if (!in)
2612 return -ENOMEM;
2613
1da36696
TT		 2614 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2615 memset(in, 0, inlen);
724b2aa1 2616 tir = &priv->indir_tir[tt];
1da36696
TT		 2617 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2618 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2619 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2620 if (err)
40ab6a6e 2621 goto err_destroy_tirs;
f62b8bb8
AV		 2622 }
2623
6bfd390b
HHZ		 2624 kvfree(in);
2625
2626 return 0;
2627
2628err_destroy_tirs:
2629 for (tt--; tt >= 0; tt--)
2630 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2631
2632 kvfree(in);
2633
2634 return err;
2635}
2636
cb67b832 2637int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2638{
2639 int nch = priv->profile->max_nch(priv->mdev);
2640 struct mlx5e_tir *tir;
2641 void *tirc;
2642 int inlen;
2643 int err;
2644 u32 *in;
2645 int ix;
2646
2647 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2648 in = mlx5_vzalloc(inlen);
2649 if (!in)
2650 return -ENOMEM;
2651
1da36696
TT		 2652 for (ix = 0; ix < nch; ix++) {
2653 memset(in, 0, inlen);
724b2aa1 2654 tir = &priv->direct_tir[ix];
1da36696
TT		 2655 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2656 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2657 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2658 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2659 if (err)
2660 goto err_destroy_ch_tirs;
2661 }
2662
2663 kvfree(in);
2664
f62b8bb8
AV		 2665 return 0;
2666
1da36696
TT		 2667err_destroy_ch_tirs:
2668 for (ix--; ix >= 0; ix--)
724b2aa1 2669 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2670
1da36696 2671 kvfree(in);
f62b8bb8
AV		 2672
2673 return err;
2674}
2675
6bfd390b 2676static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2677{
2678 int i;
2679
1da36696 2680 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2681 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2682}
2683
cb67b832 2684void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2685{
2686 int nch = priv->profile->max_nch(priv->mdev);
2687 int i;
2688
2689 for (i = 0; i < nch; i++)
2690 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2691}
2692
36350114
GP		 2693int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2694{
2695 int err = 0;
2696 int i;
2697
2698 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2699 return 0;
2700
2701 for (i = 0; i < priv->params.num_channels; i++) {
2702 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2703 if (err)
2704 return err;
2705 }
2706
2707 return 0;
2708}
2709
08fb1dac
SM		 2710static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2711{
2712 struct mlx5e_priv *priv = netdev_priv(netdev);
2713 bool was_opened;
2714 int err = 0;
2715
2716 if (tc && tc != MLX5E_MAX_NUM_TC)
2717 return -EINVAL;
2718
2719 mutex_lock(&priv->state_lock);
2720
2721 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2722 if (was_opened)
2723 mlx5e_close_locked(priv->netdev);
2724
2725 priv->params.num_tc = tc ? tc : 1;
2726
2727 if (was_opened)
2728 err = mlx5e_open_locked(priv->netdev);
2729
2730 mutex_unlock(&priv->state_lock);
2731
2732 return err;
2733}
2734
2735static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2736 __be16 proto, struct tc_to_netdev *tc)
2737{
e8f887ac
AV		 2738 struct mlx5e_priv *priv = netdev_priv(dev);
2739
2740 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2741 goto mqprio;
2742
2743 switch (tc->type) {
e3a2b7ed
AV		 2744 case TC_SETUP_CLSFLOWER:
2745 switch (tc->cls_flower->command) {
2746 case TC_CLSFLOWER_REPLACE:
2747 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2748 case TC_CLSFLOWER_DESTROY:
2749 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2750 case TC_CLSFLOWER_STATS:
2751 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2752 }
e8f887ac
AV		 2753 default:
2754 return -EOPNOTSUPP;
2755 }
2756
2757mqprio:
67ba422e 2758 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2759 return -EINVAL;
2760
56f36acd
AN		 2761 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2762
2763 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 2764}
2765
bc1f4470 2766static void
f62b8bb8
AV		 2767mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2768{
2769 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2770 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2771 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2772 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2773
370bad0f
OG		 2774 if (mlx5e_is_uplink_rep(priv)) {
2775 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2776 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2777 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2778 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2779 } else {
2780 stats->rx_packets = sstats->rx_packets;
2781 stats->rx_bytes = sstats->rx_bytes;
2782 stats->tx_packets = sstats->tx_packets;
2783 stats->tx_bytes = sstats->tx_bytes;
2784 stats->tx_dropped = sstats->tx_queue_dropped;
2785 }
269e6b3a
GP		 2786
2787 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2788
2789 stats->rx_length_errors =
9218b44d
GP		 2790 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2791 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2792 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2793 stats->rx_crc_errors =
9218b44d
GP		 2794 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2795 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2796 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2797 stats->tx_carrier_errors =
9218b44d 2798 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2799 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2800 stats->rx_frame_errors;
2801 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2802
2803 /* vport multicast also counts packets that are dropped due to steering
2804 * or rx out of buffer
2805 */
9218b44d
GP		 2806 stats->multicast =
2807 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 2808
f62b8bb8
AV		 2809}
2810
2811static void mlx5e_set_rx_mode(struct net_device *dev)
2812{
2813 struct mlx5e_priv *priv = netdev_priv(dev);
2814
7bb29755 2815 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2816}
2817
2818static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2819{
2820 struct mlx5e_priv *priv = netdev_priv(netdev);
2821 struct sockaddr *saddr = addr;
2822
2823 if (!is_valid_ether_addr(saddr->sa_data))
2824 return -EADDRNOTAVAIL;
2825
2826 netif_addr_lock_bh(netdev);
2827 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2828 netif_addr_unlock_bh(netdev);
2829
7bb29755 2830 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2831
2832 return 0;
2833}
2834
0e405443
GP		 2835#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2836 do { \
2837 if (enable) \
2838 netdev->features |= feature; \
2839 else \
2840 netdev->features &= ~feature; \
2841 } while (0)
2842
2843typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2844
2845static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2846{
2847 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2848 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2849 int err;
f62b8bb8
AV		 2850
2851 mutex_lock(&priv->state_lock);
f62b8bb8 2852
0e405443
GP		 2853 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2854 mlx5e_close_locked(priv->netdev);
98e81b0a 2855
0e405443
GP		 2856 priv->params.lro_en = enable;
2857 err = mlx5e_modify_tirs_lro(priv);
2858 if (err) {
2859 netdev_err(netdev, "lro modify failed, %d\n", err);
2860 priv->params.lro_en = !enable;
98e81b0a 2861 }
f62b8bb8 2862
0e405443
GP		 2863 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2864 mlx5e_open_locked(priv->netdev);
2865
9b37b07f
AS		 2866 mutex_unlock(&priv->state_lock);
2867
0e405443
GP		 2868 return err;
2869}
2870
2871static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2872{
2873 struct mlx5e_priv *priv = netdev_priv(netdev);
2874
2875 if (enable)
2876 mlx5e_enable_vlan_filter(priv);
2877 else
2878 mlx5e_disable_vlan_filter(priv);
2879
2880 return 0;
2881}
2882
2883static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2884{
2885 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2886
0e405443 2887 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2888 netdev_err(netdev,
2889 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2890 return -EINVAL;
2891 }
2892
0e405443
GP		 2893 return 0;
2894}
2895
94cb1ebb
EBE		 2896static int set_feature_rx_all(struct net_device *netdev, bool enable)
2897{
2898 struct mlx5e_priv *priv = netdev_priv(netdev);
2899 struct mlx5_core_dev *mdev = priv->mdev;
2900
2901 return mlx5_set_port_fcs(mdev, !enable);
2902}
2903
36350114
GP		 2904static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2905{
2906 struct mlx5e_priv *priv = netdev_priv(netdev);
2907 int err;
2908
2909 mutex_lock(&priv->state_lock);
2910
2911 priv->params.vlan_strip_disable = !enable;
2912 err = mlx5e_modify_rqs_vsd(priv, !enable);
2913 if (err)
2914 priv->params.vlan_strip_disable = enable;
2915
2916 mutex_unlock(&priv->state_lock);
2917
2918 return err;
2919}
2920
45bf454a
MG		 2921#ifdef CONFIG_RFS_ACCEL
2922static int set_feature_arfs(struct net_device *netdev, bool enable)
2923{
2924 struct mlx5e_priv *priv = netdev_priv(netdev);
2925 int err;
2926
2927 if (enable)
2928 err = mlx5e_arfs_enable(priv);
2929 else
2930 err = mlx5e_arfs_disable(priv);
2931
2932 return err;
2933}
2934#endif
2935
0e405443
GP		 2936static int mlx5e_handle_feature(struct net_device *netdev,
2937 netdev_features_t wanted_features,
2938 netdev_features_t feature,
2939 mlx5e_feature_handler feature_handler)
2940{
2941 netdev_features_t changes = wanted_features ^ netdev->features;
2942 bool enable = !!(wanted_features & feature);
2943 int err;
2944
2945 if (!(changes & feature))
2946 return 0;
2947
2948 err = feature_handler(netdev, enable);
2949 if (err) {
2950 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2951 enable ? "Enable" : "Disable", feature, err);
2952 return err;
2953 }
2954
2955 MLX5E_SET_FEATURE(netdev, feature, enable);
2956 return 0;
2957}
2958
2959static int mlx5e_set_features(struct net_device *netdev,
2960 netdev_features_t features)
2961{
2962 int err;
2963
2964 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2965 set_feature_lro);
2966 err |= mlx5e_handle_feature(netdev, features,
2967 NETIF_F_HW_VLAN_CTAG_FILTER,
2968 set_feature_vlan_filter);
2969 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2970 set_feature_tc_num_filters);
94cb1ebb
EBE		 2971 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2972 set_feature_rx_all);
36350114
GP		 2973 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2974 set_feature_rx_vlan);
45bf454a
MG		 2975#ifdef CONFIG_RFS_ACCEL
2976 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2977 set_feature_arfs);
2978#endif
0e405443
GP		 2979
2980 return err ? -EINVAL : 0;
f62b8bb8
AV		 2981}
2982
2983static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2984{
2985 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2986 bool was_opened;
98e81b0a 2987 int err = 0;
506753b0 2988 bool reset;
f62b8bb8 2989
f62b8bb8 2990 mutex_lock(&priv->state_lock);
98e81b0a 2991
506753b0
TT		 2992 reset = !priv->params.lro_en &&
2993 (priv->params.rq_wq_type !=
2994 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2995
98e81b0a 2996 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2997 if (was_opened && reset)
98e81b0a
AS		 2998 mlx5e_close_locked(netdev);
2999
f62b8bb8 3000 netdev->mtu = new_mtu;
13f9bba7 3001 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 3002
506753b0 3003 if (was_opened && reset)
98e81b0a
AS		 3004 err = mlx5e_open_locked(netdev);
3005
f62b8bb8
AV		 3006 mutex_unlock(&priv->state_lock);
3007
3008 return err;
3009}
3010
ef9814de
EBE		 3011static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3012{
3013 switch (cmd) {
3014 case SIOCSHWTSTAMP:
3015 return mlx5e_hwstamp_set(dev, ifr);
3016 case SIOCGHWTSTAMP:
3017 return mlx5e_hwstamp_get(dev, ifr);
3018 default:
3019 return -EOPNOTSUPP;
3020 }
3021}
3022
66e49ded
SM		 3023static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3024{
3025 struct mlx5e_priv *priv = netdev_priv(dev);
3026 struct mlx5_core_dev *mdev = priv->mdev;
3027
3028 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3029}
3030
79aab093
MS		 3031static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3032 __be16 vlan_proto)
66e49ded
SM		 3033{
3034 struct mlx5e_priv *priv = netdev_priv(dev);
3035 struct mlx5_core_dev *mdev = priv->mdev;
3036
79aab093
MS		 3037 if (vlan_proto != htons(ETH_P_8021Q))
3038 return -EPROTONOSUPPORT;
3039
66e49ded
SM		 3040 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3041 vlan, qos);
3042}
3043
f942380c
MHY		 3044static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3045{
3046 struct mlx5e_priv *priv = netdev_priv(dev);
3047 struct mlx5_core_dev *mdev = priv->mdev;
3048
3049 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3050}
3051
1edc57e2
MHY		 3052static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3053{
3054 struct mlx5e_priv *priv = netdev_priv(dev);
3055 struct mlx5_core_dev *mdev = priv->mdev;
3056
3057 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3058}
bd77bf1c
MHY		 3059
3060static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3061 int max_tx_rate)
3062{
3063 struct mlx5e_priv *priv = netdev_priv(dev);
3064 struct mlx5_core_dev *mdev = priv->mdev;
3065
bd77bf1c 3066 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3067 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3068}
3069
66e49ded
SM		 3070static int mlx5_vport_link2ifla(u8 esw_link)
3071{
3072 switch (esw_link) {
3073 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3074 return IFLA_VF_LINK_STATE_DISABLE;
3075 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3076 return IFLA_VF_LINK_STATE_ENABLE;
3077 }
3078 return IFLA_VF_LINK_STATE_AUTO;
3079}
3080
3081static int mlx5_ifla_link2vport(u8 ifla_link)
3082{
3083 switch (ifla_link) {
3084 case IFLA_VF_LINK_STATE_DISABLE:
3085 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3086 case IFLA_VF_LINK_STATE_ENABLE:
3087 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3088 }
3089 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3090}
3091
3092static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3093 int link_state)
3094{
3095 struct mlx5e_priv *priv = netdev_priv(dev);
3096 struct mlx5_core_dev *mdev = priv->mdev;
3097
3098 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3099 mlx5_ifla_link2vport(link_state));
3100}
3101
3102static int mlx5e_get_vf_config(struct net_device *dev,
3103 int vf, struct ifla_vf_info *ivi)
3104{
3105 struct mlx5e_priv *priv = netdev_priv(dev);
3106 struct mlx5_core_dev *mdev = priv->mdev;
3107 int err;
3108
3109 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3110 if (err)
3111 return err;
3112 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3113 return 0;
3114}
3115
3116static int mlx5e_get_vf_stats(struct net_device *dev,
3117 int vf, struct ifla_vf_stats *vf_stats)
3118{
3119 struct mlx5e_priv *priv = netdev_priv(dev);
3120 struct mlx5_core_dev *mdev = priv->mdev;
3121
3122 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3123 vf_stats);
3124}
3125
1ad9a00a
PB		 3126static void mlx5e_add_vxlan_port(struct net_device *netdev,
3127 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3128{
3129 struct mlx5e_priv *priv = netdev_priv(netdev);
3130
974c3f30
AD		 3131 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3132 return;
3133
b3f63c3d
MF		 3134 if (!mlx5e_vxlan_allowed(priv->mdev))
3135 return;
3136
974c3f30 3137 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3138}
3139
1ad9a00a
PB		 3140static void mlx5e_del_vxlan_port(struct net_device *netdev,
3141 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3142{
3143 struct mlx5e_priv *priv = netdev_priv(netdev);
3144
974c3f30
AD		 3145 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3146 return;
3147
b3f63c3d
MF		 3148 if (!mlx5e_vxlan_allowed(priv->mdev))
3149 return;
3150
974c3f30 3151 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3152}
3153
3154static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3155 struct sk_buff *skb,
3156 netdev_features_t features)
3157{
3158 struct udphdr *udph;
3159 u16 proto;
3160 u16 port = 0;
3161
3162 switch (vlan_get_protocol(skb)) {
3163 case htons(ETH_P_IP):
3164 proto = ip_hdr(skb)->protocol;
3165 break;
3166 case htons(ETH_P_IPV6):
3167 proto = ipv6_hdr(skb)->nexthdr;
3168 break;
3169 default:
3170 goto out;
3171 }
3172
3173 if (proto == IPPROTO_UDP) {
3174 udph = udp_hdr(skb);
3175 port = be16_to_cpu(udph->dest);
3176 }
3177
3178 /* Verify if UDP port is being offloaded by HW */
3179 if (port && mlx5e_vxlan_lookup_port(priv, port))
3180 return features;
3181
3182out:
3183 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3184 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3185}
3186
3187static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3188 struct net_device *netdev,
3189 netdev_features_t features)
3190{
3191 struct mlx5e_priv *priv = netdev_priv(netdev);
3192
3193 features = vlan_features_check(skb, features);
3194 features = vxlan_features_check(skb, features);
3195
3196 /* Validate if the tunneled packet is being offloaded by HW */
3197 if (skb->encapsulation &&
3198 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3199 return mlx5e_vxlan_features_check(priv, skb, features);
3200
3201 return features;
3202}
3203
3947ca18
DJ		 3204static void mlx5e_tx_timeout(struct net_device *dev)
3205{
3206 struct mlx5e_priv *priv = netdev_priv(dev);
3207 bool sched_work = false;
3208 int i;
3209
3210 netdev_err(dev, "TX timeout detected\n");
3211
3212 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3213 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3214
2c1ccc99 3215 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3216 continue;
3217 sched_work = true;
c0f1147d 3218 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3219 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3220 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3221 }
3222
3223 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3224 schedule_work(&priv->tx_timeout_work);
3225}
3226
86994156
RS		 3227static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3228{
3229 struct mlx5e_priv *priv = netdev_priv(netdev);
3230 struct bpf_prog *old_prog;
3231 int err = 0;
3232 bool reset, was_opened;
3233 int i;
3234
3235 mutex_lock(&priv->state_lock);
3236
3237 if ((netdev->features & NETIF_F_LRO) && prog) {
3238 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3239 err = -EINVAL;
3240 goto unlock;
3241 }
3242
3243 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3244 /* no need for full reset when exchanging programs */
3245 reset = (!priv->xdp_prog || !prog);
3246
3247 if (was_opened && reset)
3248 mlx5e_close_locked(netdev);
c54c0629
DB		 3249 if (was_opened && !reset) {
3250 /* num_channels is invariant here, so we can take the
3251 * batched reference right upfront.
3252 */
3253 prog = bpf_prog_add(prog, priv->params.num_channels);
3254 if (IS_ERR(prog)) {
3255 err = PTR_ERR(prog);
3256 goto unlock;
3257 }
3258 }
86994156 3259
c54c0629
DB		 3260 /* exchange programs, extra prog reference we got from caller
3261 * as long as we don't fail from this point onwards.
3262 */
86994156 3263 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3264 if (old_prog)
3265 bpf_prog_put(old_prog);
3266
3267 if (reset) /* change RQ type according to priv->xdp_prog */
3268 mlx5e_set_rq_priv_params(priv);
3269
3270 if (was_opened && reset)
3271 mlx5e_open_locked(netdev);
3272
3273 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3274 goto unlock;
3275
3276 /* exchanging programs w/o reset, we update ref counts on behalf
3277 * of the channels RQs here.
3278 */
86994156
RS		 3279 for (i = 0; i < priv->params.num_channels; i++) {
3280 struct mlx5e_channel *c = priv->channel[i];
3281
c0f1147d 3282 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3283 napi_synchronize(&c->napi);
3284 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3285
3286 old_prog = xchg(&c->rq.xdp_prog, prog);
3287
c0f1147d 3288 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3289 /* napi_schedule in case we have missed anything */
3290 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3291 napi_schedule(&c->napi);
3292
3293 if (old_prog)
3294 bpf_prog_put(old_prog);
3295 }
3296
3297unlock:
3298 mutex_unlock(&priv->state_lock);
3299 return err;
3300}
3301
3302static bool mlx5e_xdp_attached(struct net_device *dev)
3303{
3304 struct mlx5e_priv *priv = netdev_priv(dev);
3305
3306 return !!priv->xdp_prog;
3307}
3308
3309static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3310{
3311 switch (xdp->command) {
3312 case XDP_SETUP_PROG:
3313 return mlx5e_xdp_set(dev, xdp->prog);
3314 case XDP_QUERY_PROG:
3315 xdp->prog_attached = mlx5e_xdp_attached(dev);
3316 return 0;
3317 default:
3318 return -EINVAL;
3319 }
3320}
3321
80378384
CO		 3322#ifdef CONFIG_NET_POLL_CONTROLLER
3323/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3324 * reenabling interrupts.
3325 */
3326static void mlx5e_netpoll(struct net_device *dev)
3327{
3328 struct mlx5e_priv *priv = netdev_priv(dev);
3329 int i;
3330
3331 for (i = 0; i < priv->params.num_channels; i++)
3332 napi_schedule(&priv->channel[i]->napi);
3333}
3334#endif
3335
b0eed40e 3336static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3337 .ndo_open = mlx5e_open,
3338 .ndo_stop = mlx5e_close,
3339 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3340 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3341 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3342 .ndo_get_stats64 = mlx5e_get_stats,
3343 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3344 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3345 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3346 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3347 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3348 .ndo_change_mtu = mlx5e_change_mtu,
3349 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3350 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3351#ifdef CONFIG_RFS_ACCEL
3352 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3353#endif
3947ca18 3354 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3355 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3356#ifdef CONFIG_NET_POLL_CONTROLLER
3357 .ndo_poll_controller = mlx5e_netpoll,
3358#endif
b0eed40e
SM		 3359};
3360
3361static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3362 .ndo_open = mlx5e_open,
3363 .ndo_stop = mlx5e_close,
3364 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3365 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3366 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3367 .ndo_get_stats64 = mlx5e_get_stats,
3368 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3369 .ndo_set_mac_address = mlx5e_set_mac,
3370 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3371 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3372 .ndo_set_features = mlx5e_set_features,
3373 .ndo_change_mtu = mlx5e_change_mtu,
3374 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3375 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3376 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3377 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3378 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3379#ifdef CONFIG_RFS_ACCEL
3380 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3381#endif
b0eed40e
SM		 3382 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3383 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3384 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3385 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3386 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3387 .ndo_get_vf_config = mlx5e_get_vf_config,
3388 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3389 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3390 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3391 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3392#ifdef CONFIG_NET_POLL_CONTROLLER
3393 .ndo_poll_controller = mlx5e_netpoll,
3394#endif
370bad0f
OG		 3395 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3396 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3397};
3398
3399static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3400{
3401 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3402 return -EOPNOTSUPP;
f62b8bb8
AV		 3403 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3404 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3405 !MLX5_CAP_ETH(mdev, csum_cap) ||
3406 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3407 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3408 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3409 MLX5_CAP_FLOWTABLE(mdev,
3410 flow_table_properties_nic_receive.max_ft_level)
3411 < 3) {
f62b8bb8
AV		 3412 mlx5_core_warn(mdev,
3413 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3414 return -EOPNOTSUPP;
f62b8bb8 3415 }
66189961
TT		 3416 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3417 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3418 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3419 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3420
f62b8bb8
AV		 3421 return 0;
3422}
3423
58d52291
AS		 3424u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3425{
3426 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3427
3428 return bf_buf_size -
3429 sizeof(struct mlx5e_tx_wqe) +
3430 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3431}
3432
d8c9660d
TT		 3433void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3434 u32 *indirection_rqt, int len,
85082dba
TT		 3435 int num_channels)
3436{
d8c9660d
TT		 3437 int node = mdev->priv.numa_node;
3438 int node_num_of_cores;
85082dba
TT		 3439 int i;
3440
d8c9660d
TT		 3441 if (node == -1)
3442 node = first_online_node;
3443
3444 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3445
3446 if (node_num_of_cores)
3447 num_channels = min_t(int, num_channels, node_num_of_cores);
3448
85082dba
TT		 3449 for (i = 0; i < len; i++)
3450 indirection_rqt[i] = i % num_channels;
3451}
3452
b797a684
SM		 3453static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3454{
3455 enum pcie_link_width width;
3456 enum pci_bus_speed speed;
3457 int err = 0;
3458
3459 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3460 if (err)
3461 return err;
3462
3463 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3464 return -EINVAL;
3465
3466 switch (speed) {
3467 case PCIE_SPEED_2_5GT:
3468 *pci_bw = 2500 * width;
3469 break;
3470 case PCIE_SPEED_5_0GT:
3471 *pci_bw = 5000 * width;
3472 break;
3473 case PCIE_SPEED_8_0GT:
3474 *pci_bw = 8000 * width;
3475 break;
3476 default:
3477 return -EINVAL;
3478 }
3479
3480 return 0;
3481}
3482
3483static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3484{
3485 return (link_speed && pci_bw &&
3486 (pci_bw < 40000) && (pci_bw < link_speed));
3487}
3488
9908aa29
TT		 3489void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3490{
3491 params->rx_cq_period_mode = cq_period_mode;
3492
3493 params->rx_cq_moderation.pkts =
3494 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3495 params->rx_cq_moderation.usec =
3496 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3497
3498 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3499 params->rx_cq_moderation.usec =
3500 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3501}
3502
2b029556
SM		 3503u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3504{
3505 int i;
3506
3507 /* The supported periods are organized in ascending order */
3508 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3509 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3510 break;
3511
3512 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3513}
3514
6bfd390b
HHZ		 3515static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3516 struct net_device *netdev,
127ea380
HHZ		 3517 const struct mlx5e_profile *profile,
3518 void *ppriv)
f62b8bb8
AV		 3519{
3520 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3521 u32 link_speed = 0;
3522 u32 pci_bw = 0;
cb3c7fd4
GR		 3523 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3524 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3525 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3526
2fc4bfb7
SM		 3527 priv->mdev = mdev;
3528 priv->netdev = netdev;
3529 priv->params.num_channels = profile->max_nch(mdev);
3530 priv->profile = profile;
3531 priv->ppriv = ppriv;
3532
2b029556
SM		 3533 priv->params.lro_timeout =
3534 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3535
b4e029da
KH		 3536 priv->params.log_sq_size = is_kdump_kernel() ?
3537 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3538 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3539
b797a684 3540 /* set CQE compression */
9bcc8606 3541 priv->params.rx_cqe_compress_def = false;
b797a684
SM		 3542 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3543 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3544 mlx5e_get_max_linkspeed(mdev, &link_speed);
3545 mlx5e_get_pci_bw(mdev, &pci_bw);
3546 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3547 link_speed, pci_bw);
9bcc8606 3548 priv->params.rx_cqe_compress_def =
b797a684
SM		 3549 cqe_compress_heuristic(link_speed, pci_bw);
3550 }
b797a684 3551
b0d4660b
TT		 3552 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS,
3553 priv->params.rx_cqe_compress_def);
3554
2fc4bfb7
SM		 3555 mlx5e_set_rq_priv_params(priv);
3556 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3557 priv->params.lro_en = true;
9908aa29 3558
cb3c7fd4
GR		 3559 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3560 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3561
3562 priv->params.tx_cq_moderation.usec =
f62b8bb8 3563 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3564 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3565 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3566 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
8c7245a6 3567 mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
a6f402e4
SM		 3568 if (priv->params.tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3569 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3570 priv->params.tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3571
f62b8bb8 3572 priv->params.num_tc = 1;
2be6967c 3573 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3574
57afead5
AS		 3575 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3576 sizeof(priv->params.toeplitz_hash_key));
3577
d8c9660d 3578 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3579 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3580
9908aa29 3581 /* Initialize pflags */
59ece1c9
SD		 3582 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3583 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29 3584
f62b8bb8
AV		 3585 mutex_init(&priv->state_lock);
3586
3587 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3588 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3589 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3590 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3591}
3592
3593static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3594{
3595 struct mlx5e_priv *priv = netdev_priv(netdev);
3596
e1d7d349 3597 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3598 if (is_zero_ether_addr(netdev->dev_addr) &&
3599 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3600 eth_hw_addr_random(netdev);
3601 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3602 }
f62b8bb8
AV		 3603}
3604
cb67b832
HHZ		 3605static const struct switchdev_ops mlx5e_switchdev_ops = {
3606 .switchdev_port_attr_get = mlx5e_attr_get,
3607};
3608
6bfd390b 3609static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3610{
3611 struct mlx5e_priv *priv = netdev_priv(netdev);
3612 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3613 bool fcs_supported;
3614 bool fcs_enabled;
f62b8bb8
AV		 3615
3616 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3617
08fb1dac 3618 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3619 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3620#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3621 if (MLX5_CAP_GEN(mdev, qos))
3622 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3623#endif
3624 } else {
b0eed40e 3625 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3626 }
66e49ded 3627
f62b8bb8
AV		 3628 netdev->watchdog_timeo = 15 * HZ;
3629
3630 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3631
12be4b21 3632 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3633 netdev->vlan_features |= NETIF_F_IP_CSUM;
3634 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3635 netdev->vlan_features |= NETIF_F_GRO;
3636 netdev->vlan_features |= NETIF_F_TSO;
3637 netdev->vlan_features |= NETIF_F_TSO6;
3638 netdev->vlan_features |= NETIF_F_RXCSUM;
3639 netdev->vlan_features |= NETIF_F_RXHASH;
3640
3641 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3642 netdev->vlan_features |= NETIF_F_LRO;
3643
3644 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3645 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3646 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3647 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3648
b3f63c3d 3649 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3650 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3651 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3652 NETIF_F_GSO_PARTIAL;
b3f63c3d 3653 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3654 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3655 netdev->hw_enc_features |= NETIF_F_TSO;
3656 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3657 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3658 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3659 NETIF_F_GSO_PARTIAL;
3660 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3661 }
3662
94cb1ebb
EBE		 3663 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3664
3665 if (fcs_supported)
3666 netdev->hw_features |= NETIF_F_RXALL;
3667
f62b8bb8
AV		 3668 netdev->features = netdev->hw_features;
3669 if (!priv->params.lro_en)
3670 netdev->features &= ~NETIF_F_LRO;
3671
94cb1ebb
EBE		 3672 if (fcs_enabled)
3673 netdev->features &= ~NETIF_F_RXALL;
3674
e8f887ac
AV		 3675#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3676 if (FT_CAP(flow_modify_en) &&
3677 FT_CAP(modify_root) &&
3678 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3679 FT_CAP(flow_table_modify)) {
3680 netdev->hw_features |= NETIF_F_HW_TC;
3681#ifdef CONFIG_RFS_ACCEL
3682 netdev->hw_features |= NETIF_F_NTUPLE;
3683#endif
3684 }
e8f887ac 3685
f62b8bb8
AV		 3686 netdev->features |= NETIF_F_HIGHDMA;
3687
3688 netdev->priv_flags |= IFF_UNICAST_FLT;
3689
3690 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3691
3692#ifdef CONFIG_NET_SWITCHDEV
3693 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3694 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3695#endif
f62b8bb8
AV		 3696}
3697
593cf338
RS		 3698static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3699{
3700 struct mlx5_core_dev *mdev = priv->mdev;
3701 int err;
3702
3703 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3704 if (err) {
3705 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3706 priv->q_counter = 0;
3707 }
3708}
3709
3710static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3711{
3712 if (!priv->q_counter)
3713 return;
3714
3715 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3716}
3717
6bfd390b
HHZ		 3718static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3719 struct net_device *netdev,
127ea380
HHZ		 3720 const struct mlx5e_profile *profile,
3721 void *ppriv)
6bfd390b
HHZ		 3722{
3723 struct mlx5e_priv *priv = netdev_priv(netdev);
3724
127ea380 3725 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3726 mlx5e_build_nic_netdev(netdev);
3727 mlx5e_vxlan_init(priv);
3728}
3729
3730static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3731{
3732 mlx5e_vxlan_cleanup(priv);
127ea380 3733
a055c19b
DB		 3734 if (priv->xdp_prog)
3735 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3736}
3737
3738static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3739{
3740 struct mlx5_core_dev *mdev = priv->mdev;
3741 int err;
3742 int i;
3743
3744 err = mlx5e_create_indirect_rqts(priv);
3745 if (err) {
3746 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3747 return err;
3748 }
3749
3750 err = mlx5e_create_direct_rqts(priv);
3751 if (err) {
3752 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3753 goto err_destroy_indirect_rqts;
3754 }
3755
3756 err = mlx5e_create_indirect_tirs(priv);
3757 if (err) {
3758 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3759 goto err_destroy_direct_rqts;
3760 }
3761
3762 err = mlx5e_create_direct_tirs(priv);
3763 if (err) {
3764 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3765 goto err_destroy_indirect_tirs;
3766 }
3767
3768 err = mlx5e_create_flow_steering(priv);
3769 if (err) {
3770 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3771 goto err_destroy_direct_tirs;
3772 }
3773
3774 err = mlx5e_tc_init(priv);
3775 if (err)
3776 goto err_destroy_flow_steering;
3777
3778 return 0;
3779
3780err_destroy_flow_steering:
3781 mlx5e_destroy_flow_steering(priv);
3782err_destroy_direct_tirs:
3783 mlx5e_destroy_direct_tirs(priv);
3784err_destroy_indirect_tirs:
3785 mlx5e_destroy_indirect_tirs(priv);
3786err_destroy_direct_rqts:
3787 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3788 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3789err_destroy_indirect_rqts:
3790 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3791 return err;
3792}
3793
3794static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3795{
3796 int i;
3797
3798 mlx5e_tc_cleanup(priv);
3799 mlx5e_destroy_flow_steering(priv);
3800 mlx5e_destroy_direct_tirs(priv);
3801 mlx5e_destroy_indirect_tirs(priv);
3802 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3803 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3804 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3805}
3806
3807static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3808{
3809 int err;
3810
3811 err = mlx5e_create_tises(priv);
3812 if (err) {
3813 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3814 return err;
3815 }
3816
3817#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 3818 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 3819#endif
3820 return 0;
3821}
3822
3823static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3824{
3825 struct net_device *netdev = priv->netdev;
3826 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3827 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3828 struct mlx5_eswitch_rep rep;
6bfd390b 3829
7907f23a
AH		 3830 mlx5_lag_add(mdev, netdev);
3831
6bfd390b 3832 mlx5e_enable_async_events(priv);
127ea380
HHZ		 3833
3834 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3835 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3836 rep.load = mlx5e_nic_rep_load;
3837 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3838 rep.vport = FDB_UPLINK_VPORT;
726293f1 3839 rep.netdev = netdev;
9deb2241 3840 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3841 }
610e89e0
SM		 3842
3843 if (netdev->reg_state != NETREG_REGISTERED)
3844 return;
3845
3846 /* Device already registered: sync netdev system state */
3847 if (mlx5e_vxlan_allowed(mdev)) {
3848 rtnl_lock();
3849 udp_tunnel_get_rx_info(netdev);
3850 rtnl_unlock();
3851 }
3852
3853 queue_work(priv->wq, &priv->set_rx_mode_work);
6bfd390b
HHZ		 3854}
3855
3856static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3857{
3deef8ce
SM		 3858 struct mlx5_core_dev *mdev = priv->mdev;
3859 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3860
6bfd390b 3861 queue_work(priv->wq, &priv->set_rx_mode_work);
3deef8ce
SM		 3862 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3863 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 3864 mlx5e_disable_async_events(priv);
3deef8ce 3865 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 3866}
3867
3868static const struct mlx5e_profile mlx5e_nic_profile = {
3869 .init = mlx5e_nic_init,
3870 .cleanup = mlx5e_nic_cleanup,
3871 .init_rx = mlx5e_init_nic_rx,
3872 .cleanup_rx = mlx5e_cleanup_nic_rx,
3873 .init_tx = mlx5e_init_nic_tx,
3874 .cleanup_tx = mlx5e_cleanup_nic_tx,
3875 .enable = mlx5e_nic_enable,
3876 .disable = mlx5e_nic_disable,
3877 .update_stats = mlx5e_update_stats,
3878 .max_nch = mlx5e_get_max_num_channels,
3879 .max_tc = MLX5E_MAX_NUM_TC,
3880};
3881
26e59d80
MHY		 3882struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3883 const struct mlx5e_profile *profile,
3884 void *ppriv)
f62b8bb8 3885{
26e59d80 3886 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3887 struct net_device *netdev;
3888 struct mlx5e_priv *priv;
f62b8bb8 3889
08fb1dac 3890 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3891 nch * profile->max_tc,
08fb1dac 3892 nch);
f62b8bb8
AV		 3893 if (!netdev) {
3894 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3895 return NULL;
3896 }
3897
127ea380 3898 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3899
3900 netif_carrier_off(netdev);
3901
3902 priv = netdev_priv(netdev);
3903
7bb29755
MF		 3904 priv->wq = create_singlethread_workqueue("mlx5e");
3905 if (!priv->wq)
26e59d80
MHY		 3906 goto err_cleanup_nic;
3907
3908 return netdev;
3909
3910err_cleanup_nic:
3911 profile->cleanup(priv);
3912 free_netdev(netdev);
3913
3914 return NULL;
3915}
3916
3917int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3918{
3919 const struct mlx5e_profile *profile;
3920 struct mlx5e_priv *priv;
b80f71f5 3921 u16 max_mtu;
26e59d80
MHY		 3922 int err;
3923
3924 priv = netdev_priv(netdev);
3925 profile = priv->profile;
3926 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3927
6bfd390b
HHZ		 3928 err = profile->init_tx(priv);
3929 if (err)
ec8b9981 3930 goto out;
5c50368f
AS		 3931
3932 err = mlx5e_open_drop_rq(priv);
3933 if (err) {
3934 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3935 goto err_cleanup_tx;
5c50368f
AS		 3936 }
3937
6bfd390b
HHZ		 3938 err = profile->init_rx(priv);
3939 if (err)
5c50368f 3940 goto err_close_drop_rq;
5c50368f 3941
593cf338
RS		 3942 mlx5e_create_q_counter(priv);
3943
33cfaaa8 3944 mlx5e_init_l2_addr(priv);
5c50368f 3945
b80f71f5
JW		 3946 /* MTU range: 68 - hw-specific max */
3947 netdev->min_mtu = ETH_MIN_MTU;
3948 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3949 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3950
13f9bba7
SM		 3951 mlx5e_set_dev_port_mtu(netdev);
3952
6bfd390b
HHZ		 3953 if (profile->enable)
3954 profile->enable(priv);
f62b8bb8 3955
26e59d80
MHY		 3956 rtnl_lock();
3957 if (netif_running(netdev))
3958 mlx5e_open(netdev);
3959 netif_device_attach(netdev);
3960 rtnl_unlock();
f62b8bb8 3961
26e59d80 3962 return 0;
5c50368f
AS		 3963
3964err_close_drop_rq:
3965 mlx5e_close_drop_rq(priv);
3966
6bfd390b
HHZ		 3967err_cleanup_tx:
3968 profile->cleanup_tx(priv);
5c50368f 3969
26e59d80
MHY		 3970out:
3971 return err;
f62b8bb8
AV		 3972}
3973
127ea380
HHZ		 3974static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3975{
3976 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3977 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3978 int vport;
dbe413e3 3979 u8 mac[ETH_ALEN];
127ea380
HHZ		 3980
3981 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3982 return;
3983
dbe413e3
HHZ		 3984 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3985
127ea380
HHZ		 3986 for (vport = 1; vport < total_vfs; vport++) {
3987 struct mlx5_eswitch_rep rep;
3988
cb67b832
HHZ		 3989 rep.load = mlx5e_vport_rep_load;
3990 rep.unload = mlx5e_vport_rep_unload;
127ea380 3991 rep.vport = vport;
dbe413e3 3992 ether_addr_copy(rep.hw_id, mac);
9deb2241 3993 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3994 }
3995}
3996
6f08a22c
SM		 3997static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
3998{
3999 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4000 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4001 int vport;
4002
4003 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4004 return;
4005
4006 for (vport = 1; vport < total_vfs; vport++)
4007 mlx5_eswitch_unregister_vport_rep(esw, vport);
4008}
4009
26e59d80
MHY		 4010void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4011{
4012 struct mlx5e_priv *priv = netdev_priv(netdev);
4013 const struct mlx5e_profile *profile = priv->profile;
4014
4015 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80
MHY		 4016
4017 rtnl_lock();
4018 if (netif_running(netdev))
4019 mlx5e_close(netdev);
4020 netif_device_detach(netdev);
4021 rtnl_unlock();
4022
37f304d1
SM		 4023 if (profile->disable)
4024 profile->disable(priv);
4025 flush_workqueue(priv->wq);
4026
26e59d80
MHY		 4027 mlx5e_destroy_q_counter(priv);
4028 profile->cleanup_rx(priv);
4029 mlx5e_close_drop_rq(priv);
4030 profile->cleanup_tx(priv);
26e59d80
MHY		 4031 cancel_delayed_work_sync(&priv->update_stats_work);
4032}
4033
4034/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4035 * hardware contexts and to connect it to the current netdev.
4036 */
4037static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4038{
4039 struct mlx5e_priv *priv = vpriv;
4040 struct net_device *netdev = priv->netdev;
4041 int err;
4042
4043 if (netif_device_present(netdev))
4044 return 0;
4045
4046 err = mlx5e_create_mdev_resources(mdev);
4047 if (err)
4048 return err;
4049
4050 err = mlx5e_attach_netdev(mdev, netdev);
4051 if (err) {
4052 mlx5e_destroy_mdev_resources(mdev);
4053 return err;
4054 }
4055
6f08a22c 4056 mlx5e_register_vport_rep(mdev);
26e59d80
MHY		 4057 return 0;
4058}
4059
4060static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4061{
4062 struct mlx5e_priv *priv = vpriv;
4063 struct net_device *netdev = priv->netdev;
4064
4065 if (!netif_device_present(netdev))
4066 return;
4067
6f08a22c 4068 mlx5e_unregister_vport_rep(mdev);
26e59d80
MHY		 4069 mlx5e_detach_netdev(mdev, netdev);
4070 mlx5e_destroy_mdev_resources(mdev);
4071}
4072
b50d292b
HHZ		 4073static void *mlx5e_add(struct mlx5_core_dev *mdev)
4074{
127ea380 4075 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4076 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4077 void *ppriv = NULL;
26e59d80
MHY		 4078 void *priv;
4079 int vport;
4080 int err;
4081 struct net_device *netdev;
b50d292b 4082
26e59d80
MHY		 4083 err = mlx5e_check_required_hca_cap(mdev);
4084 if (err)
b50d292b
HHZ		 4085 return NULL;
4086
127ea380
HHZ		 4087 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4088 ppriv = &esw->offloads.vport_reps[0];
4089
26e59d80
MHY		 4090 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4091 if (!netdev) {
4092 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4093 goto err_unregister_reps;
4094 }
4095
4096 priv = netdev_priv(netdev);
4097
4098 err = mlx5e_attach(mdev, priv);
4099 if (err) {
4100 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4101 goto err_destroy_netdev;
4102 }
4103
4104 err = register_netdev(netdev);
4105 if (err) {
4106 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4107 goto err_detach;
b50d292b 4108 }
26e59d80
MHY		 4109
4110 return priv;
4111
4112err_detach:
4113 mlx5e_detach(mdev, priv);
4114
4115err_destroy_netdev:
4116 mlx5e_destroy_netdev(mdev, priv);
4117
4118err_unregister_reps:
4119 for (vport = 1; vport < total_vfs; vport++)
4120 mlx5_eswitch_unregister_vport_rep(esw, vport);
4121
4122 return NULL;
b50d292b
HHZ		 4123}
4124
cb67b832 4125void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4126{
6bfd390b 4127 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4128 struct net_device *netdev = priv->netdev;
4129
7bb29755 4130 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4131 if (profile->cleanup)
4132 profile->cleanup(priv);
26e59d80 4133 free_netdev(netdev);
f62b8bb8
AV		 4134}
4135
b50d292b
HHZ		 4136static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4137{
4138 struct mlx5e_priv *priv = vpriv;
127ea380 4139
5e1e93c7 4140 unregister_netdev(priv->netdev);
26e59d80
MHY		 4141 mlx5e_detach(mdev, vpriv);
4142 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4143}
4144
f62b8bb8
AV		 4145static void *mlx5e_get_netdev(void *vpriv)
4146{
4147 struct mlx5e_priv *priv = vpriv;
4148
4149 return priv->netdev;
4150}
4151
4152static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4153 .add = mlx5e_add,
4154 .remove = mlx5e_remove,
26e59d80
MHY		 4155 .attach = mlx5e_attach,
4156 .detach = mlx5e_detach,
f62b8bb8
AV		 4157 .event = mlx5e_async_event,
4158 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4159 .get_dev = mlx5e_get_netdev,
4160};
4161
4162void mlx5e_init(void)
4163{
665bc539 4164 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4165 mlx5_register_interface(&mlx5e_interface);
4166}
4167
4168void mlx5e_cleanup(void)
4169{
4170 mlx5_unregister_interface(&mlx5e_interface);
4171}
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