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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
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f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
547eede0 42#include "en_accel/ipsec.h"
899a59d3
IT		 43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
b3f63c3d 45#include "vxlan.h"
f62b8bb8
AV		 46
47struct mlx5e_rq_param {
cb3c7fd4
GR		 48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
f62b8bb8
AV		 50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
696a97cf
EE		 81void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 83{
6a9764ef
SM		 84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
2fc4bfb7 87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 88 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
696a97cf
EE		 91 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
6a9764ef
SM		 93 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 95 break;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 97 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
bce2b2bf
TT		 100 params->rq_headroom = params->xdp_prog ?
101 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102 params->rq_headroom += NET_IP_ALIGN;
4078e637
TT		 103
104 /* Extra room needed for build_skb */
bce2b2bf 105 params->lro_wqe_sz -= params->rq_headroom +
4078e637 106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 107 }
2fc4bfb7 108
6a9764ef
SM		 109 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111 BIT(params->log_rq_size),
112 BIT(params->mpwqe_log_stride_sz),
113 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 114}
115
696a97cf
EE		 116static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
117 struct mlx5e_params *params)
2fc4bfb7 118{
6a9764ef 119 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
899a59d3 120 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
2fc4bfb7
SM		 121 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
122 MLX5_WQ_TYPE_LINKED_LIST;
696a97cf 123 mlx5e_init_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 124}
125
f62b8bb8
AV		 126static void mlx5e_update_carrier(struct mlx5e_priv *priv)
127{
128 struct mlx5_core_dev *mdev = priv->mdev;
129 u8 port_state;
130
131 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 132 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
133 0);
f62b8bb8 134
87424ad5
SD		 135 if (port_state == VPORT_STATE_UP) {
136 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 137 netif_carrier_on(priv->netdev);
87424ad5
SD		 138 } else {
139 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 140 netif_carrier_off(priv->netdev);
87424ad5 141 }
f62b8bb8
AV		 142}
143
144static void mlx5e_update_carrier_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 update_carrier_work);
148
149 mutex_lock(&priv->state_lock);
150 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 151 if (priv->profile->update_carrier)
152 priv->profile->update_carrier(priv);
f62b8bb8
AV		 153 mutex_unlock(&priv->state_lock);
154}
155
3947ca18
DJ		 156static void mlx5e_tx_timeout_work(struct work_struct *work)
157{
158 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
159 tx_timeout_work);
160 int err;
161
162 rtnl_lock();
163 mutex_lock(&priv->state_lock);
164 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
165 goto unlock;
166 mlx5e_close_locked(priv->netdev);
167 err = mlx5e_open_locked(priv->netdev);
168 if (err)
169 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
170 err);
171unlock:
172 mutex_unlock(&priv->state_lock);
173 rtnl_unlock();
174}
175
9218b44d 176static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 177{
1510d728 178 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 179 struct mlx5e_rq_stats *rq_stats;
180 struct mlx5e_sq_stats *sq_stats;
f62b8bb8
AV		 181 int i, j;
182
9218b44d 183 memset(s, 0, sizeof(*s));
ff9c852f
SM		 184 for (i = 0; i < priv->channels.num; i++) {
185 struct mlx5e_channel *c = priv->channels.c[i];
186
187 rq_stats = &c->rq.stats;
f62b8bb8 188
faf4478b
GP		 189 s->rx_packets += rq_stats->packets;
190 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 191 s->rx_lro_packets += rq_stats->lro_packets;
192 s->rx_lro_bytes += rq_stats->lro_bytes;
f24686e8 193 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
f62b8bb8 194 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1 195 s->rx_csum_complete += rq_stats->csum_complete;
603e1f5b 196 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
bfe6d8d1 197 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 198 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 199 s->rx_xdp_tx += rq_stats->xdp_tx;
200 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 201 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 202 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 203 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 204 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
205 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
accd5883 206 s->rx_page_reuse += rq_stats->page_reuse;
4415a031
TT		 207 s->rx_cache_reuse += rq_stats->cache_reuse;
208 s->rx_cache_full += rq_stats->cache_full;
209 s->rx_cache_empty += rq_stats->cache_empty;
210 s->rx_cache_busy += rq_stats->cache_busy;
70871f1e 211 s->rx_cache_waive += rq_stats->cache_waive;
f62b8bb8 212
6a9764ef 213 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 214 sq_stats = &c->sq[j].stats;
f62b8bb8 215
faf4478b
GP		 216 s->tx_packets += sq_stats->packets;
217 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 218 s->tx_tso_packets += sq_stats->tso_packets;
219 s->tx_tso_bytes += sq_stats->tso_bytes;
220 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
221 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f24686e8 222 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
f62b8bb8
AV		 223 s->tx_queue_stopped += sq_stats->stopped;
224 s->tx_queue_wake += sq_stats->wake;
225 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 226 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1 227 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
603e1f5b
GP		 228 s->tx_csum_none += sq_stats->csum_none;
229 s->tx_csum_partial += sq_stats->csum_partial;
f62b8bb8
AV		 230 }
231 }
232
bfe6d8d1 233 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 234 priv->stats.pport.phy_counters,
235 counter_set.phys_layer_cntrs.link_down_events);
1510d728 236 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 237}
238
239static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
240{
241 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
242 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 243 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 244 struct mlx5_core_dev *mdev = priv->mdev;
245
f62b8bb8
AV		 246 MLX5_SET(query_vport_counter_in, in, opcode,
247 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
248 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
249 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
250
9218b44d
GP		 251 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
252}
253
3834a5e6 254static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
9218b44d
GP		 255{
256 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
257 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 258 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
9218b44d 259 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 260 int prio;
9218b44d 261 void *out;
f62b8bb8 262
9218b44d 263 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->IEEE_802_3_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 268
3834a5e6
GP		 269 if (!full)
270 return;
271
9218b44d
GP		 272 out = pstats->RFC_2863_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275
276 out = pstats->RFC_2819_counters;
277 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
278 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 279
121fcdc8
GP		 280 out = pstats->phy_counters;
281 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
282 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
283
5db0a4f6
GP		 284 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
285 out = pstats->phy_statistical_counters;
286 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
287 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
288 }
289
068aef33
GP		 290 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
291 out = pstats->eth_ext_counters;
292 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
5db0a4f6
GP		 293 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
294 }
295
cf678570
GP		 296 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
297 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
298 out = pstats->per_prio_counters[prio];
299 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
300 mlx5_core_access_reg(mdev, in, sz, out, sz,
301 MLX5_REG_PPCNT, 0, 0);
302 }
9218b44d
GP		 303}
304
305static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
306{
307 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
432609a4
GP		 308 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
309 int err;
9218b44d
GP		 310
311 if (!priv->q_counter)
312 return;
313
432609a4
GP		 314 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
315 if (err)
316 return;
317
318 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
9218b44d
GP		 319}
320
0f7f3481
GP		 321static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
322{
323 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
324 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 325 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
0f7f3481
GP		 326 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
327 void *out;
0f7f3481
GP		 328
329 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
330 return;
331
0f7f3481
GP		 332 out = pcie_stats->pcie_perf_counters;
333 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
334 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
0f7f3481
GP		 335}
336
3834a5e6 337void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
9218b44d 338{
164f16f7 339 if (full) {
3834a5e6 340 mlx5e_update_pcie_counters(priv);
164f16f7
IT		 341 mlx5e_ipsec_update_stats(priv);
342 }
3834a5e6 343 mlx5e_update_pport_counters(priv, full);
3dd69e3d
SM		 344 mlx5e_update_vport_counters(priv);
345 mlx5e_update_q_counter(priv);
121fcdc8 346 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 347}
348
3834a5e6
GP		 349static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
350{
351 mlx5e_update_stats(priv, false);
352}
353
cb67b832 354void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 355{
356 struct delayed_work *dwork = to_delayed_work(work);
357 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
358 update_stats_work);
359 mutex_lock(&priv->state_lock);
360 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 361 priv->profile->update_stats(priv);
7bb29755
MF		 362 queue_delayed_work(priv->wq, dwork,
363 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 364 }
365 mutex_unlock(&priv->state_lock);
366}
367
daa21560
TT		 368static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
369 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 370{
daa21560
TT		 371 struct mlx5e_priv *priv = vpriv;
372
e0f46eb9 373 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 374 return;
375
f62b8bb8
AV		 376 switch (event) {
377 case MLX5_DEV_EVENT_PORT_UP:
378 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 379 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 380 break;
f62b8bb8
AV		 381 default:
382 break;
383 }
384}
385
f62b8bb8
AV		 386static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
387{
e0f46eb9 388 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 389}
390
391static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
392{
e0f46eb9 393 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 394 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 395}
396
7e426671
TT		 397static inline int mlx5e_get_wqe_mtt_sz(void)
398{
399 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
400 * To avoid copying garbage after the mtt array, we allocate
401 * a little more.
402 */
403 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
404 MLX5_UMR_MTT_ALIGNMENT);
405}
406
31391048
SM		 407static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
408 struct mlx5e_icosq *sq,
409 struct mlx5e_umr_wqe *wqe,
410 u16 ix)
7e426671
TT		 411{
412 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
413 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
414 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 415 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 416 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
417 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
418
419 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
420 ds_cnt);
421 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
422 cseg->imm = rq->mkey_be;
423
424 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 425 ucseg->xlt_octowords =
7e426671
TT		 426 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
427 ucseg->bsf_octowords =
428 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
429 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
430
431 dseg->lkey = sq->mkey_be;
432 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
433}
434
435static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
436 struct mlx5e_channel *c)
437{
438 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
439 int mtt_sz = mlx5e_get_wqe_mtt_sz();
440 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
441 int i;
442
21c59685 443 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
231243c8 444 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 445 if (!rq->mpwqe.info)
7e426671
TT		 446 goto err_out;
447
448 /* We allocate more than mtt_sz as we will align the pointer */
231243c8
SM		 449 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
450 cpu_to_node(c->cpu));
21c59685 451 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 452 goto err_free_wqe_info;
453
454 for (i = 0; i < wq_sz; i++) {
21c59685 455 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 456
21c59685 457 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 458 MLX5_UMR_ALIGN);
459 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
460 PCI_DMA_TODEVICE);
461 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
462 goto err_unmap_mtts;
463
464 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
465 }
466
467 return 0;
468
469err_unmap_mtts:
470 while (--i >= 0) {
21c59685 471 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 472
473 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
474 PCI_DMA_TODEVICE);
475 }
21c59685 476 kfree(rq->mpwqe.mtt_no_align);
7e426671 477err_free_wqe_info:
21c59685 478 kfree(rq->mpwqe.info);
7e426671
TT		 479
480err_out:
481 return -ENOMEM;
482}
483
484static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
485{
486 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
487 int mtt_sz = mlx5e_get_wqe_mtt_sz();
488 int i;
489
490 for (i = 0; i < wq_sz; i++) {
21c59685 491 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 492
493 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
494 PCI_DMA_TODEVICE);
495 }
21c59685
SM		 496 kfree(rq->mpwqe.mtt_no_align);
497 kfree(rq->mpwqe.info);
7e426671
TT		 498}
499
a43b25da 500static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 501 u64 npages, u8 page_shift,
502 struct mlx5_core_mkey *umr_mkey)
3608ae77 503{
3608ae77
TT		 504 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
505 void *mkc;
506 u32 *in;
507 int err;
508
ec8b9981
TT		 509 if (!MLX5E_VALID_NUM_MTTS(npages))
510 return -EINVAL;
511
1b9a07ee 512 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 513 if (!in)
514 return -ENOMEM;
515
516 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
517
3608ae77
TT		 518 MLX5_SET(mkc, mkc, free, 1);
519 MLX5_SET(mkc, mkc, umr_en, 1);
520 MLX5_SET(mkc, mkc, lw, 1);
521 MLX5_SET(mkc, mkc, lr, 1);
522 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
523
524 MLX5_SET(mkc, mkc, qpn, 0xffffff);
525 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 526 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 527 MLX5_SET(mkc, mkc, translations_octword_size,
528 MLX5_MTT_OCTW(npages));
ec8b9981 529 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 530
ec8b9981 531 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 532
533 kvfree(in);
534 return err;
535}
536
a43b25da 537static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 538{
6a9764ef 539 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 540
a43b25da 541 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 542}
543
3b77235b 544static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 545 struct mlx5e_params *params,
546 struct mlx5e_rq_param *rqp,
3b77235b 547 struct mlx5e_rq *rq)
f62b8bb8 548{
a43b25da 549 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 550 void *rqc = rqp->rqc;
f62b8bb8 551 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 552 u32 byte_count;
1bfecfca 553 int npages;
f62b8bb8
AV		 554 int wq_sz;
555 int err;
556 int i;
557
231243c8 558 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 559
6a9764ef 560 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 561 &rq->wq_ctrl);
562 if (err)
563 return err;
564
565 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
566
567 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 568
6a9764ef 569 rq->wq_type = params->rq_wq_type;
7e426671
TT		 570 rq->pdev = c->pdev;
571 rq->netdev = c->netdev;
a43b25da 572 rq->tstamp = c->tstamp;
7c39afb3 573 rq->clock = &mdev->clock;
7e426671
TT		 574 rq->channel = c;
575 rq->ix = c->ix;
a43b25da 576 rq->mdev = mdev;
97bc402d 577
6a9764ef 578 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 579 if (IS_ERR(rq->xdp_prog)) {
580 err = PTR_ERR(rq->xdp_prog);
581 rq->xdp_prog = NULL;
582 goto err_rq_wq_destroy;
583 }
7e426671 584
e213f5b6
WY		 585 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
586 if (err < 0)
0ddf5432
JDB		 587 goto err_rq_wq_destroy;
588
bce2b2bf 589 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
b45d8b50 590 rq->buff.headroom = params->rq_headroom;
b5503b99 591
6a9764ef 592 switch (rq->wq_type) {
461017cb 593 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 594
7cc6d77b 595 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 596 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 597
20fd0c19 598 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 599#ifdef CONFIG_MLX5_EN_IPSEC
600 if (MLX5_IPSEC_DEV(mdev)) {
601 err = -EINVAL;
602 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
603 goto err_rq_wq_destroy;
604 }
605#endif
20fd0c19
SM		 606 if (!rq->handle_rx_cqe) {
607 err = -EINVAL;
608 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
609 goto err_rq_wq_destroy;
610 }
611
89e89f7a 612 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
b45d8b50 613 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca 614
b681c481 615 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
ec8b9981 616
a43b25da 617 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 618 if (err)
619 goto err_rq_wq_destroy;
ec8b9981
TT		 620 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
621
622 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
623 if (err)
624 goto err_destroy_umr_mkey;
461017cb
TT		 625 break;
626 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883
TT		 627 rq->wqe.frag_info =
628 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
231243c8 629 GFP_KERNEL, cpu_to_node(c->cpu));
accd5883 630 if (!rq->wqe.frag_info) {
461017cb
TT		 631 err = -ENOMEM;
632 goto err_rq_wq_destroy;
633 }
7cc6d77b 634 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 635 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 636
899a59d3
IT		 637#ifdef CONFIG_MLX5_EN_IPSEC
638 if (c->priv->ipsec)
639 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
640 else
641#endif
642 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 643 if (!rq->handle_rx_cqe) {
accd5883 644 kfree(rq->wqe.frag_info);
20fd0c19
SM		 645 err = -EINVAL;
646 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
647 goto err_rq_wq_destroy;
648 }
649
b681c481 650 byte_count = params->lro_en ?
6a9764ef 651 params->lro_wqe_sz :
c139dbfd 652 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
899a59d3
IT		 653#ifdef CONFIG_MLX5_EN_IPSEC
654 if (MLX5_IPSEC_DEV(mdev))
b681c481 655 byte_count += MLX5E_METADATA_ETHER_LEN;
899a59d3 656#endif
accd5883 657 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
1bfecfca
SM		 658
659 /* calc the required page order */
b45d8b50 660 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
accd5883 661 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
1bfecfca
SM		 662 rq->buff.page_order = order_base_2(npages);
663
461017cb 664 byte_count |= MLX5_HW_START_PADDING;
7e426671 665 rq->mkey_be = c->mkey_be;
461017cb 666 }
f62b8bb8
AV		 667
668 for (i = 0; i < wq_sz; i++) {
669 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
670
4c2af5cc
TT		 671 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
672 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
673
674 wqe->data.addr = cpu_to_be64(dma_offset);
675 }
676
461017cb 677 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 678 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 679 }
680
9a317425
AG		 681 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
682
683 switch (params->rx_cq_moderation.cq_period_mode) {
684 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
685 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
686 break;
687 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
688 default:
689 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
690 }
691
4415a031
TT		 692 rq->page_cache.head = 0;
693 rq->page_cache.tail = 0;
694
f62b8bb8
AV		 695 return 0;
696
ec8b9981
TT		 697err_destroy_umr_mkey:
698 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
699
f62b8bb8 700err_rq_wq_destroy:
97bc402d
DB		 701 if (rq->xdp_prog)
702 bpf_prog_put(rq->xdp_prog);
0ddf5432 703 xdp_rxq_info_unreg(&rq->xdp_rxq);
f62b8bb8
AV		 704 mlx5_wq_destroy(&rq->wq_ctrl);
705
706 return err;
707}
708
3b77235b 709static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 710{
4415a031
TT		 711 int i;
712
86994156
RS		 713 if (rq->xdp_prog)
714 bpf_prog_put(rq->xdp_prog);
715
0ddf5432
JDB		 716 xdp_rxq_info_unreg(&rq->xdp_rxq);
717
461017cb
TT		 718 switch (rq->wq_type) {
719 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 720 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 721 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 722 break;
723 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883 724 kfree(rq->wqe.frag_info);
461017cb
TT		 725 }
726
4415a031
TT		 727 for (i = rq->page_cache.head; i != rq->page_cache.tail;
728 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
729 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
730
731 mlx5e_page_release(rq, dma_info, false);
732 }
f62b8bb8
AV		 733 mlx5_wq_destroy(&rq->wq_ctrl);
734}
735
6a9764ef
SM		 736static int mlx5e_create_rq(struct mlx5e_rq *rq,
737 struct mlx5e_rq_param *param)
f62b8bb8 738{
a43b25da 739 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 740
741 void *in;
742 void *rqc;
743 void *wq;
744 int inlen;
745 int err;
746
747 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
748 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 749 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 750 if (!in)
751 return -ENOMEM;
752
753 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
754 wq = MLX5_ADDR_OF(rqc, rqc, wq);
755
756 memcpy(rqc, param->rqc, sizeof(param->rqc));
757
97de9f31 758 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 759 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 760 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 761 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 762 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
763
764 mlx5_fill_page_array(&rq->wq_ctrl.buf,
765 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
766
7db22ffb 767 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 768
769 kvfree(in);
770
771 return err;
772}
773
36350114
GP		 774static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
775 int next_state)
f62b8bb8
AV		 776{
777 struct mlx5e_channel *c = rq->channel;
a43b25da 778 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 779
780 void *in;
781 void *rqc;
782 int inlen;
783 int err;
784
785 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 786 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 787 if (!in)
788 return -ENOMEM;
789
790 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
791
792 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
793 MLX5_SET(rqc, rqc, state, next_state);
794
7db22ffb 795 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 796
797 kvfree(in);
798
799 return err;
800}
801
102722fc
GE		 802static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
803{
804 struct mlx5e_channel *c = rq->channel;
805 struct mlx5e_priv *priv = c->priv;
806 struct mlx5_core_dev *mdev = priv->mdev;
807
808 void *in;
809 void *rqc;
810 int inlen;
811 int err;
812
813 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 814 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 815 if (!in)
816 return -ENOMEM;
817
818 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
819
820 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
821 MLX5_SET64(modify_rq_in, in, modify_bitmask,
822 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
823 MLX5_SET(rqc, rqc, scatter_fcs, enable);
824 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
825
826 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
827
828 kvfree(in);
829
830 return err;
831}
832
36350114
GP		 833static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
834{
835 struct mlx5e_channel *c = rq->channel;
a43b25da 836 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 837 void *in;
838 void *rqc;
839 int inlen;
840 int err;
841
842 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 843 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 844 if (!in)
845 return -ENOMEM;
846
847 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
848
849 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 850 MLX5_SET64(modify_rq_in, in, modify_bitmask,
851 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 852 MLX5_SET(rqc, rqc, vsd, vsd);
853 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
854
855 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
856
857 kvfree(in);
858
859 return err;
860}
861
3b77235b 862static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 863{
a43b25da 864 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 865}
866
867static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
868{
01c196a2 869 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 870 struct mlx5e_channel *c = rq->channel;
a43b25da 871
f62b8bb8 872 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 873 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 874
01c196a2 875 while (time_before(jiffies, exp_time)) {
6a9764ef 876 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 877 return 0;
878
879 msleep(20);
880 }
881
a43b25da 882 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 883 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 884 return -ETIMEDOUT;
885}
886
f2fde18c
SM		 887static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
888{
889 struct mlx5_wq_ll *wq = &rq->wq;
890 struct mlx5e_rx_wqe *wqe;
891 __be16 wqe_ix_be;
892 u16 wqe_ix;
893
8484f9ed 894 /* UMR WQE (if in progress) is always at wq->head */
a071cb9f
TT		 895 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
896 rq->mpwqe.umr_in_progress)
21c59685 897 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 898
f2fde18c
SM		 899 while (!mlx5_wq_ll_is_empty(wq)) {
900 wqe_ix_be = *wq->tail_next;
901 wqe_ix = be16_to_cpu(wqe_ix_be);
902 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
903 rq->dealloc_wqe(rq, wqe_ix);
904 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
905 &wqe->next.next_wqe_index);
906 }
accd5883
TT		 907
908 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
909 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
910 * but yet to be re-posted.
911 */
912 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
913
914 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
915 rq->dealloc_wqe(rq, wqe_ix);
916 }
f2fde18c
SM		 917}
918
f62b8bb8 919static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 920 struct mlx5e_params *params,
f62b8bb8
AV		 921 struct mlx5e_rq_param *param,
922 struct mlx5e_rq *rq)
923{
924 int err;
925
6a9764ef 926 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 927 if (err)
928 return err;
929
3b77235b 930 err = mlx5e_create_rq(rq, param);
f62b8bb8 931 if (err)
3b77235b 932 goto err_free_rq;
f62b8bb8 933
36350114 934 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 935 if (err)
3b77235b 936 goto err_destroy_rq;
f62b8bb8 937
9a317425 938 if (params->rx_dim_enabled)
a1eaba4c 939 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
cb3c7fd4 940
f62b8bb8
AV		 941 return 0;
942
f62b8bb8
AV		 943err_destroy_rq:
944 mlx5e_destroy_rq(rq);
3b77235b
SM		 945err_free_rq:
946 mlx5e_free_rq(rq);
f62b8bb8
AV		 947
948 return err;
949}
950
acc6c595
SM		 951static void mlx5e_activate_rq(struct mlx5e_rq *rq)
952{
953 struct mlx5e_icosq *sq = &rq->channel->icosq;
954 u16 pi = sq->pc & sq->wq.sz_m1;
955 struct mlx5e_tx_wqe *nopwqe;
956
957 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
958 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
acc6c595
SM		 959 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
960 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
961}
962
963static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 964{
c0f1147d 965 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 966 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 967}
cb3c7fd4 968
acc6c595
SM		 969static void mlx5e_close_rq(struct mlx5e_rq *rq)
970{
9a317425 971 cancel_work_sync(&rq->dim.work);
f62b8bb8 972 mlx5e_destroy_rq(rq);
3b77235b
SM		 973 mlx5e_free_rx_descs(rq);
974 mlx5e_free_rq(rq);
f62b8bb8
AV		 975}
976
31391048 977static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 978{
31391048 979 kfree(sq->db.di);
b5503b99
SM		 980}
981
31391048 982static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 983{
984 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
985
31391048 986 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 987 GFP_KERNEL, numa);
31391048
SM		 988 if (!sq->db.di) {
989 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 990 return -ENOMEM;
991 }
992
993 return 0;
994}
995
31391048 996static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 997 struct mlx5e_params *params,
31391048
SM		 998 struct mlx5e_sq_param *param,
999 struct mlx5e_xdpsq *sq)
1000{
1001 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1002 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 1003 int err;
1004
1005 sq->pdev = c->pdev;
1006 sq->mkey_be = c->mkey_be;
1007 sq->channel = c;
1008 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1009 sq->min_inline_mode = params->tx_min_inline_mode;
31391048 1010
231243c8 1011 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 1012 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1013 if (err)
1014 return err;
1015 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1016
231243c8 1017 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1018 if (err)
1019 goto err_sq_wq_destroy;
1020
1021 return 0;
1022
1023err_sq_wq_destroy:
1024 mlx5_wq_destroy(&sq->wq_ctrl);
1025
1026 return err;
1027}
1028
1029static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1030{
1031 mlx5e_free_xdpsq_db(sq);
1032 mlx5_wq_destroy(&sq->wq_ctrl);
1033}
1034
1035static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1036{
f10b7cc7 1037 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 1038}
1039
31391048 1040static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1041{
1042 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1043
1044 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1045 GFP_KERNEL, numa);
1046 if (!sq->db.ico_wqe)
1047 return -ENOMEM;
1048
1049 return 0;
1050}
1051
31391048 1052static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1053 struct mlx5e_sq_param *param,
1054 struct mlx5e_icosq *sq)
f10b7cc7 1055{
31391048 1056 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1057 struct mlx5_core_dev *mdev = c->mdev;
31391048 1058 int err;
f10b7cc7 1059
31391048
SM		 1060 sq->mkey_be = c->mkey_be;
1061 sq->channel = c;
1062 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1063
231243c8 1064 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 1065 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1066 if (err)
1067 return err;
1068 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1069
231243c8 1070 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1071 if (err)
1072 goto err_sq_wq_destroy;
1073
1074 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1075
1076 return 0;
31391048
SM		 1077
1078err_sq_wq_destroy:
1079 mlx5_wq_destroy(&sq->wq_ctrl);
1080
1081 return err;
f62b8bb8
AV		 1082}
1083
31391048 1084static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1085{
31391048
SM		 1086 mlx5e_free_icosq_db(sq);
1087 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1088}
1089
31391048 1090static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1091{
31391048
SM		 1092 kfree(sq->db.wqe_info);
1093 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1094}
1095
31391048 1096static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1097{
31391048
SM		 1098 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1099 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1100
31391048
SM		 1101 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1102 GFP_KERNEL, numa);
1103 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1104 GFP_KERNEL, numa);
77bdf895 1105 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1106 mlx5e_free_txqsq_db(sq);
1107 return -ENOMEM;
b5503b99 1108 }
31391048
SM		 1109
1110 sq->dma_fifo_mask = df_sz - 1;
1111
1112 return 0;
b5503b99
SM		 1113}
1114
31391048 1115static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1116 int txq_ix,
6a9764ef 1117 struct mlx5e_params *params,
31391048
SM		 1118 struct mlx5e_sq_param *param,
1119 struct mlx5e_txqsq *sq)
f62b8bb8 1120{
31391048 1121 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1122 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1123 int err;
1124
f10b7cc7 1125 sq->pdev = c->pdev;
a43b25da 1126 sq->tstamp = c->tstamp;
7c39afb3 1127 sq->clock = &mdev->clock;
f10b7cc7
SM		 1128 sq->mkey_be = c->mkey_be;
1129 sq->channel = c;
acc6c595 1130 sq->txq_ix = txq_ix;
aff26157 1131 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1132 sq->max_inline = params->tx_max_inline;
1133 sq->min_inline_mode = params->tx_min_inline_mode;
2ac9cfe7
IT		 1134 if (MLX5_IPSEC_DEV(c->priv->mdev))
1135 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
f10b7cc7 1136
231243c8 1137 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1138 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1139 if (err)
aff26157 1140 return err;
31391048 1141 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1142
231243c8 1143 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1144 if (err)
f62b8bb8
AV		 1145 goto err_sq_wq_destroy;
1146
31391048 1147 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1148
1149 return 0;
1150
1151err_sq_wq_destroy:
1152 mlx5_wq_destroy(&sq->wq_ctrl);
1153
f62b8bb8
AV		 1154 return err;
1155}
1156
31391048 1157static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1158{
31391048 1159 mlx5e_free_txqsq_db(sq);
f62b8bb8 1160 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1161}
1162
33ad9711
SM		 1163struct mlx5e_create_sq_param {
1164 struct mlx5_wq_ctrl *wq_ctrl;
1165 u32 cqn;
1166 u32 tisn;
1167 u8 tis_lst_sz;
1168 u8 min_inline_mode;
1169};
1170
a43b25da 1171static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1172 struct mlx5e_sq_param *param,
1173 struct mlx5e_create_sq_param *csp,
1174 u32 *sqn)
f62b8bb8 1175{
f62b8bb8
AV		 1176 void *in;
1177 void *sqc;
1178 void *wq;
1179 int inlen;
1180 int err;
1181
1182 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1183 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1184 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1185 if (!in)
1186 return -ENOMEM;
1187
1188 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1189 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1190
1191 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1192 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1193 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1194 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1195
1196 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1197 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1198
33ad9711 1199 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1200
1201 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1202 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1203 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1204 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1205 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1206
33ad9711 1207 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1208
33ad9711 1209 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1210
1211 kvfree(in);
1212
1213 return err;
1214}
1215
33ad9711
SM		 1216struct mlx5e_modify_sq_param {
1217 int curr_state;
1218 int next_state;
1219 bool rl_update;
1220 int rl_index;
1221};
1222
a43b25da 1223static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1224 struct mlx5e_modify_sq_param *p)
f62b8bb8 1225{
f62b8bb8
AV		 1226 void *in;
1227 void *sqc;
1228 int inlen;
1229 int err;
1230
1231 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1232 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1233 if (!in)
1234 return -ENOMEM;
1235
1236 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1237
33ad9711
SM		 1238 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1239 MLX5_SET(sqc, sqc, state, p->next_state);
1240 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1241 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1242 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1243 }
f62b8bb8 1244
33ad9711 1245 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1246
1247 kvfree(in);
1248
1249 return err;
1250}
1251
a43b25da 1252static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1253{
a43b25da 1254 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1255}
1256
a43b25da 1257static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1258 struct mlx5e_sq_param *param,
1259 struct mlx5e_create_sq_param *csp,
1260 u32 *sqn)
f62b8bb8 1261{
33ad9711 1262 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1263 int err;
1264
a43b25da 1265 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1266 if (err)
1267 return err;
1268
1269 msp.curr_state = MLX5_SQC_STATE_RST;
1270 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1271 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1272 if (err)
a43b25da 1273 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1274
1275 return err;
1276}
1277
7f859ecf
SM		 1278static int mlx5e_set_sq_maxrate(struct net_device *dev,
1279 struct mlx5e_txqsq *sq, u32 rate);
1280
31391048 1281static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1282 u32 tisn,
acc6c595 1283 int txq_ix,
6a9764ef 1284 struct mlx5e_params *params,
31391048
SM		 1285 struct mlx5e_sq_param *param,
1286 struct mlx5e_txqsq *sq)
1287{
1288 struct mlx5e_create_sq_param csp = {};
7f859ecf 1289 u32 tx_rate;
f62b8bb8
AV		 1290 int err;
1291
6a9764ef 1292 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1293 if (err)
1294 return err;
1295
a43b25da 1296 csp.tisn = tisn;
31391048 1297 csp.tis_lst_sz = 1;
33ad9711
SM		 1298 csp.cqn = sq->cq.mcq.cqn;
1299 csp.wq_ctrl = &sq->wq_ctrl;
1300 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1301 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1302 if (err)
31391048 1303 goto err_free_txqsq;
f62b8bb8 1304
a43b25da 1305 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1306 if (tx_rate)
a43b25da 1307 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1308
f62b8bb8
AV		 1309 return 0;
1310
31391048 1311err_free_txqsq:
3b77235b 1312 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1313 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1314
1315 return err;
1316}
1317
acc6c595
SM		 1318static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1319{
a43b25da 1320 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1321 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1322 netdev_tx_reset_queue(sq->txq);
1323 netif_tx_start_queue(sq->txq);
1324}
1325
f62b8bb8
AV		 1326static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1327{
1328 __netif_tx_lock_bh(txq);
1329 netif_tx_stop_queue(txq);
1330 __netif_tx_unlock_bh(txq);
1331}
1332
acc6c595 1333static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1334{
33ad9711 1335 struct mlx5e_channel *c = sq->channel;
33ad9711 1336
c0f1147d 1337 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1338 /* prevent netif_tx_wake_queue */
33ad9711 1339 napi_synchronize(&c->napi);
29429f33 1340
31391048 1341 netif_tx_disable_queue(sq->txq);
f62b8bb8 1342
31391048
SM		 1343 /* last doorbell out, godspeed .. */
1344 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1345 struct mlx5e_tx_wqe *nop;
864b2d71 1346
77bdf895 1347 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1348 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1349 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1350 }
acc6c595
SM		 1351}
1352
1353static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1354{
1355 struct mlx5e_channel *c = sq->channel;
a43b25da 1356 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1357
a43b25da 1358 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1359 if (sq->rate_limit)
1360 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1361 mlx5e_free_txqsq_descs(sq);
1362 mlx5e_free_txqsq(sq);
1363}
1364
1365static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1366 struct mlx5e_params *params,
31391048
SM		 1367 struct mlx5e_sq_param *param,
1368 struct mlx5e_icosq *sq)
1369{
1370 struct mlx5e_create_sq_param csp = {};
1371 int err;
1372
6a9764ef 1373 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1374 if (err)
1375 return err;
1376
1377 csp.cqn = sq->cq.mcq.cqn;
1378 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1379 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1380 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1381 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1382 if (err)
1383 goto err_free_icosq;
1384
1385 return 0;
1386
1387err_free_icosq:
1388 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1389 mlx5e_free_icosq(sq);
1390
1391 return err;
1392}
1393
1394static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1395{
1396 struct mlx5e_channel *c = sq->channel;
1397
1398 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1399 napi_synchronize(&c->napi);
1400
a43b25da 1401 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1402 mlx5e_free_icosq(sq);
1403}
1404
1405static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1406 struct mlx5e_params *params,
31391048
SM		 1407 struct mlx5e_sq_param *param,
1408 struct mlx5e_xdpsq *sq)
1409{
1410 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1411 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1412 unsigned int inline_hdr_sz = 0;
1413 int err;
1414 int i;
1415
6a9764ef 1416 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1417 if (err)
1418 return err;
1419
1420 csp.tis_lst_sz = 1;
a43b25da 1421 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1422 csp.cqn = sq->cq.mcq.cqn;
1423 csp.wq_ctrl = &sq->wq_ctrl;
1424 csp.min_inline_mode = sq->min_inline_mode;
1425 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1426 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1427 if (err)
1428 goto err_free_xdpsq;
1429
1430 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1431 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1432 ds_cnt++;
1433 }
1434
1435 /* Pre initialize fixed WQE fields */
1436 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1437 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1438 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1439 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1440 struct mlx5_wqe_data_seg *dseg;
1441
1442 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1443 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1444
1445 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1446 dseg->lkey = sq->mkey_be;
1447 }
1448
1449 return 0;
1450
1451err_free_xdpsq:
1452 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1453 mlx5e_free_xdpsq(sq);
1454
1455 return err;
1456}
1457
1458static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1459{
1460 struct mlx5e_channel *c = sq->channel;
1461
1462 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1463 napi_synchronize(&c->napi);
1464
a43b25da 1465 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1466 mlx5e_free_xdpsq_descs(sq);
1467 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1468}
1469
95b6c6a5
EBE		 1470static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1471 struct mlx5e_cq_param *param,
1472 struct mlx5e_cq *cq)
f62b8bb8 1473{
f62b8bb8
AV		 1474 struct mlx5_core_cq *mcq = &cq->mcq;
1475 int eqn_not_used;
0b6e26ce 1476 unsigned int irqn;
f62b8bb8
AV		 1477 int err;
1478 u32 i;
1479
f62b8bb8
AV		 1480 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1481 &cq->wq_ctrl);
1482 if (err)
1483 return err;
1484
1485 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1486
f62b8bb8
AV		 1487 mcq->cqe_sz = 64;
1488 mcq->set_ci_db = cq->wq_ctrl.db.db;
1489 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1490 *mcq->set_ci_db = 0;
1491 *mcq->arm_db = 0;
1492 mcq->vector = param->eq_ix;
1493 mcq->comp = mlx5e_completion_event;
1494 mcq->event = mlx5e_cq_error_event;
1495 mcq->irqn = irqn;
f62b8bb8
AV		 1496
1497 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1498 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1499
1500 cqe->op_own = 0xf1;
1501 }
1502
a43b25da 1503 cq->mdev = mdev;
f62b8bb8
AV		 1504
1505 return 0;
1506}
1507
95b6c6a5
EBE		 1508static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1509 struct mlx5e_cq_param *param,
1510 struct mlx5e_cq *cq)
1511{
1512 struct mlx5_core_dev *mdev = c->priv->mdev;
1513 int err;
1514
231243c8
SM		 1515 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1516 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1517 param->eq_ix = c->ix;
1518
1519 err = mlx5e_alloc_cq_common(mdev, param, cq);
1520
1521 cq->napi = &c->napi;
1522 cq->channel = c;
1523
1524 return err;
1525}
1526
3b77235b 1527static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1528{
1c1b5228 1529 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1530}
1531
3b77235b 1532static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1533{
a43b25da 1534 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1535 struct mlx5_core_cq *mcq = &cq->mcq;
1536
1537 void *in;
1538 void *cqc;
1539 int inlen;
0b6e26ce 1540 unsigned int irqn_not_used;
f62b8bb8
AV		 1541 int eqn;
1542 int err;
1543
1544 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1545 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1546 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1547 if (!in)
1548 return -ENOMEM;
1549
1550 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1551
1552 memcpy(cqc, param->cqc, sizeof(param->cqc));
1553
1c1b5228
TT		 1554 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1555 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1556
1557 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1558
9908aa29 1559 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1560 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1561 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1562 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1563 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1564 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1565
1566 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1567
1568 kvfree(in);
1569
1570 if (err)
1571 return err;
1572
1573 mlx5e_cq_arm(cq);
1574
1575 return 0;
1576}
1577
3b77235b 1578static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1579{
a43b25da 1580 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1581}
1582
1583static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1584 struct net_dim_cq_moder moder,
f62b8bb8 1585 struct mlx5e_cq_param *param,
6a9764ef 1586 struct mlx5e_cq *cq)
f62b8bb8 1587{
a43b25da 1588 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1589 int err;
f62b8bb8 1590
3b77235b 1591 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1592 if (err)
1593 return err;
1594
3b77235b 1595 err = mlx5e_create_cq(cq, param);
f62b8bb8 1596 if (err)
3b77235b 1597 goto err_free_cq;
f62b8bb8 1598
7524a5d8 1599 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1600 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1601 return 0;
1602
3b77235b
SM		 1603err_free_cq:
1604 mlx5e_free_cq(cq);
f62b8bb8
AV		 1605
1606 return err;
1607}
1608
1609static void mlx5e_close_cq(struct mlx5e_cq *cq)
1610{
f62b8bb8 1611 mlx5e_destroy_cq(cq);
3b77235b 1612 mlx5e_free_cq(cq);
f62b8bb8
AV		 1613}
1614
231243c8
SM		 1615static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1616{
1617 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1618}
1619
f62b8bb8 1620static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1621 struct mlx5e_params *params,
f62b8bb8
AV		 1622 struct mlx5e_channel_param *cparam)
1623{
f62b8bb8
AV		 1624 int err;
1625 int tc;
1626
1627 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1628 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1629 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1630 if (err)
1631 goto err_close_tx_cqs;
f62b8bb8
AV		 1632 }
1633
1634 return 0;
1635
1636err_close_tx_cqs:
1637 for (tc--; tc >= 0; tc--)
1638 mlx5e_close_cq(&c->sq[tc].cq);
1639
1640 return err;
1641}
1642
1643static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1644{
1645 int tc;
1646
1647 for (tc = 0; tc < c->num_tc; tc++)
1648 mlx5e_close_cq(&c->sq[tc].cq);
1649}
1650
1651static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1652 struct mlx5e_params *params,
f62b8bb8
AV		 1653 struct mlx5e_channel_param *cparam)
1654{
1655 int err;
1656 int tc;
1657
6a9764ef
SM		 1658 for (tc = 0; tc < params->num_tc; tc++) {
1659 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1660
a43b25da
SM		 1661 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1662 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1663 if (err)
1664 goto err_close_sqs;
1665 }
1666
1667 return 0;
1668
1669err_close_sqs:
1670 for (tc--; tc >= 0; tc--)
31391048 1671 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1672
1673 return err;
1674}
1675
1676static void mlx5e_close_sqs(struct mlx5e_channel *c)
1677{
1678 int tc;
1679
1680 for (tc = 0; tc < c->num_tc; tc++)
31391048 1681 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1682}
1683
507f0c81 1684static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1685 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1686{
1687 struct mlx5e_priv *priv = netdev_priv(dev);
1688 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1689 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1690 u16 rl_index = 0;
1691 int err;
1692
1693 if (rate == sq->rate_limit)
1694 /* nothing to do */
1695 return 0;
1696
1697 if (sq->rate_limit)
1698 /* remove current rl index to free space to next ones */
1699 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1700
1701 sq->rate_limit = 0;
1702
1703 if (rate) {
1704 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1705 if (err) {
1706 netdev_err(dev, "Failed configuring rate %u: %d\n",
1707 rate, err);
1708 return err;
1709 }
1710 }
1711
33ad9711
SM		 1712 msp.curr_state = MLX5_SQC_STATE_RDY;
1713 msp.next_state = MLX5_SQC_STATE_RDY;
1714 msp.rl_index = rl_index;
1715 msp.rl_update = true;
a43b25da 1716 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1717 if (err) {
1718 netdev_err(dev, "Failed configuring rate %u: %d\n",
1719 rate, err);
1720 /* remove the rate from the table */
1721 if (rate)
1722 mlx5_rl_remove_rate(mdev, rate);
1723 return err;
1724 }
1725
1726 sq->rate_limit = rate;
1727 return 0;
1728}
1729
1730static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1731{
1732 struct mlx5e_priv *priv = netdev_priv(dev);
1733 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1734 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1735 int err = 0;
1736
1737 if (!mlx5_rl_is_supported(mdev)) {
1738 netdev_err(dev, "Rate limiting is not supported on this device\n");
1739 return -EINVAL;
1740 }
1741
1742 /* rate is given in Mb/sec, HW config is in Kb/sec */
1743 rate = rate << 10;
1744
1745 /* Check whether rate in valid range, 0 is always valid */
1746 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1747 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1748 return -ERANGE;
1749 }
1750
1751 mutex_lock(&priv->state_lock);
1752 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1753 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1754 if (!err)
1755 priv->tx_rates[index] = rate;
1756 mutex_unlock(&priv->state_lock);
1757
1758 return err;
1759}
1760
f62b8bb8 1761static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1762 struct mlx5e_params *params,
f62b8bb8
AV		 1763 struct mlx5e_channel_param *cparam,
1764 struct mlx5e_channel **cp)
1765{
9a317425 1766 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1767 struct net_device *netdev = priv->netdev;
231243c8 1768 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1769 struct mlx5e_channel *c;
a8c2eb15 1770 unsigned int irq;
f62b8bb8 1771 int err;
a8c2eb15 1772 int eqn;
f62b8bb8 1773
231243c8 1774 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1775 if (!c)
1776 return -ENOMEM;
1777
1778 c->priv = priv;
a43b25da
SM		 1779 c->mdev = priv->mdev;
1780 c->tstamp = &priv->tstamp;
f62b8bb8 1781 c->ix = ix;
231243c8 1782 c->cpu = cpu;
f62b8bb8
AV		 1783 c->pdev = &priv->mdev->pdev->dev;
1784 c->netdev = priv->netdev;
b50d292b 1785 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1786 c->num_tc = params->num_tc;
1787 c->xdp = !!params->xdp_prog;
cb3c7fd4 1788
a8c2eb15
TT		 1789 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1790 c->irq_desc = irq_to_desc(irq);
1791
f62b8bb8
AV		 1792 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1793
6a9764ef 1794 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1795 if (err)
1796 goto err_napi_del;
1797
6a9764ef 1798 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1799 if (err)
1800 goto err_close_icosq_cq;
1801
6a9764ef 1802 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1803 if (err)
1804 goto err_close_tx_cqs;
f62b8bb8 1805
d7a0ecab 1806 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1807 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1808 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1809 if (err)
1810 goto err_close_rx_cq;
1811
f62b8bb8
AV		 1812 napi_enable(&c->napi);
1813
6a9764ef 1814 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1815 if (err)
1816 goto err_disable_napi;
1817
6a9764ef 1818 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1819 if (err)
1820 goto err_close_icosq;
1821
6a9764ef 1822 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1823 if (err)
1824 goto err_close_sqs;
b5503b99 1825
6a9764ef 1826 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1827 if (err)
b5503b99 1828 goto err_close_xdp_sq;
f62b8bb8 1829
f62b8bb8
AV		 1830 *cp = c;
1831
1832 return 0;
b5503b99 1833err_close_xdp_sq:
d7a0ecab 1834 if (c->xdp)
31391048 1835 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1836
1837err_close_sqs:
1838 mlx5e_close_sqs(c);
1839
d3c9bc27 1840err_close_icosq:
31391048 1841 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1842
f62b8bb8
AV		 1843err_disable_napi:
1844 napi_disable(&c->napi);
d7a0ecab 1845 if (c->xdp)
31871f87 1846 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1847
1848err_close_rx_cq:
f62b8bb8
AV		 1849 mlx5e_close_cq(&c->rq.cq);
1850
1851err_close_tx_cqs:
1852 mlx5e_close_tx_cqs(c);
1853
d3c9bc27
TT		 1854err_close_icosq_cq:
1855 mlx5e_close_cq(&c->icosq.cq);
1856
f62b8bb8
AV		 1857err_napi_del:
1858 netif_napi_del(&c->napi);
1859 kfree(c);
1860
1861 return err;
1862}
1863
acc6c595
SM		 1864static void mlx5e_activate_channel(struct mlx5e_channel *c)
1865{
1866 int tc;
1867
1868 for (tc = 0; tc < c->num_tc; tc++)
1869 mlx5e_activate_txqsq(&c->sq[tc]);
1870 mlx5e_activate_rq(&c->rq);
231243c8 1871 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1872}
1873
1874static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1875{
1876 int tc;
1877
1878 mlx5e_deactivate_rq(&c->rq);
1879 for (tc = 0; tc < c->num_tc; tc++)
1880 mlx5e_deactivate_txqsq(&c->sq[tc]);
1881}
1882
f62b8bb8
AV		 1883static void mlx5e_close_channel(struct mlx5e_channel *c)
1884{
1885 mlx5e_close_rq(&c->rq);
b5503b99 1886 if (c->xdp)
31391048 1887 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1888 mlx5e_close_sqs(c);
31391048 1889 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1890 napi_disable(&c->napi);
b5503b99 1891 if (c->xdp)
31871f87 1892 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1893 mlx5e_close_cq(&c->rq.cq);
1894 mlx5e_close_tx_cqs(c);
d3c9bc27 1895 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1896 netif_napi_del(&c->napi);
7ae92ae5 1897
f62b8bb8
AV		 1898 kfree(c);
1899}
1900
1901static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1902 struct mlx5e_params *params,
f62b8bb8
AV		 1903 struct mlx5e_rq_param *param)
1904{
1905 void *rqc = param->rqc;
1906 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1907
6a9764ef 1908 switch (params->rq_wq_type) {
461017cb 1909 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1910 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1911 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1912 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1913 break;
1914 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1915 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1916 }
1917
f62b8bb8
AV		 1918 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1919 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1920 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1921 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1922 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1923 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1924 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1925
311c7c71 1926 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1927 param->wq.linear = 1;
1928}
1929
556dd1b9
TT		 1930static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1931{
1932 void *rqc = param->rqc;
1933 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1934
1935 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1936 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1937}
1938
d3c9bc27
TT		 1939static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1940 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1941{
1942 void *sqc = param->sqc;
1943 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1944
f62b8bb8 1945 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1946 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1947
311c7c71 1948 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1949}
1950
1951static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1952 struct mlx5e_params *params,
d3c9bc27
TT		 1953 struct mlx5e_sq_param *param)
1954{
1955 void *sqc = param->sqc;
1956 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1957
1958 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1959 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 1960 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 1961}
1962
1963static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1964 struct mlx5e_cq_param *param)
1965{
1966 void *cqc = param->cqc;
1967
30aa60b3 1968 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1969}
1970
1971static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1972 struct mlx5e_params *params,
f62b8bb8
AV		 1973 struct mlx5e_cq_param *param)
1974{
1975 void *cqc = param->cqc;
461017cb 1976 u8 log_cq_size;
f62b8bb8 1977
6a9764ef 1978 switch (params->rq_wq_type) {
461017cb 1979 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1980 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1981 break;
1982 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1983 log_cq_size = params->log_rq_size;
461017cb
TT		 1984 }
1985
1986 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1987 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1988 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1989 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1990 }
f62b8bb8
AV		 1991
1992 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1993 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1994}
1995
1996static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1997 struct mlx5e_params *params,
f62b8bb8
AV		 1998 struct mlx5e_cq_param *param)
1999{
2000 void *cqc = param->cqc;
2001
6a9764ef 2002 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 2003
2004 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2005 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2006}
2007
d3c9bc27 2008static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2009 u8 log_wq_size,
2010 struct mlx5e_cq_param *param)
d3c9bc27
TT		 2011{
2012 void *cqc = param->cqc;
2013
2014 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2015
2016 mlx5e_build_common_cq_param(priv, param);
9908aa29 2017
9a317425 2018 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2019}
2020
2021static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2022 u8 log_wq_size,
2023 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2024{
2025 void *sqc = param->sqc;
2026 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2027
2028 mlx5e_build_sq_param_common(priv, param);
2029
2030 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2031 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2032}
2033
b5503b99 2034static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2035 struct mlx5e_params *params,
b5503b99
SM		 2036 struct mlx5e_sq_param *param)
2037{
2038 void *sqc = param->sqc;
2039 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2040
2041 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2042 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2043}
2044
6a9764ef
SM		 2045static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2046 struct mlx5e_params *params,
2047 struct mlx5e_channel_param *cparam)
f62b8bb8 2048{
bc77b240 2049 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2050
6a9764ef
SM		 2051 mlx5e_build_rq_param(priv, params, &cparam->rq);
2052 mlx5e_build_sq_param(priv, params, &cparam->sq);
2053 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2054 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2055 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2056 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2057 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2058}
2059
55c2503d
SM		 2060int mlx5e_open_channels(struct mlx5e_priv *priv,
2061 struct mlx5e_channels *chs)
f62b8bb8 2062{
6b87663f 2063 struct mlx5e_channel_param *cparam;
03289b88 2064 int err = -ENOMEM;
f62b8bb8 2065 int i;
f62b8bb8 2066
6a9764ef 2067 chs->num = chs->params.num_channels;
03289b88 2068
ff9c852f 2069 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2070 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2071 if (!chs->c || !cparam)
2072 goto err_free;
f62b8bb8 2073
6a9764ef 2074 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2075 for (i = 0; i < chs->num; i++) {
6a9764ef 2076 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2077 if (err)
2078 goto err_close_channels;
2079 }
2080
6b87663f 2081 kfree(cparam);
f62b8bb8
AV		 2082 return 0;
2083
2084err_close_channels:
2085 for (i--; i >= 0; i--)
ff9c852f 2086 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2087
acc6c595 2088err_free:
ff9c852f 2089 kfree(chs->c);
6b87663f 2090 kfree(cparam);
ff9c852f 2091 chs->num = 0;
f62b8bb8
AV		 2092 return err;
2093}
2094
acc6c595 2095static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2096{
2097 int i;
2098
acc6c595
SM		 2099 for (i = 0; i < chs->num; i++)
2100 mlx5e_activate_channel(chs->c[i]);
2101}
2102
2103static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2104{
2105 int err = 0;
2106 int i;
2107
2108 for (i = 0; i < chs->num; i++) {
2109 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2110 if (err)
2111 break;
2112 }
2113
2114 return err;
2115}
2116
2117static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2118{
2119 int i;
2120
2121 for (i = 0; i < chs->num; i++)
2122 mlx5e_deactivate_channel(chs->c[i]);
2123}
2124
55c2503d 2125void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2126{
2127 int i;
c3b7c5c9 2128
ff9c852f
SM		 2129 for (i = 0; i < chs->num; i++)
2130 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2131
ff9c852f
SM		 2132 kfree(chs->c);
2133 chs->num = 0;
f62b8bb8
AV		 2134}
2135
a5f97fee
SM		 2136static int
2137mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2138{
2139 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2140 void *rqtc;
2141 int inlen;
2142 int err;
1da36696 2143 u32 *in;
a5f97fee 2144 int i;
f62b8bb8 2145
f62b8bb8 2146 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2147 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2148 if (!in)
2149 return -ENOMEM;
2150
2151 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2152
2153 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2154 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2155
a5f97fee
SM		 2156 for (i = 0; i < sz; i++)
2157 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2158
398f3351
HHZ		 2159 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2160 if (!err)
2161 rqt->enabled = true;
f62b8bb8
AV		 2162
2163 kvfree(in);
1da36696
TT		 2164 return err;
2165}
2166
cb67b832 2167void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2168{
398f3351
HHZ		 2169 rqt->enabled = false;
2170 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2171}
2172
8f493ffd 2173int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2174{
2175 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2176 int err;
6bfd390b 2177
8f493ffd
SM		 2178 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2179 if (err)
2180 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2181 return err;
6bfd390b
HHZ		 2182}
2183
cb67b832 2184int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2185{
398f3351 2186 struct mlx5e_rqt *rqt;
1da36696
TT		 2187 int err;
2188 int ix;
2189
6bfd390b 2190 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2191 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2192 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2193 if (err)
2194 goto err_destroy_rqts;
2195 }
2196
2197 return 0;
2198
2199err_destroy_rqts:
8f493ffd 2200 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2201 for (ix--; ix >= 0; ix--)
398f3351 2202 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2203
f62b8bb8
AV		 2204 return err;
2205}
2206
8f493ffd
SM		 2207void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2208{
2209 int i;
2210
2211 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2212 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2213}
2214
a5f97fee
SM		 2215static int mlx5e_rx_hash_fn(int hfunc)
2216{
2217 return (hfunc == ETH_RSS_HASH_TOP) ?
2218 MLX5_RX_HASH_FN_TOEPLITZ :
2219 MLX5_RX_HASH_FN_INVERTED_XOR8;
2220}
2221
3f6d08d1 2222int mlx5e_bits_invert(unsigned long a, int size)
a5f97fee
SM		 2223{
2224 int inv = 0;
2225 int i;
2226
2227 for (i = 0; i < size; i++)
2228 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2229
2230 return inv;
2231}
2232
2233static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2234 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2235{
2236 int i;
2237
2238 for (i = 0; i < sz; i++) {
2239 u32 rqn;
2240
2241 if (rrp.is_rss) {
2242 int ix = i;
2243
2244 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2245 ix = mlx5e_bits_invert(i, ilog2(sz));
2246
6a9764ef 2247 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2248 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2249 } else {
2250 rqn = rrp.rqn;
2251 }
2252 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2253 }
2254}
2255
2256int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2257 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2258{
2259 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2260 void *rqtc;
2261 int inlen;
1da36696 2262 u32 *in;
5c50368f
AS		 2263 int err;
2264
5c50368f 2265 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2266 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2267 if (!in)
2268 return -ENOMEM;
2269
2270 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2271
2272 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2273 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2274 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2275 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2276
2277 kvfree(in);
5c50368f
AS		 2278 return err;
2279}
2280
a5f97fee
SM		 2281static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2282 struct mlx5e_redirect_rqt_param rrp)
2283{
2284 if (!rrp.is_rss)
2285 return rrp.rqn;
2286
2287 if (ix >= rrp.rss.channels->num)
2288 return priv->drop_rq.rqn;
2289
2290 return rrp.rss.channels->c[ix]->rq.rqn;
2291}
2292
2293static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2294 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2295{
1da36696
TT		 2296 u32 rqtn;
2297 int ix;
2298
398f3351 2299 if (priv->indir_rqt.enabled) {
a5f97fee 2300 /* RSS RQ table */
398f3351 2301 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2302 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2303 }
2304
a5f97fee
SM		 2305 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2306 struct mlx5e_redirect_rqt_param direct_rrp = {
2307 .is_rss = false,
95632791
AM		 2308 {
2309 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2310 },
a5f97fee
SM		 2311 };
2312
2313 /* Direct RQ Tables */
398f3351
HHZ		 2314 if (!priv->direct_tir[ix].rqt.enabled)
2315 continue;
a5f97fee 2316
398f3351 2317 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2318 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2319 }
40ab6a6e
AS		 2320}
2321
a5f97fee
SM		 2322static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2323 struct mlx5e_channels *chs)
2324{
2325 struct mlx5e_redirect_rqt_param rrp = {
2326 .is_rss = true,
95632791
AM		 2327 {
2328 .rss = {
2329 .channels = chs,
2330 .hfunc = chs->params.rss_hfunc,
2331 }
2332 },
a5f97fee
SM		 2333 };
2334
2335 mlx5e_redirect_rqts(priv, rrp);
2336}
2337
2338static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2339{
2340 struct mlx5e_redirect_rqt_param drop_rrp = {
2341 .is_rss = false,
95632791
AM		 2342 {
2343 .rqn = priv->drop_rq.rqn,
2344 },
a5f97fee
SM		 2345 };
2346
2347 mlx5e_redirect_rqts(priv, drop_rrp);
2348}
2349
6a9764ef 2350static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2351{
6a9764ef 2352 if (!params->lro_en)
5c50368f
AS		 2353 return;
2354
2355#define ROUGH_MAX_L2_L3_HDR_SZ 256
2356
2357 MLX5_SET(tirc, tirc, lro_enable_mask,
2358 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2359 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2360 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2361 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2362 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2363}
2364
6a9764ef
SM		 2365void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2366 enum mlx5e_traffic_types tt,
7b3722fa 2367 void *tirc, bool inner)
bdfc028d 2368{
7b3722fa
GP		 2369 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2370 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2371
2372#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2373 MLX5_HASH_FIELD_SEL_DST_IP)
2374
2375#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2376 MLX5_HASH_FIELD_SEL_DST_IP |\
2377 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2378 MLX5_HASH_FIELD_SEL_L4_DPORT)
2379
2380#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2381 MLX5_HASH_FIELD_SEL_DST_IP |\
2382 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2383
6a9764ef
SM		 2384 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2385 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2386 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2387 rx_hash_toeplitz_key);
2388 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2389 rx_hash_toeplitz_key);
2390
2391 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2392 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2393 }
a100ff3e
GP		 2394
2395 switch (tt) {
2396 case MLX5E_TT_IPV4_TCP:
2397 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2398 MLX5_L3_PROT_TYPE_IPV4);
2399 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2400 MLX5_L4_PROT_TYPE_TCP);
2401 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2402 MLX5_HASH_IP_L4PORTS);
2403 break;
2404
2405 case MLX5E_TT_IPV6_TCP:
2406 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2407 MLX5_L3_PROT_TYPE_IPV6);
2408 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2409 MLX5_L4_PROT_TYPE_TCP);
2410 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2411 MLX5_HASH_IP_L4PORTS);
2412 break;
2413
2414 case MLX5E_TT_IPV4_UDP:
2415 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2416 MLX5_L3_PROT_TYPE_IPV4);
2417 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2418 MLX5_L4_PROT_TYPE_UDP);
2419 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2420 MLX5_HASH_IP_L4PORTS);
2421 break;
2422
2423 case MLX5E_TT_IPV6_UDP:
2424 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2425 MLX5_L3_PROT_TYPE_IPV6);
2426 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2427 MLX5_L4_PROT_TYPE_UDP);
2428 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429 MLX5_HASH_IP_L4PORTS);
2430 break;
2431
2432 case MLX5E_TT_IPV4_IPSEC_AH:
2433 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434 MLX5_L3_PROT_TYPE_IPV4);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436 MLX5_HASH_IP_IPSEC_SPI);
2437 break;
2438
2439 case MLX5E_TT_IPV6_IPSEC_AH:
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV6);
2442 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443 MLX5_HASH_IP_IPSEC_SPI);
2444 break;
2445
2446 case MLX5E_TT_IPV4_IPSEC_ESP:
2447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448 MLX5_L3_PROT_TYPE_IPV4);
2449 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450 MLX5_HASH_IP_IPSEC_SPI);
2451 break;
2452
2453 case MLX5E_TT_IPV6_IPSEC_ESP:
2454 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455 MLX5_L3_PROT_TYPE_IPV6);
2456 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457 MLX5_HASH_IP_IPSEC_SPI);
2458 break;
2459
2460 case MLX5E_TT_IPV4:
2461 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2462 MLX5_L3_PROT_TYPE_IPV4);
2463 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2464 MLX5_HASH_IP);
2465 break;
2466
2467 case MLX5E_TT_IPV6:
2468 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2469 MLX5_L3_PROT_TYPE_IPV6);
2470 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2471 MLX5_HASH_IP);
2472 break;
2473 default:
2474 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2475 }
bdfc028d
TT		 2476}
2477
ab0394fe 2478static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2479{
2480 struct mlx5_core_dev *mdev = priv->mdev;
2481
2482 void *in;
2483 void *tirc;
2484 int inlen;
2485 int err;
ab0394fe 2486 int tt;
1da36696 2487 int ix;
5c50368f
AS		 2488
2489 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2490 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2491 if (!in)
2492 return -ENOMEM;
2493
2494 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2495 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2496
6a9764ef 2497 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2498
1da36696 2499 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2500 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2501 inlen);
ab0394fe 2502 if (err)
1da36696 2503 goto free_in;
ab0394fe 2504 }
5c50368f 2505
6bfd390b 2506 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2507 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2508 in, inlen);
2509 if (err)
2510 goto free_in;
2511 }
2512
2513free_in:
5c50368f
AS		 2514 kvfree(in);
2515
2516 return err;
2517}
2518
7b3722fa
GP		 2519static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2520 enum mlx5e_traffic_types tt,
2521 u32 *tirc)
2522{
2523 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2524
2525 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2526
2527 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2528 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2529 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2530
2531 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2532}
2533
cd255eff 2534static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2535{
40ab6a6e 2536 struct mlx5_core_dev *mdev = priv->mdev;
c139dbfd 2537 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
40ab6a6e
AS		 2538 int err;
2539
cd255eff 2540 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2541 if (err)
2542 return err;
2543
cd255eff
SM		 2544 /* Update vport context MTU */
2545 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2546 return 0;
2547}
40ab6a6e 2548
cd255eff
SM		 2549static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2550{
2551 struct mlx5_core_dev *mdev = priv->mdev;
2552 u16 hw_mtu = 0;
2553 int err;
40ab6a6e 2554
cd255eff
SM		 2555 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2556 if (err || !hw_mtu) /* fallback to port oper mtu */
2557 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2558
c139dbfd 2559 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
cd255eff
SM		 2560}
2561
2e20a151 2562static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2563{
2e20a151 2564 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2565 u16 mtu;
2566 int err;
2567
2568 err = mlx5e_set_mtu(priv, netdev->mtu);
2569 if (err)
2570 return err;
40ab6a6e 2571
cd255eff
SM		 2572 mlx5e_query_mtu(priv, &mtu);
2573 if (mtu != netdev->mtu)
2574 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2575 __func__, mtu, netdev->mtu);
40ab6a6e 2576
cd255eff 2577 netdev->mtu = mtu;
40ab6a6e
AS		 2578 return 0;
2579}
2580
08fb1dac
SM		 2581static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2582{
2583 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2584 int nch = priv->channels.params.num_channels;
2585 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2586 int tc;
2587
2588 netdev_reset_tc(netdev);
2589
2590 if (ntc == 1)
2591 return;
2592
2593 netdev_set_num_tc(netdev, ntc);
2594
7ccdd084
RS		 2595 /* Map netdev TCs to offset 0
2596 * We have our own UP to TXQ mapping for QoS
2597 */
08fb1dac 2598 for (tc = 0; tc < ntc; tc++)
7ccdd084 2599 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2600}
2601
acc6c595
SM		 2602static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2603{
2604 struct mlx5e_channel *c;
2605 struct mlx5e_txqsq *sq;
2606 int i, tc;
2607
2608 for (i = 0; i < priv->channels.num; i++)
2609 for (tc = 0; tc < priv->profile->max_tc; tc++)
2610 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2611
2612 for (i = 0; i < priv->channels.num; i++) {
2613 c = priv->channels.c[i];
2614 for (tc = 0; tc < c->num_tc; tc++) {
2615 sq = &c->sq[tc];
2616 priv->txq2sq[sq->txq_ix] = sq;
2617 }
2618 }
2619}
2620
603f4a45 2621void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2622{
9008ae07
SM		 2623 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2624 struct net_device *netdev = priv->netdev;
2625
2626 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2627 netif_set_real_num_tx_queues(netdev, num_txqs);
2628 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2629
acc6c595
SM		 2630 mlx5e_build_channels_tx_maps(priv);
2631 mlx5e_activate_channels(&priv->channels);
2632 netif_tx_start_all_queues(priv->netdev);
9008ae07 2633
a9f7705f 2634 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2635 mlx5e_add_sqs_fwd_rules(priv);
2636
acc6c595 2637 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2638 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2639}
2640
603f4a45 2641void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2642{
9008ae07
SM		 2643 mlx5e_redirect_rqts_to_drop(priv);
2644
a9f7705f 2645 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2646 mlx5e_remove_sqs_fwd_rules(priv);
2647
acc6c595
SM		 2648 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2649 * polling for inactive tx queues.
2650 */
2651 netif_tx_stop_all_queues(priv->netdev);
2652 netif_tx_disable(priv->netdev);
2653 mlx5e_deactivate_channels(&priv->channels);
2654}
2655
55c2503d 2656void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2657 struct mlx5e_channels *new_chs,
2658 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2659{
2660 struct net_device *netdev = priv->netdev;
2661 int new_num_txqs;
7ca42c80 2662 int carrier_ok;
55c2503d
SM		 2663 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2664
7ca42c80 2665 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2666 netif_carrier_off(netdev);
2667
2668 if (new_num_txqs < netdev->real_num_tx_queues)
2669 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2670
2671 mlx5e_deactivate_priv_channels(priv);
2672 mlx5e_close_channels(&priv->channels);
2673
2674 priv->channels = *new_chs;
2675
2e20a151
SM		 2676 /* New channels are ready to roll, modify HW settings if needed */
2677 if (hw_modify)
2678 hw_modify(priv);
2679
55c2503d
SM		 2680 mlx5e_refresh_tirs(priv, false);
2681 mlx5e_activate_priv_channels(priv);
2682
7ca42c80
ES		 2683 /* return carrier back if needed */
2684 if (carrier_ok)
2685 netif_carrier_on(netdev);
55c2503d
SM		 2686}
2687
237f258c 2688void mlx5e_timestamp_init(struct mlx5e_priv *priv)
7c39afb3
FD		 2689{
2690 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2691 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2692}
2693
40ab6a6e
AS		 2694int mlx5e_open_locked(struct net_device *netdev)
2695{
2696 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2697 int err;
2698
2699 set_bit(MLX5E_STATE_OPENED, &priv->state);
2700
ff9c852f 2701 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2702 if (err)
343b29f3 2703 goto err_clear_state_opened_flag;
40ab6a6e 2704
b676f653 2705 mlx5e_refresh_tirs(priv, false);
acc6c595 2706 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2707 if (priv->profile->update_carrier)
2708 priv->profile->update_carrier(priv);
be4891af 2709
cb67b832
HHZ		 2710 if (priv->profile->update_stats)
2711 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2712
9b37b07f 2713 return 0;
343b29f3
AS		 2714
2715err_clear_state_opened_flag:
2716 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2717 return err;
40ab6a6e
AS		 2718}
2719
cb67b832 2720int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2721{
2722 struct mlx5e_priv *priv = netdev_priv(netdev);
2723 int err;
2724
2725 mutex_lock(&priv->state_lock);
2726 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2727 if (!err)
2728 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2729 mutex_unlock(&priv->state_lock);
2730
2731 return err;
2732}
2733
2734int mlx5e_close_locked(struct net_device *netdev)
2735{
2736 struct mlx5e_priv *priv = netdev_priv(netdev);
2737
a1985740
AS		 2738 /* May already be CLOSED in case a previous configuration operation
2739 * (e.g RX/TX queue size change) that involves close&open failed.
2740 */
2741 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2742 return 0;
2743
40ab6a6e
AS		 2744 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2745
40ab6a6e 2746 netif_carrier_off(priv->netdev);
acc6c595
SM		 2747 mlx5e_deactivate_priv_channels(priv);
2748 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2749
2750 return 0;
2751}
2752
cb67b832 2753int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2754{
2755 struct mlx5e_priv *priv = netdev_priv(netdev);
2756 int err;
2757
26e59d80
MHY		 2758 if (!netif_device_present(netdev))
2759 return -ENODEV;
2760
40ab6a6e 2761 mutex_lock(&priv->state_lock);
63bfd399 2762 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 2763 err = mlx5e_close_locked(netdev);
2764 mutex_unlock(&priv->state_lock);
2765
2766 return err;
2767}
2768
a43b25da 2769static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2770 struct mlx5e_rq *rq,
2771 struct mlx5e_rq_param *param)
40ab6a6e 2772{
40ab6a6e
AS		 2773 void *rqc = param->rqc;
2774 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2775 int err;
2776
2777 param->wq.db_numa_node = param->wq.buf_numa_node;
2778
2779 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2780 &rq->wq_ctrl);
2781 if (err)
2782 return err;
2783
0ddf5432
JDB		 2784 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2785 xdp_rxq_info_unused(&rq->xdp_rxq);
2786
a43b25da 2787 rq->mdev = mdev;
40ab6a6e
AS		 2788
2789 return 0;
2790}
2791
a43b25da 2792static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2793 struct mlx5e_cq *cq,
2794 struct mlx5e_cq_param *param)
40ab6a6e 2795{
95b6c6a5 2796 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2797}
2798
a43b25da
SM		 2799static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2800 struct mlx5e_rq *drop_rq)
40ab6a6e 2801{
a43b25da
SM		 2802 struct mlx5e_cq_param cq_param = {};
2803 struct mlx5e_rq_param rq_param = {};
2804 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2805 int err;
2806
556dd1b9 2807 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2808
a43b25da 2809 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2810 if (err)
2811 return err;
2812
3b77235b 2813 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2814 if (err)
3b77235b 2815 goto err_free_cq;
40ab6a6e 2816
a43b25da 2817 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2818 if (err)
3b77235b 2819 goto err_destroy_cq;
40ab6a6e 2820
a43b25da 2821 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2822 if (err)
3b77235b 2823 goto err_free_rq;
40ab6a6e
AS		 2824
2825 return 0;
2826
3b77235b 2827err_free_rq:
a43b25da 2828 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2829
2830err_destroy_cq:
a43b25da 2831 mlx5e_destroy_cq(cq);
40ab6a6e 2832
3b77235b 2833err_free_cq:
a43b25da 2834 mlx5e_free_cq(cq);
3b77235b 2835
40ab6a6e
AS		 2836 return err;
2837}
2838
a43b25da 2839static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2840{
a43b25da
SM		 2841 mlx5e_destroy_rq(drop_rq);
2842 mlx5e_free_rq(drop_rq);
2843 mlx5e_destroy_cq(&drop_rq->cq);
2844 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2845}
2846
5426a0b2
SM		 2847int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2848 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2849{
c4f287c4 2850 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2851 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2852
08fb1dac 2853 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2854 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2855 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2856
2857 if (mlx5_lag_is_lacp_owner(mdev))
2858 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2859
5426a0b2 2860 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2861}
2862
5426a0b2 2863void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2864{
5426a0b2 2865 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2866}
2867
cb67b832 2868int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2869{
2870 int err;
2871 int tc;
2872
6bfd390b 2873 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2874 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2875 if (err)
2876 goto err_close_tises;
2877 }
2878
2879 return 0;
2880
2881err_close_tises:
2882 for (tc--; tc >= 0; tc--)
5426a0b2 2883 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2884
2885 return err;
2886}
2887
cb67b832 2888void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2889{
2890 int tc;
2891
6bfd390b 2892 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2893 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2894}
2895
6a9764ef
SM		 2896static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2897 enum mlx5e_traffic_types tt,
2898 u32 *tirc)
f62b8bb8 2899{
b50d292b 2900 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2901
6a9764ef 2902 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2903
4cbeaff5 2904 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2905 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 2906 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 2907}
2908
6a9764ef 2909static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2910{
b50d292b 2911 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2912
6a9764ef 2913 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2914
2915 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2916 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2917 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2918}
2919
8f493ffd 2920int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2921{
724b2aa1 2922 struct mlx5e_tir *tir;
f62b8bb8
AV		 2923 void *tirc;
2924 int inlen;
7b3722fa 2925 int i = 0;
f62b8bb8 2926 int err;
1da36696 2927 u32 *in;
1da36696 2928 int tt;
f62b8bb8
AV		 2929
2930 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2931 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2932 if (!in)
2933 return -ENOMEM;
2934
1da36696
TT		 2935 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2936 memset(in, 0, inlen);
724b2aa1 2937 tir = &priv->indir_tir[tt];
1da36696 2938 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2939 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2940 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 2941 if (err) {
2942 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2943 goto err_destroy_inner_tirs;
2944 }
f62b8bb8
AV		 2945 }
2946
7b3722fa
GP		 2947 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2948 goto out;
2949
2950 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2951 memset(in, 0, inlen);
2952 tir = &priv->inner_indir_tir[i];
2953 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2954 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2955 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2956 if (err) {
2957 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2958 goto err_destroy_inner_tirs;
2959 }
2960 }
2961
2962out:
6bfd390b
HHZ		 2963 kvfree(in);
2964
2965 return 0;
2966
7b3722fa
GP		 2967err_destroy_inner_tirs:
2968 for (i--; i >= 0; i--)
2969 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2970
6bfd390b
HHZ		 2971 for (tt--; tt >= 0; tt--)
2972 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2973
2974 kvfree(in);
2975
2976 return err;
2977}
2978
cb67b832 2979int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2980{
2981 int nch = priv->profile->max_nch(priv->mdev);
2982 struct mlx5e_tir *tir;
2983 void *tirc;
2984 int inlen;
2985 int err;
2986 u32 *in;
2987 int ix;
2988
2989 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2990 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2991 if (!in)
2992 return -ENOMEM;
2993
1da36696
TT		 2994 for (ix = 0; ix < nch; ix++) {
2995 memset(in, 0, inlen);
724b2aa1 2996 tir = &priv->direct_tir[ix];
1da36696 2997 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2998 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2999 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 3000 if (err)
3001 goto err_destroy_ch_tirs;
3002 }
3003
3004 kvfree(in);
3005
f62b8bb8
AV		 3006 return 0;
3007
1da36696 3008err_destroy_ch_tirs:
8f493ffd 3009 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 3010 for (ix--; ix >= 0; ix--)
724b2aa1 3011 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 3012
1da36696 3013 kvfree(in);
f62b8bb8
AV		 3014
3015 return err;
3016}
3017
8f493ffd 3018void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 3019{
3020 int i;
3021
1da36696 3022 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3023 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 3024
3025 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3026 return;
3027
3028 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3029 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3030}
3031
cb67b832 3032void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 3033{
3034 int nch = priv->profile->max_nch(priv->mdev);
3035 int i;
3036
3037 for (i = 0; i < nch; i++)
3038 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3039}
3040
102722fc
GE		 3041static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3042{
3043 int err = 0;
3044 int i;
3045
3046 for (i = 0; i < chs->num; i++) {
3047 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3048 if (err)
3049 return err;
3050 }
3051
3052 return 0;
3053}
3054
f6d96a20 3055static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3056{
3057 int err = 0;
3058 int i;
3059
ff9c852f
SM		 3060 for (i = 0; i < chs->num; i++) {
3061 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3062 if (err)
3063 return err;
3064 }
3065
3066 return 0;
3067}
3068
0cf0f6d3
JP		 3069static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3070 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3071{
3072 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3073 struct mlx5e_channels new_channels = {};
0cf0f6d3 3074 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3075 int err = 0;
3076
0cf0f6d3
JP		 3077 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3078
08fb1dac
SM		 3079 if (tc && tc != MLX5E_MAX_NUM_TC)
3080 return -EINVAL;
3081
3082 mutex_lock(&priv->state_lock);
3083
6f9485af
SM		 3084 new_channels.params = priv->channels.params;
3085 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3086
20b6a1c7 3087 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3088 priv->channels.params = new_channels.params;
3089 goto out;
3090 }
08fb1dac 3091
6f9485af
SM		 3092 err = mlx5e_open_channels(priv, &new_channels);
3093 if (err)
3094 goto out;
08fb1dac 3095
2e20a151 3096 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3097out:
08fb1dac 3098 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3099 return err;
3100}
3101
e80541ec 3102#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3103static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
0cf0f6d3 3104 struct tc_cls_flower_offload *cls_flower)
08fb1dac 3105{
d6c862ba 3106 if (cls_flower->common.chain_index)
0cf0f6d3 3107 return -EOPNOTSUPP;
e8f887ac 3108
0cf0f6d3
JP		 3109 switch (cls_flower->command) {
3110 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 3111 return mlx5e_configure_flower(priv, cls_flower);
0cf0f6d3
JP		 3112 case TC_CLSFLOWER_DESTROY:
3113 return mlx5e_delete_flower(priv, cls_flower);
3114 case TC_CLSFLOWER_STATS:
3115 return mlx5e_stats_flower(priv, cls_flower);
3116 default:
a5fcf8a6 3117 return -EOPNOTSUPP;
0cf0f6d3
JP		 3118 }
3119}
d6c862ba
JP		 3120
3121int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3122 void *cb_priv)
3123{
3124 struct mlx5e_priv *priv = cb_priv;
3125
44ae12a7
JP		 3126 if (!tc_can_offload(priv->netdev))
3127 return -EOPNOTSUPP;
3128
d6c862ba
JP		 3129 switch (type) {
3130 case TC_SETUP_CLSFLOWER:
3131 return mlx5e_setup_tc_cls_flower(priv, type_data);
3132 default:
3133 return -EOPNOTSUPP;
3134 }
3135}
3136
3137static int mlx5e_setup_tc_block(struct net_device *dev,
3138 struct tc_block_offload *f)
3139{
3140 struct mlx5e_priv *priv = netdev_priv(dev);
3141
3142 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3143 return -EOPNOTSUPP;
3144
3145 switch (f->command) {
3146 case TC_BLOCK_BIND:
3147 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3148 priv, priv);
3149 case TC_BLOCK_UNBIND:
3150 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3151 priv);
3152 return 0;
3153 default:
3154 return -EOPNOTSUPP;
3155 }
3156}
e80541ec 3157#endif
a5fcf8a6 3158
717503b9
JP		 3159int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3160 void *type_data)
0cf0f6d3 3161{
2572ac53 3162 switch (type) {
fde6af47 3163#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3164 case TC_SETUP_BLOCK:
3165 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3166#endif
575ed7d3 3167 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3168 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3169 default:
3170 return -EOPNOTSUPP;
3171 }
08fb1dac
SM		 3172}
3173
bc1f4470 3174static void
f62b8bb8
AV		 3175mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3176{
3177 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3178 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3179 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3180 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3181
370bad0f
OG		 3182 if (mlx5e_is_uplink_rep(priv)) {
3183 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3184 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3185 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3186 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3187 } else {
3188 stats->rx_packets = sstats->rx_packets;
3189 stats->rx_bytes = sstats->rx_bytes;
3190 stats->tx_packets = sstats->tx_packets;
3191 stats->tx_bytes = sstats->tx_bytes;
3192 stats->tx_dropped = sstats->tx_queue_dropped;
3193 }
269e6b3a
GP		 3194
3195 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3196
3197 stats->rx_length_errors =
9218b44d
GP		 3198 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3199 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3200 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3201 stats->rx_crc_errors =
9218b44d
GP		 3202 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3203 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3204 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3205 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3206 stats->rx_frame_errors;
3207 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3208
3209 /* vport multicast also counts packets that are dropped due to steering
3210 * or rx out of buffer
3211 */
9218b44d
GP		 3212 stats->multicast =
3213 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3214}
3215
3216static void mlx5e_set_rx_mode(struct net_device *dev)
3217{
3218 struct mlx5e_priv *priv = netdev_priv(dev);
3219
7bb29755 3220 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3221}
3222
3223static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3224{
3225 struct mlx5e_priv *priv = netdev_priv(netdev);
3226 struct sockaddr *saddr = addr;
3227
3228 if (!is_valid_ether_addr(saddr->sa_data))
3229 return -EADDRNOTAVAIL;
3230
3231 netif_addr_lock_bh(netdev);
3232 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3233 netif_addr_unlock_bh(netdev);
3234
7bb29755 3235 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3236
3237 return 0;
3238}
3239
75b81ce7 3240#define MLX5E_SET_FEATURE(features, feature, enable) \
0e405443
GP		 3241 do { \
3242 if (enable) \
75b81ce7 3243 *features |= feature; \
0e405443 3244 else \
75b81ce7 3245 *features &= ~feature; \
0e405443
GP		 3246 } while (0)
3247
3248typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3249
3250static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3251{
3252 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3253 struct mlx5e_channels new_channels = {};
3254 int err = 0;
3255 bool reset;
f62b8bb8
AV		 3256
3257 mutex_lock(&priv->state_lock);
f62b8bb8 3258
2e20a151
SM		 3259 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3260 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3261
2e20a151
SM		 3262 new_channels.params = priv->channels.params;
3263 new_channels.params.lro_en = enable;
3264
3265 if (!reset) {
3266 priv->channels.params = new_channels.params;
3267 err = mlx5e_modify_tirs_lro(priv);
3268 goto out;
98e81b0a 3269 }
f62b8bb8 3270
2e20a151
SM		 3271 err = mlx5e_open_channels(priv, &new_channels);
3272 if (err)
3273 goto out;
0e405443 3274
2e20a151
SM		 3275 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3276out:
9b37b07f 3277 mutex_unlock(&priv->state_lock);
0e405443
GP		 3278 return err;
3279}
3280
2b52a283 3281static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3282{
3283 struct mlx5e_priv *priv = netdev_priv(netdev);
3284
3285 if (enable)
2b52a283 3286 mlx5e_enable_cvlan_filter(priv);
0e405443 3287 else
2b52a283 3288 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3289
3290 return 0;
3291}
3292
3293static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3294{
3295 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3296
0e405443 3297 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3298 netdev_err(netdev,
3299 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3300 return -EINVAL;
3301 }
3302
0e405443
GP		 3303 return 0;
3304}
3305
94cb1ebb
EBE		 3306static int set_feature_rx_all(struct net_device *netdev, bool enable)
3307{
3308 struct mlx5e_priv *priv = netdev_priv(netdev);
3309 struct mlx5_core_dev *mdev = priv->mdev;
3310
3311 return mlx5_set_port_fcs(mdev, !enable);
3312}
3313
102722fc
GE		 3314static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3315{
3316 struct mlx5e_priv *priv = netdev_priv(netdev);
3317 int err;
3318
3319 mutex_lock(&priv->state_lock);
3320
3321 priv->channels.params.scatter_fcs_en = enable;
3322 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3323 if (err)
3324 priv->channels.params.scatter_fcs_en = !enable;
3325
3326 mutex_unlock(&priv->state_lock);
3327
3328 return err;
3329}
3330
36350114
GP		 3331static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3332{
3333 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3334 int err = 0;
36350114
GP		 3335
3336 mutex_lock(&priv->state_lock);
3337
6a9764ef 3338 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3339 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3340 goto unlock;
3341
3342 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3343 if (err)
6a9764ef 3344 priv->channels.params.vlan_strip_disable = enable;
36350114 3345
ff9c852f 3346unlock:
36350114
GP		 3347 mutex_unlock(&priv->state_lock);
3348
3349 return err;
3350}
3351
45bf454a
MG		 3352#ifdef CONFIG_RFS_ACCEL
3353static int set_feature_arfs(struct net_device *netdev, bool enable)
3354{
3355 struct mlx5e_priv *priv = netdev_priv(netdev);
3356 int err;
3357
3358 if (enable)
3359 err = mlx5e_arfs_enable(priv);
3360 else
3361 err = mlx5e_arfs_disable(priv);
3362
3363 return err;
3364}
3365#endif
3366
0e405443 3367static int mlx5e_handle_feature(struct net_device *netdev,
75b81ce7 3368 netdev_features_t *features,
0e405443
GP		 3369 netdev_features_t wanted_features,
3370 netdev_features_t feature,
3371 mlx5e_feature_handler feature_handler)
3372{
3373 netdev_features_t changes = wanted_features ^ netdev->features;
3374 bool enable = !!(wanted_features & feature);
3375 int err;
3376
3377 if (!(changes & feature))
3378 return 0;
3379
3380 err = feature_handler(netdev, enable);
3381 if (err) {
b20eab15
GP		 3382 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3383 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3384 return err;
3385 }
3386
75b81ce7 3387 MLX5E_SET_FEATURE(features, feature, enable);
0e405443
GP		 3388 return 0;
3389}
3390
3391static int mlx5e_set_features(struct net_device *netdev,
3392 netdev_features_t features)
3393{
75b81ce7 3394 netdev_features_t oper_features = netdev->features;
0e405443
GP		 3395 int err;
3396
75b81ce7
GP		 3397 err = mlx5e_handle_feature(netdev, &oper_features, features,
3398 NETIF_F_LRO, set_feature_lro);
3399 err |= mlx5e_handle_feature(netdev, &oper_features, features,
0e405443 3400 NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3401 set_feature_cvlan_filter);
75b81ce7
GP		 3402 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3403 NETIF_F_HW_TC, set_feature_tc_num_filters);
3404 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3405 NETIF_F_RXALL, set_feature_rx_all);
3406 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3407 NETIF_F_RXFCS, set_feature_rx_fcs);
3408 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3409 NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
45bf454a 3410#ifdef CONFIG_RFS_ACCEL
75b81ce7
GP		 3411 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3412 NETIF_F_NTUPLE, set_feature_arfs);
45bf454a 3413#endif
0e405443 3414
75b81ce7
GP		 3415 if (err) {
3416 netdev->features = oper_features;
3417 return -EINVAL;
3418 }
3419
3420 return 0;
f62b8bb8
AV		 3421}
3422
7d92d580
GP		 3423static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3424 netdev_features_t features)
3425{
3426 struct mlx5e_priv *priv = netdev_priv(netdev);
3427
3428 mutex_lock(&priv->state_lock);
3429 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3430 /* HW strips the outer C-tag header, this is a problem
3431 * for S-tag traffic.
3432 */
3433 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3434 if (!priv->channels.params.vlan_strip_disable)
3435 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3436 }
3437 mutex_unlock(&priv->state_lock);
3438
3439 return features;
3440}
3441
f62b8bb8
AV		 3442static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3443{
3444 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3445 struct mlx5e_channels new_channels = {};
3446 int curr_mtu;
98e81b0a 3447 int err = 0;
506753b0 3448 bool reset;
f62b8bb8 3449
f62b8bb8 3450 mutex_lock(&priv->state_lock);
98e81b0a 3451
6a9764ef
SM		 3452 reset = !priv->channels.params.lro_en &&
3453 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3454 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3455
2e20a151 3456 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3457
2e20a151 3458 curr_mtu = netdev->mtu;
f62b8bb8 3459 netdev->mtu = new_mtu;
98e81b0a 3460
2e20a151
SM		 3461 if (!reset) {
3462 mlx5e_set_dev_port_mtu(priv);
3463 goto out;
3464 }
98e81b0a 3465
2e20a151
SM		 3466 new_channels.params = priv->channels.params;
3467 err = mlx5e_open_channels(priv, &new_channels);
3468 if (err) {
3469 netdev->mtu = curr_mtu;
3470 goto out;
3471 }
3472
3473 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3474
2e20a151
SM		 3475out:
3476 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3477 return err;
3478}
3479
7c39afb3
FD		 3480int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3481{
3482 struct hwtstamp_config config;
3483 int err;
3484
3485 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3486 return -EOPNOTSUPP;
3487
3488 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3489 return -EFAULT;
3490
3491 /* TX HW timestamp */
3492 switch (config.tx_type) {
3493 case HWTSTAMP_TX_OFF:
3494 case HWTSTAMP_TX_ON:
3495 break;
3496 default:
3497 return -ERANGE;
3498 }
3499
3500 mutex_lock(&priv->state_lock);
3501 /* RX HW timestamp */
3502 switch (config.rx_filter) {
3503 case HWTSTAMP_FILTER_NONE:
3504 /* Reset CQE compression to Admin default */
3505 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3506 break;
3507 case HWTSTAMP_FILTER_ALL:
3508 case HWTSTAMP_FILTER_SOME:
3509 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3510 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3511 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3512 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3513 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3514 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3515 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3516 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3517 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3518 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3519 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3520 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3521 case HWTSTAMP_FILTER_NTP_ALL:
3522 /* Disable CQE compression */
3523 netdev_warn(priv->netdev, "Disabling cqe compression");
3524 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3525 if (err) {
3526 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3527 mutex_unlock(&priv->state_lock);
3528 return err;
3529 }
3530 config.rx_filter = HWTSTAMP_FILTER_ALL;
3531 break;
3532 default:
3533 mutex_unlock(&priv->state_lock);
3534 return -ERANGE;
3535 }
3536
3537 memcpy(&priv->tstamp, &config, sizeof(config));
3538 mutex_unlock(&priv->state_lock);
3539
3540 return copy_to_user(ifr->ifr_data, &config,
3541 sizeof(config)) ? -EFAULT : 0;
3542}
3543
3544int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3545{
3546 struct hwtstamp_config *cfg = &priv->tstamp;
3547
3548 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3549 return -EOPNOTSUPP;
3550
3551 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3552}
3553
ef9814de
EBE		 3554static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3555{
1170fbd8
FD		 3556 struct mlx5e_priv *priv = netdev_priv(dev);
3557
ef9814de
EBE		 3558 switch (cmd) {
3559 case SIOCSHWTSTAMP:
1170fbd8 3560 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3561 case SIOCGHWTSTAMP:
1170fbd8 3562 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3563 default:
3564 return -EOPNOTSUPP;
3565 }
3566}
3567
e80541ec 3568#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3569static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3570{
3571 struct mlx5e_priv *priv = netdev_priv(dev);
3572 struct mlx5_core_dev *mdev = priv->mdev;
3573
3574 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3575}
3576
79aab093
MS		 3577static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3578 __be16 vlan_proto)
66e49ded
SM		 3579{
3580 struct mlx5e_priv *priv = netdev_priv(dev);
3581 struct mlx5_core_dev *mdev = priv->mdev;
3582
79aab093
MS		 3583 if (vlan_proto != htons(ETH_P_8021Q))
3584 return -EPROTONOSUPPORT;
3585
66e49ded
SM		 3586 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3587 vlan, qos);
3588}
3589
f942380c
MHY		 3590static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3591{
3592 struct mlx5e_priv *priv = netdev_priv(dev);
3593 struct mlx5_core_dev *mdev = priv->mdev;
3594
3595 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3596}
3597
1edc57e2
MHY		 3598static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3599{
3600 struct mlx5e_priv *priv = netdev_priv(dev);
3601 struct mlx5_core_dev *mdev = priv->mdev;
3602
3603 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3604}
bd77bf1c
MHY		 3605
3606static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3607 int max_tx_rate)
3608{
3609 struct mlx5e_priv *priv = netdev_priv(dev);
3610 struct mlx5_core_dev *mdev = priv->mdev;
3611
bd77bf1c 3612 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3613 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3614}
3615
66e49ded
SM		 3616static int mlx5_vport_link2ifla(u8 esw_link)
3617{
3618 switch (esw_link) {
3619 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3620 return IFLA_VF_LINK_STATE_DISABLE;
3621 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3622 return IFLA_VF_LINK_STATE_ENABLE;
3623 }
3624 return IFLA_VF_LINK_STATE_AUTO;
3625}
3626
3627static int mlx5_ifla_link2vport(u8 ifla_link)
3628{
3629 switch (ifla_link) {
3630 case IFLA_VF_LINK_STATE_DISABLE:
3631 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3632 case IFLA_VF_LINK_STATE_ENABLE:
3633 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3634 }
3635 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3636}
3637
3638static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3639 int link_state)
3640{
3641 struct mlx5e_priv *priv = netdev_priv(dev);
3642 struct mlx5_core_dev *mdev = priv->mdev;
3643
3644 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3645 mlx5_ifla_link2vport(link_state));
3646}
3647
3648static int mlx5e_get_vf_config(struct net_device *dev,
3649 int vf, struct ifla_vf_info *ivi)
3650{
3651 struct mlx5e_priv *priv = netdev_priv(dev);
3652 struct mlx5_core_dev *mdev = priv->mdev;
3653 int err;
3654
3655 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3656 if (err)
3657 return err;
3658 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3659 return 0;
3660}
3661
3662static int mlx5e_get_vf_stats(struct net_device *dev,
3663 int vf, struct ifla_vf_stats *vf_stats)
3664{
3665 struct mlx5e_priv *priv = netdev_priv(dev);
3666 struct mlx5_core_dev *mdev = priv->mdev;
3667
3668 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3669 vf_stats);
3670}
e80541ec 3671#endif
66e49ded 3672
1ad9a00a
PB		 3673static void mlx5e_add_vxlan_port(struct net_device *netdev,
3674 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3675{
3676 struct mlx5e_priv *priv = netdev_priv(netdev);
3677
974c3f30
AD		 3678 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3679 return;
3680
b3f63c3d
MF		 3681 if (!mlx5e_vxlan_allowed(priv->mdev))
3682 return;
3683
974c3f30 3684 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3685}
3686
1ad9a00a
PB		 3687static void mlx5e_del_vxlan_port(struct net_device *netdev,
3688 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3689{
3690 struct mlx5e_priv *priv = netdev_priv(netdev);
3691
974c3f30
AD		 3692 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3693 return;
3694
b3f63c3d
MF		 3695 if (!mlx5e_vxlan_allowed(priv->mdev))
3696 return;
3697
974c3f30 3698 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3699}
3700
27299841
GP		 3701static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3702 struct sk_buff *skb,
3703 netdev_features_t features)
b3f63c3d 3704{
2989ad1e 3705 unsigned int offset = 0;
b3f63c3d 3706 struct udphdr *udph;
27299841
GP		 3707 u8 proto;
3708 u16 port;
b3f63c3d
MF		 3709
3710 switch (vlan_get_protocol(skb)) {
3711 case htons(ETH_P_IP):
3712 proto = ip_hdr(skb)->protocol;
3713 break;
3714 case htons(ETH_P_IPV6):
2989ad1e 3715 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 3716 break;
3717 default:
3718 goto out;
3719 }
3720
27299841
GP		 3721 switch (proto) {
3722 case IPPROTO_GRE:
3723 return features;
3724 case IPPROTO_UDP:
b3f63c3d
MF		 3725 udph = udp_hdr(skb);
3726 port = be16_to_cpu(udph->dest);
b3f63c3d 3727
27299841
GP		 3728 /* Verify if UDP port is being offloaded by HW */
3729 if (mlx5e_vxlan_lookup_port(priv, port))
3730 return features;
3731 }
b3f63c3d
MF		 3732
3733out:
3734 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3735 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3736}
3737
3738static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3739 struct net_device *netdev,
3740 netdev_features_t features)
3741{
3742 struct mlx5e_priv *priv = netdev_priv(netdev);
3743
3744 features = vlan_features_check(skb, features);
3745 features = vxlan_features_check(skb, features);
3746
2ac9cfe7
IT		 3747#ifdef CONFIG_MLX5_EN_IPSEC
3748 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3749 return features;
3750#endif
3751
b3f63c3d
MF		 3752 /* Validate if the tunneled packet is being offloaded by HW */
3753 if (skb->encapsulation &&
3754 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 3755 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 3756
3757 return features;
3758}
3759
3947ca18
DJ		 3760static void mlx5e_tx_timeout(struct net_device *dev)
3761{
3762 struct mlx5e_priv *priv = netdev_priv(dev);
3763 bool sched_work = false;
3764 int i;
3765
3766 netdev_err(dev, "TX timeout detected\n");
3767
6a9764ef 3768 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3769 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3770
2c1ccc99 3771 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3772 continue;
3773 sched_work = true;
c0f1147d 3774 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3775 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3776 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3777 }
3778
3779 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3780 schedule_work(&priv->tx_timeout_work);
3781}
3782
86994156
RS		 3783static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3784{
3785 struct mlx5e_priv *priv = netdev_priv(netdev);
3786 struct bpf_prog *old_prog;
3787 int err = 0;
3788 bool reset, was_opened;
3789 int i;
3790
3791 mutex_lock(&priv->state_lock);
3792
3793 if ((netdev->features & NETIF_F_LRO) && prog) {
3794 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3795 err = -EINVAL;
3796 goto unlock;
3797 }
3798
547eede0
IT		 3799 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3800 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3801 err = -EINVAL;
3802 goto unlock;
3803 }
3804
86994156
RS		 3805 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3806 /* no need for full reset when exchanging programs */
6a9764ef 3807 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3808
3809 if (was_opened && reset)
3810 mlx5e_close_locked(netdev);
c54c0629
DB		 3811 if (was_opened && !reset) {
3812 /* num_channels is invariant here, so we can take the
3813 * batched reference right upfront.
3814 */
6a9764ef 3815 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3816 if (IS_ERR(prog)) {
3817 err = PTR_ERR(prog);
3818 goto unlock;
3819 }
3820 }
86994156 3821
c54c0629
DB		 3822 /* exchange programs, extra prog reference we got from caller
3823 * as long as we don't fail from this point onwards.
3824 */
6a9764ef 3825 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3826 if (old_prog)
3827 bpf_prog_put(old_prog);
3828
3829 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3830 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3831
3832 if (was_opened && reset)
3833 mlx5e_open_locked(netdev);
3834
3835 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3836 goto unlock;
3837
3838 /* exchanging programs w/o reset, we update ref counts on behalf
3839 * of the channels RQs here.
3840 */
ff9c852f
SM		 3841 for (i = 0; i < priv->channels.num; i++) {
3842 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3843
c0f1147d 3844 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3845 napi_synchronize(&c->napi);
3846 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3847
3848 old_prog = xchg(&c->rq.xdp_prog, prog);
3849
c0f1147d 3850 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 3851 /* napi_schedule in case we have missed anything */
86994156
RS		 3852 napi_schedule(&c->napi);
3853
3854 if (old_prog)
3855 bpf_prog_put(old_prog);
3856 }
3857
3858unlock:
3859 mutex_unlock(&priv->state_lock);
3860 return err;
3861}
3862
821b2e29 3863static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3864{
3865 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3866 const struct bpf_prog *xdp_prog;
3867 u32 prog_id = 0;
86994156 3868
821b2e29
MKL		 3869 mutex_lock(&priv->state_lock);
3870 xdp_prog = priv->channels.params.xdp_prog;
3871 if (xdp_prog)
3872 prog_id = xdp_prog->aux->id;
3873 mutex_unlock(&priv->state_lock);
3874
3875 return prog_id;
86994156
RS		 3876}
3877
f4e63525 3878static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 3879{
3880 switch (xdp->command) {
3881 case XDP_SETUP_PROG:
3882 return mlx5e_xdp_set(dev, xdp->prog);
3883 case XDP_QUERY_PROG:
821b2e29
MKL		 3884 xdp->prog_id = mlx5e_xdp_query(dev);
3885 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3886 return 0;
3887 default:
3888 return -EINVAL;
3889 }
3890}
3891
80378384
CO		 3892#ifdef CONFIG_NET_POLL_CONTROLLER
3893/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3894 * reenabling interrupts.
3895 */
3896static void mlx5e_netpoll(struct net_device *dev)
3897{
3898 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3899 struct mlx5e_channels *chs = &priv->channels;
3900
80378384
CO		 3901 int i;
3902
ff9c852f
SM		 3903 for (i = 0; i < chs->num; i++)
3904 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3905}
3906#endif
3907
e80541ec 3908static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 3909 .ndo_open = mlx5e_open,
3910 .ndo_stop = mlx5e_close,
3911 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 3912 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 3913 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3914 .ndo_get_stats64 = mlx5e_get_stats,
3915 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3916 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3917 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3918 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3919 .ndo_set_features = mlx5e_set_features,
7d92d580 3920 .ndo_fix_features = mlx5e_fix_features,
b0eed40e
SM		 3921 .ndo_change_mtu = mlx5e_change_mtu,
3922 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3923 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 3924 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3925 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3926 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3927#ifdef CONFIG_RFS_ACCEL
3928 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3929#endif
3947ca18 3930 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 3931 .ndo_bpf = mlx5e_xdp,
80378384
CO		 3932#ifdef CONFIG_NET_POLL_CONTROLLER
3933 .ndo_poll_controller = mlx5e_netpoll,
3934#endif
e80541ec 3935#ifdef CONFIG_MLX5_ESWITCH
706b3583 3936 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 3937 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3938 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3939 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3940 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3941 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3942 .ndo_get_vf_config = mlx5e_get_vf_config,
3943 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3944 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 3945 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3946 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 3947#endif
f62b8bb8
AV		 3948};
3949
3950static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3951{
3952 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3953 return -EOPNOTSUPP;
f62b8bb8
AV		 3954 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3955 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3956 !MLX5_CAP_ETH(mdev, csum_cap) ||
3957 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3958 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3959 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3960 MLX5_CAP_FLOWTABLE(mdev,
3961 flow_table_properties_nic_receive.max_ft_level)
3962 < 3) {
f62b8bb8
AV		 3963 mlx5_core_warn(mdev,
3964 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3965 return -EOPNOTSUPP;
f62b8bb8 3966 }
66189961
TT		 3967 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3968 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3969 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3970 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3971
f62b8bb8
AV		 3972 return 0;
3973}
3974
58d52291
AS		 3975u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3976{
3977 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3978
3979 return bf_buf_size -
3980 sizeof(struct mlx5e_tx_wqe) +
3981 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3982}
3983
d4b6c488 3984void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 3985 int num_channels)
3986{
3987 int i;
3988
3989 for (i = 0; i < len; i++)
3990 indirection_rqt[i] = i % num_channels;
3991}
3992
b797a684
SM		 3993static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3994{
3995 enum pcie_link_width width;
3996 enum pci_bus_speed speed;
3997 int err = 0;
3998
3999 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
4000 if (err)
4001 return err;
4002
4003 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
4004 return -EINVAL;
4005
4006 switch (speed) {
4007 case PCIE_SPEED_2_5GT:
4008 *pci_bw = 2500 * width;
4009 break;
4010 case PCIE_SPEED_5_0GT:
4011 *pci_bw = 5000 * width;
4012 break;
4013 case PCIE_SPEED_8_0GT:
4014 *pci_bw = 8000 * width;
4015 break;
4016 default:
4017 return -EINVAL;
4018 }
4019
4020 return 0;
4021}
4022
4023static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
4024{
4025 return (link_speed && pci_bw &&
4026 (pci_bw < 40000) && (pci_bw < link_speed));
4027}
4028
0f6e4cf6
EBE		 4029static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
4030{
4031 return !(link_speed && pci_bw &&
4032 (pci_bw <= 16000) && (pci_bw < link_speed));
4033}
4034
0088cbbc
TG		 4035void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4036{
4037 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4038
4039 params->tx_cq_moderation.pkts =
4040 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4041 params->tx_cq_moderation.usec =
4042 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4043
4044 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4045 params->tx_cq_moderation.usec =
4046 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4047
4048 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4049 params->tx_cq_moderation.cq_period_mode ==
4050 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4051}
4052
9908aa29
TT		 4053void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4054{
0088cbbc 4055 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
9908aa29
TT		 4056
4057 params->rx_cq_moderation.pkts =
4058 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4059 params->rx_cq_moderation.usec =
0088cbbc 4060 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
9908aa29
TT		 4061
4062 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4063 params->rx_cq_moderation.usec =
4064 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 4065
9a317425
AG		 4066 if (params->rx_dim_enabled) {
4067 switch (cq_period_mode) {
4068 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
4069 params->rx_cq_moderation =
4070 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
4071 break;
4072 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
4073 default:
4074 params->rx_cq_moderation =
4075 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
4076 }
4077 }
457fcd8a 4078
6a9764ef 4079 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4080 params->rx_cq_moderation.cq_period_mode ==
4081 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4082}
4083
2b029556
SM		 4084u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4085{
4086 int i;
4087
4088 /* The supported periods are organized in ascending order */
4089 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4090 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4091 break;
4092
4093 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4094}
4095
8f493ffd
SM		 4096void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4097 struct mlx5e_params *params,
4098 u16 max_channels)
f62b8bb8 4099{
6a9764ef 4100 u8 cq_period_mode = 0;
b797a684
SM		 4101 u32 link_speed = 0;
4102 u32 pci_bw = 0;
2fc4bfb7 4103
6a9764ef
SM		 4104 params->num_channels = max_channels;
4105 params->num_tc = 1;
2b029556 4106
0f6e4cf6
EBE		 4107 mlx5e_get_max_linkspeed(mdev, &link_speed);
4108 mlx5e_get_pci_bw(mdev, &pci_bw);
4109 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
4110 link_speed, pci_bw);
4111
6a9764ef
SM		 4112 /* SQ */
4113 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4114 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4115 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4116
b797a684 4117 /* set CQE compression */
6a9764ef 4118 params->rx_cqe_compress_def = false;
b797a684 4119 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4120 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 4121 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 4122
6a9764ef
SM		 4123 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4124
4125 /* RQ */
4126 mlx5e_set_rq_params(mdev, params);
b797a684 4127
6a9764ef 4128 /* HW LRO */
c139dbfd 4129
5426a0b2 4130 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4131 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 4132 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 4133 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4134
6a9764ef
SM		 4135 /* CQ moderation params */
4136 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4137 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4138 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4139 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
6a9764ef 4140 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
0088cbbc 4141 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
9908aa29 4142
6a9764ef
SM		 4143 /* TX inline */
4144 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
fbcb127e 4145 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4146
6a9764ef
SM		 4147 /* RSS */
4148 params->rss_hfunc = ETH_RSS_HASH_XOR;
4149 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4150 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4151 MLX5E_INDIR_RQT_SIZE, max_channels);
4152}
f62b8bb8 4153
6a9764ef
SM		 4154static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4155 struct net_device *netdev,
4156 const struct mlx5e_profile *profile,
4157 void *ppriv)
4158{
4159 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4160
6a9764ef
SM		 4161 priv->mdev = mdev;
4162 priv->netdev = netdev;
4163 priv->profile = profile;
4164 priv->ppriv = ppriv;
79c48764 4165 priv->msglevel = MLX5E_MSG_LEVEL;
c139dbfd 4166 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
2d75b2bc 4167
6a9764ef 4168 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 4169
f62b8bb8
AV		 4170 mutex_init(&priv->state_lock);
4171
4172 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4173 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4174 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8 4175 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
237f258c
FD		 4176
4177 mlx5e_timestamp_init(priv);
f62b8bb8
AV		 4178}
4179
4180static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4181{
4182 struct mlx5e_priv *priv = netdev_priv(netdev);
4183
e1d7d349 4184 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4185 if (is_zero_ether_addr(netdev->dev_addr) &&
4186 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4187 eth_hw_addr_random(netdev);
4188 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4189 }
f62b8bb8
AV		 4190}
4191
e80541ec 4192#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4193static const struct switchdev_ops mlx5e_switchdev_ops = {
4194 .switchdev_port_attr_get = mlx5e_attr_get,
4195};
e80541ec 4196#endif
cb67b832 4197
6bfd390b 4198static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4199{
4200 struct mlx5e_priv *priv = netdev_priv(netdev);
4201 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4202 bool fcs_supported;
4203 bool fcs_enabled;
f62b8bb8
AV		 4204
4205 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4206
e80541ec
SM		 4207 netdev->netdev_ops = &mlx5e_netdev_ops;
4208
08fb1dac 4209#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4210 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4211 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4212#endif
66e49ded 4213
f62b8bb8
AV		 4214 netdev->watchdog_timeo = 15 * HZ;
4215
4216 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4217
12be4b21 4218 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4219 netdev->vlan_features |= NETIF_F_IP_CSUM;
4220 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4221 netdev->vlan_features |= NETIF_F_GRO;
4222 netdev->vlan_features |= NETIF_F_TSO;
4223 netdev->vlan_features |= NETIF_F_TSO6;
4224 netdev->vlan_features |= NETIF_F_RXCSUM;
4225 netdev->vlan_features |= NETIF_F_RXHASH;
4226
4227 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4228 netdev->vlan_features |= NETIF_F_LRO;
4229
4230 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4231 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4232 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4233 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4234 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4235
27299841
GP		 4236 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4237 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
b3f63c3d 4238 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4239 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4240 netdev->hw_enc_features |= NETIF_F_TSO;
4241 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4242 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4243 }
4244
4245 if (mlx5e_vxlan_allowed(mdev)) {
4246 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4247 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4248 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4249 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4250 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4251 }
4252
27299841
GP		 4253 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4254 netdev->hw_features |= NETIF_F_GSO_GRE |
4255 NETIF_F_GSO_GRE_CSUM;
4256 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4257 NETIF_F_GSO_GRE_CSUM;
4258 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4259 NETIF_F_GSO_GRE_CSUM;
4260 }
4261
94cb1ebb
EBE		 4262 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4263
4264 if (fcs_supported)
4265 netdev->hw_features |= NETIF_F_RXALL;
4266
102722fc
GE		 4267 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4268 netdev->hw_features |= NETIF_F_RXFCS;
4269
f62b8bb8 4270 netdev->features = netdev->hw_features;
6a9764ef 4271 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4272 netdev->features &= ~NETIF_F_LRO;
4273
94cb1ebb
EBE		 4274 if (fcs_enabled)
4275 netdev->features &= ~NETIF_F_RXALL;
4276
102722fc
GE		 4277 if (!priv->channels.params.scatter_fcs_en)
4278 netdev->features &= ~NETIF_F_RXFCS;
4279
e8f887ac
AV		 4280#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4281 if (FT_CAP(flow_modify_en) &&
4282 FT_CAP(modify_root) &&
4283 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4284 FT_CAP(flow_table_modify)) {
4285 netdev->hw_features |= NETIF_F_HW_TC;
4286#ifdef CONFIG_RFS_ACCEL
4287 netdev->hw_features |= NETIF_F_NTUPLE;
4288#endif
4289 }
e8f887ac 4290
f62b8bb8 4291 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4292 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4293
4294 netdev->priv_flags |= IFF_UNICAST_FLT;
4295
4296 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4297
e80541ec 4298#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
a9f7705f 4299 if (MLX5_VPORT_MANAGER(mdev))
cb67b832
HHZ		 4300 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4301#endif
547eede0
IT		 4302
4303 mlx5e_ipsec_build_netdev(priv);
f62b8bb8
AV		 4304}
4305
593cf338
RS		 4306static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4307{
4308 struct mlx5_core_dev *mdev = priv->mdev;
4309 int err;
4310
4311 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4312 if (err) {
4313 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4314 priv->q_counter = 0;
4315 }
4316}
4317
4318static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4319{
4320 if (!priv->q_counter)
4321 return;
4322
4323 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4324}
4325
6bfd390b
HHZ		 4326static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4327 struct net_device *netdev,
127ea380
HHZ		 4328 const struct mlx5e_profile *profile,
4329 void *ppriv)
6bfd390b
HHZ		 4330{
4331 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4332 int err;
6bfd390b 4333
127ea380 4334 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4335 err = mlx5e_ipsec_init(priv);
4336 if (err)
4337 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
6bfd390b
HHZ		 4338 mlx5e_build_nic_netdev(netdev);
4339 mlx5e_vxlan_init(priv);
4340}
4341
4342static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4343{
547eede0 4344 mlx5e_ipsec_cleanup(priv);
6bfd390b
HHZ		 4345 mlx5e_vxlan_cleanup(priv);
4346}
4347
4348static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4349{
4350 struct mlx5_core_dev *mdev = priv->mdev;
4351 int err;
6bfd390b 4352
8f493ffd
SM		 4353 err = mlx5e_create_indirect_rqt(priv);
4354 if (err)
6bfd390b 4355 return err;
6bfd390b
HHZ		 4356
4357 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4358 if (err)
6bfd390b 4359 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4360
4361 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4362 if (err)
6bfd390b 4363 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4364
4365 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4366 if (err)
6bfd390b 4367 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4368
4369 err = mlx5e_create_flow_steering(priv);
4370 if (err) {
4371 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4372 goto err_destroy_direct_tirs;
4373 }
4374
4375 err = mlx5e_tc_init(priv);
4376 if (err)
4377 goto err_destroy_flow_steering;
4378
4379 return 0;
4380
4381err_destroy_flow_steering:
4382 mlx5e_destroy_flow_steering(priv);
4383err_destroy_direct_tirs:
4384 mlx5e_destroy_direct_tirs(priv);
4385err_destroy_indirect_tirs:
4386 mlx5e_destroy_indirect_tirs(priv);
4387err_destroy_direct_rqts:
8f493ffd 4388 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4389err_destroy_indirect_rqts:
4390 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4391 return err;
4392}
4393
4394static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4395{
6bfd390b
HHZ		 4396 mlx5e_tc_cleanup(priv);
4397 mlx5e_destroy_flow_steering(priv);
4398 mlx5e_destroy_direct_tirs(priv);
4399 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4400 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4401 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4402}
4403
4404static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4405{
4406 int err;
4407
4408 err = mlx5e_create_tises(priv);
4409 if (err) {
4410 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4411 return err;
4412 }
4413
4414#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4415 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4416#endif
4417 return 0;
4418}
4419
4420static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4421{
4422 struct net_device *netdev = priv->netdev;
4423 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4424 u16 max_mtu;
4425
4426 mlx5e_init_l2_addr(priv);
4427
63bfd399
EBE		 4428 /* Marking the link as currently not needed by the Driver */
4429 if (!netif_running(netdev))
4430 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4431
2c3b5bee
SM		 4432 /* MTU range: 68 - hw-specific max */
4433 netdev->min_mtu = ETH_MIN_MTU;
4434 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
c139dbfd 4435 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
2c3b5bee 4436 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4437
7907f23a
AH		 4438 mlx5_lag_add(mdev, netdev);
4439
6bfd390b 4440 mlx5e_enable_async_events(priv);
127ea380 4441
a9f7705f 4442 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39 4443 mlx5e_register_vport_reps(priv);
2c3b5bee 4444
610e89e0
SM		 4445 if (netdev->reg_state != NETREG_REGISTERED)
4446 return;
2a5e7a13
HN		 4447#ifdef CONFIG_MLX5_CORE_EN_DCB
4448 mlx5e_dcbnl_init_app(priv);
4449#endif
610e89e0
SM		 4450 /* Device already registered: sync netdev system state */
4451 if (mlx5e_vxlan_allowed(mdev)) {
4452 rtnl_lock();
4453 udp_tunnel_get_rx_info(netdev);
4454 rtnl_unlock();
4455 }
4456
4457 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4458
4459 rtnl_lock();
4460 if (netif_running(netdev))
4461 mlx5e_open(netdev);
4462 netif_device_attach(netdev);
4463 rtnl_unlock();
6bfd390b
HHZ		 4464}
4465
4466static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4467{
3deef8ce 4468 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4469
2a5e7a13
HN		 4470#ifdef CONFIG_MLX5_CORE_EN_DCB
4471 if (priv->netdev->reg_state == NETREG_REGISTERED)
4472 mlx5e_dcbnl_delete_app(priv);
4473#endif
4474
2c3b5bee
SM		 4475 rtnl_lock();
4476 if (netif_running(priv->netdev))
4477 mlx5e_close(priv->netdev);
4478 netif_device_detach(priv->netdev);
4479 rtnl_unlock();
4480
6bfd390b 4481 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4482
a9f7705f 4483 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39
SM		 4484 mlx5e_unregister_vport_reps(priv);
4485
6bfd390b 4486 mlx5e_disable_async_events(priv);
3deef8ce 4487 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4488}
4489
4490static const struct mlx5e_profile mlx5e_nic_profile = {
4491 .init = mlx5e_nic_init,
4492 .cleanup = mlx5e_nic_cleanup,
4493 .init_rx = mlx5e_init_nic_rx,
4494 .cleanup_rx = mlx5e_cleanup_nic_rx,
4495 .init_tx = mlx5e_init_nic_tx,
4496 .cleanup_tx = mlx5e_cleanup_nic_tx,
4497 .enable = mlx5e_nic_enable,
4498 .disable = mlx5e_nic_disable,
3834a5e6 4499 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4500 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4501 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4502 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4503 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4504 .max_tc = MLX5E_MAX_NUM_TC,
4505};
4506
2c3b5bee
SM		 4507/* mlx5e generic netdev management API (move to en_common.c) */
4508
26e59d80
MHY		 4509struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4510 const struct mlx5e_profile *profile,
4511 void *ppriv)
f62b8bb8 4512{
26e59d80 4513 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4514 struct net_device *netdev;
4515 struct mlx5e_priv *priv;
f62b8bb8 4516
08fb1dac 4517 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4518 nch * profile->max_tc,
08fb1dac 4519 nch);
f62b8bb8
AV		 4520 if (!netdev) {
4521 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4522 return NULL;
4523 }
4524
be4891af
SM		 4525#ifdef CONFIG_RFS_ACCEL
4526 netdev->rx_cpu_rmap = mdev->rmap;
4527#endif
4528
127ea380 4529 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4530
4531 netif_carrier_off(netdev);
4532
4533 priv = netdev_priv(netdev);
4534
7bb29755
MF		 4535 priv->wq = create_singlethread_workqueue("mlx5e");
4536 if (!priv->wq)
26e59d80
MHY		 4537 goto err_cleanup_nic;
4538
4539 return netdev;
4540
4541err_cleanup_nic:
31ac9338
OG		 4542 if (profile->cleanup)
4543 profile->cleanup(priv);
26e59d80
MHY		 4544 free_netdev(netdev);
4545
4546 return NULL;
4547}
4548
2c3b5bee 4549int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4550{
2c3b5bee 4551 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4552 const struct mlx5e_profile *profile;
26e59d80
MHY		 4553 int err;
4554
26e59d80
MHY		 4555 profile = priv->profile;
4556 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4557
6bfd390b
HHZ		 4558 err = profile->init_tx(priv);
4559 if (err)
ec8b9981 4560 goto out;
5c50368f 4561
a43b25da 4562 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4563 if (err) {
4564 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4565 goto err_cleanup_tx;
5c50368f
AS		 4566 }
4567
6bfd390b
HHZ		 4568 err = profile->init_rx(priv);
4569 if (err)
5c50368f 4570 goto err_close_drop_rq;
5c50368f 4571
593cf338
RS		 4572 mlx5e_create_q_counter(priv);
4573
6bfd390b
HHZ		 4574 if (profile->enable)
4575 profile->enable(priv);
f62b8bb8 4576
26e59d80 4577 return 0;
5c50368f
AS		 4578
4579err_close_drop_rq:
a43b25da 4580 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4581
6bfd390b
HHZ		 4582err_cleanup_tx:
4583 profile->cleanup_tx(priv);
5c50368f 4584
26e59d80
MHY		 4585out:
4586 return err;
f62b8bb8
AV		 4587}
4588
2c3b5bee 4589void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4590{
26e59d80
MHY		 4591 const struct mlx5e_profile *profile = priv->profile;
4592
4593 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4594
37f304d1
SM		 4595 if (profile->disable)
4596 profile->disable(priv);
4597 flush_workqueue(priv->wq);
4598
26e59d80
MHY		 4599 mlx5e_destroy_q_counter(priv);
4600 profile->cleanup_rx(priv);
a43b25da 4601 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4602 profile->cleanup_tx(priv);
26e59d80
MHY		 4603 cancel_delayed_work_sync(&priv->update_stats_work);
4604}
4605
2c3b5bee
SM		 4606void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4607{
4608 const struct mlx5e_profile *profile = priv->profile;
4609 struct net_device *netdev = priv->netdev;
4610
4611 destroy_workqueue(priv->wq);
4612 if (profile->cleanup)
4613 profile->cleanup(priv);
4614 free_netdev(netdev);
4615}
4616
26e59d80
MHY		 4617/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4618 * hardware contexts and to connect it to the current netdev.
4619 */
4620static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4621{
4622 struct mlx5e_priv *priv = vpriv;
4623 struct net_device *netdev = priv->netdev;
4624 int err;
4625
4626 if (netif_device_present(netdev))
4627 return 0;
4628
4629 err = mlx5e_create_mdev_resources(mdev);
4630 if (err)
4631 return err;
4632
2c3b5bee 4633 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4634 if (err) {
4635 mlx5e_destroy_mdev_resources(mdev);
4636 return err;
4637 }
4638
4639 return 0;
4640}
4641
4642static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4643{
4644 struct mlx5e_priv *priv = vpriv;
4645 struct net_device *netdev = priv->netdev;
4646
4647 if (!netif_device_present(netdev))
4648 return;
4649
2c3b5bee 4650 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4651 mlx5e_destroy_mdev_resources(mdev);
4652}
4653
b50d292b
HHZ		 4654static void *mlx5e_add(struct mlx5_core_dev *mdev)
4655{
07c9f1e5
SM		 4656 struct net_device *netdev;
4657 void *rpriv = NULL;
26e59d80 4658 void *priv;
26e59d80 4659 int err;
b50d292b 4660
26e59d80
MHY		 4661 err = mlx5e_check_required_hca_cap(mdev);
4662 if (err)
b50d292b
HHZ		 4663 return NULL;
4664
e80541ec 4665#ifdef CONFIG_MLX5_ESWITCH
a9f7705f 4666 if (MLX5_VPORT_MANAGER(mdev)) {
07c9f1e5 4667 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 4668 if (!rpriv) {
07c9f1e5 4669 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 4670 return NULL;
4671 }
1d447a39 4672 }
e80541ec 4673#endif
127ea380 4674
1d447a39 4675 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4676 if (!netdev) {
4677 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 4678 goto err_free_rpriv;
26e59d80
MHY		 4679 }
4680
4681 priv = netdev_priv(netdev);
4682
4683 err = mlx5e_attach(mdev, priv);
4684 if (err) {
4685 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4686 goto err_destroy_netdev;
4687 }
4688
4689 err = register_netdev(netdev);
4690 if (err) {
4691 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4692 goto err_detach;
b50d292b 4693 }
26e59d80 4694
2a5e7a13
HN		 4695#ifdef CONFIG_MLX5_CORE_EN_DCB
4696 mlx5e_dcbnl_init_app(priv);
4697#endif
26e59d80
MHY		 4698 return priv;
4699
4700err_detach:
4701 mlx5e_detach(mdev, priv);
26e59d80 4702err_destroy_netdev:
2c3b5bee 4703 mlx5e_destroy_netdev(priv);
07c9f1e5 4704err_free_rpriv:
1d447a39 4705 kfree(rpriv);
26e59d80 4706 return NULL;
b50d292b
HHZ		 4707}
4708
b50d292b
HHZ		 4709static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4710{
4711 struct mlx5e_priv *priv = vpriv;
1d447a39 4712 void *ppriv = priv->ppriv;
127ea380 4713
2a5e7a13
HN		 4714#ifdef CONFIG_MLX5_CORE_EN_DCB
4715 mlx5e_dcbnl_delete_app(priv);
4716#endif
5e1e93c7 4717 unregister_netdev(priv->netdev);
26e59d80 4718 mlx5e_detach(mdev, vpriv);
2c3b5bee 4719 mlx5e_destroy_netdev(priv);
1d447a39 4720 kfree(ppriv);
b50d292b
HHZ		 4721}
4722
f62b8bb8
AV		 4723static void *mlx5e_get_netdev(void *vpriv)
4724{
4725 struct mlx5e_priv *priv = vpriv;
4726
4727 return priv->netdev;
4728}
4729
4730static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4731 .add = mlx5e_add,
4732 .remove = mlx5e_remove,
26e59d80
MHY		 4733 .attach = mlx5e_attach,
4734 .detach = mlx5e_detach,
f62b8bb8
AV		 4735 .event = mlx5e_async_event,
4736 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4737 .get_dev = mlx5e_get_netdev,
4738};
4739
4740void mlx5e_init(void)
4741{
2ac9cfe7 4742 mlx5e_ipsec_build_inverse_table();
665bc539 4743 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4744 mlx5_register_interface(&mlx5e_interface);
4745}
4746
4747void mlx5e_cleanup(void)
4748{
4749 mlx5_unregister_interface(&mlx5e_interface);
4750}
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