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Merge branch 'mlx4-drivers-version-update'
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
9908aa29 58 u8 cq_period_mode;
f62b8bb8
AV		 59};
60
61struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
b5503b99 64 struct mlx5e_sq_param xdp_sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
2fc4bfb7
SM		 71static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72{
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76}
77
6a9764ef
SM		 78void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 80{
6a9764ef
SM		 81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
2fc4bfb7 84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 85 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 96 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 99
100 /* Extra room needed for build_skb */
6a9764ef 101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 103 }
2fc4bfb7 104
6a9764ef
SM		 105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 110}
111
6a9764ef 112static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 113{
6a9764ef
SM		 114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
2fc4bfb7
SM		 116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 118 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 119}
120
f62b8bb8
AV		 121static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122{
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
e7546514 127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 128
87424ad5
SD		 129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 131 netif_carrier_on(priv->netdev);
87424ad5
SD		 132 } else {
133 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 134 netif_carrier_off(priv->netdev);
87424ad5 135 }
f62b8bb8
AV		 136}
137
138static void mlx5e_update_carrier_work(struct work_struct *work)
139{
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
142
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
147}
148
3947ca18
DJ		 149static void mlx5e_tx_timeout_work(struct work_struct *work)
150{
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 tx_timeout_work);
153 int err;
154
155 rtnl_lock();
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
158 goto unlock;
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
161 if (err)
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
163 err);
164unlock:
165 mutex_unlock(&priv->state_lock);
166 rtnl_unlock();
167}
168
9218b44d 169static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 170{
1510d728 171 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
9218b44d 174 u64 tx_offload_none = 0;
f62b8bb8
AV		 175 int i, j;
176
9218b44d 177 memset(s, 0, sizeof(*s));
ff9c852f
SM		 178 for (i = 0; i < priv->channels.num; i++) {
179 struct mlx5e_channel *c = priv->channels.c[i];
180
181 rq_stats = &c->rq.stats;
f62b8bb8 182
faf4478b
GP		 183 s->rx_packets += rq_stats->packets;
184 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 185 s->rx_lro_packets += rq_stats->lro_packets;
186 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 187 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 188 s->rx_csum_complete += rq_stats->csum_complete;
189 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 190 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 191 s->rx_xdp_tx += rq_stats->xdp_tx;
192 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 193 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 194 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 195 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 196 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
197 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 198 s->rx_cache_reuse += rq_stats->cache_reuse;
199 s->rx_cache_full += rq_stats->cache_full;
200 s->rx_cache_empty += rq_stats->cache_empty;
201 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 202
6a9764ef 203 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 204 sq_stats = &c->sq[j].stats;
f62b8bb8 205
faf4478b
GP		 206 s->tx_packets += sq_stats->packets;
207 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 208 s->tx_tso_packets += sq_stats->tso_packets;
209 s->tx_tso_bytes += sq_stats->tso_bytes;
210 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
211 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 212 s->tx_queue_stopped += sq_stats->stopped;
213 s->tx_queue_wake += sq_stats->wake;
214 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 215 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 216 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
217 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 218 }
219 }
220
9218b44d 221 /* Update calculated offload counters */
bfe6d8d1
GP		 222 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
223 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 224
bfe6d8d1 225 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 226 priv->stats.pport.phy_counters,
227 counter_set.phys_layer_cntrs.link_down_events);
1510d728 228 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 229}
230
231static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
232{
233 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
234 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 235 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 236 struct mlx5_core_dev *mdev = priv->mdev;
237
f62b8bb8
AV		 238 MLX5_SET(query_vport_counter_in, in, opcode,
239 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
240 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
241 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
242
9218b44d
GP		 243 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
244}
245
246static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
247{
248 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
249 struct mlx5_core_dev *mdev = priv->mdev;
250 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 251 int prio;
9218b44d
GP		 252 void *out;
253 u32 *in;
254
1b9a07ee 255 in = kvzalloc(sz, GFP_KERNEL);
9218b44d 256 if (!in)
1b9a07ee 257 return;
f62b8bb8 258
9218b44d 259 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 260
9218b44d
GP		 261 out = pstats->IEEE_802_3_counters;
262 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
263 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 272
121fcdc8
GP		 273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
5db0a4f6
GP		 277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 }
282
cf678570
GP		 283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
289 }
290
9218b44d
GP		 291 kvfree(in);
292}
293
294static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
295{
296 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
297
298 if (!priv->q_counter)
299 return;
300
301 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
302 &qcnt->rx_out_of_buffer);
303}
304
0f7f3481
GP		 305static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
306{
307 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
308 struct mlx5_core_dev *mdev = priv->mdev;
309 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
310 void *out;
311 u32 *in;
312
313 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
314 return;
315
1b9a07ee 316 in = kvzalloc(sz, GFP_KERNEL);
0f7f3481
GP		 317 if (!in)
318 return;
319
320 out = pcie_stats->pcie_perf_counters;
321 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
322 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
323
324 kvfree(in);
325}
326
9218b44d
GP		 327void mlx5e_update_stats(struct mlx5e_priv *priv)
328{
3dd69e3d 329 mlx5e_update_pcie_counters(priv);
9218b44d 330 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 331 mlx5e_update_vport_counters(priv);
332 mlx5e_update_q_counter(priv);
121fcdc8 333 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 334}
335
cb67b832 336void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 337{
338 struct delayed_work *dwork = to_delayed_work(work);
339 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
340 update_stats_work);
341 mutex_lock(&priv->state_lock);
342 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 343 priv->profile->update_stats(priv);
7bb29755
MF		 344 queue_delayed_work(priv->wq, dwork,
345 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 346 }
347 mutex_unlock(&priv->state_lock);
348}
349
daa21560
TT		 350static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
351 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 352{
daa21560 353 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 354 struct ptp_clock_event ptp_event;
355 struct mlx5_eqe *eqe = NULL;
daa21560 356
e0f46eb9 357 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 358 return;
359
f62b8bb8
AV		 360 switch (event) {
361 case MLX5_DEV_EVENT_PORT_UP:
362 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 363 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 364 break;
ee7f1220
EE		 365 case MLX5_DEV_EVENT_PPS:
366 eqe = (struct mlx5_eqe *)param;
367 ptp_event.type = PTP_CLOCK_EXTTS;
368 ptp_event.index = eqe->data.pps.pin;
369 ptp_event.timestamp =
370 timecounter_cyc2time(&priv->tstamp.clock,
371 be64_to_cpu(eqe->data.pps.time_stamp));
372 mlx5e_pps_event_handler(vpriv, &ptp_event);
373 break;
f62b8bb8
AV		 374 default:
375 break;
376 }
377}
378
f62b8bb8
AV		 379static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
380{
e0f46eb9 381 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 382}
383
384static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
385{
e0f46eb9 386 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 387 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 388}
389
7e426671
TT		 390static inline int mlx5e_get_wqe_mtt_sz(void)
391{
392 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
393 * To avoid copying garbage after the mtt array, we allocate
394 * a little more.
395 */
396 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
397 MLX5_UMR_MTT_ALIGNMENT);
398}
399
31391048
SM		 400static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
401 struct mlx5e_icosq *sq,
402 struct mlx5e_umr_wqe *wqe,
403 u16 ix)
7e426671
TT		 404{
405 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
406 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
407 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 408 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 409 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
410 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
411
412 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
413 ds_cnt);
414 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
415 cseg->imm = rq->mkey_be;
416
417 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 418 ucseg->xlt_octowords =
7e426671
TT		 419 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
420 ucseg->bsf_octowords =
421 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
422 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
423
424 dseg->lkey = sq->mkey_be;
425 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
426}
427
428static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
429 struct mlx5e_channel *c)
430{
431 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
432 int mtt_sz = mlx5e_get_wqe_mtt_sz();
433 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
434 int i;
435
21c59685
SM		 436 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
437 GFP_KERNEL, cpu_to_node(c->cpu));
438 if (!rq->mpwqe.info)
7e426671
TT		 439 goto err_out;
440
441 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 442 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 443 cpu_to_node(c->cpu));
21c59685 444 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 445 goto err_free_wqe_info;
446
447 for (i = 0; i < wq_sz; i++) {
21c59685 448 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 449
21c59685 450 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 451 MLX5_UMR_ALIGN);
452 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
453 PCI_DMA_TODEVICE);
454 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
455 goto err_unmap_mtts;
456
457 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
458 }
459
460 return 0;
461
462err_unmap_mtts:
463 while (--i >= 0) {
21c59685 464 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 465
466 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
467 PCI_DMA_TODEVICE);
468 }
21c59685 469 kfree(rq->mpwqe.mtt_no_align);
7e426671 470err_free_wqe_info:
21c59685 471 kfree(rq->mpwqe.info);
7e426671
TT		 472
473err_out:
474 return -ENOMEM;
475}
476
477static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
478{
479 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
480 int mtt_sz = mlx5e_get_wqe_mtt_sz();
481 int i;
482
483 for (i = 0; i < wq_sz; i++) {
21c59685 484 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 485
486 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
487 PCI_DMA_TODEVICE);
488 }
21c59685
SM		 489 kfree(rq->mpwqe.mtt_no_align);
490 kfree(rq->mpwqe.info);
7e426671
TT		 491}
492
a43b25da 493static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 494 u64 npages, u8 page_shift,
495 struct mlx5_core_mkey *umr_mkey)
3608ae77 496{
3608ae77
TT		 497 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
498 void *mkc;
499 u32 *in;
500 int err;
501
ec8b9981
TT		 502 if (!MLX5E_VALID_NUM_MTTS(npages))
503 return -EINVAL;
504
1b9a07ee 505 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 506 if (!in)
507 return -ENOMEM;
508
509 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
510
3608ae77
TT		 511 MLX5_SET(mkc, mkc, free, 1);
512 MLX5_SET(mkc, mkc, umr_en, 1);
513 MLX5_SET(mkc, mkc, lw, 1);
514 MLX5_SET(mkc, mkc, lr, 1);
515 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
516
517 MLX5_SET(mkc, mkc, qpn, 0xffffff);
518 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 519 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 520 MLX5_SET(mkc, mkc, translations_octword_size,
521 MLX5_MTT_OCTW(npages));
ec8b9981 522 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 523
ec8b9981 524 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 525
526 kvfree(in);
527 return err;
528}
529
a43b25da 530static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 531{
6a9764ef 532 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 533
a43b25da 534 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 535}
536
3b77235b 537static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 538 struct mlx5e_params *params,
539 struct mlx5e_rq_param *rqp,
3b77235b 540 struct mlx5e_rq *rq)
f62b8bb8 541{
a43b25da 542 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 543 void *rqc = rqp->rqc;
f62b8bb8 544 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 545 u32 byte_count;
1bfecfca
SM		 546 u32 frag_sz;
547 int npages;
f62b8bb8
AV		 548 int wq_sz;
549 int err;
550 int i;
551
6a9764ef 552 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 553
6a9764ef 554 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 555 &rq->wq_ctrl);
556 if (err)
557 return err;
558
559 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
560
561 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 562
6a9764ef 563 rq->wq_type = params->rq_wq_type;
7e426671
TT		 564 rq->pdev = c->pdev;
565 rq->netdev = c->netdev;
a43b25da 566 rq->tstamp = c->tstamp;
7e426671
TT		 567 rq->channel = c;
568 rq->ix = c->ix;
a43b25da 569 rq->mdev = mdev;
97bc402d 570
6a9764ef 571 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 572 if (IS_ERR(rq->xdp_prog)) {
573 err = PTR_ERR(rq->xdp_prog);
574 rq->xdp_prog = NULL;
575 goto err_rq_wq_destroy;
576 }
7e426671 577
d8bec2b2 578 if (rq->xdp_prog) {
b5503b99 579 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 580 rq->rx_headroom = XDP_PACKET_HEADROOM;
581 } else {
582 rq->buff.map_dir = DMA_FROM_DEVICE;
583 rq->rx_headroom = MLX5_RX_HEADROOM;
584 }
b5503b99 585
6a9764ef 586 switch (rq->wq_type) {
461017cb 587 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 588
461017cb 589 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 590 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 591
20fd0c19
SM		 592 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
593 if (!rq->handle_rx_cqe) {
594 err = -EINVAL;
595 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
596 goto err_rq_wq_destroy;
597 }
598
6a9764ef
SM		 599 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
600 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 601
602 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
603 byte_count = rq->buff.wqe_sz;
ec8b9981 604
a43b25da 605 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 606 if (err)
607 goto err_rq_wq_destroy;
ec8b9981
TT		 608 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
609
610 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
611 if (err)
612 goto err_destroy_umr_mkey;
461017cb
TT		 613 break;
614 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 615 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
616 GFP_KERNEL, cpu_to_node(c->cpu));
617 if (!rq->dma_info) {
461017cb
TT		 618 err = -ENOMEM;
619 goto err_rq_wq_destroy;
620 }
461017cb 621 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 622 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 623
20fd0c19
SM		 624 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
625 if (!rq->handle_rx_cqe) {
626 kfree(rq->dma_info);
627 err = -EINVAL;
628 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
629 goto err_rq_wq_destroy;
630 }
631
6a9764ef
SM		 632 rq->buff.wqe_sz = params->lro_en ?
633 params->lro_wqe_sz :
a43b25da 634 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 635 byte_count = rq->buff.wqe_sz;
636
637 /* calc the required page order */
d8bec2b2 638 frag_sz = rq->rx_headroom +
1bfecfca
SM		 639 byte_count /* packet data */ +
640 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
641 frag_sz = SKB_DATA_ALIGN(frag_sz);
642
643 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
644 rq->buff.page_order = order_base_2(npages);
645
461017cb 646 byte_count |= MLX5_HW_START_PADDING;
7e426671 647 rq->mkey_be = c->mkey_be;
461017cb 648 }
f62b8bb8
AV		 649
650 for (i = 0; i < wq_sz; i++) {
651 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
652
461017cb 653 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 654 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 655 }
656
cb3c7fd4 657 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 658 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 659 rq->page_cache.head = 0;
660 rq->page_cache.tail = 0;
661
f62b8bb8
AV		 662 return 0;
663
ec8b9981
TT		 664err_destroy_umr_mkey:
665 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
666
f62b8bb8 667err_rq_wq_destroy:
97bc402d
DB		 668 if (rq->xdp_prog)
669 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 670 mlx5_wq_destroy(&rq->wq_ctrl);
671
672 return err;
673}
674
3b77235b 675static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 676{
4415a031
TT		 677 int i;
678
86994156
RS		 679 if (rq->xdp_prog)
680 bpf_prog_put(rq->xdp_prog);
681
461017cb
TT		 682 switch (rq->wq_type) {
683 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 684 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 685 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 686 break;
687 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 688 kfree(rq->dma_info);
461017cb
TT		 689 }
690
4415a031
TT		 691 for (i = rq->page_cache.head; i != rq->page_cache.tail;
692 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
693 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
694
695 mlx5e_page_release(rq, dma_info, false);
696 }
f62b8bb8
AV		 697 mlx5_wq_destroy(&rq->wq_ctrl);
698}
699
6a9764ef
SM		 700static int mlx5e_create_rq(struct mlx5e_rq *rq,
701 struct mlx5e_rq_param *param)
f62b8bb8 702{
a43b25da 703 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 704
705 void *in;
706 void *rqc;
707 void *wq;
708 int inlen;
709 int err;
710
711 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
712 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 713 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 714 if (!in)
715 return -ENOMEM;
716
717 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
718 wq = MLX5_ADDR_OF(rqc, rqc, wq);
719
720 memcpy(rqc, param->rqc, sizeof(param->rqc));
721
97de9f31 722 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 723 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 724 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 725 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 726 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
727
728 mlx5_fill_page_array(&rq->wq_ctrl.buf,
729 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
730
7db22ffb 731 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 732
733 kvfree(in);
734
735 return err;
736}
737
36350114
GP		 738static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
739 int next_state)
f62b8bb8
AV		 740{
741 struct mlx5e_channel *c = rq->channel;
a43b25da 742 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 743
744 void *in;
745 void *rqc;
746 int inlen;
747 int err;
748
749 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 750 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 751 if (!in)
752 return -ENOMEM;
753
754 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
755
756 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
757 MLX5_SET(rqc, rqc, state, next_state);
758
7db22ffb 759 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 760
761 kvfree(in);
762
763 return err;
764}
765
102722fc
GE		 766static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
767{
768 struct mlx5e_channel *c = rq->channel;
769 struct mlx5e_priv *priv = c->priv;
770 struct mlx5_core_dev *mdev = priv->mdev;
771
772 void *in;
773 void *rqc;
774 int inlen;
775 int err;
776
777 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 778 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 779 if (!in)
780 return -ENOMEM;
781
782 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
783
784 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
785 MLX5_SET64(modify_rq_in, in, modify_bitmask,
786 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
787 MLX5_SET(rqc, rqc, scatter_fcs, enable);
788 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
789
790 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
791
792 kvfree(in);
793
794 return err;
795}
796
36350114
GP		 797static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
798{
799 struct mlx5e_channel *c = rq->channel;
a43b25da 800 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 801 void *in;
802 void *rqc;
803 int inlen;
804 int err;
805
806 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 807 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 808 if (!in)
809 return -ENOMEM;
810
811 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
812
813 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 814 MLX5_SET64(modify_rq_in, in, modify_bitmask,
815 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 816 MLX5_SET(rqc, rqc, vsd, vsd);
817 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
818
819 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
820
821 kvfree(in);
822
823 return err;
824}
825
3b77235b 826static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 827{
a43b25da 828 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 829}
830
831static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
832{
01c196a2 833 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 834 struct mlx5e_channel *c = rq->channel;
a43b25da 835
f62b8bb8 836 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 837 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 838
01c196a2 839 while (time_before(jiffies, exp_time)) {
6a9764ef 840 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 841 return 0;
842
843 msleep(20);
844 }
845
a43b25da 846 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 847 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 848 return -ETIMEDOUT;
849}
850
f2fde18c
SM		 851static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
852{
853 struct mlx5_wq_ll *wq = &rq->wq;
854 struct mlx5e_rx_wqe *wqe;
855 __be16 wqe_ix_be;
856 u16 wqe_ix;
857
8484f9ed
SM		 858 /* UMR WQE (if in progress) is always at wq->head */
859 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 860 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 861
f2fde18c
SM		 862 while (!mlx5_wq_ll_is_empty(wq)) {
863 wqe_ix_be = *wq->tail_next;
864 wqe_ix = be16_to_cpu(wqe_ix_be);
865 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
866 rq->dealloc_wqe(rq, wqe_ix);
867 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
868 &wqe->next.next_wqe_index);
869 }
870}
871
f62b8bb8 872static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 873 struct mlx5e_params *params,
f62b8bb8
AV		 874 struct mlx5e_rq_param *param,
875 struct mlx5e_rq *rq)
876{
877 int err;
878
6a9764ef 879 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 880 if (err)
881 return err;
882
3b77235b 883 err = mlx5e_create_rq(rq, param);
f62b8bb8 884 if (err)
3b77235b 885 goto err_free_rq;
f62b8bb8 886
36350114 887 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 888 if (err)
3b77235b 889 goto err_destroy_rq;
f62b8bb8 890
6a9764ef 891 if (params->rx_am_enabled)
cb3c7fd4
GR		 892 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
893
f62b8bb8
AV		 894 return 0;
895
f62b8bb8
AV		 896err_destroy_rq:
897 mlx5e_destroy_rq(rq);
3b77235b
SM		 898err_free_rq:
899 mlx5e_free_rq(rq);
f62b8bb8
AV		 900
901 return err;
902}
903
acc6c595
SM		 904static void mlx5e_activate_rq(struct mlx5e_rq *rq)
905{
906 struct mlx5e_icosq *sq = &rq->channel->icosq;
907 u16 pi = sq->pc & sq->wq.sz_m1;
908 struct mlx5e_tx_wqe *nopwqe;
909
910 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
911 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
912 sq->db.ico_wqe[pi].num_wqebbs = 1;
913 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
914 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
915}
916
917static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 918{
c0f1147d 919 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 920 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 921}
cb3c7fd4 922
acc6c595
SM		 923static void mlx5e_close_rq(struct mlx5e_rq *rq)
924{
925 cancel_work_sync(&rq->am.work);
f62b8bb8 926 mlx5e_destroy_rq(rq);
3b77235b
SM		 927 mlx5e_free_rx_descs(rq);
928 mlx5e_free_rq(rq);
f62b8bb8
AV		 929}
930
31391048 931static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 932{
31391048 933 kfree(sq->db.di);
b5503b99
SM		 934}
935
31391048 936static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 937{
938 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
939
31391048 940 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 941 GFP_KERNEL, numa);
31391048
SM		 942 if (!sq->db.di) {
943 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 944 return -ENOMEM;
945 }
946
947 return 0;
948}
949
31391048 950static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 951 struct mlx5e_params *params,
31391048
SM		 952 struct mlx5e_sq_param *param,
953 struct mlx5e_xdpsq *sq)
954{
955 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 956 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 957 int err;
958
959 sq->pdev = c->pdev;
960 sq->mkey_be = c->mkey_be;
961 sq->channel = c;
962 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 963 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 964
965 param->wq.db_numa_node = cpu_to_node(c->cpu);
966 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
967 if (err)
968 return err;
969 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
970
971 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
972 if (err)
973 goto err_sq_wq_destroy;
974
975 return 0;
976
977err_sq_wq_destroy:
978 mlx5_wq_destroy(&sq->wq_ctrl);
979
980 return err;
981}
982
983static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
984{
985 mlx5e_free_xdpsq_db(sq);
986 mlx5_wq_destroy(&sq->wq_ctrl);
987}
988
989static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 990{
f10b7cc7 991 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 992}
993
31391048 994static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 995{
996 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
997
998 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
999 GFP_KERNEL, numa);
1000 if (!sq->db.ico_wqe)
1001 return -ENOMEM;
1002
1003 return 0;
1004}
1005
31391048 1006static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1007 struct mlx5e_sq_param *param,
1008 struct mlx5e_icosq *sq)
f10b7cc7 1009{
31391048 1010 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1011 struct mlx5_core_dev *mdev = c->mdev;
31391048 1012 int err;
f10b7cc7 1013
31391048
SM		 1014 sq->pdev = c->pdev;
1015 sq->mkey_be = c->mkey_be;
1016 sq->channel = c;
1017 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1018
31391048
SM		 1019 param->wq.db_numa_node = cpu_to_node(c->cpu);
1020 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1021 if (err)
1022 return err;
1023 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1024
31391048
SM		 1025 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1026 if (err)
1027 goto err_sq_wq_destroy;
1028
1029 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1030
1031 return 0;
31391048
SM		 1032
1033err_sq_wq_destroy:
1034 mlx5_wq_destroy(&sq->wq_ctrl);
1035
1036 return err;
f62b8bb8
AV		 1037}
1038
31391048 1039static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1040{
31391048
SM		 1041 mlx5e_free_icosq_db(sq);
1042 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1043}
1044
31391048 1045static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1046{
31391048
SM		 1047 kfree(sq->db.wqe_info);
1048 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1049}
1050
31391048 1051static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1052{
31391048
SM		 1053 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1054 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1055
31391048
SM		 1056 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1057 GFP_KERNEL, numa);
1058 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1059 GFP_KERNEL, numa);
77bdf895 1060 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1061 mlx5e_free_txqsq_db(sq);
1062 return -ENOMEM;
b5503b99 1063 }
31391048
SM		 1064
1065 sq->dma_fifo_mask = df_sz - 1;
1066
1067 return 0;
b5503b99
SM		 1068}
1069
31391048 1070static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1071 int txq_ix,
6a9764ef 1072 struct mlx5e_params *params,
31391048
SM		 1073 struct mlx5e_sq_param *param,
1074 struct mlx5e_txqsq *sq)
f62b8bb8 1075{
31391048 1076 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1077 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1078 int err;
1079
f10b7cc7 1080 sq->pdev = c->pdev;
a43b25da 1081 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1082 sq->mkey_be = c->mkey_be;
1083 sq->channel = c;
acc6c595 1084 sq->txq_ix = txq_ix;
aff26157 1085 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1086 sq->max_inline = params->tx_max_inline;
1087 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1088
311c7c71 1089 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1090 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1091 if (err)
aff26157 1092 return err;
31391048 1093 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1094
31391048 1095 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1096 if (err)
f62b8bb8
AV		 1097 goto err_sq_wq_destroy;
1098
31391048 1099 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1100
1101 return 0;
1102
1103err_sq_wq_destroy:
1104 mlx5_wq_destroy(&sq->wq_ctrl);
1105
f62b8bb8
AV		 1106 return err;
1107}
1108
31391048 1109static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1110{
31391048 1111 mlx5e_free_txqsq_db(sq);
f62b8bb8 1112 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1113}
1114
33ad9711
SM		 1115struct mlx5e_create_sq_param {
1116 struct mlx5_wq_ctrl *wq_ctrl;
1117 u32 cqn;
1118 u32 tisn;
1119 u8 tis_lst_sz;
1120 u8 min_inline_mode;
1121};
1122
a43b25da 1123static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1124 struct mlx5e_sq_param *param,
1125 struct mlx5e_create_sq_param *csp,
1126 u32 *sqn)
f62b8bb8 1127{
f62b8bb8
AV		 1128 void *in;
1129 void *sqc;
1130 void *wq;
1131 int inlen;
1132 int err;
1133
1134 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1135 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1136 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1137 if (!in)
1138 return -ENOMEM;
1139
1140 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1141 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1142
1143 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1144 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1145 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1146 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1147
1148 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1149 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1150
33ad9711 1151 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1152
1153 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1154 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1155 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1156 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1157 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1158
33ad9711 1159 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1160
33ad9711 1161 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1162
1163 kvfree(in);
1164
1165 return err;
1166}
1167
33ad9711
SM		 1168struct mlx5e_modify_sq_param {
1169 int curr_state;
1170 int next_state;
1171 bool rl_update;
1172 int rl_index;
1173};
1174
a43b25da 1175static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1176 struct mlx5e_modify_sq_param *p)
f62b8bb8 1177{
f62b8bb8
AV		 1178 void *in;
1179 void *sqc;
1180 int inlen;
1181 int err;
1182
1183 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1184 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1185 if (!in)
1186 return -ENOMEM;
1187
1188 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1189
33ad9711
SM		 1190 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1191 MLX5_SET(sqc, sqc, state, p->next_state);
1192 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1193 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1194 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1195 }
f62b8bb8 1196
33ad9711 1197 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1198
1199 kvfree(in);
1200
1201 return err;
1202}
1203
a43b25da 1204static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1205{
a43b25da 1206 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1207}
1208
a43b25da 1209static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1210 struct mlx5e_sq_param *param,
1211 struct mlx5e_create_sq_param *csp,
1212 u32 *sqn)
f62b8bb8 1213{
33ad9711 1214 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1215 int err;
1216
a43b25da 1217 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1218 if (err)
1219 return err;
1220
1221 msp.curr_state = MLX5_SQC_STATE_RST;
1222 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1223 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1224 if (err)
a43b25da 1225 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1226
1227 return err;
1228}
1229
7f859ecf
SM		 1230static int mlx5e_set_sq_maxrate(struct net_device *dev,
1231 struct mlx5e_txqsq *sq, u32 rate);
1232
31391048 1233static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1234 u32 tisn,
acc6c595 1235 int txq_ix,
6a9764ef 1236 struct mlx5e_params *params,
31391048
SM		 1237 struct mlx5e_sq_param *param,
1238 struct mlx5e_txqsq *sq)
1239{
1240 struct mlx5e_create_sq_param csp = {};
7f859ecf 1241 u32 tx_rate;
f62b8bb8
AV		 1242 int err;
1243
6a9764ef 1244 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1245 if (err)
1246 return err;
1247
a43b25da 1248 csp.tisn = tisn;
31391048 1249 csp.tis_lst_sz = 1;
33ad9711
SM		 1250 csp.cqn = sq->cq.mcq.cqn;
1251 csp.wq_ctrl = &sq->wq_ctrl;
1252 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1253 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1254 if (err)
31391048 1255 goto err_free_txqsq;
f62b8bb8 1256
a43b25da 1257 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1258 if (tx_rate)
a43b25da 1259 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1260
f62b8bb8
AV		 1261 return 0;
1262
31391048 1263err_free_txqsq:
3b77235b 1264 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1265 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1266
1267 return err;
1268}
1269
acc6c595
SM		 1270static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1271{
a43b25da 1272 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1273 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1274 netdev_tx_reset_queue(sq->txq);
1275 netif_tx_start_queue(sq->txq);
1276}
1277
f62b8bb8
AV		 1278static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1279{
1280 __netif_tx_lock_bh(txq);
1281 netif_tx_stop_queue(txq);
1282 __netif_tx_unlock_bh(txq);
1283}
1284
acc6c595 1285static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1286{
33ad9711 1287 struct mlx5e_channel *c = sq->channel;
33ad9711 1288
c0f1147d 1289 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1290 /* prevent netif_tx_wake_queue */
33ad9711 1291 napi_synchronize(&c->napi);
29429f33 1292
31391048 1293 netif_tx_disable_queue(sq->txq);
f62b8bb8 1294
31391048
SM		 1295 /* last doorbell out, godspeed .. */
1296 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1297 struct mlx5e_tx_wqe *nop;
864b2d71 1298
77bdf895 1299 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1300 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1301 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1302 }
acc6c595
SM		 1303}
1304
1305static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1306{
1307 struct mlx5e_channel *c = sq->channel;
a43b25da 1308 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1309
a43b25da 1310 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1311 if (sq->rate_limit)
1312 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1313 mlx5e_free_txqsq_descs(sq);
1314 mlx5e_free_txqsq(sq);
1315}
1316
1317static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1318 struct mlx5e_params *params,
31391048
SM		 1319 struct mlx5e_sq_param *param,
1320 struct mlx5e_icosq *sq)
1321{
1322 struct mlx5e_create_sq_param csp = {};
1323 int err;
1324
6a9764ef 1325 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1326 if (err)
1327 return err;
1328
1329 csp.cqn = sq->cq.mcq.cqn;
1330 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1331 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1332 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1333 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1334 if (err)
1335 goto err_free_icosq;
1336
1337 return 0;
1338
1339err_free_icosq:
1340 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341 mlx5e_free_icosq(sq);
1342
1343 return err;
1344}
1345
1346static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1347{
1348 struct mlx5e_channel *c = sq->channel;
1349
1350 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351 napi_synchronize(&c->napi);
1352
a43b25da 1353 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1354 mlx5e_free_icosq(sq);
1355}
1356
1357static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1358 struct mlx5e_params *params,
31391048
SM		 1359 struct mlx5e_sq_param *param,
1360 struct mlx5e_xdpsq *sq)
1361{
1362 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1363 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1364 unsigned int inline_hdr_sz = 0;
1365 int err;
1366 int i;
1367
6a9764ef 1368 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1369 if (err)
1370 return err;
1371
1372 csp.tis_lst_sz = 1;
a43b25da 1373 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1374 csp.cqn = sq->cq.mcq.cqn;
1375 csp.wq_ctrl = &sq->wq_ctrl;
1376 csp.min_inline_mode = sq->min_inline_mode;
1377 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1378 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1379 if (err)
1380 goto err_free_xdpsq;
1381
1382 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1383 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1384 ds_cnt++;
1385 }
1386
1387 /* Pre initialize fixed WQE fields */
1388 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1389 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1390 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1391 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1392 struct mlx5_wqe_data_seg *dseg;
1393
1394 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1395 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1396
1397 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1398 dseg->lkey = sq->mkey_be;
1399 }
1400
1401 return 0;
1402
1403err_free_xdpsq:
1404 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1405 mlx5e_free_xdpsq(sq);
1406
1407 return err;
1408}
1409
1410static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1411{
1412 struct mlx5e_channel *c = sq->channel;
1413
1414 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415 napi_synchronize(&c->napi);
1416
a43b25da 1417 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1418 mlx5e_free_xdpsq_descs(sq);
1419 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1420}
1421
95b6c6a5
EBE		 1422static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1423 struct mlx5e_cq_param *param,
1424 struct mlx5e_cq *cq)
f62b8bb8 1425{
f62b8bb8
AV		 1426 struct mlx5_core_cq *mcq = &cq->mcq;
1427 int eqn_not_used;
0b6e26ce 1428 unsigned int irqn;
f62b8bb8
AV		 1429 int err;
1430 u32 i;
1431
f62b8bb8
AV		 1432 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1433 &cq->wq_ctrl);
1434 if (err)
1435 return err;
1436
1437 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1438
f62b8bb8
AV		 1439 mcq->cqe_sz = 64;
1440 mcq->set_ci_db = cq->wq_ctrl.db.db;
1441 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1442 *mcq->set_ci_db = 0;
1443 *mcq->arm_db = 0;
1444 mcq->vector = param->eq_ix;
1445 mcq->comp = mlx5e_completion_event;
1446 mcq->event = mlx5e_cq_error_event;
1447 mcq->irqn = irqn;
f62b8bb8
AV		 1448
1449 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1450 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1451
1452 cqe->op_own = 0xf1;
1453 }
1454
a43b25da 1455 cq->mdev = mdev;
f62b8bb8
AV		 1456
1457 return 0;
1458}
1459
95b6c6a5
EBE		 1460static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1461 struct mlx5e_cq_param *param,
1462 struct mlx5e_cq *cq)
1463{
1464 struct mlx5_core_dev *mdev = c->priv->mdev;
1465 int err;
1466
1467 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1468 param->wq.db_numa_node = cpu_to_node(c->cpu);
1469 param->eq_ix = c->ix;
1470
1471 err = mlx5e_alloc_cq_common(mdev, param, cq);
1472
1473 cq->napi = &c->napi;
1474 cq->channel = c;
1475
1476 return err;
1477}
1478
3b77235b 1479static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1480{
1c1b5228 1481 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1482}
1483
3b77235b 1484static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1485{
a43b25da 1486 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1487 struct mlx5_core_cq *mcq = &cq->mcq;
1488
1489 void *in;
1490 void *cqc;
1491 int inlen;
0b6e26ce 1492 unsigned int irqn_not_used;
f62b8bb8
AV		 1493 int eqn;
1494 int err;
1495
1496 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1497 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1498 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1499 if (!in)
1500 return -ENOMEM;
1501
1502 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1503
1504 memcpy(cqc, param->cqc, sizeof(param->cqc));
1505
1c1b5228
TT		 1506 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1507 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1508
1509 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1510
9908aa29 1511 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1512 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1513 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1514 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1515 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1516 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1517
1518 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1519
1520 kvfree(in);
1521
1522 if (err)
1523 return err;
1524
1525 mlx5e_cq_arm(cq);
1526
1527 return 0;
1528}
1529
3b77235b 1530static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1531{
a43b25da 1532 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1533}
1534
1535static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1536 struct mlx5e_cq_moder moder,
f62b8bb8 1537 struct mlx5e_cq_param *param,
6a9764ef 1538 struct mlx5e_cq *cq)
f62b8bb8 1539{
a43b25da 1540 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1541 int err;
f62b8bb8 1542
3b77235b 1543 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1544 if (err)
1545 return err;
1546
3b77235b 1547 err = mlx5e_create_cq(cq, param);
f62b8bb8 1548 if (err)
3b77235b 1549 goto err_free_cq;
f62b8bb8 1550
7524a5d8 1551 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1552 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1553 return 0;
1554
3b77235b
SM		 1555err_free_cq:
1556 mlx5e_free_cq(cq);
f62b8bb8
AV		 1557
1558 return err;
1559}
1560
1561static void mlx5e_close_cq(struct mlx5e_cq *cq)
1562{
f62b8bb8 1563 mlx5e_destroy_cq(cq);
3b77235b 1564 mlx5e_free_cq(cq);
f62b8bb8
AV		 1565}
1566
1567static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1568{
1569 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1570}
1571
1572static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1573 struct mlx5e_params *params,
f62b8bb8
AV		 1574 struct mlx5e_channel_param *cparam)
1575{
f62b8bb8
AV		 1576 int err;
1577 int tc;
1578
1579 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1580 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1581 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1582 if (err)
1583 goto err_close_tx_cqs;
f62b8bb8
AV		 1584 }
1585
1586 return 0;
1587
1588err_close_tx_cqs:
1589 for (tc--; tc >= 0; tc--)
1590 mlx5e_close_cq(&c->sq[tc].cq);
1591
1592 return err;
1593}
1594
1595static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1596{
1597 int tc;
1598
1599 for (tc = 0; tc < c->num_tc; tc++)
1600 mlx5e_close_cq(&c->sq[tc].cq);
1601}
1602
1603static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1604 struct mlx5e_params *params,
f62b8bb8
AV		 1605 struct mlx5e_channel_param *cparam)
1606{
1607 int err;
1608 int tc;
1609
6a9764ef
SM		 1610 for (tc = 0; tc < params->num_tc; tc++) {
1611 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1612
a43b25da
SM		 1613 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1614 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1615 if (err)
1616 goto err_close_sqs;
1617 }
1618
1619 return 0;
1620
1621err_close_sqs:
1622 for (tc--; tc >= 0; tc--)
31391048 1623 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1624
1625 return err;
1626}
1627
1628static void mlx5e_close_sqs(struct mlx5e_channel *c)
1629{
1630 int tc;
1631
1632 for (tc = 0; tc < c->num_tc; tc++)
31391048 1633 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1634}
1635
507f0c81 1636static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1637 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1638{
1639 struct mlx5e_priv *priv = netdev_priv(dev);
1640 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1641 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1642 u16 rl_index = 0;
1643 int err;
1644
1645 if (rate == sq->rate_limit)
1646 /* nothing to do */
1647 return 0;
1648
1649 if (sq->rate_limit)
1650 /* remove current rl index to free space to next ones */
1651 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1652
1653 sq->rate_limit = 0;
1654
1655 if (rate) {
1656 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1657 if (err) {
1658 netdev_err(dev, "Failed configuring rate %u: %d\n",
1659 rate, err);
1660 return err;
1661 }
1662 }
1663
33ad9711
SM		 1664 msp.curr_state = MLX5_SQC_STATE_RDY;
1665 msp.next_state = MLX5_SQC_STATE_RDY;
1666 msp.rl_index = rl_index;
1667 msp.rl_update = true;
a43b25da 1668 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1669 if (err) {
1670 netdev_err(dev, "Failed configuring rate %u: %d\n",
1671 rate, err);
1672 /* remove the rate from the table */
1673 if (rate)
1674 mlx5_rl_remove_rate(mdev, rate);
1675 return err;
1676 }
1677
1678 sq->rate_limit = rate;
1679 return 0;
1680}
1681
1682static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1683{
1684 struct mlx5e_priv *priv = netdev_priv(dev);
1685 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1686 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1687 int err = 0;
1688
1689 if (!mlx5_rl_is_supported(mdev)) {
1690 netdev_err(dev, "Rate limiting is not supported on this device\n");
1691 return -EINVAL;
1692 }
1693
1694 /* rate is given in Mb/sec, HW config is in Kb/sec */
1695 rate = rate << 10;
1696
1697 /* Check whether rate in valid range, 0 is always valid */
1698 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1699 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1700 return -ERANGE;
1701 }
1702
1703 mutex_lock(&priv->state_lock);
1704 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1705 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1706 if (!err)
1707 priv->tx_rates[index] = rate;
1708 mutex_unlock(&priv->state_lock);
1709
1710 return err;
1711}
1712
f62b8bb8 1713static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1714 struct mlx5e_params *params,
f62b8bb8
AV		 1715 struct mlx5e_channel_param *cparam,
1716 struct mlx5e_channel **cp)
1717{
6a9764ef 1718 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1719 struct net_device *netdev = priv->netdev;
1720 int cpu = mlx5e_get_cpu(priv, ix);
1721 struct mlx5e_channel *c;
1722 int err;
1723
1724 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1725 if (!c)
1726 return -ENOMEM;
1727
1728 c->priv = priv;
a43b25da
SM		 1729 c->mdev = priv->mdev;
1730 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1731 c->ix = ix;
1732 c->cpu = cpu;
1733 c->pdev = &priv->mdev->pdev->dev;
1734 c->netdev = priv->netdev;
b50d292b 1735 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1736 c->num_tc = params->num_tc;
1737 c->xdp = !!params->xdp_prog;
cb3c7fd4 1738
f62b8bb8
AV		 1739 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1740
6a9764ef 1741 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1742 if (err)
1743 goto err_napi_del;
1744
6a9764ef 1745 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1746 if (err)
1747 goto err_close_icosq_cq;
1748
6a9764ef 1749 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1750 if (err)
1751 goto err_close_tx_cqs;
f62b8bb8 1752
d7a0ecab 1753 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1754 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1755 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1756 if (err)
1757 goto err_close_rx_cq;
1758
f62b8bb8
AV		 1759 napi_enable(&c->napi);
1760
6a9764ef 1761 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1762 if (err)
1763 goto err_disable_napi;
1764
6a9764ef 1765 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1766 if (err)
1767 goto err_close_icosq;
1768
6a9764ef 1769 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1770 if (err)
1771 goto err_close_sqs;
b5503b99 1772
6a9764ef 1773 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1774 if (err)
b5503b99 1775 goto err_close_xdp_sq;
f62b8bb8 1776
f62b8bb8
AV		 1777 *cp = c;
1778
1779 return 0;
b5503b99 1780err_close_xdp_sq:
d7a0ecab 1781 if (c->xdp)
31391048 1782 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1783
1784err_close_sqs:
1785 mlx5e_close_sqs(c);
1786
d3c9bc27 1787err_close_icosq:
31391048 1788 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1789
f62b8bb8
AV		 1790err_disable_napi:
1791 napi_disable(&c->napi);
d7a0ecab 1792 if (c->xdp)
31871f87 1793 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1794
1795err_close_rx_cq:
f62b8bb8
AV		 1796 mlx5e_close_cq(&c->rq.cq);
1797
1798err_close_tx_cqs:
1799 mlx5e_close_tx_cqs(c);
1800
d3c9bc27
TT		 1801err_close_icosq_cq:
1802 mlx5e_close_cq(&c->icosq.cq);
1803
f62b8bb8
AV		 1804err_napi_del:
1805 netif_napi_del(&c->napi);
1806 kfree(c);
1807
1808 return err;
1809}
1810
acc6c595
SM		 1811static void mlx5e_activate_channel(struct mlx5e_channel *c)
1812{
1813 int tc;
1814
1815 for (tc = 0; tc < c->num_tc; tc++)
1816 mlx5e_activate_txqsq(&c->sq[tc]);
1817 mlx5e_activate_rq(&c->rq);
a43b25da 1818 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1819}
1820
1821static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1822{
1823 int tc;
1824
1825 mlx5e_deactivate_rq(&c->rq);
1826 for (tc = 0; tc < c->num_tc; tc++)
1827 mlx5e_deactivate_txqsq(&c->sq[tc]);
1828}
1829
f62b8bb8
AV		 1830static void mlx5e_close_channel(struct mlx5e_channel *c)
1831{
1832 mlx5e_close_rq(&c->rq);
b5503b99 1833 if (c->xdp)
31391048 1834 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1835 mlx5e_close_sqs(c);
31391048 1836 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1837 napi_disable(&c->napi);
b5503b99 1838 if (c->xdp)
31871f87 1839 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1840 mlx5e_close_cq(&c->rq.cq);
1841 mlx5e_close_tx_cqs(c);
d3c9bc27 1842 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1843 netif_napi_del(&c->napi);
7ae92ae5 1844
f62b8bb8
AV		 1845 kfree(c);
1846}
1847
1848static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1849 struct mlx5e_params *params,
f62b8bb8
AV		 1850 struct mlx5e_rq_param *param)
1851{
1852 void *rqc = param->rqc;
1853 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1854
6a9764ef 1855 switch (params->rq_wq_type) {
461017cb 1856 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1857 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1858 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1859 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1860 break;
1861 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1862 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1863 }
1864
f62b8bb8
AV		 1865 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1866 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1867 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1868 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1869 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1870 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1871 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1872
311c7c71 1873 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1874 param->wq.linear = 1;
1875}
1876
556dd1b9
TT		 1877static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1878{
1879 void *rqc = param->rqc;
1880 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1881
1882 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1883 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1884}
1885
d3c9bc27
TT		 1886static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1887 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1888{
1889 void *sqc = param->sqc;
1890 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1891
f62b8bb8 1892 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1893 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1894
311c7c71 1895 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1896}
1897
1898static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1899 struct mlx5e_params *params,
d3c9bc27
TT		 1900 struct mlx5e_sq_param *param)
1901{
1902 void *sqc = param->sqc;
1903 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1904
1905 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1906 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1907}
1908
1909static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1910 struct mlx5e_cq_param *param)
1911{
1912 void *cqc = param->cqc;
1913
30aa60b3 1914 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1915}
1916
1917static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1918 struct mlx5e_params *params,
f62b8bb8
AV		 1919 struct mlx5e_cq_param *param)
1920{
1921 void *cqc = param->cqc;
461017cb 1922 u8 log_cq_size;
f62b8bb8 1923
6a9764ef 1924 switch (params->rq_wq_type) {
461017cb 1925 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1926 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1927 break;
1928 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1929 log_cq_size = params->log_rq_size;
461017cb
TT		 1930 }
1931
1932 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1933 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1934 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1935 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1936 }
f62b8bb8
AV		 1937
1938 mlx5e_build_common_cq_param(priv, param);
1939}
1940
1941static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1942 struct mlx5e_params *params,
f62b8bb8
AV		 1943 struct mlx5e_cq_param *param)
1944{
1945 void *cqc = param->cqc;
1946
6a9764ef 1947 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1948
1949 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1950
1951 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1952}
1953
d3c9bc27 1954static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1955 u8 log_wq_size,
1956 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1957{
1958 void *cqc = param->cqc;
1959
1960 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1961
1962 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1963
1964 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1965}
1966
1967static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1968 u8 log_wq_size,
1969 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1970{
1971 void *sqc = param->sqc;
1972 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1973
1974 mlx5e_build_sq_param_common(priv, param);
1975
1976 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1977 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1978}
1979
b5503b99 1980static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1981 struct mlx5e_params *params,
b5503b99
SM		 1982 struct mlx5e_sq_param *param)
1983{
1984 void *sqc = param->sqc;
1985 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1986
1987 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1988 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1989}
1990
6a9764ef
SM		 1991static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1992 struct mlx5e_params *params,
1993 struct mlx5e_channel_param *cparam)
f62b8bb8 1994{
bc77b240 1995 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1996
6a9764ef
SM		 1997 mlx5e_build_rq_param(priv, params, &cparam->rq);
1998 mlx5e_build_sq_param(priv, params, &cparam->sq);
1999 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2000 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2001 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2002 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2003 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2004}
2005
55c2503d
SM		 2006int mlx5e_open_channels(struct mlx5e_priv *priv,
2007 struct mlx5e_channels *chs)
f62b8bb8 2008{
6b87663f 2009 struct mlx5e_channel_param *cparam;
03289b88 2010 int err = -ENOMEM;
f62b8bb8 2011 int i;
f62b8bb8 2012
6a9764ef 2013 chs->num = chs->params.num_channels;
03289b88 2014
ff9c852f 2015 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2016 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2017 if (!chs->c || !cparam)
2018 goto err_free;
f62b8bb8 2019
6a9764ef 2020 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2021 for (i = 0; i < chs->num; i++) {
6a9764ef 2022 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2023 if (err)
2024 goto err_close_channels;
2025 }
2026
6b87663f 2027 kfree(cparam);
f62b8bb8
AV		 2028 return 0;
2029
2030err_close_channels:
2031 for (i--; i >= 0; i--)
ff9c852f 2032 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2033
acc6c595 2034err_free:
ff9c852f 2035 kfree(chs->c);
6b87663f 2036 kfree(cparam);
ff9c852f 2037 chs->num = 0;
f62b8bb8
AV		 2038 return err;
2039}
2040
acc6c595 2041static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2042{
2043 int i;
2044
acc6c595
SM		 2045 for (i = 0; i < chs->num; i++)
2046 mlx5e_activate_channel(chs->c[i]);
2047}
2048
2049static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2050{
2051 int err = 0;
2052 int i;
2053
2054 for (i = 0; i < chs->num; i++) {
2055 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2056 if (err)
2057 break;
2058 }
2059
2060 return err;
2061}
2062
2063static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2064{
2065 int i;
2066
2067 for (i = 0; i < chs->num; i++)
2068 mlx5e_deactivate_channel(chs->c[i]);
2069}
2070
55c2503d 2071void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2072{
2073 int i;
c3b7c5c9 2074
ff9c852f
SM		 2075 for (i = 0; i < chs->num; i++)
2076 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2077
ff9c852f
SM		 2078 kfree(chs->c);
2079 chs->num = 0;
f62b8bb8
AV		 2080}
2081
a5f97fee
SM		 2082static int
2083mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2084{
2085 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2086 void *rqtc;
2087 int inlen;
2088 int err;
1da36696 2089 u32 *in;
a5f97fee 2090 int i;
f62b8bb8 2091
f62b8bb8 2092 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2093 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2094 if (!in)
2095 return -ENOMEM;
2096
2097 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2098
2099 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2100 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2101
a5f97fee
SM		 2102 for (i = 0; i < sz; i++)
2103 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2104
398f3351
HHZ		 2105 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2106 if (!err)
2107 rqt->enabled = true;
f62b8bb8
AV		 2108
2109 kvfree(in);
1da36696
TT		 2110 return err;
2111}
2112
cb67b832 2113void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2114{
398f3351
HHZ		 2115 rqt->enabled = false;
2116 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2117}
2118
8f493ffd 2119int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2120{
2121 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2122 int err;
6bfd390b 2123
8f493ffd
SM		 2124 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2125 if (err)
2126 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2127 return err;
6bfd390b
HHZ		 2128}
2129
cb67b832 2130int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2131{
398f3351 2132 struct mlx5e_rqt *rqt;
1da36696
TT		 2133 int err;
2134 int ix;
2135
6bfd390b 2136 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2137 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2138 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2139 if (err)
2140 goto err_destroy_rqts;
2141 }
2142
2143 return 0;
2144
2145err_destroy_rqts:
8f493ffd 2146 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2147 for (ix--; ix >= 0; ix--)
398f3351 2148 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2149
f62b8bb8
AV		 2150 return err;
2151}
2152
8f493ffd
SM		 2153void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2154{
2155 int i;
2156
2157 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2158 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2159}
2160
a5f97fee
SM		 2161static int mlx5e_rx_hash_fn(int hfunc)
2162{
2163 return (hfunc == ETH_RSS_HASH_TOP) ?
2164 MLX5_RX_HASH_FN_TOEPLITZ :
2165 MLX5_RX_HASH_FN_INVERTED_XOR8;
2166}
2167
2168static int mlx5e_bits_invert(unsigned long a, int size)
2169{
2170 int inv = 0;
2171 int i;
2172
2173 for (i = 0; i < size; i++)
2174 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2175
2176 return inv;
2177}
2178
2179static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2180 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2181{
2182 int i;
2183
2184 for (i = 0; i < sz; i++) {
2185 u32 rqn;
2186
2187 if (rrp.is_rss) {
2188 int ix = i;
2189
2190 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2191 ix = mlx5e_bits_invert(i, ilog2(sz));
2192
6a9764ef 2193 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2194 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2195 } else {
2196 rqn = rrp.rqn;
2197 }
2198 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2199 }
2200}
2201
2202int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2203 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2204{
2205 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2206 void *rqtc;
2207 int inlen;
1da36696 2208 u32 *in;
5c50368f
AS		 2209 int err;
2210
5c50368f 2211 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2212 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2213 if (!in)
2214 return -ENOMEM;
2215
2216 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2217
2218 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2219 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2220 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2221 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2222
2223 kvfree(in);
5c50368f
AS		 2224 return err;
2225}
2226
a5f97fee
SM		 2227static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2228 struct mlx5e_redirect_rqt_param rrp)
2229{
2230 if (!rrp.is_rss)
2231 return rrp.rqn;
2232
2233 if (ix >= rrp.rss.channels->num)
2234 return priv->drop_rq.rqn;
2235
2236 return rrp.rss.channels->c[ix]->rq.rqn;
2237}
2238
2239static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2240 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2241{
1da36696
TT		 2242 u32 rqtn;
2243 int ix;
2244
398f3351 2245 if (priv->indir_rqt.enabled) {
a5f97fee 2246 /* RSS RQ table */
398f3351 2247 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2248 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2249 }
2250
a5f97fee
SM		 2251 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2252 struct mlx5e_redirect_rqt_param direct_rrp = {
2253 .is_rss = false,
95632791
AM		 2254 {
2255 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2256 },
a5f97fee
SM		 2257 };
2258
2259 /* Direct RQ Tables */
398f3351
HHZ		 2260 if (!priv->direct_tir[ix].rqt.enabled)
2261 continue;
a5f97fee 2262
398f3351 2263 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2264 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2265 }
40ab6a6e
AS		 2266}
2267
a5f97fee
SM		 2268static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2269 struct mlx5e_channels *chs)
2270{
2271 struct mlx5e_redirect_rqt_param rrp = {
2272 .is_rss = true,
95632791
AM		 2273 {
2274 .rss = {
2275 .channels = chs,
2276 .hfunc = chs->params.rss_hfunc,
2277 }
2278 },
a5f97fee
SM		 2279 };
2280
2281 mlx5e_redirect_rqts(priv, rrp);
2282}
2283
2284static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2285{
2286 struct mlx5e_redirect_rqt_param drop_rrp = {
2287 .is_rss = false,
95632791
AM		 2288 {
2289 .rqn = priv->drop_rq.rqn,
2290 },
a5f97fee
SM		 2291 };
2292
2293 mlx5e_redirect_rqts(priv, drop_rrp);
2294}
2295
6a9764ef 2296static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2297{
6a9764ef 2298 if (!params->lro_en)
5c50368f
AS		 2299 return;
2300
2301#define ROUGH_MAX_L2_L3_HDR_SZ 256
2302
2303 MLX5_SET(tirc, tirc, lro_enable_mask,
2304 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2305 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2306 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2307 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2308 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2309}
2310
6a9764ef
SM		 2311void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2312 enum mlx5e_traffic_types tt,
2313 void *tirc)
bdfc028d 2314{
a100ff3e
GP		 2315 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2316
2317#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2318 MLX5_HASH_FIELD_SEL_DST_IP)
2319
2320#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2321 MLX5_HASH_FIELD_SEL_DST_IP |\
2322 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2323 MLX5_HASH_FIELD_SEL_L4_DPORT)
2324
2325#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2326 MLX5_HASH_FIELD_SEL_DST_IP |\
2327 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2328
6a9764ef
SM		 2329 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2330 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2331 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2332 rx_hash_toeplitz_key);
2333 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2334 rx_hash_toeplitz_key);
2335
2336 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2337 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2338 }
a100ff3e
GP		 2339
2340 switch (tt) {
2341 case MLX5E_TT_IPV4_TCP:
2342 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2343 MLX5_L3_PROT_TYPE_IPV4);
2344 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2345 MLX5_L4_PROT_TYPE_TCP);
2346 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2347 MLX5_HASH_IP_L4PORTS);
2348 break;
2349
2350 case MLX5E_TT_IPV6_TCP:
2351 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2352 MLX5_L3_PROT_TYPE_IPV6);
2353 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2354 MLX5_L4_PROT_TYPE_TCP);
2355 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2356 MLX5_HASH_IP_L4PORTS);
2357 break;
2358
2359 case MLX5E_TT_IPV4_UDP:
2360 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2361 MLX5_L3_PROT_TYPE_IPV4);
2362 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2363 MLX5_L4_PROT_TYPE_UDP);
2364 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2365 MLX5_HASH_IP_L4PORTS);
2366 break;
2367
2368 case MLX5E_TT_IPV6_UDP:
2369 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2370 MLX5_L3_PROT_TYPE_IPV6);
2371 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2372 MLX5_L4_PROT_TYPE_UDP);
2373 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2374 MLX5_HASH_IP_L4PORTS);
2375 break;
2376
2377 case MLX5E_TT_IPV4_IPSEC_AH:
2378 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2379 MLX5_L3_PROT_TYPE_IPV4);
2380 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2381 MLX5_HASH_IP_IPSEC_SPI);
2382 break;
2383
2384 case MLX5E_TT_IPV6_IPSEC_AH:
2385 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2386 MLX5_L3_PROT_TYPE_IPV6);
2387 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2388 MLX5_HASH_IP_IPSEC_SPI);
2389 break;
2390
2391 case MLX5E_TT_IPV4_IPSEC_ESP:
2392 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2393 MLX5_L3_PROT_TYPE_IPV4);
2394 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2395 MLX5_HASH_IP_IPSEC_SPI);
2396 break;
2397
2398 case MLX5E_TT_IPV6_IPSEC_ESP:
2399 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400 MLX5_L3_PROT_TYPE_IPV6);
2401 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2402 MLX5_HASH_IP_IPSEC_SPI);
2403 break;
2404
2405 case MLX5E_TT_IPV4:
2406 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2407 MLX5_L3_PROT_TYPE_IPV4);
2408 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2409 MLX5_HASH_IP);
2410 break;
2411
2412 case MLX5E_TT_IPV6:
2413 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2414 MLX5_L3_PROT_TYPE_IPV6);
2415 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416 MLX5_HASH_IP);
2417 break;
2418 default:
2419 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2420 }
bdfc028d
TT		 2421}
2422
ab0394fe 2423static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2424{
2425 struct mlx5_core_dev *mdev = priv->mdev;
2426
2427 void *in;
2428 void *tirc;
2429 int inlen;
2430 int err;
ab0394fe 2431 int tt;
1da36696 2432 int ix;
5c50368f
AS		 2433
2434 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2435 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2436 if (!in)
2437 return -ENOMEM;
2438
2439 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2440 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2441
6a9764ef 2442 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2443
1da36696 2444 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2445 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2446 inlen);
ab0394fe 2447 if (err)
1da36696 2448 goto free_in;
ab0394fe 2449 }
5c50368f 2450
6bfd390b 2451 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2452 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2453 in, inlen);
2454 if (err)
2455 goto free_in;
2456 }
2457
2458free_in:
5c50368f
AS		 2459 kvfree(in);
2460
2461 return err;
2462}
2463
cd255eff 2464static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2465{
40ab6a6e 2466 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2467 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2468 int err;
2469
cd255eff 2470 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2471 if (err)
2472 return err;
2473
cd255eff
SM		 2474 /* Update vport context MTU */
2475 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2476 return 0;
2477}
40ab6a6e 2478
cd255eff
SM		 2479static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2480{
2481 struct mlx5_core_dev *mdev = priv->mdev;
2482 u16 hw_mtu = 0;
2483 int err;
40ab6a6e 2484
cd255eff
SM		 2485 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2486 if (err || !hw_mtu) /* fallback to port oper mtu */
2487 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2488
2489 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2490}
2491
2e20a151 2492static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2493{
2e20a151 2494 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2495 u16 mtu;
2496 int err;
2497
2498 err = mlx5e_set_mtu(priv, netdev->mtu);
2499 if (err)
2500 return err;
40ab6a6e 2501
cd255eff
SM		 2502 mlx5e_query_mtu(priv, &mtu);
2503 if (mtu != netdev->mtu)
2504 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2505 __func__, mtu, netdev->mtu);
40ab6a6e 2506
cd255eff 2507 netdev->mtu = mtu;
40ab6a6e
AS		 2508 return 0;
2509}
2510
08fb1dac
SM		 2511static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2512{
2513 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2514 int nch = priv->channels.params.num_channels;
2515 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2516 int tc;
2517
2518 netdev_reset_tc(netdev);
2519
2520 if (ntc == 1)
2521 return;
2522
2523 netdev_set_num_tc(netdev, ntc);
2524
7ccdd084
RS		 2525 /* Map netdev TCs to offset 0
2526 * We have our own UP to TXQ mapping for QoS
2527 */
08fb1dac 2528 for (tc = 0; tc < ntc; tc++)
7ccdd084 2529 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2530}
2531
acc6c595
SM		 2532static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2533{
2534 struct mlx5e_channel *c;
2535 struct mlx5e_txqsq *sq;
2536 int i, tc;
2537
2538 for (i = 0; i < priv->channels.num; i++)
2539 for (tc = 0; tc < priv->profile->max_tc; tc++)
2540 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2541
2542 for (i = 0; i < priv->channels.num; i++) {
2543 c = priv->channels.c[i];
2544 for (tc = 0; tc < c->num_tc; tc++) {
2545 sq = &c->sq[tc];
2546 priv->txq2sq[sq->txq_ix] = sq;
2547 }
2548 }
2549}
2550
955bc480
SM		 2551static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2552{
2553 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2554 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2555}
2556
603f4a45 2557void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2558{
9008ae07
SM		 2559 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2560 struct net_device *netdev = priv->netdev;
2561
2562 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2563 netif_set_real_num_tx_queues(netdev, num_txqs);
2564 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2565
acc6c595
SM		 2566 mlx5e_build_channels_tx_maps(priv);
2567 mlx5e_activate_channels(&priv->channels);
2568 netif_tx_start_all_queues(priv->netdev);
9008ae07 2569
955bc480 2570 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
9008ae07
SM		 2571 mlx5e_add_sqs_fwd_rules(priv);
2572
acc6c595 2573 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2574 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2575}
2576
603f4a45 2577void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2578{
9008ae07
SM		 2579 mlx5e_redirect_rqts_to_drop(priv);
2580
955bc480 2581 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
9008ae07
SM		 2582 mlx5e_remove_sqs_fwd_rules(priv);
2583
acc6c595
SM		 2584 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2585 * polling for inactive tx queues.
2586 */
2587 netif_tx_stop_all_queues(priv->netdev);
2588 netif_tx_disable(priv->netdev);
2589 mlx5e_deactivate_channels(&priv->channels);
2590}
2591
55c2503d 2592void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2593 struct mlx5e_channels *new_chs,
2594 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2595{
2596 struct net_device *netdev = priv->netdev;
2597 int new_num_txqs;
2598
2599 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2600
2601 netif_carrier_off(netdev);
2602
2603 if (new_num_txqs < netdev->real_num_tx_queues)
2604 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2605
2606 mlx5e_deactivate_priv_channels(priv);
2607 mlx5e_close_channels(&priv->channels);
2608
2609 priv->channels = *new_chs;
2610
2e20a151
SM		 2611 /* New channels are ready to roll, modify HW settings if needed */
2612 if (hw_modify)
2613 hw_modify(priv);
2614
55c2503d
SM		 2615 mlx5e_refresh_tirs(priv, false);
2616 mlx5e_activate_priv_channels(priv);
2617
2618 mlx5e_update_carrier(priv);
2619}
2620
40ab6a6e
AS		 2621int mlx5e_open_locked(struct net_device *netdev)
2622{
2623 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2624 int err;
2625
2626 set_bit(MLX5E_STATE_OPENED, &priv->state);
2627
ff9c852f 2628 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2629 if (err)
343b29f3 2630 goto err_clear_state_opened_flag;
40ab6a6e 2631
b676f653 2632 mlx5e_refresh_tirs(priv, false);
acc6c595 2633 mlx5e_activate_priv_channels(priv);
ce89ef36 2634 mlx5e_update_carrier(priv);
ef9814de 2635 mlx5e_timestamp_init(priv);
be4891af 2636
cb67b832
HHZ		 2637 if (priv->profile->update_stats)
2638 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2639
9b37b07f 2640 return 0;
343b29f3
AS		 2641
2642err_clear_state_opened_flag:
2643 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2644 return err;
40ab6a6e
AS		 2645}
2646
cb67b832 2647int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2648{
2649 struct mlx5e_priv *priv = netdev_priv(netdev);
2650 int err;
2651
2652 mutex_lock(&priv->state_lock);
2653 err = mlx5e_open_locked(netdev);
2654 mutex_unlock(&priv->state_lock);
2655
2656 return err;
2657}
2658
2659int mlx5e_close_locked(struct net_device *netdev)
2660{
2661 struct mlx5e_priv *priv = netdev_priv(netdev);
2662
a1985740
AS		 2663 /* May already be CLOSED in case a previous configuration operation
2664 * (e.g RX/TX queue size change) that involves close&open failed.
2665 */
2666 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2667 return 0;
2668
40ab6a6e
AS		 2669 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2670
ef9814de 2671 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2672 netif_carrier_off(priv->netdev);
acc6c595
SM		 2673 mlx5e_deactivate_priv_channels(priv);
2674 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2675
2676 return 0;
2677}
2678
cb67b832 2679int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2680{
2681 struct mlx5e_priv *priv = netdev_priv(netdev);
2682 int err;
2683
26e59d80
MHY		 2684 if (!netif_device_present(netdev))
2685 return -ENODEV;
2686
40ab6a6e
AS		 2687 mutex_lock(&priv->state_lock);
2688 err = mlx5e_close_locked(netdev);
2689 mutex_unlock(&priv->state_lock);
2690
2691 return err;
2692}
2693
a43b25da 2694static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2695 struct mlx5e_rq *rq,
2696 struct mlx5e_rq_param *param)
40ab6a6e 2697{
40ab6a6e
AS		 2698 void *rqc = param->rqc;
2699 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2700 int err;
2701
2702 param->wq.db_numa_node = param->wq.buf_numa_node;
2703
2704 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2705 &rq->wq_ctrl);
2706 if (err)
2707 return err;
2708
a43b25da 2709 rq->mdev = mdev;
40ab6a6e
AS		 2710
2711 return 0;
2712}
2713
a43b25da 2714static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2715 struct mlx5e_cq *cq,
2716 struct mlx5e_cq_param *param)
40ab6a6e 2717{
95b6c6a5 2718 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2719}
2720
a43b25da
SM		 2721static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2722 struct mlx5e_rq *drop_rq)
40ab6a6e 2723{
a43b25da
SM		 2724 struct mlx5e_cq_param cq_param = {};
2725 struct mlx5e_rq_param rq_param = {};
2726 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2727 int err;
2728
556dd1b9 2729 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2730
a43b25da 2731 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2732 if (err)
2733 return err;
2734
3b77235b 2735 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2736 if (err)
3b77235b 2737 goto err_free_cq;
40ab6a6e 2738
a43b25da 2739 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2740 if (err)
3b77235b 2741 goto err_destroy_cq;
40ab6a6e 2742
a43b25da 2743 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2744 if (err)
3b77235b 2745 goto err_free_rq;
40ab6a6e
AS		 2746
2747 return 0;
2748
3b77235b 2749err_free_rq:
a43b25da 2750 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2751
2752err_destroy_cq:
a43b25da 2753 mlx5e_destroy_cq(cq);
40ab6a6e 2754
3b77235b 2755err_free_cq:
a43b25da 2756 mlx5e_free_cq(cq);
3b77235b 2757
40ab6a6e
AS		 2758 return err;
2759}
2760
a43b25da 2761static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2762{
a43b25da
SM		 2763 mlx5e_destroy_rq(drop_rq);
2764 mlx5e_free_rq(drop_rq);
2765 mlx5e_destroy_cq(&drop_rq->cq);
2766 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2767}
2768
5426a0b2
SM		 2769int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2770 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2771{
c4f287c4 2772 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2773 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2774
08fb1dac 2775 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2776 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2777 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2778
2779 if (mlx5_lag_is_lacp_owner(mdev))
2780 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2781
5426a0b2 2782 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2783}
2784
5426a0b2 2785void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2786{
5426a0b2 2787 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2788}
2789
cb67b832 2790int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2791{
2792 int err;
2793 int tc;
2794
6bfd390b 2795 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2796 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2797 if (err)
2798 goto err_close_tises;
2799 }
2800
2801 return 0;
2802
2803err_close_tises:
2804 for (tc--; tc >= 0; tc--)
5426a0b2 2805 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2806
2807 return err;
2808}
2809
cb67b832 2810void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2811{
2812 int tc;
2813
6bfd390b 2814 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2815 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2816}
2817
6a9764ef
SM		 2818static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2819 enum mlx5e_traffic_types tt,
2820 u32 *tirc)
f62b8bb8 2821{
b50d292b 2822 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2823
6a9764ef 2824 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2825
4cbeaff5 2826 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2827 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2828 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2829}
2830
6a9764ef 2831static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2832{
b50d292b 2833 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2834
6a9764ef 2835 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2836
2837 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2838 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2839 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2840}
2841
8f493ffd 2842int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2843{
724b2aa1 2844 struct mlx5e_tir *tir;
f62b8bb8
AV		 2845 void *tirc;
2846 int inlen;
2847 int err;
1da36696 2848 u32 *in;
1da36696 2849 int tt;
f62b8bb8
AV		 2850
2851 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2852 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2853 if (!in)
2854 return -ENOMEM;
2855
1da36696
TT		 2856 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2857 memset(in, 0, inlen);
724b2aa1 2858 tir = &priv->indir_tir[tt];
1da36696 2859 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2860 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2861 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2862 if (err)
40ab6a6e 2863 goto err_destroy_tirs;
f62b8bb8
AV		 2864 }
2865
6bfd390b
HHZ		 2866 kvfree(in);
2867
2868 return 0;
2869
2870err_destroy_tirs:
8f493ffd 2871 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
6bfd390b
HHZ		 2872 for (tt--; tt >= 0; tt--)
2873 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2874
2875 kvfree(in);
2876
2877 return err;
2878}
2879
cb67b832 2880int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2881{
2882 int nch = priv->profile->max_nch(priv->mdev);
2883 struct mlx5e_tir *tir;
2884 void *tirc;
2885 int inlen;
2886 int err;
2887 u32 *in;
2888 int ix;
2889
2890 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2891 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2892 if (!in)
2893 return -ENOMEM;
2894
1da36696
TT		 2895 for (ix = 0; ix < nch; ix++) {
2896 memset(in, 0, inlen);
724b2aa1 2897 tir = &priv->direct_tir[ix];
1da36696 2898 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2899 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2900 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2901 if (err)
2902 goto err_destroy_ch_tirs;
2903 }
2904
2905 kvfree(in);
2906
f62b8bb8
AV		 2907 return 0;
2908
1da36696 2909err_destroy_ch_tirs:
8f493ffd 2910 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2911 for (ix--; ix >= 0; ix--)
724b2aa1 2912 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2913
1da36696 2914 kvfree(in);
f62b8bb8
AV		 2915
2916 return err;
2917}
2918
8f493ffd 2919void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2920{
2921 int i;
2922
1da36696 2923 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2924 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2925}
2926
cb67b832 2927void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2928{
2929 int nch = priv->profile->max_nch(priv->mdev);
2930 int i;
2931
2932 for (i = 0; i < nch; i++)
2933 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2934}
2935
102722fc
GE		 2936static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2937{
2938 int err = 0;
2939 int i;
2940
2941 for (i = 0; i < chs->num; i++) {
2942 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2943 if (err)
2944 return err;
2945 }
2946
2947 return 0;
2948}
2949
f6d96a20 2950static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2951{
2952 int err = 0;
2953 int i;
2954
ff9c852f
SM		 2955 for (i = 0; i < chs->num; i++) {
2956 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2957 if (err)
2958 return err;
2959 }
2960
2961 return 0;
2962}
2963
08fb1dac
SM		 2964static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2965{
2966 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2967 struct mlx5e_channels new_channels = {};
08fb1dac
SM		 2968 int err = 0;
2969
2970 if (tc && tc != MLX5E_MAX_NUM_TC)
2971 return -EINVAL;
2972
2973 mutex_lock(&priv->state_lock);
2974
6f9485af
SM		 2975 new_channels.params = priv->channels.params;
2976 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2977
20b6a1c7 2978 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 2979 priv->channels.params = new_channels.params;
2980 goto out;
2981 }
08fb1dac 2982
6f9485af
SM		 2983 err = mlx5e_open_channels(priv, &new_channels);
2984 if (err)
2985 goto out;
08fb1dac 2986
2e20a151 2987 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2988out:
08fb1dac 2989 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2990 return err;
2991}
2992
2993static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2994 __be16 proto, struct tc_to_netdev *tc)
2995{
e8f887ac
AV		 2996 struct mlx5e_priv *priv = netdev_priv(dev);
2997
2998 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2999 goto mqprio;
3000
3001 switch (tc->type) {
e3a2b7ed
AV		 3002 case TC_SETUP_CLSFLOWER:
3003 switch (tc->cls_flower->command) {
3004 case TC_CLSFLOWER_REPLACE:
3005 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3006 case TC_CLSFLOWER_DESTROY:
3007 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 3008 case TC_CLSFLOWER_STATS:
3009 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 3010 }
e8f887ac
AV		 3011 default:
3012 return -EOPNOTSUPP;
3013 }
3014
3015mqprio:
67ba422e 3016 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 3017 return -EINVAL;
3018
56f36acd
AN		 3019 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3020
3021 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 3022}
3023
bc1f4470 3024static void
f62b8bb8
AV		 3025mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3026{
3027 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3028 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3029 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3030 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3031
370bad0f
OG		 3032 if (mlx5e_is_uplink_rep(priv)) {
3033 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3034 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3035 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3036 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3037 } else {
3038 stats->rx_packets = sstats->rx_packets;
3039 stats->rx_bytes = sstats->rx_bytes;
3040 stats->tx_packets = sstats->tx_packets;
3041 stats->tx_bytes = sstats->tx_bytes;
3042 stats->tx_dropped = sstats->tx_queue_dropped;
3043 }
269e6b3a
GP		 3044
3045 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3046
3047 stats->rx_length_errors =
9218b44d
GP		 3048 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3049 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3050 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3051 stats->rx_crc_errors =
9218b44d
GP		 3052 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3053 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3054 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 3055 stats->tx_carrier_errors =
9218b44d 3056 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 3057 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3058 stats->rx_frame_errors;
3059 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3060
3061 /* vport multicast also counts packets that are dropped due to steering
3062 * or rx out of buffer
3063 */
9218b44d
GP		 3064 stats->multicast =
3065 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 3066
f62b8bb8
AV		 3067}
3068
3069static void mlx5e_set_rx_mode(struct net_device *dev)
3070{
3071 struct mlx5e_priv *priv = netdev_priv(dev);
3072
7bb29755 3073 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3074}
3075
3076static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3077{
3078 struct mlx5e_priv *priv = netdev_priv(netdev);
3079 struct sockaddr *saddr = addr;
3080
3081 if (!is_valid_ether_addr(saddr->sa_data))
3082 return -EADDRNOTAVAIL;
3083
3084 netif_addr_lock_bh(netdev);
3085 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3086 netif_addr_unlock_bh(netdev);
3087
7bb29755 3088 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3089
3090 return 0;
3091}
3092
0e405443
GP		 3093#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3094 do { \
3095 if (enable) \
3096 netdev->features |= feature; \
3097 else \
3098 netdev->features &= ~feature; \
3099 } while (0)
3100
3101typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3102
3103static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3104{
3105 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3106 struct mlx5e_channels new_channels = {};
3107 int err = 0;
3108 bool reset;
f62b8bb8
AV		 3109
3110 mutex_lock(&priv->state_lock);
f62b8bb8 3111
2e20a151
SM		 3112 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3113 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3114
2e20a151
SM		 3115 new_channels.params = priv->channels.params;
3116 new_channels.params.lro_en = enable;
3117
3118 if (!reset) {
3119 priv->channels.params = new_channels.params;
3120 err = mlx5e_modify_tirs_lro(priv);
3121 goto out;
98e81b0a 3122 }
f62b8bb8 3123
2e20a151
SM		 3124 err = mlx5e_open_channels(priv, &new_channels);
3125 if (err)
3126 goto out;
0e405443 3127
2e20a151
SM		 3128 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3129out:
9b37b07f 3130 mutex_unlock(&priv->state_lock);
0e405443
GP		 3131 return err;
3132}
3133
3134static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3135{
3136 struct mlx5e_priv *priv = netdev_priv(netdev);
3137
3138 if (enable)
3139 mlx5e_enable_vlan_filter(priv);
3140 else
3141 mlx5e_disable_vlan_filter(priv);
3142
3143 return 0;
3144}
3145
3146static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3147{
3148 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3149
0e405443 3150 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3151 netdev_err(netdev,
3152 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3153 return -EINVAL;
3154 }
3155
0e405443
GP		 3156 return 0;
3157}
3158
94cb1ebb
EBE		 3159static int set_feature_rx_all(struct net_device *netdev, bool enable)
3160{
3161 struct mlx5e_priv *priv = netdev_priv(netdev);
3162 struct mlx5_core_dev *mdev = priv->mdev;
3163
3164 return mlx5_set_port_fcs(mdev, !enable);
3165}
3166
102722fc
GE		 3167static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3168{
3169 struct mlx5e_priv *priv = netdev_priv(netdev);
3170 int err;
3171
3172 mutex_lock(&priv->state_lock);
3173
3174 priv->channels.params.scatter_fcs_en = enable;
3175 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3176 if (err)
3177 priv->channels.params.scatter_fcs_en = !enable;
3178
3179 mutex_unlock(&priv->state_lock);
3180
3181 return err;
3182}
3183
36350114
GP		 3184static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3185{
3186 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3187 int err = 0;
36350114
GP		 3188
3189 mutex_lock(&priv->state_lock);
3190
6a9764ef 3191 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3192 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3193 goto unlock;
3194
3195 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3196 if (err)
6a9764ef 3197 priv->channels.params.vlan_strip_disable = enable;
36350114 3198
ff9c852f 3199unlock:
36350114
GP		 3200 mutex_unlock(&priv->state_lock);
3201
3202 return err;
3203}
3204
45bf454a
MG		 3205#ifdef CONFIG_RFS_ACCEL
3206static int set_feature_arfs(struct net_device *netdev, bool enable)
3207{
3208 struct mlx5e_priv *priv = netdev_priv(netdev);
3209 int err;
3210
3211 if (enable)
3212 err = mlx5e_arfs_enable(priv);
3213 else
3214 err = mlx5e_arfs_disable(priv);
3215
3216 return err;
3217}
3218#endif
3219
0e405443
GP		 3220static int mlx5e_handle_feature(struct net_device *netdev,
3221 netdev_features_t wanted_features,
3222 netdev_features_t feature,
3223 mlx5e_feature_handler feature_handler)
3224{
3225 netdev_features_t changes = wanted_features ^ netdev->features;
3226 bool enable = !!(wanted_features & feature);
3227 int err;
3228
3229 if (!(changes & feature))
3230 return 0;
3231
3232 err = feature_handler(netdev, enable);
3233 if (err) {
3234 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3235 enable ? "Enable" : "Disable", feature, err);
3236 return err;
3237 }
3238
3239 MLX5E_SET_FEATURE(netdev, feature, enable);
3240 return 0;
3241}
3242
3243static int mlx5e_set_features(struct net_device *netdev,
3244 netdev_features_t features)
3245{
3246 int err;
3247
3248 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3249 set_feature_lro);
3250 err |= mlx5e_handle_feature(netdev, features,
3251 NETIF_F_HW_VLAN_CTAG_FILTER,
3252 set_feature_vlan_filter);
3253 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3254 set_feature_tc_num_filters);
94cb1ebb
EBE		 3255 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3256 set_feature_rx_all);
102722fc
GE		 3257 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3258 set_feature_rx_fcs);
36350114
GP		 3259 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3260 set_feature_rx_vlan);
45bf454a
MG		 3261#ifdef CONFIG_RFS_ACCEL
3262 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3263 set_feature_arfs);
3264#endif
0e405443
GP		 3265
3266 return err ? -EINVAL : 0;
f62b8bb8
AV		 3267}
3268
3269static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3270{
3271 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3272 struct mlx5e_channels new_channels = {};
3273 int curr_mtu;
98e81b0a 3274 int err = 0;
506753b0 3275 bool reset;
f62b8bb8 3276
f62b8bb8 3277 mutex_lock(&priv->state_lock);
98e81b0a 3278
6a9764ef
SM		 3279 reset = !priv->channels.params.lro_en &&
3280 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3281 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3282
2e20a151 3283 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3284
2e20a151 3285 curr_mtu = netdev->mtu;
f62b8bb8 3286 netdev->mtu = new_mtu;
98e81b0a 3287
2e20a151
SM		 3288 if (!reset) {
3289 mlx5e_set_dev_port_mtu(priv);
3290 goto out;
3291 }
98e81b0a 3292
2e20a151
SM		 3293 new_channels.params = priv->channels.params;
3294 err = mlx5e_open_channels(priv, &new_channels);
3295 if (err) {
3296 netdev->mtu = curr_mtu;
3297 goto out;
3298 }
3299
3300 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3301
2e20a151
SM		 3302out:
3303 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3304 return err;
3305}
3306
ef9814de
EBE		 3307static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3308{
3309 switch (cmd) {
3310 case SIOCSHWTSTAMP:
3311 return mlx5e_hwstamp_set(dev, ifr);
3312 case SIOCGHWTSTAMP:
3313 return mlx5e_hwstamp_get(dev, ifr);
3314 default:
3315 return -EOPNOTSUPP;
3316 }
3317}
3318
66e49ded
SM		 3319static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3320{
3321 struct mlx5e_priv *priv = netdev_priv(dev);
3322 struct mlx5_core_dev *mdev = priv->mdev;
3323
3324 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3325}
3326
79aab093
MS		 3327static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3328 __be16 vlan_proto)
66e49ded
SM		 3329{
3330 struct mlx5e_priv *priv = netdev_priv(dev);
3331 struct mlx5_core_dev *mdev = priv->mdev;
3332
79aab093
MS		 3333 if (vlan_proto != htons(ETH_P_8021Q))
3334 return -EPROTONOSUPPORT;
3335
66e49ded
SM		 3336 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3337 vlan, qos);
3338}
3339
f942380c
MHY		 3340static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3341{
3342 struct mlx5e_priv *priv = netdev_priv(dev);
3343 struct mlx5_core_dev *mdev = priv->mdev;
3344
3345 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3346}
3347
1edc57e2
MHY		 3348static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3349{
3350 struct mlx5e_priv *priv = netdev_priv(dev);
3351 struct mlx5_core_dev *mdev = priv->mdev;
3352
3353 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3354}
bd77bf1c
MHY		 3355
3356static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3357 int max_tx_rate)
3358{
3359 struct mlx5e_priv *priv = netdev_priv(dev);
3360 struct mlx5_core_dev *mdev = priv->mdev;
3361
bd77bf1c 3362 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3363 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3364}
3365
66e49ded
SM		 3366static int mlx5_vport_link2ifla(u8 esw_link)
3367{
3368 switch (esw_link) {
3369 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3370 return IFLA_VF_LINK_STATE_DISABLE;
3371 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3372 return IFLA_VF_LINK_STATE_ENABLE;
3373 }
3374 return IFLA_VF_LINK_STATE_AUTO;
3375}
3376
3377static int mlx5_ifla_link2vport(u8 ifla_link)
3378{
3379 switch (ifla_link) {
3380 case IFLA_VF_LINK_STATE_DISABLE:
3381 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3382 case IFLA_VF_LINK_STATE_ENABLE:
3383 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3384 }
3385 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3386}
3387
3388static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3389 int link_state)
3390{
3391 struct mlx5e_priv *priv = netdev_priv(dev);
3392 struct mlx5_core_dev *mdev = priv->mdev;
3393
3394 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3395 mlx5_ifla_link2vport(link_state));
3396}
3397
3398static int mlx5e_get_vf_config(struct net_device *dev,
3399 int vf, struct ifla_vf_info *ivi)
3400{
3401 struct mlx5e_priv *priv = netdev_priv(dev);
3402 struct mlx5_core_dev *mdev = priv->mdev;
3403 int err;
3404
3405 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3406 if (err)
3407 return err;
3408 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3409 return 0;
3410}
3411
3412static int mlx5e_get_vf_stats(struct net_device *dev,
3413 int vf, struct ifla_vf_stats *vf_stats)
3414{
3415 struct mlx5e_priv *priv = netdev_priv(dev);
3416 struct mlx5_core_dev *mdev = priv->mdev;
3417
3418 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3419 vf_stats);
3420}
3421
1ad9a00a
PB		 3422static void mlx5e_add_vxlan_port(struct net_device *netdev,
3423 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3424{
3425 struct mlx5e_priv *priv = netdev_priv(netdev);
3426
974c3f30
AD		 3427 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3428 return;
3429
b3f63c3d
MF		 3430 if (!mlx5e_vxlan_allowed(priv->mdev))
3431 return;
3432
974c3f30 3433 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3434}
3435
1ad9a00a
PB		 3436static void mlx5e_del_vxlan_port(struct net_device *netdev,
3437 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3438{
3439 struct mlx5e_priv *priv = netdev_priv(netdev);
3440
974c3f30
AD		 3441 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3442 return;
3443
b3f63c3d
MF		 3444 if (!mlx5e_vxlan_allowed(priv->mdev))
3445 return;
3446
974c3f30 3447 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3448}
3449
3450static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3451 struct sk_buff *skb,
3452 netdev_features_t features)
3453{
3454 struct udphdr *udph;
3455 u16 proto;
3456 u16 port = 0;
3457
3458 switch (vlan_get_protocol(skb)) {
3459 case htons(ETH_P_IP):
3460 proto = ip_hdr(skb)->protocol;
3461 break;
3462 case htons(ETH_P_IPV6):
3463 proto = ipv6_hdr(skb)->nexthdr;
3464 break;
3465 default:
3466 goto out;
3467 }
3468
3469 if (proto == IPPROTO_UDP) {
3470 udph = udp_hdr(skb);
3471 port = be16_to_cpu(udph->dest);
3472 }
3473
3474 /* Verify if UDP port is being offloaded by HW */
3475 if (port && mlx5e_vxlan_lookup_port(priv, port))
3476 return features;
3477
3478out:
3479 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3480 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3481}
3482
3483static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3484 struct net_device *netdev,
3485 netdev_features_t features)
3486{
3487 struct mlx5e_priv *priv = netdev_priv(netdev);
3488
3489 features = vlan_features_check(skb, features);
3490 features = vxlan_features_check(skb, features);
3491
3492 /* Validate if the tunneled packet is being offloaded by HW */
3493 if (skb->encapsulation &&
3494 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3495 return mlx5e_vxlan_features_check(priv, skb, features);
3496
3497 return features;
3498}
3499
3947ca18
DJ		 3500static void mlx5e_tx_timeout(struct net_device *dev)
3501{
3502 struct mlx5e_priv *priv = netdev_priv(dev);
3503 bool sched_work = false;
3504 int i;
3505
3506 netdev_err(dev, "TX timeout detected\n");
3507
6a9764ef 3508 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3509 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3510
2c1ccc99 3511 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3512 continue;
3513 sched_work = true;
c0f1147d 3514 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3515 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3516 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3517 }
3518
3519 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3520 schedule_work(&priv->tx_timeout_work);
3521}
3522
86994156
RS		 3523static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3524{
3525 struct mlx5e_priv *priv = netdev_priv(netdev);
3526 struct bpf_prog *old_prog;
3527 int err = 0;
3528 bool reset, was_opened;
3529 int i;
3530
3531 mutex_lock(&priv->state_lock);
3532
3533 if ((netdev->features & NETIF_F_LRO) && prog) {
3534 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3535 err = -EINVAL;
3536 goto unlock;
3537 }
3538
3539 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3540 /* no need for full reset when exchanging programs */
6a9764ef 3541 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3542
3543 if (was_opened && reset)
3544 mlx5e_close_locked(netdev);
c54c0629
DB		 3545 if (was_opened && !reset) {
3546 /* num_channels is invariant here, so we can take the
3547 * batched reference right upfront.
3548 */
6a9764ef 3549 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3550 if (IS_ERR(prog)) {
3551 err = PTR_ERR(prog);
3552 goto unlock;
3553 }
3554 }
86994156 3555
c54c0629
DB		 3556 /* exchange programs, extra prog reference we got from caller
3557 * as long as we don't fail from this point onwards.
3558 */
6a9764ef 3559 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3560 if (old_prog)
3561 bpf_prog_put(old_prog);
3562
3563 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3564 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3565
3566 if (was_opened && reset)
3567 mlx5e_open_locked(netdev);
3568
3569 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3570 goto unlock;
3571
3572 /* exchanging programs w/o reset, we update ref counts on behalf
3573 * of the channels RQs here.
3574 */
ff9c852f
SM		 3575 for (i = 0; i < priv->channels.num; i++) {
3576 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3577
c0f1147d 3578 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3579 napi_synchronize(&c->napi);
3580 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3581
3582 old_prog = xchg(&c->rq.xdp_prog, prog);
3583
c0f1147d 3584 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3585 /* napi_schedule in case we have missed anything */
3586 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3587 napi_schedule(&c->napi);
3588
3589 if (old_prog)
3590 bpf_prog_put(old_prog);
3591 }
3592
3593unlock:
3594 mutex_unlock(&priv->state_lock);
3595 return err;
3596}
3597
3598static bool mlx5e_xdp_attached(struct net_device *dev)
3599{
3600 struct mlx5e_priv *priv = netdev_priv(dev);
3601
6a9764ef 3602 return !!priv->channels.params.xdp_prog;
86994156
RS		 3603}
3604
3605static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3606{
3607 switch (xdp->command) {
3608 case XDP_SETUP_PROG:
3609 return mlx5e_xdp_set(dev, xdp->prog);
3610 case XDP_QUERY_PROG:
3611 xdp->prog_attached = mlx5e_xdp_attached(dev);
3612 return 0;
3613 default:
3614 return -EINVAL;
3615 }
3616}
3617
80378384
CO		 3618#ifdef CONFIG_NET_POLL_CONTROLLER
3619/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3620 * reenabling interrupts.
3621 */
3622static void mlx5e_netpoll(struct net_device *dev)
3623{
3624 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3625 struct mlx5e_channels *chs = &priv->channels;
3626
80378384
CO		 3627 int i;
3628
ff9c852f
SM		 3629 for (i = 0; i < chs->num; i++)
3630 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3631}
3632#endif
3633
b0eed40e 3634static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3635 .ndo_open = mlx5e_open,
3636 .ndo_stop = mlx5e_close,
3637 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3638 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3639 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3640 .ndo_get_stats64 = mlx5e_get_stats,
3641 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3642 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3643 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3644 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3645 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3646 .ndo_change_mtu = mlx5e_change_mtu,
3647 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3648 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3649#ifdef CONFIG_RFS_ACCEL
3650 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3651#endif
3947ca18 3652 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3653 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3654#ifdef CONFIG_NET_POLL_CONTROLLER
3655 .ndo_poll_controller = mlx5e_netpoll,
3656#endif
b0eed40e
SM		 3657};
3658
3659static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3660 .ndo_open = mlx5e_open,
3661 .ndo_stop = mlx5e_close,
3662 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3663 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3664 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3665 .ndo_get_stats64 = mlx5e_get_stats,
3666 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3667 .ndo_set_mac_address = mlx5e_set_mac,
3668 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3669 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3670 .ndo_set_features = mlx5e_set_features,
3671 .ndo_change_mtu = mlx5e_change_mtu,
3672 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3673 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3674 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3675 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3676 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3677#ifdef CONFIG_RFS_ACCEL
3678 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3679#endif
b0eed40e
SM		 3680 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3681 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3682 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3683 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3684 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3685 .ndo_get_vf_config = mlx5e_get_vf_config,
3686 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3687 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3688 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3689 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3690#ifdef CONFIG_NET_POLL_CONTROLLER
3691 .ndo_poll_controller = mlx5e_netpoll,
3692#endif
370bad0f
OG		 3693 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3694 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3695};
3696
3697static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3698{
3699 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3700 return -EOPNOTSUPP;
f62b8bb8
AV		 3701 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3702 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3703 !MLX5_CAP_ETH(mdev, csum_cap) ||
3704 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3705 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3706 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3707 MLX5_CAP_FLOWTABLE(mdev,
3708 flow_table_properties_nic_receive.max_ft_level)
3709 < 3) {
f62b8bb8
AV		 3710 mlx5_core_warn(mdev,
3711 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3712 return -EOPNOTSUPP;
f62b8bb8 3713 }
66189961
TT		 3714 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3715 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3716 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3717 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3718
f62b8bb8
AV		 3719 return 0;
3720}
3721
58d52291
AS		 3722u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3723{
3724 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3725
3726 return bf_buf_size -
3727 sizeof(struct mlx5e_tx_wqe) +
3728 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3729}
3730
d8c9660d
TT		 3731void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3732 u32 *indirection_rqt, int len,
85082dba
TT		 3733 int num_channels)
3734{
d8c9660d
TT		 3735 int node = mdev->priv.numa_node;
3736 int node_num_of_cores;
85082dba
TT		 3737 int i;
3738
d8c9660d
TT		 3739 if (node == -1)
3740 node = first_online_node;
3741
3742 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3743
3744 if (node_num_of_cores)
3745 num_channels = min_t(int, num_channels, node_num_of_cores);
3746
85082dba
TT		 3747 for (i = 0; i < len; i++)
3748 indirection_rqt[i] = i % num_channels;
3749}
3750
b797a684
SM		 3751static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3752{
3753 enum pcie_link_width width;
3754 enum pci_bus_speed speed;
3755 int err = 0;
3756
3757 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3758 if (err)
3759 return err;
3760
3761 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3762 return -EINVAL;
3763
3764 switch (speed) {
3765 case PCIE_SPEED_2_5GT:
3766 *pci_bw = 2500 * width;
3767 break;
3768 case PCIE_SPEED_5_0GT:
3769 *pci_bw = 5000 * width;
3770 break;
3771 case PCIE_SPEED_8_0GT:
3772 *pci_bw = 8000 * width;
3773 break;
3774 default:
3775 return -EINVAL;
3776 }
3777
3778 return 0;
3779}
3780
3781static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3782{
3783 return (link_speed && pci_bw &&
3784 (pci_bw < 40000) && (pci_bw < link_speed));
3785}
3786
0f6e4cf6
EBE		 3787static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3788{
3789 return !(link_speed && pci_bw &&
3790 (pci_bw <= 16000) && (pci_bw < link_speed));
3791}
3792
9908aa29
TT		 3793void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3794{
3795 params->rx_cq_period_mode = cq_period_mode;
3796
3797 params->rx_cq_moderation.pkts =
3798 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3799 params->rx_cq_moderation.usec =
3800 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3801
3802 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3803 params->rx_cq_moderation.usec =
3804 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3805
457fcd8a
SM		 3806 if (params->rx_am_enabled)
3807 params->rx_cq_moderation =
3808 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3809
6a9764ef
SM		 3810 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3811 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3812}
3813
2b029556
SM		 3814u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3815{
3816 int i;
3817
3818 /* The supported periods are organized in ascending order */
3819 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3820 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3821 break;
3822
3823 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3824}
3825
8f493ffd
SM		 3826void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3827 struct mlx5e_params *params,
3828 u16 max_channels)
f62b8bb8 3829{
6a9764ef 3830 u8 cq_period_mode = 0;
b797a684
SM		 3831 u32 link_speed = 0;
3832 u32 pci_bw = 0;
2fc4bfb7 3833
6a9764ef
SM		 3834 params->num_channels = max_channels;
3835 params->num_tc = 1;
2b029556 3836
0f6e4cf6
EBE		 3837 mlx5e_get_max_linkspeed(mdev, &link_speed);
3838 mlx5e_get_pci_bw(mdev, &pci_bw);
3839 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3840 link_speed, pci_bw);
3841
6a9764ef
SM		 3842 /* SQ */
3843 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3844 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3845 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3846
b797a684 3847 /* set CQE compression */
6a9764ef 3848 params->rx_cqe_compress_def = false;
b797a684 3849 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
0f6e4cf6 3850 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 3851 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 3852
6a9764ef
SM		 3853 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3854
3855 /* RQ */
3856 mlx5e_set_rq_params(mdev, params);
b797a684 3857
6a9764ef 3858 /* HW LRO */
5426a0b2 3859 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 3860 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 3861 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 3862 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3863
6a9764ef
SM		 3864 /* CQ moderation params */
3865 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3866 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3867 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3868 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3869 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3870
6a9764ef
SM		 3871 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3872 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3873
6a9764ef
SM		 3874 /* TX inline */
3875 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3876 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3877 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3878 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3879 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3880
6a9764ef
SM		 3881 /* RSS */
3882 params->rss_hfunc = ETH_RSS_HASH_XOR;
3883 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3884 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3885 MLX5E_INDIR_RQT_SIZE, max_channels);
3886}
f62b8bb8 3887
6a9764ef
SM		 3888static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3889 struct net_device *netdev,
3890 const struct mlx5e_profile *profile,
3891 void *ppriv)
3892{
3893 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3894
6a9764ef
SM		 3895 priv->mdev = mdev;
3896 priv->netdev = netdev;
3897 priv->profile = profile;
3898 priv->ppriv = ppriv;
2d75b2bc 3899
6a9764ef 3900 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3901
f62b8bb8
AV		 3902 mutex_init(&priv->state_lock);
3903
3904 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3905 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3906 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3907 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3908}
3909
3910static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3911{
3912 struct mlx5e_priv *priv = netdev_priv(netdev);
3913
e1d7d349 3914 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3915 if (is_zero_ether_addr(netdev->dev_addr) &&
3916 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3917 eth_hw_addr_random(netdev);
3918 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3919 }
f62b8bb8
AV		 3920}
3921
cb67b832
HHZ		 3922static const struct switchdev_ops mlx5e_switchdev_ops = {
3923 .switchdev_port_attr_get = mlx5e_attr_get,
3924};
3925
6bfd390b 3926static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3927{
3928 struct mlx5e_priv *priv = netdev_priv(netdev);
3929 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3930 bool fcs_supported;
3931 bool fcs_enabled;
f62b8bb8
AV		 3932
3933 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3934
08fb1dac 3935 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3936 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3937#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3938 if (MLX5_CAP_GEN(mdev, qos))
3939 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3940#endif
3941 } else {
b0eed40e 3942 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3943 }
66e49ded 3944
f62b8bb8
AV		 3945 netdev->watchdog_timeo = 15 * HZ;
3946
3947 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3948
12be4b21 3949 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3950 netdev->vlan_features |= NETIF_F_IP_CSUM;
3951 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3952 netdev->vlan_features |= NETIF_F_GRO;
3953 netdev->vlan_features |= NETIF_F_TSO;
3954 netdev->vlan_features |= NETIF_F_TSO6;
3955 netdev->vlan_features |= NETIF_F_RXCSUM;
3956 netdev->vlan_features |= NETIF_F_RXHASH;
3957
3958 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3959 netdev->vlan_features |= NETIF_F_LRO;
3960
3961 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3962 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3963 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3964 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3965
b3f63c3d 3966 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3967 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3968 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3969 NETIF_F_GSO_PARTIAL;
b3f63c3d 3970 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3971 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3972 netdev->hw_enc_features |= NETIF_F_TSO;
3973 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3974 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3975 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3976 NETIF_F_GSO_PARTIAL;
3977 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3978 }
3979
94cb1ebb
EBE		 3980 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3981
3982 if (fcs_supported)
3983 netdev->hw_features |= NETIF_F_RXALL;
3984
102722fc
GE		 3985 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3986 netdev->hw_features |= NETIF_F_RXFCS;
3987
f62b8bb8 3988 netdev->features = netdev->hw_features;
6a9764ef 3989 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 3990 netdev->features &= ~NETIF_F_LRO;
3991
94cb1ebb
EBE		 3992 if (fcs_enabled)
3993 netdev->features &= ~NETIF_F_RXALL;
3994
102722fc
GE		 3995 if (!priv->channels.params.scatter_fcs_en)
3996 netdev->features &= ~NETIF_F_RXFCS;
3997
e8f887ac
AV		 3998#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3999 if (FT_CAP(flow_modify_en) &&
4000 FT_CAP(modify_root) &&
4001 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4002 FT_CAP(flow_table_modify)) {
4003 netdev->hw_features |= NETIF_F_HW_TC;
4004#ifdef CONFIG_RFS_ACCEL
4005 netdev->hw_features |= NETIF_F_NTUPLE;
4006#endif
4007 }
e8f887ac 4008
f62b8bb8
AV		 4009 netdev->features |= NETIF_F_HIGHDMA;
4010
4011 netdev->priv_flags |= IFF_UNICAST_FLT;
4012
4013 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 4014
4015#ifdef CONFIG_NET_SWITCHDEV
4016 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4017 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4018#endif
f62b8bb8
AV		 4019}
4020
593cf338
RS		 4021static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4022{
4023 struct mlx5_core_dev *mdev = priv->mdev;
4024 int err;
4025
4026 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4027 if (err) {
4028 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4029 priv->q_counter = 0;
4030 }
4031}
4032
4033static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4034{
4035 if (!priv->q_counter)
4036 return;
4037
4038 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4039}
4040
6bfd390b
HHZ		 4041static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4042 struct net_device *netdev,
127ea380
HHZ		 4043 const struct mlx5e_profile *profile,
4044 void *ppriv)
6bfd390b
HHZ		 4045{
4046 struct mlx5e_priv *priv = netdev_priv(netdev);
4047
127ea380 4048 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 4049 mlx5e_build_nic_netdev(netdev);
4050 mlx5e_vxlan_init(priv);
4051}
4052
4053static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4054{
4055 mlx5e_vxlan_cleanup(priv);
127ea380 4056
6a9764ef
SM		 4057 if (priv->channels.params.xdp_prog)
4058 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4059}
4060
4061static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4062{
4063 struct mlx5_core_dev *mdev = priv->mdev;
4064 int err;
6bfd390b 4065
8f493ffd
SM		 4066 err = mlx5e_create_indirect_rqt(priv);
4067 if (err)
6bfd390b 4068 return err;
6bfd390b
HHZ		 4069
4070 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4071 if (err)
6bfd390b 4072 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4073
4074 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4075 if (err)
6bfd390b 4076 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4077
4078 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4079 if (err)
6bfd390b 4080 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4081
4082 err = mlx5e_create_flow_steering(priv);
4083 if (err) {
4084 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4085 goto err_destroy_direct_tirs;
4086 }
4087
4088 err = mlx5e_tc_init(priv);
4089 if (err)
4090 goto err_destroy_flow_steering;
4091
4092 return 0;
4093
4094err_destroy_flow_steering:
4095 mlx5e_destroy_flow_steering(priv);
4096err_destroy_direct_tirs:
4097 mlx5e_destroy_direct_tirs(priv);
4098err_destroy_indirect_tirs:
4099 mlx5e_destroy_indirect_tirs(priv);
4100err_destroy_direct_rqts:
8f493ffd 4101 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4102err_destroy_indirect_rqts:
4103 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4104 return err;
4105}
4106
4107static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4108{
6bfd390b
HHZ		 4109 mlx5e_tc_cleanup(priv);
4110 mlx5e_destroy_flow_steering(priv);
4111 mlx5e_destroy_direct_tirs(priv);
4112 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4113 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4114 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4115}
4116
4117static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4118{
4119 int err;
4120
4121 err = mlx5e_create_tises(priv);
4122 if (err) {
4123 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4124 return err;
4125 }
4126
4127#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4128 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4129#endif
4130 return 0;
4131}
4132
4133static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4134{
4135 struct net_device *netdev = priv->netdev;
4136 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4137 u16 max_mtu;
4138
4139 mlx5e_init_l2_addr(priv);
4140
4141 /* MTU range: 68 - hw-specific max */
4142 netdev->min_mtu = ETH_MIN_MTU;
4143 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4144 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4145 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4146
7907f23a
AH		 4147 mlx5_lag_add(mdev, netdev);
4148
6bfd390b 4149 mlx5e_enable_async_events(priv);
127ea380 4150
1d447a39
SM		 4151 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4152 mlx5e_register_vport_reps(priv);
2c3b5bee 4153
610e89e0
SM		 4154 if (netdev->reg_state != NETREG_REGISTERED)
4155 return;
4156
4157 /* Device already registered: sync netdev system state */
4158 if (mlx5e_vxlan_allowed(mdev)) {
4159 rtnl_lock();
4160 udp_tunnel_get_rx_info(netdev);
4161 rtnl_unlock();
4162 }
4163
4164 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4165
4166 rtnl_lock();
4167 if (netif_running(netdev))
4168 mlx5e_open(netdev);
4169 netif_device_attach(netdev);
4170 rtnl_unlock();
6bfd390b
HHZ		 4171}
4172
4173static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4174{
3deef8ce 4175 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4176
2c3b5bee
SM		 4177 rtnl_lock();
4178 if (netif_running(priv->netdev))
4179 mlx5e_close(priv->netdev);
4180 netif_device_detach(priv->netdev);
4181 rtnl_unlock();
4182
6bfd390b 4183 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4184
3deef8ce 4185 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1d447a39
SM		 4186 mlx5e_unregister_vport_reps(priv);
4187
6bfd390b 4188 mlx5e_disable_async_events(priv);
3deef8ce 4189 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4190}
4191
4192static const struct mlx5e_profile mlx5e_nic_profile = {
4193 .init = mlx5e_nic_init,
4194 .cleanup = mlx5e_nic_cleanup,
4195 .init_rx = mlx5e_init_nic_rx,
4196 .cleanup_rx = mlx5e_cleanup_nic_rx,
4197 .init_tx = mlx5e_init_nic_tx,
4198 .cleanup_tx = mlx5e_cleanup_nic_tx,
4199 .enable = mlx5e_nic_enable,
4200 .disable = mlx5e_nic_disable,
4201 .update_stats = mlx5e_update_stats,
4202 .max_nch = mlx5e_get_max_num_channels,
20fd0c19
SM		 4203 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4204 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4205 .max_tc = MLX5E_MAX_NUM_TC,
4206};
4207
2c3b5bee
SM		 4208/* mlx5e generic netdev management API (move to en_common.c) */
4209
26e59d80
MHY		 4210struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4211 const struct mlx5e_profile *profile,
4212 void *ppriv)
f62b8bb8 4213{
26e59d80 4214 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4215 struct net_device *netdev;
4216 struct mlx5e_priv *priv;
f62b8bb8 4217
08fb1dac 4218 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4219 nch * profile->max_tc,
08fb1dac 4220 nch);
f62b8bb8
AV		 4221 if (!netdev) {
4222 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4223 return NULL;
4224 }
4225
be4891af
SM		 4226#ifdef CONFIG_RFS_ACCEL
4227 netdev->rx_cpu_rmap = mdev->rmap;
4228#endif
4229
127ea380 4230 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4231
4232 netif_carrier_off(netdev);
4233
4234 priv = netdev_priv(netdev);
4235
7bb29755
MF		 4236 priv->wq = create_singlethread_workqueue("mlx5e");
4237 if (!priv->wq)
26e59d80
MHY		 4238 goto err_cleanup_nic;
4239
4240 return netdev;
4241
4242err_cleanup_nic:
4243 profile->cleanup(priv);
4244 free_netdev(netdev);
4245
4246 return NULL;
4247}
4248
2c3b5bee 4249int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4250{
2c3b5bee 4251 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4252 const struct mlx5e_profile *profile;
26e59d80
MHY		 4253 int err;
4254
26e59d80
MHY		 4255 profile = priv->profile;
4256 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4257
6bfd390b
HHZ		 4258 err = profile->init_tx(priv);
4259 if (err)
ec8b9981 4260 goto out;
5c50368f 4261
a43b25da 4262 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4263 if (err) {
4264 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4265 goto err_cleanup_tx;
5c50368f
AS		 4266 }
4267
6bfd390b
HHZ		 4268 err = profile->init_rx(priv);
4269 if (err)
5c50368f 4270 goto err_close_drop_rq;
5c50368f 4271
593cf338
RS		 4272 mlx5e_create_q_counter(priv);
4273
6bfd390b
HHZ		 4274 if (profile->enable)
4275 profile->enable(priv);
f62b8bb8 4276
26e59d80 4277 return 0;
5c50368f
AS		 4278
4279err_close_drop_rq:
a43b25da 4280 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4281
6bfd390b
HHZ		 4282err_cleanup_tx:
4283 profile->cleanup_tx(priv);
5c50368f 4284
26e59d80
MHY		 4285out:
4286 return err;
f62b8bb8
AV		 4287}
4288
2c3b5bee 4289void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4290{
26e59d80
MHY		 4291 const struct mlx5e_profile *profile = priv->profile;
4292
4293 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4294
37f304d1
SM		 4295 if (profile->disable)
4296 profile->disable(priv);
4297 flush_workqueue(priv->wq);
4298
26e59d80
MHY		 4299 mlx5e_destroy_q_counter(priv);
4300 profile->cleanup_rx(priv);
a43b25da 4301 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4302 profile->cleanup_tx(priv);
26e59d80
MHY		 4303 cancel_delayed_work_sync(&priv->update_stats_work);
4304}
4305
2c3b5bee
SM		 4306void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4307{
4308 const struct mlx5e_profile *profile = priv->profile;
4309 struct net_device *netdev = priv->netdev;
4310
4311 destroy_workqueue(priv->wq);
4312 if (profile->cleanup)
4313 profile->cleanup(priv);
4314 free_netdev(netdev);
4315}
4316
26e59d80
MHY		 4317/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4318 * hardware contexts and to connect it to the current netdev.
4319 */
4320static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4321{
4322 struct mlx5e_priv *priv = vpriv;
4323 struct net_device *netdev = priv->netdev;
4324 int err;
4325
4326 if (netif_device_present(netdev))
4327 return 0;
4328
4329 err = mlx5e_create_mdev_resources(mdev);
4330 if (err)
4331 return err;
4332
2c3b5bee 4333 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4334 if (err) {
4335 mlx5e_destroy_mdev_resources(mdev);
4336 return err;
4337 }
4338
4339 return 0;
4340}
4341
4342static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4343{
4344 struct mlx5e_priv *priv = vpriv;
4345 struct net_device *netdev = priv->netdev;
4346
4347 if (!netif_device_present(netdev))
4348 return;
4349
2c3b5bee 4350 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4351 mlx5e_destroy_mdev_resources(mdev);
4352}
4353
b50d292b
HHZ		 4354static void *mlx5e_add(struct mlx5_core_dev *mdev)
4355{
127ea380 4356 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4357 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
1d447a39 4358 struct mlx5e_rep_priv *rpriv = NULL;
26e59d80
MHY		 4359 void *priv;
4360 int vport;
4361 int err;
4362 struct net_device *netdev;
b50d292b 4363
26e59d80
MHY		 4364 err = mlx5e_check_required_hca_cap(mdev);
4365 if (err)
b50d292b
HHZ		 4366 return NULL;
4367
1d447a39
SM		 4368 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4369 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4370 if (!rpriv) {
4371 mlx5_core_warn(mdev,
4372 "Not creating net device, Failed to alloc rep priv data\n");
4373 return NULL;
4374 }
4375 rpriv->rep = &esw->offloads.vport_reps[0];
4376 }
127ea380 4377
1d447a39 4378 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4379 if (!netdev) {
4380 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4381 goto err_unregister_reps;
4382 }
4383
4384 priv = netdev_priv(netdev);
4385
4386 err = mlx5e_attach(mdev, priv);
4387 if (err) {
4388 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4389 goto err_destroy_netdev;
4390 }
4391
4392 err = register_netdev(netdev);
4393 if (err) {
4394 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4395 goto err_detach;
b50d292b 4396 }
26e59d80
MHY		 4397
4398 return priv;
4399
4400err_detach:
4401 mlx5e_detach(mdev, priv);
4402
4403err_destroy_netdev:
2c3b5bee 4404 mlx5e_destroy_netdev(priv);
26e59d80
MHY		 4405
4406err_unregister_reps:
4407 for (vport = 1; vport < total_vfs; vport++)
4408 mlx5_eswitch_unregister_vport_rep(esw, vport);
4409
1d447a39 4410 kfree(rpriv);
26e59d80 4411 return NULL;
b50d292b
HHZ		 4412}
4413
b50d292b
HHZ		 4414static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4415{
4416 struct mlx5e_priv *priv = vpriv;
1d447a39 4417 void *ppriv = priv->ppriv;
127ea380 4418
5e1e93c7 4419 unregister_netdev(priv->netdev);
26e59d80 4420 mlx5e_detach(mdev, vpriv);
2c3b5bee 4421 mlx5e_destroy_netdev(priv);
1d447a39 4422 kfree(ppriv);
b50d292b
HHZ		 4423}
4424
f62b8bb8
AV		 4425static void *mlx5e_get_netdev(void *vpriv)
4426{
4427 struct mlx5e_priv *priv = vpriv;
4428
4429 return priv->netdev;
4430}
4431
4432static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4433 .add = mlx5e_add,
4434 .remove = mlx5e_remove,
26e59d80
MHY		 4435 .attach = mlx5e_attach,
4436 .detach = mlx5e_detach,
f62b8bb8
AV		 4437 .event = mlx5e_async_event,
4438 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4439 .get_dev = mlx5e_get_netdev,
4440};
4441
4442void mlx5e_init(void)
4443{
665bc539 4444 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4445 mlx5_register_interface(&mlx5e_interface);
4446}
4447
4448void mlx5e_cleanup(void)
4449{
4450 mlx5_unregister_interface(&mlx5e_interface);
4451}
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