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Merge tag 'pinctrl-v4.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
9bcc8606
SD		 87 priv->params.mpwqe_log_stride_sz =
88 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
2fc4bfb7
SM		 89 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90 MLX5_MPWRQ_LOG_STRIDE_SIZE;
91 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 priv->params.mpwqe_log_stride_sz;
93 break;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
95 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96 }
97 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
98 BIT(priv->params.log_rq_size));
99
100 mlx5_core_info(priv->mdev,
101 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
102 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
103 BIT(priv->params.log_rq_size),
104 BIT(priv->params.mpwqe_log_stride_sz),
9bcc8606 105 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 106}
107
108static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
109{
86994156
RS		 110 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
111 !priv->xdp_prog ?
2fc4bfb7
SM		 112 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
113 MLX5_WQ_TYPE_LINKED_LIST;
114 mlx5e_set_rq_type_params(priv, rq_type);
115}
116
f62b8bb8
AV		 117static void mlx5e_update_carrier(struct mlx5e_priv *priv)
118{
119 struct mlx5_core_dev *mdev = priv->mdev;
120 u8 port_state;
121
122 port_state = mlx5_query_vport_state(mdev,
e7546514 123 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 124
87424ad5
SD		 125 if (port_state == VPORT_STATE_UP) {
126 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 127 netif_carrier_on(priv->netdev);
87424ad5
SD		 128 } else {
129 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 130 netif_carrier_off(priv->netdev);
87424ad5 131 }
f62b8bb8
AV		 132}
133
134static void mlx5e_update_carrier_work(struct work_struct *work)
135{
136 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
137 update_carrier_work);
138
139 mutex_lock(&priv->state_lock);
140 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
141 mlx5e_update_carrier(priv);
142 mutex_unlock(&priv->state_lock);
143}
144
3947ca18
DJ		 145static void mlx5e_tx_timeout_work(struct work_struct *work)
146{
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 tx_timeout_work);
149 int err;
150
151 rtnl_lock();
152 mutex_lock(&priv->state_lock);
153 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
154 goto unlock;
155 mlx5e_close_locked(priv->netdev);
156 err = mlx5e_open_locked(priv->netdev);
157 if (err)
158 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
159 err);
160unlock:
161 mutex_unlock(&priv->state_lock);
162 rtnl_unlock();
163}
164
9218b44d 165static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 166{
9218b44d 167 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 168 struct mlx5e_rq_stats *rq_stats;
169 struct mlx5e_sq_stats *sq_stats;
9218b44d 170 u64 tx_offload_none = 0;
f62b8bb8
AV		 171 int i, j;
172
9218b44d 173 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 174 for (i = 0; i < priv->params.num_channels; i++) {
175 rq_stats = &priv->channel[i]->rq.stats;
176
faf4478b
GP		 177 s->rx_packets += rq_stats->packets;
178 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 179 s->rx_lro_packets += rq_stats->lro_packets;
180 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 181 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 182 s->rx_csum_complete += rq_stats->csum_complete;
183 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 184 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 185 s->rx_xdp_tx += rq_stats->xdp_tx;
186 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 187 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 188 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 189 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 190 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
191 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 192 s->rx_cache_reuse += rq_stats->cache_reuse;
193 s->rx_cache_full += rq_stats->cache_full;
194 s->rx_cache_empty += rq_stats->cache_empty;
195 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 196
a4418a6c 197 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 198 sq_stats = &priv->channel[i]->sq[j].stats;
199
faf4478b
GP		 200 s->tx_packets += sq_stats->packets;
201 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 202 s->tx_tso_packets += sq_stats->tso_packets;
203 s->tx_tso_bytes += sq_stats->tso_bytes;
204 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
205 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 206 s->tx_queue_stopped += sq_stats->stopped;
207 s->tx_queue_wake += sq_stats->wake;
208 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 209 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 210 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
211 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 212 }
213 }
214
9218b44d 215 /* Update calculated offload counters */
bfe6d8d1
GP		 216 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
217 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 218
bfe6d8d1 219 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 220 priv->stats.pport.phy_counters,
221 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 222}
223
224static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
225{
226 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
227 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 228 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 229 struct mlx5_core_dev *mdev = priv->mdev;
230
f62b8bb8
AV		 231 MLX5_SET(query_vport_counter_in, in, opcode,
232 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
233 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
234 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
235
236 memset(out, 0, outlen);
9218b44d
GP		 237 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
238}
239
240static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
241{
242 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
243 struct mlx5_core_dev *mdev = priv->mdev;
244 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 245 int prio;
9218b44d
GP		 246 void *out;
247 u32 *in;
248
249 in = mlx5_vzalloc(sz);
250 if (!in)
f62b8bb8
AV		 251 goto free_out;
252
9218b44d 253 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 254
9218b44d
GP		 255 out = pstats->IEEE_802_3_counters;
256 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
257 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 258
9218b44d
GP		 259 out = pstats->RFC_2863_counters;
260 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
261 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
262
263 out = pstats->RFC_2819_counters;
264 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
265 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 266
121fcdc8
GP		 267 out = pstats->phy_counters;
268 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
269 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
270
cf678570
GP		 271 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
272 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
273 out = pstats->per_prio_counters[prio];
274 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
275 mlx5_core_access_reg(mdev, in, sz, out, sz,
276 MLX5_REG_PPCNT, 0, 0);
277 }
278
f62b8bb8 279free_out:
9218b44d
GP		 280 kvfree(in);
281}
282
283static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
284{
285 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
286
287 if (!priv->q_counter)
288 return;
289
290 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
291 &qcnt->rx_out_of_buffer);
292}
293
294void mlx5e_update_stats(struct mlx5e_priv *priv)
295{
9218b44d
GP		 296 mlx5e_update_q_counter(priv);
297 mlx5e_update_vport_counters(priv);
298 mlx5e_update_pport_counters(priv);
121fcdc8 299 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 300}
301
cb67b832 302void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 303{
304 struct delayed_work *dwork = to_delayed_work(work);
305 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
306 update_stats_work);
307 mutex_lock(&priv->state_lock);
308 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 309 priv->profile->update_stats(priv);
7bb29755
MF		 310 queue_delayed_work(priv->wq, dwork,
311 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 312 }
313 mutex_unlock(&priv->state_lock);
314}
315
daa21560
TT		 316static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
317 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 318{
daa21560
TT		 319 struct mlx5e_priv *priv = vpriv;
320
e0f46eb9 321 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 322 return;
323
f62b8bb8
AV		 324 switch (event) {
325 case MLX5_DEV_EVENT_PORT_UP:
326 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 327 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 328 break;
329
330 default:
331 break;
332 }
333}
334
f62b8bb8
AV		 335static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
336{
e0f46eb9 337 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 338}
339
340static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
341{
e0f46eb9 342 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 343 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 344}
345
facc9699
SM		 346#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
347#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
348
7e426671
TT		 349static inline int mlx5e_get_wqe_mtt_sz(void)
350{
351 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
352 * To avoid copying garbage after the mtt array, we allocate
353 * a little more.
354 */
355 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
356 MLX5_UMR_MTT_ALIGNMENT);
357}
358
359static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
360 struct mlx5e_umr_wqe *wqe, u16 ix)
361{
362 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
363 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
364 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 365 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 366 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
367 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
368
369 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
370 ds_cnt);
371 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
372 cseg->imm = rq->mkey_be;
373
374 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
375 ucseg->klm_octowords =
376 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
377 ucseg->bsf_octowords =
378 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
379 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
380
381 dseg->lkey = sq->mkey_be;
382 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
383}
384
385static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
386 struct mlx5e_channel *c)
387{
388 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
389 int mtt_sz = mlx5e_get_wqe_mtt_sz();
390 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
391 int i;
392
21c59685
SM		 393 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
394 GFP_KERNEL, cpu_to_node(c->cpu));
395 if (!rq->mpwqe.info)
7e426671
TT		 396 goto err_out;
397
398 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 399 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 400 cpu_to_node(c->cpu));
21c59685 401 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 402 goto err_free_wqe_info;
403
404 for (i = 0; i < wq_sz; i++) {
21c59685 405 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 406
21c59685 407 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 408 MLX5_UMR_ALIGN);
409 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
410 PCI_DMA_TODEVICE);
411 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
412 goto err_unmap_mtts;
413
414 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
415 }
416
417 return 0;
418
419err_unmap_mtts:
420 while (--i >= 0) {
21c59685 421 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 422
423 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
424 PCI_DMA_TODEVICE);
425 }
21c59685 426 kfree(rq->mpwqe.mtt_no_align);
7e426671 427err_free_wqe_info:
21c59685 428 kfree(rq->mpwqe.info);
7e426671
TT		 429
430err_out:
431 return -ENOMEM;
432}
433
434static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
435{
436 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
437 int mtt_sz = mlx5e_get_wqe_mtt_sz();
438 int i;
439
440 for (i = 0; i < wq_sz; i++) {
21c59685 441 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 442
443 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
444 PCI_DMA_TODEVICE);
445 }
21c59685
SM		 446 kfree(rq->mpwqe.mtt_no_align);
447 kfree(rq->mpwqe.info);
7e426671
TT		 448}
449
ec8b9981
TT		 450static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
451 u64 npages, u8 page_shift,
452 struct mlx5_core_mkey *umr_mkey)
3608ae77
TT		 453{
454 struct mlx5_core_dev *mdev = priv->mdev;
3608ae77
TT		 455 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
456 void *mkc;
457 u32 *in;
458 int err;
459
ec8b9981
TT		 460 if (!MLX5E_VALID_NUM_MTTS(npages))
461 return -EINVAL;
462
3608ae77
TT		 463 in = mlx5_vzalloc(inlen);
464 if (!in)
465 return -ENOMEM;
466
467 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
468
3608ae77
TT		 469 MLX5_SET(mkc, mkc, free, 1);
470 MLX5_SET(mkc, mkc, umr_en, 1);
471 MLX5_SET(mkc, mkc, lw, 1);
472 MLX5_SET(mkc, mkc, lr, 1);
473 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
474
475 MLX5_SET(mkc, mkc, qpn, 0xffffff);
476 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 477 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 478 MLX5_SET(mkc, mkc, translations_octword_size,
479 MLX5_MTT_OCTW(npages));
ec8b9981 480 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 481
ec8b9981 482 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 483
484 kvfree(in);
485 return err;
486}
487
ec8b9981
TT		 488static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
489{
490 struct mlx5e_priv *priv = rq->priv;
491 u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
492
493 return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
494}
495
f62b8bb8
AV		 496static int mlx5e_create_rq(struct mlx5e_channel *c,
497 struct mlx5e_rq_param *param,
498 struct mlx5e_rq *rq)
499{
500 struct mlx5e_priv *priv = c->priv;
501 struct mlx5_core_dev *mdev = priv->mdev;
502 void *rqc = param->rqc;
503 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 504 u32 byte_count;
1bfecfca
SM		 505 u32 frag_sz;
506 int npages;
f62b8bb8
AV		 507 int wq_sz;
508 int err;
509 int i;
510
311c7c71
SM		 511 param->wq.db_numa_node = cpu_to_node(c->cpu);
512
f62b8bb8
AV		 513 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
514 &rq->wq_ctrl);
515 if (err)
516 return err;
517
518 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
519
520 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 521
7e426671
TT		 522 rq->wq_type = priv->params.rq_wq_type;
523 rq->pdev = c->pdev;
524 rq->netdev = c->netdev;
525 rq->tstamp = &priv->tstamp;
526 rq->channel = c;
527 rq->ix = c->ix;
528 rq->priv = c->priv;
97bc402d
DB		 529
530 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
531 if (IS_ERR(rq->xdp_prog)) {
532 err = PTR_ERR(rq->xdp_prog);
533 rq->xdp_prog = NULL;
534 goto err_rq_wq_destroy;
535 }
7e426671 536
b5503b99
SM		 537 rq->buff.map_dir = DMA_FROM_DEVICE;
538 if (rq->xdp_prog)
539 rq->buff.map_dir = DMA_BIDIRECTIONAL;
540
461017cb
TT		 541 switch (priv->params.rq_wq_type) {
542 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 543 if (mlx5e_is_vf_vport_rep(priv)) {
544 err = -EINVAL;
545 goto err_rq_wq_destroy;
546 }
547
461017cb
TT		 548 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
549 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 550 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 551
d9d9f156
TT		 552 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
553 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 554
555 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
556 byte_count = rq->buff.wqe_sz;
ec8b9981
TT		 557
558 err = mlx5e_create_rq_umr_mkey(rq);
7e426671
TT		 559 if (err)
560 goto err_rq_wq_destroy;
ec8b9981
TT		 561 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
562
563 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
564 if (err)
565 goto err_destroy_umr_mkey;
461017cb
TT		 566 break;
567 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 568 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
569 GFP_KERNEL, cpu_to_node(c->cpu));
570 if (!rq->dma_info) {
461017cb
TT		 571 err = -ENOMEM;
572 goto err_rq_wq_destroy;
573 }
1bfecfca 574
f5f82476
OG		 575 if (mlx5e_is_vf_vport_rep(priv))
576 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
577 else
578 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
579
461017cb 580 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 581 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 582
1bfecfca 583 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 584 priv->params.lro_wqe_sz :
585 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 586 byte_count = rq->buff.wqe_sz;
587
588 /* calc the required page order */
589 frag_sz = MLX5_RX_HEADROOM +
590 byte_count /* packet data */ +
591 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
592 frag_sz = SKB_DATA_ALIGN(frag_sz);
593
594 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
595 rq->buff.page_order = order_base_2(npages);
596
461017cb 597 byte_count |= MLX5_HW_START_PADDING;
7e426671 598 rq->mkey_be = c->mkey_be;
461017cb 599 }
f62b8bb8
AV		 600
601 for (i = 0; i < wq_sz; i++) {
602 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
603
461017cb 604 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 605 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 606 }
607
cb3c7fd4
GR		 608 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
609 rq->am.mode = priv->params.rx_cq_period_mode;
610
4415a031
TT		 611 rq->page_cache.head = 0;
612 rq->page_cache.tail = 0;
613
f62b8bb8
AV		 614 return 0;
615
ec8b9981
TT		 616err_destroy_umr_mkey:
617 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
618
f62b8bb8 619err_rq_wq_destroy:
97bc402d
DB		 620 if (rq->xdp_prog)
621 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 622 mlx5_wq_destroy(&rq->wq_ctrl);
623
624 return err;
625}
626
627static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
628{
4415a031
TT		 629 int i;
630
86994156
RS		 631 if (rq->xdp_prog)
632 bpf_prog_put(rq->xdp_prog);
633
461017cb
TT		 634 switch (rq->wq_type) {
635 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 636 mlx5e_rq_free_mpwqe_info(rq);
ec8b9981 637 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
461017cb
TT		 638 break;
639 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 640 kfree(rq->dma_info);
461017cb
TT		 641 }
642
4415a031
TT		 643 for (i = rq->page_cache.head; i != rq->page_cache.tail;
644 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
645 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
646
647 mlx5e_page_release(rq, dma_info, false);
648 }
f62b8bb8
AV		 649 mlx5_wq_destroy(&rq->wq_ctrl);
650}
651
652static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
653{
50cfa25a 654 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 655 struct mlx5_core_dev *mdev = priv->mdev;
656
657 void *in;
658 void *rqc;
659 void *wq;
660 int inlen;
661 int err;
662
663 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
664 sizeof(u64) * rq->wq_ctrl.buf.npages;
665 in = mlx5_vzalloc(inlen);
666 if (!in)
667 return -ENOMEM;
668
669 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
670 wq = MLX5_ADDR_OF(rqc, rqc, wq);
671
672 memcpy(rqc, param->rqc, sizeof(param->rqc));
673
97de9f31 674 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 675 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 676 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 677 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 678 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 679 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
680
681 mlx5_fill_page_array(&rq->wq_ctrl.buf,
682 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
683
7db22ffb 684 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 685
686 kvfree(in);
687
688 return err;
689}
690
36350114
GP		 691static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
692 int next_state)
f62b8bb8
AV		 693{
694 struct mlx5e_channel *c = rq->channel;
695 struct mlx5e_priv *priv = c->priv;
696 struct mlx5_core_dev *mdev = priv->mdev;
697
698 void *in;
699 void *rqc;
700 int inlen;
701 int err;
702
703 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
704 in = mlx5_vzalloc(inlen);
705 if (!in)
706 return -ENOMEM;
707
708 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
709
710 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
711 MLX5_SET(rqc, rqc, state, next_state);
712
7db22ffb 713 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 714
715 kvfree(in);
716
717 return err;
718}
719
36350114
GP		 720static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
721{
722 struct mlx5e_channel *c = rq->channel;
723 struct mlx5e_priv *priv = c->priv;
724 struct mlx5_core_dev *mdev = priv->mdev;
725
726 void *in;
727 void *rqc;
728 int inlen;
729 int err;
730
731 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
732 in = mlx5_vzalloc(inlen);
733 if (!in)
734 return -ENOMEM;
735
736 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
737
738 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 739 MLX5_SET64(modify_rq_in, in, modify_bitmask,
740 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 741 MLX5_SET(rqc, rqc, vsd, vsd);
742 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
743
744 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
745
746 kvfree(in);
747
748 return err;
749}
750
f62b8bb8
AV		 751static void mlx5e_disable_rq(struct mlx5e_rq *rq)
752{
50cfa25a 753 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 754}
755
756static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
757{
01c196a2 758 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 759 struct mlx5e_channel *c = rq->channel;
760 struct mlx5e_priv *priv = c->priv;
761 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 762
01c196a2 763 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 764 if (wq->cur_sz >= priv->params.min_rx_wqes)
765 return 0;
766
767 msleep(20);
768 }
769
770 return -ETIMEDOUT;
771}
772
f2fde18c
SM		 773static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
774{
775 struct mlx5_wq_ll *wq = &rq->wq;
776 struct mlx5e_rx_wqe *wqe;
777 __be16 wqe_ix_be;
778 u16 wqe_ix;
779
8484f9ed
SM		 780 /* UMR WQE (if in progress) is always at wq->head */
781 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 782 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 783
f2fde18c
SM		 784 while (!mlx5_wq_ll_is_empty(wq)) {
785 wqe_ix_be = *wq->tail_next;
786 wqe_ix = be16_to_cpu(wqe_ix_be);
787 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
788 rq->dealloc_wqe(rq, wqe_ix);
789 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
790 &wqe->next.next_wqe_index);
791 }
792}
793
f62b8bb8
AV		 794static int mlx5e_open_rq(struct mlx5e_channel *c,
795 struct mlx5e_rq_param *param,
796 struct mlx5e_rq *rq)
797{
d3c9bc27
TT		 798 struct mlx5e_sq *sq = &c->icosq;
799 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 800 int err;
801
802 err = mlx5e_create_rq(c, param, rq);
803 if (err)
804 return err;
805
806 err = mlx5e_enable_rq(rq, param);
807 if (err)
808 goto err_destroy_rq;
809
c0f1147d 810 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
36350114 811 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 812 if (err)
813 goto err_disable_rq;
814
cb3c7fd4
GR		 815 if (param->am_enabled)
816 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
817
f10b7cc7
SM		 818 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
819 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 820 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 821
822 return 0;
823
824err_disable_rq:
c0f1147d 825 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8
AV		 826 mlx5e_disable_rq(rq);
827err_destroy_rq:
828 mlx5e_destroy_rq(rq);
829
830 return err;
831}
832
833static void mlx5e_close_rq(struct mlx5e_rq *rq)
834{
c0f1147d 835 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 836 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 837 cancel_work_sync(&rq->am.work);
838
f62b8bb8 839 mlx5e_disable_rq(rq);
6cd392a0 840 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 841 mlx5e_destroy_rq(rq);
842}
843
b5503b99
SM		 844static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
845{
846 kfree(sq->db.xdp.di);
847 kfree(sq->db.xdp.wqe_info);
848}
849
850static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
851{
852 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
853
854 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
855 GFP_KERNEL, numa);
856 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
857 GFP_KERNEL, numa);
858 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
859 mlx5e_free_sq_xdp_db(sq);
860 return -ENOMEM;
861 }
862
863 return 0;
864}
865
f10b7cc7 866static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 867{
f10b7cc7 868 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 869}
870
f10b7cc7
SM		 871static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
872{
873 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
874
875 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
876 GFP_KERNEL, numa);
877 if (!sq->db.ico_wqe)
878 return -ENOMEM;
879
880 return 0;
881}
882
883static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
884{
885 kfree(sq->db.txq.wqe_info);
886 kfree(sq->db.txq.dma_fifo);
887 kfree(sq->db.txq.skb);
888}
889
890static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 891{
892 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
893 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
894
f10b7cc7
SM		 895 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
896 GFP_KERNEL, numa);
897 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
898 GFP_KERNEL, numa);
899 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
900 GFP_KERNEL, numa);
901 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
902 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 903 return -ENOMEM;
904 }
905
906 sq->dma_fifo_mask = df_sz - 1;
907
908 return 0;
909}
910
f10b7cc7
SM		 911static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
912{
913 switch (sq->type) {
914 case MLX5E_SQ_TXQ:
915 mlx5e_free_sq_txq_db(sq);
916 break;
917 case MLX5E_SQ_ICO:
918 mlx5e_free_sq_ico_db(sq);
919 break;
b5503b99
SM		 920 case MLX5E_SQ_XDP:
921 mlx5e_free_sq_xdp_db(sq);
922 break;
f10b7cc7
SM		 923 }
924}
925
926static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
927{
928 switch (sq->type) {
929 case MLX5E_SQ_TXQ:
930 return mlx5e_alloc_sq_txq_db(sq, numa);
931 case MLX5E_SQ_ICO:
932 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 933 case MLX5E_SQ_XDP:
934 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 935 }
936
937 return 0;
938}
939
b5503b99
SM		 940static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
941{
942 switch (sq_type) {
943 case MLX5E_SQ_ICO:
944 return MLX5E_ICOSQ_MAX_WQEBBS;
945 case MLX5E_SQ_XDP:
946 return MLX5E_XDP_TX_WQEBBS;
947 }
948 return MLX5_SEND_WQE_MAX_WQEBBS;
949}
950
f62b8bb8
AV		 951static int mlx5e_create_sq(struct mlx5e_channel *c,
952 int tc,
953 struct mlx5e_sq_param *param,
954 struct mlx5e_sq *sq)
955{
956 struct mlx5e_priv *priv = c->priv;
957 struct mlx5_core_dev *mdev = priv->mdev;
958
959 void *sqc = param->sqc;
960 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
961 int err;
962
f10b7cc7
SM		 963 sq->type = param->type;
964 sq->pdev = c->pdev;
965 sq->tstamp = &priv->tstamp;
966 sq->mkey_be = c->mkey_be;
967 sq->channel = c;
968 sq->tc = tc;
969
fd4782c2 970 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 971 if (err)
972 return err;
973
311c7c71
SM		 974 param->wq.db_numa_node = cpu_to_node(c->cpu);
975
f62b8bb8
AV		 976 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
977 &sq->wq_ctrl);
978 if (err)
979 goto err_unmap_free_uar;
980
981 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 982 if (sq->uar.bf_map) {
983 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
984 sq->uar_map = sq->uar.bf_map;
985 } else {
986 sq->uar_map = sq->uar.map;
987 }
f62b8bb8 988 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 989 sq->max_inline = param->max_inline;
cff92d7c 990 sq->min_inline_mode =
34e4e990 991 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
cff92d7c 992 param->min_inline_mode : 0;
f62b8bb8 993
7ec0bb22
DC		 994 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
995 if (err)
f62b8bb8
AV		 996 goto err_sq_wq_destroy;
997
f10b7cc7 998 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 999 int txq_ix;
1000
1001 txq_ix = c->ix + tc * priv->params.num_channels;
1002 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1003 priv->txq_to_sq_map[txq_ix] = sq;
1004 }
f62b8bb8 1005
b5503b99 1006 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 1007 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 1008
1009 return 0;
1010
1011err_sq_wq_destroy:
1012 mlx5_wq_destroy(&sq->wq_ctrl);
1013
1014err_unmap_free_uar:
1015 mlx5_unmap_free_uar(mdev, &sq->uar);
1016
1017 return err;
1018}
1019
1020static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1021{
1022 struct mlx5e_channel *c = sq->channel;
1023 struct mlx5e_priv *priv = c->priv;
1024
1025 mlx5e_free_sq_db(sq);
1026 mlx5_wq_destroy(&sq->wq_ctrl);
1027 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1028}
1029
1030static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1031{
1032 struct mlx5e_channel *c = sq->channel;
1033 struct mlx5e_priv *priv = c->priv;
1034 struct mlx5_core_dev *mdev = priv->mdev;
1035
1036 void *in;
1037 void *sqc;
1038 void *wq;
1039 int inlen;
1040 int err;
1041
1042 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1043 sizeof(u64) * sq->wq_ctrl.buf.npages;
1044 in = mlx5_vzalloc(inlen);
1045 if (!in)
1046 return -ENOMEM;
1047
1048 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1049 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1050
1051 memcpy(sqc, param->sqc, sizeof(param->sqc));
1052
f10b7cc7
SM		 1053 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1054 0 : priv->tisn[sq->tc]);
d3c9bc27 1055 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1056 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1057 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1058 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1059
1060 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1061 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1062 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1063 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1064 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1065
1066 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1067 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1068
7db22ffb 1069 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1070
1071 kvfree(in);
1072
1073 return err;
1074}
1075
507f0c81
YP		 1076static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1077 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1078{
1079 struct mlx5e_channel *c = sq->channel;
1080 struct mlx5e_priv *priv = c->priv;
1081 struct mlx5_core_dev *mdev = priv->mdev;
1082
1083 void *in;
1084 void *sqc;
1085 int inlen;
1086 int err;
1087
1088 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1089 in = mlx5_vzalloc(inlen);
1090 if (!in)
1091 return -ENOMEM;
1092
1093 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1094
1095 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1096 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1097 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1098 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1099 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1100 }
f62b8bb8 1101
7db22ffb 1102 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1103
1104 kvfree(in);
1105
1106 return err;
1107}
1108
1109static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1110{
1111 struct mlx5e_channel *c = sq->channel;
1112 struct mlx5e_priv *priv = c->priv;
1113 struct mlx5_core_dev *mdev = priv->mdev;
1114
7db22ffb 1115 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1116 if (sq->rate_limit)
1117 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1118}
1119
1120static int mlx5e_open_sq(struct mlx5e_channel *c,
1121 int tc,
1122 struct mlx5e_sq_param *param,
1123 struct mlx5e_sq *sq)
1124{
1125 int err;
1126
1127 err = mlx5e_create_sq(c, tc, param, sq);
1128 if (err)
1129 return err;
1130
1131 err = mlx5e_enable_sq(sq, param);
1132 if (err)
1133 goto err_destroy_sq;
1134
c0f1147d 1135 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
507f0c81
YP		 1136 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1137 false, 0);
f62b8bb8
AV		 1138 if (err)
1139 goto err_disable_sq;
1140
d3c9bc27 1141 if (sq->txq) {
d3c9bc27
TT		 1142 netdev_tx_reset_queue(sq->txq);
1143 netif_tx_start_queue(sq->txq);
1144 }
f62b8bb8
AV		 1145
1146 return 0;
1147
1148err_disable_sq:
c0f1147d 1149 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
f62b8bb8
AV		 1150 mlx5e_disable_sq(sq);
1151err_destroy_sq:
1152 mlx5e_destroy_sq(sq);
1153
1154 return err;
1155}
1156
1157static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1158{
1159 __netif_tx_lock_bh(txq);
1160 netif_tx_stop_queue(txq);
1161 __netif_tx_unlock_bh(txq);
1162}
1163
1164static void mlx5e_close_sq(struct mlx5e_sq *sq)
1165{
c0f1147d 1166 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6
SM		 1167 /* prevent netif_tx_wake_queue */
1168 napi_synchronize(&sq->channel->napi);
29429f33 1169
d3c9bc27 1170 if (sq->txq) {
d3c9bc27 1171 netif_tx_disable_queue(sq->txq);
f62b8bb8 1172
6e8dd6d6 1173 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1174 if (mlx5e_sq_has_room_for(sq, 1)) {
1175 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1176 mlx5e_send_nop(sq, true);
f10b7cc7 1177 }
29429f33 1178 }
f62b8bb8 1179
f62b8bb8 1180 mlx5e_disable_sq(sq);
b5503b99 1181 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1182 mlx5e_destroy_sq(sq);
1183}
1184
1185static int mlx5e_create_cq(struct mlx5e_channel *c,
1186 struct mlx5e_cq_param *param,
1187 struct mlx5e_cq *cq)
1188{
1189 struct mlx5e_priv *priv = c->priv;
1190 struct mlx5_core_dev *mdev = priv->mdev;
1191 struct mlx5_core_cq *mcq = &cq->mcq;
1192 int eqn_not_used;
0b6e26ce 1193 unsigned int irqn;
f62b8bb8
AV		 1194 int err;
1195 u32 i;
1196
311c7c71
SM		 1197 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1198 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1199 param->eq_ix = c->ix;
1200
1201 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1202 &cq->wq_ctrl);
1203 if (err)
1204 return err;
1205
1206 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1207
1208 cq->napi = &c->napi;
1209
1210 mcq->cqe_sz = 64;
1211 mcq->set_ci_db = cq->wq_ctrl.db.db;
1212 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1213 *mcq->set_ci_db = 0;
1214 *mcq->arm_db = 0;
1215 mcq->vector = param->eq_ix;
1216 mcq->comp = mlx5e_completion_event;
1217 mcq->event = mlx5e_cq_error_event;
1218 mcq->irqn = irqn;
b50d292b 1219 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 1220
1221 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1222 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1223
1224 cqe->op_own = 0xf1;
1225 }
1226
1227 cq->channel = c;
50cfa25a 1228 cq->priv = priv;
f62b8bb8
AV		 1229
1230 return 0;
1231}
1232
1233static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1234{
1c1b5228 1235 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1236}
1237
1238static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1239{
50cfa25a 1240 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1241 struct mlx5_core_dev *mdev = priv->mdev;
1242 struct mlx5_core_cq *mcq = &cq->mcq;
1243
1244 void *in;
1245 void *cqc;
1246 int inlen;
0b6e26ce 1247 unsigned int irqn_not_used;
f62b8bb8
AV		 1248 int eqn;
1249 int err;
1250
1251 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1252 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1253 in = mlx5_vzalloc(inlen);
1254 if (!in)
1255 return -ENOMEM;
1256
1257 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1258
1259 memcpy(cqc, param->cqc, sizeof(param->cqc));
1260
1c1b5228
TT		 1261 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1262 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1263
1264 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1265
9908aa29 1266 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 1267 MLX5_SET(cqc, cqc, c_eqn, eqn);
1268 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1c1b5228 1269 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1270 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1271 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1272
1273 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1274
1275 kvfree(in);
1276
1277 if (err)
1278 return err;
1279
1280 mlx5e_cq_arm(cq);
1281
1282 return 0;
1283}
1284
1285static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1286{
50cfa25a 1287 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1288 struct mlx5_core_dev *mdev = priv->mdev;
1289
1290 mlx5_core_destroy_cq(mdev, &cq->mcq);
1291}
1292
1293static int mlx5e_open_cq(struct mlx5e_channel *c,
1294 struct mlx5e_cq_param *param,
1295 struct mlx5e_cq *cq,
9908aa29 1296 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1297{
1298 int err;
1299 struct mlx5e_priv *priv = c->priv;
1300 struct mlx5_core_dev *mdev = priv->mdev;
1301
1302 err = mlx5e_create_cq(c, param, cq);
1303 if (err)
1304 return err;
1305
1306 err = mlx5e_enable_cq(cq, param);
1307 if (err)
1308 goto err_destroy_cq;
1309
7524a5d8
GP		 1310 if (MLX5_CAP_GEN(mdev, cq_moderation))
1311 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1312 moderation.usec,
1313 moderation.pkts);
f62b8bb8
AV		 1314 return 0;
1315
1316err_destroy_cq:
1317 mlx5e_destroy_cq(cq);
1318
1319 return err;
1320}
1321
1322static void mlx5e_close_cq(struct mlx5e_cq *cq)
1323{
1324 mlx5e_disable_cq(cq);
1325 mlx5e_destroy_cq(cq);
1326}
1327
1328static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1329{
1330 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1331}
1332
1333static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1334 struct mlx5e_channel_param *cparam)
1335{
1336 struct mlx5e_priv *priv = c->priv;
1337 int err;
1338 int tc;
1339
1340 for (tc = 0; tc < c->num_tc; tc++) {
1341 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1342 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1343 if (err)
1344 goto err_close_tx_cqs;
f62b8bb8
AV		 1345 }
1346
1347 return 0;
1348
1349err_close_tx_cqs:
1350 for (tc--; tc >= 0; tc--)
1351 mlx5e_close_cq(&c->sq[tc].cq);
1352
1353 return err;
1354}
1355
1356static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1357{
1358 int tc;
1359
1360 for (tc = 0; tc < c->num_tc; tc++)
1361 mlx5e_close_cq(&c->sq[tc].cq);
1362}
1363
1364static int mlx5e_open_sqs(struct mlx5e_channel *c,
1365 struct mlx5e_channel_param *cparam)
1366{
1367 int err;
1368 int tc;
1369
1370 for (tc = 0; tc < c->num_tc; tc++) {
1371 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1372 if (err)
1373 goto err_close_sqs;
1374 }
1375
1376 return 0;
1377
1378err_close_sqs:
1379 for (tc--; tc >= 0; tc--)
1380 mlx5e_close_sq(&c->sq[tc]);
1381
1382 return err;
1383}
1384
1385static void mlx5e_close_sqs(struct mlx5e_channel *c)
1386{
1387 int tc;
1388
1389 for (tc = 0; tc < c->num_tc; tc++)
1390 mlx5e_close_sq(&c->sq[tc]);
1391}
1392
5283af89 1393static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1394{
1395 int i;
1396
6bfd390b 1397 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1398 priv->channeltc_to_txq_map[ix][i] =
1399 ix + i * priv->params.num_channels;
03289b88
SM		 1400}
1401
507f0c81
YP		 1402static int mlx5e_set_sq_maxrate(struct net_device *dev,
1403 struct mlx5e_sq *sq, u32 rate)
1404{
1405 struct mlx5e_priv *priv = netdev_priv(dev);
1406 struct mlx5_core_dev *mdev = priv->mdev;
1407 u16 rl_index = 0;
1408 int err;
1409
1410 if (rate == sq->rate_limit)
1411 /* nothing to do */
1412 return 0;
1413
1414 if (sq->rate_limit)
1415 /* remove current rl index to free space to next ones */
1416 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1417
1418 sq->rate_limit = 0;
1419
1420 if (rate) {
1421 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1422 if (err) {
1423 netdev_err(dev, "Failed configuring rate %u: %d\n",
1424 rate, err);
1425 return err;
1426 }
1427 }
1428
1429 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1430 MLX5_SQC_STATE_RDY, true, rl_index);
1431 if (err) {
1432 netdev_err(dev, "Failed configuring rate %u: %d\n",
1433 rate, err);
1434 /* remove the rate from the table */
1435 if (rate)
1436 mlx5_rl_remove_rate(mdev, rate);
1437 return err;
1438 }
1439
1440 sq->rate_limit = rate;
1441 return 0;
1442}
1443
1444static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1445{
1446 struct mlx5e_priv *priv = netdev_priv(dev);
1447 struct mlx5_core_dev *mdev = priv->mdev;
1448 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1449 int err = 0;
1450
1451 if (!mlx5_rl_is_supported(mdev)) {
1452 netdev_err(dev, "Rate limiting is not supported on this device\n");
1453 return -EINVAL;
1454 }
1455
1456 /* rate is given in Mb/sec, HW config is in Kb/sec */
1457 rate = rate << 10;
1458
1459 /* Check whether rate in valid range, 0 is always valid */
1460 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1461 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1462 return -ERANGE;
1463 }
1464
1465 mutex_lock(&priv->state_lock);
1466 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1467 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1468 if (!err)
1469 priv->tx_rates[index] = rate;
1470 mutex_unlock(&priv->state_lock);
1471
1472 return err;
1473}
1474
f62b8bb8
AV		 1475static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1476 struct mlx5e_channel_param *cparam,
1477 struct mlx5e_channel **cp)
1478{
9908aa29 1479 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1480 struct net_device *netdev = priv->netdev;
cb3c7fd4 1481 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1482 int cpu = mlx5e_get_cpu(priv, ix);
1483 struct mlx5e_channel *c;
507f0c81 1484 struct mlx5e_sq *sq;
f62b8bb8 1485 int err;
507f0c81 1486 int i;
f62b8bb8
AV		 1487
1488 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1489 if (!c)
1490 return -ENOMEM;
1491
1492 c->priv = priv;
1493 c->ix = ix;
1494 c->cpu = cpu;
1495 c->pdev = &priv->mdev->pdev->dev;
1496 c->netdev = priv->netdev;
b50d292b 1497 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1498 c->num_tc = priv->params.num_tc;
d7a0ecab 1499 c->xdp = !!priv->xdp_prog;
f62b8bb8 1500
cb3c7fd4
GR		 1501 if (priv->params.rx_am_enabled)
1502 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1503 else
1504 rx_cq_profile = priv->params.rx_cq_moderation;
1505
5283af89 1506 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1507
f62b8bb8
AV		 1508 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1509
9908aa29 1510 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1511 if (err)
1512 goto err_napi_del;
1513
d3c9bc27
TT		 1514 err = mlx5e_open_tx_cqs(c, cparam);
1515 if (err)
1516 goto err_close_icosq_cq;
1517
f62b8bb8 1518 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1519 rx_cq_profile);
f62b8bb8
AV		 1520 if (err)
1521 goto err_close_tx_cqs;
f62b8bb8 1522
d7a0ecab
SM		 1523 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1524 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1525 priv->params.tx_cq_moderation) : 0;
1526 if (err)
1527 goto err_close_rx_cq;
1528
f62b8bb8
AV		 1529 napi_enable(&c->napi);
1530
d3c9bc27 1531 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1532 if (err)
1533 goto err_disable_napi;
1534
d3c9bc27
TT		 1535 err = mlx5e_open_sqs(c, cparam);
1536 if (err)
1537 goto err_close_icosq;
1538
507f0c81
YP		 1539 for (i = 0; i < priv->params.num_tc; i++) {
1540 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1541
1542 if (priv->tx_rates[txq_ix]) {
1543 sq = priv->txq_to_sq_map[txq_ix];
1544 mlx5e_set_sq_maxrate(priv->netdev, sq,
1545 priv->tx_rates[txq_ix]);
1546 }
1547 }
1548
d7a0ecab
SM		 1549 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1550 if (err)
1551 goto err_close_sqs;
b5503b99 1552
f62b8bb8
AV		 1553 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1554 if (err)
b5503b99 1555 goto err_close_xdp_sq;
f62b8bb8
AV		 1556
1557 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1558 *cp = c;
1559
1560 return 0;
b5503b99 1561err_close_xdp_sq:
d7a0ecab 1562 if (c->xdp)
87dc0255 1563 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1564
1565err_close_sqs:
1566 mlx5e_close_sqs(c);
1567
d3c9bc27
TT		 1568err_close_icosq:
1569 mlx5e_close_sq(&c->icosq);
1570
f62b8bb8
AV		 1571err_disable_napi:
1572 napi_disable(&c->napi);
d7a0ecab
SM		 1573 if (c->xdp)
1574 mlx5e_close_cq(&c->xdp_sq.cq);
1575
1576err_close_rx_cq:
f62b8bb8
AV		 1577 mlx5e_close_cq(&c->rq.cq);
1578
1579err_close_tx_cqs:
1580 mlx5e_close_tx_cqs(c);
1581
d3c9bc27
TT		 1582err_close_icosq_cq:
1583 mlx5e_close_cq(&c->icosq.cq);
1584
f62b8bb8
AV		 1585err_napi_del:
1586 netif_napi_del(&c->napi);
1587 kfree(c);
1588
1589 return err;
1590}
1591
1592static void mlx5e_close_channel(struct mlx5e_channel *c)
1593{
1594 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1595 if (c->xdp)
1596 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1597 mlx5e_close_sqs(c);
d3c9bc27 1598 mlx5e_close_sq(&c->icosq);
f62b8bb8 1599 napi_disable(&c->napi);
b5503b99
SM		 1600 if (c->xdp)
1601 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1602 mlx5e_close_cq(&c->rq.cq);
1603 mlx5e_close_tx_cqs(c);
d3c9bc27 1604 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1605 netif_napi_del(&c->napi);
7ae92ae5 1606
f62b8bb8
AV		 1607 kfree(c);
1608}
1609
1610static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1611 struct mlx5e_rq_param *param)
1612{
1613 void *rqc = param->rqc;
1614 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1615
461017cb
TT		 1616 switch (priv->params.rq_wq_type) {
1617 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1618 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1619 priv->params.mpwqe_log_num_strides - 9);
461017cb 1620 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1621 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1622 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1623 break;
1624 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1625 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1626 }
1627
f62b8bb8
AV		 1628 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1629 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1630 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1631 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1632 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1633
311c7c71 1634 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1635 param->wq.linear = 1;
cb3c7fd4
GR		 1636
1637 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1638}
1639
556dd1b9
TT		 1640static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1641{
1642 void *rqc = param->rqc;
1643 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1644
1645 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1646 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1647}
1648
d3c9bc27
TT		 1649static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1650 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1651{
1652 void *sqc = param->sqc;
1653 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1654
f62b8bb8 1655 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1656 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1657
311c7c71 1658 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1659}
1660
1661static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1662 struct mlx5e_sq_param *param)
1663{
1664 void *sqc = param->sqc;
1665 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1666
1667 mlx5e_build_sq_param_common(priv, param);
1668 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1669
58d52291 1670 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1671 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1672 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1673}
1674
1675static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1676 struct mlx5e_cq_param *param)
1677{
1678 void *cqc = param->cqc;
1679
b50d292b 1680 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1681}
1682
1683static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1684 struct mlx5e_cq_param *param)
1685{
1686 void *cqc = param->cqc;
461017cb 1687 u8 log_cq_size;
f62b8bb8 1688
461017cb
TT		 1689 switch (priv->params.rq_wq_type) {
1690 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1691 log_cq_size = priv->params.log_rq_size +
d9d9f156 1692 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1693 break;
1694 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1695 log_cq_size = priv->params.log_rq_size;
1696 }
1697
1698 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
9bcc8606 1699 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1700 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1701 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1702 }
f62b8bb8
AV		 1703
1704 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1705
1706 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1707}
1708
1709static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1710 struct mlx5e_cq_param *param)
1711{
1712 void *cqc = param->cqc;
1713
d3c9bc27 1714 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1715
1716 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1717
1718 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1719}
1720
d3c9bc27
TT		 1721static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1722 struct mlx5e_cq_param *param,
1723 u8 log_wq_size)
1724{
1725 void *cqc = param->cqc;
1726
1727 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1728
1729 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1730
1731 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1732}
1733
1734static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1735 struct mlx5e_sq_param *param,
1736 u8 log_wq_size)
1737{
1738 void *sqc = param->sqc;
1739 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1740
1741 mlx5e_build_sq_param_common(priv, param);
1742
1743 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1744 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1745
f10b7cc7 1746 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1747}
1748
b5503b99
SM		 1749static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1750 struct mlx5e_sq_param *param)
1751{
1752 void *sqc = param->sqc;
1753 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1754
1755 mlx5e_build_sq_param_common(priv, param);
1756 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1757
1758 param->max_inline = priv->params.tx_max_inline;
1759 /* FOR XDP SQs will support only L2 inline mode */
1760 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1761 param->type = MLX5E_SQ_XDP;
1762}
1763
6b87663f 1764static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1765{
bc77b240 1766 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1767
f62b8bb8
AV		 1768 mlx5e_build_rq_param(priv, &cparam->rq);
1769 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1770 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1771 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1772 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1773 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1774 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1775}
1776
1777static int mlx5e_open_channels(struct mlx5e_priv *priv)
1778{
6b87663f 1779 struct mlx5e_channel_param *cparam;
a4418a6c 1780 int nch = priv->params.num_channels;
03289b88 1781 int err = -ENOMEM;
f62b8bb8
AV		 1782 int i;
1783 int j;
1784
a4418a6c
AS		 1785 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1786 GFP_KERNEL);
03289b88 1787
a4418a6c 1788 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1789 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1790
6b87663f
AB		 1791 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1792
1793 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1794 goto err_free_txq_to_sq_map;
f62b8bb8 1795
6b87663f
AB		 1796 mlx5e_build_channel_param(priv, cparam);
1797
a4418a6c 1798 for (i = 0; i < nch; i++) {
6b87663f 1799 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1800 if (err)
1801 goto err_close_channels;
1802 }
1803
a4418a6c 1804 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1805 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1806 if (err)
1807 goto err_close_channels;
1808 }
1809
c3b7c5c9
MHY		 1810 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1811 * polling for inactive tx queues.
1812 */
1813 netif_tx_start_all_queues(priv->netdev);
1814
6b87663f 1815 kfree(cparam);
f62b8bb8
AV		 1816 return 0;
1817
1818err_close_channels:
1819 for (i--; i >= 0; i--)
1820 mlx5e_close_channel(priv->channel[i]);
1821
03289b88
SM		 1822err_free_txq_to_sq_map:
1823 kfree(priv->txq_to_sq_map);
f62b8bb8 1824 kfree(priv->channel);
6b87663f 1825 kfree(cparam);
f62b8bb8
AV		 1826
1827 return err;
1828}
1829
1830static void mlx5e_close_channels(struct mlx5e_priv *priv)
1831{
1832 int i;
1833
c3b7c5c9
MHY		 1834 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1835 * polling for inactive tx queues.
1836 */
1837 netif_tx_stop_all_queues(priv->netdev);
1838 netif_tx_disable(priv->netdev);
1839
f62b8bb8
AV		 1840 for (i = 0; i < priv->params.num_channels; i++)
1841 mlx5e_close_channel(priv->channel[i]);
1842
03289b88 1843 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1844 kfree(priv->channel);
1845}
1846
2be6967c
SM		 1847static int mlx5e_rx_hash_fn(int hfunc)
1848{
1849 return (hfunc == ETH_RSS_HASH_TOP) ?
1850 MLX5_RX_HASH_FN_TOEPLITZ :
1851 MLX5_RX_HASH_FN_INVERTED_XOR8;
1852}
1853
1854static int mlx5e_bits_invert(unsigned long a, int size)
1855{
1856 int inv = 0;
1857 int i;
1858
1859 for (i = 0; i < size; i++)
1860 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1861
1862 return inv;
1863}
1864
936896e9
AS		 1865static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1866{
1867 int i;
1868
1869 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1870 int ix = i;
1da36696 1871 u32 rqn;
936896e9
AS		 1872
1873 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1874 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1875
2d75b2bc 1876 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1877 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1878 priv->channel[ix]->rq.rqn :
1879 priv->drop_rq.rqn;
1880 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1881 }
1882}
1883
1da36696
TT		 1884static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1885 int ix)
4cbeaff5 1886{
1da36696
TT		 1887 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1888 priv->channel[ix]->rq.rqn :
1889 priv->drop_rq.rqn;
4cbeaff5 1890
1da36696 1891 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1892}
1893
398f3351
HHZ		 1894static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1895 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1896{
1897 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1898 void *rqtc;
1899 int inlen;
1900 int err;
1da36696 1901 u32 *in;
f62b8bb8 1902
f62b8bb8
AV		 1903 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1904 in = mlx5_vzalloc(inlen);
1905 if (!in)
1906 return -ENOMEM;
1907
1908 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1909
1910 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1911 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1912
1da36696
TT		 1913 if (sz > 1) /* RSS */
1914 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1915 else
1916 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1917
398f3351
HHZ		 1918 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1919 if (!err)
1920 rqt->enabled = true;
f62b8bb8
AV		 1921
1922 kvfree(in);
1da36696
TT		 1923 return err;
1924}
1925
cb67b832 1926void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1927{
398f3351
HHZ		 1928 rqt->enabled = false;
1929 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1930}
1931
6bfd390b
HHZ		 1932static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1933{
1934 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1935
1936 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1937}
1938
cb67b832 1939int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1940{
398f3351 1941 struct mlx5e_rqt *rqt;
1da36696
TT		 1942 int err;
1943 int ix;
1944
6bfd390b 1945 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1946 rqt = &priv->direct_tir[ix].rqt;
1947 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1948 if (err)
1949 goto err_destroy_rqts;
1950 }
1951
1952 return 0;
1953
1954err_destroy_rqts:
1955 for (ix--; ix >= 0; ix--)
398f3351 1956 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1957
f62b8bb8
AV		 1958 return err;
1959}
1960
1da36696 1961int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1962{
1963 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1964 void *rqtc;
1965 int inlen;
1da36696 1966 u32 *in;
5c50368f
AS		 1967 int err;
1968
5c50368f
AS		 1969 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1970 in = mlx5_vzalloc(inlen);
1971 if (!in)
1972 return -ENOMEM;
1973
1974 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1975
1976 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1977 if (sz > 1) /* RSS */
1978 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1979 else
1980 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1981
1982 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1983
1da36696 1984 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1985
1986 kvfree(in);
1987
1988 return err;
1989}
1990
40ab6a6e
AS		 1991static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1992{
1da36696
TT		 1993 u32 rqtn;
1994 int ix;
1995
398f3351
HHZ		 1996 if (priv->indir_rqt.enabled) {
1997 rqtn = priv->indir_rqt.rqtn;
1998 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1999 }
2000
1da36696 2001 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 2002 if (!priv->direct_tir[ix].rqt.enabled)
2003 continue;
2004 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 2005 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2006 }
40ab6a6e
AS		 2007}
2008
5c50368f
AS		 2009static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2010{
2011 if (!priv->params.lro_en)
2012 return;
2013
2014#define ROUGH_MAX_L2_L3_HDR_SZ 256
2015
2016 MLX5_SET(tirc, tirc, lro_enable_mask,
2017 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2018 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2019 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2020 (priv->params.lro_wqe_sz -
2021 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 2022 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 2023}
2024
bdfc028d
TT		 2025void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2026{
2027 MLX5_SET(tirc, tirc, rx_hash_fn,
2028 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2029 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2030 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2031 rx_hash_toeplitz_key);
2032 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2033 rx_hash_toeplitz_key);
2034
2035 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2036 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2037 }
2038}
2039
ab0394fe 2040static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2041{
2042 struct mlx5_core_dev *mdev = priv->mdev;
2043
2044 void *in;
2045 void *tirc;
2046 int inlen;
2047 int err;
ab0394fe 2048 int tt;
1da36696 2049 int ix;
5c50368f
AS		 2050
2051 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2052 in = mlx5_vzalloc(inlen);
2053 if (!in)
2054 return -ENOMEM;
2055
2056 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2057 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2058
2059 mlx5e_build_tir_ctx_lro(tirc, priv);
2060
1da36696 2061 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2062 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2063 inlen);
ab0394fe 2064 if (err)
1da36696 2065 goto free_in;
ab0394fe 2066 }
5c50368f 2067
6bfd390b 2068 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2069 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2070 in, inlen);
2071 if (err)
2072 goto free_in;
2073 }
2074
2075free_in:
5c50368f
AS		 2076 kvfree(in);
2077
2078 return err;
2079}
2080
cd255eff 2081static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2082{
40ab6a6e 2083 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2084 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2085 int err;
2086
cd255eff 2087 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2088 if (err)
2089 return err;
2090
cd255eff
SM		 2091 /* Update vport context MTU */
2092 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2093 return 0;
2094}
40ab6a6e 2095
cd255eff
SM		 2096static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2097{
2098 struct mlx5_core_dev *mdev = priv->mdev;
2099 u16 hw_mtu = 0;
2100 int err;
40ab6a6e 2101
cd255eff
SM		 2102 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2103 if (err || !hw_mtu) /* fallback to port oper mtu */
2104 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2105
2106 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2107}
2108
2109static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2110{
2111 struct mlx5e_priv *priv = netdev_priv(netdev);
2112 u16 mtu;
2113 int err;
2114
2115 err = mlx5e_set_mtu(priv, netdev->mtu);
2116 if (err)
2117 return err;
40ab6a6e 2118
cd255eff
SM		 2119 mlx5e_query_mtu(priv, &mtu);
2120 if (mtu != netdev->mtu)
2121 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2122 __func__, mtu, netdev->mtu);
40ab6a6e 2123
cd255eff 2124 netdev->mtu = mtu;
40ab6a6e
AS		 2125 return 0;
2126}
2127
08fb1dac
SM		 2128static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2129{
2130 struct mlx5e_priv *priv = netdev_priv(netdev);
2131 int nch = priv->params.num_channels;
2132 int ntc = priv->params.num_tc;
2133 int tc;
2134
2135 netdev_reset_tc(netdev);
2136
2137 if (ntc == 1)
2138 return;
2139
2140 netdev_set_num_tc(netdev, ntc);
2141
7ccdd084
RS		 2142 /* Map netdev TCs to offset 0
2143 * We have our own UP to TXQ mapping for QoS
2144 */
08fb1dac 2145 for (tc = 0; tc < ntc; tc++)
7ccdd084 2146 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2147}
2148
40ab6a6e
AS		 2149int mlx5e_open_locked(struct net_device *netdev)
2150{
2151 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2152 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2153 int num_txqs;
2154 int err;
2155
2156 set_bit(MLX5E_STATE_OPENED, &priv->state);
2157
08fb1dac
SM		 2158 mlx5e_netdev_set_tcs(netdev);
2159
40ab6a6e
AS		 2160 num_txqs = priv->params.num_channels * priv->params.num_tc;
2161 netif_set_real_num_tx_queues(netdev, num_txqs);
2162 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2163
40ab6a6e
AS		 2164 err = mlx5e_open_channels(priv);
2165 if (err) {
2166 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2167 __func__, err);
343b29f3 2168 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2169 }
2170
0952da79 2171 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
66189961
TT		 2172 if (err) {
2173 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2174 __func__, err);
2175 goto err_close_channels;
2176 }
2177
40ab6a6e 2178 mlx5e_redirect_rqts(priv);
ce89ef36 2179 mlx5e_update_carrier(priv);
ef9814de 2180 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2181#ifdef CONFIG_RFS_ACCEL
2182 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2183#endif
cb67b832
HHZ		 2184 if (priv->profile->update_stats)
2185 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2186
cb67b832
HHZ		 2187 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2188 err = mlx5e_add_sqs_fwd_rules(priv);
2189 if (err)
2190 goto err_close_channels;
2191 }
9b37b07f 2192 return 0;
343b29f3 2193
66189961
TT		 2194err_close_channels:
2195 mlx5e_close_channels(priv);
343b29f3
AS		 2196err_clear_state_opened_flag:
2197 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2198 return err;
40ab6a6e
AS		 2199}
2200
cb67b832 2201int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2202{
2203 struct mlx5e_priv *priv = netdev_priv(netdev);
2204 int err;
2205
2206 mutex_lock(&priv->state_lock);
2207 err = mlx5e_open_locked(netdev);
2208 mutex_unlock(&priv->state_lock);
2209
2210 return err;
2211}
2212
2213int mlx5e_close_locked(struct net_device *netdev)
2214{
2215 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2216 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2217
a1985740
AS		 2218 /* May already be CLOSED in case a previous configuration operation
2219 * (e.g RX/TX queue size change) that involves close&open failed.
2220 */
2221 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2222 return 0;
2223
40ab6a6e
AS		 2224 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2225
cb67b832
HHZ		 2226 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2227 mlx5e_remove_sqs_fwd_rules(priv);
2228
ef9814de 2229 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2230 netif_carrier_off(priv->netdev);
ce89ef36 2231 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2232 mlx5e_close_channels(priv);
2233
2234 return 0;
2235}
2236
cb67b832 2237int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2238{
2239 struct mlx5e_priv *priv = netdev_priv(netdev);
2240 int err;
2241
26e59d80
MHY		 2242 if (!netif_device_present(netdev))
2243 return -ENODEV;
2244
40ab6a6e
AS		 2245 mutex_lock(&priv->state_lock);
2246 err = mlx5e_close_locked(netdev);
2247 mutex_unlock(&priv->state_lock);
2248
2249 return err;
2250}
2251
2252static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2253 struct mlx5e_rq *rq,
2254 struct mlx5e_rq_param *param)
2255{
2256 struct mlx5_core_dev *mdev = priv->mdev;
2257 void *rqc = param->rqc;
2258 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2259 int err;
2260
2261 param->wq.db_numa_node = param->wq.buf_numa_node;
2262
2263 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2264 &rq->wq_ctrl);
2265 if (err)
2266 return err;
2267
2268 rq->priv = priv;
2269
2270 return 0;
2271}
2272
2273static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2274 struct mlx5e_cq *cq,
2275 struct mlx5e_cq_param *param)
2276{
2277 struct mlx5_core_dev *mdev = priv->mdev;
2278 struct mlx5_core_cq *mcq = &cq->mcq;
2279 int eqn_not_used;
0b6e26ce 2280 unsigned int irqn;
40ab6a6e
AS		 2281 int err;
2282
2283 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2284 &cq->wq_ctrl);
2285 if (err)
2286 return err;
2287
2288 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2289
2290 mcq->cqe_sz = 64;
2291 mcq->set_ci_db = cq->wq_ctrl.db.db;
2292 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2293 *mcq->set_ci_db = 0;
2294 *mcq->arm_db = 0;
2295 mcq->vector = param->eq_ix;
2296 mcq->comp = mlx5e_completion_event;
2297 mcq->event = mlx5e_cq_error_event;
2298 mcq->irqn = irqn;
b50d292b 2299 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 2300
2301 cq->priv = priv;
2302
2303 return 0;
2304}
2305
2306static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2307{
2308 struct mlx5e_cq_param cq_param;
2309 struct mlx5e_rq_param rq_param;
2310 struct mlx5e_rq *rq = &priv->drop_rq;
2311 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2312 int err;
2313
2314 memset(&cq_param, 0, sizeof(cq_param));
2315 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2316 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2317
2318 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2319 if (err)
2320 return err;
2321
2322 err = mlx5e_enable_cq(cq, &cq_param);
2323 if (err)
2324 goto err_destroy_cq;
2325
2326 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2327 if (err)
2328 goto err_disable_cq;
2329
2330 err = mlx5e_enable_rq(rq, &rq_param);
2331 if (err)
2332 goto err_destroy_rq;
2333
2334 return 0;
2335
2336err_destroy_rq:
2337 mlx5e_destroy_rq(&priv->drop_rq);
2338
2339err_disable_cq:
2340 mlx5e_disable_cq(&priv->drop_rq.cq);
2341
2342err_destroy_cq:
2343 mlx5e_destroy_cq(&priv->drop_rq.cq);
2344
2345 return err;
2346}
2347
2348static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2349{
2350 mlx5e_disable_rq(&priv->drop_rq);
2351 mlx5e_destroy_rq(&priv->drop_rq);
2352 mlx5e_disable_cq(&priv->drop_rq.cq);
2353 mlx5e_destroy_cq(&priv->drop_rq.cq);
2354}
2355
2356static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2357{
2358 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2359 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2360 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2361
08fb1dac 2362 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2363 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2364
2365 if (mlx5_lag_is_lacp_owner(mdev))
2366 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2367
40ab6a6e
AS		 2368 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2369}
2370
2371static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2372{
2373 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2374}
2375
cb67b832 2376int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2377{
2378 int err;
2379 int tc;
2380
6bfd390b 2381 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2382 err = mlx5e_create_tis(priv, tc);
2383 if (err)
2384 goto err_close_tises;
2385 }
2386
2387 return 0;
2388
2389err_close_tises:
2390 for (tc--; tc >= 0; tc--)
2391 mlx5e_destroy_tis(priv, tc);
2392
2393 return err;
2394}
2395
cb67b832 2396void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2397{
2398 int tc;
2399
6bfd390b 2400 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2401 mlx5e_destroy_tis(priv, tc);
2402}
2403
1da36696
TT		 2404static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2405 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2406{
2407 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2408
b50d292b 2409 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2410
5a6f8aef
AS		 2411#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2412 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2413
5a6f8aef
AS		 2414#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2415 MLX5_HASH_FIELD_SEL_DST_IP |\
2416 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2417 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2418
a741749f
AS		 2419#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2420 MLX5_HASH_FIELD_SEL_DST_IP |\
2421 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2422
5c50368f 2423 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2424
4cbeaff5 2425 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2426 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2427 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2428
2429 switch (tt) {
2430 case MLX5E_TT_IPV4_TCP:
2431 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2432 MLX5_L3_PROT_TYPE_IPV4);
2433 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2434 MLX5_L4_PROT_TYPE_TCP);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2436 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2437 break;
2438
2439 case MLX5E_TT_IPV6_TCP:
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV6);
2442 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2443 MLX5_L4_PROT_TYPE_TCP);
2444 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2445 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2446 break;
2447
2448 case MLX5E_TT_IPV4_UDP:
2449 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2450 MLX5_L3_PROT_TYPE_IPV4);
2451 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2452 MLX5_L4_PROT_TYPE_UDP);
2453 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2454 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2455 break;
2456
2457 case MLX5E_TT_IPV6_UDP:
2458 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2459 MLX5_L3_PROT_TYPE_IPV6);
2460 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2461 MLX5_L4_PROT_TYPE_UDP);
2462 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2463 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2464 break;
2465
a741749f
AS		 2466 case MLX5E_TT_IPV4_IPSEC_AH:
2467 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2468 MLX5_L3_PROT_TYPE_IPV4);
2469 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2470 MLX5_HASH_IP_IPSEC_SPI);
2471 break;
2472
2473 case MLX5E_TT_IPV6_IPSEC_AH:
2474 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2475 MLX5_L3_PROT_TYPE_IPV6);
2476 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2477 MLX5_HASH_IP_IPSEC_SPI);
2478 break;
2479
2480 case MLX5E_TT_IPV4_IPSEC_ESP:
2481 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2482 MLX5_L3_PROT_TYPE_IPV4);
2483 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2484 MLX5_HASH_IP_IPSEC_SPI);
2485 break;
2486
2487 case MLX5E_TT_IPV6_IPSEC_ESP:
2488 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2489 MLX5_L3_PROT_TYPE_IPV6);
2490 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2491 MLX5_HASH_IP_IPSEC_SPI);
2492 break;
2493
f62b8bb8
AV		 2494 case MLX5E_TT_IPV4:
2495 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2496 MLX5_L3_PROT_TYPE_IPV4);
2497 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2498 MLX5_HASH_IP);
2499 break;
2500
2501 case MLX5E_TT_IPV6:
2502 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503 MLX5_L3_PROT_TYPE_IPV6);
2504 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2505 MLX5_HASH_IP);
2506 break;
1da36696
TT		 2507 default:
2508 WARN_ONCE(true,
2509 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2510 }
2511}
2512
1da36696
TT		 2513static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2514 u32 rqtn)
f62b8bb8 2515{
b50d292b 2516 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2517
2518 mlx5e_build_tir_ctx_lro(tirc, priv);
2519
2520 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2521 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2522 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2523}
2524
6bfd390b 2525static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2526{
724b2aa1 2527 struct mlx5e_tir *tir;
f62b8bb8
AV		 2528 void *tirc;
2529 int inlen;
2530 int err;
1da36696 2531 u32 *in;
1da36696 2532 int tt;
f62b8bb8
AV		 2533
2534 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2535 in = mlx5_vzalloc(inlen);
2536 if (!in)
2537 return -ENOMEM;
2538
1da36696
TT		 2539 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2540 memset(in, 0, inlen);
724b2aa1 2541 tir = &priv->indir_tir[tt];
1da36696
TT		 2542 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2543 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2544 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2545 if (err)
40ab6a6e 2546 goto err_destroy_tirs;
f62b8bb8
AV		 2547 }
2548
6bfd390b
HHZ		 2549 kvfree(in);
2550
2551 return 0;
2552
2553err_destroy_tirs:
2554 for (tt--; tt >= 0; tt--)
2555 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2556
2557 kvfree(in);
2558
2559 return err;
2560}
2561
cb67b832 2562int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2563{
2564 int nch = priv->profile->max_nch(priv->mdev);
2565 struct mlx5e_tir *tir;
2566 void *tirc;
2567 int inlen;
2568 int err;
2569 u32 *in;
2570 int ix;
2571
2572 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2573 in = mlx5_vzalloc(inlen);
2574 if (!in)
2575 return -ENOMEM;
2576
1da36696
TT		 2577 for (ix = 0; ix < nch; ix++) {
2578 memset(in, 0, inlen);
724b2aa1 2579 tir = &priv->direct_tir[ix];
1da36696
TT		 2580 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2581 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2582 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2583 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2584 if (err)
2585 goto err_destroy_ch_tirs;
2586 }
2587
2588 kvfree(in);
2589
f62b8bb8
AV		 2590 return 0;
2591
1da36696
TT		 2592err_destroy_ch_tirs:
2593 for (ix--; ix >= 0; ix--)
724b2aa1 2594 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2595
1da36696 2596 kvfree(in);
f62b8bb8
AV		 2597
2598 return err;
2599}
2600
6bfd390b 2601static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2602{
2603 int i;
2604
1da36696 2605 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2606 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2607}
2608
cb67b832 2609void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2610{
2611 int nch = priv->profile->max_nch(priv->mdev);
2612 int i;
2613
2614 for (i = 0; i < nch; i++)
2615 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2616}
2617
36350114
GP		 2618int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2619{
2620 int err = 0;
2621 int i;
2622
2623 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2624 return 0;
2625
2626 for (i = 0; i < priv->params.num_channels; i++) {
2627 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2628 if (err)
2629 return err;
2630 }
2631
2632 return 0;
2633}
2634
08fb1dac
SM		 2635static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2636{
2637 struct mlx5e_priv *priv = netdev_priv(netdev);
2638 bool was_opened;
2639 int err = 0;
2640
2641 if (tc && tc != MLX5E_MAX_NUM_TC)
2642 return -EINVAL;
2643
2644 mutex_lock(&priv->state_lock);
2645
2646 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2647 if (was_opened)
2648 mlx5e_close_locked(priv->netdev);
2649
2650 priv->params.num_tc = tc ? tc : 1;
2651
2652 if (was_opened)
2653 err = mlx5e_open_locked(priv->netdev);
2654
2655 mutex_unlock(&priv->state_lock);
2656
2657 return err;
2658}
2659
2660static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2661 __be16 proto, struct tc_to_netdev *tc)
2662{
e8f887ac
AV		 2663 struct mlx5e_priv *priv = netdev_priv(dev);
2664
2665 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2666 goto mqprio;
2667
2668 switch (tc->type) {
e3a2b7ed
AV		 2669 case TC_SETUP_CLSFLOWER:
2670 switch (tc->cls_flower->command) {
2671 case TC_CLSFLOWER_REPLACE:
2672 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2673 case TC_CLSFLOWER_DESTROY:
2674 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2675 case TC_CLSFLOWER_STATS:
2676 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2677 }
e8f887ac
AV		 2678 default:
2679 return -EOPNOTSUPP;
2680 }
2681
2682mqprio:
67ba422e 2683 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2684 return -EINVAL;
2685
2686 return mlx5e_setup_tc(dev, tc->tc);
2687}
2688
370bad0f 2689static struct rtnl_link_stats64 *
f62b8bb8
AV		 2690mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2691{
2692 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2693 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2694 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2695 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2696
370bad0f
OG		 2697 if (mlx5e_is_uplink_rep(priv)) {
2698 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2699 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2700 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2701 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2702 } else {
2703 stats->rx_packets = sstats->rx_packets;
2704 stats->rx_bytes = sstats->rx_bytes;
2705 stats->tx_packets = sstats->tx_packets;
2706 stats->tx_bytes = sstats->tx_bytes;
2707 stats->tx_dropped = sstats->tx_queue_dropped;
2708 }
269e6b3a
GP		 2709
2710 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2711
2712 stats->rx_length_errors =
9218b44d
GP		 2713 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2714 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2715 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2716 stats->rx_crc_errors =
9218b44d
GP		 2717 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2718 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2719 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2720 stats->tx_carrier_errors =
9218b44d 2721 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2722 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2723 stats->rx_frame_errors;
2724 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2725
2726 /* vport multicast also counts packets that are dropped due to steering
2727 * or rx out of buffer
2728 */
9218b44d
GP		 2729 stats->multicast =
2730 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2731
2732 return stats;
2733}
2734
2735static void mlx5e_set_rx_mode(struct net_device *dev)
2736{
2737 struct mlx5e_priv *priv = netdev_priv(dev);
2738
7bb29755 2739 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2740}
2741
2742static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2743{
2744 struct mlx5e_priv *priv = netdev_priv(netdev);
2745 struct sockaddr *saddr = addr;
2746
2747 if (!is_valid_ether_addr(saddr->sa_data))
2748 return -EADDRNOTAVAIL;
2749
2750 netif_addr_lock_bh(netdev);
2751 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2752 netif_addr_unlock_bh(netdev);
2753
7bb29755 2754 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2755
2756 return 0;
2757}
2758
0e405443
GP		 2759#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2760 do { \
2761 if (enable) \
2762 netdev->features |= feature; \
2763 else \
2764 netdev->features &= ~feature; \
2765 } while (0)
2766
2767typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2768
2769static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2770{
2771 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2772 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2773 int err;
f62b8bb8
AV		 2774
2775 mutex_lock(&priv->state_lock);
f62b8bb8 2776
0e405443
GP		 2777 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2778 mlx5e_close_locked(priv->netdev);
98e81b0a 2779
0e405443
GP		 2780 priv->params.lro_en = enable;
2781 err = mlx5e_modify_tirs_lro(priv);
2782 if (err) {
2783 netdev_err(netdev, "lro modify failed, %d\n", err);
2784 priv->params.lro_en = !enable;
98e81b0a 2785 }
f62b8bb8 2786
0e405443
GP		 2787 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2788 mlx5e_open_locked(priv->netdev);
2789
9b37b07f
AS		 2790 mutex_unlock(&priv->state_lock);
2791
0e405443
GP		 2792 return err;
2793}
2794
2795static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2796{
2797 struct mlx5e_priv *priv = netdev_priv(netdev);
2798
2799 if (enable)
2800 mlx5e_enable_vlan_filter(priv);
2801 else
2802 mlx5e_disable_vlan_filter(priv);
2803
2804 return 0;
2805}
2806
2807static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2808{
2809 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2810
0e405443 2811 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2812 netdev_err(netdev,
2813 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2814 return -EINVAL;
2815 }
2816
0e405443
GP		 2817 return 0;
2818}
2819
94cb1ebb
EBE		 2820static int set_feature_rx_all(struct net_device *netdev, bool enable)
2821{
2822 struct mlx5e_priv *priv = netdev_priv(netdev);
2823 struct mlx5_core_dev *mdev = priv->mdev;
2824
2825 return mlx5_set_port_fcs(mdev, !enable);
2826}
2827
36350114
GP		 2828static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2829{
2830 struct mlx5e_priv *priv = netdev_priv(netdev);
2831 int err;
2832
2833 mutex_lock(&priv->state_lock);
2834
2835 priv->params.vlan_strip_disable = !enable;
2836 err = mlx5e_modify_rqs_vsd(priv, !enable);
2837 if (err)
2838 priv->params.vlan_strip_disable = enable;
2839
2840 mutex_unlock(&priv->state_lock);
2841
2842 return err;
2843}
2844
45bf454a
MG		 2845#ifdef CONFIG_RFS_ACCEL
2846static int set_feature_arfs(struct net_device *netdev, bool enable)
2847{
2848 struct mlx5e_priv *priv = netdev_priv(netdev);
2849 int err;
2850
2851 if (enable)
2852 err = mlx5e_arfs_enable(priv);
2853 else
2854 err = mlx5e_arfs_disable(priv);
2855
2856 return err;
2857}
2858#endif
2859
0e405443
GP		 2860static int mlx5e_handle_feature(struct net_device *netdev,
2861 netdev_features_t wanted_features,
2862 netdev_features_t feature,
2863 mlx5e_feature_handler feature_handler)
2864{
2865 netdev_features_t changes = wanted_features ^ netdev->features;
2866 bool enable = !!(wanted_features & feature);
2867 int err;
2868
2869 if (!(changes & feature))
2870 return 0;
2871
2872 err = feature_handler(netdev, enable);
2873 if (err) {
2874 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2875 enable ? "Enable" : "Disable", feature, err);
2876 return err;
2877 }
2878
2879 MLX5E_SET_FEATURE(netdev, feature, enable);
2880 return 0;
2881}
2882
2883static int mlx5e_set_features(struct net_device *netdev,
2884 netdev_features_t features)
2885{
2886 int err;
2887
2888 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2889 set_feature_lro);
2890 err |= mlx5e_handle_feature(netdev, features,
2891 NETIF_F_HW_VLAN_CTAG_FILTER,
2892 set_feature_vlan_filter);
2893 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2894 set_feature_tc_num_filters);
94cb1ebb
EBE		 2895 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2896 set_feature_rx_all);
36350114
GP		 2897 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2898 set_feature_rx_vlan);
45bf454a
MG		 2899#ifdef CONFIG_RFS_ACCEL
2900 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2901 set_feature_arfs);
2902#endif
0e405443
GP		 2903
2904 return err ? -EINVAL : 0;
f62b8bb8
AV		 2905}
2906
2907static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2908{
2909 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2910 bool was_opened;
98e81b0a 2911 int err = 0;
506753b0 2912 bool reset;
f62b8bb8 2913
f62b8bb8 2914 mutex_lock(&priv->state_lock);
98e81b0a 2915
506753b0
TT		 2916 reset = !priv->params.lro_en &&
2917 (priv->params.rq_wq_type !=
2918 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2919
98e81b0a 2920 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2921 if (was_opened && reset)
98e81b0a
AS		 2922 mlx5e_close_locked(netdev);
2923
f62b8bb8 2924 netdev->mtu = new_mtu;
13f9bba7 2925 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2926
506753b0 2927 if (was_opened && reset)
98e81b0a
AS		 2928 err = mlx5e_open_locked(netdev);
2929
f62b8bb8
AV		 2930 mutex_unlock(&priv->state_lock);
2931
2932 return err;
2933}
2934
ef9814de
EBE		 2935static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2936{
2937 switch (cmd) {
2938 case SIOCSHWTSTAMP:
2939 return mlx5e_hwstamp_set(dev, ifr);
2940 case SIOCGHWTSTAMP:
2941 return mlx5e_hwstamp_get(dev, ifr);
2942 default:
2943 return -EOPNOTSUPP;
2944 }
2945}
2946
66e49ded
SM		 2947static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2948{
2949 struct mlx5e_priv *priv = netdev_priv(dev);
2950 struct mlx5_core_dev *mdev = priv->mdev;
2951
2952 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2953}
2954
79aab093
MS		 2955static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2956 __be16 vlan_proto)
66e49ded
SM		 2957{
2958 struct mlx5e_priv *priv = netdev_priv(dev);
2959 struct mlx5_core_dev *mdev = priv->mdev;
2960
79aab093
MS		 2961 if (vlan_proto != htons(ETH_P_8021Q))
2962 return -EPROTONOSUPPORT;
2963
66e49ded
SM		 2964 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2965 vlan, qos);
2966}
2967
f942380c
MHY		 2968static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2969{
2970 struct mlx5e_priv *priv = netdev_priv(dev);
2971 struct mlx5_core_dev *mdev = priv->mdev;
2972
2973 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2974}
2975
1edc57e2
MHY		 2976static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2977{
2978 struct mlx5e_priv *priv = netdev_priv(dev);
2979 struct mlx5_core_dev *mdev = priv->mdev;
2980
2981 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2982}
bd77bf1c
MHY		 2983
2984static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2985 int max_tx_rate)
2986{
2987 struct mlx5e_priv *priv = netdev_priv(dev);
2988 struct mlx5_core_dev *mdev = priv->mdev;
2989
2990 if (min_tx_rate)
2991 return -EOPNOTSUPP;
2992
2993 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
2994 max_tx_rate);
2995}
2996
66e49ded
SM		 2997static int mlx5_vport_link2ifla(u8 esw_link)
2998{
2999 switch (esw_link) {
3000 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3001 return IFLA_VF_LINK_STATE_DISABLE;
3002 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3003 return IFLA_VF_LINK_STATE_ENABLE;
3004 }
3005 return IFLA_VF_LINK_STATE_AUTO;
3006}
3007
3008static int mlx5_ifla_link2vport(u8 ifla_link)
3009{
3010 switch (ifla_link) {
3011 case IFLA_VF_LINK_STATE_DISABLE:
3012 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3013 case IFLA_VF_LINK_STATE_ENABLE:
3014 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3015 }
3016 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3017}
3018
3019static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3020 int link_state)
3021{
3022 struct mlx5e_priv *priv = netdev_priv(dev);
3023 struct mlx5_core_dev *mdev = priv->mdev;
3024
3025 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3026 mlx5_ifla_link2vport(link_state));
3027}
3028
3029static int mlx5e_get_vf_config(struct net_device *dev,
3030 int vf, struct ifla_vf_info *ivi)
3031{
3032 struct mlx5e_priv *priv = netdev_priv(dev);
3033 struct mlx5_core_dev *mdev = priv->mdev;
3034 int err;
3035
3036 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3037 if (err)
3038 return err;
3039 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3040 return 0;
3041}
3042
3043static int mlx5e_get_vf_stats(struct net_device *dev,
3044 int vf, struct ifla_vf_stats *vf_stats)
3045{
3046 struct mlx5e_priv *priv = netdev_priv(dev);
3047 struct mlx5_core_dev *mdev = priv->mdev;
3048
3049 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3050 vf_stats);
3051}
3052
4a25730e
HHZ		 3053void mlx5e_add_vxlan_port(struct net_device *netdev,
3054 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3055{
3056 struct mlx5e_priv *priv = netdev_priv(netdev);
3057
974c3f30
AD		 3058 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3059 return;
3060
b3f63c3d
MF		 3061 if (!mlx5e_vxlan_allowed(priv->mdev))
3062 return;
3063
974c3f30 3064 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3065}
3066
4a25730e
HHZ		 3067void mlx5e_del_vxlan_port(struct net_device *netdev,
3068 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3069{
3070 struct mlx5e_priv *priv = netdev_priv(netdev);
3071
974c3f30
AD		 3072 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3073 return;
3074
b3f63c3d
MF		 3075 if (!mlx5e_vxlan_allowed(priv->mdev))
3076 return;
3077
974c3f30 3078 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3079}
3080
3081static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3082 struct sk_buff *skb,
3083 netdev_features_t features)
3084{
3085 struct udphdr *udph;
3086 u16 proto;
3087 u16 port = 0;
3088
3089 switch (vlan_get_protocol(skb)) {
3090 case htons(ETH_P_IP):
3091 proto = ip_hdr(skb)->protocol;
3092 break;
3093 case htons(ETH_P_IPV6):
3094 proto = ipv6_hdr(skb)->nexthdr;
3095 break;
3096 default:
3097 goto out;
3098 }
3099
3100 if (proto == IPPROTO_UDP) {
3101 udph = udp_hdr(skb);
3102 port = be16_to_cpu(udph->dest);
3103 }
3104
3105 /* Verify if UDP port is being offloaded by HW */
3106 if (port && mlx5e_vxlan_lookup_port(priv, port))
3107 return features;
3108
3109out:
3110 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3111 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3112}
3113
3114static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3115 struct net_device *netdev,
3116 netdev_features_t features)
3117{
3118 struct mlx5e_priv *priv = netdev_priv(netdev);
3119
3120 features = vlan_features_check(skb, features);
3121 features = vxlan_features_check(skb, features);
3122
3123 /* Validate if the tunneled packet is being offloaded by HW */
3124 if (skb->encapsulation &&
3125 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3126 return mlx5e_vxlan_features_check(priv, skb, features);
3127
3128 return features;
3129}
3130
3947ca18
DJ		 3131static void mlx5e_tx_timeout(struct net_device *dev)
3132{
3133 struct mlx5e_priv *priv = netdev_priv(dev);
3134 bool sched_work = false;
3135 int i;
3136
3137 netdev_err(dev, "TX timeout detected\n");
3138
3139 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3140 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3141
2c1ccc99 3142 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3143 continue;
3144 sched_work = true;
c0f1147d 3145 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3146 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3147 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3148 }
3149
3150 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3151 schedule_work(&priv->tx_timeout_work);
3152}
3153
86994156
RS		 3154static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3155{
3156 struct mlx5e_priv *priv = netdev_priv(netdev);
3157 struct bpf_prog *old_prog;
3158 int err = 0;
3159 bool reset, was_opened;
3160 int i;
3161
17bedab2
MKL		 3162 if (prog && prog->xdp_adjust_head) {
3163 netdev_err(netdev, "Does not support bpf_xdp_adjust_head()\n");
3164 return -EOPNOTSUPP;
3165 }
3166
86994156
RS		 3167 mutex_lock(&priv->state_lock);
3168
3169 if ((netdev->features & NETIF_F_LRO) && prog) {
3170 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3171 err = -EINVAL;
3172 goto unlock;
3173 }
3174
3175 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3176 /* no need for full reset when exchanging programs */
3177 reset = (!priv->xdp_prog || !prog);
3178
3179 if (was_opened && reset)
3180 mlx5e_close_locked(netdev);
c54c0629
DB		 3181 if (was_opened && !reset) {
3182 /* num_channels is invariant here, so we can take the
3183 * batched reference right upfront.
3184 */
3185 prog = bpf_prog_add(prog, priv->params.num_channels);
3186 if (IS_ERR(prog)) {
3187 err = PTR_ERR(prog);
3188 goto unlock;
3189 }
3190 }
86994156 3191
c54c0629
DB		 3192 /* exchange programs, extra prog reference we got from caller
3193 * as long as we don't fail from this point onwards.
3194 */
86994156 3195 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3196 if (old_prog)
3197 bpf_prog_put(old_prog);
3198
3199 if (reset) /* change RQ type according to priv->xdp_prog */
3200 mlx5e_set_rq_priv_params(priv);
3201
3202 if (was_opened && reset)
3203 mlx5e_open_locked(netdev);
3204
3205 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3206 goto unlock;
3207
3208 /* exchanging programs w/o reset, we update ref counts on behalf
3209 * of the channels RQs here.
3210 */
86994156
RS		 3211 for (i = 0; i < priv->params.num_channels; i++) {
3212 struct mlx5e_channel *c = priv->channel[i];
3213
c0f1147d 3214 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3215 napi_synchronize(&c->napi);
3216 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3217
3218 old_prog = xchg(&c->rq.xdp_prog, prog);
3219
c0f1147d 3220 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3221 /* napi_schedule in case we have missed anything */
3222 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3223 napi_schedule(&c->napi);
3224
3225 if (old_prog)
3226 bpf_prog_put(old_prog);
3227 }
3228
3229unlock:
3230 mutex_unlock(&priv->state_lock);
3231 return err;
3232}
3233
3234static bool mlx5e_xdp_attached(struct net_device *dev)
3235{
3236 struct mlx5e_priv *priv = netdev_priv(dev);
3237
3238 return !!priv->xdp_prog;
3239}
3240
3241static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3242{
3243 switch (xdp->command) {
3244 case XDP_SETUP_PROG:
3245 return mlx5e_xdp_set(dev, xdp->prog);
3246 case XDP_QUERY_PROG:
3247 xdp->prog_attached = mlx5e_xdp_attached(dev);
3248 return 0;
3249 default:
3250 return -EINVAL;
3251 }
3252}
3253
80378384
CO		 3254#ifdef CONFIG_NET_POLL_CONTROLLER
3255/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3256 * reenabling interrupts.
3257 */
3258static void mlx5e_netpoll(struct net_device *dev)
3259{
3260 struct mlx5e_priv *priv = netdev_priv(dev);
3261 int i;
3262
3263 for (i = 0; i < priv->params.num_channels; i++)
3264 napi_schedule(&priv->channel[i]->napi);
3265}
3266#endif
3267
b0eed40e 3268static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3269 .ndo_open = mlx5e_open,
3270 .ndo_stop = mlx5e_close,
3271 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3272 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3273 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3274 .ndo_get_stats64 = mlx5e_get_stats,
3275 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3276 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3277 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3278 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3279 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3280 .ndo_change_mtu = mlx5e_change_mtu,
3281 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3282 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3283#ifdef CONFIG_RFS_ACCEL
3284 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3285#endif
3947ca18 3286 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3287 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3288#ifdef CONFIG_NET_POLL_CONTROLLER
3289 .ndo_poll_controller = mlx5e_netpoll,
3290#endif
b0eed40e
SM		 3291};
3292
3293static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3294 .ndo_open = mlx5e_open,
3295 .ndo_stop = mlx5e_close,
3296 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3297 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3298 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3299 .ndo_get_stats64 = mlx5e_get_stats,
3300 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3301 .ndo_set_mac_address = mlx5e_set_mac,
3302 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3303 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3304 .ndo_set_features = mlx5e_set_features,
3305 .ndo_change_mtu = mlx5e_change_mtu,
3306 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3307 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3308 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3309 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3310 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3311#ifdef CONFIG_RFS_ACCEL
3312 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3313#endif
b0eed40e
SM		 3314 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3315 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3316 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3317 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3318 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3319 .ndo_get_vf_config = mlx5e_get_vf_config,
3320 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3321 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3322 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3323 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3324#ifdef CONFIG_NET_POLL_CONTROLLER
3325 .ndo_poll_controller = mlx5e_netpoll,
3326#endif
370bad0f
OG		 3327 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3328 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3329};
3330
3331static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3332{
3333 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3334 return -ENOTSUPP;
3335 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3336 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3337 !MLX5_CAP_ETH(mdev, csum_cap) ||
3338 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3339 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3340 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3341 MLX5_CAP_FLOWTABLE(mdev,
3342 flow_table_properties_nic_receive.max_ft_level)
3343 < 3) {
f62b8bb8
AV		 3344 mlx5_core_warn(mdev,
3345 "Not creating net device, some required device capabilities are missing\n");
3346 return -ENOTSUPP;
3347 }
66189961
TT		 3348 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3349 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3350 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3351 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3352
f62b8bb8
AV		 3353 return 0;
3354}
3355
58d52291
AS		 3356u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3357{
3358 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3359
3360 return bf_buf_size -
3361 sizeof(struct mlx5e_tx_wqe) +
3362 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3363}
3364
d8c9660d
TT		 3365void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3366 u32 *indirection_rqt, int len,
85082dba
TT		 3367 int num_channels)
3368{
d8c9660d
TT		 3369 int node = mdev->priv.numa_node;
3370 int node_num_of_cores;
85082dba
TT		 3371 int i;
3372
d8c9660d
TT		 3373 if (node == -1)
3374 node = first_online_node;
3375
3376 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3377
3378 if (node_num_of_cores)
3379 num_channels = min_t(int, num_channels, node_num_of_cores);
3380
85082dba
TT		 3381 for (i = 0; i < len; i++)
3382 indirection_rqt[i] = i % num_channels;
3383}
3384
b797a684
SM		 3385static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3386{
3387 enum pcie_link_width width;
3388 enum pci_bus_speed speed;
3389 int err = 0;
3390
3391 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3392 if (err)
3393 return err;
3394
3395 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3396 return -EINVAL;
3397
3398 switch (speed) {
3399 case PCIE_SPEED_2_5GT:
3400 *pci_bw = 2500 * width;
3401 break;
3402 case PCIE_SPEED_5_0GT:
3403 *pci_bw = 5000 * width;
3404 break;
3405 case PCIE_SPEED_8_0GT:
3406 *pci_bw = 8000 * width;
3407 break;
3408 default:
3409 return -EINVAL;
3410 }
3411
3412 return 0;
3413}
3414
3415static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3416{
3417 return (link_speed && pci_bw &&
3418 (pci_bw < 40000) && (pci_bw < link_speed));
3419}
3420
9908aa29
TT		 3421void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3422{
3423 params->rx_cq_period_mode = cq_period_mode;
3424
3425 params->rx_cq_moderation.pkts =
3426 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3427 params->rx_cq_moderation.usec =
3428 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3429
3430 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3431 params->rx_cq_moderation.usec =
3432 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3433}
3434
cff92d7c
HHZ		 3435static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3436 u8 *min_inline_mode)
3437{
3438 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
34e4e990 3439 case MLX5_CAP_INLINE_MODE_L2:
cff92d7c
HHZ		 3440 *min_inline_mode = MLX5_INLINE_MODE_L2;
3441 break;
34e4e990
RD		 3442 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3443 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
cff92d7c 3444 break;
34e4e990 3445 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
cff92d7c
HHZ		 3446 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3447 break;
3448 }
3449}
3450
2b029556
SM		 3451u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3452{
3453 int i;
3454
3455 /* The supported periods are organized in ascending order */
3456 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3457 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3458 break;
3459
3460 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3461}
3462
6bfd390b
HHZ		 3463static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3464 struct net_device *netdev,
127ea380
HHZ		 3465 const struct mlx5e_profile *profile,
3466 void *ppriv)
f62b8bb8
AV		 3467{
3468 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3469 u32 link_speed = 0;
3470 u32 pci_bw = 0;
cb3c7fd4
GR		 3471 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3472 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3473 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3474
2fc4bfb7
SM		 3475 priv->mdev = mdev;
3476 priv->netdev = netdev;
3477 priv->params.num_channels = profile->max_nch(mdev);
3478 priv->profile = profile;
3479 priv->ppriv = ppriv;
3480
2b029556
SM		 3481 priv->params.lro_timeout =
3482 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3483
2fc4bfb7 3484 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3485
b797a684 3486 /* set CQE compression */
9bcc8606 3487 priv->params.rx_cqe_compress_def = false;
b797a684
SM		 3488 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3489 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3490 mlx5e_get_max_linkspeed(mdev, &link_speed);
3491 mlx5e_get_pci_bw(mdev, &pci_bw);
3492 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3493 link_speed, pci_bw);
9bcc8606 3494 priv->params.rx_cqe_compress_def =
b797a684
SM		 3495 cqe_compress_heuristic(link_speed, pci_bw);
3496 }
b797a684 3497
2fc4bfb7
SM		 3498 mlx5e_set_rq_priv_params(priv);
3499 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3500 priv->params.lro_en = true;
9908aa29 3501
cb3c7fd4
GR		 3502 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3503 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3504
3505 priv->params.tx_cq_moderation.usec =
f62b8bb8 3506 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3507 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3508 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3509 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3510 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3511 priv->params.num_tc = 1;
2be6967c 3512 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3513
57afead5
AS		 3514 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3515 sizeof(priv->params.toeplitz_hash_key));
3516
d8c9660d 3517 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3518 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3519
e4b85508
SM		 3520 priv->params.lro_wqe_sz =
3521 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3522 /* Extra room needed for build_skb */
3523 MLX5_RX_HEADROOM -
3524 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3525
9908aa29 3526 /* Initialize pflags */
59ece1c9
SD		 3527 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3528 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9bcc8606 3529 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
9908aa29 3530
f62b8bb8
AV		 3531 mutex_init(&priv->state_lock);
3532
3533 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3534 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3535 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3536 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3537}
3538
3539static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3540{
3541 struct mlx5e_priv *priv = netdev_priv(netdev);
3542
e1d7d349 3543 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3544 if (is_zero_ether_addr(netdev->dev_addr) &&
3545 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3546 eth_hw_addr_random(netdev);
3547 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3548 }
f62b8bb8
AV		 3549}
3550
cb67b832
HHZ		 3551static const struct switchdev_ops mlx5e_switchdev_ops = {
3552 .switchdev_port_attr_get = mlx5e_attr_get,
3553};
3554
6bfd390b 3555static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3556{
3557 struct mlx5e_priv *priv = netdev_priv(netdev);
3558 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3559 bool fcs_supported;
3560 bool fcs_enabled;
f62b8bb8
AV		 3561
3562 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3563
08fb1dac 3564 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3565 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3566#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3567 if (MLX5_CAP_GEN(mdev, qos))
3568 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3569#endif
3570 } else {
b0eed40e 3571 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3572 }
66e49ded 3573
f62b8bb8
AV		 3574 netdev->watchdog_timeo = 15 * HZ;
3575
3576 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3577
12be4b21 3578 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3579 netdev->vlan_features |= NETIF_F_IP_CSUM;
3580 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3581 netdev->vlan_features |= NETIF_F_GRO;
3582 netdev->vlan_features |= NETIF_F_TSO;
3583 netdev->vlan_features |= NETIF_F_TSO6;
3584 netdev->vlan_features |= NETIF_F_RXCSUM;
3585 netdev->vlan_features |= NETIF_F_RXHASH;
3586
3587 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3588 netdev->vlan_features |= NETIF_F_LRO;
3589
3590 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3591 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3592 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3593 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3594
b3f63c3d 3595 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3596 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3597 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3598 NETIF_F_GSO_PARTIAL;
b3f63c3d 3599 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3600 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3601 netdev->hw_enc_features |= NETIF_F_TSO;
3602 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3603 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3604 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3605 NETIF_F_GSO_PARTIAL;
3606 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3607 }
3608
94cb1ebb
EBE		 3609 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3610
3611 if (fcs_supported)
3612 netdev->hw_features |= NETIF_F_RXALL;
3613
f62b8bb8
AV		 3614 netdev->features = netdev->hw_features;
3615 if (!priv->params.lro_en)
3616 netdev->features &= ~NETIF_F_LRO;
3617
94cb1ebb
EBE		 3618 if (fcs_enabled)
3619 netdev->features &= ~NETIF_F_RXALL;
3620
e8f887ac
AV		 3621#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3622 if (FT_CAP(flow_modify_en) &&
3623 FT_CAP(modify_root) &&
3624 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3625 FT_CAP(flow_table_modify)) {
3626 netdev->hw_features |= NETIF_F_HW_TC;
3627#ifdef CONFIG_RFS_ACCEL
3628 netdev->hw_features |= NETIF_F_NTUPLE;
3629#endif
3630 }
e8f887ac 3631
f62b8bb8
AV		 3632 netdev->features |= NETIF_F_HIGHDMA;
3633
3634 netdev->priv_flags |= IFF_UNICAST_FLT;
3635
3636 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3637
3638#ifdef CONFIG_NET_SWITCHDEV
3639 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3640 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3641#endif
f62b8bb8
AV		 3642}
3643
593cf338
RS		 3644static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3645{
3646 struct mlx5_core_dev *mdev = priv->mdev;
3647 int err;
3648
3649 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3650 if (err) {
3651 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3652 priv->q_counter = 0;
3653 }
3654}
3655
3656static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3657{
3658 if (!priv->q_counter)
3659 return;
3660
3661 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3662}
3663
6bfd390b
HHZ		 3664static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3665 struct net_device *netdev,
127ea380
HHZ		 3666 const struct mlx5e_profile *profile,
3667 void *ppriv)
6bfd390b
HHZ		 3668{
3669 struct mlx5e_priv *priv = netdev_priv(netdev);
3670
127ea380 3671 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3672 mlx5e_build_nic_netdev(netdev);
3673 mlx5e_vxlan_init(priv);
3674}
3675
3676static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3677{
3678 mlx5e_vxlan_cleanup(priv);
127ea380 3679
a055c19b
DB		 3680 if (priv->xdp_prog)
3681 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3682}
3683
3684static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3685{
3686 struct mlx5_core_dev *mdev = priv->mdev;
3687 int err;
3688 int i;
3689
3690 err = mlx5e_create_indirect_rqts(priv);
3691 if (err) {
3692 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3693 return err;
3694 }
3695
3696 err = mlx5e_create_direct_rqts(priv);
3697 if (err) {
3698 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3699 goto err_destroy_indirect_rqts;
3700 }
3701
3702 err = mlx5e_create_indirect_tirs(priv);
3703 if (err) {
3704 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3705 goto err_destroy_direct_rqts;
3706 }
3707
3708 err = mlx5e_create_direct_tirs(priv);
3709 if (err) {
3710 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3711 goto err_destroy_indirect_tirs;
3712 }
3713
3714 err = mlx5e_create_flow_steering(priv);
3715 if (err) {
3716 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3717 goto err_destroy_direct_tirs;
3718 }
3719
3720 err = mlx5e_tc_init(priv);
3721 if (err)
3722 goto err_destroy_flow_steering;
3723
3724 return 0;
3725
3726err_destroy_flow_steering:
3727 mlx5e_destroy_flow_steering(priv);
3728err_destroy_direct_tirs:
3729 mlx5e_destroy_direct_tirs(priv);
3730err_destroy_indirect_tirs:
3731 mlx5e_destroy_indirect_tirs(priv);
3732err_destroy_direct_rqts:
3733 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3734 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3735err_destroy_indirect_rqts:
3736 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3737 return err;
3738}
3739
3740static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3741{
3742 int i;
3743
3744 mlx5e_tc_cleanup(priv);
3745 mlx5e_destroy_flow_steering(priv);
3746 mlx5e_destroy_direct_tirs(priv);
3747 mlx5e_destroy_indirect_tirs(priv);
3748 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3749 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3750 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3751}
3752
3753static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3754{
3755 int err;
3756
3757 err = mlx5e_create_tises(priv);
3758 if (err) {
3759 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3760 return err;
3761 }
3762
3763#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 3764 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 3765#endif
3766 return 0;
3767}
3768
3769static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3770{
3771 struct net_device *netdev = priv->netdev;
3772 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3773 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3774 struct mlx5_eswitch_rep rep;
6bfd390b 3775
7907f23a
AH		 3776 mlx5_lag_add(mdev, netdev);
3777
6bfd390b 3778 mlx5e_enable_async_events(priv);
127ea380
HHZ		 3779
3780 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3781 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3782 rep.load = mlx5e_nic_rep_load;
3783 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3784 rep.vport = FDB_UPLINK_VPORT;
726293f1 3785 rep.netdev = netdev;
9deb2241 3786 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3787 }
610e89e0
SM		 3788
3789 if (netdev->reg_state != NETREG_REGISTERED)
3790 return;
3791
3792 /* Device already registered: sync netdev system state */
3793 if (mlx5e_vxlan_allowed(mdev)) {
3794 rtnl_lock();
3795 udp_tunnel_get_rx_info(netdev);
3796 rtnl_unlock();
3797 }
3798
3799 queue_work(priv->wq, &priv->set_rx_mode_work);
6bfd390b
HHZ		 3800}
3801
3802static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3803{
3deef8ce
SM		 3804 struct mlx5_core_dev *mdev = priv->mdev;
3805 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3806
6bfd390b 3807 queue_work(priv->wq, &priv->set_rx_mode_work);
3deef8ce
SM		 3808 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3809 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 3810 mlx5e_disable_async_events(priv);
3deef8ce 3811 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 3812}
3813
3814static const struct mlx5e_profile mlx5e_nic_profile = {
3815 .init = mlx5e_nic_init,
3816 .cleanup = mlx5e_nic_cleanup,
3817 .init_rx = mlx5e_init_nic_rx,
3818 .cleanup_rx = mlx5e_cleanup_nic_rx,
3819 .init_tx = mlx5e_init_nic_tx,
3820 .cleanup_tx = mlx5e_cleanup_nic_tx,
3821 .enable = mlx5e_nic_enable,
3822 .disable = mlx5e_nic_disable,
3823 .update_stats = mlx5e_update_stats,
3824 .max_nch = mlx5e_get_max_num_channels,
3825 .max_tc = MLX5E_MAX_NUM_TC,
3826};
3827
26e59d80
MHY		 3828struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3829 const struct mlx5e_profile *profile,
3830 void *ppriv)
f62b8bb8 3831{
26e59d80 3832 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3833 struct net_device *netdev;
3834 struct mlx5e_priv *priv;
f62b8bb8 3835
08fb1dac 3836 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3837 nch * profile->max_tc,
08fb1dac 3838 nch);
f62b8bb8
AV		 3839 if (!netdev) {
3840 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3841 return NULL;
3842 }
3843
127ea380 3844 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3845
3846 netif_carrier_off(netdev);
3847
3848 priv = netdev_priv(netdev);
3849
7bb29755
MF		 3850 priv->wq = create_singlethread_workqueue("mlx5e");
3851 if (!priv->wq)
26e59d80
MHY		 3852 goto err_cleanup_nic;
3853
3854 return netdev;
3855
3856err_cleanup_nic:
3857 profile->cleanup(priv);
3858 free_netdev(netdev);
3859
3860 return NULL;
3861}
3862
3863int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3864{
3865 const struct mlx5e_profile *profile;
3866 struct mlx5e_priv *priv;
b80f71f5 3867 u16 max_mtu;
26e59d80
MHY		 3868 int err;
3869
3870 priv = netdev_priv(netdev);
3871 profile = priv->profile;
3872 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3873
6bfd390b
HHZ		 3874 err = profile->init_tx(priv);
3875 if (err)
ec8b9981 3876 goto out;
5c50368f
AS		 3877
3878 err = mlx5e_open_drop_rq(priv);
3879 if (err) {
3880 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3881 goto err_cleanup_tx;
5c50368f
AS		 3882 }
3883
6bfd390b
HHZ		 3884 err = profile->init_rx(priv);
3885 if (err)
5c50368f 3886 goto err_close_drop_rq;
5c50368f 3887
593cf338
RS		 3888 mlx5e_create_q_counter(priv);
3889
33cfaaa8 3890 mlx5e_init_l2_addr(priv);
5c50368f 3891
b80f71f5
JW		 3892 /* MTU range: 68 - hw-specific max */
3893 netdev->min_mtu = ETH_MIN_MTU;
3894 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3895 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3896
13f9bba7
SM		 3897 mlx5e_set_dev_port_mtu(netdev);
3898
6bfd390b
HHZ		 3899 if (profile->enable)
3900 profile->enable(priv);
f62b8bb8 3901
26e59d80
MHY		 3902 rtnl_lock();
3903 if (netif_running(netdev))
3904 mlx5e_open(netdev);
3905 netif_device_attach(netdev);
3906 rtnl_unlock();
f62b8bb8 3907
26e59d80 3908 return 0;
5c50368f
AS		 3909
3910err_close_drop_rq:
3911 mlx5e_close_drop_rq(priv);
3912
6bfd390b
HHZ		 3913err_cleanup_tx:
3914 profile->cleanup_tx(priv);
5c50368f 3915
26e59d80
MHY		 3916out:
3917 return err;
f62b8bb8
AV		 3918}
3919
127ea380
HHZ		 3920static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3921{
3922 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3923 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3924 int vport;
dbe413e3 3925 u8 mac[ETH_ALEN];
127ea380
HHZ		 3926
3927 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3928 return;
3929
dbe413e3
HHZ		 3930 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3931
127ea380
HHZ		 3932 for (vport = 1; vport < total_vfs; vport++) {
3933 struct mlx5_eswitch_rep rep;
3934
cb67b832
HHZ		 3935 rep.load = mlx5e_vport_rep_load;
3936 rep.unload = mlx5e_vport_rep_unload;
127ea380 3937 rep.vport = vport;
dbe413e3 3938 ether_addr_copy(rep.hw_id, mac);
9deb2241 3939 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3940 }
3941}
3942
26e59d80
MHY		 3943void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3944{
3945 struct mlx5e_priv *priv = netdev_priv(netdev);
3946 const struct mlx5e_profile *profile = priv->profile;
3947
3948 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80
MHY		 3949
3950 rtnl_lock();
3951 if (netif_running(netdev))
3952 mlx5e_close(netdev);
3953 netif_device_detach(netdev);
3954 rtnl_unlock();
3955
37f304d1
SM		 3956 if (profile->disable)
3957 profile->disable(priv);
3958 flush_workqueue(priv->wq);
3959
26e59d80
MHY		 3960 mlx5e_destroy_q_counter(priv);
3961 profile->cleanup_rx(priv);
3962 mlx5e_close_drop_rq(priv);
3963 profile->cleanup_tx(priv);
26e59d80
MHY		 3964 cancel_delayed_work_sync(&priv->update_stats_work);
3965}
3966
3967/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3968 * hardware contexts and to connect it to the current netdev.
3969 */
3970static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3971{
3972 struct mlx5e_priv *priv = vpriv;
3973 struct net_device *netdev = priv->netdev;
3974 int err;
3975
3976 if (netif_device_present(netdev))
3977 return 0;
3978
3979 err = mlx5e_create_mdev_resources(mdev);
3980 if (err)
3981 return err;
3982
3983 err = mlx5e_attach_netdev(mdev, netdev);
3984 if (err) {
3985 mlx5e_destroy_mdev_resources(mdev);
3986 return err;
3987 }
3988
3989 return 0;
3990}
3991
3992static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3993{
3994 struct mlx5e_priv *priv = vpriv;
3995 struct net_device *netdev = priv->netdev;
3996
3997 if (!netif_device_present(netdev))
3998 return;
3999
4000 mlx5e_detach_netdev(mdev, netdev);
4001 mlx5e_destroy_mdev_resources(mdev);
4002}
4003
b50d292b
HHZ		 4004static void *mlx5e_add(struct mlx5_core_dev *mdev)
4005{
127ea380 4006 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4007 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4008 void *ppriv = NULL;
26e59d80
MHY		 4009 void *priv;
4010 int vport;
4011 int err;
4012 struct net_device *netdev;
b50d292b 4013
26e59d80
MHY		 4014 err = mlx5e_check_required_hca_cap(mdev);
4015 if (err)
b50d292b
HHZ		 4016 return NULL;
4017
127ea380
HHZ		 4018 mlx5e_register_vport_rep(mdev);
4019
4020 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4021 ppriv = &esw->offloads.vport_reps[0];
4022
26e59d80
MHY		 4023 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4024 if (!netdev) {
4025 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4026 goto err_unregister_reps;
4027 }
4028
4029 priv = netdev_priv(netdev);
4030
4031 err = mlx5e_attach(mdev, priv);
4032 if (err) {
4033 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4034 goto err_destroy_netdev;
4035 }
4036
4037 err = register_netdev(netdev);
4038 if (err) {
4039 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4040 goto err_detach;
b50d292b 4041 }
26e59d80
MHY		 4042
4043 return priv;
4044
4045err_detach:
4046 mlx5e_detach(mdev, priv);
4047
4048err_destroy_netdev:
4049 mlx5e_destroy_netdev(mdev, priv);
4050
4051err_unregister_reps:
4052 for (vport = 1; vport < total_vfs; vport++)
4053 mlx5_eswitch_unregister_vport_rep(esw, vport);
4054
4055 return NULL;
b50d292b
HHZ		 4056}
4057
cb67b832 4058void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4059{
6bfd390b 4060 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4061 struct net_device *netdev = priv->netdev;
4062
7bb29755 4063 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4064 if (profile->cleanup)
4065 profile->cleanup(priv);
26e59d80 4066 free_netdev(netdev);
f62b8bb8
AV		 4067}
4068
b50d292b
HHZ		 4069static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4070{
127ea380
HHZ		 4071 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4072 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4073 struct mlx5e_priv *priv = vpriv;
127ea380 4074 int vport;
b50d292b 4075
127ea380
HHZ		 4076 for (vport = 1; vport < total_vfs; vport++)
4077 mlx5_eswitch_unregister_vport_rep(esw, vport);
4078
5e1e93c7 4079 unregister_netdev(priv->netdev);
26e59d80
MHY		 4080 mlx5e_detach(mdev, vpriv);
4081 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4082}
4083
f62b8bb8
AV		 4084static void *mlx5e_get_netdev(void *vpriv)
4085{
4086 struct mlx5e_priv *priv = vpriv;
4087
4088 return priv->netdev;
4089}
4090
4091static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4092 .add = mlx5e_add,
4093 .remove = mlx5e_remove,
26e59d80
MHY		 4094 .attach = mlx5e_attach,
4095 .detach = mlx5e_detach,
f62b8bb8
AV		 4096 .event = mlx5e_async_event,
4097 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4098 .get_dev = mlx5e_get_netdev,
4099};
4100
4101void mlx5e_init(void)
4102{
665bc539 4103 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4104 mlx5_register_interface(&mlx5e_interface);
4105}
4106
4107void mlx5e_cleanup(void)
4108{
4109 mlx5_unregister_interface(&mlx5e_interface);
4110}
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