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net/mlx5e: Fail safe cqe compressing/moderation mode setting
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac 33#include <net/tc_act/tc_gact.h>
b4e029da 34#include <linux/crash_dump.h>
e8f887ac 35#include <net/pkt_cls.h>
86d722ad 36#include <linux/mlx5/fs.h>
b3f63c3d 37#include <net/vxlan.h>
86994156 38#include <linux/bpf.h>
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
66e49ded 41#include "eswitch.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
9908aa29 58 u8 cq_period_mode;
f62b8bb8
AV		 59};
60
61struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
b5503b99 64 struct mlx5e_sq_param xdp_sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
2fc4bfb7
SM		 71static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72{
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76}
77
6a9764ef
SM		 78void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 80{
6a9764ef
SM		 81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
2fc4bfb7 84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 85 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 96 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 99
100 /* Extra room needed for build_skb */
6a9764ef 101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 103 }
2fc4bfb7 104
6a9764ef
SM		 105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 110}
111
6a9764ef 112static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 113{
6a9764ef
SM		 114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
2fc4bfb7
SM		 116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 118 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 119}
120
f62b8bb8
AV		 121static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122{
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
e7546514 127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 128
87424ad5
SD		 129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 131 netif_carrier_on(priv->netdev);
87424ad5
SD		 132 } else {
133 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 134 netif_carrier_off(priv->netdev);
87424ad5 135 }
f62b8bb8
AV		 136}
137
138static void mlx5e_update_carrier_work(struct work_struct *work)
139{
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
142
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
147}
148
3947ca18
DJ		 149static void mlx5e_tx_timeout_work(struct work_struct *work)
150{
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 tx_timeout_work);
153 int err;
154
155 rtnl_lock();
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
158 goto unlock;
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
161 if (err)
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
163 err);
164unlock:
165 mutex_unlock(&priv->state_lock);
166 rtnl_unlock();
167}
168
9218b44d 169static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 170{
9218b44d 171 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
9218b44d 174 u64 tx_offload_none = 0;
f62b8bb8
AV		 175 int i, j;
176
9218b44d 177 memset(s, 0, sizeof(*s));
ff9c852f
SM		 178 for (i = 0; i < priv->channels.num; i++) {
179 struct mlx5e_channel *c = priv->channels.c[i];
180
181 rq_stats = &c->rq.stats;
f62b8bb8 182
faf4478b
GP		 183 s->rx_packets += rq_stats->packets;
184 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 185 s->rx_lro_packets += rq_stats->lro_packets;
186 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 187 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 188 s->rx_csum_complete += rq_stats->csum_complete;
189 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 190 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 191 s->rx_xdp_tx += rq_stats->xdp_tx;
192 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 193 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 194 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 195 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 196 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
197 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 198 s->rx_cache_reuse += rq_stats->cache_reuse;
199 s->rx_cache_full += rq_stats->cache_full;
200 s->rx_cache_empty += rq_stats->cache_empty;
201 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 202
6a9764ef 203 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 204 sq_stats = &c->sq[j].stats;
f62b8bb8 205
faf4478b
GP		 206 s->tx_packets += sq_stats->packets;
207 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 208 s->tx_tso_packets += sq_stats->tso_packets;
209 s->tx_tso_bytes += sq_stats->tso_bytes;
210 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
211 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 212 s->tx_queue_stopped += sq_stats->stopped;
213 s->tx_queue_wake += sq_stats->wake;
214 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 215 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 216 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
217 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 218 }
219 }
220
9218b44d 221 /* Update calculated offload counters */
bfe6d8d1
GP		 222 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
223 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 224
bfe6d8d1 225 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 226 priv->stats.pport.phy_counters,
227 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 228}
229
230static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
231{
232 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
233 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 234 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 235 struct mlx5_core_dev *mdev = priv->mdev;
236
f62b8bb8
AV		 237 MLX5_SET(query_vport_counter_in, in, opcode,
238 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
239 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
240 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
241
242 memset(out, 0, outlen);
9218b44d
GP		 243 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
244}
245
246static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
247{
248 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
249 struct mlx5_core_dev *mdev = priv->mdev;
250 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 251 int prio;
9218b44d
GP		 252 void *out;
253 u32 *in;
254
255 in = mlx5_vzalloc(sz);
256 if (!in)
f62b8bb8
AV		 257 goto free_out;
258
9218b44d 259 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 260
9218b44d
GP		 261 out = pstats->IEEE_802_3_counters;
262 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
263 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 272
121fcdc8
GP		 273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
5db0a4f6
GP		 277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 }
282
cf678570
GP		 283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
289 }
290
f62b8bb8 291free_out:
9218b44d
GP		 292 kvfree(in);
293}
294
295static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
296{
297 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
298
299 if (!priv->q_counter)
300 return;
301
302 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
303 &qcnt->rx_out_of_buffer);
304}
305
0f7f3481
GP		 306static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
307{
308 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
311 void *out;
312 u32 *in;
313
314 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
315 return;
316
317 in = mlx5_vzalloc(sz);
318 if (!in)
319 return;
320
321 out = pcie_stats->pcie_perf_counters;
322 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
323 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
324
325 kvfree(in);
326}
327
9218b44d
GP		 328void mlx5e_update_stats(struct mlx5e_priv *priv)
329{
3dd69e3d 330 mlx5e_update_pcie_counters(priv);
9218b44d 331 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 332 mlx5e_update_vport_counters(priv);
333 mlx5e_update_q_counter(priv);
121fcdc8 334 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 335}
336
cb67b832 337void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 338{
339 struct delayed_work *dwork = to_delayed_work(work);
340 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
341 update_stats_work);
342 mutex_lock(&priv->state_lock);
343 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 344 priv->profile->update_stats(priv);
7bb29755
MF		 345 queue_delayed_work(priv->wq, dwork,
346 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 347 }
348 mutex_unlock(&priv->state_lock);
349}
350
daa21560
TT		 351static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
352 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 353{
daa21560 354 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 355 struct ptp_clock_event ptp_event;
356 struct mlx5_eqe *eqe = NULL;
daa21560 357
e0f46eb9 358 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 359 return;
360
f62b8bb8
AV		 361 switch (event) {
362 case MLX5_DEV_EVENT_PORT_UP:
363 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 364 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 365 break;
ee7f1220
EE		 366 case MLX5_DEV_EVENT_PPS:
367 eqe = (struct mlx5_eqe *)param;
368 ptp_event.type = PTP_CLOCK_EXTTS;
369 ptp_event.index = eqe->data.pps.pin;
370 ptp_event.timestamp =
371 timecounter_cyc2time(&priv->tstamp.clock,
372 be64_to_cpu(eqe->data.pps.time_stamp));
373 mlx5e_pps_event_handler(vpriv, &ptp_event);
374 break;
f62b8bb8
AV		 375 default:
376 break;
377 }
378}
379
f62b8bb8
AV		 380static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
381{
e0f46eb9 382 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 383}
384
385static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
386{
e0f46eb9 387 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 388 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 389}
390
7e426671
TT		 391static inline int mlx5e_get_wqe_mtt_sz(void)
392{
393 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
394 * To avoid copying garbage after the mtt array, we allocate
395 * a little more.
396 */
397 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
398 MLX5_UMR_MTT_ALIGNMENT);
399}
400
31391048
SM		 401static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
402 struct mlx5e_icosq *sq,
403 struct mlx5e_umr_wqe *wqe,
404 u16 ix)
7e426671
TT		 405{
406 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
407 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
408 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 409 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 410 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
411 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
412
413 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
414 ds_cnt);
415 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
416 cseg->imm = rq->mkey_be;
417
418 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 419 ucseg->xlt_octowords =
7e426671
TT		 420 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
421 ucseg->bsf_octowords =
422 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
423 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
424
425 dseg->lkey = sq->mkey_be;
426 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
427}
428
429static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
430 struct mlx5e_channel *c)
431{
432 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
433 int mtt_sz = mlx5e_get_wqe_mtt_sz();
434 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
435 int i;
436
21c59685
SM		 437 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
438 GFP_KERNEL, cpu_to_node(c->cpu));
439 if (!rq->mpwqe.info)
7e426671
TT		 440 goto err_out;
441
442 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 443 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 444 cpu_to_node(c->cpu));
21c59685 445 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 446 goto err_free_wqe_info;
447
448 for (i = 0; i < wq_sz; i++) {
21c59685 449 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 450
21c59685 451 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 452 MLX5_UMR_ALIGN);
453 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
454 PCI_DMA_TODEVICE);
455 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
456 goto err_unmap_mtts;
457
458 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
459 }
460
461 return 0;
462
463err_unmap_mtts:
464 while (--i >= 0) {
21c59685 465 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 466
467 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
468 PCI_DMA_TODEVICE);
469 }
21c59685 470 kfree(rq->mpwqe.mtt_no_align);
7e426671 471err_free_wqe_info:
21c59685 472 kfree(rq->mpwqe.info);
7e426671
TT		 473
474err_out:
475 return -ENOMEM;
476}
477
478static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
479{
480 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
481 int mtt_sz = mlx5e_get_wqe_mtt_sz();
482 int i;
483
484 for (i = 0; i < wq_sz; i++) {
21c59685 485 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 486
487 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
488 PCI_DMA_TODEVICE);
489 }
21c59685
SM		 490 kfree(rq->mpwqe.mtt_no_align);
491 kfree(rq->mpwqe.info);
7e426671
TT		 492}
493
a43b25da 494static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 495 u64 npages, u8 page_shift,
496 struct mlx5_core_mkey *umr_mkey)
3608ae77 497{
3608ae77
TT		 498 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
499 void *mkc;
500 u32 *in;
501 int err;
502
ec8b9981
TT		 503 if (!MLX5E_VALID_NUM_MTTS(npages))
504 return -EINVAL;
505
3608ae77
TT		 506 in = mlx5_vzalloc(inlen);
507 if (!in)
508 return -ENOMEM;
509
510 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
511
3608ae77
TT		 512 MLX5_SET(mkc, mkc, free, 1);
513 MLX5_SET(mkc, mkc, umr_en, 1);
514 MLX5_SET(mkc, mkc, lw, 1);
515 MLX5_SET(mkc, mkc, lr, 1);
516 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
517
518 MLX5_SET(mkc, mkc, qpn, 0xffffff);
519 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 520 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 521 MLX5_SET(mkc, mkc, translations_octword_size,
522 MLX5_MTT_OCTW(npages));
ec8b9981 523 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 524
ec8b9981 525 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 526
527 kvfree(in);
528 return err;
529}
530
a43b25da 531static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 532{
6a9764ef 533 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 534
a43b25da 535 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 536}
537
3b77235b 538static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 539 struct mlx5e_params *params,
540 struct mlx5e_rq_param *rqp,
3b77235b 541 struct mlx5e_rq *rq)
f62b8bb8 542{
a43b25da 543 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 544 void *rqc = rqp->rqc;
f62b8bb8 545 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 546 u32 byte_count;
1bfecfca
SM		 547 u32 frag_sz;
548 int npages;
f62b8bb8
AV		 549 int wq_sz;
550 int err;
551 int i;
552
6a9764ef 553 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 554
6a9764ef 555 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 556 &rq->wq_ctrl);
557 if (err)
558 return err;
559
560 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
561
562 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 563
6a9764ef 564 rq->wq_type = params->rq_wq_type;
7e426671
TT		 565 rq->pdev = c->pdev;
566 rq->netdev = c->netdev;
a43b25da 567 rq->tstamp = c->tstamp;
7e426671
TT		 568 rq->channel = c;
569 rq->ix = c->ix;
a43b25da 570 rq->mdev = mdev;
97bc402d 571
6a9764ef 572 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 573 if (IS_ERR(rq->xdp_prog)) {
574 err = PTR_ERR(rq->xdp_prog);
575 rq->xdp_prog = NULL;
576 goto err_rq_wq_destroy;
577 }
7e426671 578
d8bec2b2 579 if (rq->xdp_prog) {
b5503b99 580 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 581 rq->rx_headroom = XDP_PACKET_HEADROOM;
582 } else {
583 rq->buff.map_dir = DMA_FROM_DEVICE;
584 rq->rx_headroom = MLX5_RX_HEADROOM;
585 }
b5503b99 586
6a9764ef 587 switch (rq->wq_type) {
461017cb 588 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
a43b25da 589 if (mlx5e_is_vf_vport_rep(c->priv)) {
f5f82476
OG		 590 err = -EINVAL;
591 goto err_rq_wq_destroy;
592 }
593
461017cb
TT		 594 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
595 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 596 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 597
6a9764ef
SM		 598 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
599 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 600
601 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
602 byte_count = rq->buff.wqe_sz;
ec8b9981 603
a43b25da 604 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 605 if (err)
606 goto err_rq_wq_destroy;
ec8b9981
TT		 607 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
608
609 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
610 if (err)
611 goto err_destroy_umr_mkey;
461017cb
TT		 612 break;
613 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 614 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
615 GFP_KERNEL, cpu_to_node(c->cpu));
616 if (!rq->dma_info) {
461017cb
TT		 617 err = -ENOMEM;
618 goto err_rq_wq_destroy;
619 }
1bfecfca 620
a43b25da 621 if (mlx5e_is_vf_vport_rep(c->priv))
f5f82476
OG		 622 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
623 else
624 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
625
461017cb 626 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 627 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 628
6a9764ef
SM		 629 rq->buff.wqe_sz = params->lro_en ?
630 params->lro_wqe_sz :
a43b25da 631 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 632 byte_count = rq->buff.wqe_sz;
633
634 /* calc the required page order */
d8bec2b2 635 frag_sz = rq->rx_headroom +
1bfecfca
SM		 636 byte_count /* packet data */ +
637 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
638 frag_sz = SKB_DATA_ALIGN(frag_sz);
639
640 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
641 rq->buff.page_order = order_base_2(npages);
642
461017cb 643 byte_count |= MLX5_HW_START_PADDING;
7e426671 644 rq->mkey_be = c->mkey_be;
461017cb 645 }
f62b8bb8
AV		 646
647 for (i = 0; i < wq_sz; i++) {
648 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
649
461017cb 650 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 651 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 652 }
653
cb3c7fd4 654 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 655 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 656 rq->page_cache.head = 0;
657 rq->page_cache.tail = 0;
658
f62b8bb8
AV		 659 return 0;
660
ec8b9981
TT		 661err_destroy_umr_mkey:
662 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
663
f62b8bb8 664err_rq_wq_destroy:
97bc402d
DB		 665 if (rq->xdp_prog)
666 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 667 mlx5_wq_destroy(&rq->wq_ctrl);
668
669 return err;
670}
671
3b77235b 672static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 673{
4415a031
TT		 674 int i;
675
86994156
RS		 676 if (rq->xdp_prog)
677 bpf_prog_put(rq->xdp_prog);
678
461017cb
TT		 679 switch (rq->wq_type) {
680 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 681 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 682 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 683 break;
684 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 685 kfree(rq->dma_info);
461017cb
TT		 686 }
687
4415a031
TT		 688 for (i = rq->page_cache.head; i != rq->page_cache.tail;
689 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
690 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
691
692 mlx5e_page_release(rq, dma_info, false);
693 }
f62b8bb8
AV		 694 mlx5_wq_destroy(&rq->wq_ctrl);
695}
696
6a9764ef
SM		 697static int mlx5e_create_rq(struct mlx5e_rq *rq,
698 struct mlx5e_rq_param *param)
f62b8bb8 699{
a43b25da 700 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 701
702 void *in;
703 void *rqc;
704 void *wq;
705 int inlen;
706 int err;
707
708 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
709 sizeof(u64) * rq->wq_ctrl.buf.npages;
710 in = mlx5_vzalloc(inlen);
711 if (!in)
712 return -ENOMEM;
713
714 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
715 wq = MLX5_ADDR_OF(rqc, rqc, wq);
716
717 memcpy(rqc, param->rqc, sizeof(param->rqc));
718
97de9f31 719 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 721 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 722 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 723 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
724
725 mlx5_fill_page_array(&rq->wq_ctrl.buf,
726 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
727
7db22ffb 728 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 729
730 kvfree(in);
731
732 return err;
733}
734
36350114
GP		 735static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
736 int next_state)
f62b8bb8
AV		 737{
738 struct mlx5e_channel *c = rq->channel;
a43b25da 739 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 740
741 void *in;
742 void *rqc;
743 int inlen;
744 int err;
745
746 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
747 in = mlx5_vzalloc(inlen);
748 if (!in)
749 return -ENOMEM;
750
751 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
752
753 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
754 MLX5_SET(rqc, rqc, state, next_state);
755
7db22ffb 756 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 757
758 kvfree(in);
759
760 return err;
761}
762
36350114
GP		 763static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
764{
765 struct mlx5e_channel *c = rq->channel;
a43b25da 766 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 767 void *in;
768 void *rqc;
769 int inlen;
770 int err;
771
772 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
773 in = mlx5_vzalloc(inlen);
774 if (!in)
775 return -ENOMEM;
776
777 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
778
779 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 780 MLX5_SET64(modify_rq_in, in, modify_bitmask,
781 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 782 MLX5_SET(rqc, rqc, vsd, vsd);
783 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
784
785 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
786
787 kvfree(in);
788
789 return err;
790}
791
3b77235b 792static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 793{
a43b25da 794 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 795}
796
797static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
798{
01c196a2 799 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 800 struct mlx5e_channel *c = rq->channel;
a43b25da 801
f62b8bb8 802 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 803 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 804
01c196a2 805 while (time_before(jiffies, exp_time)) {
6a9764ef 806 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 807 return 0;
808
809 msleep(20);
810 }
811
a43b25da 812 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 813 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 814 return -ETIMEDOUT;
815}
816
f2fde18c
SM		 817static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
818{
819 struct mlx5_wq_ll *wq = &rq->wq;
820 struct mlx5e_rx_wqe *wqe;
821 __be16 wqe_ix_be;
822 u16 wqe_ix;
823
8484f9ed
SM		 824 /* UMR WQE (if in progress) is always at wq->head */
825 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 826 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 827
f2fde18c
SM		 828 while (!mlx5_wq_ll_is_empty(wq)) {
829 wqe_ix_be = *wq->tail_next;
830 wqe_ix = be16_to_cpu(wqe_ix_be);
831 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
832 rq->dealloc_wqe(rq, wqe_ix);
833 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
834 &wqe->next.next_wqe_index);
835 }
836}
837
f62b8bb8 838static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 839 struct mlx5e_params *params,
f62b8bb8
AV		 840 struct mlx5e_rq_param *param,
841 struct mlx5e_rq *rq)
842{
843 int err;
844
6a9764ef 845 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 846 if (err)
847 return err;
848
3b77235b 849 err = mlx5e_create_rq(rq, param);
f62b8bb8 850 if (err)
3b77235b 851 goto err_free_rq;
f62b8bb8 852
36350114 853 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 854 if (err)
3b77235b 855 goto err_destroy_rq;
f62b8bb8 856
6a9764ef 857 if (params->rx_am_enabled)
cb3c7fd4
GR		 858 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
859
f62b8bb8
AV		 860 return 0;
861
f62b8bb8
AV		 862err_destroy_rq:
863 mlx5e_destroy_rq(rq);
3b77235b
SM		 864err_free_rq:
865 mlx5e_free_rq(rq);
f62b8bb8
AV		 866
867 return err;
868}
869
acc6c595
SM		 870static void mlx5e_activate_rq(struct mlx5e_rq *rq)
871{
872 struct mlx5e_icosq *sq = &rq->channel->icosq;
873 u16 pi = sq->pc & sq->wq.sz_m1;
874 struct mlx5e_tx_wqe *nopwqe;
875
876 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
877 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
878 sq->db.ico_wqe[pi].num_wqebbs = 1;
879 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
880 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
881}
882
883static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 884{
c0f1147d 885 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 886 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 887}
cb3c7fd4 888
acc6c595
SM		 889static void mlx5e_close_rq(struct mlx5e_rq *rq)
890{
891 cancel_work_sync(&rq->am.work);
f62b8bb8 892 mlx5e_destroy_rq(rq);
3b77235b
SM		 893 mlx5e_free_rx_descs(rq);
894 mlx5e_free_rq(rq);
f62b8bb8
AV		 895}
896
31391048 897static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 898{
31391048 899 kfree(sq->db.di);
b5503b99
SM		 900}
901
31391048 902static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 903{
904 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
905
31391048 906 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 907 GFP_KERNEL, numa);
31391048
SM		 908 if (!sq->db.di) {
909 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 910 return -ENOMEM;
911 }
912
913 return 0;
914}
915
31391048 916static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 917 struct mlx5e_params *params,
31391048
SM		 918 struct mlx5e_sq_param *param,
919 struct mlx5e_xdpsq *sq)
920{
921 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 922 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 923 int err;
924
925 sq->pdev = c->pdev;
926 sq->mkey_be = c->mkey_be;
927 sq->channel = c;
928 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 929 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 930
931 param->wq.db_numa_node = cpu_to_node(c->cpu);
932 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
933 if (err)
934 return err;
935 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
936
937 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
938 if (err)
939 goto err_sq_wq_destroy;
940
941 return 0;
942
943err_sq_wq_destroy:
944 mlx5_wq_destroy(&sq->wq_ctrl);
945
946 return err;
947}
948
949static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
950{
951 mlx5e_free_xdpsq_db(sq);
952 mlx5_wq_destroy(&sq->wq_ctrl);
953}
954
955static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 956{
f10b7cc7 957 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 958}
959
31391048 960static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 961{
962 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
963
964 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
965 GFP_KERNEL, numa);
966 if (!sq->db.ico_wqe)
967 return -ENOMEM;
968
969 return 0;
970}
971
31391048 972static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 973 struct mlx5e_sq_param *param,
974 struct mlx5e_icosq *sq)
f10b7cc7 975{
31391048 976 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 977 struct mlx5_core_dev *mdev = c->mdev;
31391048 978 int err;
f10b7cc7 979
31391048
SM		 980 sq->pdev = c->pdev;
981 sq->mkey_be = c->mkey_be;
982 sq->channel = c;
983 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 984
31391048
SM		 985 param->wq.db_numa_node = cpu_to_node(c->cpu);
986 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
987 if (err)
988 return err;
989 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 990
31391048
SM		 991 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
992 if (err)
993 goto err_sq_wq_destroy;
994
995 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 996
997 return 0;
31391048
SM		 998
999err_sq_wq_destroy:
1000 mlx5_wq_destroy(&sq->wq_ctrl);
1001
1002 return err;
f62b8bb8
AV		 1003}
1004
31391048 1005static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1006{
31391048
SM		 1007 mlx5e_free_icosq_db(sq);
1008 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1009}
1010
31391048 1011static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1012{
31391048
SM		 1013 kfree(sq->db.wqe_info);
1014 kfree(sq->db.dma_fifo);
1015 kfree(sq->db.skb);
f10b7cc7
SM		 1016}
1017
31391048 1018static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1019{
31391048
SM		 1020 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1021 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1022
1023 sq->db.skb = kzalloc_node(wq_sz * sizeof(*sq->db.skb),
1024 GFP_KERNEL, numa);
1025 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1026 GFP_KERNEL, numa);
1027 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1028 GFP_KERNEL, numa);
1029 if (!sq->db.skb || !sq->db.dma_fifo || !sq->db.wqe_info) {
1030 mlx5e_free_txqsq_db(sq);
1031 return -ENOMEM;
b5503b99 1032 }
31391048
SM		 1033
1034 sq->dma_fifo_mask = df_sz - 1;
1035
1036 return 0;
b5503b99
SM		 1037}
1038
31391048 1039static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1040 int txq_ix,
6a9764ef 1041 struct mlx5e_params *params,
31391048
SM		 1042 struct mlx5e_sq_param *param,
1043 struct mlx5e_txqsq *sq)
f62b8bb8 1044{
31391048 1045 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1046 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1047 int err;
1048
f10b7cc7 1049 sq->pdev = c->pdev;
a43b25da 1050 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1051 sq->mkey_be = c->mkey_be;
1052 sq->channel = c;
acc6c595 1053 sq->txq_ix = txq_ix;
aff26157 1054 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1055 sq->max_inline = params->tx_max_inline;
1056 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1057
311c7c71 1058 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1059 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1060 if (err)
aff26157 1061 return err;
31391048 1062 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1063
31391048 1064 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1065 if (err)
f62b8bb8
AV		 1066 goto err_sq_wq_destroy;
1067
31391048 1068 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1069
1070 return 0;
1071
1072err_sq_wq_destroy:
1073 mlx5_wq_destroy(&sq->wq_ctrl);
1074
f62b8bb8
AV		 1075 return err;
1076}
1077
31391048 1078static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1079{
31391048 1080 mlx5e_free_txqsq_db(sq);
f62b8bb8 1081 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1082}
1083
33ad9711
SM		 1084struct mlx5e_create_sq_param {
1085 struct mlx5_wq_ctrl *wq_ctrl;
1086 u32 cqn;
1087 u32 tisn;
1088 u8 tis_lst_sz;
1089 u8 min_inline_mode;
1090};
1091
a43b25da 1092static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1093 struct mlx5e_sq_param *param,
1094 struct mlx5e_create_sq_param *csp,
1095 u32 *sqn)
f62b8bb8 1096{
f62b8bb8
AV		 1097 void *in;
1098 void *sqc;
1099 void *wq;
1100 int inlen;
1101 int err;
1102
1103 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1104 sizeof(u64) * csp->wq_ctrl->buf.npages;
f62b8bb8
AV		 1105 in = mlx5_vzalloc(inlen);
1106 if (!in)
1107 return -ENOMEM;
1108
1109 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1110 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1111
1112 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1113 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1114 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1115 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1116
1117 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1118 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1119
33ad9711 1120 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1121
1122 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1123 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1124 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1125 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1126 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1127
33ad9711 1128 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1129
33ad9711 1130 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1131
1132 kvfree(in);
1133
1134 return err;
1135}
1136
33ad9711
SM		 1137struct mlx5e_modify_sq_param {
1138 int curr_state;
1139 int next_state;
1140 bool rl_update;
1141 int rl_index;
1142};
1143
a43b25da 1144static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1145 struct mlx5e_modify_sq_param *p)
f62b8bb8 1146{
f62b8bb8
AV		 1147 void *in;
1148 void *sqc;
1149 int inlen;
1150 int err;
1151
1152 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1153 in = mlx5_vzalloc(inlen);
1154 if (!in)
1155 return -ENOMEM;
1156
1157 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1158
33ad9711
SM		 1159 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1160 MLX5_SET(sqc, sqc, state, p->next_state);
1161 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1162 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1163 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1164 }
f62b8bb8 1165
33ad9711 1166 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1167
1168 kvfree(in);
1169
1170 return err;
1171}
1172
a43b25da 1173static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1174{
a43b25da 1175 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1176}
1177
a43b25da 1178static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1179 struct mlx5e_sq_param *param,
1180 struct mlx5e_create_sq_param *csp,
1181 u32 *sqn)
f62b8bb8 1182{
33ad9711 1183 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1184 int err;
1185
a43b25da 1186 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1187 if (err)
1188 return err;
1189
1190 msp.curr_state = MLX5_SQC_STATE_RST;
1191 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1192 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1193 if (err)
a43b25da 1194 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1195
1196 return err;
1197}
1198
7f859ecf
SM		 1199static int mlx5e_set_sq_maxrate(struct net_device *dev,
1200 struct mlx5e_txqsq *sq, u32 rate);
1201
31391048 1202static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1203 u32 tisn,
acc6c595 1204 int txq_ix,
6a9764ef 1205 struct mlx5e_params *params,
31391048
SM		 1206 struct mlx5e_sq_param *param,
1207 struct mlx5e_txqsq *sq)
1208{
1209 struct mlx5e_create_sq_param csp = {};
7f859ecf 1210 u32 tx_rate;
f62b8bb8
AV		 1211 int err;
1212
6a9764ef 1213 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1214 if (err)
1215 return err;
1216
a43b25da 1217 csp.tisn = tisn;
31391048 1218 csp.tis_lst_sz = 1;
33ad9711
SM		 1219 csp.cqn = sq->cq.mcq.cqn;
1220 csp.wq_ctrl = &sq->wq_ctrl;
1221 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1222 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1223 if (err)
31391048 1224 goto err_free_txqsq;
f62b8bb8 1225
a43b25da 1226 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1227 if (tx_rate)
a43b25da 1228 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1229
f62b8bb8
AV		 1230 return 0;
1231
31391048 1232err_free_txqsq:
3b77235b 1233 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1234 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1235
1236 return err;
1237}
1238
acc6c595
SM		 1239static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1240{
a43b25da 1241 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1242 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1243 netdev_tx_reset_queue(sq->txq);
1244 netif_tx_start_queue(sq->txq);
1245}
1246
f62b8bb8
AV		 1247static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1248{
1249 __netif_tx_lock_bh(txq);
1250 netif_tx_stop_queue(txq);
1251 __netif_tx_unlock_bh(txq);
1252}
1253
acc6c595 1254static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1255{
33ad9711 1256 struct mlx5e_channel *c = sq->channel;
33ad9711 1257
c0f1147d 1258 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1259 /* prevent netif_tx_wake_queue */
33ad9711 1260 napi_synchronize(&c->napi);
29429f33 1261
31391048 1262 netif_tx_disable_queue(sq->txq);
f62b8bb8 1263
31391048
SM		 1264 /* last doorbell out, godspeed .. */
1265 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1266 struct mlx5e_tx_wqe *nop;
864b2d71 1267
31391048
SM		 1268 sq->db.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1269 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1270 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1271 }
acc6c595
SM		 1272}
1273
1274static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1275{
1276 struct mlx5e_channel *c = sq->channel;
a43b25da 1277 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1278
a43b25da 1279 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1280 if (sq->rate_limit)
1281 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1282 mlx5e_free_txqsq_descs(sq);
1283 mlx5e_free_txqsq(sq);
1284}
1285
1286static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1287 struct mlx5e_params *params,
31391048
SM		 1288 struct mlx5e_sq_param *param,
1289 struct mlx5e_icosq *sq)
1290{
1291 struct mlx5e_create_sq_param csp = {};
1292 int err;
1293
6a9764ef 1294 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1295 if (err)
1296 return err;
1297
1298 csp.cqn = sq->cq.mcq.cqn;
1299 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1300 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1301 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1302 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1303 if (err)
1304 goto err_free_icosq;
1305
1306 return 0;
1307
1308err_free_icosq:
1309 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1310 mlx5e_free_icosq(sq);
1311
1312 return err;
1313}
1314
1315static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1316{
1317 struct mlx5e_channel *c = sq->channel;
1318
1319 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1320 napi_synchronize(&c->napi);
1321
a43b25da 1322 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1323 mlx5e_free_icosq(sq);
1324}
1325
1326static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1327 struct mlx5e_params *params,
31391048
SM		 1328 struct mlx5e_sq_param *param,
1329 struct mlx5e_xdpsq *sq)
1330{
1331 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1332 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1333 unsigned int inline_hdr_sz = 0;
1334 int err;
1335 int i;
1336
6a9764ef 1337 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1338 if (err)
1339 return err;
1340
1341 csp.tis_lst_sz = 1;
a43b25da 1342 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1343 csp.cqn = sq->cq.mcq.cqn;
1344 csp.wq_ctrl = &sq->wq_ctrl;
1345 csp.min_inline_mode = sq->min_inline_mode;
1346 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1347 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1348 if (err)
1349 goto err_free_xdpsq;
1350
1351 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1352 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1353 ds_cnt++;
1354 }
1355
1356 /* Pre initialize fixed WQE fields */
1357 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1358 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1359 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1360 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1361 struct mlx5_wqe_data_seg *dseg;
1362
1363 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1364 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1365
1366 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1367 dseg->lkey = sq->mkey_be;
1368 }
1369
1370 return 0;
1371
1372err_free_xdpsq:
1373 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1374 mlx5e_free_xdpsq(sq);
1375
1376 return err;
1377}
1378
1379static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1380{
1381 struct mlx5e_channel *c = sq->channel;
1382
1383 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1384 napi_synchronize(&c->napi);
1385
a43b25da 1386 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1387 mlx5e_free_xdpsq_descs(sq);
1388 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1389}
1390
3b77235b
SM		 1391static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1392 struct mlx5e_cq_param *param,
1393 struct mlx5e_cq *cq)
f62b8bb8 1394{
a43b25da 1395 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1396 struct mlx5_core_cq *mcq = &cq->mcq;
1397 int eqn_not_used;
0b6e26ce 1398 unsigned int irqn;
f62b8bb8
AV		 1399 int err;
1400 u32 i;
1401
311c7c71
SM		 1402 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1403 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1404 param->eq_ix = c->ix;
1405
1406 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1407 &cq->wq_ctrl);
1408 if (err)
1409 return err;
1410
1411 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1412
1413 cq->napi = &c->napi;
1414
1415 mcq->cqe_sz = 64;
1416 mcq->set_ci_db = cq->wq_ctrl.db.db;
1417 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1418 *mcq->set_ci_db = 0;
1419 *mcq->arm_db = 0;
1420 mcq->vector = param->eq_ix;
1421 mcq->comp = mlx5e_completion_event;
1422 mcq->event = mlx5e_cq_error_event;
1423 mcq->irqn = irqn;
f62b8bb8
AV		 1424
1425 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1426 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1427
1428 cqe->op_own = 0xf1;
1429 }
1430
1431 cq->channel = c;
a43b25da 1432 cq->mdev = mdev;
f62b8bb8
AV		 1433
1434 return 0;
1435}
1436
3b77235b 1437static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1438{
1c1b5228 1439 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1440}
1441
3b77235b 1442static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1443{
a43b25da 1444 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1445 struct mlx5_core_cq *mcq = &cq->mcq;
1446
1447 void *in;
1448 void *cqc;
1449 int inlen;
0b6e26ce 1450 unsigned int irqn_not_used;
f62b8bb8
AV		 1451 int eqn;
1452 int err;
1453
1454 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1455 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1456 in = mlx5_vzalloc(inlen);
1457 if (!in)
1458 return -ENOMEM;
1459
1460 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1461
1462 memcpy(cqc, param->cqc, sizeof(param->cqc));
1463
1c1b5228
TT		 1464 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1465 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1466
1467 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1468
9908aa29 1469 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1470 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1471 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1472 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1473 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1474 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1475
1476 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1477
1478 kvfree(in);
1479
1480 if (err)
1481 return err;
1482
1483 mlx5e_cq_arm(cq);
1484
1485 return 0;
1486}
1487
3b77235b 1488static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1489{
a43b25da 1490 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1491}
1492
1493static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1494 struct mlx5e_cq_moder moder,
f62b8bb8 1495 struct mlx5e_cq_param *param,
6a9764ef 1496 struct mlx5e_cq *cq)
f62b8bb8 1497{
a43b25da 1498 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1499 int err;
f62b8bb8 1500
3b77235b 1501 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1502 if (err)
1503 return err;
1504
3b77235b 1505 err = mlx5e_create_cq(cq, param);
f62b8bb8 1506 if (err)
3b77235b 1507 goto err_free_cq;
f62b8bb8 1508
7524a5d8 1509 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1510 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1511 return 0;
1512
3b77235b
SM		 1513err_free_cq:
1514 mlx5e_free_cq(cq);
f62b8bb8
AV		 1515
1516 return err;
1517}
1518
1519static void mlx5e_close_cq(struct mlx5e_cq *cq)
1520{
f62b8bb8 1521 mlx5e_destroy_cq(cq);
3b77235b 1522 mlx5e_free_cq(cq);
f62b8bb8
AV		 1523}
1524
1525static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1526{
1527 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1528}
1529
1530static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1531 struct mlx5e_params *params,
f62b8bb8
AV		 1532 struct mlx5e_channel_param *cparam)
1533{
f62b8bb8
AV		 1534 int err;
1535 int tc;
1536
1537 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1538 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1539 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1540 if (err)
1541 goto err_close_tx_cqs;
f62b8bb8
AV		 1542 }
1543
1544 return 0;
1545
1546err_close_tx_cqs:
1547 for (tc--; tc >= 0; tc--)
1548 mlx5e_close_cq(&c->sq[tc].cq);
1549
1550 return err;
1551}
1552
1553static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1554{
1555 int tc;
1556
1557 for (tc = 0; tc < c->num_tc; tc++)
1558 mlx5e_close_cq(&c->sq[tc].cq);
1559}
1560
1561static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1562 struct mlx5e_params *params,
f62b8bb8
AV		 1563 struct mlx5e_channel_param *cparam)
1564{
1565 int err;
1566 int tc;
1567
6a9764ef
SM		 1568 for (tc = 0; tc < params->num_tc; tc++) {
1569 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1570
a43b25da
SM		 1571 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1572 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1573 if (err)
1574 goto err_close_sqs;
1575 }
1576
1577 return 0;
1578
1579err_close_sqs:
1580 for (tc--; tc >= 0; tc--)
31391048 1581 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1582
1583 return err;
1584}
1585
1586static void mlx5e_close_sqs(struct mlx5e_channel *c)
1587{
1588 int tc;
1589
1590 for (tc = 0; tc < c->num_tc; tc++)
31391048 1591 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1592}
1593
507f0c81 1594static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1595 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1596{
1597 struct mlx5e_priv *priv = netdev_priv(dev);
1598 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1599 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1600 u16 rl_index = 0;
1601 int err;
1602
1603 if (rate == sq->rate_limit)
1604 /* nothing to do */
1605 return 0;
1606
1607 if (sq->rate_limit)
1608 /* remove current rl index to free space to next ones */
1609 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1610
1611 sq->rate_limit = 0;
1612
1613 if (rate) {
1614 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1615 if (err) {
1616 netdev_err(dev, "Failed configuring rate %u: %d\n",
1617 rate, err);
1618 return err;
1619 }
1620 }
1621
33ad9711
SM		 1622 msp.curr_state = MLX5_SQC_STATE_RDY;
1623 msp.next_state = MLX5_SQC_STATE_RDY;
1624 msp.rl_index = rl_index;
1625 msp.rl_update = true;
a43b25da 1626 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1627 if (err) {
1628 netdev_err(dev, "Failed configuring rate %u: %d\n",
1629 rate, err);
1630 /* remove the rate from the table */
1631 if (rate)
1632 mlx5_rl_remove_rate(mdev, rate);
1633 return err;
1634 }
1635
1636 sq->rate_limit = rate;
1637 return 0;
1638}
1639
1640static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1641{
1642 struct mlx5e_priv *priv = netdev_priv(dev);
1643 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1644 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1645 int err = 0;
1646
1647 if (!mlx5_rl_is_supported(mdev)) {
1648 netdev_err(dev, "Rate limiting is not supported on this device\n");
1649 return -EINVAL;
1650 }
1651
1652 /* rate is given in Mb/sec, HW config is in Kb/sec */
1653 rate = rate << 10;
1654
1655 /* Check whether rate in valid range, 0 is always valid */
1656 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1657 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1658 return -ERANGE;
1659 }
1660
1661 mutex_lock(&priv->state_lock);
1662 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1663 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1664 if (!err)
1665 priv->tx_rates[index] = rate;
1666 mutex_unlock(&priv->state_lock);
1667
1668 return err;
1669}
1670
b4e029da
KH		 1671static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1672{
1673 return is_kdump_kernel() ?
1674 MLX5E_MIN_NUM_CHANNELS :
1675 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1676 MLX5E_MAX_NUM_CHANNELS);
1677}
1678
f62b8bb8 1679static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1680 struct mlx5e_params *params,
f62b8bb8
AV		 1681 struct mlx5e_channel_param *cparam,
1682 struct mlx5e_channel **cp)
1683{
6a9764ef 1684 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1685 struct net_device *netdev = priv->netdev;
1686 int cpu = mlx5e_get_cpu(priv, ix);
1687 struct mlx5e_channel *c;
1688 int err;
1689
1690 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1691 if (!c)
1692 return -ENOMEM;
1693
1694 c->priv = priv;
a43b25da
SM		 1695 c->mdev = priv->mdev;
1696 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1697 c->ix = ix;
1698 c->cpu = cpu;
1699 c->pdev = &priv->mdev->pdev->dev;
1700 c->netdev = priv->netdev;
b50d292b 1701 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1702 c->num_tc = params->num_tc;
1703 c->xdp = !!params->xdp_prog;
cb3c7fd4 1704
f62b8bb8
AV		 1705 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1706
6a9764ef 1707 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1708 if (err)
1709 goto err_napi_del;
1710
6a9764ef 1711 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1712 if (err)
1713 goto err_close_icosq_cq;
1714
6a9764ef 1715 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1716 if (err)
1717 goto err_close_tx_cqs;
f62b8bb8 1718
d7a0ecab 1719 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1720 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1721 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1722 if (err)
1723 goto err_close_rx_cq;
1724
f62b8bb8
AV		 1725 napi_enable(&c->napi);
1726
6a9764ef 1727 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1728 if (err)
1729 goto err_disable_napi;
1730
6a9764ef 1731 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1732 if (err)
1733 goto err_close_icosq;
1734
6a9764ef 1735 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1736 if (err)
1737 goto err_close_sqs;
b5503b99 1738
6a9764ef 1739 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1740 if (err)
b5503b99 1741 goto err_close_xdp_sq;
f62b8bb8 1742
f62b8bb8
AV		 1743 *cp = c;
1744
1745 return 0;
b5503b99 1746err_close_xdp_sq:
d7a0ecab 1747 if (c->xdp)
31391048 1748 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1749
1750err_close_sqs:
1751 mlx5e_close_sqs(c);
1752
d3c9bc27 1753err_close_icosq:
31391048 1754 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1755
f62b8bb8
AV		 1756err_disable_napi:
1757 napi_disable(&c->napi);
d7a0ecab 1758 if (c->xdp)
31871f87 1759 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1760
1761err_close_rx_cq:
f62b8bb8
AV		 1762 mlx5e_close_cq(&c->rq.cq);
1763
1764err_close_tx_cqs:
1765 mlx5e_close_tx_cqs(c);
1766
d3c9bc27
TT		 1767err_close_icosq_cq:
1768 mlx5e_close_cq(&c->icosq.cq);
1769
f62b8bb8
AV		 1770err_napi_del:
1771 netif_napi_del(&c->napi);
1772 kfree(c);
1773
1774 return err;
1775}
1776
acc6c595
SM		 1777static void mlx5e_activate_channel(struct mlx5e_channel *c)
1778{
1779 int tc;
1780
1781 for (tc = 0; tc < c->num_tc; tc++)
1782 mlx5e_activate_txqsq(&c->sq[tc]);
1783 mlx5e_activate_rq(&c->rq);
a43b25da 1784 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1785}
1786
1787static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1788{
1789 int tc;
1790
1791 mlx5e_deactivate_rq(&c->rq);
1792 for (tc = 0; tc < c->num_tc; tc++)
1793 mlx5e_deactivate_txqsq(&c->sq[tc]);
1794}
1795
f62b8bb8
AV		 1796static void mlx5e_close_channel(struct mlx5e_channel *c)
1797{
1798 mlx5e_close_rq(&c->rq);
b5503b99 1799 if (c->xdp)
31391048 1800 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1801 mlx5e_close_sqs(c);
31391048 1802 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1803 napi_disable(&c->napi);
b5503b99 1804 if (c->xdp)
31871f87 1805 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1806 mlx5e_close_cq(&c->rq.cq);
1807 mlx5e_close_tx_cqs(c);
d3c9bc27 1808 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1809 netif_napi_del(&c->napi);
7ae92ae5 1810
f62b8bb8
AV		 1811 kfree(c);
1812}
1813
1814static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1815 struct mlx5e_params *params,
f62b8bb8
AV		 1816 struct mlx5e_rq_param *param)
1817{
1818 void *rqc = param->rqc;
1819 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1820
6a9764ef 1821 switch (params->rq_wq_type) {
461017cb 1822 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1823 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1824 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1825 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1826 break;
1827 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1828 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1829 }
1830
f62b8bb8
AV		 1831 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1832 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1833 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1834 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1835 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1836 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
f62b8bb8 1837
311c7c71 1838 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1839 param->wq.linear = 1;
1840}
1841
556dd1b9
TT		 1842static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1843{
1844 void *rqc = param->rqc;
1845 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1846
1847 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1848 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1849}
1850
d3c9bc27
TT		 1851static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1852 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1853{
1854 void *sqc = param->sqc;
1855 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1856
f62b8bb8 1857 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1858 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1859
311c7c71 1860 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1861}
1862
1863static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1864 struct mlx5e_params *params,
d3c9bc27
TT		 1865 struct mlx5e_sq_param *param)
1866{
1867 void *sqc = param->sqc;
1868 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1869
1870 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1871 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1872}
1873
1874static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1875 struct mlx5e_cq_param *param)
1876{
1877 void *cqc = param->cqc;
1878
30aa60b3 1879 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1880}
1881
1882static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1883 struct mlx5e_params *params,
f62b8bb8
AV		 1884 struct mlx5e_cq_param *param)
1885{
1886 void *cqc = param->cqc;
461017cb 1887 u8 log_cq_size;
f62b8bb8 1888
6a9764ef 1889 switch (params->rq_wq_type) {
461017cb 1890 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1891 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1892 break;
1893 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1894 log_cq_size = params->log_rq_size;
461017cb
TT		 1895 }
1896
1897 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1898 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1899 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1900 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1901 }
f62b8bb8
AV		 1902
1903 mlx5e_build_common_cq_param(priv, param);
9908aa29 1904
6a9764ef
SM		 1905 if (params->rx_am_enabled)
1906 params->rx_cq_moderation =
1907 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
f62b8bb8
AV		 1908}
1909
1910static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1911 struct mlx5e_params *params,
f62b8bb8
AV		 1912 struct mlx5e_cq_param *param)
1913{
1914 void *cqc = param->cqc;
1915
6a9764ef 1916 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1917
1918 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1919
1920 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1921}
1922
d3c9bc27 1923static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1924 u8 log_wq_size,
1925 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1926{
1927 void *cqc = param->cqc;
1928
1929 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1930
1931 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1932
1933 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1934}
1935
1936static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1937 u8 log_wq_size,
1938 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1939{
1940 void *sqc = param->sqc;
1941 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1942
1943 mlx5e_build_sq_param_common(priv, param);
1944
1945 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1946 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1947}
1948
b5503b99 1949static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1950 struct mlx5e_params *params,
b5503b99
SM		 1951 struct mlx5e_sq_param *param)
1952{
1953 void *sqc = param->sqc;
1954 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1955
1956 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1957 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1958}
1959
6a9764ef
SM		 1960static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1961 struct mlx5e_params *params,
1962 struct mlx5e_channel_param *cparam)
f62b8bb8 1963{
bc77b240 1964 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1965
6a9764ef
SM		 1966 mlx5e_build_rq_param(priv, params, &cparam->rq);
1967 mlx5e_build_sq_param(priv, params, &cparam->sq);
1968 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1969 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
1970 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
1971 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
1972 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 1973}
1974
55c2503d
SM		 1975int mlx5e_open_channels(struct mlx5e_priv *priv,
1976 struct mlx5e_channels *chs)
f62b8bb8 1977{
6b87663f 1978 struct mlx5e_channel_param *cparam;
03289b88 1979 int err = -ENOMEM;
f62b8bb8 1980 int i;
f62b8bb8 1981
6a9764ef 1982 chs->num = chs->params.num_channels;
03289b88 1983
ff9c852f 1984 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 1985 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 1986 if (!chs->c || !cparam)
1987 goto err_free;
f62b8bb8 1988
6a9764ef 1989 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 1990 for (i = 0; i < chs->num; i++) {
6a9764ef 1991 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 1992 if (err)
1993 goto err_close_channels;
1994 }
1995
6b87663f 1996 kfree(cparam);
f62b8bb8
AV		 1997 return 0;
1998
1999err_close_channels:
2000 for (i--; i >= 0; i--)
ff9c852f 2001 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2002
acc6c595 2003err_free:
ff9c852f 2004 kfree(chs->c);
6b87663f 2005 kfree(cparam);
ff9c852f 2006 chs->num = 0;
f62b8bb8
AV		 2007 return err;
2008}
2009
acc6c595 2010static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2011{
2012 int i;
2013
acc6c595
SM		 2014 for (i = 0; i < chs->num; i++)
2015 mlx5e_activate_channel(chs->c[i]);
2016}
2017
2018static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2019{
2020 int err = 0;
2021 int i;
2022
2023 for (i = 0; i < chs->num; i++) {
2024 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2025 if (err)
2026 break;
2027 }
2028
2029 return err;
2030}
2031
2032static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2033{
2034 int i;
2035
2036 for (i = 0; i < chs->num; i++)
2037 mlx5e_deactivate_channel(chs->c[i]);
2038}
2039
55c2503d 2040void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2041{
2042 int i;
c3b7c5c9 2043
ff9c852f
SM		 2044 for (i = 0; i < chs->num; i++)
2045 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2046
ff9c852f
SM		 2047 kfree(chs->c);
2048 chs->num = 0;
f62b8bb8
AV		 2049}
2050
a5f97fee
SM		 2051static int
2052mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2053{
2054 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2055 void *rqtc;
2056 int inlen;
2057 int err;
1da36696 2058 u32 *in;
a5f97fee 2059 int i;
f62b8bb8 2060
f62b8bb8
AV		 2061 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2062 in = mlx5_vzalloc(inlen);
2063 if (!in)
2064 return -ENOMEM;
2065
2066 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2067
2068 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2069 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2070
a5f97fee
SM		 2071 for (i = 0; i < sz; i++)
2072 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2073
398f3351
HHZ		 2074 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2075 if (!err)
2076 rqt->enabled = true;
f62b8bb8
AV		 2077
2078 kvfree(in);
1da36696
TT		 2079 return err;
2080}
2081
cb67b832 2082void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2083{
398f3351
HHZ		 2084 rqt->enabled = false;
2085 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2086}
2087
6bfd390b
HHZ		 2088static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
2089{
2090 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2091
a5f97fee 2092 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
6bfd390b
HHZ		 2093}
2094
cb67b832 2095int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2096{
398f3351 2097 struct mlx5e_rqt *rqt;
1da36696
TT		 2098 int err;
2099 int ix;
2100
6bfd390b 2101 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2102 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2103 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2104 if (err)
2105 goto err_destroy_rqts;
2106 }
2107
2108 return 0;
2109
2110err_destroy_rqts:
2111 for (ix--; ix >= 0; ix--)
398f3351 2112 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2113
f62b8bb8
AV		 2114 return err;
2115}
2116
a5f97fee
SM		 2117static int mlx5e_rx_hash_fn(int hfunc)
2118{
2119 return (hfunc == ETH_RSS_HASH_TOP) ?
2120 MLX5_RX_HASH_FN_TOEPLITZ :
2121 MLX5_RX_HASH_FN_INVERTED_XOR8;
2122}
2123
2124static int mlx5e_bits_invert(unsigned long a, int size)
2125{
2126 int inv = 0;
2127 int i;
2128
2129 for (i = 0; i < size; i++)
2130 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2131
2132 return inv;
2133}
2134
2135static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2136 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2137{
2138 int i;
2139
2140 for (i = 0; i < sz; i++) {
2141 u32 rqn;
2142
2143 if (rrp.is_rss) {
2144 int ix = i;
2145
2146 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2147 ix = mlx5e_bits_invert(i, ilog2(sz));
2148
6a9764ef 2149 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2150 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2151 } else {
2152 rqn = rrp.rqn;
2153 }
2154 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2155 }
2156}
2157
2158int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2159 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2160{
2161 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2162 void *rqtc;
2163 int inlen;
1da36696 2164 u32 *in;
5c50368f
AS		 2165 int err;
2166
5c50368f
AS		 2167 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2168 in = mlx5_vzalloc(inlen);
2169 if (!in)
2170 return -ENOMEM;
2171
2172 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2173
2174 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2175 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2176 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2177 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2178
2179 kvfree(in);
5c50368f
AS		 2180 return err;
2181}
2182
a5f97fee
SM		 2183static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2184 struct mlx5e_redirect_rqt_param rrp)
2185{
2186 if (!rrp.is_rss)
2187 return rrp.rqn;
2188
2189 if (ix >= rrp.rss.channels->num)
2190 return priv->drop_rq.rqn;
2191
2192 return rrp.rss.channels->c[ix]->rq.rqn;
2193}
2194
2195static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2196 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2197{
1da36696
TT		 2198 u32 rqtn;
2199 int ix;
2200
398f3351 2201 if (priv->indir_rqt.enabled) {
a5f97fee 2202 /* RSS RQ table */
398f3351 2203 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2204 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2205 }
2206
a5f97fee
SM		 2207 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2208 struct mlx5e_redirect_rqt_param direct_rrp = {
2209 .is_rss = false,
2210 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2211 };
2212
2213 /* Direct RQ Tables */
398f3351
HHZ		 2214 if (!priv->direct_tir[ix].rqt.enabled)
2215 continue;
a5f97fee 2216
398f3351 2217 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2218 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2219 }
40ab6a6e
AS		 2220}
2221
a5f97fee
SM		 2222static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2223 struct mlx5e_channels *chs)
2224{
2225 struct mlx5e_redirect_rqt_param rrp = {
2226 .is_rss = true,
2227 .rss.channels = chs,
6a9764ef 2228 .rss.hfunc = chs->params.rss_hfunc
a5f97fee
SM		 2229 };
2230
2231 mlx5e_redirect_rqts(priv, rrp);
2232}
2233
2234static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2235{
2236 struct mlx5e_redirect_rqt_param drop_rrp = {
2237 .is_rss = false,
2238 .rqn = priv->drop_rq.rqn
2239 };
2240
2241 mlx5e_redirect_rqts(priv, drop_rrp);
2242}
2243
6a9764ef 2244static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2245{
6a9764ef 2246 if (!params->lro_en)
5c50368f
AS		 2247 return;
2248
2249#define ROUGH_MAX_L2_L3_HDR_SZ 256
2250
2251 MLX5_SET(tirc, tirc, lro_enable_mask,
2252 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2253 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2254 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2255 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2256 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2257}
2258
6a9764ef
SM		 2259void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2260 enum mlx5e_traffic_types tt,
2261 void *tirc)
bdfc028d 2262{
a100ff3e
GP		 2263 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2264
2265#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2266 MLX5_HASH_FIELD_SEL_DST_IP)
2267
2268#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2269 MLX5_HASH_FIELD_SEL_DST_IP |\
2270 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2271 MLX5_HASH_FIELD_SEL_L4_DPORT)
2272
2273#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2274 MLX5_HASH_FIELD_SEL_DST_IP |\
2275 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2276
6a9764ef
SM		 2277 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2278 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2279 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2280 rx_hash_toeplitz_key);
2281 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2282 rx_hash_toeplitz_key);
2283
2284 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2285 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2286 }
a100ff3e
GP		 2287
2288 switch (tt) {
2289 case MLX5E_TT_IPV4_TCP:
2290 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2291 MLX5_L3_PROT_TYPE_IPV4);
2292 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2293 MLX5_L4_PROT_TYPE_TCP);
2294 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2295 MLX5_HASH_IP_L4PORTS);
2296 break;
2297
2298 case MLX5E_TT_IPV6_TCP:
2299 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2300 MLX5_L3_PROT_TYPE_IPV6);
2301 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2302 MLX5_L4_PROT_TYPE_TCP);
2303 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2304 MLX5_HASH_IP_L4PORTS);
2305 break;
2306
2307 case MLX5E_TT_IPV4_UDP:
2308 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2309 MLX5_L3_PROT_TYPE_IPV4);
2310 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2311 MLX5_L4_PROT_TYPE_UDP);
2312 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2313 MLX5_HASH_IP_L4PORTS);
2314 break;
2315
2316 case MLX5E_TT_IPV6_UDP:
2317 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2318 MLX5_L3_PROT_TYPE_IPV6);
2319 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2320 MLX5_L4_PROT_TYPE_UDP);
2321 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2322 MLX5_HASH_IP_L4PORTS);
2323 break;
2324
2325 case MLX5E_TT_IPV4_IPSEC_AH:
2326 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2327 MLX5_L3_PROT_TYPE_IPV4);
2328 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2329 MLX5_HASH_IP_IPSEC_SPI);
2330 break;
2331
2332 case MLX5E_TT_IPV6_IPSEC_AH:
2333 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2334 MLX5_L3_PROT_TYPE_IPV6);
2335 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2336 MLX5_HASH_IP_IPSEC_SPI);
2337 break;
2338
2339 case MLX5E_TT_IPV4_IPSEC_ESP:
2340 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2341 MLX5_L3_PROT_TYPE_IPV4);
2342 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2343 MLX5_HASH_IP_IPSEC_SPI);
2344 break;
2345
2346 case MLX5E_TT_IPV6_IPSEC_ESP:
2347 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2348 MLX5_L3_PROT_TYPE_IPV6);
2349 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2350 MLX5_HASH_IP_IPSEC_SPI);
2351 break;
2352
2353 case MLX5E_TT_IPV4:
2354 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2355 MLX5_L3_PROT_TYPE_IPV4);
2356 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2357 MLX5_HASH_IP);
2358 break;
2359
2360 case MLX5E_TT_IPV6:
2361 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2362 MLX5_L3_PROT_TYPE_IPV6);
2363 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2364 MLX5_HASH_IP);
2365 break;
2366 default:
2367 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2368 }
bdfc028d
TT		 2369}
2370
ab0394fe 2371static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2372{
2373 struct mlx5_core_dev *mdev = priv->mdev;
2374
2375 void *in;
2376 void *tirc;
2377 int inlen;
2378 int err;
ab0394fe 2379 int tt;
1da36696 2380 int ix;
5c50368f
AS		 2381
2382 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2383 in = mlx5_vzalloc(inlen);
2384 if (!in)
2385 return -ENOMEM;
2386
2387 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2388 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2389
6a9764ef 2390 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2391
1da36696 2392 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2393 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2394 inlen);
ab0394fe 2395 if (err)
1da36696 2396 goto free_in;
ab0394fe 2397 }
5c50368f 2398
6bfd390b 2399 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2400 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2401 in, inlen);
2402 if (err)
2403 goto free_in;
2404 }
2405
2406free_in:
5c50368f
AS		 2407 kvfree(in);
2408
2409 return err;
2410}
2411
cd255eff 2412static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2413{
40ab6a6e 2414 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2415 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2416 int err;
2417
cd255eff 2418 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2419 if (err)
2420 return err;
2421
cd255eff
SM		 2422 /* Update vport context MTU */
2423 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2424 return 0;
2425}
40ab6a6e 2426
cd255eff
SM		 2427static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2428{
2429 struct mlx5_core_dev *mdev = priv->mdev;
2430 u16 hw_mtu = 0;
2431 int err;
40ab6a6e 2432
cd255eff
SM		 2433 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2434 if (err || !hw_mtu) /* fallback to port oper mtu */
2435 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2436
2437 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2438}
2439
2440static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2441{
2442 struct mlx5e_priv *priv = netdev_priv(netdev);
2443 u16 mtu;
2444 int err;
2445
2446 err = mlx5e_set_mtu(priv, netdev->mtu);
2447 if (err)
2448 return err;
40ab6a6e 2449
cd255eff
SM		 2450 mlx5e_query_mtu(priv, &mtu);
2451 if (mtu != netdev->mtu)
2452 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2453 __func__, mtu, netdev->mtu);
40ab6a6e 2454
cd255eff 2455 netdev->mtu = mtu;
40ab6a6e
AS		 2456 return 0;
2457}
2458
08fb1dac
SM		 2459static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2460{
2461 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2462 int nch = priv->channels.params.num_channels;
2463 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2464 int tc;
2465
2466 netdev_reset_tc(netdev);
2467
2468 if (ntc == 1)
2469 return;
2470
2471 netdev_set_num_tc(netdev, ntc);
2472
7ccdd084
RS		 2473 /* Map netdev TCs to offset 0
2474 * We have our own UP to TXQ mapping for QoS
2475 */
08fb1dac 2476 for (tc = 0; tc < ntc; tc++)
7ccdd084 2477 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2478}
2479
acc6c595
SM		 2480static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2481{
2482 struct mlx5e_channel *c;
2483 struct mlx5e_txqsq *sq;
2484 int i, tc;
2485
2486 for (i = 0; i < priv->channels.num; i++)
2487 for (tc = 0; tc < priv->profile->max_tc; tc++)
2488 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2489
2490 for (i = 0; i < priv->channels.num; i++) {
2491 c = priv->channels.c[i];
2492 for (tc = 0; tc < c->num_tc; tc++) {
2493 sq = &c->sq[tc];
2494 priv->txq2sq[sq->txq_ix] = sq;
2495 }
2496 }
2497}
2498
2499static void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2500{
9008ae07
SM		 2501 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2502 struct net_device *netdev = priv->netdev;
2503
2504 mlx5e_netdev_set_tcs(netdev);
2505 if (netdev->real_num_tx_queues != num_txqs)
2506 netif_set_real_num_tx_queues(netdev, num_txqs);
2507 if (netdev->real_num_rx_queues != priv->channels.num)
2508 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2509
acc6c595
SM		 2510 mlx5e_build_channels_tx_maps(priv);
2511 mlx5e_activate_channels(&priv->channels);
2512 netif_tx_start_all_queues(priv->netdev);
9008ae07
SM		 2513
2514 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2515 mlx5e_add_sqs_fwd_rules(priv);
2516
acc6c595 2517 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2518 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2519}
2520
2521static void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2522{
9008ae07
SM		 2523 mlx5e_redirect_rqts_to_drop(priv);
2524
2525 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2526 mlx5e_remove_sqs_fwd_rules(priv);
2527
acc6c595
SM		 2528 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2529 * polling for inactive tx queues.
2530 */
2531 netif_tx_stop_all_queues(priv->netdev);
2532 netif_tx_disable(priv->netdev);
2533 mlx5e_deactivate_channels(&priv->channels);
2534}
2535
55c2503d
SM		 2536void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2537 struct mlx5e_channels *new_chs)
2538{
2539 struct net_device *netdev = priv->netdev;
2540 int new_num_txqs;
2541
2542 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2543
2544 netif_carrier_off(netdev);
2545
2546 if (new_num_txqs < netdev->real_num_tx_queues)
2547 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2548
2549 mlx5e_deactivate_priv_channels(priv);
2550 mlx5e_close_channels(&priv->channels);
2551
2552 priv->channels = *new_chs;
2553
2554 mlx5e_refresh_tirs(priv, false);
2555 mlx5e_activate_priv_channels(priv);
2556
2557 mlx5e_update_carrier(priv);
2558}
2559
40ab6a6e
AS		 2560int mlx5e_open_locked(struct net_device *netdev)
2561{
2562 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2563 int err;
2564
2565 set_bit(MLX5E_STATE_OPENED, &priv->state);
2566
ff9c852f 2567 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2568 if (err)
343b29f3 2569 goto err_clear_state_opened_flag;
40ab6a6e 2570
b676f653 2571 mlx5e_refresh_tirs(priv, false);
acc6c595 2572 mlx5e_activate_priv_channels(priv);
ce89ef36 2573 mlx5e_update_carrier(priv);
ef9814de 2574 mlx5e_timestamp_init(priv);
be4891af 2575
cb67b832
HHZ		 2576 if (priv->profile->update_stats)
2577 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2578
9b37b07f 2579 return 0;
343b29f3
AS		 2580
2581err_clear_state_opened_flag:
2582 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2583 return err;
40ab6a6e
AS		 2584}
2585
cb67b832 2586int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2587{
2588 struct mlx5e_priv *priv = netdev_priv(netdev);
2589 int err;
2590
2591 mutex_lock(&priv->state_lock);
2592 err = mlx5e_open_locked(netdev);
2593 mutex_unlock(&priv->state_lock);
2594
2595 return err;
2596}
2597
2598int mlx5e_close_locked(struct net_device *netdev)
2599{
2600 struct mlx5e_priv *priv = netdev_priv(netdev);
2601
a1985740
AS		 2602 /* May already be CLOSED in case a previous configuration operation
2603 * (e.g RX/TX queue size change) that involves close&open failed.
2604 */
2605 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2606 return 0;
2607
40ab6a6e
AS		 2608 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2609
ef9814de 2610 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2611 netif_carrier_off(priv->netdev);
acc6c595
SM		 2612 mlx5e_deactivate_priv_channels(priv);
2613 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2614
2615 return 0;
2616}
2617
cb67b832 2618int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2619{
2620 struct mlx5e_priv *priv = netdev_priv(netdev);
2621 int err;
2622
26e59d80
MHY		 2623 if (!netif_device_present(netdev))
2624 return -ENODEV;
2625
40ab6a6e
AS		 2626 mutex_lock(&priv->state_lock);
2627 err = mlx5e_close_locked(netdev);
2628 mutex_unlock(&priv->state_lock);
2629
2630 return err;
2631}
2632
a43b25da 2633static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2634 struct mlx5e_rq *rq,
2635 struct mlx5e_rq_param *param)
40ab6a6e 2636{
40ab6a6e
AS		 2637 void *rqc = param->rqc;
2638 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2639 int err;
2640
2641 param->wq.db_numa_node = param->wq.buf_numa_node;
2642
2643 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2644 &rq->wq_ctrl);
2645 if (err)
2646 return err;
2647
a43b25da 2648 rq->mdev = mdev;
40ab6a6e
AS		 2649
2650 return 0;
2651}
2652
a43b25da 2653static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2654 struct mlx5e_cq *cq,
2655 struct mlx5e_cq_param *param)
40ab6a6e 2656{
40ab6a6e
AS		 2657 struct mlx5_core_cq *mcq = &cq->mcq;
2658 int eqn_not_used;
0b6e26ce 2659 unsigned int irqn;
40ab6a6e
AS		 2660 int err;
2661
2662 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2663 &cq->wq_ctrl);
2664 if (err)
2665 return err;
2666
2667 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2668
2669 mcq->cqe_sz = 64;
2670 mcq->set_ci_db = cq->wq_ctrl.db.db;
2671 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2672 *mcq->set_ci_db = 0;
2673 *mcq->arm_db = 0;
2674 mcq->vector = param->eq_ix;
2675 mcq->comp = mlx5e_completion_event;
2676 mcq->event = mlx5e_cq_error_event;
2677 mcq->irqn = irqn;
40ab6a6e 2678
a43b25da 2679 cq->mdev = mdev;
40ab6a6e
AS		 2680
2681 return 0;
2682}
2683
a43b25da
SM		 2684static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2685 struct mlx5e_rq *drop_rq)
40ab6a6e 2686{
a43b25da
SM		 2687 struct mlx5e_cq_param cq_param = {};
2688 struct mlx5e_rq_param rq_param = {};
2689 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2690 int err;
2691
556dd1b9 2692 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2693
a43b25da 2694 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2695 if (err)
2696 return err;
2697
3b77235b 2698 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2699 if (err)
3b77235b 2700 goto err_free_cq;
40ab6a6e 2701
a43b25da 2702 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2703 if (err)
3b77235b 2704 goto err_destroy_cq;
40ab6a6e 2705
a43b25da 2706 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2707 if (err)
3b77235b 2708 goto err_free_rq;
40ab6a6e
AS		 2709
2710 return 0;
2711
3b77235b 2712err_free_rq:
a43b25da 2713 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2714
2715err_destroy_cq:
a43b25da 2716 mlx5e_destroy_cq(cq);
40ab6a6e 2717
3b77235b 2718err_free_cq:
a43b25da 2719 mlx5e_free_cq(cq);
3b77235b 2720
40ab6a6e
AS		 2721 return err;
2722}
2723
a43b25da 2724static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2725{
a43b25da
SM		 2726 mlx5e_destroy_rq(drop_rq);
2727 mlx5e_free_rq(drop_rq);
2728 mlx5e_destroy_cq(&drop_rq->cq);
2729 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2730}
2731
2732static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2733{
2734 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2735 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2736 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2737
08fb1dac 2738 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2739 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2740
2741 if (mlx5_lag_is_lacp_owner(mdev))
2742 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2743
40ab6a6e
AS		 2744 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2745}
2746
2747static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2748{
2749 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2750}
2751
cb67b832 2752int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2753{
2754 int err;
2755 int tc;
2756
6bfd390b 2757 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2758 err = mlx5e_create_tis(priv, tc);
2759 if (err)
2760 goto err_close_tises;
2761 }
2762
2763 return 0;
2764
2765err_close_tises:
2766 for (tc--; tc >= 0; tc--)
2767 mlx5e_destroy_tis(priv, tc);
2768
2769 return err;
2770}
2771
cb67b832 2772void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2773{
2774 int tc;
2775
6bfd390b 2776 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2777 mlx5e_destroy_tis(priv, tc);
2778}
2779
6a9764ef
SM		 2780static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2781 enum mlx5e_traffic_types tt,
2782 u32 *tirc)
f62b8bb8 2783{
b50d292b 2784 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2785
6a9764ef 2786 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2787
4cbeaff5 2788 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2789 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2790 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2791}
2792
6a9764ef 2793static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2794{
b50d292b 2795 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2796
6a9764ef 2797 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2798
2799 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2800 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2801 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2802}
2803
6bfd390b 2804static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2805{
724b2aa1 2806 struct mlx5e_tir *tir;
f62b8bb8
AV		 2807 void *tirc;
2808 int inlen;
2809 int err;
1da36696 2810 u32 *in;
1da36696 2811 int tt;
f62b8bb8
AV		 2812
2813 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2814 in = mlx5_vzalloc(inlen);
2815 if (!in)
2816 return -ENOMEM;
2817
1da36696
TT		 2818 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2819 memset(in, 0, inlen);
724b2aa1 2820 tir = &priv->indir_tir[tt];
1da36696 2821 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2822 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2823 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2824 if (err)
40ab6a6e 2825 goto err_destroy_tirs;
f62b8bb8
AV		 2826 }
2827
6bfd390b
HHZ		 2828 kvfree(in);
2829
2830 return 0;
2831
2832err_destroy_tirs:
2833 for (tt--; tt >= 0; tt--)
2834 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2835
2836 kvfree(in);
2837
2838 return err;
2839}
2840
cb67b832 2841int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2842{
2843 int nch = priv->profile->max_nch(priv->mdev);
2844 struct mlx5e_tir *tir;
2845 void *tirc;
2846 int inlen;
2847 int err;
2848 u32 *in;
2849 int ix;
2850
2851 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2852 in = mlx5_vzalloc(inlen);
2853 if (!in)
2854 return -ENOMEM;
2855
1da36696
TT		 2856 for (ix = 0; ix < nch; ix++) {
2857 memset(in, 0, inlen);
724b2aa1 2858 tir = &priv->direct_tir[ix];
1da36696 2859 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2860 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2861 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2862 if (err)
2863 goto err_destroy_ch_tirs;
2864 }
2865
2866 kvfree(in);
2867
f62b8bb8
AV		 2868 return 0;
2869
1da36696
TT		 2870err_destroy_ch_tirs:
2871 for (ix--; ix >= 0; ix--)
724b2aa1 2872 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2873
1da36696 2874 kvfree(in);
f62b8bb8
AV		 2875
2876 return err;
2877}
2878
6bfd390b 2879static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2880{
2881 int i;
2882
1da36696 2883 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2884 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2885}
2886
cb67b832 2887void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2888{
2889 int nch = priv->profile->max_nch(priv->mdev);
2890 int i;
2891
2892 for (i = 0; i < nch; i++)
2893 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2894}
2895
ff9c852f 2896int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2897{
2898 int err = 0;
2899 int i;
2900
ff9c852f
SM		 2901 for (i = 0; i < chs->num; i++) {
2902 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2903 if (err)
2904 return err;
2905 }
2906
2907 return 0;
2908}
2909
08fb1dac
SM		 2910static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2911{
2912 struct mlx5e_priv *priv = netdev_priv(netdev);
2913 bool was_opened;
2914 int err = 0;
2915
2916 if (tc && tc != MLX5E_MAX_NUM_TC)
2917 return -EINVAL;
2918
2919 mutex_lock(&priv->state_lock);
2920
2921 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2922 if (was_opened)
2923 mlx5e_close_locked(priv->netdev);
2924
6a9764ef 2925 priv->channels.params.num_tc = tc ? tc : 1;
08fb1dac
SM		 2926
2927 if (was_opened)
2928 err = mlx5e_open_locked(priv->netdev);
2929
2930 mutex_unlock(&priv->state_lock);
2931
2932 return err;
2933}
2934
2935static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2936 __be16 proto, struct tc_to_netdev *tc)
2937{
e8f887ac
AV		 2938 struct mlx5e_priv *priv = netdev_priv(dev);
2939
2940 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2941 goto mqprio;
2942
2943 switch (tc->type) {
e3a2b7ed
AV		 2944 case TC_SETUP_CLSFLOWER:
2945 switch (tc->cls_flower->command) {
2946 case TC_CLSFLOWER_REPLACE:
2947 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2948 case TC_CLSFLOWER_DESTROY:
2949 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2950 case TC_CLSFLOWER_STATS:
2951 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2952 }
e8f887ac
AV		 2953 default:
2954 return -EOPNOTSUPP;
2955 }
2956
2957mqprio:
67ba422e 2958 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2959 return -EINVAL;
2960
56f36acd
AN		 2961 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2962
2963 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 2964}
2965
bc1f4470 2966static void
f62b8bb8
AV		 2967mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2968{
2969 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2970 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2971 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2972 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2973
370bad0f
OG		 2974 if (mlx5e_is_uplink_rep(priv)) {
2975 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2976 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2977 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2978 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2979 } else {
2980 stats->rx_packets = sstats->rx_packets;
2981 stats->rx_bytes = sstats->rx_bytes;
2982 stats->tx_packets = sstats->tx_packets;
2983 stats->tx_bytes = sstats->tx_bytes;
2984 stats->tx_dropped = sstats->tx_queue_dropped;
2985 }
269e6b3a
GP		 2986
2987 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2988
2989 stats->rx_length_errors =
9218b44d
GP		 2990 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2991 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2992 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2993 stats->rx_crc_errors =
9218b44d
GP		 2994 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2995 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2996 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2997 stats->tx_carrier_errors =
9218b44d 2998 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2999 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3000 stats->rx_frame_errors;
3001 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3002
3003 /* vport multicast also counts packets that are dropped due to steering
3004 * or rx out of buffer
3005 */
9218b44d
GP		 3006 stats->multicast =
3007 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 3008
f62b8bb8
AV		 3009}
3010
3011static void mlx5e_set_rx_mode(struct net_device *dev)
3012{
3013 struct mlx5e_priv *priv = netdev_priv(dev);
3014
7bb29755 3015 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3016}
3017
3018static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3019{
3020 struct mlx5e_priv *priv = netdev_priv(netdev);
3021 struct sockaddr *saddr = addr;
3022
3023 if (!is_valid_ether_addr(saddr->sa_data))
3024 return -EADDRNOTAVAIL;
3025
3026 netif_addr_lock_bh(netdev);
3027 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3028 netif_addr_unlock_bh(netdev);
3029
7bb29755 3030 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3031
3032 return 0;
3033}
3034
0e405443
GP		 3035#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3036 do { \
3037 if (enable) \
3038 netdev->features |= feature; \
3039 else \
3040 netdev->features &= ~feature; \
3041 } while (0)
3042
3043typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3044
3045static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3046{
3047 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 3048 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3049 int err;
f62b8bb8
AV		 3050
3051 mutex_lock(&priv->state_lock);
f62b8bb8 3052
6a9764ef 3053 if (was_opened && (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
0e405443 3054 mlx5e_close_locked(priv->netdev);
98e81b0a 3055
6a9764ef 3056 priv->channels.params.lro_en = enable;
0e405443
GP		 3057 err = mlx5e_modify_tirs_lro(priv);
3058 if (err) {
3059 netdev_err(netdev, "lro modify failed, %d\n", err);
6a9764ef 3060 priv->channels.params.lro_en = !enable;
98e81b0a 3061 }
f62b8bb8 3062
6a9764ef 3063 if (was_opened && (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
0e405443
GP		 3064 mlx5e_open_locked(priv->netdev);
3065
9b37b07f
AS		 3066 mutex_unlock(&priv->state_lock);
3067
0e405443
GP		 3068 return err;
3069}
3070
3071static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3072{
3073 struct mlx5e_priv *priv = netdev_priv(netdev);
3074
3075 if (enable)
3076 mlx5e_enable_vlan_filter(priv);
3077 else
3078 mlx5e_disable_vlan_filter(priv);
3079
3080 return 0;
3081}
3082
3083static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3084{
3085 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3086
0e405443 3087 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3088 netdev_err(netdev,
3089 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3090 return -EINVAL;
3091 }
3092
0e405443
GP		 3093 return 0;
3094}
3095
94cb1ebb
EBE		 3096static int set_feature_rx_all(struct net_device *netdev, bool enable)
3097{
3098 struct mlx5e_priv *priv = netdev_priv(netdev);
3099 struct mlx5_core_dev *mdev = priv->mdev;
3100
3101 return mlx5_set_port_fcs(mdev, !enable);
3102}
3103
36350114
GP		 3104static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3105{
3106 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3107 int err = 0;
36350114
GP		 3108
3109 mutex_lock(&priv->state_lock);
3110
6a9764ef 3111 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3112 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3113 goto unlock;
3114
3115 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3116 if (err)
6a9764ef 3117 priv->channels.params.vlan_strip_disable = enable;
36350114 3118
ff9c852f 3119unlock:
36350114
GP		 3120 mutex_unlock(&priv->state_lock);
3121
3122 return err;
3123}
3124
45bf454a
MG		 3125#ifdef CONFIG_RFS_ACCEL
3126static int set_feature_arfs(struct net_device *netdev, bool enable)
3127{
3128 struct mlx5e_priv *priv = netdev_priv(netdev);
3129 int err;
3130
3131 if (enable)
3132 err = mlx5e_arfs_enable(priv);
3133 else
3134 err = mlx5e_arfs_disable(priv);
3135
3136 return err;
3137}
3138#endif
3139
0e405443
GP		 3140static int mlx5e_handle_feature(struct net_device *netdev,
3141 netdev_features_t wanted_features,
3142 netdev_features_t feature,
3143 mlx5e_feature_handler feature_handler)
3144{
3145 netdev_features_t changes = wanted_features ^ netdev->features;
3146 bool enable = !!(wanted_features & feature);
3147 int err;
3148
3149 if (!(changes & feature))
3150 return 0;
3151
3152 err = feature_handler(netdev, enable);
3153 if (err) {
3154 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3155 enable ? "Enable" : "Disable", feature, err);
3156 return err;
3157 }
3158
3159 MLX5E_SET_FEATURE(netdev, feature, enable);
3160 return 0;
3161}
3162
3163static int mlx5e_set_features(struct net_device *netdev,
3164 netdev_features_t features)
3165{
3166 int err;
3167
3168 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3169 set_feature_lro);
3170 err |= mlx5e_handle_feature(netdev, features,
3171 NETIF_F_HW_VLAN_CTAG_FILTER,
3172 set_feature_vlan_filter);
3173 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3174 set_feature_tc_num_filters);
94cb1ebb
EBE		 3175 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3176 set_feature_rx_all);
36350114
GP		 3177 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3178 set_feature_rx_vlan);
45bf454a
MG		 3179#ifdef CONFIG_RFS_ACCEL
3180 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3181 set_feature_arfs);
3182#endif
0e405443
GP		 3183
3184 return err ? -EINVAL : 0;
f62b8bb8
AV		 3185}
3186
3187static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3188{
3189 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 3190 bool was_opened;
98e81b0a 3191 int err = 0;
506753b0 3192 bool reset;
f62b8bb8 3193
f62b8bb8 3194 mutex_lock(&priv->state_lock);
98e81b0a 3195
6a9764ef
SM		 3196 reset = !priv->channels.params.lro_en &&
3197 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3198 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3199
98e81b0a 3200 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 3201 if (was_opened && reset)
98e81b0a
AS		 3202 mlx5e_close_locked(netdev);
3203
f62b8bb8 3204 netdev->mtu = new_mtu;
13f9bba7 3205 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 3206
506753b0 3207 if (was_opened && reset)
98e81b0a
AS		 3208 err = mlx5e_open_locked(netdev);
3209
f62b8bb8
AV		 3210 mutex_unlock(&priv->state_lock);
3211
3212 return err;
3213}
3214
ef9814de
EBE		 3215static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3216{
3217 switch (cmd) {
3218 case SIOCSHWTSTAMP:
3219 return mlx5e_hwstamp_set(dev, ifr);
3220 case SIOCGHWTSTAMP:
3221 return mlx5e_hwstamp_get(dev, ifr);
3222 default:
3223 return -EOPNOTSUPP;
3224 }
3225}
3226
66e49ded
SM		 3227static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3228{
3229 struct mlx5e_priv *priv = netdev_priv(dev);
3230 struct mlx5_core_dev *mdev = priv->mdev;
3231
3232 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3233}
3234
79aab093
MS		 3235static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3236 __be16 vlan_proto)
66e49ded
SM		 3237{
3238 struct mlx5e_priv *priv = netdev_priv(dev);
3239 struct mlx5_core_dev *mdev = priv->mdev;
3240
79aab093
MS		 3241 if (vlan_proto != htons(ETH_P_8021Q))
3242 return -EPROTONOSUPPORT;
3243
66e49ded
SM		 3244 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3245 vlan, qos);
3246}
3247
f942380c
MHY		 3248static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3249{
3250 struct mlx5e_priv *priv = netdev_priv(dev);
3251 struct mlx5_core_dev *mdev = priv->mdev;
3252
3253 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3254}
3255
1edc57e2
MHY		 3256static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3257{
3258 struct mlx5e_priv *priv = netdev_priv(dev);
3259 struct mlx5_core_dev *mdev = priv->mdev;
3260
3261 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3262}
bd77bf1c
MHY		 3263
3264static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3265 int max_tx_rate)
3266{
3267 struct mlx5e_priv *priv = netdev_priv(dev);
3268 struct mlx5_core_dev *mdev = priv->mdev;
3269
bd77bf1c 3270 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3271 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3272}
3273
66e49ded
SM		 3274static int mlx5_vport_link2ifla(u8 esw_link)
3275{
3276 switch (esw_link) {
3277 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3278 return IFLA_VF_LINK_STATE_DISABLE;
3279 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3280 return IFLA_VF_LINK_STATE_ENABLE;
3281 }
3282 return IFLA_VF_LINK_STATE_AUTO;
3283}
3284
3285static int mlx5_ifla_link2vport(u8 ifla_link)
3286{
3287 switch (ifla_link) {
3288 case IFLA_VF_LINK_STATE_DISABLE:
3289 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3290 case IFLA_VF_LINK_STATE_ENABLE:
3291 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3292 }
3293 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3294}
3295
3296static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3297 int link_state)
3298{
3299 struct mlx5e_priv *priv = netdev_priv(dev);
3300 struct mlx5_core_dev *mdev = priv->mdev;
3301
3302 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3303 mlx5_ifla_link2vport(link_state));
3304}
3305
3306static int mlx5e_get_vf_config(struct net_device *dev,
3307 int vf, struct ifla_vf_info *ivi)
3308{
3309 struct mlx5e_priv *priv = netdev_priv(dev);
3310 struct mlx5_core_dev *mdev = priv->mdev;
3311 int err;
3312
3313 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3314 if (err)
3315 return err;
3316 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3317 return 0;
3318}
3319
3320static int mlx5e_get_vf_stats(struct net_device *dev,
3321 int vf, struct ifla_vf_stats *vf_stats)
3322{
3323 struct mlx5e_priv *priv = netdev_priv(dev);
3324 struct mlx5_core_dev *mdev = priv->mdev;
3325
3326 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3327 vf_stats);
3328}
3329
1ad9a00a
PB		 3330static void mlx5e_add_vxlan_port(struct net_device *netdev,
3331 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3332{
3333 struct mlx5e_priv *priv = netdev_priv(netdev);
3334
974c3f30
AD		 3335 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3336 return;
3337
b3f63c3d
MF		 3338 if (!mlx5e_vxlan_allowed(priv->mdev))
3339 return;
3340
974c3f30 3341 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3342}
3343
1ad9a00a
PB		 3344static void mlx5e_del_vxlan_port(struct net_device *netdev,
3345 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3346{
3347 struct mlx5e_priv *priv = netdev_priv(netdev);
3348
974c3f30
AD		 3349 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3350 return;
3351
b3f63c3d
MF		 3352 if (!mlx5e_vxlan_allowed(priv->mdev))
3353 return;
3354
974c3f30 3355 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3356}
3357
3358static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3359 struct sk_buff *skb,
3360 netdev_features_t features)
3361{
3362 struct udphdr *udph;
3363 u16 proto;
3364 u16 port = 0;
3365
3366 switch (vlan_get_protocol(skb)) {
3367 case htons(ETH_P_IP):
3368 proto = ip_hdr(skb)->protocol;
3369 break;
3370 case htons(ETH_P_IPV6):
3371 proto = ipv6_hdr(skb)->nexthdr;
3372 break;
3373 default:
3374 goto out;
3375 }
3376
3377 if (proto == IPPROTO_UDP) {
3378 udph = udp_hdr(skb);
3379 port = be16_to_cpu(udph->dest);
3380 }
3381
3382 /* Verify if UDP port is being offloaded by HW */
3383 if (port && mlx5e_vxlan_lookup_port(priv, port))
3384 return features;
3385
3386out:
3387 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3388 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3389}
3390
3391static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3392 struct net_device *netdev,
3393 netdev_features_t features)
3394{
3395 struct mlx5e_priv *priv = netdev_priv(netdev);
3396
3397 features = vlan_features_check(skb, features);
3398 features = vxlan_features_check(skb, features);
3399
3400 /* Validate if the tunneled packet is being offloaded by HW */
3401 if (skb->encapsulation &&
3402 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3403 return mlx5e_vxlan_features_check(priv, skb, features);
3404
3405 return features;
3406}
3407
3947ca18
DJ		 3408static void mlx5e_tx_timeout(struct net_device *dev)
3409{
3410 struct mlx5e_priv *priv = netdev_priv(dev);
3411 bool sched_work = false;
3412 int i;
3413
3414 netdev_err(dev, "TX timeout detected\n");
3415
6a9764ef 3416 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3417 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3418
2c1ccc99 3419 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3420 continue;
3421 sched_work = true;
c0f1147d 3422 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3423 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3424 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3425 }
3426
3427 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3428 schedule_work(&priv->tx_timeout_work);
3429}
3430
86994156
RS		 3431static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3432{
3433 struct mlx5e_priv *priv = netdev_priv(netdev);
3434 struct bpf_prog *old_prog;
3435 int err = 0;
3436 bool reset, was_opened;
3437 int i;
3438
3439 mutex_lock(&priv->state_lock);
3440
3441 if ((netdev->features & NETIF_F_LRO) && prog) {
3442 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3443 err = -EINVAL;
3444 goto unlock;
3445 }
3446
3447 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3448 /* no need for full reset when exchanging programs */
6a9764ef 3449 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3450
3451 if (was_opened && reset)
3452 mlx5e_close_locked(netdev);
c54c0629
DB		 3453 if (was_opened && !reset) {
3454 /* num_channels is invariant here, so we can take the
3455 * batched reference right upfront.
3456 */
6a9764ef 3457 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3458 if (IS_ERR(prog)) {
3459 err = PTR_ERR(prog);
3460 goto unlock;
3461 }
3462 }
86994156 3463
c54c0629
DB		 3464 /* exchange programs, extra prog reference we got from caller
3465 * as long as we don't fail from this point onwards.
3466 */
6a9764ef 3467 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3468 if (old_prog)
3469 bpf_prog_put(old_prog);
3470
3471 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3472 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3473
3474 if (was_opened && reset)
3475 mlx5e_open_locked(netdev);
3476
3477 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3478 goto unlock;
3479
3480 /* exchanging programs w/o reset, we update ref counts on behalf
3481 * of the channels RQs here.
3482 */
ff9c852f
SM		 3483 for (i = 0; i < priv->channels.num; i++) {
3484 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3485
c0f1147d 3486 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3487 napi_synchronize(&c->napi);
3488 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3489
3490 old_prog = xchg(&c->rq.xdp_prog, prog);
3491
c0f1147d 3492 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3493 /* napi_schedule in case we have missed anything */
3494 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3495 napi_schedule(&c->napi);
3496
3497 if (old_prog)
3498 bpf_prog_put(old_prog);
3499 }
3500
3501unlock:
3502 mutex_unlock(&priv->state_lock);
3503 return err;
3504}
3505
3506static bool mlx5e_xdp_attached(struct net_device *dev)
3507{
3508 struct mlx5e_priv *priv = netdev_priv(dev);
3509
6a9764ef 3510 return !!priv->channels.params.xdp_prog;
86994156
RS		 3511}
3512
3513static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3514{
3515 switch (xdp->command) {
3516 case XDP_SETUP_PROG:
3517 return mlx5e_xdp_set(dev, xdp->prog);
3518 case XDP_QUERY_PROG:
3519 xdp->prog_attached = mlx5e_xdp_attached(dev);
3520 return 0;
3521 default:
3522 return -EINVAL;
3523 }
3524}
3525
80378384
CO		 3526#ifdef CONFIG_NET_POLL_CONTROLLER
3527/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3528 * reenabling interrupts.
3529 */
3530static void mlx5e_netpoll(struct net_device *dev)
3531{
3532 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3533 struct mlx5e_channels *chs = &priv->channels;
3534
80378384
CO		 3535 int i;
3536
ff9c852f
SM		 3537 for (i = 0; i < chs->num; i++)
3538 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3539}
3540#endif
3541
b0eed40e 3542static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3543 .ndo_open = mlx5e_open,
3544 .ndo_stop = mlx5e_close,
3545 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3546 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3547 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3548 .ndo_get_stats64 = mlx5e_get_stats,
3549 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3550 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3551 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3552 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3553 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3554 .ndo_change_mtu = mlx5e_change_mtu,
3555 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3556 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3557#ifdef CONFIG_RFS_ACCEL
3558 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3559#endif
3947ca18 3560 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3561 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3562#ifdef CONFIG_NET_POLL_CONTROLLER
3563 .ndo_poll_controller = mlx5e_netpoll,
3564#endif
b0eed40e
SM		 3565};
3566
3567static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3568 .ndo_open = mlx5e_open,
3569 .ndo_stop = mlx5e_close,
3570 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3571 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3572 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3573 .ndo_get_stats64 = mlx5e_get_stats,
3574 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3575 .ndo_set_mac_address = mlx5e_set_mac,
3576 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3577 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3578 .ndo_set_features = mlx5e_set_features,
3579 .ndo_change_mtu = mlx5e_change_mtu,
3580 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3581 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3582 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3583 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3584 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3585#ifdef CONFIG_RFS_ACCEL
3586 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3587#endif
b0eed40e
SM		 3588 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3589 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3590 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3591 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3592 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3593 .ndo_get_vf_config = mlx5e_get_vf_config,
3594 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3595 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3596 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3597 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3598#ifdef CONFIG_NET_POLL_CONTROLLER
3599 .ndo_poll_controller = mlx5e_netpoll,
3600#endif
370bad0f
OG		 3601 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3602 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3603};
3604
3605static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3606{
3607 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3608 return -EOPNOTSUPP;
f62b8bb8
AV		 3609 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3610 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3611 !MLX5_CAP_ETH(mdev, csum_cap) ||
3612 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3613 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3614 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3615 MLX5_CAP_FLOWTABLE(mdev,
3616 flow_table_properties_nic_receive.max_ft_level)
3617 < 3) {
f62b8bb8
AV		 3618 mlx5_core_warn(mdev,
3619 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3620 return -EOPNOTSUPP;
f62b8bb8 3621 }
66189961
TT		 3622 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3623 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3624 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3625 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3626
f62b8bb8
AV		 3627 return 0;
3628}
3629
58d52291
AS		 3630u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3631{
3632 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3633
3634 return bf_buf_size -
3635 sizeof(struct mlx5e_tx_wqe) +
3636 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3637}
3638
d8c9660d
TT		 3639void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3640 u32 *indirection_rqt, int len,
85082dba
TT		 3641 int num_channels)
3642{
d8c9660d
TT		 3643 int node = mdev->priv.numa_node;
3644 int node_num_of_cores;
85082dba
TT		 3645 int i;
3646
d8c9660d
TT		 3647 if (node == -1)
3648 node = first_online_node;
3649
3650 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3651
3652 if (node_num_of_cores)
3653 num_channels = min_t(int, num_channels, node_num_of_cores);
3654
85082dba
TT		 3655 for (i = 0; i < len; i++)
3656 indirection_rqt[i] = i % num_channels;
3657}
3658
b797a684
SM		 3659static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3660{
3661 enum pcie_link_width width;
3662 enum pci_bus_speed speed;
3663 int err = 0;
3664
3665 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3666 if (err)
3667 return err;
3668
3669 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3670 return -EINVAL;
3671
3672 switch (speed) {
3673 case PCIE_SPEED_2_5GT:
3674 *pci_bw = 2500 * width;
3675 break;
3676 case PCIE_SPEED_5_0GT:
3677 *pci_bw = 5000 * width;
3678 break;
3679 case PCIE_SPEED_8_0GT:
3680 *pci_bw = 8000 * width;
3681 break;
3682 default:
3683 return -EINVAL;
3684 }
3685
3686 return 0;
3687}
3688
3689static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3690{
3691 return (link_speed && pci_bw &&
3692 (pci_bw < 40000) && (pci_bw < link_speed));
3693}
3694
9908aa29
TT		 3695void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3696{
3697 params->rx_cq_period_mode = cq_period_mode;
3698
3699 params->rx_cq_moderation.pkts =
3700 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3701 params->rx_cq_moderation.usec =
3702 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3703
3704 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3705 params->rx_cq_moderation.usec =
3706 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef
SM		 3707
3708 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3709 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3710}
3711
2b029556
SM		 3712u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3713{
3714 int i;
3715
3716 /* The supported periods are organized in ascending order */
3717 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3718 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3719 break;
3720
3721 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3722}
3723
6a9764ef
SM		 3724static void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3725 struct mlx5e_params *params,
3726 u16 max_channels)
f62b8bb8 3727{
6a9764ef 3728 u8 cq_period_mode = 0;
b797a684
SM		 3729 u32 link_speed = 0;
3730 u32 pci_bw = 0;
2fc4bfb7 3731
6a9764ef
SM		 3732 params->num_channels = max_channels;
3733 params->num_tc = 1;
2b029556 3734
6a9764ef
SM		 3735 /* SQ */
3736 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3737 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3738 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3739
b797a684 3740 /* set CQE compression */
6a9764ef 3741 params->rx_cqe_compress_def = false;
b797a684 3742 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
6a9764ef 3743 MLX5_CAP_GEN(mdev, vport_group_manager)) {
b797a684
SM		 3744 mlx5e_get_max_linkspeed(mdev, &link_speed);
3745 mlx5e_get_pci_bw(mdev, &pci_bw);
3746 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
6a9764ef
SM		 3747 link_speed, pci_bw);
3748 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
b797a684 3749 }
6a9764ef
SM		 3750 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3751
3752 /* RQ */
3753 mlx5e_set_rq_params(mdev, params);
b797a684 3754
6a9764ef
SM		 3755 /* HW LRO */
3756 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3757 params->lro_en = true;
3758 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3759
6a9764ef
SM		 3760 /* CQ moderation params */
3761 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3762 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3763 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3764 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3765 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3766
6a9764ef
SM		 3767 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3768 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3769
6a9764ef
SM		 3770 /* TX inline */
3771 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3772 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3773 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3774 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3775 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3776
6a9764ef
SM		 3777 /* RSS */
3778 params->rss_hfunc = ETH_RSS_HASH_XOR;
3779 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3780 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3781 MLX5E_INDIR_RQT_SIZE, max_channels);
3782}
f62b8bb8 3783
6a9764ef
SM		 3784static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3785 struct net_device *netdev,
3786 const struct mlx5e_profile *profile,
3787 void *ppriv)
3788{
3789 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3790
6a9764ef
SM		 3791 priv->mdev = mdev;
3792 priv->netdev = netdev;
3793 priv->profile = profile;
3794 priv->ppriv = ppriv;
2d75b2bc 3795
6a9764ef 3796 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3797
f62b8bb8
AV		 3798 mutex_init(&priv->state_lock);
3799
3800 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3801 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3802 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3803 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3804}
3805
3806static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3807{
3808 struct mlx5e_priv *priv = netdev_priv(netdev);
3809
e1d7d349 3810 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3811 if (is_zero_ether_addr(netdev->dev_addr) &&
3812 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3813 eth_hw_addr_random(netdev);
3814 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3815 }
f62b8bb8
AV		 3816}
3817
cb67b832
HHZ		 3818static const struct switchdev_ops mlx5e_switchdev_ops = {
3819 .switchdev_port_attr_get = mlx5e_attr_get,
3820};
3821
6bfd390b 3822static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3823{
3824 struct mlx5e_priv *priv = netdev_priv(netdev);
3825 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3826 bool fcs_supported;
3827 bool fcs_enabled;
f62b8bb8
AV		 3828
3829 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3830
08fb1dac 3831 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3832 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3833#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3834 if (MLX5_CAP_GEN(mdev, qos))
3835 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3836#endif
3837 } else {
b0eed40e 3838 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3839 }
66e49ded 3840
f62b8bb8
AV		 3841 netdev->watchdog_timeo = 15 * HZ;
3842
3843 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3844
12be4b21 3845 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3846 netdev->vlan_features |= NETIF_F_IP_CSUM;
3847 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3848 netdev->vlan_features |= NETIF_F_GRO;
3849 netdev->vlan_features |= NETIF_F_TSO;
3850 netdev->vlan_features |= NETIF_F_TSO6;
3851 netdev->vlan_features |= NETIF_F_RXCSUM;
3852 netdev->vlan_features |= NETIF_F_RXHASH;
3853
3854 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3855 netdev->vlan_features |= NETIF_F_LRO;
3856
3857 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3858 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3859 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3860 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3861
b3f63c3d 3862 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3863 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3864 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3865 NETIF_F_GSO_PARTIAL;
b3f63c3d 3866 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3867 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3868 netdev->hw_enc_features |= NETIF_F_TSO;
3869 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3870 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3871 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3872 NETIF_F_GSO_PARTIAL;
3873 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3874 }
3875
94cb1ebb
EBE		 3876 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3877
3878 if (fcs_supported)
3879 netdev->hw_features |= NETIF_F_RXALL;
3880
f62b8bb8 3881 netdev->features = netdev->hw_features;
6a9764ef 3882 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 3883 netdev->features &= ~NETIF_F_LRO;
3884
94cb1ebb
EBE		 3885 if (fcs_enabled)
3886 netdev->features &= ~NETIF_F_RXALL;
3887
e8f887ac
AV		 3888#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3889 if (FT_CAP(flow_modify_en) &&
3890 FT_CAP(modify_root) &&
3891 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3892 FT_CAP(flow_table_modify)) {
3893 netdev->hw_features |= NETIF_F_HW_TC;
3894#ifdef CONFIG_RFS_ACCEL
3895 netdev->hw_features |= NETIF_F_NTUPLE;
3896#endif
3897 }
e8f887ac 3898
f62b8bb8
AV		 3899 netdev->features |= NETIF_F_HIGHDMA;
3900
3901 netdev->priv_flags |= IFF_UNICAST_FLT;
3902
3903 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3904
3905#ifdef CONFIG_NET_SWITCHDEV
3906 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3907 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3908#endif
f62b8bb8
AV		 3909}
3910
593cf338
RS		 3911static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3912{
3913 struct mlx5_core_dev *mdev = priv->mdev;
3914 int err;
3915
3916 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3917 if (err) {
3918 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3919 priv->q_counter = 0;
3920 }
3921}
3922
3923static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3924{
3925 if (!priv->q_counter)
3926 return;
3927
3928 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3929}
3930
6bfd390b
HHZ		 3931static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3932 struct net_device *netdev,
127ea380
HHZ		 3933 const struct mlx5e_profile *profile,
3934 void *ppriv)
6bfd390b
HHZ		 3935{
3936 struct mlx5e_priv *priv = netdev_priv(netdev);
3937
127ea380 3938 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3939 mlx5e_build_nic_netdev(netdev);
3940 mlx5e_vxlan_init(priv);
3941}
3942
3943static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3944{
3945 mlx5e_vxlan_cleanup(priv);
127ea380 3946
6a9764ef
SM		 3947 if (priv->channels.params.xdp_prog)
3948 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 3949}
3950
3951static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3952{
3953 struct mlx5_core_dev *mdev = priv->mdev;
3954 int err;
3955 int i;
3956
3957 err = mlx5e_create_indirect_rqts(priv);
3958 if (err) {
3959 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3960 return err;
3961 }
3962
3963 err = mlx5e_create_direct_rqts(priv);
3964 if (err) {
3965 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3966 goto err_destroy_indirect_rqts;
3967 }
3968
3969 err = mlx5e_create_indirect_tirs(priv);
3970 if (err) {
3971 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3972 goto err_destroy_direct_rqts;
3973 }
3974
3975 err = mlx5e_create_direct_tirs(priv);
3976 if (err) {
3977 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3978 goto err_destroy_indirect_tirs;
3979 }
3980
3981 err = mlx5e_create_flow_steering(priv);
3982 if (err) {
3983 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3984 goto err_destroy_direct_tirs;
3985 }
3986
3987 err = mlx5e_tc_init(priv);
3988 if (err)
3989 goto err_destroy_flow_steering;
3990
3991 return 0;
3992
3993err_destroy_flow_steering:
3994 mlx5e_destroy_flow_steering(priv);
3995err_destroy_direct_tirs:
3996 mlx5e_destroy_direct_tirs(priv);
3997err_destroy_indirect_tirs:
3998 mlx5e_destroy_indirect_tirs(priv);
3999err_destroy_direct_rqts:
4000 for (i = 0; i < priv->profile->max_nch(mdev); i++)
4001 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
4002err_destroy_indirect_rqts:
4003 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4004 return err;
4005}
4006
4007static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4008{
4009 int i;
4010
4011 mlx5e_tc_cleanup(priv);
4012 mlx5e_destroy_flow_steering(priv);
4013 mlx5e_destroy_direct_tirs(priv);
4014 mlx5e_destroy_indirect_tirs(priv);
4015 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
4016 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
4017 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4018}
4019
4020static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4021{
4022 int err;
4023
4024 err = mlx5e_create_tises(priv);
4025 if (err) {
4026 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4027 return err;
4028 }
4029
4030#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4031 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4032#endif
4033 return 0;
4034}
4035
4036static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4037{
4038 struct net_device *netdev = priv->netdev;
4039 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 4040 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4041 struct mlx5_eswitch_rep rep;
6bfd390b 4042
7907f23a
AH		 4043 mlx5_lag_add(mdev, netdev);
4044
6bfd390b 4045 mlx5e_enable_async_events(priv);
127ea380
HHZ		 4046
4047 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 4048 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 4049 rep.load = mlx5e_nic_rep_load;
4050 rep.unload = mlx5e_nic_rep_unload;
9deb2241 4051 rep.vport = FDB_UPLINK_VPORT;
726293f1 4052 rep.netdev = netdev;
9deb2241 4053 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 4054 }
610e89e0
SM		 4055
4056 if (netdev->reg_state != NETREG_REGISTERED)
4057 return;
4058
4059 /* Device already registered: sync netdev system state */
4060 if (mlx5e_vxlan_allowed(mdev)) {
4061 rtnl_lock();
4062 udp_tunnel_get_rx_info(netdev);
4063 rtnl_unlock();
4064 }
4065
4066 queue_work(priv->wq, &priv->set_rx_mode_work);
6bfd390b
HHZ		 4067}
4068
4069static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4070{
3deef8ce
SM		 4071 struct mlx5_core_dev *mdev = priv->mdev;
4072 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4073
6bfd390b 4074 queue_work(priv->wq, &priv->set_rx_mode_work);
3deef8ce
SM		 4075 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4076 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 4077 mlx5e_disable_async_events(priv);
3deef8ce 4078 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4079}
4080
4081static const struct mlx5e_profile mlx5e_nic_profile = {
4082 .init = mlx5e_nic_init,
4083 .cleanup = mlx5e_nic_cleanup,
4084 .init_rx = mlx5e_init_nic_rx,
4085 .cleanup_rx = mlx5e_cleanup_nic_rx,
4086 .init_tx = mlx5e_init_nic_tx,
4087 .cleanup_tx = mlx5e_cleanup_nic_tx,
4088 .enable = mlx5e_nic_enable,
4089 .disable = mlx5e_nic_disable,
4090 .update_stats = mlx5e_update_stats,
4091 .max_nch = mlx5e_get_max_num_channels,
4092 .max_tc = MLX5E_MAX_NUM_TC,
4093};
4094
26e59d80
MHY		 4095struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4096 const struct mlx5e_profile *profile,
4097 void *ppriv)
f62b8bb8 4098{
26e59d80 4099 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4100 struct net_device *netdev;
4101 struct mlx5e_priv *priv;
f62b8bb8 4102
08fb1dac 4103 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4104 nch * profile->max_tc,
08fb1dac 4105 nch);
f62b8bb8
AV		 4106 if (!netdev) {
4107 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4108 return NULL;
4109 }
4110
be4891af
SM		 4111#ifdef CONFIG_RFS_ACCEL
4112 netdev->rx_cpu_rmap = mdev->rmap;
4113#endif
4114
127ea380 4115 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4116
4117 netif_carrier_off(netdev);
4118
4119 priv = netdev_priv(netdev);
4120
7bb29755
MF		 4121 priv->wq = create_singlethread_workqueue("mlx5e");
4122 if (!priv->wq)
26e59d80
MHY		 4123 goto err_cleanup_nic;
4124
4125 return netdev;
4126
4127err_cleanup_nic:
4128 profile->cleanup(priv);
4129 free_netdev(netdev);
4130
4131 return NULL;
4132}
4133
4134int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4135{
4136 const struct mlx5e_profile *profile;
4137 struct mlx5e_priv *priv;
b80f71f5 4138 u16 max_mtu;
26e59d80
MHY		 4139 int err;
4140
4141 priv = netdev_priv(netdev);
4142 profile = priv->profile;
4143 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4144
6bfd390b
HHZ		 4145 err = profile->init_tx(priv);
4146 if (err)
ec8b9981 4147 goto out;
5c50368f 4148
a43b25da 4149 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4150 if (err) {
4151 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4152 goto err_cleanup_tx;
5c50368f
AS		 4153 }
4154
6bfd390b
HHZ		 4155 err = profile->init_rx(priv);
4156 if (err)
5c50368f 4157 goto err_close_drop_rq;
5c50368f 4158
593cf338
RS		 4159 mlx5e_create_q_counter(priv);
4160
33cfaaa8 4161 mlx5e_init_l2_addr(priv);
5c50368f 4162
b80f71f5
JW		 4163 /* MTU range: 68 - hw-specific max */
4164 netdev->min_mtu = ETH_MIN_MTU;
4165 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4166 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4167
13f9bba7
SM		 4168 mlx5e_set_dev_port_mtu(netdev);
4169
6bfd390b
HHZ		 4170 if (profile->enable)
4171 profile->enable(priv);
f62b8bb8 4172
26e59d80
MHY		 4173 rtnl_lock();
4174 if (netif_running(netdev))
4175 mlx5e_open(netdev);
4176 netif_device_attach(netdev);
4177 rtnl_unlock();
f62b8bb8 4178
26e59d80 4179 return 0;
5c50368f
AS		 4180
4181err_close_drop_rq:
a43b25da 4182 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4183
6bfd390b
HHZ		 4184err_cleanup_tx:
4185 profile->cleanup_tx(priv);
5c50368f 4186
26e59d80
MHY		 4187out:
4188 return err;
f62b8bb8
AV		 4189}
4190
127ea380
HHZ		 4191static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
4192{
4193 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4194 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4195 int vport;
dbe413e3 4196 u8 mac[ETH_ALEN];
127ea380
HHZ		 4197
4198 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4199 return;
4200
dbe413e3
HHZ		 4201 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
4202
127ea380
HHZ		 4203 for (vport = 1; vport < total_vfs; vport++) {
4204 struct mlx5_eswitch_rep rep;
4205
cb67b832
HHZ		 4206 rep.load = mlx5e_vport_rep_load;
4207 rep.unload = mlx5e_vport_rep_unload;
127ea380 4208 rep.vport = vport;
dbe413e3 4209 ether_addr_copy(rep.hw_id, mac);
9deb2241 4210 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 4211 }
4212}
4213
6f08a22c
SM		 4214static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
4215{
4216 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4217 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4218 int vport;
4219
4220 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4221 return;
4222
4223 for (vport = 1; vport < total_vfs; vport++)
4224 mlx5_eswitch_unregister_vport_rep(esw, vport);
4225}
4226
26e59d80
MHY		 4227void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4228{
4229 struct mlx5e_priv *priv = netdev_priv(netdev);
4230 const struct mlx5e_profile *profile = priv->profile;
4231
4232 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80
MHY		 4233
4234 rtnl_lock();
4235 if (netif_running(netdev))
4236 mlx5e_close(netdev);
4237 netif_device_detach(netdev);
4238 rtnl_unlock();
4239
37f304d1
SM		 4240 if (profile->disable)
4241 profile->disable(priv);
4242 flush_workqueue(priv->wq);
4243
26e59d80
MHY		 4244 mlx5e_destroy_q_counter(priv);
4245 profile->cleanup_rx(priv);
a43b25da 4246 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4247 profile->cleanup_tx(priv);
26e59d80
MHY		 4248 cancel_delayed_work_sync(&priv->update_stats_work);
4249}
4250
4251/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4252 * hardware contexts and to connect it to the current netdev.
4253 */
4254static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4255{
4256 struct mlx5e_priv *priv = vpriv;
4257 struct net_device *netdev = priv->netdev;
4258 int err;
4259
4260 if (netif_device_present(netdev))
4261 return 0;
4262
4263 err = mlx5e_create_mdev_resources(mdev);
4264 if (err)
4265 return err;
4266
4267 err = mlx5e_attach_netdev(mdev, netdev);
4268 if (err) {
4269 mlx5e_destroy_mdev_resources(mdev);
4270 return err;
4271 }
4272
6f08a22c 4273 mlx5e_register_vport_rep(mdev);
26e59d80
MHY		 4274 return 0;
4275}
4276
4277static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4278{
4279 struct mlx5e_priv *priv = vpriv;
4280 struct net_device *netdev = priv->netdev;
4281
4282 if (!netif_device_present(netdev))
4283 return;
4284
6f08a22c 4285 mlx5e_unregister_vport_rep(mdev);
26e59d80
MHY		 4286 mlx5e_detach_netdev(mdev, netdev);
4287 mlx5e_destroy_mdev_resources(mdev);
4288}
4289
b50d292b
HHZ		 4290static void *mlx5e_add(struct mlx5_core_dev *mdev)
4291{
127ea380 4292 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4293 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4294 void *ppriv = NULL;
26e59d80
MHY		 4295 void *priv;
4296 int vport;
4297 int err;
4298 struct net_device *netdev;
b50d292b 4299
26e59d80
MHY		 4300 err = mlx5e_check_required_hca_cap(mdev);
4301 if (err)
b50d292b
HHZ		 4302 return NULL;
4303
127ea380
HHZ		 4304 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4305 ppriv = &esw->offloads.vport_reps[0];
4306
26e59d80
MHY		 4307 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4308 if (!netdev) {
4309 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4310 goto err_unregister_reps;
4311 }
4312
4313 priv = netdev_priv(netdev);
4314
4315 err = mlx5e_attach(mdev, priv);
4316 if (err) {
4317 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4318 goto err_destroy_netdev;
4319 }
4320
4321 err = register_netdev(netdev);
4322 if (err) {
4323 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4324 goto err_detach;
b50d292b 4325 }
26e59d80
MHY		 4326
4327 return priv;
4328
4329err_detach:
4330 mlx5e_detach(mdev, priv);
4331
4332err_destroy_netdev:
4333 mlx5e_destroy_netdev(mdev, priv);
4334
4335err_unregister_reps:
4336 for (vport = 1; vport < total_vfs; vport++)
4337 mlx5_eswitch_unregister_vport_rep(esw, vport);
4338
4339 return NULL;
b50d292b
HHZ		 4340}
4341
cb67b832 4342void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4343{
6bfd390b 4344 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4345 struct net_device *netdev = priv->netdev;
4346
7bb29755 4347 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4348 if (profile->cleanup)
4349 profile->cleanup(priv);
26e59d80 4350 free_netdev(netdev);
f62b8bb8
AV		 4351}
4352
b50d292b
HHZ		 4353static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4354{
4355 struct mlx5e_priv *priv = vpriv;
127ea380 4356
5e1e93c7 4357 unregister_netdev(priv->netdev);
26e59d80
MHY		 4358 mlx5e_detach(mdev, vpriv);
4359 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4360}
4361
f62b8bb8
AV		 4362static void *mlx5e_get_netdev(void *vpriv)
4363{
4364 struct mlx5e_priv *priv = vpriv;
4365
4366 return priv->netdev;
4367}
4368
4369static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4370 .add = mlx5e_add,
4371 .remove = mlx5e_remove,
26e59d80
MHY		 4372 .attach = mlx5e_attach,
4373 .detach = mlx5e_detach,
f62b8bb8
AV		 4374 .event = mlx5e_async_event,
4375 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4376 .get_dev = mlx5e_get_netdev,
4377};
4378
4379void mlx5e_init(void)
4380{
665bc539 4381 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4382 mlx5_register_interface(&mlx5e_interface);
4383}
4384
4385void mlx5e_cleanup(void)
4386{
4387 mlx5_unregister_interface(&mlx5e_interface);
4388}
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