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net/mlx5: Enable flow-steering for IB link
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
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f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac 33#include <net/tc_act/tc_gact.h>
b4e029da 34#include <linux/crash_dump.h>
e8f887ac 35#include <net/pkt_cls.h>
86d722ad 36#include <linux/mlx5/fs.h>
b3f63c3d 37#include <net/vxlan.h>
86994156 38#include <linux/bpf.h>
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
66e49ded 41#include "eswitch.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
9908aa29 58 u8 cq_period_mode;
f62b8bb8
AV		 59};
60
61struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
b5503b99 64 struct mlx5e_sq_param xdp_sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
2fc4bfb7
SM		 71static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72{
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76}
77
6a9764ef
SM		 78void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 80{
6a9764ef
SM		 81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
2fc4bfb7 84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 85 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 96 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 99
100 /* Extra room needed for build_skb */
6a9764ef 101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 103 }
2fc4bfb7 104
6a9764ef
SM		 105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 110}
111
6a9764ef 112static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 113{
6a9764ef
SM		 114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
2fc4bfb7
SM		 116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 118 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 119}
120
f62b8bb8
AV		 121static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122{
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
e7546514 127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 128
87424ad5
SD		 129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 131 netif_carrier_on(priv->netdev);
87424ad5
SD		 132 } else {
133 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 134 netif_carrier_off(priv->netdev);
87424ad5 135 }
f62b8bb8
AV		 136}
137
138static void mlx5e_update_carrier_work(struct work_struct *work)
139{
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
142
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
147}
148
3947ca18
DJ		 149static void mlx5e_tx_timeout_work(struct work_struct *work)
150{
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 tx_timeout_work);
153 int err;
154
155 rtnl_lock();
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
158 goto unlock;
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
161 if (err)
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
163 err);
164unlock:
165 mutex_unlock(&priv->state_lock);
166 rtnl_unlock();
167}
168
9218b44d 169static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 170{
9218b44d 171 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
9218b44d 174 u64 tx_offload_none = 0;
f62b8bb8
AV		 175 int i, j;
176
9218b44d 177 memset(s, 0, sizeof(*s));
ff9c852f
SM		 178 for (i = 0; i < priv->channels.num; i++) {
179 struct mlx5e_channel *c = priv->channels.c[i];
180
181 rq_stats = &c->rq.stats;
f62b8bb8 182
faf4478b
GP		 183 s->rx_packets += rq_stats->packets;
184 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 185 s->rx_lro_packets += rq_stats->lro_packets;
186 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 187 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 188 s->rx_csum_complete += rq_stats->csum_complete;
189 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 190 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 191 s->rx_xdp_tx += rq_stats->xdp_tx;
192 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 193 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 194 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 195 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 196 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
197 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 198 s->rx_cache_reuse += rq_stats->cache_reuse;
199 s->rx_cache_full += rq_stats->cache_full;
200 s->rx_cache_empty += rq_stats->cache_empty;
201 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 202
6a9764ef 203 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 204 sq_stats = &c->sq[j].stats;
f62b8bb8 205
faf4478b
GP		 206 s->tx_packets += sq_stats->packets;
207 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 208 s->tx_tso_packets += sq_stats->tso_packets;
209 s->tx_tso_bytes += sq_stats->tso_bytes;
210 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
211 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 212 s->tx_queue_stopped += sq_stats->stopped;
213 s->tx_queue_wake += sq_stats->wake;
214 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 215 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 216 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
217 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 218 }
219 }
220
9218b44d 221 /* Update calculated offload counters */
bfe6d8d1
GP		 222 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
223 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 224
bfe6d8d1 225 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 226 priv->stats.pport.phy_counters,
227 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 228}
229
230static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
231{
232 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
233 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 234 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 235 struct mlx5_core_dev *mdev = priv->mdev;
236
f62b8bb8
AV		 237 MLX5_SET(query_vport_counter_in, in, opcode,
238 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
239 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
240 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
241
242 memset(out, 0, outlen);
9218b44d
GP		 243 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
244}
245
246static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
247{
248 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
249 struct mlx5_core_dev *mdev = priv->mdev;
250 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 251 int prio;
9218b44d
GP		 252 void *out;
253 u32 *in;
254
255 in = mlx5_vzalloc(sz);
256 if (!in)
f62b8bb8
AV		 257 goto free_out;
258
9218b44d 259 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 260
9218b44d
GP		 261 out = pstats->IEEE_802_3_counters;
262 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
263 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 272
121fcdc8
GP		 273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
5db0a4f6
GP		 277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 }
282
cf678570
GP		 283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
289 }
290
f62b8bb8 291free_out:
9218b44d
GP		 292 kvfree(in);
293}
294
295static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
296{
297 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
298
299 if (!priv->q_counter)
300 return;
301
302 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
303 &qcnt->rx_out_of_buffer);
304}
305
0f7f3481
GP		 306static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
307{
308 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
311 void *out;
312 u32 *in;
313
314 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
315 return;
316
317 in = mlx5_vzalloc(sz);
318 if (!in)
319 return;
320
321 out = pcie_stats->pcie_perf_counters;
322 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
323 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
324
325 kvfree(in);
326}
327
9218b44d
GP		 328void mlx5e_update_stats(struct mlx5e_priv *priv)
329{
3dd69e3d 330 mlx5e_update_pcie_counters(priv);
9218b44d 331 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 332 mlx5e_update_vport_counters(priv);
333 mlx5e_update_q_counter(priv);
121fcdc8 334 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 335}
336
cb67b832 337void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 338{
339 struct delayed_work *dwork = to_delayed_work(work);
340 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
341 update_stats_work);
342 mutex_lock(&priv->state_lock);
343 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 344 priv->profile->update_stats(priv);
7bb29755
MF		 345 queue_delayed_work(priv->wq, dwork,
346 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 347 }
348 mutex_unlock(&priv->state_lock);
349}
350
daa21560
TT		 351static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
352 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 353{
daa21560 354 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 355 struct ptp_clock_event ptp_event;
356 struct mlx5_eqe *eqe = NULL;
daa21560 357
e0f46eb9 358 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 359 return;
360
f62b8bb8
AV		 361 switch (event) {
362 case MLX5_DEV_EVENT_PORT_UP:
363 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 364 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 365 break;
ee7f1220
EE		 366 case MLX5_DEV_EVENT_PPS:
367 eqe = (struct mlx5_eqe *)param;
368 ptp_event.type = PTP_CLOCK_EXTTS;
369 ptp_event.index = eqe->data.pps.pin;
370 ptp_event.timestamp =
371 timecounter_cyc2time(&priv->tstamp.clock,
372 be64_to_cpu(eqe->data.pps.time_stamp));
373 mlx5e_pps_event_handler(vpriv, &ptp_event);
374 break;
f62b8bb8
AV		 375 default:
376 break;
377 }
378}
379
f62b8bb8
AV		 380static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
381{
e0f46eb9 382 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 383}
384
385static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
386{
e0f46eb9 387 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 388 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 389}
390
7e426671
TT		 391static inline int mlx5e_get_wqe_mtt_sz(void)
392{
393 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
394 * To avoid copying garbage after the mtt array, we allocate
395 * a little more.
396 */
397 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
398 MLX5_UMR_MTT_ALIGNMENT);
399}
400
31391048
SM		 401static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
402 struct mlx5e_icosq *sq,
403 struct mlx5e_umr_wqe *wqe,
404 u16 ix)
7e426671
TT		 405{
406 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
407 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
408 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 409 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 410 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
411 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
412
413 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
414 ds_cnt);
415 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
416 cseg->imm = rq->mkey_be;
417
418 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 419 ucseg->xlt_octowords =
7e426671
TT		 420 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
421 ucseg->bsf_octowords =
422 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
423 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
424
425 dseg->lkey = sq->mkey_be;
426 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
427}
428
429static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
430 struct mlx5e_channel *c)
431{
432 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
433 int mtt_sz = mlx5e_get_wqe_mtt_sz();
434 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
435 int i;
436
21c59685
SM		 437 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
438 GFP_KERNEL, cpu_to_node(c->cpu));
439 if (!rq->mpwqe.info)
7e426671
TT		 440 goto err_out;
441
442 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 443 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 444 cpu_to_node(c->cpu));
21c59685 445 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 446 goto err_free_wqe_info;
447
448 for (i = 0; i < wq_sz; i++) {
21c59685 449 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 450
21c59685 451 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 452 MLX5_UMR_ALIGN);
453 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
454 PCI_DMA_TODEVICE);
455 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
456 goto err_unmap_mtts;
457
458 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
459 }
460
461 return 0;
462
463err_unmap_mtts:
464 while (--i >= 0) {
21c59685 465 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 466
467 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
468 PCI_DMA_TODEVICE);
469 }
21c59685 470 kfree(rq->mpwqe.mtt_no_align);
7e426671 471err_free_wqe_info:
21c59685 472 kfree(rq->mpwqe.info);
7e426671
TT		 473
474err_out:
475 return -ENOMEM;
476}
477
478static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
479{
480 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
481 int mtt_sz = mlx5e_get_wqe_mtt_sz();
482 int i;
483
484 for (i = 0; i < wq_sz; i++) {
21c59685 485 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 486
487 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
488 PCI_DMA_TODEVICE);
489 }
21c59685
SM		 490 kfree(rq->mpwqe.mtt_no_align);
491 kfree(rq->mpwqe.info);
7e426671
TT		 492}
493
a43b25da 494static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 495 u64 npages, u8 page_shift,
496 struct mlx5_core_mkey *umr_mkey)
3608ae77 497{
3608ae77
TT		 498 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
499 void *mkc;
500 u32 *in;
501 int err;
502
ec8b9981
TT		 503 if (!MLX5E_VALID_NUM_MTTS(npages))
504 return -EINVAL;
505
3608ae77
TT		 506 in = mlx5_vzalloc(inlen);
507 if (!in)
508 return -ENOMEM;
509
510 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
511
3608ae77
TT		 512 MLX5_SET(mkc, mkc, free, 1);
513 MLX5_SET(mkc, mkc, umr_en, 1);
514 MLX5_SET(mkc, mkc, lw, 1);
515 MLX5_SET(mkc, mkc, lr, 1);
516 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
517
518 MLX5_SET(mkc, mkc, qpn, 0xffffff);
519 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 520 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 521 MLX5_SET(mkc, mkc, translations_octword_size,
522 MLX5_MTT_OCTW(npages));
ec8b9981 523 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 524
ec8b9981 525 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 526
527 kvfree(in);
528 return err;
529}
530
a43b25da 531static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 532{
6a9764ef 533 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 534
a43b25da 535 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 536}
537
3b77235b 538static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 539 struct mlx5e_params *params,
540 struct mlx5e_rq_param *rqp,
3b77235b 541 struct mlx5e_rq *rq)
f62b8bb8 542{
a43b25da 543 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 544 void *rqc = rqp->rqc;
f62b8bb8 545 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 546 u32 byte_count;
1bfecfca
SM		 547 u32 frag_sz;
548 int npages;
f62b8bb8
AV		 549 int wq_sz;
550 int err;
551 int i;
552
6a9764ef 553 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 554
6a9764ef 555 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 556 &rq->wq_ctrl);
557 if (err)
558 return err;
559
560 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
561
562 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 563
6a9764ef 564 rq->wq_type = params->rq_wq_type;
7e426671
TT		 565 rq->pdev = c->pdev;
566 rq->netdev = c->netdev;
a43b25da 567 rq->tstamp = c->tstamp;
7e426671
TT		 568 rq->channel = c;
569 rq->ix = c->ix;
a43b25da 570 rq->mdev = mdev;
97bc402d 571
6a9764ef 572 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 573 if (IS_ERR(rq->xdp_prog)) {
574 err = PTR_ERR(rq->xdp_prog);
575 rq->xdp_prog = NULL;
576 goto err_rq_wq_destroy;
577 }
7e426671 578
d8bec2b2 579 if (rq->xdp_prog) {
b5503b99 580 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 581 rq->rx_headroom = XDP_PACKET_HEADROOM;
582 } else {
583 rq->buff.map_dir = DMA_FROM_DEVICE;
584 rq->rx_headroom = MLX5_RX_HEADROOM;
585 }
b5503b99 586
6a9764ef 587 switch (rq->wq_type) {
461017cb 588 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
a43b25da 589 if (mlx5e_is_vf_vport_rep(c->priv)) {
f5f82476
OG		 590 err = -EINVAL;
591 goto err_rq_wq_destroy;
592 }
593
461017cb
TT		 594 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
595 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 596 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 597
6a9764ef
SM		 598 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
599 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 600
601 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
602 byte_count = rq->buff.wqe_sz;
ec8b9981 603
a43b25da 604 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 605 if (err)
606 goto err_rq_wq_destroy;
ec8b9981
TT		 607 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
608
609 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
610 if (err)
611 goto err_destroy_umr_mkey;
461017cb
TT		 612 break;
613 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 614 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
615 GFP_KERNEL, cpu_to_node(c->cpu));
616 if (!rq->dma_info) {
461017cb
TT		 617 err = -ENOMEM;
618 goto err_rq_wq_destroy;
619 }
1bfecfca 620
a43b25da 621 if (mlx5e_is_vf_vport_rep(c->priv))
f5f82476
OG		 622 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
623 else
624 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
625
461017cb 626 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 627 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 628
6a9764ef
SM		 629 rq->buff.wqe_sz = params->lro_en ?
630 params->lro_wqe_sz :
a43b25da 631 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 632 byte_count = rq->buff.wqe_sz;
633
634 /* calc the required page order */
d8bec2b2 635 frag_sz = rq->rx_headroom +
1bfecfca
SM		 636 byte_count /* packet data */ +
637 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
638 frag_sz = SKB_DATA_ALIGN(frag_sz);
639
640 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
641 rq->buff.page_order = order_base_2(npages);
642
461017cb 643 byte_count |= MLX5_HW_START_PADDING;
7e426671 644 rq->mkey_be = c->mkey_be;
461017cb 645 }
f62b8bb8
AV		 646
647 for (i = 0; i < wq_sz; i++) {
648 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
649
461017cb 650 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 651 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 652 }
653
cb3c7fd4 654 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 655 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 656 rq->page_cache.head = 0;
657 rq->page_cache.tail = 0;
658
f62b8bb8
AV		 659 return 0;
660
ec8b9981
TT		 661err_destroy_umr_mkey:
662 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
663
f62b8bb8 664err_rq_wq_destroy:
97bc402d
DB		 665 if (rq->xdp_prog)
666 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 667 mlx5_wq_destroy(&rq->wq_ctrl);
668
669 return err;
670}
671
3b77235b 672static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 673{
4415a031
TT		 674 int i;
675
86994156
RS		 676 if (rq->xdp_prog)
677 bpf_prog_put(rq->xdp_prog);
678
461017cb
TT		 679 switch (rq->wq_type) {
680 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 681 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 682 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 683 break;
684 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 685 kfree(rq->dma_info);
461017cb
TT		 686 }
687
4415a031
TT		 688 for (i = rq->page_cache.head; i != rq->page_cache.tail;
689 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
690 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
691
692 mlx5e_page_release(rq, dma_info, false);
693 }
f62b8bb8
AV		 694 mlx5_wq_destroy(&rq->wq_ctrl);
695}
696
6a9764ef
SM		 697static int mlx5e_create_rq(struct mlx5e_rq *rq,
698 struct mlx5e_rq_param *param)
f62b8bb8 699{
a43b25da 700 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 701
702 void *in;
703 void *rqc;
704 void *wq;
705 int inlen;
706 int err;
707
708 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
709 sizeof(u64) * rq->wq_ctrl.buf.npages;
710 in = mlx5_vzalloc(inlen);
711 if (!in)
712 return -ENOMEM;
713
714 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
715 wq = MLX5_ADDR_OF(rqc, rqc, wq);
716
717 memcpy(rqc, param->rqc, sizeof(param->rqc));
718
97de9f31 719 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 721 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 722 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 723 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
724
725 mlx5_fill_page_array(&rq->wq_ctrl.buf,
726 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
727
7db22ffb 728 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 729
730 kvfree(in);
731
732 return err;
733}
734
36350114
GP		 735static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
736 int next_state)
f62b8bb8
AV		 737{
738 struct mlx5e_channel *c = rq->channel;
a43b25da 739 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 740
741 void *in;
742 void *rqc;
743 int inlen;
744 int err;
745
746 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
747 in = mlx5_vzalloc(inlen);
748 if (!in)
749 return -ENOMEM;
750
751 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
752
753 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
754 MLX5_SET(rqc, rqc, state, next_state);
755
7db22ffb 756 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 757
758 kvfree(in);
759
760 return err;
761}
762
102722fc
GE		 763static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
764{
765 struct mlx5e_channel *c = rq->channel;
766 struct mlx5e_priv *priv = c->priv;
767 struct mlx5_core_dev *mdev = priv->mdev;
768
769 void *in;
770 void *rqc;
771 int inlen;
772 int err;
773
774 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
775 in = mlx5_vzalloc(inlen);
776 if (!in)
777 return -ENOMEM;
778
779 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
780
781 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
782 MLX5_SET64(modify_rq_in, in, modify_bitmask,
783 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
784 MLX5_SET(rqc, rqc, scatter_fcs, enable);
785 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
786
787 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
788
789 kvfree(in);
790
791 return err;
792}
793
36350114
GP		 794static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
795{
796 struct mlx5e_channel *c = rq->channel;
a43b25da 797 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 798 void *in;
799 void *rqc;
800 int inlen;
801 int err;
802
803 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
804 in = mlx5_vzalloc(inlen);
805 if (!in)
806 return -ENOMEM;
807
808 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
809
810 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 811 MLX5_SET64(modify_rq_in, in, modify_bitmask,
812 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 813 MLX5_SET(rqc, rqc, vsd, vsd);
814 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
815
816 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
817
818 kvfree(in);
819
820 return err;
821}
822
3b77235b 823static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 824{
a43b25da 825 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 826}
827
828static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
829{
01c196a2 830 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 831 struct mlx5e_channel *c = rq->channel;
a43b25da 832
f62b8bb8 833 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 834 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 835
01c196a2 836 while (time_before(jiffies, exp_time)) {
6a9764ef 837 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 838 return 0;
839
840 msleep(20);
841 }
842
a43b25da 843 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 844 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 845 return -ETIMEDOUT;
846}
847
f2fde18c
SM		 848static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
849{
850 struct mlx5_wq_ll *wq = &rq->wq;
851 struct mlx5e_rx_wqe *wqe;
852 __be16 wqe_ix_be;
853 u16 wqe_ix;
854
8484f9ed
SM		 855 /* UMR WQE (if in progress) is always at wq->head */
856 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 857 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 858
f2fde18c
SM		 859 while (!mlx5_wq_ll_is_empty(wq)) {
860 wqe_ix_be = *wq->tail_next;
861 wqe_ix = be16_to_cpu(wqe_ix_be);
862 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
863 rq->dealloc_wqe(rq, wqe_ix);
864 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
865 &wqe->next.next_wqe_index);
866 }
867}
868
f62b8bb8 869static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 870 struct mlx5e_params *params,
f62b8bb8
AV		 871 struct mlx5e_rq_param *param,
872 struct mlx5e_rq *rq)
873{
874 int err;
875
6a9764ef 876 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 877 if (err)
878 return err;
879
3b77235b 880 err = mlx5e_create_rq(rq, param);
f62b8bb8 881 if (err)
3b77235b 882 goto err_free_rq;
f62b8bb8 883
36350114 884 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 885 if (err)
3b77235b 886 goto err_destroy_rq;
f62b8bb8 887
6a9764ef 888 if (params->rx_am_enabled)
cb3c7fd4
GR		 889 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
890
f62b8bb8
AV		 891 return 0;
892
f62b8bb8
AV		 893err_destroy_rq:
894 mlx5e_destroy_rq(rq);
3b77235b
SM		 895err_free_rq:
896 mlx5e_free_rq(rq);
f62b8bb8
AV		 897
898 return err;
899}
900
acc6c595
SM		 901static void mlx5e_activate_rq(struct mlx5e_rq *rq)
902{
903 struct mlx5e_icosq *sq = &rq->channel->icosq;
904 u16 pi = sq->pc & sq->wq.sz_m1;
905 struct mlx5e_tx_wqe *nopwqe;
906
907 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
908 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
909 sq->db.ico_wqe[pi].num_wqebbs = 1;
910 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
911 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
912}
913
914static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 915{
c0f1147d 916 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 917 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 918}
cb3c7fd4 919
acc6c595
SM		 920static void mlx5e_close_rq(struct mlx5e_rq *rq)
921{
922 cancel_work_sync(&rq->am.work);
f62b8bb8 923 mlx5e_destroy_rq(rq);
3b77235b
SM		 924 mlx5e_free_rx_descs(rq);
925 mlx5e_free_rq(rq);
f62b8bb8
AV		 926}
927
31391048 928static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 929{
31391048 930 kfree(sq->db.di);
b5503b99
SM		 931}
932
31391048 933static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 934{
935 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
936
31391048 937 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 938 GFP_KERNEL, numa);
31391048
SM		 939 if (!sq->db.di) {
940 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 941 return -ENOMEM;
942 }
943
944 return 0;
945}
946
31391048 947static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 948 struct mlx5e_params *params,
31391048
SM		 949 struct mlx5e_sq_param *param,
950 struct mlx5e_xdpsq *sq)
951{
952 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 953 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 954 int err;
955
956 sq->pdev = c->pdev;
957 sq->mkey_be = c->mkey_be;
958 sq->channel = c;
959 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 960 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 961
962 param->wq.db_numa_node = cpu_to_node(c->cpu);
963 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
964 if (err)
965 return err;
966 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
967
968 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
969 if (err)
970 goto err_sq_wq_destroy;
971
972 return 0;
973
974err_sq_wq_destroy:
975 mlx5_wq_destroy(&sq->wq_ctrl);
976
977 return err;
978}
979
980static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
981{
982 mlx5e_free_xdpsq_db(sq);
983 mlx5_wq_destroy(&sq->wq_ctrl);
984}
985
986static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 987{
f10b7cc7 988 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 989}
990
31391048 991static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 992{
993 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
994
995 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
996 GFP_KERNEL, numa);
997 if (!sq->db.ico_wqe)
998 return -ENOMEM;
999
1000 return 0;
1001}
1002
31391048 1003static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1004 struct mlx5e_sq_param *param,
1005 struct mlx5e_icosq *sq)
f10b7cc7 1006{
31391048 1007 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1008 struct mlx5_core_dev *mdev = c->mdev;
31391048 1009 int err;
f10b7cc7 1010
31391048
SM		 1011 sq->pdev = c->pdev;
1012 sq->mkey_be = c->mkey_be;
1013 sq->channel = c;
1014 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1015
31391048
SM		 1016 param->wq.db_numa_node = cpu_to_node(c->cpu);
1017 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1018 if (err)
1019 return err;
1020 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1021
31391048
SM		 1022 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1023 if (err)
1024 goto err_sq_wq_destroy;
1025
1026 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1027
1028 return 0;
31391048
SM		 1029
1030err_sq_wq_destroy:
1031 mlx5_wq_destroy(&sq->wq_ctrl);
1032
1033 return err;
f62b8bb8
AV		 1034}
1035
31391048 1036static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1037{
31391048
SM		 1038 mlx5e_free_icosq_db(sq);
1039 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1040}
1041
31391048 1042static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1043{
31391048
SM		 1044 kfree(sq->db.wqe_info);
1045 kfree(sq->db.dma_fifo);
1046 kfree(sq->db.skb);
f10b7cc7
SM		 1047}
1048
31391048 1049static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1050{
31391048
SM		 1051 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1052 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1053
1054 sq->db.skb = kzalloc_node(wq_sz * sizeof(*sq->db.skb),
1055 GFP_KERNEL, numa);
1056 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1057 GFP_KERNEL, numa);
1058 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1059 GFP_KERNEL, numa);
1060 if (!sq->db.skb || !sq->db.dma_fifo || !sq->db.wqe_info) {
1061 mlx5e_free_txqsq_db(sq);
1062 return -ENOMEM;
b5503b99 1063 }
31391048
SM		 1064
1065 sq->dma_fifo_mask = df_sz - 1;
1066
1067 return 0;
b5503b99
SM		 1068}
1069
31391048 1070static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1071 int txq_ix,
6a9764ef 1072 struct mlx5e_params *params,
31391048
SM		 1073 struct mlx5e_sq_param *param,
1074 struct mlx5e_txqsq *sq)
f62b8bb8 1075{
31391048 1076 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1077 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1078 int err;
1079
f10b7cc7 1080 sq->pdev = c->pdev;
a43b25da 1081 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1082 sq->mkey_be = c->mkey_be;
1083 sq->channel = c;
acc6c595 1084 sq->txq_ix = txq_ix;
aff26157 1085 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1086 sq->max_inline = params->tx_max_inline;
1087 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1088
311c7c71 1089 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1090 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1091 if (err)
aff26157 1092 return err;
31391048 1093 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1094
31391048 1095 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1096 if (err)
f62b8bb8
AV		 1097 goto err_sq_wq_destroy;
1098
31391048 1099 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1100
1101 return 0;
1102
1103err_sq_wq_destroy:
1104 mlx5_wq_destroy(&sq->wq_ctrl);
1105
f62b8bb8
AV		 1106 return err;
1107}
1108
31391048 1109static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1110{
31391048 1111 mlx5e_free_txqsq_db(sq);
f62b8bb8 1112 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1113}
1114
33ad9711
SM		 1115struct mlx5e_create_sq_param {
1116 struct mlx5_wq_ctrl *wq_ctrl;
1117 u32 cqn;
1118 u32 tisn;
1119 u8 tis_lst_sz;
1120 u8 min_inline_mode;
1121};
1122
a43b25da 1123static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1124 struct mlx5e_sq_param *param,
1125 struct mlx5e_create_sq_param *csp,
1126 u32 *sqn)
f62b8bb8 1127{
f62b8bb8
AV		 1128 void *in;
1129 void *sqc;
1130 void *wq;
1131 int inlen;
1132 int err;
1133
1134 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1135 sizeof(u64) * csp->wq_ctrl->buf.npages;
f62b8bb8
AV		 1136 in = mlx5_vzalloc(inlen);
1137 if (!in)
1138 return -ENOMEM;
1139
1140 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1141 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1142
1143 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1144 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1145 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1146 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1147
1148 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1149 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1150
33ad9711 1151 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1152
1153 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1154 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1155 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1156 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1157 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1158
33ad9711 1159 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1160
33ad9711 1161 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1162
1163 kvfree(in);
1164
1165 return err;
1166}
1167
33ad9711
SM		 1168struct mlx5e_modify_sq_param {
1169 int curr_state;
1170 int next_state;
1171 bool rl_update;
1172 int rl_index;
1173};
1174
a43b25da 1175static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1176 struct mlx5e_modify_sq_param *p)
f62b8bb8 1177{
f62b8bb8
AV		 1178 void *in;
1179 void *sqc;
1180 int inlen;
1181 int err;
1182
1183 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1184 in = mlx5_vzalloc(inlen);
1185 if (!in)
1186 return -ENOMEM;
1187
1188 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1189
33ad9711
SM		 1190 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1191 MLX5_SET(sqc, sqc, state, p->next_state);
1192 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1193 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1194 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1195 }
f62b8bb8 1196
33ad9711 1197 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1198
1199 kvfree(in);
1200
1201 return err;
1202}
1203
a43b25da 1204static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1205{
a43b25da 1206 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1207}
1208
a43b25da 1209static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1210 struct mlx5e_sq_param *param,
1211 struct mlx5e_create_sq_param *csp,
1212 u32 *sqn)
f62b8bb8 1213{
33ad9711 1214 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1215 int err;
1216
a43b25da 1217 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1218 if (err)
1219 return err;
1220
1221 msp.curr_state = MLX5_SQC_STATE_RST;
1222 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1223 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1224 if (err)
a43b25da 1225 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1226
1227 return err;
1228}
1229
7f859ecf
SM		 1230static int mlx5e_set_sq_maxrate(struct net_device *dev,
1231 struct mlx5e_txqsq *sq, u32 rate);
1232
31391048 1233static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1234 u32 tisn,
acc6c595 1235 int txq_ix,
6a9764ef 1236 struct mlx5e_params *params,
31391048
SM		 1237 struct mlx5e_sq_param *param,
1238 struct mlx5e_txqsq *sq)
1239{
1240 struct mlx5e_create_sq_param csp = {};
7f859ecf 1241 u32 tx_rate;
f62b8bb8
AV		 1242 int err;
1243
6a9764ef 1244 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1245 if (err)
1246 return err;
1247
a43b25da 1248 csp.tisn = tisn;
31391048 1249 csp.tis_lst_sz = 1;
33ad9711
SM		 1250 csp.cqn = sq->cq.mcq.cqn;
1251 csp.wq_ctrl = &sq->wq_ctrl;
1252 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1253 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1254 if (err)
31391048 1255 goto err_free_txqsq;
f62b8bb8 1256
a43b25da 1257 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1258 if (tx_rate)
a43b25da 1259 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1260
f62b8bb8
AV		 1261 return 0;
1262
31391048 1263err_free_txqsq:
3b77235b 1264 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1265 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1266
1267 return err;
1268}
1269
acc6c595
SM		 1270static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1271{
a43b25da 1272 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1273 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1274 netdev_tx_reset_queue(sq->txq);
1275 netif_tx_start_queue(sq->txq);
1276}
1277
f62b8bb8
AV		 1278static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1279{
1280 __netif_tx_lock_bh(txq);
1281 netif_tx_stop_queue(txq);
1282 __netif_tx_unlock_bh(txq);
1283}
1284
acc6c595 1285static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1286{
33ad9711 1287 struct mlx5e_channel *c = sq->channel;
33ad9711 1288
c0f1147d 1289 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1290 /* prevent netif_tx_wake_queue */
33ad9711 1291 napi_synchronize(&c->napi);
29429f33 1292
31391048 1293 netif_tx_disable_queue(sq->txq);
f62b8bb8 1294
31391048
SM		 1295 /* last doorbell out, godspeed .. */
1296 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1297 struct mlx5e_tx_wqe *nop;
864b2d71 1298
31391048
SM		 1299 sq->db.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1300 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1301 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1302 }
acc6c595
SM		 1303}
1304
1305static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1306{
1307 struct mlx5e_channel *c = sq->channel;
a43b25da 1308 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1309
a43b25da 1310 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1311 if (sq->rate_limit)
1312 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1313 mlx5e_free_txqsq_descs(sq);
1314 mlx5e_free_txqsq(sq);
1315}
1316
1317static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1318 struct mlx5e_params *params,
31391048
SM		 1319 struct mlx5e_sq_param *param,
1320 struct mlx5e_icosq *sq)
1321{
1322 struct mlx5e_create_sq_param csp = {};
1323 int err;
1324
6a9764ef 1325 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1326 if (err)
1327 return err;
1328
1329 csp.cqn = sq->cq.mcq.cqn;
1330 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1331 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1332 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1333 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1334 if (err)
1335 goto err_free_icosq;
1336
1337 return 0;
1338
1339err_free_icosq:
1340 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341 mlx5e_free_icosq(sq);
1342
1343 return err;
1344}
1345
1346static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1347{
1348 struct mlx5e_channel *c = sq->channel;
1349
1350 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351 napi_synchronize(&c->napi);
1352
a43b25da 1353 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1354 mlx5e_free_icosq(sq);
1355}
1356
1357static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1358 struct mlx5e_params *params,
31391048
SM		 1359 struct mlx5e_sq_param *param,
1360 struct mlx5e_xdpsq *sq)
1361{
1362 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1363 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1364 unsigned int inline_hdr_sz = 0;
1365 int err;
1366 int i;
1367
6a9764ef 1368 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1369 if (err)
1370 return err;
1371
1372 csp.tis_lst_sz = 1;
a43b25da 1373 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1374 csp.cqn = sq->cq.mcq.cqn;
1375 csp.wq_ctrl = &sq->wq_ctrl;
1376 csp.min_inline_mode = sq->min_inline_mode;
1377 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1378 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1379 if (err)
1380 goto err_free_xdpsq;
1381
1382 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1383 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1384 ds_cnt++;
1385 }
1386
1387 /* Pre initialize fixed WQE fields */
1388 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1389 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1390 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1391 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1392 struct mlx5_wqe_data_seg *dseg;
1393
1394 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1395 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1396
1397 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1398 dseg->lkey = sq->mkey_be;
1399 }
1400
1401 return 0;
1402
1403err_free_xdpsq:
1404 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1405 mlx5e_free_xdpsq(sq);
1406
1407 return err;
1408}
1409
1410static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1411{
1412 struct mlx5e_channel *c = sq->channel;
1413
1414 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415 napi_synchronize(&c->napi);
1416
a43b25da 1417 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1418 mlx5e_free_xdpsq_descs(sq);
1419 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1420}
1421
95b6c6a5
EBE		 1422static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1423 struct mlx5e_cq_param *param,
1424 struct mlx5e_cq *cq)
f62b8bb8 1425{
f62b8bb8
AV		 1426 struct mlx5_core_cq *mcq = &cq->mcq;
1427 int eqn_not_used;
0b6e26ce 1428 unsigned int irqn;
f62b8bb8
AV		 1429 int err;
1430 u32 i;
1431
f62b8bb8
AV		 1432 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1433 &cq->wq_ctrl);
1434 if (err)
1435 return err;
1436
1437 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1438
f62b8bb8
AV		 1439 mcq->cqe_sz = 64;
1440 mcq->set_ci_db = cq->wq_ctrl.db.db;
1441 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1442 *mcq->set_ci_db = 0;
1443 *mcq->arm_db = 0;
1444 mcq->vector = param->eq_ix;
1445 mcq->comp = mlx5e_completion_event;
1446 mcq->event = mlx5e_cq_error_event;
1447 mcq->irqn = irqn;
f62b8bb8
AV		 1448
1449 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1450 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1451
1452 cqe->op_own = 0xf1;
1453 }
1454
a43b25da 1455 cq->mdev = mdev;
f62b8bb8
AV		 1456
1457 return 0;
1458}
1459
95b6c6a5
EBE		 1460static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1461 struct mlx5e_cq_param *param,
1462 struct mlx5e_cq *cq)
1463{
1464 struct mlx5_core_dev *mdev = c->priv->mdev;
1465 int err;
1466
1467 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1468 param->wq.db_numa_node = cpu_to_node(c->cpu);
1469 param->eq_ix = c->ix;
1470
1471 err = mlx5e_alloc_cq_common(mdev, param, cq);
1472
1473 cq->napi = &c->napi;
1474 cq->channel = c;
1475
1476 return err;
1477}
1478
3b77235b 1479static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1480{
1c1b5228 1481 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1482}
1483
3b77235b 1484static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1485{
a43b25da 1486 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1487 struct mlx5_core_cq *mcq = &cq->mcq;
1488
1489 void *in;
1490 void *cqc;
1491 int inlen;
0b6e26ce 1492 unsigned int irqn_not_used;
f62b8bb8
AV		 1493 int eqn;
1494 int err;
1495
1496 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1497 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1498 in = mlx5_vzalloc(inlen);
1499 if (!in)
1500 return -ENOMEM;
1501
1502 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1503
1504 memcpy(cqc, param->cqc, sizeof(param->cqc));
1505
1c1b5228
TT		 1506 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1507 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1508
1509 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1510
9908aa29 1511 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1512 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1513 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1514 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1515 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1516 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1517
1518 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1519
1520 kvfree(in);
1521
1522 if (err)
1523 return err;
1524
1525 mlx5e_cq_arm(cq);
1526
1527 return 0;
1528}
1529
3b77235b 1530static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1531{
a43b25da 1532 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1533}
1534
1535static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1536 struct mlx5e_cq_moder moder,
f62b8bb8 1537 struct mlx5e_cq_param *param,
6a9764ef 1538 struct mlx5e_cq *cq)
f62b8bb8 1539{
a43b25da 1540 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1541 int err;
f62b8bb8 1542
3b77235b 1543 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1544 if (err)
1545 return err;
1546
3b77235b 1547 err = mlx5e_create_cq(cq, param);
f62b8bb8 1548 if (err)
3b77235b 1549 goto err_free_cq;
f62b8bb8 1550
7524a5d8 1551 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1552 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1553 return 0;
1554
3b77235b
SM		 1555err_free_cq:
1556 mlx5e_free_cq(cq);
f62b8bb8
AV		 1557
1558 return err;
1559}
1560
1561static void mlx5e_close_cq(struct mlx5e_cq *cq)
1562{
f62b8bb8 1563 mlx5e_destroy_cq(cq);
3b77235b 1564 mlx5e_free_cq(cq);
f62b8bb8
AV		 1565}
1566
1567static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1568{
1569 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1570}
1571
1572static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1573 struct mlx5e_params *params,
f62b8bb8
AV		 1574 struct mlx5e_channel_param *cparam)
1575{
f62b8bb8
AV		 1576 int err;
1577 int tc;
1578
1579 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1580 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1581 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1582 if (err)
1583 goto err_close_tx_cqs;
f62b8bb8
AV		 1584 }
1585
1586 return 0;
1587
1588err_close_tx_cqs:
1589 for (tc--; tc >= 0; tc--)
1590 mlx5e_close_cq(&c->sq[tc].cq);
1591
1592 return err;
1593}
1594
1595static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1596{
1597 int tc;
1598
1599 for (tc = 0; tc < c->num_tc; tc++)
1600 mlx5e_close_cq(&c->sq[tc].cq);
1601}
1602
1603static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1604 struct mlx5e_params *params,
f62b8bb8
AV		 1605 struct mlx5e_channel_param *cparam)
1606{
1607 int err;
1608 int tc;
1609
6a9764ef
SM		 1610 for (tc = 0; tc < params->num_tc; tc++) {
1611 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1612
a43b25da
SM		 1613 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1614 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1615 if (err)
1616 goto err_close_sqs;
1617 }
1618
1619 return 0;
1620
1621err_close_sqs:
1622 for (tc--; tc >= 0; tc--)
31391048 1623 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1624
1625 return err;
1626}
1627
1628static void mlx5e_close_sqs(struct mlx5e_channel *c)
1629{
1630 int tc;
1631
1632 for (tc = 0; tc < c->num_tc; tc++)
31391048 1633 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1634}
1635
507f0c81 1636static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1637 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1638{
1639 struct mlx5e_priv *priv = netdev_priv(dev);
1640 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1641 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1642 u16 rl_index = 0;
1643 int err;
1644
1645 if (rate == sq->rate_limit)
1646 /* nothing to do */
1647 return 0;
1648
1649 if (sq->rate_limit)
1650 /* remove current rl index to free space to next ones */
1651 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1652
1653 sq->rate_limit = 0;
1654
1655 if (rate) {
1656 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1657 if (err) {
1658 netdev_err(dev, "Failed configuring rate %u: %d\n",
1659 rate, err);
1660 return err;
1661 }
1662 }
1663
33ad9711
SM		 1664 msp.curr_state = MLX5_SQC_STATE_RDY;
1665 msp.next_state = MLX5_SQC_STATE_RDY;
1666 msp.rl_index = rl_index;
1667 msp.rl_update = true;
a43b25da 1668 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1669 if (err) {
1670 netdev_err(dev, "Failed configuring rate %u: %d\n",
1671 rate, err);
1672 /* remove the rate from the table */
1673 if (rate)
1674 mlx5_rl_remove_rate(mdev, rate);
1675 return err;
1676 }
1677
1678 sq->rate_limit = rate;
1679 return 0;
1680}
1681
1682static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1683{
1684 struct mlx5e_priv *priv = netdev_priv(dev);
1685 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1686 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1687 int err = 0;
1688
1689 if (!mlx5_rl_is_supported(mdev)) {
1690 netdev_err(dev, "Rate limiting is not supported on this device\n");
1691 return -EINVAL;
1692 }
1693
1694 /* rate is given in Mb/sec, HW config is in Kb/sec */
1695 rate = rate << 10;
1696
1697 /* Check whether rate in valid range, 0 is always valid */
1698 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1699 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1700 return -ERANGE;
1701 }
1702
1703 mutex_lock(&priv->state_lock);
1704 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1705 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1706 if (!err)
1707 priv->tx_rates[index] = rate;
1708 mutex_unlock(&priv->state_lock);
1709
1710 return err;
1711}
1712
b4e029da
KH		 1713static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1714{
1715 return is_kdump_kernel() ?
1716 MLX5E_MIN_NUM_CHANNELS :
1717 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1718 MLX5E_MAX_NUM_CHANNELS);
1719}
1720
f62b8bb8 1721static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1722 struct mlx5e_params *params,
f62b8bb8
AV		 1723 struct mlx5e_channel_param *cparam,
1724 struct mlx5e_channel **cp)
1725{
6a9764ef 1726 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1727 struct net_device *netdev = priv->netdev;
1728 int cpu = mlx5e_get_cpu(priv, ix);
1729 struct mlx5e_channel *c;
1730 int err;
1731
1732 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1733 if (!c)
1734 return -ENOMEM;
1735
1736 c->priv = priv;
a43b25da
SM		 1737 c->mdev = priv->mdev;
1738 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1739 c->ix = ix;
1740 c->cpu = cpu;
1741 c->pdev = &priv->mdev->pdev->dev;
1742 c->netdev = priv->netdev;
b50d292b 1743 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1744 c->num_tc = params->num_tc;
1745 c->xdp = !!params->xdp_prog;
cb3c7fd4 1746
f62b8bb8
AV		 1747 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1748
6a9764ef 1749 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1750 if (err)
1751 goto err_napi_del;
1752
6a9764ef 1753 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1754 if (err)
1755 goto err_close_icosq_cq;
1756
6a9764ef 1757 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1758 if (err)
1759 goto err_close_tx_cqs;
f62b8bb8 1760
d7a0ecab 1761 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1762 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1763 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1764 if (err)
1765 goto err_close_rx_cq;
1766
f62b8bb8
AV		 1767 napi_enable(&c->napi);
1768
6a9764ef 1769 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1770 if (err)
1771 goto err_disable_napi;
1772
6a9764ef 1773 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1774 if (err)
1775 goto err_close_icosq;
1776
6a9764ef 1777 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1778 if (err)
1779 goto err_close_sqs;
b5503b99 1780
6a9764ef 1781 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1782 if (err)
b5503b99 1783 goto err_close_xdp_sq;
f62b8bb8 1784
f62b8bb8
AV		 1785 *cp = c;
1786
1787 return 0;
b5503b99 1788err_close_xdp_sq:
d7a0ecab 1789 if (c->xdp)
31391048 1790 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1791
1792err_close_sqs:
1793 mlx5e_close_sqs(c);
1794
d3c9bc27 1795err_close_icosq:
31391048 1796 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1797
f62b8bb8
AV		 1798err_disable_napi:
1799 napi_disable(&c->napi);
d7a0ecab 1800 if (c->xdp)
31871f87 1801 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1802
1803err_close_rx_cq:
f62b8bb8
AV		 1804 mlx5e_close_cq(&c->rq.cq);
1805
1806err_close_tx_cqs:
1807 mlx5e_close_tx_cqs(c);
1808
d3c9bc27
TT		 1809err_close_icosq_cq:
1810 mlx5e_close_cq(&c->icosq.cq);
1811
f62b8bb8
AV		 1812err_napi_del:
1813 netif_napi_del(&c->napi);
1814 kfree(c);
1815
1816 return err;
1817}
1818
acc6c595
SM		 1819static void mlx5e_activate_channel(struct mlx5e_channel *c)
1820{
1821 int tc;
1822
1823 for (tc = 0; tc < c->num_tc; tc++)
1824 mlx5e_activate_txqsq(&c->sq[tc]);
1825 mlx5e_activate_rq(&c->rq);
a43b25da 1826 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1827}
1828
1829static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1830{
1831 int tc;
1832
1833 mlx5e_deactivate_rq(&c->rq);
1834 for (tc = 0; tc < c->num_tc; tc++)
1835 mlx5e_deactivate_txqsq(&c->sq[tc]);
1836}
1837
f62b8bb8
AV		 1838static void mlx5e_close_channel(struct mlx5e_channel *c)
1839{
1840 mlx5e_close_rq(&c->rq);
b5503b99 1841 if (c->xdp)
31391048 1842 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1843 mlx5e_close_sqs(c);
31391048 1844 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1845 napi_disable(&c->napi);
b5503b99 1846 if (c->xdp)
31871f87 1847 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1848 mlx5e_close_cq(&c->rq.cq);
1849 mlx5e_close_tx_cqs(c);
d3c9bc27 1850 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1851 netif_napi_del(&c->napi);
7ae92ae5 1852
f62b8bb8
AV		 1853 kfree(c);
1854}
1855
1856static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1857 struct mlx5e_params *params,
f62b8bb8
AV		 1858 struct mlx5e_rq_param *param)
1859{
1860 void *rqc = param->rqc;
1861 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1862
6a9764ef 1863 switch (params->rq_wq_type) {
461017cb 1864 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1865 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1866 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1867 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1868 break;
1869 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1870 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1871 }
1872
f62b8bb8
AV		 1873 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1874 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1875 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1876 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1877 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1878 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1879 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1880
311c7c71 1881 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1882 param->wq.linear = 1;
1883}
1884
556dd1b9
TT		 1885static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1886{
1887 void *rqc = param->rqc;
1888 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1889
1890 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1891 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1892}
1893
d3c9bc27
TT		 1894static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1895 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1896{
1897 void *sqc = param->sqc;
1898 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1899
f62b8bb8 1900 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1901 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1902
311c7c71 1903 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1904}
1905
1906static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1907 struct mlx5e_params *params,
d3c9bc27
TT		 1908 struct mlx5e_sq_param *param)
1909{
1910 void *sqc = param->sqc;
1911 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1912
1913 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1914 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1915}
1916
1917static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1918 struct mlx5e_cq_param *param)
1919{
1920 void *cqc = param->cqc;
1921
30aa60b3 1922 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1923}
1924
1925static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1926 struct mlx5e_params *params,
f62b8bb8
AV		 1927 struct mlx5e_cq_param *param)
1928{
1929 void *cqc = param->cqc;
461017cb 1930 u8 log_cq_size;
f62b8bb8 1931
6a9764ef 1932 switch (params->rq_wq_type) {
461017cb 1933 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1934 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1935 break;
1936 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1937 log_cq_size = params->log_rq_size;
461017cb
TT		 1938 }
1939
1940 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1941 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1942 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1943 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1944 }
f62b8bb8
AV		 1945
1946 mlx5e_build_common_cq_param(priv, param);
1947}
1948
1949static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1950 struct mlx5e_params *params,
f62b8bb8
AV		 1951 struct mlx5e_cq_param *param)
1952{
1953 void *cqc = param->cqc;
1954
6a9764ef 1955 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1956
1957 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1958
1959 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1960}
1961
d3c9bc27 1962static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1963 u8 log_wq_size,
1964 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1965{
1966 void *cqc = param->cqc;
1967
1968 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1969
1970 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1971
1972 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1973}
1974
1975static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1976 u8 log_wq_size,
1977 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1978{
1979 void *sqc = param->sqc;
1980 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1981
1982 mlx5e_build_sq_param_common(priv, param);
1983
1984 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1985 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1986}
1987
b5503b99 1988static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1989 struct mlx5e_params *params,
b5503b99
SM		 1990 struct mlx5e_sq_param *param)
1991{
1992 void *sqc = param->sqc;
1993 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1994
1995 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1996 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1997}
1998
6a9764ef
SM		 1999static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2000 struct mlx5e_params *params,
2001 struct mlx5e_channel_param *cparam)
f62b8bb8 2002{
bc77b240 2003 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2004
6a9764ef
SM		 2005 mlx5e_build_rq_param(priv, params, &cparam->rq);
2006 mlx5e_build_sq_param(priv, params, &cparam->sq);
2007 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2008 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2009 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2010 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2011 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2012}
2013
55c2503d
SM		 2014int mlx5e_open_channels(struct mlx5e_priv *priv,
2015 struct mlx5e_channels *chs)
f62b8bb8 2016{
6b87663f 2017 struct mlx5e_channel_param *cparam;
03289b88 2018 int err = -ENOMEM;
f62b8bb8 2019 int i;
f62b8bb8 2020
6a9764ef 2021 chs->num = chs->params.num_channels;
03289b88 2022
ff9c852f 2023 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2024 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2025 if (!chs->c || !cparam)
2026 goto err_free;
f62b8bb8 2027
6a9764ef 2028 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2029 for (i = 0; i < chs->num; i++) {
6a9764ef 2030 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2031 if (err)
2032 goto err_close_channels;
2033 }
2034
6b87663f 2035 kfree(cparam);
f62b8bb8
AV		 2036 return 0;
2037
2038err_close_channels:
2039 for (i--; i >= 0; i--)
ff9c852f 2040 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2041
acc6c595 2042err_free:
ff9c852f 2043 kfree(chs->c);
6b87663f 2044 kfree(cparam);
ff9c852f 2045 chs->num = 0;
f62b8bb8
AV		 2046 return err;
2047}
2048
acc6c595 2049static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2050{
2051 int i;
2052
acc6c595
SM		 2053 for (i = 0; i < chs->num; i++)
2054 mlx5e_activate_channel(chs->c[i]);
2055}
2056
2057static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2058{
2059 int err = 0;
2060 int i;
2061
2062 for (i = 0; i < chs->num; i++) {
2063 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2064 if (err)
2065 break;
2066 }
2067
2068 return err;
2069}
2070
2071static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2072{
2073 int i;
2074
2075 for (i = 0; i < chs->num; i++)
2076 mlx5e_deactivate_channel(chs->c[i]);
2077}
2078
55c2503d 2079void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2080{
2081 int i;
c3b7c5c9 2082
ff9c852f
SM		 2083 for (i = 0; i < chs->num; i++)
2084 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2085
ff9c852f
SM		 2086 kfree(chs->c);
2087 chs->num = 0;
f62b8bb8
AV		 2088}
2089
a5f97fee
SM		 2090static int
2091mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2092{
2093 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2094 void *rqtc;
2095 int inlen;
2096 int err;
1da36696 2097 u32 *in;
a5f97fee 2098 int i;
f62b8bb8 2099
f62b8bb8
AV		 2100 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2101 in = mlx5_vzalloc(inlen);
2102 if (!in)
2103 return -ENOMEM;
2104
2105 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2106
2107 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2108 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2109
a5f97fee
SM		 2110 for (i = 0; i < sz; i++)
2111 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2112
398f3351
HHZ		 2113 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2114 if (!err)
2115 rqt->enabled = true;
f62b8bb8
AV		 2116
2117 kvfree(in);
1da36696
TT		 2118 return err;
2119}
2120
cb67b832 2121void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2122{
398f3351
HHZ		 2123 rqt->enabled = false;
2124 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2125}
2126
6bfd390b
HHZ		 2127static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
2128{
2129 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2130
a5f97fee 2131 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
6bfd390b
HHZ		 2132}
2133
cb67b832 2134int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2135{
398f3351 2136 struct mlx5e_rqt *rqt;
1da36696
TT		 2137 int err;
2138 int ix;
2139
6bfd390b 2140 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2141 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2142 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2143 if (err)
2144 goto err_destroy_rqts;
2145 }
2146
2147 return 0;
2148
2149err_destroy_rqts:
2150 for (ix--; ix >= 0; ix--)
398f3351 2151 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2152
f62b8bb8
AV		 2153 return err;
2154}
2155
a5f97fee
SM		 2156static int mlx5e_rx_hash_fn(int hfunc)
2157{
2158 return (hfunc == ETH_RSS_HASH_TOP) ?
2159 MLX5_RX_HASH_FN_TOEPLITZ :
2160 MLX5_RX_HASH_FN_INVERTED_XOR8;
2161}
2162
2163static int mlx5e_bits_invert(unsigned long a, int size)
2164{
2165 int inv = 0;
2166 int i;
2167
2168 for (i = 0; i < size; i++)
2169 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2170
2171 return inv;
2172}
2173
2174static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2175 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2176{
2177 int i;
2178
2179 for (i = 0; i < sz; i++) {
2180 u32 rqn;
2181
2182 if (rrp.is_rss) {
2183 int ix = i;
2184
2185 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2186 ix = mlx5e_bits_invert(i, ilog2(sz));
2187
6a9764ef 2188 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2189 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2190 } else {
2191 rqn = rrp.rqn;
2192 }
2193 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2194 }
2195}
2196
2197int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2198 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2199{
2200 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2201 void *rqtc;
2202 int inlen;
1da36696 2203 u32 *in;
5c50368f
AS		 2204 int err;
2205
5c50368f
AS		 2206 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2207 in = mlx5_vzalloc(inlen);
2208 if (!in)
2209 return -ENOMEM;
2210
2211 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2212
2213 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2214 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2215 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2216 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2217
2218 kvfree(in);
5c50368f
AS		 2219 return err;
2220}
2221
a5f97fee
SM		 2222static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2223 struct mlx5e_redirect_rqt_param rrp)
2224{
2225 if (!rrp.is_rss)
2226 return rrp.rqn;
2227
2228 if (ix >= rrp.rss.channels->num)
2229 return priv->drop_rq.rqn;
2230
2231 return rrp.rss.channels->c[ix]->rq.rqn;
2232}
2233
2234static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2235 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2236{
1da36696
TT		 2237 u32 rqtn;
2238 int ix;
2239
398f3351 2240 if (priv->indir_rqt.enabled) {
a5f97fee 2241 /* RSS RQ table */
398f3351 2242 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2243 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2244 }
2245
a5f97fee
SM		 2246 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2247 struct mlx5e_redirect_rqt_param direct_rrp = {
2248 .is_rss = false,
95632791
AM		 2249 {
2250 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2251 },
a5f97fee
SM		 2252 };
2253
2254 /* Direct RQ Tables */
398f3351
HHZ		 2255 if (!priv->direct_tir[ix].rqt.enabled)
2256 continue;
a5f97fee 2257
398f3351 2258 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2259 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2260 }
40ab6a6e
AS		 2261}
2262
a5f97fee
SM		 2263static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2264 struct mlx5e_channels *chs)
2265{
2266 struct mlx5e_redirect_rqt_param rrp = {
2267 .is_rss = true,
95632791
AM		 2268 {
2269 .rss = {
2270 .channels = chs,
2271 .hfunc = chs->params.rss_hfunc,
2272 }
2273 },
a5f97fee
SM		 2274 };
2275
2276 mlx5e_redirect_rqts(priv, rrp);
2277}
2278
2279static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2280{
2281 struct mlx5e_redirect_rqt_param drop_rrp = {
2282 .is_rss = false,
95632791
AM		 2283 {
2284 .rqn = priv->drop_rq.rqn,
2285 },
a5f97fee
SM		 2286 };
2287
2288 mlx5e_redirect_rqts(priv, drop_rrp);
2289}
2290
6a9764ef 2291static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2292{
6a9764ef 2293 if (!params->lro_en)
5c50368f
AS		 2294 return;
2295
2296#define ROUGH_MAX_L2_L3_HDR_SZ 256
2297
2298 MLX5_SET(tirc, tirc, lro_enable_mask,
2299 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2300 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2301 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2302 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2303 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2304}
2305
6a9764ef
SM		 2306void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2307 enum mlx5e_traffic_types tt,
2308 void *tirc)
bdfc028d 2309{
a100ff3e
GP		 2310 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2311
2312#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2313 MLX5_HASH_FIELD_SEL_DST_IP)
2314
2315#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2316 MLX5_HASH_FIELD_SEL_DST_IP |\
2317 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2318 MLX5_HASH_FIELD_SEL_L4_DPORT)
2319
2320#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2321 MLX5_HASH_FIELD_SEL_DST_IP |\
2322 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2323
6a9764ef
SM		 2324 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2325 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2326 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2327 rx_hash_toeplitz_key);
2328 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2329 rx_hash_toeplitz_key);
2330
2331 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2332 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2333 }
a100ff3e
GP		 2334
2335 switch (tt) {
2336 case MLX5E_TT_IPV4_TCP:
2337 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2338 MLX5_L3_PROT_TYPE_IPV4);
2339 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2340 MLX5_L4_PROT_TYPE_TCP);
2341 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2342 MLX5_HASH_IP_L4PORTS);
2343 break;
2344
2345 case MLX5E_TT_IPV6_TCP:
2346 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2347 MLX5_L3_PROT_TYPE_IPV6);
2348 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2349 MLX5_L4_PROT_TYPE_TCP);
2350 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2351 MLX5_HASH_IP_L4PORTS);
2352 break;
2353
2354 case MLX5E_TT_IPV4_UDP:
2355 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2356 MLX5_L3_PROT_TYPE_IPV4);
2357 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2358 MLX5_L4_PROT_TYPE_UDP);
2359 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2360 MLX5_HASH_IP_L4PORTS);
2361 break;
2362
2363 case MLX5E_TT_IPV6_UDP:
2364 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2365 MLX5_L3_PROT_TYPE_IPV6);
2366 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2367 MLX5_L4_PROT_TYPE_UDP);
2368 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2369 MLX5_HASH_IP_L4PORTS);
2370 break;
2371
2372 case MLX5E_TT_IPV4_IPSEC_AH:
2373 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2374 MLX5_L3_PROT_TYPE_IPV4);
2375 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2376 MLX5_HASH_IP_IPSEC_SPI);
2377 break;
2378
2379 case MLX5E_TT_IPV6_IPSEC_AH:
2380 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2381 MLX5_L3_PROT_TYPE_IPV6);
2382 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2383 MLX5_HASH_IP_IPSEC_SPI);
2384 break;
2385
2386 case MLX5E_TT_IPV4_IPSEC_ESP:
2387 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2388 MLX5_L3_PROT_TYPE_IPV4);
2389 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2390 MLX5_HASH_IP_IPSEC_SPI);
2391 break;
2392
2393 case MLX5E_TT_IPV6_IPSEC_ESP:
2394 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2395 MLX5_L3_PROT_TYPE_IPV6);
2396 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2397 MLX5_HASH_IP_IPSEC_SPI);
2398 break;
2399
2400 case MLX5E_TT_IPV4:
2401 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2402 MLX5_L3_PROT_TYPE_IPV4);
2403 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2404 MLX5_HASH_IP);
2405 break;
2406
2407 case MLX5E_TT_IPV6:
2408 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409 MLX5_L3_PROT_TYPE_IPV6);
2410 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2411 MLX5_HASH_IP);
2412 break;
2413 default:
2414 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2415 }
bdfc028d
TT		 2416}
2417
ab0394fe 2418static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2419{
2420 struct mlx5_core_dev *mdev = priv->mdev;
2421
2422 void *in;
2423 void *tirc;
2424 int inlen;
2425 int err;
ab0394fe 2426 int tt;
1da36696 2427 int ix;
5c50368f
AS		 2428
2429 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2430 in = mlx5_vzalloc(inlen);
2431 if (!in)
2432 return -ENOMEM;
2433
2434 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2435 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2436
6a9764ef 2437 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2438
1da36696 2439 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2440 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2441 inlen);
ab0394fe 2442 if (err)
1da36696 2443 goto free_in;
ab0394fe 2444 }
5c50368f 2445
6bfd390b 2446 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2447 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2448 in, inlen);
2449 if (err)
2450 goto free_in;
2451 }
2452
2453free_in:
5c50368f
AS		 2454 kvfree(in);
2455
2456 return err;
2457}
2458
cd255eff 2459static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2460{
40ab6a6e 2461 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2462 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2463 int err;
2464
cd255eff 2465 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2466 if (err)
2467 return err;
2468
cd255eff
SM		 2469 /* Update vport context MTU */
2470 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2471 return 0;
2472}
40ab6a6e 2473
cd255eff
SM		 2474static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2475{
2476 struct mlx5_core_dev *mdev = priv->mdev;
2477 u16 hw_mtu = 0;
2478 int err;
40ab6a6e 2479
cd255eff
SM		 2480 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2481 if (err || !hw_mtu) /* fallback to port oper mtu */
2482 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2483
2484 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2485}
2486
2e20a151 2487static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2488{
2e20a151 2489 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2490 u16 mtu;
2491 int err;
2492
2493 err = mlx5e_set_mtu(priv, netdev->mtu);
2494 if (err)
2495 return err;
40ab6a6e 2496
cd255eff
SM		 2497 mlx5e_query_mtu(priv, &mtu);
2498 if (mtu != netdev->mtu)
2499 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2500 __func__, mtu, netdev->mtu);
40ab6a6e 2501
cd255eff 2502 netdev->mtu = mtu;
40ab6a6e
AS		 2503 return 0;
2504}
2505
08fb1dac
SM		 2506static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2507{
2508 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2509 int nch = priv->channels.params.num_channels;
2510 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2511 int tc;
2512
2513 netdev_reset_tc(netdev);
2514
2515 if (ntc == 1)
2516 return;
2517
2518 netdev_set_num_tc(netdev, ntc);
2519
7ccdd084
RS		 2520 /* Map netdev TCs to offset 0
2521 * We have our own UP to TXQ mapping for QoS
2522 */
08fb1dac 2523 for (tc = 0; tc < ntc; tc++)
7ccdd084 2524 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2525}
2526
acc6c595
SM		 2527static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2528{
2529 struct mlx5e_channel *c;
2530 struct mlx5e_txqsq *sq;
2531 int i, tc;
2532
2533 for (i = 0; i < priv->channels.num; i++)
2534 for (tc = 0; tc < priv->profile->max_tc; tc++)
2535 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2536
2537 for (i = 0; i < priv->channels.num; i++) {
2538 c = priv->channels.c[i];
2539 for (tc = 0; tc < c->num_tc; tc++) {
2540 sq = &c->sq[tc];
2541 priv->txq2sq[sq->txq_ix] = sq;
2542 }
2543 }
2544}
2545
2546static void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2547{
9008ae07
SM		 2548 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2549 struct net_device *netdev = priv->netdev;
2550
2551 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2552 netif_set_real_num_tx_queues(netdev, num_txqs);
2553 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2554
acc6c595
SM		 2555 mlx5e_build_channels_tx_maps(priv);
2556 mlx5e_activate_channels(&priv->channels);
2557 netif_tx_start_all_queues(priv->netdev);
9008ae07
SM		 2558
2559 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2560 mlx5e_add_sqs_fwd_rules(priv);
2561
acc6c595 2562 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2563 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2564}
2565
2566static void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2567{
9008ae07
SM		 2568 mlx5e_redirect_rqts_to_drop(priv);
2569
2570 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2571 mlx5e_remove_sqs_fwd_rules(priv);
2572
acc6c595
SM		 2573 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2574 * polling for inactive tx queues.
2575 */
2576 netif_tx_stop_all_queues(priv->netdev);
2577 netif_tx_disable(priv->netdev);
2578 mlx5e_deactivate_channels(&priv->channels);
2579}
2580
55c2503d 2581void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2582 struct mlx5e_channels *new_chs,
2583 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2584{
2585 struct net_device *netdev = priv->netdev;
2586 int new_num_txqs;
2587
2588 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2589
2590 netif_carrier_off(netdev);
2591
2592 if (new_num_txqs < netdev->real_num_tx_queues)
2593 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2594
2595 mlx5e_deactivate_priv_channels(priv);
2596 mlx5e_close_channels(&priv->channels);
2597
2598 priv->channels = *new_chs;
2599
2e20a151
SM		 2600 /* New channels are ready to roll, modify HW settings if needed */
2601 if (hw_modify)
2602 hw_modify(priv);
2603
55c2503d
SM		 2604 mlx5e_refresh_tirs(priv, false);
2605 mlx5e_activate_priv_channels(priv);
2606
2607 mlx5e_update_carrier(priv);
2608}
2609
40ab6a6e
AS		 2610int mlx5e_open_locked(struct net_device *netdev)
2611{
2612 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2613 int err;
2614
2615 set_bit(MLX5E_STATE_OPENED, &priv->state);
2616
ff9c852f 2617 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2618 if (err)
343b29f3 2619 goto err_clear_state_opened_flag;
40ab6a6e 2620
b676f653 2621 mlx5e_refresh_tirs(priv, false);
acc6c595 2622 mlx5e_activate_priv_channels(priv);
ce89ef36 2623 mlx5e_update_carrier(priv);
ef9814de 2624 mlx5e_timestamp_init(priv);
be4891af 2625
cb67b832
HHZ		 2626 if (priv->profile->update_stats)
2627 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2628
9b37b07f 2629 return 0;
343b29f3
AS		 2630
2631err_clear_state_opened_flag:
2632 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2633 return err;
40ab6a6e
AS		 2634}
2635
cb67b832 2636int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2637{
2638 struct mlx5e_priv *priv = netdev_priv(netdev);
2639 int err;
2640
2641 mutex_lock(&priv->state_lock);
2642 err = mlx5e_open_locked(netdev);
2643 mutex_unlock(&priv->state_lock);
2644
2645 return err;
2646}
2647
2648int mlx5e_close_locked(struct net_device *netdev)
2649{
2650 struct mlx5e_priv *priv = netdev_priv(netdev);
2651
a1985740
AS		 2652 /* May already be CLOSED in case a previous configuration operation
2653 * (e.g RX/TX queue size change) that involves close&open failed.
2654 */
2655 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2656 return 0;
2657
40ab6a6e
AS		 2658 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2659
ef9814de 2660 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2661 netif_carrier_off(priv->netdev);
acc6c595
SM		 2662 mlx5e_deactivate_priv_channels(priv);
2663 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2664
2665 return 0;
2666}
2667
cb67b832 2668int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2669{
2670 struct mlx5e_priv *priv = netdev_priv(netdev);
2671 int err;
2672
26e59d80
MHY		 2673 if (!netif_device_present(netdev))
2674 return -ENODEV;
2675
40ab6a6e
AS		 2676 mutex_lock(&priv->state_lock);
2677 err = mlx5e_close_locked(netdev);
2678 mutex_unlock(&priv->state_lock);
2679
2680 return err;
2681}
2682
a43b25da 2683static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2684 struct mlx5e_rq *rq,
2685 struct mlx5e_rq_param *param)
40ab6a6e 2686{
40ab6a6e
AS		 2687 void *rqc = param->rqc;
2688 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2689 int err;
2690
2691 param->wq.db_numa_node = param->wq.buf_numa_node;
2692
2693 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2694 &rq->wq_ctrl);
2695 if (err)
2696 return err;
2697
a43b25da 2698 rq->mdev = mdev;
40ab6a6e
AS		 2699
2700 return 0;
2701}
2702
a43b25da 2703static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2704 struct mlx5e_cq *cq,
2705 struct mlx5e_cq_param *param)
40ab6a6e 2706{
95b6c6a5 2707 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2708}
2709
a43b25da
SM		 2710static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2711 struct mlx5e_rq *drop_rq)
40ab6a6e 2712{
a43b25da
SM		 2713 struct mlx5e_cq_param cq_param = {};
2714 struct mlx5e_rq_param rq_param = {};
2715 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2716 int err;
2717
556dd1b9 2718 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2719
a43b25da 2720 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2721 if (err)
2722 return err;
2723
3b77235b 2724 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2725 if (err)
3b77235b 2726 goto err_free_cq;
40ab6a6e 2727
a43b25da 2728 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2729 if (err)
3b77235b 2730 goto err_destroy_cq;
40ab6a6e 2731
a43b25da 2732 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2733 if (err)
3b77235b 2734 goto err_free_rq;
40ab6a6e
AS		 2735
2736 return 0;
2737
3b77235b 2738err_free_rq:
a43b25da 2739 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2740
2741err_destroy_cq:
a43b25da 2742 mlx5e_destroy_cq(cq);
40ab6a6e 2743
3b77235b 2744err_free_cq:
a43b25da 2745 mlx5e_free_cq(cq);
3b77235b 2746
40ab6a6e
AS		 2747 return err;
2748}
2749
a43b25da 2750static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2751{
a43b25da
SM		 2752 mlx5e_destroy_rq(drop_rq);
2753 mlx5e_free_rq(drop_rq);
2754 mlx5e_destroy_cq(&drop_rq->cq);
2755 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2756}
2757
2758static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2759{
2760 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2761 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2762 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2763
08fb1dac 2764 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2765 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2766
2767 if (mlx5_lag_is_lacp_owner(mdev))
2768 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2769
40ab6a6e
AS		 2770 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2771}
2772
2773static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2774{
2775 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2776}
2777
cb67b832 2778int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2779{
2780 int err;
2781 int tc;
2782
6bfd390b 2783 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2784 err = mlx5e_create_tis(priv, tc);
2785 if (err)
2786 goto err_close_tises;
2787 }
2788
2789 return 0;
2790
2791err_close_tises:
2792 for (tc--; tc >= 0; tc--)
2793 mlx5e_destroy_tis(priv, tc);
2794
2795 return err;
2796}
2797
cb67b832 2798void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2799{
2800 int tc;
2801
6bfd390b 2802 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2803 mlx5e_destroy_tis(priv, tc);
2804}
2805
6a9764ef
SM		 2806static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2807 enum mlx5e_traffic_types tt,
2808 u32 *tirc)
f62b8bb8 2809{
b50d292b 2810 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2811
6a9764ef 2812 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2813
4cbeaff5 2814 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2815 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2816 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2817}
2818
6a9764ef 2819static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2820{
b50d292b 2821 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2822
6a9764ef 2823 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2824
2825 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2826 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2827 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2828}
2829
6bfd390b 2830static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2831{
724b2aa1 2832 struct mlx5e_tir *tir;
f62b8bb8
AV		 2833 void *tirc;
2834 int inlen;
2835 int err;
1da36696 2836 u32 *in;
1da36696 2837 int tt;
f62b8bb8
AV		 2838
2839 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2840 in = mlx5_vzalloc(inlen);
2841 if (!in)
2842 return -ENOMEM;
2843
1da36696
TT		 2844 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2845 memset(in, 0, inlen);
724b2aa1 2846 tir = &priv->indir_tir[tt];
1da36696 2847 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2848 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2849 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2850 if (err)
40ab6a6e 2851 goto err_destroy_tirs;
f62b8bb8
AV		 2852 }
2853
6bfd390b
HHZ		 2854 kvfree(in);
2855
2856 return 0;
2857
2858err_destroy_tirs:
2859 for (tt--; tt >= 0; tt--)
2860 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2861
2862 kvfree(in);
2863
2864 return err;
2865}
2866
cb67b832 2867int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2868{
2869 int nch = priv->profile->max_nch(priv->mdev);
2870 struct mlx5e_tir *tir;
2871 void *tirc;
2872 int inlen;
2873 int err;
2874 u32 *in;
2875 int ix;
2876
2877 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2878 in = mlx5_vzalloc(inlen);
2879 if (!in)
2880 return -ENOMEM;
2881
1da36696
TT		 2882 for (ix = 0; ix < nch; ix++) {
2883 memset(in, 0, inlen);
724b2aa1 2884 tir = &priv->direct_tir[ix];
1da36696 2885 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2886 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2887 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2888 if (err)
2889 goto err_destroy_ch_tirs;
2890 }
2891
2892 kvfree(in);
2893
f62b8bb8
AV		 2894 return 0;
2895
1da36696
TT		 2896err_destroy_ch_tirs:
2897 for (ix--; ix >= 0; ix--)
724b2aa1 2898 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2899
1da36696 2900 kvfree(in);
f62b8bb8
AV		 2901
2902 return err;
2903}
2904
6bfd390b 2905static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2906{
2907 int i;
2908
1da36696 2909 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2910 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2911}
2912
cb67b832 2913void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2914{
2915 int nch = priv->profile->max_nch(priv->mdev);
2916 int i;
2917
2918 for (i = 0; i < nch; i++)
2919 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2920}
2921
102722fc
GE		 2922static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2923{
2924 int err = 0;
2925 int i;
2926
2927 for (i = 0; i < chs->num; i++) {
2928 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2929 if (err)
2930 return err;
2931 }
2932
2933 return 0;
2934}
2935
f6d96a20 2936static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2937{
2938 int err = 0;
2939 int i;
2940
ff9c852f
SM		 2941 for (i = 0; i < chs->num; i++) {
2942 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2943 if (err)
2944 return err;
2945 }
2946
2947 return 0;
2948}
2949
08fb1dac
SM		 2950static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2951{
2952 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2953 struct mlx5e_channels new_channels = {};
08fb1dac
SM		 2954 int err = 0;
2955
2956 if (tc && tc != MLX5E_MAX_NUM_TC)
2957 return -EINVAL;
2958
2959 mutex_lock(&priv->state_lock);
2960
6f9485af
SM		 2961 new_channels.params = priv->channels.params;
2962 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2963
6f9485af
SM		 2964 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2965 priv->channels.params = new_channels.params;
2966 goto out;
2967 }
08fb1dac 2968
6f9485af
SM		 2969 err = mlx5e_open_channels(priv, &new_channels);
2970 if (err)
2971 goto out;
08fb1dac 2972
2e20a151 2973 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2974out:
08fb1dac 2975 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2976 return err;
2977}
2978
2979static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2980 __be16 proto, struct tc_to_netdev *tc)
2981{
e8f887ac
AV		 2982 struct mlx5e_priv *priv = netdev_priv(dev);
2983
2984 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2985 goto mqprio;
2986
2987 switch (tc->type) {
e3a2b7ed
AV		 2988 case TC_SETUP_CLSFLOWER:
2989 switch (tc->cls_flower->command) {
2990 case TC_CLSFLOWER_REPLACE:
2991 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2992 case TC_CLSFLOWER_DESTROY:
2993 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2994 case TC_CLSFLOWER_STATS:
2995 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2996 }
e8f887ac
AV		 2997 default:
2998 return -EOPNOTSUPP;
2999 }
3000
3001mqprio:
67ba422e 3002 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 3003 return -EINVAL;
3004
56f36acd
AN		 3005 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3006
3007 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 3008}
3009
bc1f4470 3010static void
f62b8bb8
AV		 3011mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3012{
3013 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3014 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3015 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3016 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3017
370bad0f
OG		 3018 if (mlx5e_is_uplink_rep(priv)) {
3019 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3020 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3021 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3022 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3023 } else {
3024 stats->rx_packets = sstats->rx_packets;
3025 stats->rx_bytes = sstats->rx_bytes;
3026 stats->tx_packets = sstats->tx_packets;
3027 stats->tx_bytes = sstats->tx_bytes;
3028 stats->tx_dropped = sstats->tx_queue_dropped;
3029 }
269e6b3a
GP		 3030
3031 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3032
3033 stats->rx_length_errors =
9218b44d
GP		 3034 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3035 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3036 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3037 stats->rx_crc_errors =
9218b44d
GP		 3038 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3039 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3040 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 3041 stats->tx_carrier_errors =
9218b44d 3042 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 3043 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3044 stats->rx_frame_errors;
3045 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3046
3047 /* vport multicast also counts packets that are dropped due to steering
3048 * or rx out of buffer
3049 */
9218b44d
GP		 3050 stats->multicast =
3051 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 3052
f62b8bb8
AV		 3053}
3054
3055static void mlx5e_set_rx_mode(struct net_device *dev)
3056{
3057 struct mlx5e_priv *priv = netdev_priv(dev);
3058
7bb29755 3059 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3060}
3061
3062static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3063{
3064 struct mlx5e_priv *priv = netdev_priv(netdev);
3065 struct sockaddr *saddr = addr;
3066
3067 if (!is_valid_ether_addr(saddr->sa_data))
3068 return -EADDRNOTAVAIL;
3069
3070 netif_addr_lock_bh(netdev);
3071 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3072 netif_addr_unlock_bh(netdev);
3073
7bb29755 3074 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3075
3076 return 0;
3077}
3078
0e405443
GP		 3079#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3080 do { \
3081 if (enable) \
3082 netdev->features |= feature; \
3083 else \
3084 netdev->features &= ~feature; \
3085 } while (0)
3086
3087typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3088
3089static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3090{
3091 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3092 struct mlx5e_channels new_channels = {};
3093 int err = 0;
3094 bool reset;
f62b8bb8
AV		 3095
3096 mutex_lock(&priv->state_lock);
f62b8bb8 3097
2e20a151
SM		 3098 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3099 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3100
2e20a151
SM		 3101 new_channels.params = priv->channels.params;
3102 new_channels.params.lro_en = enable;
3103
3104 if (!reset) {
3105 priv->channels.params = new_channels.params;
3106 err = mlx5e_modify_tirs_lro(priv);
3107 goto out;
98e81b0a 3108 }
f62b8bb8 3109
2e20a151
SM		 3110 err = mlx5e_open_channels(priv, &new_channels);
3111 if (err)
3112 goto out;
0e405443 3113
2e20a151
SM		 3114 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3115out:
9b37b07f 3116 mutex_unlock(&priv->state_lock);
0e405443
GP		 3117 return err;
3118}
3119
3120static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3121{
3122 struct mlx5e_priv *priv = netdev_priv(netdev);
3123
3124 if (enable)
3125 mlx5e_enable_vlan_filter(priv);
3126 else
3127 mlx5e_disable_vlan_filter(priv);
3128
3129 return 0;
3130}
3131
3132static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3133{
3134 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3135
0e405443 3136 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3137 netdev_err(netdev,
3138 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3139 return -EINVAL;
3140 }
3141
0e405443
GP		 3142 return 0;
3143}
3144
94cb1ebb
EBE		 3145static int set_feature_rx_all(struct net_device *netdev, bool enable)
3146{
3147 struct mlx5e_priv *priv = netdev_priv(netdev);
3148 struct mlx5_core_dev *mdev = priv->mdev;
3149
3150 return mlx5_set_port_fcs(mdev, !enable);
3151}
3152
102722fc
GE		 3153static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3154{
3155 struct mlx5e_priv *priv = netdev_priv(netdev);
3156 int err;
3157
3158 mutex_lock(&priv->state_lock);
3159
3160 priv->channels.params.scatter_fcs_en = enable;
3161 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3162 if (err)
3163 priv->channels.params.scatter_fcs_en = !enable;
3164
3165 mutex_unlock(&priv->state_lock);
3166
3167 return err;
3168}
3169
36350114
GP		 3170static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3171{
3172 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3173 int err = 0;
36350114
GP		 3174
3175 mutex_lock(&priv->state_lock);
3176
6a9764ef 3177 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3178 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3179 goto unlock;
3180
3181 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3182 if (err)
6a9764ef 3183 priv->channels.params.vlan_strip_disable = enable;
36350114 3184
ff9c852f 3185unlock:
36350114
GP		 3186 mutex_unlock(&priv->state_lock);
3187
3188 return err;
3189}
3190
45bf454a
MG		 3191#ifdef CONFIG_RFS_ACCEL
3192static int set_feature_arfs(struct net_device *netdev, bool enable)
3193{
3194 struct mlx5e_priv *priv = netdev_priv(netdev);
3195 int err;
3196
3197 if (enable)
3198 err = mlx5e_arfs_enable(priv);
3199 else
3200 err = mlx5e_arfs_disable(priv);
3201
3202 return err;
3203}
3204#endif
3205
0e405443
GP		 3206static int mlx5e_handle_feature(struct net_device *netdev,
3207 netdev_features_t wanted_features,
3208 netdev_features_t feature,
3209 mlx5e_feature_handler feature_handler)
3210{
3211 netdev_features_t changes = wanted_features ^ netdev->features;
3212 bool enable = !!(wanted_features & feature);
3213 int err;
3214
3215 if (!(changes & feature))
3216 return 0;
3217
3218 err = feature_handler(netdev, enable);
3219 if (err) {
3220 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3221 enable ? "Enable" : "Disable", feature, err);
3222 return err;
3223 }
3224
3225 MLX5E_SET_FEATURE(netdev, feature, enable);
3226 return 0;
3227}
3228
3229static int mlx5e_set_features(struct net_device *netdev,
3230 netdev_features_t features)
3231{
3232 int err;
3233
3234 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3235 set_feature_lro);
3236 err |= mlx5e_handle_feature(netdev, features,
3237 NETIF_F_HW_VLAN_CTAG_FILTER,
3238 set_feature_vlan_filter);
3239 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3240 set_feature_tc_num_filters);
94cb1ebb
EBE		 3241 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3242 set_feature_rx_all);
102722fc
GE		 3243 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3244 set_feature_rx_fcs);
36350114
GP		 3245 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3246 set_feature_rx_vlan);
45bf454a
MG		 3247#ifdef CONFIG_RFS_ACCEL
3248 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3249 set_feature_arfs);
3250#endif
0e405443
GP		 3251
3252 return err ? -EINVAL : 0;
f62b8bb8
AV		 3253}
3254
3255static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3256{
3257 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3258 struct mlx5e_channels new_channels = {};
3259 int curr_mtu;
98e81b0a 3260 int err = 0;
506753b0 3261 bool reset;
f62b8bb8 3262
f62b8bb8 3263 mutex_lock(&priv->state_lock);
98e81b0a 3264
6a9764ef
SM		 3265 reset = !priv->channels.params.lro_en &&
3266 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3267 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3268
2e20a151 3269 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3270
2e20a151 3271 curr_mtu = netdev->mtu;
f62b8bb8 3272 netdev->mtu = new_mtu;
98e81b0a 3273
2e20a151
SM		 3274 if (!reset) {
3275 mlx5e_set_dev_port_mtu(priv);
3276 goto out;
3277 }
98e81b0a 3278
2e20a151
SM		 3279 new_channels.params = priv->channels.params;
3280 err = mlx5e_open_channels(priv, &new_channels);
3281 if (err) {
3282 netdev->mtu = curr_mtu;
3283 goto out;
3284 }
3285
3286 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3287
2e20a151
SM		 3288out:
3289 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3290 return err;
3291}
3292
ef9814de
EBE		 3293static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3294{
3295 switch (cmd) {
3296 case SIOCSHWTSTAMP:
3297 return mlx5e_hwstamp_set(dev, ifr);
3298 case SIOCGHWTSTAMP:
3299 return mlx5e_hwstamp_get(dev, ifr);
3300 default:
3301 return -EOPNOTSUPP;
3302 }
3303}
3304
66e49ded
SM		 3305static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3306{
3307 struct mlx5e_priv *priv = netdev_priv(dev);
3308 struct mlx5_core_dev *mdev = priv->mdev;
3309
3310 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3311}
3312
79aab093
MS		 3313static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3314 __be16 vlan_proto)
66e49ded
SM		 3315{
3316 struct mlx5e_priv *priv = netdev_priv(dev);
3317 struct mlx5_core_dev *mdev = priv->mdev;
3318
79aab093
MS		 3319 if (vlan_proto != htons(ETH_P_8021Q))
3320 return -EPROTONOSUPPORT;
3321
66e49ded
SM		 3322 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3323 vlan, qos);
3324}
3325
f942380c
MHY		 3326static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3327{
3328 struct mlx5e_priv *priv = netdev_priv(dev);
3329 struct mlx5_core_dev *mdev = priv->mdev;
3330
3331 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3332}
3333
1edc57e2
MHY		 3334static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3335{
3336 struct mlx5e_priv *priv = netdev_priv(dev);
3337 struct mlx5_core_dev *mdev = priv->mdev;
3338
3339 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3340}
bd77bf1c
MHY		 3341
3342static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3343 int max_tx_rate)
3344{
3345 struct mlx5e_priv *priv = netdev_priv(dev);
3346 struct mlx5_core_dev *mdev = priv->mdev;
3347
bd77bf1c 3348 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3349 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3350}
3351
66e49ded
SM		 3352static int mlx5_vport_link2ifla(u8 esw_link)
3353{
3354 switch (esw_link) {
3355 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3356 return IFLA_VF_LINK_STATE_DISABLE;
3357 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3358 return IFLA_VF_LINK_STATE_ENABLE;
3359 }
3360 return IFLA_VF_LINK_STATE_AUTO;
3361}
3362
3363static int mlx5_ifla_link2vport(u8 ifla_link)
3364{
3365 switch (ifla_link) {
3366 case IFLA_VF_LINK_STATE_DISABLE:
3367 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3368 case IFLA_VF_LINK_STATE_ENABLE:
3369 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3370 }
3371 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3372}
3373
3374static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3375 int link_state)
3376{
3377 struct mlx5e_priv *priv = netdev_priv(dev);
3378 struct mlx5_core_dev *mdev = priv->mdev;
3379
3380 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3381 mlx5_ifla_link2vport(link_state));
3382}
3383
3384static int mlx5e_get_vf_config(struct net_device *dev,
3385 int vf, struct ifla_vf_info *ivi)
3386{
3387 struct mlx5e_priv *priv = netdev_priv(dev);
3388 struct mlx5_core_dev *mdev = priv->mdev;
3389 int err;
3390
3391 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3392 if (err)
3393 return err;
3394 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3395 return 0;
3396}
3397
3398static int mlx5e_get_vf_stats(struct net_device *dev,
3399 int vf, struct ifla_vf_stats *vf_stats)
3400{
3401 struct mlx5e_priv *priv = netdev_priv(dev);
3402 struct mlx5_core_dev *mdev = priv->mdev;
3403
3404 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3405 vf_stats);
3406}
3407
1ad9a00a
PB		 3408static void mlx5e_add_vxlan_port(struct net_device *netdev,
3409 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3410{
3411 struct mlx5e_priv *priv = netdev_priv(netdev);
3412
974c3f30
AD		 3413 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3414 return;
3415
b3f63c3d
MF		 3416 if (!mlx5e_vxlan_allowed(priv->mdev))
3417 return;
3418
974c3f30 3419 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3420}
3421
1ad9a00a
PB		 3422static void mlx5e_del_vxlan_port(struct net_device *netdev,
3423 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3424{
3425 struct mlx5e_priv *priv = netdev_priv(netdev);
3426
974c3f30
AD		 3427 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3428 return;
3429
b3f63c3d
MF		 3430 if (!mlx5e_vxlan_allowed(priv->mdev))
3431 return;
3432
974c3f30 3433 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3434}
3435
3436static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3437 struct sk_buff *skb,
3438 netdev_features_t features)
3439{
3440 struct udphdr *udph;
3441 u16 proto;
3442 u16 port = 0;
3443
3444 switch (vlan_get_protocol(skb)) {
3445 case htons(ETH_P_IP):
3446 proto = ip_hdr(skb)->protocol;
3447 break;
3448 case htons(ETH_P_IPV6):
3449 proto = ipv6_hdr(skb)->nexthdr;
3450 break;
3451 default:
3452 goto out;
3453 }
3454
3455 if (proto == IPPROTO_UDP) {
3456 udph = udp_hdr(skb);
3457 port = be16_to_cpu(udph->dest);
3458 }
3459
3460 /* Verify if UDP port is being offloaded by HW */
3461 if (port && mlx5e_vxlan_lookup_port(priv, port))
3462 return features;
3463
3464out:
3465 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3466 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3467}
3468
3469static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3470 struct net_device *netdev,
3471 netdev_features_t features)
3472{
3473 struct mlx5e_priv *priv = netdev_priv(netdev);
3474
3475 features = vlan_features_check(skb, features);
3476 features = vxlan_features_check(skb, features);
3477
3478 /* Validate if the tunneled packet is being offloaded by HW */
3479 if (skb->encapsulation &&
3480 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3481 return mlx5e_vxlan_features_check(priv, skb, features);
3482
3483 return features;
3484}
3485
3947ca18
DJ		 3486static void mlx5e_tx_timeout(struct net_device *dev)
3487{
3488 struct mlx5e_priv *priv = netdev_priv(dev);
3489 bool sched_work = false;
3490 int i;
3491
3492 netdev_err(dev, "TX timeout detected\n");
3493
6a9764ef 3494 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3495 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3496
2c1ccc99 3497 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3498 continue;
3499 sched_work = true;
c0f1147d 3500 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3501 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3502 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3503 }
3504
3505 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3506 schedule_work(&priv->tx_timeout_work);
3507}
3508
86994156
RS		 3509static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3510{
3511 struct mlx5e_priv *priv = netdev_priv(netdev);
3512 struct bpf_prog *old_prog;
3513 int err = 0;
3514 bool reset, was_opened;
3515 int i;
3516
3517 mutex_lock(&priv->state_lock);
3518
3519 if ((netdev->features & NETIF_F_LRO) && prog) {
3520 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3521 err = -EINVAL;
3522 goto unlock;
3523 }
3524
3525 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3526 /* no need for full reset when exchanging programs */
6a9764ef 3527 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3528
3529 if (was_opened && reset)
3530 mlx5e_close_locked(netdev);
c54c0629
DB		 3531 if (was_opened && !reset) {
3532 /* num_channels is invariant here, so we can take the
3533 * batched reference right upfront.
3534 */
6a9764ef 3535 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3536 if (IS_ERR(prog)) {
3537 err = PTR_ERR(prog);
3538 goto unlock;
3539 }
3540 }
86994156 3541
c54c0629
DB		 3542 /* exchange programs, extra prog reference we got from caller
3543 * as long as we don't fail from this point onwards.
3544 */
6a9764ef 3545 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3546 if (old_prog)
3547 bpf_prog_put(old_prog);
3548
3549 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3550 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3551
3552 if (was_opened && reset)
3553 mlx5e_open_locked(netdev);
3554
3555 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3556 goto unlock;
3557
3558 /* exchanging programs w/o reset, we update ref counts on behalf
3559 * of the channels RQs here.
3560 */
ff9c852f
SM		 3561 for (i = 0; i < priv->channels.num; i++) {
3562 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3563
c0f1147d 3564 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3565 napi_synchronize(&c->napi);
3566 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3567
3568 old_prog = xchg(&c->rq.xdp_prog, prog);
3569
c0f1147d 3570 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3571 /* napi_schedule in case we have missed anything */
3572 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3573 napi_schedule(&c->napi);
3574
3575 if (old_prog)
3576 bpf_prog_put(old_prog);
3577 }
3578
3579unlock:
3580 mutex_unlock(&priv->state_lock);
3581 return err;
3582}
3583
3584static bool mlx5e_xdp_attached(struct net_device *dev)
3585{
3586 struct mlx5e_priv *priv = netdev_priv(dev);
3587
6a9764ef 3588 return !!priv->channels.params.xdp_prog;
86994156
RS		 3589}
3590
3591static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3592{
3593 switch (xdp->command) {
3594 case XDP_SETUP_PROG:
3595 return mlx5e_xdp_set(dev, xdp->prog);
3596 case XDP_QUERY_PROG:
3597 xdp->prog_attached = mlx5e_xdp_attached(dev);
3598 return 0;
3599 default:
3600 return -EINVAL;
3601 }
3602}
3603
80378384
CO		 3604#ifdef CONFIG_NET_POLL_CONTROLLER
3605/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3606 * reenabling interrupts.
3607 */
3608static void mlx5e_netpoll(struct net_device *dev)
3609{
3610 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3611 struct mlx5e_channels *chs = &priv->channels;
3612
80378384
CO		 3613 int i;
3614
ff9c852f
SM		 3615 for (i = 0; i < chs->num; i++)
3616 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3617}
3618#endif
3619
b0eed40e 3620static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3621 .ndo_open = mlx5e_open,
3622 .ndo_stop = mlx5e_close,
3623 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3624 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3625 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3626 .ndo_get_stats64 = mlx5e_get_stats,
3627 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3628 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3629 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3630 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3631 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3632 .ndo_change_mtu = mlx5e_change_mtu,
3633 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3634 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3635#ifdef CONFIG_RFS_ACCEL
3636 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3637#endif
3947ca18 3638 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3639 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3640#ifdef CONFIG_NET_POLL_CONTROLLER
3641 .ndo_poll_controller = mlx5e_netpoll,
3642#endif
b0eed40e
SM		 3643};
3644
3645static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3646 .ndo_open = mlx5e_open,
3647 .ndo_stop = mlx5e_close,
3648 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3649 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3650 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3651 .ndo_get_stats64 = mlx5e_get_stats,
3652 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3653 .ndo_set_mac_address = mlx5e_set_mac,
3654 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3655 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3656 .ndo_set_features = mlx5e_set_features,
3657 .ndo_change_mtu = mlx5e_change_mtu,
3658 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3659 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3660 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3661 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3662 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3663#ifdef CONFIG_RFS_ACCEL
3664 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3665#endif
b0eed40e
SM		 3666 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3667 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3668 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3669 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3670 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3671 .ndo_get_vf_config = mlx5e_get_vf_config,
3672 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3673 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3674 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3675 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3676#ifdef CONFIG_NET_POLL_CONTROLLER
3677 .ndo_poll_controller = mlx5e_netpoll,
3678#endif
370bad0f
OG		 3679 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3680 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3681};
3682
3683static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3684{
3685 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3686 return -EOPNOTSUPP;
f62b8bb8
AV		 3687 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3688 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3689 !MLX5_CAP_ETH(mdev, csum_cap) ||
3690 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3691 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3692 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3693 MLX5_CAP_FLOWTABLE(mdev,
3694 flow_table_properties_nic_receive.max_ft_level)
3695 < 3) {
f62b8bb8
AV		 3696 mlx5_core_warn(mdev,
3697 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3698 return -EOPNOTSUPP;
f62b8bb8 3699 }
66189961
TT		 3700 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3701 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3702 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3703 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3704
f62b8bb8
AV		 3705 return 0;
3706}
3707
58d52291
AS		 3708u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3709{
3710 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3711
3712 return bf_buf_size -
3713 sizeof(struct mlx5e_tx_wqe) +
3714 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3715}
3716
d8c9660d
TT		 3717void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3718 u32 *indirection_rqt, int len,
85082dba
TT		 3719 int num_channels)
3720{
d8c9660d
TT		 3721 int node = mdev->priv.numa_node;
3722 int node_num_of_cores;
85082dba
TT		 3723 int i;
3724
d8c9660d
TT		 3725 if (node == -1)
3726 node = first_online_node;
3727
3728 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3729
3730 if (node_num_of_cores)
3731 num_channels = min_t(int, num_channels, node_num_of_cores);
3732
85082dba
TT		 3733 for (i = 0; i < len; i++)
3734 indirection_rqt[i] = i % num_channels;
3735}
3736
b797a684
SM		 3737static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3738{
3739 enum pcie_link_width width;
3740 enum pci_bus_speed speed;
3741 int err = 0;
3742
3743 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3744 if (err)
3745 return err;
3746
3747 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3748 return -EINVAL;
3749
3750 switch (speed) {
3751 case PCIE_SPEED_2_5GT:
3752 *pci_bw = 2500 * width;
3753 break;
3754 case PCIE_SPEED_5_0GT:
3755 *pci_bw = 5000 * width;
3756 break;
3757 case PCIE_SPEED_8_0GT:
3758 *pci_bw = 8000 * width;
3759 break;
3760 default:
3761 return -EINVAL;
3762 }
3763
3764 return 0;
3765}
3766
3767static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3768{
3769 return (link_speed && pci_bw &&
3770 (pci_bw < 40000) && (pci_bw < link_speed));
3771}
3772
9908aa29
TT		 3773void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3774{
3775 params->rx_cq_period_mode = cq_period_mode;
3776
3777 params->rx_cq_moderation.pkts =
3778 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3779 params->rx_cq_moderation.usec =
3780 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3781
3782 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3783 params->rx_cq_moderation.usec =
3784 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3785
457fcd8a
SM		 3786 if (params->rx_am_enabled)
3787 params->rx_cq_moderation =
3788 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3789
6a9764ef
SM		 3790 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3791 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3792}
3793
2b029556
SM		 3794u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3795{
3796 int i;
3797
3798 /* The supported periods are organized in ascending order */
3799 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3800 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3801 break;
3802
3803 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3804}
3805
6a9764ef
SM		 3806static void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3807 struct mlx5e_params *params,
3808 u16 max_channels)
f62b8bb8 3809{
6a9764ef 3810 u8 cq_period_mode = 0;
b797a684
SM		 3811 u32 link_speed = 0;
3812 u32 pci_bw = 0;
2fc4bfb7 3813
6a9764ef
SM		 3814 params->num_channels = max_channels;
3815 params->num_tc = 1;
2b029556 3816
6a9764ef
SM		 3817 /* SQ */
3818 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3819 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3820 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3821
b797a684 3822 /* set CQE compression */
6a9764ef 3823 params->rx_cqe_compress_def = false;
b797a684 3824 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
6a9764ef 3825 MLX5_CAP_GEN(mdev, vport_group_manager)) {
b797a684
SM		 3826 mlx5e_get_max_linkspeed(mdev, &link_speed);
3827 mlx5e_get_pci_bw(mdev, &pci_bw);
3828 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
6a9764ef
SM		 3829 link_speed, pci_bw);
3830 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
b797a684 3831 }
6a9764ef
SM		 3832 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3833
3834 /* RQ */
3835 mlx5e_set_rq_params(mdev, params);
b797a684 3836
6a9764ef
SM		 3837 /* HW LRO */
3838 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3839 params->lro_en = true;
3840 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3841
6a9764ef
SM		 3842 /* CQ moderation params */
3843 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3844 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3845 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3846 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3847 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3848
6a9764ef
SM		 3849 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3850 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3851
6a9764ef
SM		 3852 /* TX inline */
3853 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3854 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3855 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3856 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3857 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3858
6a9764ef
SM		 3859 /* RSS */
3860 params->rss_hfunc = ETH_RSS_HASH_XOR;
3861 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3862 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3863 MLX5E_INDIR_RQT_SIZE, max_channels);
3864}
f62b8bb8 3865
6a9764ef
SM		 3866static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3867 struct net_device *netdev,
3868 const struct mlx5e_profile *profile,
3869 void *ppriv)
3870{
3871 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3872
6a9764ef
SM		 3873 priv->mdev = mdev;
3874 priv->netdev = netdev;
3875 priv->profile = profile;
3876 priv->ppriv = ppriv;
2d75b2bc 3877
6a9764ef 3878 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3879
f62b8bb8
AV		 3880 mutex_init(&priv->state_lock);
3881
3882 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3883 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3884 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3885 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3886}
3887
3888static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3889{
3890 struct mlx5e_priv *priv = netdev_priv(netdev);
3891
e1d7d349 3892 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3893 if (is_zero_ether_addr(netdev->dev_addr) &&
3894 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3895 eth_hw_addr_random(netdev);
3896 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3897 }
f62b8bb8
AV		 3898}
3899
cb67b832
HHZ		 3900static const struct switchdev_ops mlx5e_switchdev_ops = {
3901 .switchdev_port_attr_get = mlx5e_attr_get,
3902};
3903
6bfd390b 3904static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3905{
3906 struct mlx5e_priv *priv = netdev_priv(netdev);
3907 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3908 bool fcs_supported;
3909 bool fcs_enabled;
f62b8bb8
AV		 3910
3911 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3912
08fb1dac 3913 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3914 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3915#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3916 if (MLX5_CAP_GEN(mdev, qos))
3917 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3918#endif
3919 } else {
b0eed40e 3920 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3921 }
66e49ded 3922
f62b8bb8
AV		 3923 netdev->watchdog_timeo = 15 * HZ;
3924
3925 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3926
12be4b21 3927 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3928 netdev->vlan_features |= NETIF_F_IP_CSUM;
3929 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3930 netdev->vlan_features |= NETIF_F_GRO;
3931 netdev->vlan_features |= NETIF_F_TSO;
3932 netdev->vlan_features |= NETIF_F_TSO6;
3933 netdev->vlan_features |= NETIF_F_RXCSUM;
3934 netdev->vlan_features |= NETIF_F_RXHASH;
3935
3936 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3937 netdev->vlan_features |= NETIF_F_LRO;
3938
3939 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3940 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3941 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3942 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3943
b3f63c3d 3944 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3945 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3946 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3947 NETIF_F_GSO_PARTIAL;
b3f63c3d 3948 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3949 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3950 netdev->hw_enc_features |= NETIF_F_TSO;
3951 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3952 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3953 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3954 NETIF_F_GSO_PARTIAL;
3955 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3956 }
3957
94cb1ebb
EBE		 3958 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3959
3960 if (fcs_supported)
3961 netdev->hw_features |= NETIF_F_RXALL;
3962
102722fc
GE		 3963 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3964 netdev->hw_features |= NETIF_F_RXFCS;
3965
f62b8bb8 3966 netdev->features = netdev->hw_features;
6a9764ef 3967 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 3968 netdev->features &= ~NETIF_F_LRO;
3969
94cb1ebb
EBE		 3970 if (fcs_enabled)
3971 netdev->features &= ~NETIF_F_RXALL;
3972
102722fc
GE		 3973 if (!priv->channels.params.scatter_fcs_en)
3974 netdev->features &= ~NETIF_F_RXFCS;
3975
e8f887ac
AV		 3976#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3977 if (FT_CAP(flow_modify_en) &&
3978 FT_CAP(modify_root) &&
3979 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3980 FT_CAP(flow_table_modify)) {
3981 netdev->hw_features |= NETIF_F_HW_TC;
3982#ifdef CONFIG_RFS_ACCEL
3983 netdev->hw_features |= NETIF_F_NTUPLE;
3984#endif
3985 }
e8f887ac 3986
f62b8bb8
AV		 3987 netdev->features |= NETIF_F_HIGHDMA;
3988
3989 netdev->priv_flags |= IFF_UNICAST_FLT;
3990
3991 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3992
3993#ifdef CONFIG_NET_SWITCHDEV
3994 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3995 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3996#endif
f62b8bb8
AV		 3997}
3998
593cf338
RS		 3999static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4000{
4001 struct mlx5_core_dev *mdev = priv->mdev;
4002 int err;
4003
4004 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4005 if (err) {
4006 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4007 priv->q_counter = 0;
4008 }
4009}
4010
4011static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4012{
4013 if (!priv->q_counter)
4014 return;
4015
4016 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4017}
4018
6bfd390b
HHZ		 4019static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4020 struct net_device *netdev,
127ea380
HHZ		 4021 const struct mlx5e_profile *profile,
4022 void *ppriv)
6bfd390b
HHZ		 4023{
4024 struct mlx5e_priv *priv = netdev_priv(netdev);
4025
127ea380 4026 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 4027 mlx5e_build_nic_netdev(netdev);
4028 mlx5e_vxlan_init(priv);
4029}
4030
4031static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4032{
4033 mlx5e_vxlan_cleanup(priv);
127ea380 4034
6a9764ef
SM		 4035 if (priv->channels.params.xdp_prog)
4036 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4037}
4038
4039static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4040{
4041 struct mlx5_core_dev *mdev = priv->mdev;
4042 int err;
4043 int i;
4044
4045 err = mlx5e_create_indirect_rqts(priv);
4046 if (err) {
4047 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
4048 return err;
4049 }
4050
4051 err = mlx5e_create_direct_rqts(priv);
4052 if (err) {
4053 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
4054 goto err_destroy_indirect_rqts;
4055 }
4056
4057 err = mlx5e_create_indirect_tirs(priv);
4058 if (err) {
4059 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
4060 goto err_destroy_direct_rqts;
4061 }
4062
4063 err = mlx5e_create_direct_tirs(priv);
4064 if (err) {
4065 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
4066 goto err_destroy_indirect_tirs;
4067 }
4068
4069 err = mlx5e_create_flow_steering(priv);
4070 if (err) {
4071 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4072 goto err_destroy_direct_tirs;
4073 }
4074
4075 err = mlx5e_tc_init(priv);
4076 if (err)
4077 goto err_destroy_flow_steering;
4078
4079 return 0;
4080
4081err_destroy_flow_steering:
4082 mlx5e_destroy_flow_steering(priv);
4083err_destroy_direct_tirs:
4084 mlx5e_destroy_direct_tirs(priv);
4085err_destroy_indirect_tirs:
4086 mlx5e_destroy_indirect_tirs(priv);
4087err_destroy_direct_rqts:
4088 for (i = 0; i < priv->profile->max_nch(mdev); i++)
4089 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
4090err_destroy_indirect_rqts:
4091 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4092 return err;
4093}
4094
4095static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4096{
4097 int i;
4098
4099 mlx5e_tc_cleanup(priv);
4100 mlx5e_destroy_flow_steering(priv);
4101 mlx5e_destroy_direct_tirs(priv);
4102 mlx5e_destroy_indirect_tirs(priv);
4103 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
4104 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
4105 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4106}
4107
4108static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4109{
4110 int err;
4111
4112 err = mlx5e_create_tises(priv);
4113 if (err) {
4114 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4115 return err;
4116 }
4117
4118#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4119 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4120#endif
4121 return 0;
4122}
4123
4124static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4125{
4126 struct net_device *netdev = priv->netdev;
4127 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 4128 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4129 struct mlx5_eswitch_rep rep;
6bfd390b 4130
7907f23a
AH		 4131 mlx5_lag_add(mdev, netdev);
4132
6bfd390b 4133 mlx5e_enable_async_events(priv);
127ea380
HHZ		 4134
4135 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 4136 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 4137 rep.load = mlx5e_nic_rep_load;
4138 rep.unload = mlx5e_nic_rep_unload;
9deb2241 4139 rep.vport = FDB_UPLINK_VPORT;
726293f1 4140 rep.netdev = netdev;
9deb2241 4141 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 4142 }
610e89e0
SM		 4143
4144 if (netdev->reg_state != NETREG_REGISTERED)
4145 return;
4146
4147 /* Device already registered: sync netdev system state */
4148 if (mlx5e_vxlan_allowed(mdev)) {
4149 rtnl_lock();
4150 udp_tunnel_get_rx_info(netdev);
4151 rtnl_unlock();
4152 }
4153
4154 queue_work(priv->wq, &priv->set_rx_mode_work);
6bfd390b
HHZ		 4155}
4156
4157static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4158{
3deef8ce
SM		 4159 struct mlx5_core_dev *mdev = priv->mdev;
4160 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4161
6bfd390b 4162 queue_work(priv->wq, &priv->set_rx_mode_work);
3deef8ce
SM		 4163 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4164 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 4165 mlx5e_disable_async_events(priv);
3deef8ce 4166 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4167}
4168
4169static const struct mlx5e_profile mlx5e_nic_profile = {
4170 .init = mlx5e_nic_init,
4171 .cleanup = mlx5e_nic_cleanup,
4172 .init_rx = mlx5e_init_nic_rx,
4173 .cleanup_rx = mlx5e_cleanup_nic_rx,
4174 .init_tx = mlx5e_init_nic_tx,
4175 .cleanup_tx = mlx5e_cleanup_nic_tx,
4176 .enable = mlx5e_nic_enable,
4177 .disable = mlx5e_nic_disable,
4178 .update_stats = mlx5e_update_stats,
4179 .max_nch = mlx5e_get_max_num_channels,
4180 .max_tc = MLX5E_MAX_NUM_TC,
4181};
4182
26e59d80
MHY		 4183struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4184 const struct mlx5e_profile *profile,
4185 void *ppriv)
f62b8bb8 4186{
26e59d80 4187 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4188 struct net_device *netdev;
4189 struct mlx5e_priv *priv;
f62b8bb8 4190
08fb1dac 4191 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4192 nch * profile->max_tc,
08fb1dac 4193 nch);
f62b8bb8
AV		 4194 if (!netdev) {
4195 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4196 return NULL;
4197 }
4198
be4891af
SM		 4199#ifdef CONFIG_RFS_ACCEL
4200 netdev->rx_cpu_rmap = mdev->rmap;
4201#endif
4202
127ea380 4203 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4204
4205 netif_carrier_off(netdev);
4206
4207 priv = netdev_priv(netdev);
4208
7bb29755
MF		 4209 priv->wq = create_singlethread_workqueue("mlx5e");
4210 if (!priv->wq)
26e59d80
MHY		 4211 goto err_cleanup_nic;
4212
4213 return netdev;
4214
4215err_cleanup_nic:
4216 profile->cleanup(priv);
4217 free_netdev(netdev);
4218
4219 return NULL;
4220}
4221
4222int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4223{
4224 const struct mlx5e_profile *profile;
4225 struct mlx5e_priv *priv;
b80f71f5 4226 u16 max_mtu;
26e59d80
MHY		 4227 int err;
4228
4229 priv = netdev_priv(netdev);
4230 profile = priv->profile;
4231 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4232
6bfd390b
HHZ		 4233 err = profile->init_tx(priv);
4234 if (err)
ec8b9981 4235 goto out;
5c50368f 4236
a43b25da 4237 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4238 if (err) {
4239 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4240 goto err_cleanup_tx;
5c50368f
AS		 4241 }
4242
6bfd390b
HHZ		 4243 err = profile->init_rx(priv);
4244 if (err)
5c50368f 4245 goto err_close_drop_rq;
5c50368f 4246
593cf338
RS		 4247 mlx5e_create_q_counter(priv);
4248
33cfaaa8 4249 mlx5e_init_l2_addr(priv);
5c50368f 4250
b80f71f5
JW		 4251 /* MTU range: 68 - hw-specific max */
4252 netdev->min_mtu = ETH_MIN_MTU;
4253 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4254 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4255
2e20a151 4256 mlx5e_set_dev_port_mtu(priv);
13f9bba7 4257
6bfd390b
HHZ		 4258 if (profile->enable)
4259 profile->enable(priv);
f62b8bb8 4260
26e59d80
MHY		 4261 rtnl_lock();
4262 if (netif_running(netdev))
4263 mlx5e_open(netdev);
4264 netif_device_attach(netdev);
4265 rtnl_unlock();
f62b8bb8 4266
26e59d80 4267 return 0;
5c50368f
AS		 4268
4269err_close_drop_rq:
a43b25da 4270 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4271
6bfd390b
HHZ		 4272err_cleanup_tx:
4273 profile->cleanup_tx(priv);
5c50368f 4274
26e59d80
MHY		 4275out:
4276 return err;
f62b8bb8
AV		 4277}
4278
127ea380
HHZ		 4279static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
4280{
4281 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4282 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4283 int vport;
dbe413e3 4284 u8 mac[ETH_ALEN];
127ea380
HHZ		 4285
4286 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4287 return;
4288
dbe413e3
HHZ		 4289 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
4290
127ea380
HHZ		 4291 for (vport = 1; vport < total_vfs; vport++) {
4292 struct mlx5_eswitch_rep rep;
4293
cb67b832
HHZ		 4294 rep.load = mlx5e_vport_rep_load;
4295 rep.unload = mlx5e_vport_rep_unload;
127ea380 4296 rep.vport = vport;
dbe413e3 4297 ether_addr_copy(rep.hw_id, mac);
9deb2241 4298 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 4299 }
4300}
4301
6f08a22c
SM		 4302static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
4303{
4304 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4305 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4306 int vport;
4307
4308 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4309 return;
4310
4311 for (vport = 1; vport < total_vfs; vport++)
4312 mlx5_eswitch_unregister_vport_rep(esw, vport);
4313}
4314
26e59d80
MHY		 4315void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4316{
4317 struct mlx5e_priv *priv = netdev_priv(netdev);
4318 const struct mlx5e_profile *profile = priv->profile;
4319
4320 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80
MHY		 4321
4322 rtnl_lock();
4323 if (netif_running(netdev))
4324 mlx5e_close(netdev);
4325 netif_device_detach(netdev);
4326 rtnl_unlock();
4327
37f304d1
SM		 4328 if (profile->disable)
4329 profile->disable(priv);
4330 flush_workqueue(priv->wq);
4331
26e59d80
MHY		 4332 mlx5e_destroy_q_counter(priv);
4333 profile->cleanup_rx(priv);
a43b25da 4334 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4335 profile->cleanup_tx(priv);
26e59d80
MHY		 4336 cancel_delayed_work_sync(&priv->update_stats_work);
4337}
4338
4339/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4340 * hardware contexts and to connect it to the current netdev.
4341 */
4342static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4343{
4344 struct mlx5e_priv *priv = vpriv;
4345 struct net_device *netdev = priv->netdev;
4346 int err;
4347
4348 if (netif_device_present(netdev))
4349 return 0;
4350
4351 err = mlx5e_create_mdev_resources(mdev);
4352 if (err)
4353 return err;
4354
4355 err = mlx5e_attach_netdev(mdev, netdev);
4356 if (err) {
4357 mlx5e_destroy_mdev_resources(mdev);
4358 return err;
4359 }
4360
6f08a22c 4361 mlx5e_register_vport_rep(mdev);
26e59d80
MHY		 4362 return 0;
4363}
4364
4365static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4366{
4367 struct mlx5e_priv *priv = vpriv;
4368 struct net_device *netdev = priv->netdev;
4369
4370 if (!netif_device_present(netdev))
4371 return;
4372
6f08a22c 4373 mlx5e_unregister_vport_rep(mdev);
26e59d80
MHY		 4374 mlx5e_detach_netdev(mdev, netdev);
4375 mlx5e_destroy_mdev_resources(mdev);
4376}
4377
b50d292b
HHZ		 4378static void *mlx5e_add(struct mlx5_core_dev *mdev)
4379{
127ea380 4380 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4381 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4382 void *ppriv = NULL;
26e59d80
MHY		 4383 void *priv;
4384 int vport;
4385 int err;
4386 struct net_device *netdev;
b50d292b 4387
26e59d80
MHY		 4388 err = mlx5e_check_required_hca_cap(mdev);
4389 if (err)
b50d292b
HHZ		 4390 return NULL;
4391
127ea380
HHZ		 4392 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4393 ppriv = &esw->offloads.vport_reps[0];
4394
26e59d80
MHY		 4395 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4396 if (!netdev) {
4397 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4398 goto err_unregister_reps;
4399 }
4400
4401 priv = netdev_priv(netdev);
4402
4403 err = mlx5e_attach(mdev, priv);
4404 if (err) {
4405 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4406 goto err_destroy_netdev;
4407 }
4408
4409 err = register_netdev(netdev);
4410 if (err) {
4411 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4412 goto err_detach;
b50d292b 4413 }
26e59d80
MHY		 4414
4415 return priv;
4416
4417err_detach:
4418 mlx5e_detach(mdev, priv);
4419
4420err_destroy_netdev:
4421 mlx5e_destroy_netdev(mdev, priv);
4422
4423err_unregister_reps:
4424 for (vport = 1; vport < total_vfs; vport++)
4425 mlx5_eswitch_unregister_vport_rep(esw, vport);
4426
4427 return NULL;
b50d292b
HHZ		 4428}
4429
cb67b832 4430void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4431{
6bfd390b 4432 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4433 struct net_device *netdev = priv->netdev;
4434
7bb29755 4435 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4436 if (profile->cleanup)
4437 profile->cleanup(priv);
26e59d80 4438 free_netdev(netdev);
f62b8bb8
AV		 4439}
4440
b50d292b
HHZ		 4441static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4442{
4443 struct mlx5e_priv *priv = vpriv;
127ea380 4444
5e1e93c7 4445 unregister_netdev(priv->netdev);
26e59d80
MHY		 4446 mlx5e_detach(mdev, vpriv);
4447 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4448}
4449
f62b8bb8
AV		 4450static void *mlx5e_get_netdev(void *vpriv)
4451{
4452 struct mlx5e_priv *priv = vpriv;
4453
4454 return priv->netdev;
4455}
4456
4457static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4458 .add = mlx5e_add,
4459 .remove = mlx5e_remove,
26e59d80
MHY		 4460 .attach = mlx5e_attach,
4461 .detach = mlx5e_detach,
f62b8bb8
AV		 4462 .event = mlx5e_async_event,
4463 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4464 .get_dev = mlx5e_get_netdev,
4465};
4466
4467void mlx5e_init(void)
4468{
665bc539 4469 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4470 mlx5_register_interface(&mlx5e_interface);
4471}
4472
4473void mlx5e_cleanup(void)
4474{
4475 mlx5_unregister_interface(&mlx5e_interface);
4476}
Ubuntu Jammy Linux kernel mirror