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net: flow_offload: add flow_block_cb_is_busy() and use it
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rep.c
CommitLineData
cb67b832
HHZ
1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <generated/utsrelease.h>
34#include <linux/mlx5/fs.h>
35#include <net/switchdev.h>
d957b4e3 36#include <net/pkt_cls.h>
717503b9 37#include <net/act_api.h>
232c0013
HHZ
38#include <net/netevent.h>
39#include <net/arp.h>
f60f315d 40#include <net/devlink.h>
cb67b832
HHZ
41
42#include "eswitch.h"
43#include "en.h"
1d447a39 44#include "en_rep.h"
adb4c123 45#include "en_tc.h"
101f4de9 46#include "en/tc_tun.h"
f6dfb4c3 47#include "fs_core.h"
97417f61 48#include "lib/port_tun.h"
cb67b832 49
4c8fb298 50#define MLX5E_REP_PARAMS_DEF_LOG_SQ_SIZE \
e7164313 51 max(0x7, MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)
8956f001 52#define MLX5E_REP_PARAMS_DEF_NUM_CHANNELS 1
4246f698 53
cb67b832
HHZ
54static const char mlx5e_rep_driver_name[] = "mlx5e_rep";
55
f5bc2c5d
OS
56struct mlx5e_rep_indr_block_priv {
57 struct net_device *netdev;
58 struct mlx5e_rep_priv *rpriv;
59
60 struct list_head list;
61};
62
25f2d0e7
EB
63static void mlx5e_rep_indr_unregister_block(struct mlx5e_rep_priv *rpriv,
64 struct net_device *netdev);
f5bc2c5d 65
cb67b832
HHZ
66static void mlx5e_rep_get_drvinfo(struct net_device *dev,
67 struct ethtool_drvinfo *drvinfo)
68{
cf83c8fd
DL
69 struct mlx5e_priv *priv = netdev_priv(dev);
70 struct mlx5_core_dev *mdev = priv->mdev;
71
cb67b832
HHZ
72 strlcpy(drvinfo->driver, mlx5e_rep_driver_name,
73 sizeof(drvinfo->driver));
74 strlcpy(drvinfo->version, UTS_RELEASE, sizeof(drvinfo->version));
cf83c8fd
DL
75 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
76 "%d.%d.%04d (%.16s)",
77 fw_rev_maj(mdev), fw_rev_min(mdev),
78 fw_rev_sub(mdev), mdev->board_id);
79}
80
81static void mlx5e_uplink_rep_get_drvinfo(struct net_device *dev,
82 struct ethtool_drvinfo *drvinfo)
83{
84 struct mlx5e_priv *priv = netdev_priv(dev);
85
86 mlx5e_rep_get_drvinfo(dev, drvinfo);
87 strlcpy(drvinfo->bus_info, pci_name(priv->mdev->pdev),
88 sizeof(drvinfo->bus_info));
cb67b832
HHZ
89}
90
91static const struct counter_desc sw_rep_stats_desc[] = {
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
96};
97
a228060a
OG
98struct vport_stats {
99 u64 vport_rx_packets;
100 u64 vport_tx_packets;
101 u64 vport_rx_bytes;
102 u64 vport_tx_bytes;
103};
104
105static const struct counter_desc vport_rep_stats_desc[] = {
106 { MLX5E_DECLARE_STAT(struct vport_stats, vport_rx_packets) },
107 { MLX5E_DECLARE_STAT(struct vport_stats, vport_rx_bytes) },
108 { MLX5E_DECLARE_STAT(struct vport_stats, vport_tx_packets) },
109 { MLX5E_DECLARE_STAT(struct vport_stats, vport_tx_bytes) },
110};
111
112#define NUM_VPORT_REP_SW_COUNTERS ARRAY_SIZE(sw_rep_stats_desc)
113#define NUM_VPORT_REP_HW_COUNTERS ARRAY_SIZE(vport_rep_stats_desc)
cb67b832
HHZ
114
115static void mlx5e_rep_get_strings(struct net_device *dev,
116 u32 stringset, uint8_t *data)
117{
a228060a 118 int i, j;
cb67b832
HHZ
119
120 switch (stringset) {
121 case ETH_SS_STATS:
a228060a 122 for (i = 0; i < NUM_VPORT_REP_SW_COUNTERS; i++)
cb67b832
HHZ
123 strcpy(data + (i * ETH_GSTRING_LEN),
124 sw_rep_stats_desc[i].format);
a228060a
OG
125 for (j = 0; j < NUM_VPORT_REP_HW_COUNTERS; j++, i++)
126 strcpy(data + (i * ETH_GSTRING_LEN),
127 vport_rep_stats_desc[j].format);
cb67b832
HHZ
128 break;
129 }
130}
131
9b81d5a9 132static void mlx5e_rep_update_hw_counters(struct mlx5e_priv *priv)
370bad0f
OG
133{
134 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1d447a39
SM
135 struct mlx5e_rep_priv *rpriv = priv->ppriv;
136 struct mlx5_eswitch_rep *rep = rpriv->rep;
370bad0f
OG
137 struct rtnl_link_stats64 *vport_stats;
138 struct ifla_vf_stats vf_stats;
139 int err;
140
141 err = mlx5_eswitch_get_vport_stats(esw, rep->vport, &vf_stats);
142 if (err) {
143 pr_warn("vport %d error %d reading stats\n", rep->vport, err);
144 return;
145 }
146
147 vport_stats = &priv->stats.vf_vport;
148 /* flip tx/rx as we are reporting the counters for the switch vport */
149 vport_stats->rx_packets = vf_stats.tx_packets;
150 vport_stats->rx_bytes = vf_stats.tx_bytes;
151 vport_stats->tx_packets = vf_stats.rx_packets;
152 vport_stats->tx_bytes = vf_stats.rx_bytes;
153}
154
d9ee0491
OG
155static void mlx5e_uplink_rep_update_hw_counters(struct mlx5e_priv *priv)
156{
157 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
158 struct rtnl_link_stats64 *vport_stats;
159
160 mlx5e_grp_802_3_update_stats(priv);
161
162 vport_stats = &priv->stats.vf_vport;
163
164 vport_stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
165 vport_stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
166 vport_stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
167 vport_stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
168}
169
370bad0f 170static void mlx5e_rep_update_sw_counters(struct mlx5e_priv *priv)
cb67b832
HHZ
171{
172 struct mlx5e_sw_stats *s = &priv->stats.sw;
b832d4fd 173 struct rtnl_link_stats64 stats64 = {};
cb67b832
HHZ
174
175 memset(s, 0, sizeof(*s));
b832d4fd 176 mlx5e_fold_sw_stats64(priv, &stats64);
cb67b832 177
b832d4fd
SM
178 s->rx_packets = stats64.rx_packets;
179 s->rx_bytes = stats64.rx_bytes;
180 s->tx_packets = stats64.tx_packets;
181 s->tx_bytes = stats64.tx_bytes;
182 s->tx_queue_dropped = stats64.tx_dropped;
370bad0f
OG
183}
184
cb67b832
HHZ
185static void mlx5e_rep_get_ethtool_stats(struct net_device *dev,
186 struct ethtool_stats *stats, u64 *data)
187{
188 struct mlx5e_priv *priv = netdev_priv(dev);
a228060a 189 int i, j;
cb67b832
HHZ
190
191 if (!data)
192 return;
193
194 mutex_lock(&priv->state_lock);
168af00a 195 mlx5e_rep_update_sw_counters(priv);
9b81d5a9 196 priv->profile->update_stats(priv);
cb67b832
HHZ
197 mutex_unlock(&priv->state_lock);
198
a228060a 199 for (i = 0; i < NUM_VPORT_REP_SW_COUNTERS; i++)
cb67b832
HHZ
200 data[i] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
201 sw_rep_stats_desc, i);
a228060a
OG
202
203 for (j = 0; j < NUM_VPORT_REP_HW_COUNTERS; j++, i++)
204 data[i] = MLX5E_READ_CTR64_CPU(&priv->stats.vf_vport,
205 vport_rep_stats_desc, j);
cb67b832
HHZ
206}
207
208static int mlx5e_rep_get_sset_count(struct net_device *dev, int sset)
209{
210 switch (sset) {
211 case ETH_SS_STATS:
a228060a 212 return NUM_VPORT_REP_SW_COUNTERS + NUM_VPORT_REP_HW_COUNTERS;
cb67b832
HHZ
213 default:
214 return -EOPNOTSUPP;
215 }
216}
217
f128f138
GT
218static void mlx5e_rep_get_ringparam(struct net_device *dev,
219 struct ethtool_ringparam *param)
220{
221 struct mlx5e_priv *priv = netdev_priv(dev);
222
223 mlx5e_ethtool_get_ringparam(priv, param);
224}
225
226static int mlx5e_rep_set_ringparam(struct net_device *dev,
227 struct ethtool_ringparam *param)
228{
229 struct mlx5e_priv *priv = netdev_priv(dev);
230
231 return mlx5e_ethtool_set_ringparam(priv, param);
232}
233
84a09733
GT
234static int mlx5e_replace_rep_vport_rx_rule(struct mlx5e_priv *priv,
235 struct mlx5_flow_destination *dest)
236{
237 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
238 struct mlx5e_rep_priv *rpriv = priv->ppriv;
239 struct mlx5_eswitch_rep *rep = rpriv->rep;
240 struct mlx5_flow_handle *flow_rule;
241
242 flow_rule = mlx5_eswitch_create_vport_rx_rule(esw,
243 rep->vport,
244 dest);
245 if (IS_ERR(flow_rule))
246 return PTR_ERR(flow_rule);
247
248 mlx5_del_flow_rules(rpriv->vport_rx_rule);
249 rpriv->vport_rx_rule = flow_rule;
250 return 0;
251}
252
253static void mlx5e_rep_get_channels(struct net_device *dev,
254 struct ethtool_channels *ch)
255{
256 struct mlx5e_priv *priv = netdev_priv(dev);
257
258 mlx5e_ethtool_get_channels(priv, ch);
259}
260
261static int mlx5e_rep_set_channels(struct net_device *dev,
262 struct ethtool_channels *ch)
263{
264 struct mlx5e_priv *priv = netdev_priv(dev);
265 u16 curr_channels_amount = priv->channels.params.num_channels;
266 u32 new_channels_amount = ch->combined_count;
267 struct mlx5_flow_destination new_dest;
268 int err = 0;
269
270 err = mlx5e_ethtool_set_channels(priv, ch);
271 if (err)
272 return err;
273
274 if (curr_channels_amount == 1 && new_channels_amount > 1) {
275 new_dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
276 new_dest.ft = priv->fs.ttc.ft.t;
277 } else if (new_channels_amount == 1 && curr_channels_amount > 1) {
278 new_dest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
279 new_dest.tir_num = priv->direct_tir[0].tirn;
280 } else {
281 return 0;
282 }
283
284 err = mlx5e_replace_rep_vport_rx_rule(priv, &new_dest);
285 if (err) {
286 netdev_warn(priv->netdev, "Failed to update vport rx rule, when going from (%d) channels to (%d) channels\n",
287 curr_channels_amount, new_channels_amount);
288 return err;
289 }
290
291 return 0;
292}
293
ff9b85de
OG
294static int mlx5e_rep_get_coalesce(struct net_device *netdev,
295 struct ethtool_coalesce *coal)
296{
297 struct mlx5e_priv *priv = netdev_priv(netdev);
298
299 return mlx5e_ethtool_get_coalesce(priv, coal);
300}
301
302static int mlx5e_rep_set_coalesce(struct net_device *netdev,
303 struct ethtool_coalesce *coal)
304{
305 struct mlx5e_priv *priv = netdev_priv(netdev);
306
307 return mlx5e_ethtool_set_coalesce(priv, coal);
308}
309
84a09733
GT
310static u32 mlx5e_rep_get_rxfh_key_size(struct net_device *netdev)
311{
312 struct mlx5e_priv *priv = netdev_priv(netdev);
313
314 return mlx5e_ethtool_get_rxfh_key_size(priv);
315}
316
317static u32 mlx5e_rep_get_rxfh_indir_size(struct net_device *netdev)
318{
319 struct mlx5e_priv *priv = netdev_priv(netdev);
320
321 return mlx5e_ethtool_get_rxfh_indir_size(priv);
322}
323
ff9b85de
OG
324static void mlx5e_uplink_rep_get_pauseparam(struct net_device *netdev,
325 struct ethtool_pauseparam *pauseparam)
326{
327 struct mlx5e_priv *priv = netdev_priv(netdev);
328
329 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
330}
331
332static int mlx5e_uplink_rep_set_pauseparam(struct net_device *netdev,
333 struct ethtool_pauseparam *pauseparam)
334{
335 struct mlx5e_priv *priv = netdev_priv(netdev);
336
337 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
338}
339
340static int mlx5e_uplink_rep_get_link_ksettings(struct net_device *netdev,
341 struct ethtool_link_ksettings *link_ksettings)
342{
343 struct mlx5e_priv *priv = netdev_priv(netdev);
344
345 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
346}
347
348static int mlx5e_uplink_rep_set_link_ksettings(struct net_device *netdev,
349 const struct ethtool_link_ksettings *link_ksettings)
350{
351 struct mlx5e_priv *priv = netdev_priv(netdev);
352
353 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
354}
355
9b81d5a9 356static const struct ethtool_ops mlx5e_rep_ethtool_ops = {
ff9b85de
OG
357 .get_drvinfo = mlx5e_rep_get_drvinfo,
358 .get_link = ethtool_op_get_link,
359 .get_strings = mlx5e_rep_get_strings,
360 .get_sset_count = mlx5e_rep_get_sset_count,
361 .get_ethtool_stats = mlx5e_rep_get_ethtool_stats,
362 .get_ringparam = mlx5e_rep_get_ringparam,
363 .set_ringparam = mlx5e_rep_set_ringparam,
364 .get_channels = mlx5e_rep_get_channels,
365 .set_channels = mlx5e_rep_set_channels,
366 .get_coalesce = mlx5e_rep_get_coalesce,
367 .set_coalesce = mlx5e_rep_set_coalesce,
368 .get_rxfh_key_size = mlx5e_rep_get_rxfh_key_size,
369 .get_rxfh_indir_size = mlx5e_rep_get_rxfh_indir_size,
370};
371
372static const struct ethtool_ops mlx5e_uplink_rep_ethtool_ops = {
cf83c8fd 373 .get_drvinfo = mlx5e_uplink_rep_get_drvinfo,
cb67b832
HHZ
374 .get_link = ethtool_op_get_link,
375 .get_strings = mlx5e_rep_get_strings,
376 .get_sset_count = mlx5e_rep_get_sset_count,
377 .get_ethtool_stats = mlx5e_rep_get_ethtool_stats,
f128f138
GT
378 .get_ringparam = mlx5e_rep_get_ringparam,
379 .set_ringparam = mlx5e_rep_set_ringparam,
84a09733
GT
380 .get_channels = mlx5e_rep_get_channels,
381 .set_channels = mlx5e_rep_set_channels,
ff9b85de
OG
382 .get_coalesce = mlx5e_rep_get_coalesce,
383 .set_coalesce = mlx5e_rep_set_coalesce,
384 .get_link_ksettings = mlx5e_uplink_rep_get_link_ksettings,
385 .set_link_ksettings = mlx5e_uplink_rep_set_link_ksettings,
84a09733
GT
386 .get_rxfh_key_size = mlx5e_rep_get_rxfh_key_size,
387 .get_rxfh_indir_size = mlx5e_rep_get_rxfh_indir_size,
ff9b85de
OG
388 .get_pauseparam = mlx5e_uplink_rep_get_pauseparam,
389 .set_pauseparam = mlx5e_uplink_rep_set_pauseparam,
cb67b832
HHZ
390};
391
6dcfa234
FF
392static int mlx5e_rep_get_port_parent_id(struct net_device *dev,
393 struct netdev_phys_item_id *ppid)
cb67b832 394{
7ff40a46
PB
395 struct mlx5_eswitch *esw;
396 struct mlx5e_priv *priv;
397 u64 parent_id;
398
399 priv = netdev_priv(dev);
400 esw = priv->mdev->priv.eswitch;
cb67b832 401
f6455de0 402 if (esw->mode == MLX5_ESWITCH_NONE)
cb67b832
HHZ
403 return -EOPNOTSUPP;
404
7ff40a46
PB
405 parent_id = mlx5_query_nic_system_image_guid(priv->mdev);
406 ppid->id_len = sizeof(parent_id);
407 memcpy(ppid->id, &parent_id, sizeof(parent_id));
cb67b832
HHZ
408
409 return 0;
410}
411
f7a68945
MB
412static void mlx5e_sqs2vport_stop(struct mlx5_eswitch *esw,
413 struct mlx5_eswitch_rep *rep)
414{
2c47bf80 415 struct mlx5e_rep_sq *rep_sq, *tmp;
5ed99fb4 416 struct mlx5e_rep_priv *rpriv;
f7a68945 417
f6455de0 418 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
f7a68945
MB
419 return;
420
5ed99fb4 421 rpriv = mlx5e_rep_to_rep_priv(rep);
2c47bf80
MB
422 list_for_each_entry_safe(rep_sq, tmp, &rpriv->vport_sqs_list, list) {
423 mlx5_eswitch_del_send_to_vport_rule(rep_sq->send_to_vport_rule);
424 list_del(&rep_sq->list);
425 kfree(rep_sq);
f7a68945
MB
426 }
427}
428
429static int mlx5e_sqs2vport_start(struct mlx5_eswitch *esw,
430 struct mlx5_eswitch_rep *rep,
5ecadff0 431 u32 *sqns_array, int sqns_num)
f7a68945
MB
432{
433 struct mlx5_flow_handle *flow_rule;
5ed99fb4 434 struct mlx5e_rep_priv *rpriv;
2c47bf80 435 struct mlx5e_rep_sq *rep_sq;
f7a68945
MB
436 int err;
437 int i;
438
f6455de0 439 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
f7a68945
MB
440 return 0;
441
5ed99fb4 442 rpriv = mlx5e_rep_to_rep_priv(rep);
f7a68945 443 for (i = 0; i < sqns_num; i++) {
2c47bf80
MB
444 rep_sq = kzalloc(sizeof(*rep_sq), GFP_KERNEL);
445 if (!rep_sq) {
f7a68945
MB
446 err = -ENOMEM;
447 goto out_err;
448 }
449
450 /* Add re-inject rule to the PF/representor sqs */
451 flow_rule = mlx5_eswitch_add_send_to_vport_rule(esw,
452 rep->vport,
453 sqns_array[i]);
454 if (IS_ERR(flow_rule)) {
455 err = PTR_ERR(flow_rule);
2c47bf80 456 kfree(rep_sq);
f7a68945
MB
457 goto out_err;
458 }
2c47bf80
MB
459 rep_sq->send_to_vport_rule = flow_rule;
460 list_add(&rep_sq->list, &rpriv->vport_sqs_list);
f7a68945
MB
461 }
462 return 0;
463
464out_err:
465 mlx5e_sqs2vport_stop(esw, rep);
466 return err;
467}
468
cb67b832 469int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv)
cb67b832
HHZ
470{
471 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1d447a39
SM
472 struct mlx5e_rep_priv *rpriv = priv->ppriv;
473 struct mlx5_eswitch_rep *rep = rpriv->rep;
cb67b832 474 struct mlx5e_channel *c;
9008ae07
SM
475 int n, tc, num_sqs = 0;
476 int err = -ENOMEM;
5ecadff0 477 u32 *sqs;
cb67b832 478
5ecadff0 479 sqs = kcalloc(priv->channels.num * priv->channels.params.num_tc, sizeof(*sqs), GFP_KERNEL);
cb67b832 480 if (!sqs)
9008ae07 481 goto out;
cb67b832 482
ff9c852f
SM
483 for (n = 0; n < priv->channels.num; n++) {
484 c = priv->channels.c[n];
cb67b832
HHZ
485 for (tc = 0; tc < c->num_tc; tc++)
486 sqs[num_sqs++] = c->sq[tc].sqn;
487 }
488
f7a68945 489 err = mlx5e_sqs2vport_start(esw, rep, sqs, num_sqs);
cb67b832 490 kfree(sqs);
9008ae07
SM
491
492out:
493 if (err)
494 netdev_warn(priv->netdev, "Failed to add SQs FWD rules %d\n", err);
cb67b832
HHZ
495 return err;
496}
497
cb67b832
HHZ
498void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv)
499{
500 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1d447a39
SM
501 struct mlx5e_rep_priv *rpriv = priv->ppriv;
502 struct mlx5_eswitch_rep *rep = rpriv->rep;
cb67b832 503
f7a68945 504 mlx5e_sqs2vport_stop(esw, rep);
cb67b832
HHZ
505}
506
f6dfb4c3
HHZ
507static void mlx5e_rep_neigh_update_init_interval(struct mlx5e_rep_priv *rpriv)
508{
509#if IS_ENABLED(CONFIG_IPV6)
423c9db2 510 unsigned long ipv6_interval = NEIGH_VAR(&nd_tbl.parms,
f6dfb4c3
HHZ
511 DELAY_PROBE_TIME);
512#else
513 unsigned long ipv6_interval = ~0UL;
514#endif
515 unsigned long ipv4_interval = NEIGH_VAR(&arp_tbl.parms,
516 DELAY_PROBE_TIME);
5ed99fb4 517 struct net_device *netdev = rpriv->netdev;
f6dfb4c3
HHZ
518 struct mlx5e_priv *priv = netdev_priv(netdev);
519
520 rpriv->neigh_update.min_interval = min_t(unsigned long, ipv6_interval, ipv4_interval);
521 mlx5_fc_update_sampling_interval(priv->mdev, rpriv->neigh_update.min_interval);
522}
523
524void mlx5e_rep_queue_neigh_stats_work(struct mlx5e_priv *priv)
525{
526 struct mlx5e_rep_priv *rpriv = priv->ppriv;
527 struct mlx5e_neigh_update_table *neigh_update = &rpriv->neigh_update;
528
529 mlx5_fc_queue_stats_work(priv->mdev,
530 &neigh_update->neigh_stats_work,
531 neigh_update->min_interval);
532}
533
534static void mlx5e_rep_neigh_stats_work(struct work_struct *work)
535{
536 struct mlx5e_rep_priv *rpriv = container_of(work, struct mlx5e_rep_priv,
537 neigh_update.neigh_stats_work.work);
5ed99fb4 538 struct net_device *netdev = rpriv->netdev;
f6dfb4c3
HHZ
539 struct mlx5e_priv *priv = netdev_priv(netdev);
540 struct mlx5e_neigh_hash_entry *nhe;
541
542 rtnl_lock();
543 if (!list_empty(&rpriv->neigh_update.neigh_list))
544 mlx5e_rep_queue_neigh_stats_work(priv);
545
546 list_for_each_entry(nhe, &rpriv->neigh_update.neigh_list, neigh_list)
547 mlx5e_tc_update_neigh_used_value(nhe);
548
549 rtnl_unlock();
550}
551
232c0013
HHZ
552static void mlx5e_rep_neigh_entry_hold(struct mlx5e_neigh_hash_entry *nhe)
553{
554 refcount_inc(&nhe->refcnt);
555}
556
557static void mlx5e_rep_neigh_entry_release(struct mlx5e_neigh_hash_entry *nhe)
558{
559 if (refcount_dec_and_test(&nhe->refcnt))
560 kfree(nhe);
561}
562
563static void mlx5e_rep_update_flows(struct mlx5e_priv *priv,
564 struct mlx5e_encap_entry *e,
565 bool neigh_connected,
566 unsigned char ha[ETH_ALEN])
567{
568 struct ethhdr *eth = (struct ethhdr *)e->encap_header;
569
570 ASSERT_RTNL();
571
61c806da
OG
572 if ((e->flags & MLX5_ENCAP_ENTRY_VALID) &&
573 (!neigh_connected || !ether_addr_equal(e->h_dest, ha)))
232c0013
HHZ
574 mlx5e_tc_encap_flows_del(priv, e);
575
576 if (neigh_connected && !(e->flags & MLX5_ENCAP_ENTRY_VALID)) {
577 ether_addr_copy(e->h_dest, ha);
578 ether_addr_copy(eth->h_dest, ha);
6707f74b
TZ
579 /* Update the encap source mac, in case that we delete
580 * the flows when encap source mac changed.
581 */
582 ether_addr_copy(eth->h_source, e->route_dev->dev_addr);
232c0013
HHZ
583
584 mlx5e_tc_encap_flows_add(priv, e);
585 }
586}
587
588static void mlx5e_rep_neigh_update(struct work_struct *work)
589{
590 struct mlx5e_neigh_hash_entry *nhe =
591 container_of(work, struct mlx5e_neigh_hash_entry, neigh_update_work);
592 struct neighbour *n = nhe->n;
593 struct mlx5e_encap_entry *e;
594 unsigned char ha[ETH_ALEN];
595 struct mlx5e_priv *priv;
596 bool neigh_connected;
597 bool encap_connected;
598 u8 nud_state, dead;
599
600 rtnl_lock();
601
602 /* If these parameters are changed after we release the lock,
603 * we'll receive another event letting us know about it.
604 * We use this lock to avoid inconsistency between the neigh validity
605 * and it's hw address.
606 */
607 read_lock_bh(&n->lock);
608 memcpy(ha, n->ha, ETH_ALEN);
609 nud_state = n->nud_state;
610 dead = n->dead;
611 read_unlock_bh(&n->lock);
612
613 neigh_connected = (nud_state & NUD_VALID) && !dead;
614
615 list_for_each_entry(e, &nhe->encap_list, encap_list) {
616 encap_connected = !!(e->flags & MLX5_ENCAP_ENTRY_VALID);
617 priv = netdev_priv(e->out_dev);
618
619 if (encap_connected != neigh_connected ||
620 !ether_addr_equal(e->h_dest, ha))
621 mlx5e_rep_update_flows(priv, e, neigh_connected, ha);
622 }
623 mlx5e_rep_neigh_entry_release(nhe);
624 rtnl_unlock();
625 neigh_release(n);
626}
627
f5bc2c5d
OS
628static struct mlx5e_rep_indr_block_priv *
629mlx5e_rep_indr_block_priv_lookup(struct mlx5e_rep_priv *rpriv,
630 struct net_device *netdev)
631{
632 struct mlx5e_rep_indr_block_priv *cb_priv;
633
634 /* All callback list access should be protected by RTNL. */
635 ASSERT_RTNL();
636
637 list_for_each_entry(cb_priv,
638 &rpriv->uplink_priv.tc_indr_block_priv_list,
639 list)
640 if (cb_priv->netdev == netdev)
641 return cb_priv;
642
643 return NULL;
644}
645
646static void mlx5e_rep_indr_clean_block_privs(struct mlx5e_rep_priv *rpriv)
647{
648 struct mlx5e_rep_indr_block_priv *cb_priv, *temp;
649 struct list_head *head = &rpriv->uplink_priv.tc_indr_block_priv_list;
650
651 list_for_each_entry_safe(cb_priv, temp, head, list) {
25f2d0e7 652 mlx5e_rep_indr_unregister_block(rpriv, cb_priv->netdev);
f5bc2c5d
OS
653 kfree(cb_priv);
654 }
655}
656
657static int
658mlx5e_rep_indr_offload(struct net_device *netdev,
659 struct tc_cls_flower_offload *flower,
660 struct mlx5e_rep_indr_block_priv *indr_priv)
661{
ef381359 662 struct mlx5e_priv *priv = netdev_priv(indr_priv->rpriv->netdev);
d9ee0491
OG
663 int flags = MLX5E_TC_EGRESS | MLX5E_TC_ESW_OFFLOAD;
664 int err = 0;
ef381359
OS
665
666 switch (flower->command) {
667 case TC_CLSFLOWER_REPLACE:
d9ee0491 668 err = mlx5e_configure_flower(netdev, priv, flower, flags);
ef381359
OS
669 break;
670 case TC_CLSFLOWER_DESTROY:
d9ee0491 671 err = mlx5e_delete_flower(netdev, priv, flower, flags);
ef381359
OS
672 break;
673 case TC_CLSFLOWER_STATS:
d9ee0491 674 err = mlx5e_stats_flower(netdev, priv, flower, flags);
ef381359
OS
675 break;
676 default:
677 err = -EOPNOTSUPP;
678 }
679
680 return err;
f5bc2c5d
OS
681}
682
683static int mlx5e_rep_indr_setup_block_cb(enum tc_setup_type type,
684 void *type_data, void *indr_priv)
685{
686 struct mlx5e_rep_indr_block_priv *priv = indr_priv;
687
688 switch (type) {
689 case TC_SETUP_CLSFLOWER:
690 return mlx5e_rep_indr_offload(priv->netdev, type_data, priv);
691 default:
692 return -EOPNOTSUPP;
693 }
694}
695
955bcb6e
PNA
696static void mlx5e_rep_indr_tc_block_unbind(void *cb_priv)
697{
698 struct mlx5e_rep_indr_block_priv *indr_priv = cb_priv;
699
700 list_del(&indr_priv->list);
701 kfree(indr_priv);
702}
703
704static LIST_HEAD(mlx5e_block_cb_list);
705
f5bc2c5d
OS
706static int
707mlx5e_rep_indr_setup_tc_block(struct net_device *netdev,
708 struct mlx5e_rep_priv *rpriv,
955bcb6e 709 struct flow_block_offload *f)
f5bc2c5d
OS
710{
711 struct mlx5e_rep_indr_block_priv *indr_priv;
955bcb6e 712 struct flow_block_cb *block_cb;
f5bc2c5d 713
32f8c409 714 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
f5bc2c5d
OS
715 return -EOPNOTSUPP;
716
955bcb6e
PNA
717 f->driver_block_list = &mlx5e_block_cb_list;
718
f5bc2c5d 719 switch (f->command) {
9c0e189e 720 case FLOW_BLOCK_BIND:
f5bc2c5d
OS
721 indr_priv = mlx5e_rep_indr_block_priv_lookup(rpriv, netdev);
722 if (indr_priv)
723 return -EEXIST;
724
0d4fd02e
PNA
725 if (flow_block_cb_is_busy(mlx5e_rep_indr_setup_block_cb,
726 indr_priv, &mlx5e_block_cb_list))
727 return -EBUSY;
728
f5bc2c5d
OS
729 indr_priv = kmalloc(sizeof(*indr_priv), GFP_KERNEL);
730 if (!indr_priv)
731 return -ENOMEM;
732
733 indr_priv->netdev = netdev;
734 indr_priv->rpriv = rpriv;
735 list_add(&indr_priv->list,
736 &rpriv->uplink_priv.tc_indr_block_priv_list);
737
955bcb6e
PNA
738 block_cb = flow_block_cb_alloc(f->net,
739 mlx5e_rep_indr_setup_block_cb,
740 indr_priv, indr_priv,
741 mlx5e_rep_indr_tc_block_unbind);
742 if (IS_ERR(block_cb)) {
f5bc2c5d
OS
743 list_del(&indr_priv->list);
744 kfree(indr_priv);
955bcb6e 745 return PTR_ERR(block_cb);
f5bc2c5d 746 }
955bcb6e
PNA
747 flow_block_cb_add(block_cb, f);
748 list_add_tail(&block_cb->driver_list, &mlx5e_block_cb_list);
f5bc2c5d 749
955bcb6e 750 return 0;
9c0e189e 751 case FLOW_BLOCK_UNBIND:
25f2d0e7
EB
752 indr_priv = mlx5e_rep_indr_block_priv_lookup(rpriv, netdev);
753 if (!indr_priv)
754 return -ENOENT;
755
955bcb6e
PNA
756 block_cb = flow_block_cb_lookup(f,
757 mlx5e_rep_indr_setup_block_cb,
758 indr_priv);
759 if (!block_cb)
760 return -ENOENT;
f5bc2c5d 761
955bcb6e
PNA
762 flow_block_cb_remove(block_cb, f);
763 list_del(&block_cb->driver_list);
f5bc2c5d
OS
764 return 0;
765 default:
766 return -EOPNOTSUPP;
767 }
768 return 0;
769}
770
771static
772int mlx5e_rep_indr_setup_tc_cb(struct net_device *netdev, void *cb_priv,
773 enum tc_setup_type type, void *type_data)
774{
775 switch (type) {
776 case TC_SETUP_BLOCK:
777 return mlx5e_rep_indr_setup_tc_block(netdev, cb_priv,
778 type_data);
779 default:
780 return -EOPNOTSUPP;
781 }
782}
783
784static int mlx5e_rep_indr_register_block(struct mlx5e_rep_priv *rpriv,
785 struct net_device *netdev)
786{
787 int err;
788
789 err = __tc_indr_block_cb_register(netdev, rpriv,
790 mlx5e_rep_indr_setup_tc_cb,
25f2d0e7 791 rpriv);
f5bc2c5d
OS
792 if (err) {
793 struct mlx5e_priv *priv = netdev_priv(rpriv->netdev);
794
795 mlx5_core_err(priv->mdev, "Failed to register remote block notifier for %s err=%d\n",
796 netdev_name(netdev), err);
797 }
798 return err;
799}
800
25f2d0e7
EB
801static void mlx5e_rep_indr_unregister_block(struct mlx5e_rep_priv *rpriv,
802 struct net_device *netdev)
f5bc2c5d
OS
803{
804 __tc_indr_block_cb_unregister(netdev, mlx5e_rep_indr_setup_tc_cb,
25f2d0e7 805 rpriv);
f5bc2c5d
OS
806}
807
808static int mlx5e_nic_rep_netdevice_event(struct notifier_block *nb,
809 unsigned long event, void *ptr)
810{
811 struct mlx5e_rep_priv *rpriv = container_of(nb, struct mlx5e_rep_priv,
812 uplink_priv.netdevice_nb);
813 struct mlx5e_priv *priv = netdev_priv(rpriv->netdev);
814 struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
815
35a605db 816 if (!mlx5e_tc_tun_device_to_offload(priv, netdev) &&
24bcd210 817 !(is_vlan_dev(netdev) && vlan_dev_real_dev(netdev) == rpriv->netdev))
f5bc2c5d
OS
818 return NOTIFY_OK;
819
820 switch (event) {
821 case NETDEV_REGISTER:
822 mlx5e_rep_indr_register_block(rpriv, netdev);
823 break;
824 case NETDEV_UNREGISTER:
25f2d0e7 825 mlx5e_rep_indr_unregister_block(rpriv, netdev);
f5bc2c5d
OS
826 break;
827 }
828 return NOTIFY_OK;
829}
830
232c0013
HHZ
831static struct mlx5e_neigh_hash_entry *
832mlx5e_rep_neigh_entry_lookup(struct mlx5e_priv *priv,
833 struct mlx5e_neigh *m_neigh);
834
835static int mlx5e_rep_netevent_event(struct notifier_block *nb,
836 unsigned long event, void *ptr)
837{
838 struct mlx5e_rep_priv *rpriv = container_of(nb, struct mlx5e_rep_priv,
839 neigh_update.netevent_nb);
840 struct mlx5e_neigh_update_table *neigh_update = &rpriv->neigh_update;
5ed99fb4 841 struct net_device *netdev = rpriv->netdev;
232c0013
HHZ
842 struct mlx5e_priv *priv = netdev_priv(netdev);
843 struct mlx5e_neigh_hash_entry *nhe = NULL;
844 struct mlx5e_neigh m_neigh = {};
a2fa1fe5 845 struct neigh_parms *p;
232c0013 846 struct neighbour *n;
a2fa1fe5 847 bool found = false;
232c0013
HHZ
848
849 switch (event) {
850 case NETEVENT_NEIGH_UPDATE:
851 n = ptr;
852#if IS_ENABLED(CONFIG_IPV6)
423c9db2 853 if (n->tbl != &nd_tbl && n->tbl != &arp_tbl)
232c0013
HHZ
854#else
855 if (n->tbl != &arp_tbl)
856#endif
857 return NOTIFY_DONE;
858
859 m_neigh.dev = n->dev;
f6dfb4c3 860 m_neigh.family = n->ops->family;
232c0013
HHZ
861 memcpy(&m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
862
863 /* We are in atomic context and can't take RTNL mutex, so use
864 * spin_lock_bh to lookup the neigh table. bh is used since
865 * netevent can be called from a softirq context.
866 */
867 spin_lock_bh(&neigh_update->encap_lock);
868 nhe = mlx5e_rep_neigh_entry_lookup(priv, &m_neigh);
869 if (!nhe) {
870 spin_unlock_bh(&neigh_update->encap_lock);
871 return NOTIFY_DONE;
872 }
873
874 /* This assignment is valid as long as the the neigh reference
875 * is taken
876 */
877 nhe->n = n;
878
879 /* Take a reference to ensure the neighbour and mlx5 encap
880 * entry won't be destructed until we drop the reference in
881 * delayed work.
882 */
883 neigh_hold(n);
884 mlx5e_rep_neigh_entry_hold(nhe);
885
886 if (!queue_work(priv->wq, &nhe->neigh_update_work)) {
887 mlx5e_rep_neigh_entry_release(nhe);
888 neigh_release(n);
889 }
890 spin_unlock_bh(&neigh_update->encap_lock);
891 break;
a2fa1fe5
HHZ
892
893 case NETEVENT_DELAY_PROBE_TIME_UPDATE:
894 p = ptr;
895
896 /* We check the device is present since we don't care about
897 * changes in the default table, we only care about changes
898 * done per device delay prob time parameter.
899 */
900#if IS_ENABLED(CONFIG_IPV6)
423c9db2 901 if (!p->dev || (p->tbl != &nd_tbl && p->tbl != &arp_tbl))
a2fa1fe5
HHZ
902#else
903 if (!p->dev || p->tbl != &arp_tbl)
904#endif
905 return NOTIFY_DONE;
906
907 /* We are in atomic context and can't take RTNL mutex,
908 * so use spin_lock_bh to walk the neigh list and look for
909 * the relevant device. bh is used since netevent can be
910 * called from a softirq context.
911 */
912 spin_lock_bh(&neigh_update->encap_lock);
913 list_for_each_entry(nhe, &neigh_update->neigh_list, neigh_list) {
914 if (p->dev == nhe->m_neigh.dev) {
915 found = true;
916 break;
917 }
918 }
919 spin_unlock_bh(&neigh_update->encap_lock);
920 if (!found)
921 return NOTIFY_DONE;
922
923 neigh_update->min_interval = min_t(unsigned long,
924 NEIGH_VAR(p, DELAY_PROBE_TIME),
925 neigh_update->min_interval);
926 mlx5_fc_update_sampling_interval(priv->mdev,
927 neigh_update->min_interval);
928 break;
232c0013
HHZ
929 }
930 return NOTIFY_DONE;
931}
932
37b498ff
HHZ
933static const struct rhashtable_params mlx5e_neigh_ht_params = {
934 .head_offset = offsetof(struct mlx5e_neigh_hash_entry, rhash_node),
935 .key_offset = offsetof(struct mlx5e_neigh_hash_entry, m_neigh),
936 .key_len = sizeof(struct mlx5e_neigh),
937 .automatic_shrinking = true,
938};
939
940static int mlx5e_rep_neigh_init(struct mlx5e_rep_priv *rpriv)
941{
942 struct mlx5e_neigh_update_table *neigh_update = &rpriv->neigh_update;
232c0013
HHZ
943 int err;
944
945 err = rhashtable_init(&neigh_update->neigh_ht, &mlx5e_neigh_ht_params);
946 if (err)
947 return err;
37b498ff
HHZ
948
949 INIT_LIST_HEAD(&neigh_update->neigh_list);
232c0013 950 spin_lock_init(&neigh_update->encap_lock);
f6dfb4c3
HHZ
951 INIT_DELAYED_WORK(&neigh_update->neigh_stats_work,
952 mlx5e_rep_neigh_stats_work);
953 mlx5e_rep_neigh_update_init_interval(rpriv);
232c0013
HHZ
954
955 rpriv->neigh_update.netevent_nb.notifier_call = mlx5e_rep_netevent_event;
956 err = register_netevent_notifier(&rpriv->neigh_update.netevent_nb);
957 if (err)
958 goto out_err;
959 return 0;
960
961out_err:
962 rhashtable_destroy(&neigh_update->neigh_ht);
963 return err;
37b498ff
HHZ
964}
965
966static void mlx5e_rep_neigh_cleanup(struct mlx5e_rep_priv *rpriv)
967{
968 struct mlx5e_neigh_update_table *neigh_update = &rpriv->neigh_update;
5ed99fb4 969 struct mlx5e_priv *priv = netdev_priv(rpriv->netdev);
232c0013
HHZ
970
971 unregister_netevent_notifier(&neigh_update->netevent_nb);
972
973 flush_workqueue(priv->wq); /* flush neigh update works */
37b498ff 974
f6dfb4c3
HHZ
975 cancel_delayed_work_sync(&rpriv->neigh_update.neigh_stats_work);
976
37b498ff
HHZ
977 rhashtable_destroy(&neigh_update->neigh_ht);
978}
979
980static int mlx5e_rep_neigh_entry_insert(struct mlx5e_priv *priv,
981 struct mlx5e_neigh_hash_entry *nhe)
982{
983 struct mlx5e_rep_priv *rpriv = priv->ppriv;
984 int err;
985
986 err = rhashtable_insert_fast(&rpriv->neigh_update.neigh_ht,
987 &nhe->rhash_node,
988 mlx5e_neigh_ht_params);
989 if (err)
990 return err;
991
992 list_add(&nhe->neigh_list, &rpriv->neigh_update.neigh_list);
993
994 return err;
995}
996
997static void mlx5e_rep_neigh_entry_remove(struct mlx5e_priv *priv,
998 struct mlx5e_neigh_hash_entry *nhe)
999{
1000 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1001
232c0013
HHZ
1002 spin_lock_bh(&rpriv->neigh_update.encap_lock);
1003
37b498ff
HHZ
1004 list_del(&nhe->neigh_list);
1005
1006 rhashtable_remove_fast(&rpriv->neigh_update.neigh_ht,
1007 &nhe->rhash_node,
1008 mlx5e_neigh_ht_params);
232c0013 1009 spin_unlock_bh(&rpriv->neigh_update.encap_lock);
37b498ff
HHZ
1010}
1011
232c0013
HHZ
1012/* This function must only be called under RTNL lock or under the
1013 * representor's encap_lock in case RTNL mutex can't be held.
1014 */
37b498ff
HHZ
1015static struct mlx5e_neigh_hash_entry *
1016mlx5e_rep_neigh_entry_lookup(struct mlx5e_priv *priv,
1017 struct mlx5e_neigh *m_neigh)
1018{
1019 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1020 struct mlx5e_neigh_update_table *neigh_update = &rpriv->neigh_update;
1021
1022 return rhashtable_lookup_fast(&neigh_update->neigh_ht, m_neigh,
1023 mlx5e_neigh_ht_params);
1024}
1025
232c0013
HHZ
1026static int mlx5e_rep_neigh_entry_create(struct mlx5e_priv *priv,
1027 struct mlx5e_encap_entry *e,
1028 struct mlx5e_neigh_hash_entry **nhe)
1029{
1030 int err;
1031
1032 *nhe = kzalloc(sizeof(**nhe), GFP_KERNEL);
1033 if (!*nhe)
1034 return -ENOMEM;
1035
1036 memcpy(&(*nhe)->m_neigh, &e->m_neigh, sizeof(e->m_neigh));
1037 INIT_WORK(&(*nhe)->neigh_update_work, mlx5e_rep_neigh_update);
1038 INIT_LIST_HEAD(&(*nhe)->encap_list);
1039 refcount_set(&(*nhe)->refcnt, 1);
1040
1041 err = mlx5e_rep_neigh_entry_insert(priv, *nhe);
1042 if (err)
1043 goto out_free;
1044 return 0;
1045
1046out_free:
1047 kfree(*nhe);
1048 return err;
1049}
1050
1051static void mlx5e_rep_neigh_entry_destroy(struct mlx5e_priv *priv,
1052 struct mlx5e_neigh_hash_entry *nhe)
1053{
1054 /* The neigh hash entry must be removed from the hash table regardless
1055 * of the reference count value, so it won't be found by the next
1056 * neigh notification call. The neigh hash entry reference count is
1057 * incremented only during creation and neigh notification calls and
1058 * protects from freeing the nhe struct.
1059 */
1060 mlx5e_rep_neigh_entry_remove(priv, nhe);
1061 mlx5e_rep_neigh_entry_release(nhe);
1062}
1063
1064int mlx5e_rep_encap_entry_attach(struct mlx5e_priv *priv,
1065 struct mlx5e_encap_entry *e)
1066{
97417f61
EB
1067 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1068 struct mlx5_rep_uplink_priv *uplink_priv = &rpriv->uplink_priv;
1069 struct mlx5_tun_entropy *tun_entropy = &uplink_priv->tun_entropy;
232c0013
HHZ
1070 struct mlx5e_neigh_hash_entry *nhe;
1071 int err;
1072
97417f61
EB
1073 err = mlx5_tun_entropy_refcount_inc(tun_entropy, e->reformat_type);
1074 if (err)
1075 return err;
232c0013
HHZ
1076 nhe = mlx5e_rep_neigh_entry_lookup(priv, &e->m_neigh);
1077 if (!nhe) {
1078 err = mlx5e_rep_neigh_entry_create(priv, e, &nhe);
97417f61
EB
1079 if (err) {
1080 mlx5_tun_entropy_refcount_dec(tun_entropy,
1081 e->reformat_type);
232c0013 1082 return err;
97417f61 1083 }
232c0013
HHZ
1084 }
1085 list_add(&e->encap_list, &nhe->encap_list);
1086 return 0;
1087}
1088
1089void mlx5e_rep_encap_entry_detach(struct mlx5e_priv *priv,
1090 struct mlx5e_encap_entry *e)
1091{
97417f61
EB
1092 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1093 struct mlx5_rep_uplink_priv *uplink_priv = &rpriv->uplink_priv;
1094 struct mlx5_tun_entropy *tun_entropy = &uplink_priv->tun_entropy;
232c0013
HHZ
1095 struct mlx5e_neigh_hash_entry *nhe;
1096
1097 list_del(&e->encap_list);
1098 nhe = mlx5e_rep_neigh_entry_lookup(priv, &e->m_neigh);
1099
1100 if (list_empty(&nhe->encap_list))
1101 mlx5e_rep_neigh_entry_destroy(priv, nhe);
97417f61 1102 mlx5_tun_entropy_refcount_dec(tun_entropy, e->reformat_type);
232c0013
HHZ
1103}
1104
9b81d5a9 1105static int mlx5e_rep_open(struct net_device *dev)
20a1ea67
OG
1106{
1107 struct mlx5e_priv *priv = netdev_priv(dev);
1d447a39
SM
1108 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1109 struct mlx5_eswitch_rep *rep = rpriv->rep;
20a1ea67
OG
1110 int err;
1111
63bfd399
EBE
1112 mutex_lock(&priv->state_lock);
1113 err = mlx5e_open_locked(dev);
20a1ea67 1114 if (err)
63bfd399 1115 goto unlock;
20a1ea67 1116
84c9c8f2 1117 if (!mlx5_modify_vport_admin_state(priv->mdev,
cc9c82a8 1118 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT,
cbc44e76
BW
1119 rep->vport, 1,
1120 MLX5_VPORT_ADMIN_STATE_UP))
20a1ea67
OG
1121 netif_carrier_on(dev);
1122
63bfd399
EBE
1123unlock:
1124 mutex_unlock(&priv->state_lock);
1125 return err;
20a1ea67
OG
1126}
1127
9b81d5a9 1128static int mlx5e_rep_close(struct net_device *dev)
20a1ea67
OG
1129{
1130 struct mlx5e_priv *priv = netdev_priv(dev);
1d447a39
SM
1131 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1132 struct mlx5_eswitch_rep *rep = rpriv->rep;
63bfd399 1133 int ret;
20a1ea67 1134
63bfd399 1135 mutex_lock(&priv->state_lock);
84c9c8f2 1136 mlx5_modify_vport_admin_state(priv->mdev,
cc9c82a8 1137 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT,
cbc44e76
BW
1138 rep->vport, 1,
1139 MLX5_VPORT_ADMIN_STATE_DOWN);
63bfd399
EBE
1140 ret = mlx5e_close_locked(dev);
1141 mutex_unlock(&priv->state_lock);
1142 return ret;
20a1ea67
OG
1143}
1144
de4784ca 1145static int
855afa09 1146mlx5e_rep_setup_tc_cls_flower(struct mlx5e_priv *priv,
60bd4af8 1147 struct tc_cls_flower_offload *cls_flower, int flags)
d957b4e3 1148{
8c818c27
JP
1149 switch (cls_flower->command) {
1150 case TC_CLSFLOWER_REPLACE:
71d82d2a
OS
1151 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
1152 flags);
8c818c27 1153 case TC_CLSFLOWER_DESTROY:
71d82d2a
OS
1154 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
1155 flags);
8c818c27 1156 case TC_CLSFLOWER_STATS:
71d82d2a
OS
1157 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
1158 flags);
60bd4af8
OG
1159 default:
1160 return -EOPNOTSUPP;
1161 }
1162}
1163
855afa09
JP
1164static int mlx5e_rep_setup_tc_cb(enum tc_setup_type type, void *type_data,
1165 void *cb_priv)
1166{
1167 struct mlx5e_priv *priv = cb_priv;
1168
1169 switch (type) {
1170 case TC_SETUP_CLSFLOWER:
d9ee0491
OG
1171 return mlx5e_rep_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
1172 MLX5E_TC_ESW_OFFLOAD);
855afa09
JP
1173 default:
1174 return -EOPNOTSUPP;
1175 }
1176}
1177
8c818c27 1178static int mlx5e_rep_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1179 void *type_data)
8c818c27 1180{
4e95bc26
PNA
1181 struct mlx5e_priv *priv = netdev_priv(dev);
1182
2572ac53 1183 switch (type) {
855afa09 1184 case TC_SETUP_BLOCK:
4e95bc26
PNA
1185 return flow_block_cb_setup_simple(type_data, NULL,
1186 mlx5e_rep_setup_tc_cb,
1187 priv, priv, true);
d957b4e3
OG
1188 default:
1189 return -EOPNOTSUPP;
1190 }
1191}
1192
370bad0f
OG
1193bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv)
1194{
1d447a39
SM
1195 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1196 struct mlx5_eswitch_rep *rep;
1197
733d3e54 1198 if (!MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39 1199 return false;
370bad0f 1200
d9ee0491
OG
1201 if (!rpriv) /* non vport rep mlx5e instances don't use this field */
1202 return false;
370bad0f 1203
d9ee0491 1204 rep = rpriv->rep;
b05af6aa 1205 return (rep->vport == MLX5_VPORT_UPLINK);
370bad0f
OG
1206}
1207
13e509a4 1208static bool mlx5e_rep_has_offload_stats(const struct net_device *dev, int attr_id)
370bad0f 1209{
370bad0f
OG
1210 switch (attr_id) {
1211 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
370bad0f
OG
1212 return true;
1213 }
1214
1215 return false;
1216}
1217
1218static int
1219mlx5e_get_sw_stats64(const struct net_device *dev,
1220 struct rtnl_link_stats64 *stats)
1221{
1222 struct mlx5e_priv *priv = netdev_priv(dev);
370bad0f 1223
b832d4fd 1224 mlx5e_fold_sw_stats64(priv, stats);
370bad0f
OG
1225 return 0;
1226}
1227
13e509a4
OG
1228static int mlx5e_rep_get_offload_stats(int attr_id, const struct net_device *dev,
1229 void *sp)
370bad0f
OG
1230{
1231 switch (attr_id) {
1232 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1233 return mlx5e_get_sw_stats64(dev, sp);
1234 }
1235
1236 return -EINVAL;
1237}
1238
bc1f4470 1239static void
9b81d5a9 1240mlx5e_rep_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
370bad0f
OG
1241{
1242 struct mlx5e_priv *priv = netdev_priv(dev);
1243
ed56c519 1244 /* update HW stats in background for next time */
cdeef2b1 1245 mlx5e_queue_update_stats(priv);
370bad0f 1246 memcpy(stats, &priv->stats.vf_vport, sizeof(*stats));
370bad0f
OG
1247}
1248
9b81d5a9 1249static int mlx5e_rep_change_mtu(struct net_device *netdev, int new_mtu)
d9ee0491
OG
1250{
1251 return mlx5e_change_mtu(netdev, new_mtu, NULL);
1252}
1253
b36cdb42 1254static int mlx5e_uplink_rep_change_mtu(struct net_device *netdev, int new_mtu)
d9ee0491 1255{
b36cdb42 1256 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
d9ee0491
OG
1257}
1258
b36cdb42 1259static int mlx5e_uplink_rep_set_mac(struct net_device *netdev, void *addr)
d9ee0491 1260{
b36cdb42
OG
1261 struct sockaddr *saddr = addr;
1262
1263 if (!is_valid_ether_addr(saddr->sa_data))
1264 return -EADDRNOTAVAIL;
1265
1266 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1267 return 0;
d9ee0491
OG
1268}
1269
6ce966fd
OG
1270static int mlx5e_uplink_rep_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
1271 __be16 vlan_proto)
1272{
1273 netdev_warn_once(dev, "legacy vf vlan setting isn't supported in switchdev mode\n");
1274
1275 if (vlan != 0)
1276 return -EOPNOTSUPP;
1277
1278 /* allow setting 0-vid for compatibility with libvirt */
1279 return 0;
1280}
1281
f60f315d
PP
1282static struct devlink_port *mlx5e_get_devlink_port(struct net_device *dev)
1283{
1284 struct mlx5e_priv *priv = netdev_priv(dev);
1285 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1286
1287 return &rpriv->dl_port;
1288}
1289
9b81d5a9
VP
1290static const struct net_device_ops mlx5e_netdev_ops_rep = {
1291 .ndo_open = mlx5e_rep_open,
1292 .ndo_stop = mlx5e_rep_close,
d9ee0491 1293 .ndo_start_xmit = mlx5e_xmit,
d9ee0491 1294 .ndo_setup_tc = mlx5e_rep_setup_tc,
f60f315d 1295 .ndo_get_devlink_port = mlx5e_get_devlink_port,
9b81d5a9 1296 .ndo_get_stats64 = mlx5e_rep_get_stats,
13e509a4
OG
1297 .ndo_has_offload_stats = mlx5e_rep_has_offload_stats,
1298 .ndo_get_offload_stats = mlx5e_rep_get_offload_stats,
9b81d5a9 1299 .ndo_change_mtu = mlx5e_rep_change_mtu,
d9ee0491 1300};
250a42b6 1301
d9ee0491 1302static const struct net_device_ops mlx5e_netdev_ops_uplink_rep = {
b36cdb42 1303 .ndo_open = mlx5e_open,
d9ee0491 1304 .ndo_stop = mlx5e_close,
cb67b832 1305 .ndo_start_xmit = mlx5e_xmit,
b36cdb42 1306 .ndo_set_mac_address = mlx5e_uplink_rep_set_mac,
8c818c27 1307 .ndo_setup_tc = mlx5e_rep_setup_tc,
f60f315d 1308 .ndo_get_devlink_port = mlx5e_get_devlink_port,
d9ee0491 1309 .ndo_get_stats64 = mlx5e_get_stats,
13e509a4
OG
1310 .ndo_has_offload_stats = mlx5e_rep_has_offload_stats,
1311 .ndo_get_offload_stats = mlx5e_rep_get_offload_stats,
d9ee0491 1312 .ndo_change_mtu = mlx5e_uplink_rep_change_mtu,
073caf50
OG
1313 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
1314 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
1315 .ndo_features_check = mlx5e_features_check,
1316 .ndo_set_vf_mac = mlx5e_set_vf_mac,
1317 .ndo_set_vf_rate = mlx5e_set_vf_rate,
1318 .ndo_get_vf_config = mlx5e_get_vf_config,
1319 .ndo_get_vf_stats = mlx5e_get_vf_stats,
6ce966fd 1320 .ndo_set_vf_vlan = mlx5e_uplink_rep_set_vf_vlan,
d3cbd425 1321 .ndo_set_features = mlx5e_set_features,
cb67b832
HHZ
1322};
1323
a0646c88
EB
1324bool mlx5e_eswitch_rep(struct net_device *netdev)
1325{
9b81d5a9 1326 if (netdev->netdev_ops == &mlx5e_netdev_ops_rep ||
a0646c88
EB
1327 netdev->netdev_ops == &mlx5e_netdev_ops_uplink_rep)
1328 return true;
1329
1330 return false;
1331}
1332
025380b2 1333static void mlx5e_build_rep_params(struct net_device *netdev)
cb67b832 1334{
025380b2 1335 struct mlx5e_priv *priv = netdev_priv(netdev);
d9ee0491
OG
1336 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1337 struct mlx5_eswitch_rep *rep = rpriv->rep;
025380b2
OG
1338 struct mlx5_core_dev *mdev = priv->mdev;
1339 struct mlx5e_params *params;
1340
cb67b832
HHZ
1341 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
1342 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1343 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1344
025380b2 1345 params = &priv->channels.params;
472a1e44 1346 params->hard_mtu = MLX5E_ETH_HARD_MTU;
025380b2 1347 params->sw_mtu = netdev->mtu;
d9ee0491
OG
1348
1349 /* SQ */
b05af6aa 1350 if (rep->vport == MLX5_VPORT_UPLINK)
d9ee0491
OG
1351 params->log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1352 else
5d1f7354 1353 params->log_sq_size = MLX5E_REP_PARAMS_DEF_LOG_SQ_SIZE;
cb67b832 1354
749359f4
GT
1355 /* RQ */
1356 mlx5e_build_rq_params(mdev, params);
1357
1358 /* CQ moderation params */
9a317425 1359 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
6a9764ef 1360 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
cb67b832 1361
6a9764ef 1362 params->num_tc = 1;
69dad68d 1363 params->tunneled_offload_en = false;
5f195c2c
CM
1364
1365 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
84a09733
GT
1366
1367 /* RSS */
025380b2 1368 mlx5e_build_rss_params(&priv->rss_params, params->num_channels);
cb67b832
HHZ
1369}
1370
1371static void mlx5e_build_rep_netdev(struct net_device *netdev)
1372{
250a42b6 1373 struct mlx5e_priv *priv = netdev_priv(netdev);
d9ee0491
OG
1374 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1375 struct mlx5_eswitch_rep *rep = rpriv->rep;
250a42b6 1376 struct mlx5_core_dev *mdev = priv->mdev;
250a42b6 1377
b05af6aa 1378 if (rep->vport == MLX5_VPORT_UPLINK) {
c42260f1 1379 SET_NETDEV_DEV(netdev, mdev->device);
d9ee0491
OG
1380 netdev->netdev_ops = &mlx5e_netdev_ops_uplink_rep;
1381 /* we want a persistent mac for the uplink rep */
e1d974d0 1382 mlx5_query_mac_address(mdev, netdev->dev_addr);
ff9b85de 1383 netdev->ethtool_ops = &mlx5e_uplink_rep_ethtool_ops;
b36cdb42
OG
1384#ifdef CONFIG_MLX5_CORE_EN_DCB
1385 if (MLX5_CAP_GEN(mdev, qos))
1386 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
1387#endif
d9ee0491 1388 } else {
9b81d5a9 1389 netdev->netdev_ops = &mlx5e_netdev_ops_rep;
d9ee0491 1390 eth_hw_addr_random(netdev);
9b81d5a9 1391 netdev->ethtool_ops = &mlx5e_rep_ethtool_ops;
d9ee0491 1392 }
cb67b832
HHZ
1393
1394 netdev->watchdog_timeo = 15 * HZ;
1395
d3cbd425 1396 netdev->features |= NETIF_F_NETNS_LOCAL;
cb67b832 1397
d3cbd425 1398 netdev->hw_features |= NETIF_F_HW_TC;
dabeb3b0
GT
1399 netdev->hw_features |= NETIF_F_SG;
1400 netdev->hw_features |= NETIF_F_IP_CSUM;
1401 netdev->hw_features |= NETIF_F_IPV6_CSUM;
1402 netdev->hw_features |= NETIF_F_GRO;
1403 netdev->hw_features |= NETIF_F_TSO;
1404 netdev->hw_features |= NETIF_F_TSO6;
1405 netdev->hw_features |= NETIF_F_RXCSUM;
1406
d3cbd425
CM
1407 if (rep->vport == MLX5_VPORT_UPLINK)
1408 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1409 else
1ee4457c
OG
1410 netdev->features |= NETIF_F_VLAN_CHALLENGED;
1411
dabeb3b0 1412 netdev->features |= netdev->hw_features;
cb67b832
HHZ
1413}
1414
182570b2
FD
1415static int mlx5e_init_rep(struct mlx5_core_dev *mdev,
1416 struct net_device *netdev,
1417 const struct mlx5e_profile *profile,
1418 void *ppriv)
cb67b832 1419{
6a9764ef 1420 struct mlx5e_priv *priv = netdev_priv(netdev);
182570b2 1421 int err;
6a9764ef 1422
519a0bf5 1423 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
182570b2
FD
1424 if (err)
1425 return err;
6a9764ef 1426
8956f001 1427 priv->channels.params.num_channels = MLX5E_REP_PARAMS_DEF_NUM_CHANNELS;
c139dbfd 1428
025380b2 1429 mlx5e_build_rep_params(netdev);
cb67b832 1430 mlx5e_build_rep_netdev(netdev);
237f258c
FD
1431
1432 mlx5e_timestamp_init(priv);
182570b2
FD
1433
1434 return 0;
1435}
1436
1437static void mlx5e_cleanup_rep(struct mlx5e_priv *priv)
1438{
1439 mlx5e_netdev_cleanup(priv->netdev, priv);
cb67b832
HHZ
1440}
1441
84a09733
GT
1442static int mlx5e_create_rep_ttc_table(struct mlx5e_priv *priv)
1443{
1444 struct ttc_params ttc_params = {};
1445 int tt, err;
1446
1447 priv->fs.ns = mlx5_get_flow_namespace(priv->mdev,
1448 MLX5_FLOW_NAMESPACE_KERNEL);
1449
1450 /* The inner_ttc in the ttc params is intentionally not set */
1451 ttc_params.any_tt_tirn = priv->direct_tir[0].tirn;
1452 mlx5e_set_ttc_ft_params(&ttc_params);
1453 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
1454 ttc_params.indir_tirn[tt] = priv->indir_tir[tt].tirn;
1455
1456 err = mlx5e_create_ttc_table(priv, &ttc_params, &priv->fs.ttc);
1457 if (err) {
1458 netdev_err(priv->netdev, "Failed to create rep ttc table, err=%d\n", err);
1459 return err;
1460 }
1461 return 0;
1462}
1463
092297e0 1464static int mlx5e_create_rep_vport_rx_rule(struct mlx5e_priv *priv)
cb67b832
HHZ
1465{
1466 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1d447a39
SM
1467 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1468 struct mlx5_eswitch_rep *rep = rpriv->rep;
74491de9 1469 struct mlx5_flow_handle *flow_rule;
c966f7d5 1470 struct mlx5_flow_destination dest;
092297e0 1471
c966f7d5
GT
1472 dest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1473 dest.tir_num = priv->direct_tir[0].tirn;
092297e0
GT
1474 flow_rule = mlx5_eswitch_create_vport_rx_rule(esw,
1475 rep->vport,
c966f7d5 1476 &dest);
092297e0
GT
1477 if (IS_ERR(flow_rule))
1478 return PTR_ERR(flow_rule);
1479 rpriv->vport_rx_rule = flow_rule;
1480 return 0;
1481}
1482
1483static int mlx5e_init_rep_rx(struct mlx5e_priv *priv)
1484{
1485 struct mlx5_core_dev *mdev = priv->mdev;
cb67b832 1486 int err;
cb67b832 1487
2c3b5bee
SM
1488 mlx5e_init_l2_addr(priv);
1489
1462e48d
RD
1490 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
1491 if (err) {
1492 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
1493 return err;
1494 }
1495
84a09733 1496 err = mlx5e_create_indirect_rqt(priv);
8f493ffd 1497 if (err)
1462e48d 1498 goto err_close_drop_rq;
cb67b832 1499
db05815b 1500 err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
84a09733
GT
1501 if (err)
1502 goto err_destroy_indirect_rqts;
1503
1504 err = mlx5e_create_indirect_tirs(priv, false);
8f493ffd 1505 if (err)
cb67b832 1506 goto err_destroy_direct_rqts;
cb67b832 1507
db05815b 1508 err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
84a09733
GT
1509 if (err)
1510 goto err_destroy_indirect_tirs;
1511
1512 err = mlx5e_create_rep_ttc_table(priv);
092297e0 1513 if (err)
cb67b832 1514 goto err_destroy_direct_tirs;
cb67b832 1515
84a09733
GT
1516 err = mlx5e_create_rep_vport_rx_rule(priv);
1517 if (err)
1518 goto err_destroy_ttc_table;
1519
cb67b832
HHZ
1520 return 0;
1521
84a09733
GT
1522err_destroy_ttc_table:
1523 mlx5e_destroy_ttc_table(priv, &priv->fs.ttc);
cb67b832 1524err_destroy_direct_tirs:
db05815b 1525 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
84a09733
GT
1526err_destroy_indirect_tirs:
1527 mlx5e_destroy_indirect_tirs(priv, false);
cb67b832 1528err_destroy_direct_rqts:
db05815b 1529 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
84a09733
GT
1530err_destroy_indirect_rqts:
1531 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD
1532err_close_drop_rq:
1533 mlx5e_close_drop_rq(&priv->drop_rq);
cb67b832
HHZ
1534 return err;
1535}
1536
1537static void mlx5e_cleanup_rep_rx(struct mlx5e_priv *priv)
1538{
1d447a39 1539 struct mlx5e_rep_priv *rpriv = priv->ppriv;
cb67b832 1540
5ed99fb4 1541 mlx5_del_flow_rules(rpriv->vport_rx_rule);
84a09733 1542 mlx5e_destroy_ttc_table(priv, &priv->fs.ttc);
db05815b 1543 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
84a09733 1544 mlx5e_destroy_indirect_tirs(priv, false);
db05815b 1545 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
84a09733 1546 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d 1547 mlx5e_close_drop_rq(&priv->drop_rq);
cb67b832
HHZ
1548}
1549
1550static int mlx5e_init_rep_tx(struct mlx5e_priv *priv)
1551{
d9ee0491
OG
1552 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1553 struct mlx5_rep_uplink_priv *uplink_priv;
1554 int tc, err;
cb67b832
HHZ
1555
1556 err = mlx5e_create_tises(priv);
1557 if (err) {
1558 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
1559 return err;
1560 }
d9ee0491 1561
b05af6aa 1562 if (rpriv->rep->vport == MLX5_VPORT_UPLINK) {
d9ee0491
OG
1563 uplink_priv = &rpriv->uplink_priv;
1564
b4a23329
RD
1565 INIT_LIST_HEAD(&uplink_priv->unready_flows);
1566
d9ee0491
OG
1567 /* init shared tc flow table */
1568 err = mlx5e_tc_esw_init(&uplink_priv->tc_ht);
1569 if (err)
1570 goto destroy_tises;
1571
97417f61
EB
1572 mlx5_init_port_tun_entropy(&uplink_priv->tun_entropy, priv->mdev);
1573
d9ee0491
OG
1574 /* init indirect block notifications */
1575 INIT_LIST_HEAD(&uplink_priv->tc_indr_block_priv_list);
1576 uplink_priv->netdevice_nb.notifier_call = mlx5e_nic_rep_netdevice_event;
1577 err = register_netdevice_notifier(&uplink_priv->netdevice_nb);
1578 if (err) {
1579 mlx5_core_err(priv->mdev, "Failed to register netdev notifier\n");
1580 goto tc_esw_cleanup;
1581 }
1582 }
1583
cb67b832 1584 return 0;
d9ee0491
OG
1585
1586tc_esw_cleanup:
1587 mlx5e_tc_esw_cleanup(&uplink_priv->tc_ht);
1588destroy_tises:
1589 for (tc = 0; tc < priv->profile->max_tc; tc++)
1590 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
1591 return err;
1592}
1593
1594static void mlx5e_cleanup_rep_tx(struct mlx5e_priv *priv)
1595{
1596 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1597 int tc;
1598
1599 for (tc = 0; tc < priv->profile->max_tc; tc++)
1600 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
1601
b05af6aa 1602 if (rpriv->rep->vport == MLX5_VPORT_UPLINK) {
d9ee0491
OG
1603 /* clean indirect TC block notifications */
1604 unregister_netdevice_notifier(&rpriv->uplink_priv.netdevice_nb);
1605 mlx5e_rep_indr_clean_block_privs(rpriv);
1606
1607 /* delete shared tc flow table */
1608 mlx5e_tc_esw_cleanup(&rpriv->uplink_priv.tc_ht);
1609 }
cb67b832
HHZ
1610}
1611
9b81d5a9 1612static void mlx5e_rep_enable(struct mlx5e_priv *priv)
b36cdb42 1613{
6d7ee2ed 1614 mlx5e_set_netdev_mtu_boundaries(priv);
b36cdb42
OG
1615}
1616
a90f88fe
GT
1617static int mlx5e_update_rep_rx(struct mlx5e_priv *priv)
1618{
1619 return 0;
1620}
1621
b36cdb42
OG
1622static int uplink_rep_async_event(struct notifier_block *nb, unsigned long event, void *data)
1623{
1624 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
b36cdb42 1625
b4a23329
RD
1626 if (event == MLX5_EVENT_TYPE_PORT_CHANGE) {
1627 struct mlx5_eqe *eqe = data;
b36cdb42 1628
b4a23329
RD
1629 switch (eqe->sub_type) {
1630 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
1631 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
1632 queue_work(priv->wq, &priv->update_carrier_work);
1633 break;
1634 default:
1635 return NOTIFY_DONE;
1636 }
1637
1638 return NOTIFY_OK;
b36cdb42
OG
1639 }
1640
b4a23329
RD
1641 if (event == MLX5_DEV_EVENT_PORT_AFFINITY) {
1642 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1643
1644 queue_work(priv->wq, &rpriv->uplink_priv.reoffload_flows_work);
1645
1646 return NOTIFY_OK;
1647 }
1648
1649 return NOTIFY_DONE;
b36cdb42
OG
1650}
1651
1652static void mlx5e_uplink_rep_enable(struct mlx5e_priv *priv)
1653{
1654 struct net_device *netdev = priv->netdev;
1655 struct mlx5_core_dev *mdev = priv->mdev;
b4a23329 1656 struct mlx5e_rep_priv *rpriv = priv->ppriv;
b36cdb42
OG
1657 u16 max_mtu;
1658
1659 netdev->min_mtu = ETH_MIN_MTU;
1660 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
1661 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
1662 mlx5e_set_dev_port_mtu(priv);
1663
b4a23329
RD
1664 INIT_WORK(&rpriv->uplink_priv.reoffload_flows_work,
1665 mlx5e_tc_reoffload_flows_work);
1666
b36cdb42
OG
1667 mlx5_lag_add(mdev, netdev);
1668 priv->events_nb.notifier_call = uplink_rep_async_event;
1669 mlx5_notifier_register(mdev, &priv->events_nb);
1670#ifdef CONFIG_MLX5_CORE_EN_DCB
1671 mlx5e_dcbnl_initialize(priv);
1672 mlx5e_dcbnl_init_app(priv);
1673#endif
1674}
1675
1676static void mlx5e_uplink_rep_disable(struct mlx5e_priv *priv)
1677{
1678 struct mlx5_core_dev *mdev = priv->mdev;
b4a23329 1679 struct mlx5e_rep_priv *rpriv = priv->ppriv;
b36cdb42
OG
1680
1681#ifdef CONFIG_MLX5_CORE_EN_DCB
1682 mlx5e_dcbnl_delete_app(priv);
1683#endif
1684 mlx5_notifier_unregister(mdev, &priv->events_nb);
b4a23329 1685 cancel_work_sync(&rpriv->uplink_priv.reoffload_flows_work);
b36cdb42
OG
1686 mlx5_lag_remove(mdev);
1687}
1688
9b81d5a9 1689static const struct mlx5e_profile mlx5e_rep_profile = {
cb67b832 1690 .init = mlx5e_init_rep,
182570b2 1691 .cleanup = mlx5e_cleanup_rep,
cb67b832
HHZ
1692 .init_rx = mlx5e_init_rep_rx,
1693 .cleanup_rx = mlx5e_cleanup_rep_rx,
1694 .init_tx = mlx5e_init_rep_tx,
d9ee0491 1695 .cleanup_tx = mlx5e_cleanup_rep_tx,
9b81d5a9 1696 .enable = mlx5e_rep_enable,
a90f88fe 1697 .update_rx = mlx5e_update_rep_rx,
9b81d5a9 1698 .update_stats = mlx5e_rep_update_hw_counters,
20fd0c19 1699 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe_rep,
749359f4 1700 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
cb67b832
HHZ
1701 .max_tc = 1,
1702};
1703
b36cdb42
OG
1704static const struct mlx5e_profile mlx5e_uplink_rep_profile = {
1705 .init = mlx5e_init_rep,
1706 .cleanup = mlx5e_cleanup_rep,
1707 .init_rx = mlx5e_init_rep_rx,
1708 .cleanup_rx = mlx5e_cleanup_rep_rx,
1709 .init_tx = mlx5e_init_rep_tx,
1710 .cleanup_tx = mlx5e_cleanup_rep_tx,
1711 .enable = mlx5e_uplink_rep_enable,
1712 .disable = mlx5e_uplink_rep_disable,
a90f88fe 1713 .update_rx = mlx5e_update_rep_rx,
b36cdb42
OG
1714 .update_stats = mlx5e_uplink_rep_update_hw_counters,
1715 .update_carrier = mlx5e_update_carrier,
1716 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe_rep,
1717 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
1718 .max_tc = MLX5E_MAX_NUM_TC,
1719};
1720
f60f315d
PP
1721static bool
1722is_devlink_port_supported(const struct mlx5_core_dev *dev,
1723 const struct mlx5e_rep_priv *rpriv)
1724{
1725 return rpriv->rep->vport == MLX5_VPORT_UPLINK ||
1726 rpriv->rep->vport == MLX5_VPORT_PF ||
1727 mlx5_eswitch_is_vf_vport(dev->priv.eswitch, rpriv->rep->vport);
1728}
1729
1730static int register_devlink_port(struct mlx5_core_dev *dev,
1731 struct mlx5e_rep_priv *rpriv)
1732{
1733 struct devlink *devlink = priv_to_devlink(dev);
1734 struct mlx5_eswitch_rep *rep = rpriv->rep;
1735 struct netdev_phys_item_id ppid = {};
1736 int ret;
1737
1738 if (!is_devlink_port_supported(dev, rpriv))
1739 return 0;
1740
1741 ret = mlx5e_rep_get_port_parent_id(rpriv->netdev, &ppid);
1742 if (ret)
1743 return ret;
1744
1745 if (rep->vport == MLX5_VPORT_UPLINK)
1746 devlink_port_attrs_set(&rpriv->dl_port,
1747 DEVLINK_PORT_FLAVOUR_PHYSICAL,
1748 PCI_FUNC(dev->pdev->devfn), false, 0,
1749 &ppid.id[0], ppid.id_len);
1750 else if (rep->vport == MLX5_VPORT_PF)
1751 devlink_port_attrs_pci_pf_set(&rpriv->dl_port,
1752 &ppid.id[0], ppid.id_len,
1753 dev->pdev->devfn);
1754 else if (mlx5_eswitch_is_vf_vport(dev->priv.eswitch, rpriv->rep->vport))
1755 devlink_port_attrs_pci_vf_set(&rpriv->dl_port,
1756 &ppid.id[0], ppid.id_len,
1757 dev->pdev->devfn,
1758 rep->vport - 1);
1759
1760 return devlink_port_register(devlink, &rpriv->dl_port, rep->vport);
1761}
1762
1763static void unregister_devlink_port(struct mlx5_core_dev *dev,
1764 struct mlx5e_rep_priv *rpriv)
1765{
1766 if (is_devlink_port_supported(dev, rpriv))
1767 devlink_port_unregister(&rpriv->dl_port);
1768}
1769
1d447a39 1770/* e-Switch vport representors */
1d447a39 1771static int
4c66df01 1772mlx5e_vport_rep_load(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep)
1d447a39 1773{
b36cdb42 1774 const struct mlx5e_profile *profile;
1d447a39 1775 struct mlx5e_rep_priv *rpriv;
26e59d80 1776 struct net_device *netdev;
779d986d 1777 int nch, err;
26e59d80 1778
1d447a39
SM
1779 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
1780 if (!rpriv)
1781 return -ENOMEM;
1782
d9ee0491
OG
1783 /* rpriv->rep to be looked up when profile->init() is called */
1784 rpriv->rep = rep;
1785
779d986d 1786 nch = mlx5e_get_max_num_channels(dev);
9b81d5a9
VP
1787 profile = (rep->vport == MLX5_VPORT_UPLINK) ?
1788 &mlx5e_uplink_rep_profile : &mlx5e_rep_profile;
b36cdb42 1789 netdev = mlx5e_create_netdev(dev, profile, nch, rpriv);
26e59d80
MHY
1790 if (!netdev) {
1791 pr_warn("Failed to create representor netdev for vport %d\n",
1792 rep->vport);
1d447a39 1793 kfree(rpriv);
cb67b832
HHZ
1794 return -EINVAL;
1795 }
26e59d80 1796
5ed99fb4 1797 rpriv->netdev = netdev;
8693115a 1798 rep->rep_data[REP_ETH].priv = rpriv;
5ed99fb4 1799 INIT_LIST_HEAD(&rpriv->vport_sqs_list);
26e59d80 1800
b05af6aa 1801 if (rep->vport == MLX5_VPORT_UPLINK) {
aec002f6
OG
1802 err = mlx5e_create_mdev_resources(dev);
1803 if (err)
1804 goto err_destroy_netdev;
1805 }
1806
2c3b5bee 1807 err = mlx5e_attach_netdev(netdev_priv(netdev));
26e59d80
MHY
1808 if (err) {
1809 pr_warn("Failed to attach representor netdev for vport %d\n",
1810 rep->vport);
aec002f6 1811 goto err_destroy_mdev_resources;
26e59d80
MHY
1812 }
1813
37b498ff
HHZ
1814 err = mlx5e_rep_neigh_init(rpriv);
1815 if (err) {
1816 pr_warn("Failed to initialized neighbours handling for vport %d\n",
1817 rep->vport);
1818 goto err_detach_netdev;
1819 }
1820
f60f315d
PP
1821 err = register_devlink_port(dev, rpriv);
1822 if (err) {
1823 esw_warn(dev, "Failed to register devlink port %d\n",
1824 rep->vport);
1825 goto err_neigh_cleanup;
1826 }
1827
26e59d80
MHY
1828 err = register_netdev(netdev);
1829 if (err) {
1830 pr_warn("Failed to register representor netdev for vport %d\n",
1831 rep->vport);
f60f315d 1832 goto err_devlink_cleanup;
26e59d80
MHY
1833 }
1834
f60f315d
PP
1835 if (is_devlink_port_supported(dev, rpriv))
1836 devlink_port_type_eth_set(&rpriv->dl_port, netdev);
cb67b832 1837 return 0;
26e59d80 1838
f60f315d
PP
1839err_devlink_cleanup:
1840 unregister_devlink_port(dev, rpriv);
1841
37b498ff
HHZ
1842err_neigh_cleanup:
1843 mlx5e_rep_neigh_cleanup(rpriv);
1844
26e59d80 1845err_detach_netdev:
2c3b5bee 1846 mlx5e_detach_netdev(netdev_priv(netdev));
26e59d80 1847
aec002f6 1848err_destroy_mdev_resources:
b05af6aa 1849 if (rep->vport == MLX5_VPORT_UPLINK)
aec002f6
OG
1850 mlx5e_destroy_mdev_resources(dev);
1851
26e59d80 1852err_destroy_netdev:
2c3b5bee 1853 mlx5e_destroy_netdev(netdev_priv(netdev));
1d447a39 1854 kfree(rpriv);
26e59d80 1855 return err;
cb67b832
HHZ
1856}
1857
1d447a39 1858static void
4c66df01 1859mlx5e_vport_rep_unload(struct mlx5_eswitch_rep *rep)
cb67b832 1860{
5ed99fb4
MB
1861 struct mlx5e_rep_priv *rpriv = mlx5e_rep_to_rep_priv(rep);
1862 struct net_device *netdev = rpriv->netdev;
1d447a39 1863 struct mlx5e_priv *priv = netdev_priv(netdev);
f60f315d 1864 struct mlx5_core_dev *dev = priv->mdev;
1d447a39 1865 void *ppriv = priv->ppriv;
cb67b832 1866
f60f315d
PP
1867 if (is_devlink_port_supported(dev, rpriv))
1868 devlink_port_type_clear(&rpriv->dl_port);
5ed99fb4 1869 unregister_netdev(netdev);
f60f315d 1870 unregister_devlink_port(dev, rpriv);
37b498ff 1871 mlx5e_rep_neigh_cleanup(rpriv);
1d447a39 1872 mlx5e_detach_netdev(priv);
b05af6aa 1873 if (rep->vport == MLX5_VPORT_UPLINK)
aec002f6 1874 mlx5e_destroy_mdev_resources(priv->mdev);
1d447a39
SM
1875 mlx5e_destroy_netdev(priv);
1876 kfree(ppriv); /* mlx5e_rep_priv */
1877}
1878
22215908
MB
1879static void *mlx5e_vport_rep_get_proto_dev(struct mlx5_eswitch_rep *rep)
1880{
1881 struct mlx5e_rep_priv *rpriv;
1882
1883 rpriv = mlx5e_rep_to_rep_priv(rep);
1884
1885 return rpriv->netdev;
1886}
1887
8693115a
PP
1888static const struct mlx5_eswitch_rep_ops rep_ops = {
1889 .load = mlx5e_vport_rep_load,
1890 .unload = mlx5e_vport_rep_unload,
1891 .get_proto_dev = mlx5e_vport_rep_get_proto_dev
1892};
1893
aec002f6 1894void mlx5e_rep_register_vport_reps(struct mlx5_core_dev *mdev)
1d447a39 1895{
aec002f6 1896 struct mlx5_eswitch *esw = mdev->priv.eswitch;
1d447a39 1897
8693115a 1898 mlx5_eswitch_register_vport_reps(esw, &rep_ops, REP_ETH);
1d447a39
SM
1899}
1900
aec002f6 1901void mlx5e_rep_unregister_vport_reps(struct mlx5_core_dev *mdev)
1d447a39 1902{
1d447a39 1903 struct mlx5_eswitch *esw = mdev->priv.eswitch;
1d447a39 1904
f8e8fa02 1905 mlx5_eswitch_unregister_vport_reps(esw, REP_ETH);
1d447a39 1906}