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net/mlx5e: Add channel events counter
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.c
CommitLineData
c0752f2b
KH		 1/*
2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
e185d43f 34#include "en_accel/ipsec.h"
43585a41 35#include "en_accel/tls.h"
c0752f2b
KH		 36
37static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
f24686e8 46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
bf239741
IL		 47
48#ifdef CONFIG_MLX5_EN_TLS
49 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
51#endif
52
c0752f2b
KH		 53 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
f24686e8 55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
c0752f2b
KH		 56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
cbe73aae 62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
c0752f2b
KH		 63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
c0752f2b
KH		 68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
db75373c 70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
86155656 71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
f65a59ff 72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
bc5a7ccd 73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_udp_seg_rem) },
f65a59ff 74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
c0752f2b
KH		 75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
dc983f0e 86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
a1bf74dc 87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
2d7103c8
TT		 88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
57d689a8 91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
c0752f2b
KH		 92};
93
94#define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
95
96static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
97{
98 return NUM_SW_COUNTERS;
99}
100
101static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
102{
103 int i;
104
105 for (i = 0; i < NUM_SW_COUNTERS; i++)
106 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
107 return idx;
108}
109
110static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
111{
112 int i;
113
114 for (i = 0; i < NUM_SW_COUNTERS; i++)
115 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
116 return idx;
117}
118
868a01a2 119void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
19386177
KH		 120{
121 struct mlx5e_sw_stats temp, *s = &temp;
05909bab 122 int i;
19386177
KH		 123
124 memset(s, 0, sizeof(*s));
19386177 125
05909bab
EBE		 126 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) {
127 struct mlx5e_channel_stats *channel_stats =
128 &priv->channel_stats[i];
129 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
130 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch;
131 int j;
19386177
KH		 132
133 s->rx_packets += rq_stats->packets;
134 s->rx_bytes += rq_stats->bytes;
135 s->rx_lro_packets += rq_stats->lro_packets;
136 s->rx_lro_bytes += rq_stats->lro_bytes;
137 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
138 s->rx_csum_none += rq_stats->csum_none;
139 s->rx_csum_complete += rq_stats->csum_complete;
140 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
141 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
142 s->rx_xdp_drop += rq_stats->xdp_drop;
143 s->rx_xdp_tx += rq_stats->xdp_tx;
cbe73aae 144 s->rx_xdp_tx_cqe += rq_stats->xdp_tx_cqe;
19386177
KH		 145 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
146 s->rx_wqe_err += rq_stats->wqe_err;
147 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
148 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
149 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
150 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
151 s->rx_page_reuse += rq_stats->page_reuse;
152 s->rx_cache_reuse += rq_stats->cache_reuse;
153 s->rx_cache_full += rq_stats->cache_full;
154 s->rx_cache_empty += rq_stats->cache_empty;
155 s->rx_cache_busy += rq_stats->cache_busy;
156 s->rx_cache_waive += rq_stats->cache_waive;
dc983f0e 157 s->rx_congst_umr += rq_stats->congst_umr;
a1bf74dc 158 s->ch_events += ch_stats->events;
2d7103c8
TT		 159 s->ch_poll += ch_stats->poll;
160 s->ch_arm += ch_stats->arm;
161 s->ch_aff_change += ch_stats->aff_change;
19386177
KH		 162 s->ch_eq_rearm += ch_stats->eq_rearm;
163
05909bab
EBE		 164 for (j = 0; j < priv->max_opened_tc; j++) {
165 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
19386177
KH		 166
167 s->tx_packets += sq_stats->packets;
168 s->tx_bytes += sq_stats->bytes;
169 s->tx_tso_packets += sq_stats->tso_packets;
170 s->tx_tso_bytes += sq_stats->tso_bytes;
171 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
172 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
173 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
174 s->tx_queue_stopped += sq_stats->stopped;
175 s->tx_queue_wake += sq_stats->wake;
bc5a7ccd 176 s->tx_udp_seg_rem += sq_stats->udp_seg_rem;
19386177 177 s->tx_queue_dropped += sq_stats->dropped;
16cc14d8 178 s->tx_cqe_err += sq_stats->cqe_err;
db75373c 179 s->tx_recover += sq_stats->recover;
19386177
KH		 180 s->tx_xmit_more += sq_stats->xmit_more;
181 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
182 s->tx_csum_none += sq_stats->csum_none;
183 s->tx_csum_partial += sq_stats->csum_partial;
bf239741
IL		 184#ifdef CONFIG_MLX5_EN_TLS
185 s->tx_tls_ooo += sq_stats->tls_ooo;
186 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
187#endif
86155656 188 s->tx_cqes += sq_stats->cqes;
19386177
KH		 189 }
190 }
191
19386177
KH		 192 memcpy(&priv->stats.sw, s, sizeof(*s));
193}
194
fd8dcdb8
KH		 195static const struct counter_desc q_stats_desc[] = {
196 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
197};
198
7cbaf9a3
MS		 199static const struct counter_desc drop_rq_stats_desc[] = {
200 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
201};
202
fd8dcdb8 203#define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
7cbaf9a3 204#define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
fd8dcdb8
KH		 205
206static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
207{
7cbaf9a3
MS		 208 int num_stats = 0;
209
210 if (priv->q_counter)
211 num_stats += NUM_Q_COUNTERS;
212
213 if (priv->drop_rq_q_counter)
214 num_stats += NUM_DROP_RQ_COUNTERS;
215
216 return num_stats;
fd8dcdb8
KH		 217}
218
219static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
220{
221 int i;
222
223 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
7cbaf9a3
MS		 224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
225 q_stats_desc[i].format);
226
227 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
228 strcpy(data + (idx++) * ETH_GSTRING_LEN,
229 drop_rq_stats_desc[i].format);
230
fd8dcdb8
KH		 231 return idx;
232}
233
234static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
235{
236 int i;
237
238 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
7cbaf9a3
MS		 239 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
240 q_stats_desc, i);
241 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
242 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
243 drop_rq_stats_desc, i);
fd8dcdb8
KH		 244 return idx;
245}
246
19386177
KH		 247static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
248{
249 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
250 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
19386177 251
7cbaf9a3
MS		 252 if (priv->q_counter &&
253 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
254 sizeof(out)))
255 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
256 out, out_of_buffer);
257 if (priv->drop_rq_q_counter &&
258 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
259 out, sizeof(out)))
260 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
261 out_of_buffer);
19386177
KH		 262}
263
5c298143
MS		 264#define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
265static const struct counter_desc vnic_env_stats_desc[] = {
266 { "rx_steer_missed_packets",
267 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
268};
269
270#define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
271
272static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
273{
274 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
275 NUM_VNIC_ENV_COUNTERS : 0;
276}
277
278static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
279 int idx)
280{
281 int i;
282
283 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
284 return idx;
285
286 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
287 strcpy(data + (idx++) * ETH_GSTRING_LEN,
288 vnic_env_stats_desc[i].format);
289 return idx;
290}
291
292static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
293 int idx)
294{
295 int i;
296
297 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
298 return idx;
299
300 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
301 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
302 vnic_env_stats_desc, i);
303 return idx;
304}
305
306static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
307{
308 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
309 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
310 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
311 struct mlx5_core_dev *mdev = priv->mdev;
312
313 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
314 return;
315
316 MLX5_SET(query_vnic_env_in, in, opcode,
317 MLX5_CMD_OP_QUERY_VNIC_ENV);
318 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
319 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
320 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
321}
322
40cab9f1
KH		 323#define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
324static const struct counter_desc vport_stats_desc[] = {
325 { "rx_vport_unicast_packets",
326 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
327 { "rx_vport_unicast_bytes",
328 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
329 { "tx_vport_unicast_packets",
330 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
331 { "tx_vport_unicast_bytes",
332 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
333 { "rx_vport_multicast_packets",
334 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
335 { "rx_vport_multicast_bytes",
336 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
337 { "tx_vport_multicast_packets",
338 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
339 { "tx_vport_multicast_bytes",
340 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
341 { "rx_vport_broadcast_packets",
342 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
343 { "rx_vport_broadcast_bytes",
344 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
345 { "tx_vport_broadcast_packets",
346 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
347 { "tx_vport_broadcast_bytes",
348 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
349 { "rx_vport_rdma_unicast_packets",
350 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
351 { "rx_vport_rdma_unicast_bytes",
352 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
353 { "tx_vport_rdma_unicast_packets",
354 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
355 { "tx_vport_rdma_unicast_bytes",
356 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
357 { "rx_vport_rdma_multicast_packets",
358 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
359 { "rx_vport_rdma_multicast_bytes",
360 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
361 { "tx_vport_rdma_multicast_packets",
362 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
363 { "tx_vport_rdma_multicast_bytes",
364 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
365};
366
367#define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
368
369static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
370{
371 return NUM_VPORT_COUNTERS;
372}
373
374static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
375 int idx)
376{
377 int i;
378
379 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
380 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
381 return idx;
382}
383
384static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
385 int idx)
386{
387 int i;
388
389 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
390 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
391 vport_stats_desc, i);
392 return idx;
393}
394
19386177
KH		 395static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
396{
397 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
398 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
399 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
400 struct mlx5_core_dev *mdev = priv->mdev;
401
402 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
403 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
404 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
405 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
406}
407
6e6ef814
KH		 408#define PPORT_802_3_OFF(c) \
409 MLX5_BYTE_OFF(ppcnt_reg, \
410 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
411static const struct counter_desc pport_802_3_stats_desc[] = {
412 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
413 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
414 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
415 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
416 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
417 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
418 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
419 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
420 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
421 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
422 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
423 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
424 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
425 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
426 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
427 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
428 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
429 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
430};
431
432#define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
433
434static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
435{
436 return NUM_PPORT_802_3_COUNTERS;
437}
438
439static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
440 int idx)
441{
442 int i;
443
444 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
445 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
446 return idx;
447}
448
449static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
450 int idx)
451{
452 int i;
453
454 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
455 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
456 pport_802_3_stats_desc, i);
457 return idx;
458}
459
19386177
KH		 460static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
461{
462 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
463 struct mlx5_core_dev *mdev = priv->mdev;
464 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
465 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
466 void *out;
467
468 MLX5_SET(ppcnt_reg, in, local_port, 1);
469 out = pstats->IEEE_802_3_counters;
470 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
471 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
472}
473
fc8e64a3
KH		 474#define PPORT_2863_OFF(c) \
475 MLX5_BYTE_OFF(ppcnt_reg, \
476 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
477static const struct counter_desc pport_2863_stats_desc[] = {
478 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
479 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
480 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
481};
482
483#define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
484
485static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
486{
487 return NUM_PPORT_2863_COUNTERS;
488}
489
490static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
491 int idx)
492{
493 int i;
494
495 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
496 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
497 return idx;
498}
499
500static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
501 int idx)
502{
503 int i;
504
505 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
506 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
507 pport_2863_stats_desc, i);
508 return idx;
509}
510
19386177
KH		 511static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
512{
513 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
514 struct mlx5_core_dev *mdev = priv->mdev;
515 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
516 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
517 void *out;
518
519 MLX5_SET(ppcnt_reg, in, local_port, 1);
520 out = pstats->RFC_2863_counters;
521 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
522 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
523}
524
e0e0def9
KH		 525#define PPORT_2819_OFF(c) \
526 MLX5_BYTE_OFF(ppcnt_reg, \
527 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
528static const struct counter_desc pport_2819_stats_desc[] = {
529 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
530 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
531 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
532 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
533 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
534 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
535 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
536 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
537 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
538 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
539 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
540 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
541 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
542};
543
544#define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
545
546static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
547{
548 return NUM_PPORT_2819_COUNTERS;
549}
550
551static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
552 int idx)
553{
554 int i;
555
556 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
557 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
558 return idx;
559}
560
561static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
562 int idx)
563{
564 int i;
565
566 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
567 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
568 pport_2819_stats_desc, i);
569 return idx;
570}
571
19386177
KH		 572static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
573{
574 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
575 struct mlx5_core_dev *mdev = priv->mdev;
576 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
577 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
578 void *out;
579
580 MLX5_SET(ppcnt_reg, in, local_port, 1);
581 out = pstats->RFC_2819_counters;
582 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
583 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
584}
585
2e4df0b2
KH		 586#define PPORT_PHY_STATISTICAL_OFF(c) \
587 MLX5_BYTE_OFF(ppcnt_reg, \
588 counter_set.phys_layer_statistical_cntrs.c##_high)
589static const struct counter_desc pport_phy_statistical_stats_desc[] = {
590 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
591 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
592};
593
6ab75516 594#define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
2e4df0b2
KH		 595
596static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
597{
6ab75516 598 /* "1" for link_down_events special counter */
2e4df0b2 599 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
6ab75516 600 NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1;
2e4df0b2
KH		 601}
602
603static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
604 int idx)
605{
606 int i;
607
6ab75516
SM		 608 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
609
610 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
611 return idx;
612
613 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
614 strcpy(data + (idx++) * ETH_GSTRING_LEN,
615 pport_phy_statistical_stats_desc[i].format);
2e4df0b2
KH		 616 return idx;
617}
618
619static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
620{
621 int i;
622
6ab75516
SM		 623 /* link_down_events_phy has special handling since it is not stored in __be64 format */
624 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
625 counter_set.phys_layer_cntrs.link_down_events);
626
627 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
628 return idx;
629
630 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
631 data[idx++] =
632 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
633 pport_phy_statistical_stats_desc, i);
2e4df0b2
KH		 634 return idx;
635}
636
19386177
KH		 637static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
638{
639 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
640 struct mlx5_core_dev *mdev = priv->mdev;
641 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
642 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
643 void *out;
644
645 MLX5_SET(ppcnt_reg, in, local_port, 1);
646 out = pstats->phy_counters;
647 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
648 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
649
650 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
651 return;
652
653 out = pstats->phy_statistical_counters;
654 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
655 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
656}
657
3488bd4c
KH		 658#define PPORT_ETH_EXT_OFF(c) \
659 MLX5_BYTE_OFF(ppcnt_reg, \
660 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
661static const struct counter_desc pport_eth_ext_stats_desc[] = {
662 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
663};
664
665#define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
666
667static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
668{
669 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
670 return NUM_PPORT_ETH_EXT_COUNTERS;
671
672 return 0;
673}
674
675static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
676 int idx)
677{
678 int i;
679
680 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
681 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
682 strcpy(data + (idx++) * ETH_GSTRING_LEN,
683 pport_eth_ext_stats_desc[i].format);
684 return idx;
685}
686
687static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
688 int idx)
689{
690 int i;
691
692 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
693 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
694 data[idx++] =
695 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
696 pport_eth_ext_stats_desc, i);
697 return idx;
698}
699
19386177
KH		 700static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
701{
702 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
703 struct mlx5_core_dev *mdev = priv->mdev;
704 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
705 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
706 void *out;
707
708 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
709 return;
710
711 MLX5_SET(ppcnt_reg, in, local_port, 1);
712 out = pstats->eth_ext_counters;
713 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
714 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
715}
716
9fd2b5f1
KH		 717#define PCIE_PERF_OFF(c) \
718 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
719static const struct counter_desc pcie_perf_stats_desc[] = {
720 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
721 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
722};
723
724#define PCIE_PERF_OFF64(c) \
725 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
726static const struct counter_desc pcie_perf_stats_desc64[] = {
727 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
728};
729
730static const struct counter_desc pcie_perf_stall_stats_desc[] = {
731 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
732 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
733 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
734 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
735};
736
737#define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
738#define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
739#define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
740
741static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
742{
743 int num_stats = 0;
744
745 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
746 num_stats += NUM_PCIE_PERF_COUNTERS;
747
748 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
749 num_stats += NUM_PCIE_PERF_COUNTERS64;
750
751 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
752 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
753
754 return num_stats;
755}
756
757static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
758 int idx)
759{
760 int i;
761
762 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
763 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
764 strcpy(data + (idx++) * ETH_GSTRING_LEN,
765 pcie_perf_stats_desc[i].format);
766
767 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
768 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
769 strcpy(data + (idx++) * ETH_GSTRING_LEN,
770 pcie_perf_stats_desc64[i].format);
771
772 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
773 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
774 strcpy(data + (idx++) * ETH_GSTRING_LEN,
775 pcie_perf_stall_stats_desc[i].format);
776 return idx;
777}
778
779static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
780 int idx)
781{
782 int i;
783
784 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
785 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
786 data[idx++] =
787 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
788 pcie_perf_stats_desc, i);
789
790 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
791 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
792 data[idx++] =
793 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
794 pcie_perf_stats_desc64, i);
795
796 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
797 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
798 data[idx++] =
799 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
800 pcie_perf_stall_stats_desc, i);
801 return idx;
802}
803
19386177
KH		 804static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
805{
806 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
807 struct mlx5_core_dev *mdev = priv->mdev;
808 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
809 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
810 void *out;
811
812 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
813 return;
814
815 out = pcie_stats->pcie_perf_counters;
816 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
817 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
818}
819
4377bea2
KH		 820#define PPORT_PER_PRIO_OFF(c) \
821 MLX5_BYTE_OFF(ppcnt_reg, \
822 counter_set.eth_per_prio_grp_data_layout.c##_high)
e6000651
KH		 823static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
824 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
825 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
826 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
827 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
828};
829
830#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
831
832static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv)
833{
834 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
835}
836
837static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
838 u8 *data,
839 int idx)
840{
841 int i, prio;
842
843 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
844 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
845 sprintf(data + (idx++) * ETH_GSTRING_LEN,
846 pport_per_prio_traffic_stats_desc[i].format, prio);
847 }
848
849 return idx;
850}
851
852static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
853 u64 *data,
854 int idx)
855{
856 int i, prio;
857
858 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
859 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
860 data[idx++] =
861 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
862 pport_per_prio_traffic_stats_desc, i);
863 }
864
865 return idx;
866}
867
4377bea2
KH		 868static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
869 /* %s is "global" or "prio{i}" */
870 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
871 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
872 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
873 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
874 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
875};
876
2fcb12df
IK		 877static const struct counter_desc pport_pfc_stall_stats_desc[] = {
878 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
879 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
880};
881
4377bea2 882#define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
2fcb12df
IK		 883#define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
884 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
885 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
4377bea2
KH		 886
887static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
888{
889 struct mlx5_core_dev *mdev = priv->mdev;
890 u8 pfc_en_tx;
891 u8 pfc_en_rx;
892 int err;
893
894 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
895 return 0;
896
897 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
898
899 return err ? 0 : pfc_en_tx | pfc_en_rx;
900}
901
902static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
903{
904 struct mlx5_core_dev *mdev = priv->mdev;
905 u32 rx_pause;
906 u32 tx_pause;
907 int err;
908
909 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
910 return false;
911
912 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
913
914 return err ? false : rx_pause | tx_pause;
915}
916
917static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
918{
919 return (mlx5e_query_global_pause_combined(priv) +
920 hweight8(mlx5e_query_pfc_combined(priv))) *
2fcb12df
IK		 921 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
922 NUM_PPORT_PFC_STALL_COUNTERS(priv);
4377bea2
KH		 923}
924
925static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
926 u8 *data,
927 int idx)
928{
929 unsigned long pfc_combined;
930 int i, prio;
931
932 pfc_combined = mlx5e_query_pfc_combined(priv);
933 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
934 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
935 char pfc_string[ETH_GSTRING_LEN];
936
937 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
938 sprintf(data + (idx++) * ETH_GSTRING_LEN,
939 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
940 }
941 }
942
943 if (mlx5e_query_global_pause_combined(priv)) {
944 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
945 sprintf(data + (idx++) * ETH_GSTRING_LEN,
946 pport_per_prio_pfc_stats_desc[i].format, "global");
947 }
948 }
949
2fcb12df
IK		 950 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
951 strcpy(data + (idx++) * ETH_GSTRING_LEN,
952 pport_pfc_stall_stats_desc[i].format);
953
4377bea2
KH		 954 return idx;
955}
956
957static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
958 u64 *data,
959 int idx)
960{
961 unsigned long pfc_combined;
962 int i, prio;
963
964 pfc_combined = mlx5e_query_pfc_combined(priv);
965 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
966 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
967 data[idx++] =
968 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
969 pport_per_prio_pfc_stats_desc, i);
970 }
971 }
972
973 if (mlx5e_query_global_pause_combined(priv)) {
974 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
975 data[idx++] =
976 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
977 pport_per_prio_pfc_stats_desc, i);
978 }
979 }
980
2fcb12df
IK		 981 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
982 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
983 pport_pfc_stall_stats_desc, i);
984
4377bea2
KH		 985 return idx;
986}
987
a8984281
KH		 988static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
989{
990 return mlx5e_grp_per_prio_traffic_get_num_stats(priv) +
991 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
992}
993
994static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
995 int idx)
996{
997 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
998 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
999 return idx;
1000}
1001
1002static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
1003 int idx)
1004{
1005 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1006 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1007 return idx;
1008}
1009
19386177
KH		 1010static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
1011{
1012 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1013 struct mlx5_core_dev *mdev = priv->mdev;
1014 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1015 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1016 int prio;
1017 void *out;
1018
1019 MLX5_SET(ppcnt_reg, in, local_port, 1);
1020 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1021 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1022 out = pstats->per_prio_counters[prio];
1023 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1024 mlx5_core_access_reg(mdev, in, sz, out, sz,
1025 MLX5_REG_PPCNT, 0, 0);
1026 }
1027}
1028
0e6f01a4
KH		 1029static const struct counter_desc mlx5e_pme_status_desc[] = {
1030 { "module_unplug", 8 },
1031};
1032
1033static const struct counter_desc mlx5e_pme_error_desc[] = {
1034 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1035 { "module_high_temp", 48 }, /* high temperature */
1036 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1037};
1038
1039#define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1040#define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1041
1042static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1043{
1044 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1045}
1046
1047static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1048 int idx)
1049{
1050 int i;
1051
1052 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1053 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1054
1055 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1056 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1057
1058 return idx;
1059}
1060
1061static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1062 int idx)
1063{
1064 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1065 int i;
1066
1067 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1068 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1069 mlx5e_pme_status_desc, i);
1070
1071 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1072 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1073 mlx5e_pme_error_desc, i);
1074
1075 return idx;
1076}
1077
e185d43f
KH		 1078static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1079{
1080 return mlx5e_ipsec_get_count(priv);
1081}
1082
1083static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1084 int idx)
1085{
1086 return idx + mlx5e_ipsec_get_strings(priv,
1087 data + idx * ETH_GSTRING_LEN);
1088}
1089
1090static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1091 int idx)
1092{
1093 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1094}
1095
19386177
KH		 1096static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1097{
1098 mlx5e_ipsec_update_stats(priv);
1099}
1100
43585a41
IL		 1101static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1102{
1103 return mlx5e_tls_get_count(priv);
1104}
1105
1106static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1107 int idx)
1108{
1109 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1110}
1111
1112static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1113{
1114 return idx + mlx5e_tls_get_stats(priv, data + idx);
1115}
1116
1fe85006
KH		 1117static const struct counter_desc rq_stats_desc[] = {
1118 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1119 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1120 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1121 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1122 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1123 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1124 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1125 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
cbe73aae 1126 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_cqe) },
1fe85006
KH		 1127 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
1128 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1129 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
f24686e8 1130 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1fe85006
KH		 1131 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1132 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
1133 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1134 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1135 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1136 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1137 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1138 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1139 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1140 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1141 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
dc983f0e 1142 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
1fe85006
KH		 1143};
1144
1145static const struct counter_desc sq_stats_desc[] = {
1146 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1147 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1148 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1149 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1150 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1151 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1152 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1153 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
f24686e8 1154 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1fe85006
KH		 1155 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1156 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1157 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1fe85006
KH		 1158 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1159 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
db75373c 1160 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
86155656 1161 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
f65a59ff
TT		 1162 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1163 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1fe85006
KH		 1164};
1165
57d689a8 1166static const struct counter_desc ch_stats_desc[] = {
a1bf74dc 1167 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
2d7103c8
TT		 1168 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
1169 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
1170 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
57d689a8
EBE		 1171 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1172};
1173
1fe85006
KH		 1174#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1175#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
57d689a8 1176#define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1fe85006
KH		 1177
1178static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1179{
05909bab
EBE		 1180 int max_nch = priv->profile->max_nch(priv->mdev);
1181
05909bab
EBE		 1182 return (NUM_RQ_STATS * max_nch) +
1183 (NUM_CH_STATS * max_nch) +
1184 (NUM_SQ_STATS * max_nch * priv->max_opened_tc);
1fe85006
KH		 1185}
1186
1187static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1188 int idx)
1189{
05909bab 1190 int max_nch = priv->profile->max_nch(priv->mdev);
1fe85006
KH		 1191 int i, j, tc;
1192
05909bab 1193 for (i = 0; i < max_nch; i++)
57d689a8
EBE		 1194 for (j = 0; j < NUM_CH_STATS; j++)
1195 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1196 ch_stats_desc[j].format, i);
1197
05909bab 1198 for (i = 0; i < max_nch; i++)
1fe85006
KH		 1199 for (j = 0; j < NUM_RQ_STATS; j++)
1200 sprintf(data + (idx++) * ETH_GSTRING_LEN, rq_stats_desc[j].format, i);
1201
05909bab
EBE		 1202 for (tc = 0; tc < priv->max_opened_tc; tc++)
1203 for (i = 0; i < max_nch; i++)
1fe85006
KH		 1204 for (j = 0; j < NUM_SQ_STATS; j++)
1205 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1206 sq_stats_desc[j].format,
1207 priv->channel_tc2txq[i][tc]);
1208
1209 return idx;
1210}
1211
1212static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1213 int idx)
1214{
05909bab 1215 int max_nch = priv->profile->max_nch(priv->mdev);
1fe85006
KH		 1216 int i, j, tc;
1217
05909bab 1218 for (i = 0; i < max_nch; i++)
57d689a8
EBE		 1219 for (j = 0; j < NUM_CH_STATS; j++)
1220 data[idx++] =
05909bab 1221 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch,
57d689a8
EBE		 1222 ch_stats_desc, j);
1223
05909bab 1224 for (i = 0; i < max_nch; i++)
1fe85006
KH		 1225 for (j = 0; j < NUM_RQ_STATS; j++)
1226 data[idx++] =
05909bab 1227 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq,
1fe85006
KH		 1228 rq_stats_desc, j);
1229
05909bab
EBE		 1230 for (tc = 0; tc < priv->max_opened_tc; tc++)
1231 for (i = 0; i < max_nch; i++)
1fe85006
KH		 1232 for (j = 0; j < NUM_SQ_STATS; j++)
1233 data[idx++] =
05909bab 1234 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc],
1fe85006
KH		 1235 sq_stats_desc, j);
1236
1237 return idx;
1238}
1239
19386177 1240/* The stats groups order is opposite to the update_stats() order calls */
c0752f2b
KH		 1241const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1242 {
1243 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1244 .fill_strings = mlx5e_grp_sw_fill_strings,
1245 .fill_stats = mlx5e_grp_sw_fill_stats,
19386177 1246 .update_stats = mlx5e_grp_sw_update_stats,
fd8dcdb8
KH		 1247 },
1248 {
1249 .get_num_stats = mlx5e_grp_q_get_num_stats,
1250 .fill_strings = mlx5e_grp_q_fill_strings,
1251 .fill_stats = mlx5e_grp_q_fill_stats,
19386177
KH		 1252 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1253 .update_stats = mlx5e_grp_q_update_stats,
fd8dcdb8 1254 },
5c298143
MS		 1255 {
1256 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1257 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1258 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1259 .update_stats = mlx5e_grp_vnic_env_update_stats,
1260 },
40cab9f1
KH		 1261 {
1262 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1263 .fill_strings = mlx5e_grp_vport_fill_strings,
1264 .fill_stats = mlx5e_grp_vport_fill_stats,
19386177
KH		 1265 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1266 .update_stats = mlx5e_grp_vport_update_stats,
40cab9f1 1267 },
6e6ef814
KH		 1268 {
1269 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1270 .fill_strings = mlx5e_grp_802_3_fill_strings,
1271 .fill_stats = mlx5e_grp_802_3_fill_stats,
19386177
KH		 1272 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1273 .update_stats = mlx5e_grp_802_3_update_stats,
6e6ef814 1274 },
fc8e64a3
KH		 1275 {
1276 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1277 .fill_strings = mlx5e_grp_2863_fill_strings,
1278 .fill_stats = mlx5e_grp_2863_fill_stats,
19386177 1279 .update_stats = mlx5e_grp_2863_update_stats,
fc8e64a3 1280 },
e0e0def9
KH		 1281 {
1282 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1283 .fill_strings = mlx5e_grp_2819_fill_strings,
1284 .fill_stats = mlx5e_grp_2819_fill_stats,
19386177 1285 .update_stats = mlx5e_grp_2819_update_stats,
e0e0def9 1286 },
2e4df0b2
KH		 1287 {
1288 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1289 .fill_strings = mlx5e_grp_phy_fill_strings,
1290 .fill_stats = mlx5e_grp_phy_fill_stats,
19386177 1291 .update_stats = mlx5e_grp_phy_update_stats,
2e4df0b2 1292 },
3488bd4c
KH		 1293 {
1294 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1295 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1296 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
19386177 1297 .update_stats = mlx5e_grp_eth_ext_update_stats,
9fd2b5f1
KH		 1298 },
1299 {
1300 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1301 .fill_strings = mlx5e_grp_pcie_fill_strings,
1302 .fill_stats = mlx5e_grp_pcie_fill_stats,
19386177 1303 .update_stats = mlx5e_grp_pcie_update_stats,
9fd2b5f1 1304 },
e6000651 1305 {
a8984281
KH		 1306 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1307 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1308 .fill_stats = mlx5e_grp_per_prio_fill_stats,
19386177 1309 .update_stats = mlx5e_grp_per_prio_update_stats,
4377bea2 1310 },
0e6f01a4
KH		 1311 {
1312 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1313 .fill_strings = mlx5e_grp_pme_fill_strings,
1314 .fill_stats = mlx5e_grp_pme_fill_stats,
1315 },
e185d43f
KH		 1316 {
1317 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1318 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1319 .fill_stats = mlx5e_grp_ipsec_fill_stats,
19386177 1320 .update_stats = mlx5e_grp_ipsec_update_stats,
e185d43f 1321 },
43585a41
IL		 1322 {
1323 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1324 .fill_strings = mlx5e_grp_tls_fill_strings,
1325 .fill_stats = mlx5e_grp_tls_fill_stats,
1326 },
1fe85006
KH		 1327 {
1328 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1329 .fill_strings = mlx5e_grp_channels_fill_strings,
1330 .fill_stats = mlx5e_grp_channels_fill_stats,
1331 }
c0752f2b
KH		 1332};
1333
1334const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);
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