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net/mlx5e: Re-order fields of struct mlx5e_xdpsq
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.c
CommitLineData
c0752f2b
KH		 1/*
2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
e185d43f 34#include "en_accel/ipsec.h"
43585a41 35#include "en_accel/tls.h"
c0752f2b
KH		 36
37static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
f24686e8 46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
2ad9ecdb 47 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) },
bf239741
IL		 48
49#ifdef CONFIG_MLX5_EN_TLS
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
51 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
52#endif
53
c0752f2b
KH		 54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
f24686e8 56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
c0752f2b
KH		 57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
86690b4b 62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) },
890388ad 63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) },
c0752f2b 64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
890388ad
TT		 65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
c0752f2b
KH		 67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
c0752f2b
KH		 71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
db75373c 73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
86155656 74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
f65a59ff 75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
bc5a7ccd 76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_udp_seg_rem) },
f65a59ff 77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
c0752f2b 78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
b71ba6b4
TT		 79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) },
c0752f2b
KH		 81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
dc983f0e 90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
a1bf74dc 91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
2d7103c8
TT		 92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
57d689a8 95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
c0752f2b
KH		 96};
97
98#define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
99
100static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
101{
102 return NUM_SW_COUNTERS;
103}
104
105static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
106{
107 int i;
108
109 for (i = 0; i < NUM_SW_COUNTERS; i++)
110 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
111 return idx;
112}
113
114static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
115{
116 int i;
117
118 for (i = 0; i < NUM_SW_COUNTERS; i++)
119 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
120 return idx;
121}
122
868a01a2 123void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
19386177
KH		 124{
125 struct mlx5e_sw_stats temp, *s = &temp;
05909bab 126 int i;
19386177
KH		 127
128 memset(s, 0, sizeof(*s));
19386177 129
05909bab
EBE		 130 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) {
131 struct mlx5e_channel_stats *channel_stats =
132 &priv->channel_stats[i];
890388ad 133 struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq;
05909bab
EBE		 134 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
135 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch;
136 int j;
19386177
KH		 137
138 s->rx_packets += rq_stats->packets;
139 s->rx_bytes += rq_stats->bytes;
140 s->rx_lro_packets += rq_stats->lro_packets;
141 s->rx_lro_bytes += rq_stats->lro_bytes;
142 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
143 s->rx_csum_none += rq_stats->csum_none;
144 s->rx_csum_complete += rq_stats->csum_complete;
145 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
146 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
890388ad 147 s->rx_xdp_drop += rq_stats->xdp_drop;
86690b4b 148 s->rx_xdp_redirect += rq_stats->xdp_redirect;
890388ad
TT		 149 s->rx_xdp_tx_xmit += xdpsq_stats->xmit;
150 s->rx_xdp_tx_full += xdpsq_stats->full;
151 s->rx_xdp_tx_err += xdpsq_stats->err;
152 s->rx_xdp_tx_cqe += xdpsq_stats->cqes;
19386177 153 s->rx_wqe_err += rq_stats->wqe_err;
b71ba6b4
TT		 154 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes;
155 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides;
19386177
KH		 156 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
157 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
158 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
159 s->rx_page_reuse += rq_stats->page_reuse;
160 s->rx_cache_reuse += rq_stats->cache_reuse;
161 s->rx_cache_full += rq_stats->cache_full;
162 s->rx_cache_empty += rq_stats->cache_empty;
163 s->rx_cache_busy += rq_stats->cache_busy;
164 s->rx_cache_waive += rq_stats->cache_waive;
dc983f0e 165 s->rx_congst_umr += rq_stats->congst_umr;
a1bf74dc 166 s->ch_events += ch_stats->events;
2d7103c8
TT		 167 s->ch_poll += ch_stats->poll;
168 s->ch_arm += ch_stats->arm;
169 s->ch_aff_change += ch_stats->aff_change;
890388ad 170 s->ch_eq_rearm += ch_stats->eq_rearm;
19386177 171
05909bab
EBE		 172 for (j = 0; j < priv->max_opened_tc; j++) {
173 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
19386177
KH		 174
175 s->tx_packets += sq_stats->packets;
176 s->tx_bytes += sq_stats->bytes;
177 s->tx_tso_packets += sq_stats->tso_packets;
178 s->tx_tso_bytes += sq_stats->tso_bytes;
179 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
180 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
181 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
2ad9ecdb 182 s->tx_nop += sq_stats->nop;
19386177
KH		 183 s->tx_queue_stopped += sq_stats->stopped;
184 s->tx_queue_wake += sq_stats->wake;
bc5a7ccd 185 s->tx_udp_seg_rem += sq_stats->udp_seg_rem;
19386177 186 s->tx_queue_dropped += sq_stats->dropped;
16cc14d8 187 s->tx_cqe_err += sq_stats->cqe_err;
db75373c 188 s->tx_recover += sq_stats->recover;
19386177
KH		 189 s->tx_xmit_more += sq_stats->xmit_more;
190 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
191 s->tx_csum_none += sq_stats->csum_none;
192 s->tx_csum_partial += sq_stats->csum_partial;
bf239741
IL		 193#ifdef CONFIG_MLX5_EN_TLS
194 s->tx_tls_ooo += sq_stats->tls_ooo;
195 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
196#endif
86155656 197 s->tx_cqes += sq_stats->cqes;
19386177
KH		 198 }
199 }
200
19386177
KH		 201 memcpy(&priv->stats.sw, s, sizeof(*s));
202}
203
fd8dcdb8
KH		 204static const struct counter_desc q_stats_desc[] = {
205 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
206};
207
7cbaf9a3
MS		 208static const struct counter_desc drop_rq_stats_desc[] = {
209 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
210};
211
fd8dcdb8 212#define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
7cbaf9a3 213#define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
fd8dcdb8
KH		 214
215static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
216{
7cbaf9a3
MS		 217 int num_stats = 0;
218
219 if (priv->q_counter)
220 num_stats += NUM_Q_COUNTERS;
221
222 if (priv->drop_rq_q_counter)
223 num_stats += NUM_DROP_RQ_COUNTERS;
224
225 return num_stats;
fd8dcdb8
KH		 226}
227
228static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
229{
230 int i;
231
232 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
7cbaf9a3
MS		 233 strcpy(data + (idx++) * ETH_GSTRING_LEN,
234 q_stats_desc[i].format);
235
236 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
237 strcpy(data + (idx++) * ETH_GSTRING_LEN,
238 drop_rq_stats_desc[i].format);
239
fd8dcdb8
KH		 240 return idx;
241}
242
243static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
244{
245 int i;
246
247 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
7cbaf9a3
MS		 248 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
249 q_stats_desc, i);
250 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
251 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
252 drop_rq_stats_desc, i);
fd8dcdb8
KH		 253 return idx;
254}
255
19386177
KH		 256static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
257{
258 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
259 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
19386177 260
7cbaf9a3
MS		 261 if (priv->q_counter &&
262 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
263 sizeof(out)))
264 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
265 out, out_of_buffer);
266 if (priv->drop_rq_q_counter &&
267 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
268 out, sizeof(out)))
269 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
270 out_of_buffer);
19386177
KH		 271}
272
5c298143
MS		 273#define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
274static const struct counter_desc vnic_env_stats_desc[] = {
275 { "rx_steer_missed_packets",
276 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
277};
278
279#define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
280
281static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
282{
283 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
284 NUM_VNIC_ENV_COUNTERS : 0;
285}
286
287static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
288 int idx)
289{
290 int i;
291
292 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
293 return idx;
294
295 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
296 strcpy(data + (idx++) * ETH_GSTRING_LEN,
297 vnic_env_stats_desc[i].format);
298 return idx;
299}
300
301static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
302 int idx)
303{
304 int i;
305
306 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
307 return idx;
308
309 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
310 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
311 vnic_env_stats_desc, i);
312 return idx;
313}
314
315static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
316{
317 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
318 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
319 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
320 struct mlx5_core_dev *mdev = priv->mdev;
321
322 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
323 return;
324
325 MLX5_SET(query_vnic_env_in, in, opcode,
326 MLX5_CMD_OP_QUERY_VNIC_ENV);
327 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
328 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
329 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
330}
331
40cab9f1
KH		 332#define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
333static const struct counter_desc vport_stats_desc[] = {
334 { "rx_vport_unicast_packets",
335 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
336 { "rx_vport_unicast_bytes",
337 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
338 { "tx_vport_unicast_packets",
339 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
340 { "tx_vport_unicast_bytes",
341 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
342 { "rx_vport_multicast_packets",
343 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
344 { "rx_vport_multicast_bytes",
345 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
346 { "tx_vport_multicast_packets",
347 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
348 { "tx_vport_multicast_bytes",
349 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
350 { "rx_vport_broadcast_packets",
351 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
352 { "rx_vport_broadcast_bytes",
353 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
354 { "tx_vport_broadcast_packets",
355 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
356 { "tx_vport_broadcast_bytes",
357 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
358 { "rx_vport_rdma_unicast_packets",
359 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
360 { "rx_vport_rdma_unicast_bytes",
361 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
362 { "tx_vport_rdma_unicast_packets",
363 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
364 { "tx_vport_rdma_unicast_bytes",
365 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
366 { "rx_vport_rdma_multicast_packets",
367 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
368 { "rx_vport_rdma_multicast_bytes",
369 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
370 { "tx_vport_rdma_multicast_packets",
371 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
372 { "tx_vport_rdma_multicast_bytes",
373 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
374};
375
376#define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
377
378static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
379{
380 return NUM_VPORT_COUNTERS;
381}
382
383static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
384 int idx)
385{
386 int i;
387
388 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
389 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
390 return idx;
391}
392
393static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
394 int idx)
395{
396 int i;
397
398 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
399 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
400 vport_stats_desc, i);
401 return idx;
402}
403
19386177
KH		 404static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
405{
406 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
407 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
408 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
409 struct mlx5_core_dev *mdev = priv->mdev;
410
411 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
412 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
413 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
414 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
415}
416
6e6ef814
KH		 417#define PPORT_802_3_OFF(c) \
418 MLX5_BYTE_OFF(ppcnt_reg, \
419 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
420static const struct counter_desc pport_802_3_stats_desc[] = {
421 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
422 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
423 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
424 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
425 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
426 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
427 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
428 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
429 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
430 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
431 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
432 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
433 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
434 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
435 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
436 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
437 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
438 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
439};
440
441#define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
442
443static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
444{
445 return NUM_PPORT_802_3_COUNTERS;
446}
447
448static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
449 int idx)
450{
451 int i;
452
453 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
454 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
455 return idx;
456}
457
458static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
459 int idx)
460{
461 int i;
462
463 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
464 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
465 pport_802_3_stats_desc, i);
466 return idx;
467}
468
19386177
KH		 469static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
470{
471 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
472 struct mlx5_core_dev *mdev = priv->mdev;
473 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
474 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
475 void *out;
476
477 MLX5_SET(ppcnt_reg, in, local_port, 1);
478 out = pstats->IEEE_802_3_counters;
479 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
480 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
481}
482
fc8e64a3
KH		 483#define PPORT_2863_OFF(c) \
484 MLX5_BYTE_OFF(ppcnt_reg, \
485 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
486static const struct counter_desc pport_2863_stats_desc[] = {
487 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
488 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
489 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
490};
491
492#define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
493
494static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
495{
496 return NUM_PPORT_2863_COUNTERS;
497}
498
499static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
500 int idx)
501{
502 int i;
503
504 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
505 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
506 return idx;
507}
508
509static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
510 int idx)
511{
512 int i;
513
514 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
515 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
516 pport_2863_stats_desc, i);
517 return idx;
518}
519
19386177
KH		 520static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
521{
522 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
523 struct mlx5_core_dev *mdev = priv->mdev;
524 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
525 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
526 void *out;
527
528 MLX5_SET(ppcnt_reg, in, local_port, 1);
529 out = pstats->RFC_2863_counters;
530 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
531 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
532}
533
e0e0def9
KH		 534#define PPORT_2819_OFF(c) \
535 MLX5_BYTE_OFF(ppcnt_reg, \
536 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
537static const struct counter_desc pport_2819_stats_desc[] = {
538 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
539 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
540 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
541 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
542 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
543 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
544 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
545 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
546 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
547 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
548 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
549 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
550 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
551};
552
553#define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
554
555static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
556{
557 return NUM_PPORT_2819_COUNTERS;
558}
559
560static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
561 int idx)
562{
563 int i;
564
565 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
566 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
567 return idx;
568}
569
570static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
571 int idx)
572{
573 int i;
574
575 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
576 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
577 pport_2819_stats_desc, i);
578 return idx;
579}
580
19386177
KH		 581static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
582{
583 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
584 struct mlx5_core_dev *mdev = priv->mdev;
585 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
586 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
587 void *out;
588
589 MLX5_SET(ppcnt_reg, in, local_port, 1);
590 out = pstats->RFC_2819_counters;
591 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
592 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593}
594
2e4df0b2
KH		 595#define PPORT_PHY_STATISTICAL_OFF(c) \
596 MLX5_BYTE_OFF(ppcnt_reg, \
597 counter_set.phys_layer_statistical_cntrs.c##_high)
598static const struct counter_desc pport_phy_statistical_stats_desc[] = {
599 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
600 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
601};
602
6ab75516 603#define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
2e4df0b2
KH		 604
605static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
606{
6ab75516 607 /* "1" for link_down_events special counter */
2e4df0b2 608 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
6ab75516 609 NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1;
2e4df0b2
KH		 610}
611
612static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
613 int idx)
614{
615 int i;
616
6ab75516
SM		 617 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
618
619 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
620 return idx;
621
622 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
623 strcpy(data + (idx++) * ETH_GSTRING_LEN,
624 pport_phy_statistical_stats_desc[i].format);
2e4df0b2
KH		 625 return idx;
626}
627
628static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
629{
630 int i;
631
6ab75516
SM		 632 /* link_down_events_phy has special handling since it is not stored in __be64 format */
633 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
634 counter_set.phys_layer_cntrs.link_down_events);
635
636 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
637 return idx;
638
639 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
640 data[idx++] =
641 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
642 pport_phy_statistical_stats_desc, i);
2e4df0b2
KH		 643 return idx;
644}
645
19386177
KH		 646static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
647{
648 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
649 struct mlx5_core_dev *mdev = priv->mdev;
650 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
651 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
652 void *out;
653
654 MLX5_SET(ppcnt_reg, in, local_port, 1);
655 out = pstats->phy_counters;
656 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
657 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
658
659 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
660 return;
661
662 out = pstats->phy_statistical_counters;
663 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
664 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
665}
666
3488bd4c
KH		 667#define PPORT_ETH_EXT_OFF(c) \
668 MLX5_BYTE_OFF(ppcnt_reg, \
669 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
670static const struct counter_desc pport_eth_ext_stats_desc[] = {
671 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
672};
673
674#define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
675
676static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
677{
678 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
679 return NUM_PPORT_ETH_EXT_COUNTERS;
680
681 return 0;
682}
683
684static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
685 int idx)
686{
687 int i;
688
689 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
690 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
691 strcpy(data + (idx++) * ETH_GSTRING_LEN,
692 pport_eth_ext_stats_desc[i].format);
693 return idx;
694}
695
696static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
697 int idx)
698{
699 int i;
700
701 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
702 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
703 data[idx++] =
704 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
705 pport_eth_ext_stats_desc, i);
706 return idx;
707}
708
19386177
KH		 709static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
710{
711 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
712 struct mlx5_core_dev *mdev = priv->mdev;
713 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
714 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
715 void *out;
716
717 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
718 return;
719
720 MLX5_SET(ppcnt_reg, in, local_port, 1);
721 out = pstats->eth_ext_counters;
722 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
723 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
724}
725
9fd2b5f1
KH		 726#define PCIE_PERF_OFF(c) \
727 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
728static const struct counter_desc pcie_perf_stats_desc[] = {
729 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
730 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
731};
732
733#define PCIE_PERF_OFF64(c) \
734 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
735static const struct counter_desc pcie_perf_stats_desc64[] = {
736 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
737};
738
739static const struct counter_desc pcie_perf_stall_stats_desc[] = {
740 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
741 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
742 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
743 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
744};
745
746#define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
747#define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
748#define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
749
750static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
751{
752 int num_stats = 0;
753
754 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
755 num_stats += NUM_PCIE_PERF_COUNTERS;
756
757 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
758 num_stats += NUM_PCIE_PERF_COUNTERS64;
759
760 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
761 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
762
763 return num_stats;
764}
765
766static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
767 int idx)
768{
769 int i;
770
771 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
772 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
773 strcpy(data + (idx++) * ETH_GSTRING_LEN,
774 pcie_perf_stats_desc[i].format);
775
776 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
777 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
778 strcpy(data + (idx++) * ETH_GSTRING_LEN,
779 pcie_perf_stats_desc64[i].format);
780
781 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
782 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
783 strcpy(data + (idx++) * ETH_GSTRING_LEN,
784 pcie_perf_stall_stats_desc[i].format);
785 return idx;
786}
787
788static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
789 int idx)
790{
791 int i;
792
793 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
794 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
795 data[idx++] =
796 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
797 pcie_perf_stats_desc, i);
798
799 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
800 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
801 data[idx++] =
802 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
803 pcie_perf_stats_desc64, i);
804
805 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
806 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
807 data[idx++] =
808 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
809 pcie_perf_stall_stats_desc, i);
810 return idx;
811}
812
19386177
KH		 813static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
814{
815 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
816 struct mlx5_core_dev *mdev = priv->mdev;
817 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
818 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
819 void *out;
820
821 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
822 return;
823
824 out = pcie_stats->pcie_perf_counters;
825 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
826 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
827}
828
4377bea2
KH		 829#define PPORT_PER_PRIO_OFF(c) \
830 MLX5_BYTE_OFF(ppcnt_reg, \
831 counter_set.eth_per_prio_grp_data_layout.c##_high)
e6000651
KH		 832static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
833 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
834 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
835 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
836 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
837};
838
839#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
840
841static int mlx5e_grp_per_prio_traffic_get_num_stats(struct mlx5e_priv *priv)
842{
843 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
844}
845
846static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
847 u8 *data,
848 int idx)
849{
850 int i, prio;
851
852 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
853 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
854 sprintf(data + (idx++) * ETH_GSTRING_LEN,
855 pport_per_prio_traffic_stats_desc[i].format, prio);
856 }
857
858 return idx;
859}
860
861static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
862 u64 *data,
863 int idx)
864{
865 int i, prio;
866
867 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
868 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
869 data[idx++] =
870 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
871 pport_per_prio_traffic_stats_desc, i);
872 }
873
874 return idx;
875}
876
4377bea2
KH		 877static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
878 /* %s is "global" or "prio{i}" */
879 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
880 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
881 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
882 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
883 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
884};
885
2fcb12df
IK		 886static const struct counter_desc pport_pfc_stall_stats_desc[] = {
887 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
888 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
889};
890
4377bea2 891#define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
2fcb12df
IK		 892#define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
893 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
894 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
4377bea2
KH		 895
896static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
897{
898 struct mlx5_core_dev *mdev = priv->mdev;
899 u8 pfc_en_tx;
900 u8 pfc_en_rx;
901 int err;
902
903 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
904 return 0;
905
906 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
907
908 return err ? 0 : pfc_en_tx | pfc_en_rx;
909}
910
911static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
912{
913 struct mlx5_core_dev *mdev = priv->mdev;
914 u32 rx_pause;
915 u32 tx_pause;
916 int err;
917
918 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
919 return false;
920
921 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
922
923 return err ? false : rx_pause | tx_pause;
924}
925
926static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
927{
928 return (mlx5e_query_global_pause_combined(priv) +
929 hweight8(mlx5e_query_pfc_combined(priv))) *
2fcb12df
IK		 930 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
931 NUM_PPORT_PFC_STALL_COUNTERS(priv);
4377bea2
KH		 932}
933
934static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
935 u8 *data,
936 int idx)
937{
938 unsigned long pfc_combined;
939 int i, prio;
940
941 pfc_combined = mlx5e_query_pfc_combined(priv);
942 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
943 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
944 char pfc_string[ETH_GSTRING_LEN];
945
946 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
947 sprintf(data + (idx++) * ETH_GSTRING_LEN,
948 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
949 }
950 }
951
952 if (mlx5e_query_global_pause_combined(priv)) {
953 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
954 sprintf(data + (idx++) * ETH_GSTRING_LEN,
955 pport_per_prio_pfc_stats_desc[i].format, "global");
956 }
957 }
958
2fcb12df
IK		 959 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
960 strcpy(data + (idx++) * ETH_GSTRING_LEN,
961 pport_pfc_stall_stats_desc[i].format);
962
4377bea2
KH		 963 return idx;
964}
965
966static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
967 u64 *data,
968 int idx)
969{
970 unsigned long pfc_combined;
971 int i, prio;
972
973 pfc_combined = mlx5e_query_pfc_combined(priv);
974 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
975 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
976 data[idx++] =
977 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
978 pport_per_prio_pfc_stats_desc, i);
979 }
980 }
981
982 if (mlx5e_query_global_pause_combined(priv)) {
983 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
984 data[idx++] =
985 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
986 pport_per_prio_pfc_stats_desc, i);
987 }
988 }
989
2fcb12df
IK		 990 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
991 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
992 pport_pfc_stall_stats_desc, i);
993
4377bea2
KH		 994 return idx;
995}
996
a8984281
KH		 997static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
998{
999 return mlx5e_grp_per_prio_traffic_get_num_stats(priv) +
1000 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
1001}
1002
1003static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
1004 int idx)
1005{
1006 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
1007 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
1008 return idx;
1009}
1010
1011static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
1012 int idx)
1013{
1014 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1015 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1016 return idx;
1017}
1018
19386177
KH		 1019static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
1020{
1021 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1022 struct mlx5_core_dev *mdev = priv->mdev;
1023 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1024 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1025 int prio;
1026 void *out;
1027
1028 MLX5_SET(ppcnt_reg, in, local_port, 1);
1029 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1030 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1031 out = pstats->per_prio_counters[prio];
1032 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1033 mlx5_core_access_reg(mdev, in, sz, out, sz,
1034 MLX5_REG_PPCNT, 0, 0);
1035 }
1036}
1037
0e6f01a4
KH		 1038static const struct counter_desc mlx5e_pme_status_desc[] = {
1039 { "module_unplug", 8 },
1040};
1041
1042static const struct counter_desc mlx5e_pme_error_desc[] = {
1043 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1044 { "module_high_temp", 48 }, /* high temperature */
1045 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1046};
1047
1048#define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1049#define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1050
1051static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1052{
1053 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1054}
1055
1056static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1057 int idx)
1058{
1059 int i;
1060
1061 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1062 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1063
1064 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1065 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1066
1067 return idx;
1068}
1069
1070static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1071 int idx)
1072{
1073 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1074 int i;
1075
1076 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1077 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1078 mlx5e_pme_status_desc, i);
1079
1080 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1081 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1082 mlx5e_pme_error_desc, i);
1083
1084 return idx;
1085}
1086
e185d43f
KH		 1087static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1088{
1089 return mlx5e_ipsec_get_count(priv);
1090}
1091
1092static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1093 int idx)
1094{
1095 return idx + mlx5e_ipsec_get_strings(priv,
1096 data + idx * ETH_GSTRING_LEN);
1097}
1098
1099static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1100 int idx)
1101{
1102 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1103}
1104
19386177
KH		 1105static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1106{
1107 mlx5e_ipsec_update_stats(priv);
1108}
1109
43585a41
IL		 1110static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1111{
1112 return mlx5e_tls_get_count(priv);
1113}
1114
1115static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1116 int idx)
1117{
1118 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1119}
1120
1121static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1122{
1123 return idx + mlx5e_tls_get_stats(priv, data + idx);
1124}
1125
1fe85006
KH		 1126static const struct counter_desc rq_stats_desc[] = {
1127 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1128 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1129 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1130 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1131 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1132 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1133 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
86690b4b 1134 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) },
1fe85006
KH		 1135 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1136 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
f24686e8 1137 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1fe85006 1138 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
b71ba6b4
TT		 1139 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
1140 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
1fe85006
KH		 1141 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1142 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1143 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1144 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1145 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1146 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1147 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1148 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1149 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
dc983f0e 1150 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
1fe85006
KH		 1151};
1152
1153static const struct counter_desc sq_stats_desc[] = {
1154 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1155 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1156 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1157 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1158 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1159 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1160 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1161 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
f24686e8 1162 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1fe85006
KH		 1163 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1164 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1165 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1fe85006
KH		 1166 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1167 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
db75373c 1168 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
86155656 1169 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
f65a59ff
TT		 1170 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1171 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1fe85006
KH		 1172};
1173
890388ad
TT		 1174static const struct counter_desc rq_xdpsq_stats_desc[] = {
1175 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1176 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1177 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1178 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1179};
1180
57d689a8 1181static const struct counter_desc ch_stats_desc[] = {
a1bf74dc 1182 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
2d7103c8
TT		 1183 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
1184 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
1185 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
57d689a8
EBE		 1186 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1187};
1188
1fe85006
KH		 1189#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1190#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
890388ad 1191#define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc)
57d689a8 1192#define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1fe85006
KH		 1193
1194static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1195{
05909bab
EBE		 1196 int max_nch = priv->profile->max_nch(priv->mdev);
1197
05909bab
EBE		 1198 return (NUM_RQ_STATS * max_nch) +
1199 (NUM_CH_STATS * max_nch) +
890388ad
TT		 1200 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) +
1201 (NUM_RQ_XDPSQ_STATS * max_nch);
1fe85006
KH		 1202}
1203
1204static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1205 int idx)
1206{
05909bab 1207 int max_nch = priv->profile->max_nch(priv->mdev);
1fe85006
KH		 1208 int i, j, tc;
1209
05909bab 1210 for (i = 0; i < max_nch; i++)
57d689a8
EBE		 1211 for (j = 0; j < NUM_CH_STATS; j++)
1212 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1213 ch_stats_desc[j].format, i);
1214
890388ad 1215 for (i = 0; i < max_nch; i++) {
1fe85006 1216 for (j = 0; j < NUM_RQ_STATS; j++)
890388ad
TT		 1217 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1218 rq_stats_desc[j].format, i);
1219 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1220 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1221 rq_xdpsq_stats_desc[j].format, i);
1222 }
1fe85006 1223
05909bab
EBE		 1224 for (tc = 0; tc < priv->max_opened_tc; tc++)
1225 for (i = 0; i < max_nch; i++)
1fe85006
KH		 1226 for (j = 0; j < NUM_SQ_STATS; j++)
1227 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1228 sq_stats_desc[j].format,
1229 priv->channel_tc2txq[i][tc]);
1230
1231 return idx;
1232}
1233
1234static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1235 int idx)
1236{
05909bab 1237 int max_nch = priv->profile->max_nch(priv->mdev);
1fe85006
KH		 1238 int i, j, tc;
1239
05909bab 1240 for (i = 0; i < max_nch; i++)
57d689a8
EBE		 1241 for (j = 0; j < NUM_CH_STATS; j++)
1242 data[idx++] =
05909bab 1243 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch,
57d689a8
EBE		 1244 ch_stats_desc, j);
1245
890388ad 1246 for (i = 0; i < max_nch; i++) {
1fe85006
KH		 1247 for (j = 0; j < NUM_RQ_STATS; j++)
1248 data[idx++] =
05909bab 1249 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq,
1fe85006 1250 rq_stats_desc, j);
890388ad
TT		 1251 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1252 data[idx++] =
1253 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq,
1254 rq_xdpsq_stats_desc, j);
1255 }
1fe85006 1256
05909bab
EBE		 1257 for (tc = 0; tc < priv->max_opened_tc; tc++)
1258 for (i = 0; i < max_nch; i++)
1fe85006
KH		 1259 for (j = 0; j < NUM_SQ_STATS; j++)
1260 data[idx++] =
05909bab 1261 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc],
1fe85006
KH		 1262 sq_stats_desc, j);
1263
1264 return idx;
1265}
1266
19386177 1267/* The stats groups order is opposite to the update_stats() order calls */
c0752f2b
KH		 1268const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1269 {
1270 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1271 .fill_strings = mlx5e_grp_sw_fill_strings,
1272 .fill_stats = mlx5e_grp_sw_fill_stats,
19386177 1273 .update_stats = mlx5e_grp_sw_update_stats,
fd8dcdb8
KH		 1274 },
1275 {
1276 .get_num_stats = mlx5e_grp_q_get_num_stats,
1277 .fill_strings = mlx5e_grp_q_fill_strings,
1278 .fill_stats = mlx5e_grp_q_fill_stats,
19386177
KH		 1279 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1280 .update_stats = mlx5e_grp_q_update_stats,
fd8dcdb8 1281 },
5c298143
MS		 1282 {
1283 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1284 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1285 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1286 .update_stats = mlx5e_grp_vnic_env_update_stats,
1287 },
40cab9f1
KH		 1288 {
1289 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1290 .fill_strings = mlx5e_grp_vport_fill_strings,
1291 .fill_stats = mlx5e_grp_vport_fill_stats,
19386177
KH		 1292 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1293 .update_stats = mlx5e_grp_vport_update_stats,
40cab9f1 1294 },
6e6ef814
KH		 1295 {
1296 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1297 .fill_strings = mlx5e_grp_802_3_fill_strings,
1298 .fill_stats = mlx5e_grp_802_3_fill_stats,
19386177
KH		 1299 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1300 .update_stats = mlx5e_grp_802_3_update_stats,
6e6ef814 1301 },
fc8e64a3
KH		 1302 {
1303 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1304 .fill_strings = mlx5e_grp_2863_fill_strings,
1305 .fill_stats = mlx5e_grp_2863_fill_stats,
19386177 1306 .update_stats = mlx5e_grp_2863_update_stats,
fc8e64a3 1307 },
e0e0def9
KH		 1308 {
1309 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1310 .fill_strings = mlx5e_grp_2819_fill_strings,
1311 .fill_stats = mlx5e_grp_2819_fill_stats,
19386177 1312 .update_stats = mlx5e_grp_2819_update_stats,
e0e0def9 1313 },
2e4df0b2
KH		 1314 {
1315 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1316 .fill_strings = mlx5e_grp_phy_fill_strings,
1317 .fill_stats = mlx5e_grp_phy_fill_stats,
19386177 1318 .update_stats = mlx5e_grp_phy_update_stats,
2e4df0b2 1319 },
3488bd4c
KH		 1320 {
1321 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1322 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1323 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
19386177 1324 .update_stats = mlx5e_grp_eth_ext_update_stats,
9fd2b5f1
KH		 1325 },
1326 {
1327 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1328 .fill_strings = mlx5e_grp_pcie_fill_strings,
1329 .fill_stats = mlx5e_grp_pcie_fill_stats,
19386177 1330 .update_stats = mlx5e_grp_pcie_update_stats,
9fd2b5f1 1331 },
e6000651 1332 {
a8984281
KH		 1333 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1334 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1335 .fill_stats = mlx5e_grp_per_prio_fill_stats,
19386177 1336 .update_stats = mlx5e_grp_per_prio_update_stats,
4377bea2 1337 },
0e6f01a4
KH		 1338 {
1339 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1340 .fill_strings = mlx5e_grp_pme_fill_strings,
1341 .fill_stats = mlx5e_grp_pme_fill_stats,
1342 },
e185d43f
KH		 1343 {
1344 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1345 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1346 .fill_stats = mlx5e_grp_ipsec_fill_stats,
19386177 1347 .update_stats = mlx5e_grp_ipsec_update_stats,
e185d43f 1348 },
43585a41
IL		 1349 {
1350 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1351 .fill_strings = mlx5e_grp_tls_fill_strings,
1352 .fill_stats = mlx5e_grp_tls_fill_stats,
1353 },
1fe85006
KH		 1354 {
1355 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1356 .fill_strings = mlx5e_grp_channels_fill_strings,
1357 .fill_stats = mlx5e_grp_channels_fill_stats,
1358 }
c0752f2b
KH		 1359};
1360
1361const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);
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