]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5e: CQE compression
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.h
CommitLineData
9218b44d
GP		 1/*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#ifndef __MLX5_EN_STATS_H__
33#define __MLX5_EN_STATS_H__
34
35#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be64_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
43
44#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
45
46struct counter_desc {
47 char name[ETH_GSTRING_LEN];
48 int offset; /* Byte offset */
49};
50
51struct mlx5e_sw_stats {
52 u64 rx_packets;
53 u64 rx_bytes;
54 u64 tx_packets;
55 u64 tx_bytes;
56 u64 tso_packets;
57 u64 tso_bytes;
58 u64 tso_inner_packets;
59 u64 tso_inner_bytes;
60 u64 lro_packets;
61 u64 lro_bytes;
62 u64 rx_csum_good;
63 u64 rx_csum_none;
64 u64 rx_csum_sw;
1b223dd3 65 u64 rx_csum_inner;
9218b44d
GP		 66 u64 tx_csum_offload;
67 u64 tx_csum_inner;
68 u64 tx_queue_stopped;
69 u64 tx_queue_wake;
70 u64 tx_queue_dropped;
71 u64 rx_wqe_err;
72 u64 rx_mpwqe_filler;
73 u64 rx_mpwqe_frag;
74 u64 rx_buff_alloc_err;
7219ab34
TT		 75 u64 rx_cqe_compress_blks;
76 u64 rx_cqe_compress_pkts;
121fcdc8
GP		 77
78 /* Special handling counters */
79 u64 link_down_events;
9218b44d
GP		 80};
81
82static const struct counter_desc sw_stats_desc[] = {
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tso_packets) },
88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tso_bytes) },
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tso_inner_packets) },
90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tso_inner_bytes) },
91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, lro_packets) },
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, lro_bytes) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_good) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_sw) },
1b223dd3 96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_inner) },
9218b44d
GP		 97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_offload) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_inner) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_frag) },
105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
7219ab34
TT		 106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
121fcdc8 108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events) },
9218b44d
GP		 109};
110
111struct mlx5e_qcounter_stats {
112 u32 rx_out_of_buffer;
113};
114
115static const struct counter_desc q_stats_desc[] = {
116 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
117};
118
119#define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
120#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
121 vstats->query_vport_out, c)
122
123struct mlx5e_vport_stats {
124 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
125};
126
127static const struct counter_desc vport_stats_desc[] = {
8075cb72
GP		 128 { "rx_vport_error_packets",
129 VPORT_COUNTER_OFF(received_errors.packets) },
130 { "rx_vport_error_bytes", VPORT_COUNTER_OFF(received_errors.octets) },
131 { "tx_vport_error_packets",
132 VPORT_COUNTER_OFF(transmit_errors.packets) },
133 { "tx_vport_error_bytes", VPORT_COUNTER_OFF(transmit_errors.octets) },
134 { "rx_vport_unicast_packets",
9218b44d 135 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
8075cb72
GP		 136 { "rx_vport_unicast_bytes",
137 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
138 { "tx_vport_unicast_packets",
9218b44d 139 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
8075cb72 140 { "tx_vport_unicast_bytes",
9218b44d 141 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
8075cb72 142 { "rx_vport_multicast_packets",
9218b44d 143 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
8075cb72 144 { "rx_vport_multicast_bytes",
9218b44d 145 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
8075cb72 146 { "tx_vport_multicast_packets",
9218b44d 147 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
8075cb72 148 { "tx_vport_multicast_bytes",
9218b44d 149 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
8075cb72 150 { "rx_vport_broadcast_packets",
9218b44d 151 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
8075cb72 152 { "rx_vport_broadcast_bytes",
9218b44d 153 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
8075cb72 154 { "tx_vport_broadcast_packets",
9218b44d 155 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
8075cb72 156 { "tx_vport_broadcast_bytes",
9218b44d
GP		 157 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
158};
159
160#define PPORT_802_3_OFF(c) \
161 MLX5_BYTE_OFF(ppcnt_reg, \
162 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
163#define PPORT_802_3_GET(pstats, c) \
164 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
165 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
166#define PPORT_2863_OFF(c) \
167 MLX5_BYTE_OFF(ppcnt_reg, \
168 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
169#define PPORT_2863_GET(pstats, c) \
170 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
171 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
172#define PPORT_2819_OFF(c) \
173 MLX5_BYTE_OFF(ppcnt_reg, \
174 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
175#define PPORT_2819_GET(pstats, c) \
176 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
177 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
cf678570
GP		 178#define PPORT_PER_PRIO_OFF(c) \
179 MLX5_BYTE_OFF(ppcnt_reg, \
180 counter_set.eth_per_prio_grp_data_layout.c##_high)
181#define PPORT_PER_PRIO_GET(pstats, prio, c) \
182 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
183 counter_set.eth_per_prio_grp_data_layout.c##_high)
184#define NUM_PPORT_PRIO 8
9218b44d
GP		 185
186struct mlx5e_pport_stats {
187 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
188 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
189 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
cf678570 190 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
121fcdc8 191 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
9218b44d
GP		 192};
193
194static const struct counter_desc pport_802_3_stats_desc[] = {
195 { "frames_tx", PPORT_802_3_OFF(a_frames_transmitted_ok) },
196 { "frames_rx", PPORT_802_3_OFF(a_frames_received_ok) },
197 { "check_seq_err", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
198 { "alignment_err", PPORT_802_3_OFF(a_alignment_errors) },
199 { "octets_tx", PPORT_802_3_OFF(a_octets_transmitted_ok) },
200 { "octets_received", PPORT_802_3_OFF(a_octets_received_ok) },
201 { "multicast_xmitted", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
202 { "broadcast_xmitted", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
203 { "multicast_rx", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
204 { "broadcast_rx", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
205 { "in_range_len_errors", PPORT_802_3_OFF(a_in_range_length_errors) },
206 { "out_of_range_len", PPORT_802_3_OFF(a_out_of_range_length_field) },
207 { "too_long_errors", PPORT_802_3_OFF(a_frame_too_long_errors) },
208 { "symbol_err", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
209 { "mac_control_tx", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
210 { "mac_control_rx", PPORT_802_3_OFF(a_mac_control_frames_received) },
211 { "unsupported_op_rx",
212 PPORT_802_3_OFF(a_unsupported_opcodes_received) },
213 { "pause_ctrl_rx", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
214 { "pause_ctrl_tx",
215 PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
216};
217
218static const struct counter_desc pport_2863_stats_desc[] = {
219 { "in_octets", PPORT_2863_OFF(if_in_octets) },
220 { "in_ucast_pkts", PPORT_2863_OFF(if_in_ucast_pkts) },
221 { "in_discards", PPORT_2863_OFF(if_in_discards) },
222 { "in_errors", PPORT_2863_OFF(if_in_errors) },
223 { "in_unknown_protos", PPORT_2863_OFF(if_in_unknown_protos) },
224 { "out_octets", PPORT_2863_OFF(if_out_octets) },
225 { "out_ucast_pkts", PPORT_2863_OFF(if_out_ucast_pkts) },
226 { "out_discards", PPORT_2863_OFF(if_out_discards) },
227 { "out_errors", PPORT_2863_OFF(if_out_errors) },
228 { "in_multicast_pkts", PPORT_2863_OFF(if_in_multicast_pkts) },
229 { "in_broadcast_pkts", PPORT_2863_OFF(if_in_broadcast_pkts) },
230 { "out_multicast_pkts", PPORT_2863_OFF(if_out_multicast_pkts) },
231 { "out_broadcast_pkts", PPORT_2863_OFF(if_out_broadcast_pkts) },
232};
233
234static const struct counter_desc pport_2819_stats_desc[] = {
235 { "drop_events", PPORT_2819_OFF(ether_stats_drop_events) },
236 { "octets", PPORT_2819_OFF(ether_stats_octets) },
237 { "pkts", PPORT_2819_OFF(ether_stats_pkts) },
238 { "broadcast_pkts", PPORT_2819_OFF(ether_stats_broadcast_pkts) },
239 { "multicast_pkts", PPORT_2819_OFF(ether_stats_multicast_pkts) },
240 { "crc_align_errors", PPORT_2819_OFF(ether_stats_crc_align_errors) },
241 { "undersize_pkts", PPORT_2819_OFF(ether_stats_undersize_pkts) },
242 { "oversize_pkts", PPORT_2819_OFF(ether_stats_oversize_pkts) },
243 { "fragments", PPORT_2819_OFF(ether_stats_fragments) },
244 { "jabbers", PPORT_2819_OFF(ether_stats_jabbers) },
245 { "collisions", PPORT_2819_OFF(ether_stats_collisions) },
246 { "p64octets", PPORT_2819_OFF(ether_stats_pkts64octets) },
247 { "p65to127octets", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
248 { "p128to255octets", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
249 { "p256to511octets", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
250 { "p512to1023octets", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
251 { "p1024to1518octets",
252 PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
253 { "p1519to2047octets",
254 PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
255 { "p2048to4095octets",
256 PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
257 { "p4096to8191octets",
258 PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
259 { "p8192to10239octets",
260 PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
261};
262
cf678570
GP		 263static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
264 { "rx_octets", PPORT_PER_PRIO_OFF(rx_octets) },
265 { "rx_frames", PPORT_PER_PRIO_OFF(rx_frames) },
266 { "tx_octets", PPORT_PER_PRIO_OFF(tx_octets) },
267 { "tx_frames", PPORT_PER_PRIO_OFF(tx_frames) },
268};
269
270static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
271 { "rx_pause", PPORT_PER_PRIO_OFF(rx_pause) },
272 { "rx_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
273 { "tx_pause", PPORT_PER_PRIO_OFF(tx_pause) },
274 { "tx_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
275 { "rx_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
276};
277
9218b44d
GP		 278struct mlx5e_rq_stats {
279 u64 packets;
280 u64 bytes;
9218b44d 281 u64 csum_sw;
1b223dd3
SM		 282 u64 csum_inner;
283 u64 csum_none;
9218b44d
GP		 284 u64 lro_packets;
285 u64 lro_bytes;
286 u64 wqe_err;
287 u64 mpwqe_filler;
288 u64 mpwqe_frag;
289 u64 buff_alloc_err;
7219ab34
TT		 290 u64 cqe_compress_blks;
291 u64 cqe_compress_pkts;
9218b44d
GP		 292};
293
294static const struct counter_desc rq_stats_desc[] = {
295 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, packets) },
296 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, bytes) },
9218b44d 297 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, csum_sw) },
1b223dd3
SM		 298 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, csum_inner) },
299 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, csum_none) },
9218b44d
GP		 300 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, lro_packets) },
301 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, lro_bytes) },
302 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, wqe_err) },
303 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
304 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, mpwqe_frag) },
305 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
7219ab34
TT		 306 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
307 { MLX5E_DECLARE_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
9218b44d
GP		 308};
309
310struct mlx5e_sq_stats {
311 /* commonly accessed in data path */
312 u64 packets;
313 u64 bytes;
314 u64 tso_packets;
315 u64 tso_bytes;
316 u64 tso_inner_packets;
317 u64 tso_inner_bytes;
318 u64 csum_offload_inner;
319 u64 nop;
320 /* less likely accessed in data path */
321 u64 csum_offload_none;
322 u64 stopped;
323 u64 wake;
324 u64 dropped;
325};
326
327static const struct counter_desc sq_stats_desc[] = {
328 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, packets) },
329 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, bytes) },
330 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, tso_packets) },
331 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, tso_bytes) },
332 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
333 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
334 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, csum_offload_inner) },
335 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, nop) },
336 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, csum_offload_none) },
337 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, stopped) },
338 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, wake) },
339 { MLX5E_DECLARE_STAT(struct mlx5e_sq_stats, dropped) },
340};
341
342#define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
343#define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
344#define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
345#define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
346#define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
347#define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
cf678570
GP		 348#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \
349 ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
350#define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
351 ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
9218b44d
GP		 352#define NUM_PPORT_COUNTERS (NUM_PPORT_802_3_COUNTERS + \
353 NUM_PPORT_2863_COUNTERS + \
cf678570
GP		 354 NUM_PPORT_2819_COUNTERS + \
355 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \
356 NUM_PPORT_PRIO)
9218b44d
GP		 357#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
358#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
359
360struct mlx5e_stats {
361 struct mlx5e_sw_stats sw;
362 struct mlx5e_qcounter_stats qcnt;
363 struct mlx5e_vport_stats vport;
364 struct mlx5e_pport_stats pport;
365};
366
367#endif /* __MLX5_EN_STATS_H__ */
Ubuntu Artful kernel mirror