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net/mlx5: E-Switch, Get reg_c0 value on CQE
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
db76ca24 42#include <linux/completion.h>
03a9d11e 43#include <net/tc_act/tc_mirred.h>
776b12b6 44#include <net/tc_act/tc_vlan.h>
bbd00f7e 45#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 46#include <net/tc_act/tc_pedit.h>
26c02749 47#include <net/tc_act/tc_csum.h>
f6dfb4c3 48#include <net/arp.h>
3616d08b 49#include <net/ipv6_stubs.h>
e8f887ac 50#include "en.h"
1d447a39 51#include "en_rep.h"
232c0013 52#include "en_tc.h"
03a9d11e 53#include "eswitch.h"
39ac237c 54#include "eswitch_offloads_chains.h"
3f6d08d1 55#include "fs_core.h"
2c81bfd5 56#include "en/port.h"
101f4de9 57#include "en/tc_tun.h"
04de7dda 58#include "lib/devcom.h"
9272e3df 59#include "lib/geneve.h"
7a978759 60#include "diag/en_tc_tracepoint.h"
e8f887ac 61
3bc4b7bf
OG		 62struct mlx5_nic_flow_attr {
63 u32 action;
64 u32 flow_tag;
2b688ea5 65 struct mlx5_modify_hdr *modify_hdr;
5c65c564 66 u32 hairpin_tirn;
38aa51c1 67 u8 match_level;
3f6d08d1 68 struct mlx5_flow_table *hairpin_ft;
b8aee822 69 struct mlx5_fc *counter;
3bc4b7bf
OG		 70};
71
226f2ca3 72#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 73
65ba8fb7 74enum {
226f2ca3
VB		 75 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
76 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
77 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 78 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 79 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
80 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
81 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
82 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
83 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
84 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
85 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 86 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
65ba8fb7
OG		 87};
88
e4ad91f2
CM		 89#define MLX5E_TC_MAX_SPLITS 1
90
79baaec7
EB		 91/* Helper struct for accessing a struct containing list_head array.
92 * Containing struct
93 * |- Helper array
94 * [0] Helper item 0
95 * |- list_head item 0
96 * |- index (0)
97 * [1] Helper item 1
98 * |- list_head item 1
99 * |- index (1)
100 * To access the containing struct from one of the list_head items:
101 * 1. Get the helper item from the list_head item using
102 * helper item =
103 * container_of(list_head item, helper struct type, list_head field)
104 * 2. Get the contining struct from the helper item and its index in the array:
105 * containing struct =
106 * container_of(helper item, containing struct type, helper field[index])
107 */
108struct encap_flow_item {
948993f2 109 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 110 struct list_head list;
111 int index;
112};
113
e8f887ac
AV		 114struct mlx5e_tc_flow {
115 struct rhash_head node;
655dc3d2 116 struct mlx5e_priv *priv;
e8f887ac 117 u64 cookie;
226f2ca3 118 unsigned long flags;
e4ad91f2 119 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 120 /* Flow can be associated with multiple encap IDs.
121 * The number of encaps is bounded by the number of supported
122 * destinations.
123 */
124 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 125 struct mlx5e_tc_flow *peer_flow;
dd58edc3 126 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 127 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 128 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 129 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 130 struct list_head peer; /* flows with peer flow */
b4a23329 131 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
2a1f1768 132 int tmp_efi_index;
6a06c2f7 133 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 134 refcount_t refcnt;
c5d326b2 135 struct rcu_head rcu_head;
95435ad7 136 struct completion init_done;
3bc4b7bf
OG		 137 union {
138 struct mlx5_esw_flow_attr esw_attr[0];
139 struct mlx5_nic_flow_attr nic_attr[0];
140 };
e8f887ac
AV		 141};
142
17091853 143struct mlx5e_tc_flow_parse_attr {
1f6da306 144 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 145 struct net_device *filter_dev;
17091853 146 struct mlx5_flow_spec spec;
d79b6df6 147 int num_mod_hdr_actions;
218d05ce 148 int max_mod_hdr_actions;
d79b6df6 149 void *mod_hdr_actions;
98b66cb1 150 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 151};
152
acff797c 153#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 154#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 155
77ab67b7
OG		 156struct mlx5e_hairpin {
157 struct mlx5_hairpin *pair;
158
159 struct mlx5_core_dev *func_mdev;
3f6d08d1 160 struct mlx5e_priv *func_priv;
77ab67b7
OG		 161 u32 tdn;
162 u32 tirn;
3f6d08d1
OG		 163
164 int num_channels;
165 struct mlx5e_rqt indir_rqt;
166 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
167 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 168};
169
5c65c564
OG		 170struct mlx5e_hairpin_entry {
171 /* a node of a hash table which keeps all the hairpin entries */
172 struct hlist_node hairpin_hlist;
173
73edca73
VB		 174 /* protects flows list */
175 spinlock_t flows_lock;
5c65c564
OG		 176 /* flows sharing the same hairpin */
177 struct list_head flows;
db76ca24
VB		 178 /* hpe's that were not fully initialized when dead peer update event
179 * function traversed them.
180 */
181 struct list_head dead_peer_wait_list;
5c65c564 182
d8822868 183 u16 peer_vhca_id;
106be53b 184 u8 prio;
5c65c564 185 struct mlx5e_hairpin *hp;
e4f9abbd 186 refcount_t refcnt;
db76ca24 187 struct completion res_ready;
5c65c564
OG		 188};
189
11c9c548
OG		 190struct mod_hdr_key {
191 int num_actions;
192 void *actions;
193};
194
195struct mlx5e_mod_hdr_entry {
196 /* a node of a hash table which keeps all the mod_hdr entries */
197 struct hlist_node mod_hdr_hlist;
198
83a52f0d
VB		 199 /* protects flows list */
200 spinlock_t flows_lock;
11c9c548
OG		 201 /* flows sharing the same mod_hdr entry */
202 struct list_head flows;
203
204 struct mod_hdr_key key;
205
2b688ea5 206 struct mlx5_modify_hdr *modify_hdr;
dd58edc3
VB		 207
208 refcount_t refcnt;
a734d007
VB		 209 struct completion res_ready;
210 int compl_result;
11c9c548
OG		 211};
212
213#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
214
5a7e5bcb
VB		 215static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
216 struct mlx5e_tc_flow *flow);
217
218static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
219{
220 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
221 return ERR_PTR(-EINVAL);
222 return flow;
223}
224
225static void mlx5e_flow_put(struct mlx5e_priv *priv,
226 struct mlx5e_tc_flow *flow)
227{
228 if (refcount_dec_and_test(&flow->refcnt)) {
229 mlx5e_tc_del_flow(priv, flow);
c5d326b2 230 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 231 }
232}
233
226f2ca3
VB		 234static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
235{
236 /* Complete all memory stores before setting bit. */
237 smp_mb__before_atomic();
238 set_bit(flag, &flow->flags);
239}
240
241#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
242
c5d326b2
VB		 243static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
244 unsigned long flag)
245{
246 /* test_and_set_bit() provides all necessary barriers */
247 return test_and_set_bit(flag, &flow->flags);
248}
249
250#define flow_flag_test_and_set(flow, flag) \
251 __flow_flag_test_and_set(flow, \
252 MLX5E_TC_FLOW_FLAG_##flag)
253
226f2ca3
VB		 254static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
255{
256 /* Complete all memory stores before clearing bit. */
257 smp_mb__before_atomic();
258 clear_bit(flag, &flow->flags);
259}
260
261#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
262 MLX5E_TC_FLOW_FLAG_##flag)
263
264static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
265{
266 bool ret = test_bit(flag, &flow->flags);
267
268 /* Read fields of flow structure only after checking flags. */
269 smp_mb__after_atomic();
270 return ret;
271}
272
273#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
274 MLX5E_TC_FLOW_FLAG_##flag)
275
276static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
277{
278 return flow_flag_test(flow, ESWITCH);
279}
280
84179981
PB		 281static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
282{
283 return flow_flag_test(flow, FT);
284}
285
226f2ca3
VB		 286static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
287{
288 return flow_flag_test(flow, OFFLOADED);
289}
290
11c9c548
OG		 291static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
292{
293 return jhash(key->actions,
294 key->num_actions * MLX5_MH_ACT_SZ, 0);
295}
296
297static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
298 struct mod_hdr_key *b)
299{
300 if (a->num_actions != b->num_actions)
301 return 1;
302
303 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
304}
305
dd58edc3
VB		 306static struct mod_hdr_tbl *
307get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
308{
309 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
310
311 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
312 &priv->fs.tc.mod_hdr;
313}
314
315static struct mlx5e_mod_hdr_entry *
316mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
317{
318 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
319
320 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
321 if (!cmp_mod_hdr_info(&mh->key, key)) {
322 refcount_inc(&mh->refcnt);
323 found = mh;
324 break;
325 }
326 }
327
328 return found;
329}
330
331static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
d2faae25
VB		 332 struct mlx5e_mod_hdr_entry *mh,
333 int namespace)
dd58edc3 334{
d2faae25
VB		 335 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
336
337 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
dd58edc3 338 return;
d2faae25
VB		 339 hash_del(&mh->mod_hdr_hlist);
340 mutex_unlock(&tbl->lock);
dd58edc3
VB		 341
342 WARN_ON(!list_empty(&mh->flows));
a734d007 343 if (mh->compl_result > 0)
2b688ea5 344 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
d2faae25 345
dd58edc3
VB		 346 kfree(mh);
347}
348
d2faae25
VB		 349static int get_flow_name_space(struct mlx5e_tc_flow *flow)
350{
351 return mlx5e_is_eswitch_flow(flow) ?
352 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
353}
11c9c548
OG		 354static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
355 struct mlx5e_tc_flow *flow,
356 struct mlx5e_tc_flow_parse_attr *parse_attr)
357{
11c9c548
OG		 358 int num_actions, actions_size, namespace, err;
359 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 360 struct mod_hdr_tbl *tbl;
11c9c548 361 struct mod_hdr_key key;
11c9c548
OG		 362 u32 hash_key;
363
364 num_actions = parse_attr->num_mod_hdr_actions;
365 actions_size = MLX5_MH_ACT_SZ * num_actions;
366
367 key.actions = parse_attr->mod_hdr_actions;
368 key.num_actions = num_actions;
369
370 hash_key = hash_mod_hdr_info(&key);
371
d2faae25 372 namespace = get_flow_name_space(flow);
dd58edc3 373 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 374
d2faae25 375 mutex_lock(&tbl->lock);
dd58edc3 376 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
a734d007
VB		 377 if (mh) {
378 mutex_unlock(&tbl->lock);
379 wait_for_completion(&mh->res_ready);
380
381 if (mh->compl_result < 0) {
382 err = -EREMOTEIO;
383 goto attach_header_err;
384 }
11c9c548 385 goto attach_flow;
a734d007 386 }
11c9c548
OG		 387
388 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
d2faae25 389 if (!mh) {
a734d007
VB		 390 mutex_unlock(&tbl->lock);
391 return -ENOMEM;
d2faae25 392 }
11c9c548
OG		 393
394 mh->key.actions = (void *)mh + sizeof(*mh);
395 memcpy(mh->key.actions, key.actions, actions_size);
396 mh->key.num_actions = num_actions;
83a52f0d 397 spin_lock_init(&mh->flows_lock);
11c9c548 398 INIT_LIST_HEAD(&mh->flows);
dd58edc3 399 refcount_set(&mh->refcnt, 1);
a734d007
VB		 400 init_completion(&mh->res_ready);
401
402 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
403 mutex_unlock(&tbl->lock);
11c9c548 404
2b688ea5
MG		 405 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
406 mh->key.num_actions,
407 mh->key.actions);
408 if (IS_ERR(mh->modify_hdr)) {
409 err = PTR_ERR(mh->modify_hdr);
a734d007
VB		 410 mh->compl_result = err;
411 goto alloc_header_err;
412 }
413 mh->compl_result = 1;
414 complete_all(&mh->res_ready);
11c9c548
OG		 415
416attach_flow:
dd58edc3 417 flow->mh = mh;
83a52f0d 418 spin_lock(&mh->flows_lock);
11c9c548 419 list_add(&flow->mod_hdr, &mh->flows);
83a52f0d 420 spin_unlock(&mh->flows_lock);
d2faae25 421 if (mlx5e_is_eswitch_flow(flow))
2b688ea5 422 flow->esw_attr->modify_hdr = mh->modify_hdr;
11c9c548 423 else
2b688ea5 424 flow->nic_attr->modify_hdr = mh->modify_hdr;
11c9c548
OG		 425
426 return 0;
427
a734d007
VB		 428alloc_header_err:
429 complete_all(&mh->res_ready);
430attach_header_err:
431 mlx5e_mod_hdr_put(priv, mh, namespace);
11c9c548
OG		 432 return err;
433}
434
435static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
436 struct mlx5e_tc_flow *flow)
437{
5a7e5bcb 438 /* flow wasn't fully initialized */
dd58edc3 439 if (!flow->mh)
5a7e5bcb
VB		 440 return;
441
83a52f0d 442 spin_lock(&flow->mh->flows_lock);
11c9c548 443 list_del(&flow->mod_hdr);
83a52f0d 444 spin_unlock(&flow->mh->flows_lock);
11c9c548 445
d2faae25 446 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
dd58edc3 447 flow->mh = NULL;
11c9c548
OG		 448}
449
77ab67b7
OG		 450static
451struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
452{
453 struct net_device *netdev;
454 struct mlx5e_priv *priv;
455
456 netdev = __dev_get_by_index(net, ifindex);
457 priv = netdev_priv(netdev);
458 return priv->mdev;
459}
460
461static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
462{
463 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
464 void *tirc;
465 int err;
466
467 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
468 if (err)
469 goto alloc_tdn_err;
470
471 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
472
473 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 474 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 475 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
476
477 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
478 if (err)
479 goto create_tir_err;
480
481 return 0;
482
483create_tir_err:
484 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
485alloc_tdn_err:
486 return err;
487}
488
489static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
490{
491 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
492 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
493}
494
3f6d08d1
OG		 495static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
496{
497 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
498 struct mlx5e_priv *priv = hp->func_priv;
499 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
500
501 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
502 hp->num_channels);
503
504 for (i = 0; i < sz; i++) {
505 ix = i;
bbeb53b8 506 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 507 ix = mlx5e_bits_invert(i, ilog2(sz));
508 ix = indirection_rqt[ix];
509 rqn = hp->pair->rqn[ix];
510 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
511 }
512}
513
514static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
515{
516 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
517 struct mlx5e_priv *priv = hp->func_priv;
518 struct mlx5_core_dev *mdev = priv->mdev;
519 void *rqtc;
520 u32 *in;
521
522 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
523 in = kvzalloc(inlen, GFP_KERNEL);
524 if (!in)
525 return -ENOMEM;
526
527 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
528
529 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
530 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
531
532 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
533
534 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
535 if (!err)
536 hp->indir_rqt.enabled = true;
537
538 kvfree(in);
539 return err;
540}
541
542static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
543{
544 struct mlx5e_priv *priv = hp->func_priv;
545 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
546 int tt, i, err;
547 void *tirc;
548
549 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 550 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
551
3f6d08d1
OG		 552 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
553 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
554
555 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
556 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
557 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 558 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
559
3f6d08d1
OG		 560 err = mlx5_core_create_tir(hp->func_mdev, in,
561 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
562 if (err) {
563 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
564 goto err_destroy_tirs;
565 }
566 }
567 return 0;
568
569err_destroy_tirs:
570 for (i = 0; i < tt; i++)
571 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
572 return err;
573}
574
575static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
576{
577 int tt;
578
579 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
580 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
581}
582
583static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
584 struct ttc_params *ttc_params)
585{
586 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
587 int tt;
588
589 memset(ttc_params, 0, sizeof(*ttc_params));
590
591 ttc_params->any_tt_tirn = hp->tirn;
592
593 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
594 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
595
6412bb39 596 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 597 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
598 ft_attr->prio = MLX5E_TC_PRIO;
599}
600
601static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
602{
603 struct mlx5e_priv *priv = hp->func_priv;
604 struct ttc_params ttc_params;
605 int err;
606
607 err = mlx5e_hairpin_create_indirect_rqt(hp);
608 if (err)
609 return err;
610
611 err = mlx5e_hairpin_create_indirect_tirs(hp);
612 if (err)
613 goto err_create_indirect_tirs;
614
615 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
616 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
617 if (err)
618 goto err_create_ttc_table;
619
620 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
621 hp->num_channels, hp->ttc.ft.t->id);
622
623 return 0;
624
625err_create_ttc_table:
626 mlx5e_hairpin_destroy_indirect_tirs(hp);
627err_create_indirect_tirs:
628 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
629
630 return err;
631}
632
633static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
634{
635 struct mlx5e_priv *priv = hp->func_priv;
636
637 mlx5e_destroy_ttc_table(priv, &hp->ttc);
638 mlx5e_hairpin_destroy_indirect_tirs(hp);
639 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
640}
641
77ab67b7
OG		 642static struct mlx5e_hairpin *
643mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
644 int peer_ifindex)
645{
646 struct mlx5_core_dev *func_mdev, *peer_mdev;
647 struct mlx5e_hairpin *hp;
648 struct mlx5_hairpin *pair;
649 int err;
650
651 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
652 if (!hp)
653 return ERR_PTR(-ENOMEM);
654
655 func_mdev = priv->mdev;
656 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
657
658 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
659 if (IS_ERR(pair)) {
660 err = PTR_ERR(pair);
661 goto create_pair_err;
662 }
663 hp->pair = pair;
664 hp->func_mdev = func_mdev;
3f6d08d1
OG		 665 hp->func_priv = priv;
666 hp->num_channels = params->num_channels;
77ab67b7
OG		 667
668 err = mlx5e_hairpin_create_transport(hp);
669 if (err)
670 goto create_transport_err;
671
3f6d08d1
OG		 672 if (hp->num_channels > 1) {
673 err = mlx5e_hairpin_rss_init(hp);
674 if (err)
675 goto rss_init_err;
676 }
677
77ab67b7
OG		 678 return hp;
679
3f6d08d1
OG		 680rss_init_err:
681 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 682create_transport_err:
683 mlx5_core_hairpin_destroy(hp->pair);
684create_pair_err:
685 kfree(hp);
686 return ERR_PTR(err);
687}
688
689static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
690{
3f6d08d1
OG		 691 if (hp->num_channels > 1)
692 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 693 mlx5e_hairpin_destroy_transport(hp);
694 mlx5_core_hairpin_destroy(hp->pair);
695 kvfree(hp);
696}
697
106be53b
OG		 698static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
699{
700 return (peer_vhca_id << 16 | prio);
701}
702
5c65c564 703static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 704 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 705{
706 struct mlx5e_hairpin_entry *hpe;
106be53b 707 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 708
709 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 710 hairpin_hlist, hash_key) {
e4f9abbd
VB		 711 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
712 refcount_inc(&hpe->refcnt);
5c65c564 713 return hpe;
e4f9abbd 714 }
5c65c564
OG		 715 }
716
717 return NULL;
718}
719
e4f9abbd
VB		 720static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
721 struct mlx5e_hairpin_entry *hpe)
722{
723 /* no more hairpin flows for us, release the hairpin pair */
b32accda 724 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 725 return;
b32accda
VB		 726 hash_del(&hpe->hairpin_hlist);
727 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 728
db76ca24
VB		 729 if (!IS_ERR_OR_NULL(hpe->hp)) {
730 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
731 dev_name(hpe->hp->pair->peer_mdev->device));
732
733 mlx5e_hairpin_destroy(hpe->hp);
734 }
e4f9abbd
VB		 735
736 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 737 kfree(hpe);
738}
739
106be53b
OG		 740#define UNKNOWN_MATCH_PRIO 8
741
742static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 743 struct mlx5_flow_spec *spec, u8 *match_prio,
744 struct netlink_ext_ack *extack)
106be53b
OG		 745{
746 void *headers_c, *headers_v;
747 u8 prio_val, prio_mask = 0;
748 bool vlan_present;
749
750#ifdef CONFIG_MLX5_CORE_EN_DCB
751 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 752 NL_SET_ERR_MSG_MOD(extack,
753 "only PCP trust state supported for hairpin");
106be53b
OG		 754 return -EOPNOTSUPP;
755 }
756#endif
757 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
758 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
759
760 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
761 if (vlan_present) {
762 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
763 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
764 }
765
766 if (!vlan_present || !prio_mask) {
767 prio_val = UNKNOWN_MATCH_PRIO;
768 } else if (prio_mask != 0x7) {
e98bedf5
EB		 769 NL_SET_ERR_MSG_MOD(extack,
770 "masked priority match not supported for hairpin");
106be53b
OG		 771 return -EOPNOTSUPP;
772 }
773
774 *match_prio = prio_val;
775 return 0;
776}
777
5c65c564
OG		 778static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
779 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 780 struct mlx5e_tc_flow_parse_attr *parse_attr,
781 struct netlink_ext_ack *extack)
5c65c564 782{
98b66cb1 783 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 784 struct mlx5_hairpin_params params;
d8822868 785 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 786 struct mlx5e_hairpin_entry *hpe;
787 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 788 u64 link_speed64;
789 u32 link_speed;
106be53b 790 u8 match_prio;
d8822868 791 u16 peer_id;
5c65c564
OG		 792 int err;
793
d8822868
OG		 794 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
795 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 796 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 797 return -EOPNOTSUPP;
798 }
799
d8822868 800 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 801 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
802 extack);
106be53b
OG		 803 if (err)
804 return err;
b32accda
VB		 805
806 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 807 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 808 if (hpe) {
809 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
810 wait_for_completion(&hpe->res_ready);
811
812 if (IS_ERR(hpe->hp)) {
813 err = -EREMOTEIO;
814 goto out_err;
815 }
5c65c564 816 goto attach_flow;
db76ca24 817 }
5c65c564
OG		 818
819 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 820 if (!hpe) {
db76ca24
VB		 821 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
822 return -ENOMEM;
b32accda 823 }
5c65c564 824
73edca73 825 spin_lock_init(&hpe->flows_lock);
5c65c564 826 INIT_LIST_HEAD(&hpe->flows);
db76ca24 827 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 828 hpe->peer_vhca_id = peer_id;
106be53b 829 hpe->prio = match_prio;
e4f9abbd 830 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 831 init_completion(&hpe->res_ready);
832
833 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
834 hash_hairpin_info(peer_id, match_prio));
835 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 836
837 params.log_data_size = 15;
838 params.log_data_size = min_t(u8, params.log_data_size,
839 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
840 params.log_data_size = max_t(u8, params.log_data_size,
841 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 842
eb9180f7
OG		 843 params.log_num_packets = params.log_data_size -
844 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
845 params.log_num_packets = min_t(u8, params.log_num_packets,
846 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
847
848 params.q_counter = priv->q_counter;
3f6d08d1 849 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 850 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 851 link_speed = max_t(u32, link_speed, 50000);
852 link_speed64 = link_speed;
853 do_div(link_speed64, 50000);
854 params.num_channels = link_speed64;
855
5c65c564 856 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 857 hpe->hp = hp;
858 complete_all(&hpe->res_ready);
5c65c564
OG		 859 if (IS_ERR(hp)) {
860 err = PTR_ERR(hp);
db76ca24 861 goto out_err;
5c65c564
OG		 862 }
863
eb9180f7 864 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 865 hp->tirn, hp->pair->rqn[0],
866 dev_name(hp->pair->peer_mdev->device),
eb9180f7 867 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 868
5c65c564 869attach_flow:
3f6d08d1 870 if (hpe->hp->num_channels > 1) {
226f2ca3 871 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 872 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
873 } else {
874 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
875 }
b32accda 876
e4f9abbd 877 flow->hpe = hpe;
73edca73 878 spin_lock(&hpe->flows_lock);
5c65c564 879 list_add(&flow->hairpin, &hpe->flows);
73edca73 880 spin_unlock(&hpe->flows_lock);
3f6d08d1 881
5c65c564
OG		 882 return 0;
883
db76ca24
VB		 884out_err:
885 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 886 return err;
887}
888
889static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
890 struct mlx5e_tc_flow *flow)
891{
5a7e5bcb 892 /* flow wasn't fully initialized */
e4f9abbd 893 if (!flow->hpe)
5a7e5bcb
VB		 894 return;
895
73edca73 896 spin_lock(&flow->hpe->flows_lock);
5c65c564 897 list_del(&flow->hairpin);
73edca73
VB		 898 spin_unlock(&flow->hpe->flows_lock);
899
e4f9abbd
VB		 900 mlx5e_hairpin_put(priv, flow->hpe);
901 flow->hpe = NULL;
5c65c564
OG		 902}
903
c83954ab 904static int
74491de9 905mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 906 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 907 struct mlx5e_tc_flow *flow,
908 struct netlink_ext_ack *extack)
e8f887ac 909{
bb0ee7dc 910 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 911 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 912 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 913 struct mlx5_flow_destination dest[2] = {};
66958ed9 914 struct mlx5_flow_act flow_act = {
3bc4b7bf 915 .action = attr->action,
bb0ee7dc 916 .flags = FLOW_ACT_NO_APPEND,
66958ed9 917 };
aad7e08d 918 struct mlx5_fc *counter = NULL;
5c65c564 919 int err, dest_ix = 0;
e8f887ac 920
bb0ee7dc
JL		 921 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
922 flow_context->flow_tag = attr->flow_tag;
923
226f2ca3 924 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 925 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 926 if (err)
927 return err;
928
226f2ca3 929 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 930 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
931 dest[dest_ix].ft = attr->hairpin_ft;
932 } else {
5c65c564
OG		 933 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
934 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 935 }
936 dest_ix++;
3f6d08d1
OG		 937 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
938 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
939 dest[dest_ix].ft = priv->fs.vlan.ft.t;
940 dest_ix++;
5c65c564 941 }
aad7e08d 942
5c65c564
OG		 943 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
944 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 945 if (IS_ERR(counter))
946 return PTR_ERR(counter);
947
5c65c564 948 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 949 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 950 dest_ix++;
b8aee822 951 attr->counter = counter;
aad7e08d
AV		 952 }
953
2f4fe4ca 954 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 955 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 956 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 957 kfree(parse_attr->mod_hdr_actions);
c83954ab 958 if (err)
5a7e5bcb 959 return err;
2f4fe4ca
OG		 960 }
961
b6fac0b4 962 mutex_lock(&priv->fs.tc.t_lock);
acff797c 963 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
61dc7b01
PB		 964 struct mlx5_flow_table_attr ft_attr = {};
965 int tc_grp_size, tc_tbl_size, tc_num_grps;
21b9c144
OG		 966 u32 max_flow_counter;
967
968 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
969 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
970
971 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
972
973 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
974 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
61dc7b01 975 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
21b9c144 976
61dc7b01
PB		 977 ft_attr.prio = MLX5E_TC_PRIO;
978 ft_attr.max_fte = tc_tbl_size;
979 ft_attr.level = MLX5E_TC_FT_LEVEL;
980 ft_attr.autogroup.max_num_groups = tc_num_grps;
acff797c
MG		 981 priv->fs.tc.t =
982 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
61dc7b01 983 &ft_attr);
acff797c 984 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 985 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 986 NL_SET_ERR_MSG_MOD(extack,
987 "Failed to create tc offload table\n");
e8f887ac
AV		 988 netdev_err(priv->netdev,
989 "Failed to create tc offload table\n");
5a7e5bcb 990 return PTR_ERR(priv->fs.tc.t);
e8f887ac 991 }
e8f887ac
AV		 992 }
993
38aa51c1 994 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 995 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 996
c83954ab
RL		 997 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
998 &flow_act, dest, dest_ix);
b6fac0b4 999 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 1000
a2b7189b 1001 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1002}
1003
d85cdccb
OG		 1004static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1005 struct mlx5e_tc_flow *flow)
1006{
513f8f7f 1007 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 1008 struct mlx5_fc *counter = NULL;
1009
b8aee822 1010 counter = attr->counter;
5a7e5bcb
VB		 1011 if (!IS_ERR_OR_NULL(flow->rule[0]))
1012 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1013 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1014
b6fac0b4 1015 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1016 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1017 mlx5_destroy_flow_table(priv->fs.tc.t);
1018 priv->fs.tc.t = NULL;
1019 }
b6fac0b4 1020 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1021
513f8f7f 1022 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1023 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1024
226f2ca3 1025 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1026 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1027}
1028
aa0cbbae 1029static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1030 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1031
3c37745e 1032static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1033 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1034 struct net_device *mirred_dev,
1035 int out_index,
8c4dc42b 1036 struct netlink_ext_ack *extack,
0ad060ee
RD		 1037 struct net_device **encap_dev,
1038 bool *encap_valid);
3c37745e 1039
6d2a3ed0
OG		 1040static struct mlx5_flow_handle *
1041mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1042 struct mlx5e_tc_flow *flow,
1043 struct mlx5_flow_spec *spec,
1044 struct mlx5_esw_flow_attr *attr)
1045{
1046 struct mlx5_flow_handle *rule;
1047
1048 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1049 if (IS_ERR(rule))
1050 return rule;
1051
e85e02ba 1052 if (attr->split_count) {
6d2a3ed0
OG		 1053 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1054 if (IS_ERR(flow->rule[1])) {
1055 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1056 return flow->rule[1];
1057 }
1058 }
1059
6d2a3ed0
OG		 1060 return rule;
1061}
1062
1063static void
1064mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1065 struct mlx5e_tc_flow *flow,
1066 struct mlx5_esw_flow_attr *attr)
1067{
226f2ca3 1068 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1069
e85e02ba 1070 if (attr->split_count)
6d2a3ed0
OG		 1071 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1072
1073 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1074}
1075
5dbe906f
PB		 1076static struct mlx5_flow_handle *
1077mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1078 struct mlx5e_tc_flow *flow,
1079 struct mlx5_flow_spec *spec,
1080 struct mlx5_esw_flow_attr *slow_attr)
1081{
1082 struct mlx5_flow_handle *rule;
1083
1084 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1085 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1086 slow_attr->split_count = 0;
39ac237c 1087 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f
PB		 1088
1089 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1090 if (!IS_ERR(rule))
226f2ca3 1091 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1092
1093 return rule;
1094}
1095
1096static void
1097mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1098 struct mlx5e_tc_flow *flow,
1099 struct mlx5_esw_flow_attr *slow_attr)
1100{
1101 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1102 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1103 slow_attr->split_count = 0;
39ac237c 1104 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f 1105 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1106 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1107}
1108
ad86755b
VB		 1109/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1110 * function.
1111 */
1112static void unready_flow_add(struct mlx5e_tc_flow *flow,
1113 struct list_head *unready_flows)
1114{
1115 flow_flag_set(flow, NOT_READY);
1116 list_add_tail(&flow->unready, unready_flows);
1117}
1118
1119/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1120 * function.
1121 */
1122static void unready_flow_del(struct mlx5e_tc_flow *flow)
1123{
1124 list_del(&flow->unready);
1125 flow_flag_clear(flow, NOT_READY);
1126}
1127
b4a23329
RD		 1128static void add_unready_flow(struct mlx5e_tc_flow *flow)
1129{
1130 struct mlx5_rep_uplink_priv *uplink_priv;
1131 struct mlx5e_rep_priv *rpriv;
1132 struct mlx5_eswitch *esw;
1133
1134 esw = flow->priv->mdev->priv.eswitch;
1135 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1136 uplink_priv = &rpriv->uplink_priv;
1137
ad86755b
VB		 1138 mutex_lock(&uplink_priv->unready_flows_lock);
1139 unready_flow_add(flow, &uplink_priv->unready_flows);
1140 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1141}
1142
1143static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1144{
ad86755b
VB		 1145 struct mlx5_rep_uplink_priv *uplink_priv;
1146 struct mlx5e_rep_priv *rpriv;
1147 struct mlx5_eswitch *esw;
1148
1149 esw = flow->priv->mdev->priv.eswitch;
1150 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1151 uplink_priv = &rpriv->uplink_priv;
1152
1153 mutex_lock(&uplink_priv->unready_flows_lock);
1154 unready_flow_del(flow);
1155 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1156}
1157
c83954ab 1158static int
74491de9 1159mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1160 struct mlx5e_tc_flow *flow,
1161 struct netlink_ext_ack *extack)
adb4c123
OG		 1162{
1163 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 1164 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1165 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3c37745e 1166 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1167 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1168 struct mlx5e_rep_priv *rpriv;
1169 struct mlx5e_priv *out_priv;
0ad060ee 1170 bool encap_valid = true;
39ac237c 1171 u32 max_prio, max_chain;
0ad060ee 1172 int err = 0;
f493f155 1173 int out_index;
8b32580d 1174
39ac237c 1175 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
d14f6f2a
OG		 1176 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1177 return -EOPNOTSUPP;
1178 }
bf07aa73 1179
84179981
PB		 1180 /* We check chain range only for tc flows.
1181 * For ft flows, we checked attr->chain was originally 0 and set it to
1182 * FDB_FT_CHAIN which is outside tc range.
1183 * See mlx5e_rep_setup_ft_cb().
1184 */
39ac237c 1185 max_chain = mlx5_esw_chains_get_chain_range(esw);
84179981 1186 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
bf07aa73 1187 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
5a7e5bcb 1188 return -EOPNOTSUPP;
bf07aa73
PB		 1189 }
1190
39ac237c 1191 max_prio = mlx5_esw_chains_get_prio_range(esw);
bf07aa73
PB		 1192 if (attr->prio > max_prio) {
1193 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
5a7e5bcb 1194 return -EOPNOTSUPP;
bf07aa73 1195 }
e52c2802 1196
f493f155 1197 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1198 int mirred_ifindex;
1199
f493f155
EB		 1200 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1201 continue;
1202
7040632d 1203 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1204 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1205 mirred_ifindex);
733d4f36 1206 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1207 extack, &encap_dev, &encap_valid);
1208 if (err)
5a7e5bcb 1209 return err;
0ad060ee 1210
3c37745e
OG		 1211 out_priv = netdev_priv(encap_dev);
1212 rpriv = out_priv->ppriv;
1cc26d74
EB		 1213 attr->dests[out_index].rep = rpriv->rep;
1214 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1215 }
1216
8b32580d 1217 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1218 if (err)
5a7e5bcb 1219 return err;
adb4c123 1220
d7e75a32 1221 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1222 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1223 kfree(parse_attr->mod_hdr_actions);
c83954ab 1224 if (err)
5a7e5bcb 1225 return err;
d7e75a32
OG		 1226 }
1227
b8aee822 1228 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1229 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1230 if (IS_ERR(counter))
1231 return PTR_ERR(counter);
b8aee822
MB		 1232
1233 attr->counter = counter;
1234 }
1235
0ad060ee
RD		 1236 /* we get here if one of the following takes place:
1237 * (1) there's no error
1238 * (2) there's an encap action and we don't have valid neigh
3c37745e 1239 */
0ad060ee 1240 if (!encap_valid) {
5dbe906f
PB		 1241 /* continue with goto slow path rule instead */
1242 struct mlx5_esw_flow_attr slow_attr;
1243
1244 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1245 } else {
6d2a3ed0 1246 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1247 }
c83954ab 1248
5a7e5bcb
VB		 1249 if (IS_ERR(flow->rule[0]))
1250 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1251 else
1252 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1253
1254 return 0;
aa0cbbae 1255}
d85cdccb 1256
9272e3df
YK		 1257static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1258{
1259 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1260 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1261 spec->match_value,
1262 misc_parameters_3);
1263 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1264 headers_v,
1265 geneve_tlv_option_0_data);
1266
1267 return !!geneve_tlv_opt_0_data;
1268}
1269
d85cdccb
OG		 1270static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1271 struct mlx5e_tc_flow *flow)
1272{
1273 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1274 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1275 struct mlx5_esw_flow_attr slow_attr;
f493f155 1276 int out_index;
d85cdccb 1277
226f2ca3 1278 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1279 remove_unready_flow(flow);
ef06c9ee
RD		 1280 kvfree(attr->parse_attr);
1281 return;
1282 }
1283
226f2ca3
VB		 1284 if (mlx5e_is_offloaded_flow(flow)) {
1285 if (flow_flag_test(flow, SLOW))
5dbe906f
PB		 1286 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1287 else
1288 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1289 }
d85cdccb 1290
9272e3df
YK		 1291 if (mlx5_flow_has_geneve_opt(flow))
1292 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1293
513f8f7f 1294 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1295
f493f155 1296 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1297 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1298 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1299 kfree(attr->parse_attr->tun_info[out_index]);
1300 }
f493f155 1301 kvfree(attr->parse_attr);
d7e75a32 1302
513f8f7f 1303 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1304 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1305
1306 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1307 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1308}
1309
232c0013 1310void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1311 struct mlx5e_encap_entry *e,
1312 struct list_head *flow_list)
232c0013 1313{
3c37745e 1314 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1315 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1316 struct mlx5_flow_handle *rule;
1317 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1318 struct mlx5e_tc_flow *flow;
1319 int err;
1320
2b688ea5
MG		 1321 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1322 e->reformat_type,
1323 e->encap_size, e->encap_header,
1324 MLX5_FLOW_NAMESPACE_FDB);
1325 if (IS_ERR(e->pkt_reformat)) {
1326 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1327 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1328 return;
1329 }
1330 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1331 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1332
2a1f1768 1333 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1334 bool all_flow_encaps_valid = true;
1335 int i;
1336
95435ad7
VB		 1337 if (!mlx5e_is_offloaded_flow(flow))
1338 continue;
3c37745e 1339 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1340 spec = &esw_attr->parse_attr->spec;
1341
2b688ea5 1342 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1343 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1344 /* Flow can be associated with multiple encap entries.
1345 * Before offloading the flow verify that all of them have
1346 * a valid neighbour.
1347 */
1348 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1349 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1350 continue;
1351 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1352 all_flow_encaps_valid = false;
1353 break;
1354 }
1355 }
1356 /* Do not offload flows with unresolved neighbors */
1357 if (!all_flow_encaps_valid)
2a1f1768 1358 continue;
5dbe906f 1359 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1360 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1361 if (IS_ERR(rule)) {
1362 err = PTR_ERR(rule);
232c0013
HHZ		 1363 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1364 err);
2a1f1768 1365 continue;
232c0013 1366 }
5dbe906f
PB		 1367
1368 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
6d2a3ed0 1369 flow->rule[0] = rule;
226f2ca3
VB		 1370 /* was unset when slow path rule removed */
1371 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1372 }
1373}
1374
1375void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1376 struct mlx5e_encap_entry *e,
1377 struct list_head *flow_list)
232c0013 1378{
3c37745e 1379 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1380 struct mlx5_esw_flow_attr slow_attr;
1381 struct mlx5_flow_handle *rule;
1382 struct mlx5_flow_spec *spec;
232c0013 1383 struct mlx5e_tc_flow *flow;
5dbe906f 1384 int err;
232c0013 1385
2a1f1768 1386 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1387 if (!mlx5e_is_offloaded_flow(flow))
1388 continue;
5dbe906f
PB		 1389 spec = &flow->esw_attr->parse_attr->spec;
1390
1391 /* update from encap rule to slow path rule */
1392 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b 1393 /* mark the flow's encap dest as non-valid */
2a1f1768 1394 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1395
1396 if (IS_ERR(rule)) {
1397 err = PTR_ERR(rule);
1398 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1399 err);
2a1f1768 1400 continue;
5dbe906f
PB		 1401 }
1402
1403 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1404 flow->rule[0] = rule;
226f2ca3
VB		 1405 /* was unset when fast path rule removed */
1406 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1407 }
1408
61c806da
OG		 1409 /* we know that the encap is valid */
1410 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1411 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1412}
1413
b8aee822
MB		 1414static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1415{
226f2ca3 1416 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1417 return flow->esw_attr->counter;
1418 else
1419 return flow->nic_attr->counter;
1420}
1421
2a1f1768
VB		 1422/* Takes reference to all flows attached to encap and adds the flows to
1423 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1424 */
1425void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1426{
1427 struct encap_flow_item *efi;
1428 struct mlx5e_tc_flow *flow;
1429
1430 list_for_each_entry(efi, &e->flows, list) {
1431 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1432 if (IS_ERR(mlx5e_flow_get(flow)))
1433 continue;
95435ad7 1434 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1435
1436 flow->tmp_efi_index = efi->index;
1437 list_add(&flow->tmp_list, flow_list);
1438 }
1439}
1440
6a06c2f7 1441/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1442void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1443{
1444 struct mlx5e_tc_flow *flow, *tmp;
1445
1446 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1447 mlx5e_flow_put(priv, flow);
1448}
1449
ac0d9176
VB		 1450static struct mlx5e_encap_entry *
1451mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1452 struct mlx5e_encap_entry *e)
1453{
1454 struct mlx5e_encap_entry *next = NULL;
1455
1456retry:
1457 rcu_read_lock();
1458
1459 /* find encap with non-zero reference counter value */
1460 for (next = e ?
1461 list_next_or_null_rcu(&nhe->encap_list,
1462 &e->encap_list,
1463 struct mlx5e_encap_entry,
1464 encap_list) :
1465 list_first_or_null_rcu(&nhe->encap_list,
1466 struct mlx5e_encap_entry,
1467 encap_list);
1468 next;
1469 next = list_next_or_null_rcu(&nhe->encap_list,
1470 &next->encap_list,
1471 struct mlx5e_encap_entry,
1472 encap_list))
1473 if (mlx5e_encap_take(next))
1474 break;
1475
1476 rcu_read_unlock();
1477
1478 /* release starting encap */
1479 if (e)
1480 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1481 if (!next)
1482 return next;
1483
1484 /* wait for encap to be fully initialized */
1485 wait_for_completion(&next->res_ready);
1486 /* continue searching if encap entry is not in valid state after completion */
1487 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1488 e = next;
1489 goto retry;
1490 }
1491
1492 return next;
1493}
1494
f6dfb4c3
HHZ		 1495void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1496{
1497 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1498 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1499 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1500 struct mlx5_fc *counter;
1501 struct neigh_table *tbl;
1502 bool neigh_used = false;
1503 struct neighbour *n;
90bb7692 1504 u64 lastuse;
f6dfb4c3
HHZ		 1505
1506 if (m_neigh->family == AF_INET)
1507 tbl = &arp_tbl;
1508#if IS_ENABLED(CONFIG_IPV6)
1509 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1510 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1511#endif
1512 else
1513 return;
1514
ac0d9176
VB		 1515 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1516 * next one.
1517 */
1518 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1519 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1520 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1521 struct mlx5_eswitch *esw;
1522 LIST_HEAD(flow_list);
948993f2 1523
6a06c2f7
VB		 1524 esw = priv->mdev->priv.eswitch;
1525 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1526 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1527 flow = container_of(efi, struct mlx5e_tc_flow,
1528 encaps[efi->index]);
5a7e5bcb
VB		 1529 if (IS_ERR(mlx5e_flow_get(flow)))
1530 continue;
6a06c2f7 1531 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1532
226f2ca3 1533 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1534 counter = mlx5e_tc_get_counter(flow);
90bb7692 1535 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1536 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1537 neigh_used = true;
1538 break;
1539 }
1540 }
1541 }
6a06c2f7 1542 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1543
6a06c2f7 1544 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1545 if (neigh_used) {
1546 /* release current encap before breaking the loop */
6a06c2f7 1547 mlx5e_encap_put(priv, e);
e36d4810 1548 break;
ac0d9176 1549 }
f6dfb4c3
HHZ		 1550 }
1551
c786fe59
VB		 1552 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1553
f6dfb4c3
HHZ		 1554 if (neigh_used) {
1555 nhe->reported_lastuse = jiffies;
1556
1557 /* find the relevant neigh according to the cached device and
1558 * dst ip pair
1559 */
1560 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1561 if (!n)
f6dfb4c3 1562 return;
f6dfb4c3
HHZ		 1563
1564 neigh_event_send(n, NULL);
1565 neigh_release(n);
1566 }
1567}
1568
61086f39 1569static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1570{
948993f2 1571 WARN_ON(!list_empty(&e->flows));
948993f2 1572
3c140dd5
VB		 1573 if (e->compl_result > 0) {
1574 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1575
1576 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1577 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1578 }
948993f2 1579
2a4b6526 1580 kfree(e->tun_info);
948993f2 1581 kfree(e->encap_header);
ac0d9176 1582 kfree_rcu(e, rcu);
948993f2
VB		 1583}
1584
61086f39
VB		 1585void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1586{
1587 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1588
1589 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1590 return;
1591 hash_del_rcu(&e->encap_hlist);
1592 mutex_unlock(&esw->offloads.encap_tbl_lock);
1593
1594 mlx5e_encap_dealloc(priv, e);
1595}
1596
d85cdccb 1597static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1598 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1599{
61086f39
VB		 1600 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1601 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1602
5a7e5bcb 1603 /* flow wasn't fully initialized */
61086f39 1604 if (!e)
5a7e5bcb
VB		 1605 return;
1606
61086f39 1607 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1608 list_del(&flow->encaps[out_index].list);
948993f2 1609 flow->encaps[out_index].e = NULL;
61086f39
VB		 1610 if (!refcount_dec_and_test(&e->refcnt)) {
1611 mutex_unlock(&esw->offloads.encap_tbl_lock);
1612 return;
1613 }
1614 hash_del_rcu(&e->encap_hlist);
1615 mutex_unlock(&esw->offloads.encap_tbl_lock);
1616
1617 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1618}
1619
04de7dda
RD		 1620static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1621{
1622 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1623
226f2ca3
VB		 1624 if (!flow_flag_test(flow, ESWITCH) ||
1625 !flow_flag_test(flow, DUP))
04de7dda
RD		 1626 return;
1627
1628 mutex_lock(&esw->offloads.peer_mutex);
1629 list_del(&flow->peer);
1630 mutex_unlock(&esw->offloads.peer_mutex);
1631
226f2ca3 1632 flow_flag_clear(flow, DUP);
04de7dda 1633
eb252c3a
RD		 1634 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1635 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1636 kfree(flow->peer_flow);
1637 }
1638
04de7dda
RD		 1639 flow->peer_flow = NULL;
1640}
1641
1642static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1643{
1644 struct mlx5_core_dev *dev = flow->priv->mdev;
1645 struct mlx5_devcom *devcom = dev->priv.devcom;
1646 struct mlx5_eswitch *peer_esw;
1647
1648 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1649 if (!peer_esw)
1650 return;
1651
1652 __mlx5e_tc_del_fdb_peer_flow(flow);
1653 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1654}
1655
e8f887ac 1656static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1657 struct mlx5e_tc_flow *flow)
e8f887ac 1658{
226f2ca3 1659 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1660 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1661 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1662 } else {
d85cdccb 1663 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1664 }
e8f887ac
AV		 1665}
1666
bbd00f7e
HHZ		 1667
1668static int parse_tunnel_attr(struct mlx5e_priv *priv,
1669 struct mlx5_flow_spec *spec,
f9e30088 1670 struct flow_cls_offload *f,
6363651d 1671 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1672{
e98bedf5 1673 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1674 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1675 outer_headers);
1676 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1677 outer_headers);
f9e30088 1678 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1679 int err;
2e72eb43 1680
101f4de9 1681 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1682 headers_c, headers_v, match_level);
54c177ca
OS		 1683 if (err) {
1684 NL_SET_ERR_MSG_MOD(extack,
1685 "failed to parse tunnel attributes");
101f4de9 1686 return err;
bbd00f7e
HHZ		 1687 }
1688
fe1587a7
DL		 1689 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1690 struct flow_match_control match;
1691 u16 addr_type;
1692
1693 flow_rule_match_enc_control(rule, &match);
1694 addr_type = match.key->addr_type;
1695
1696 /* For tunnel addr_type used same key id`s as for non-tunnel */
1697 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1698 struct flow_match_ipv4_addrs match;
1699
1700 flow_rule_match_enc_ipv4_addrs(rule, &match);
1701 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1702 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1703 ntohl(match.mask->src));
1704 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1705 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1706 ntohl(match.key->src));
1707
1708 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1709 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1710 ntohl(match.mask->dst));
1711 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1712 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1713 ntohl(match.key->dst));
1714
1715 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1716 ethertype);
1717 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1718 ETH_P_IP);
1719 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1720 struct flow_match_ipv6_addrs match;
1721
1722 flow_rule_match_enc_ipv6_addrs(rule, &match);
1723 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1724 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1725 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1726 ipv6));
1727 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1728 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1729 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1730 ipv6));
1731
1732 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1733 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1734 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1735 ipv6));
1736 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1737 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1738 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1739 ipv6));
1740
1741 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1742 ethertype);
1743 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1744 ETH_P_IPV6);
1745 }
2e72eb43 1746 }
bbd00f7e 1747
8f256622
PNA		 1748 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1749 struct flow_match_ip match;
bcef735c 1750
8f256622
PNA		 1751 flow_rule_match_enc_ip(rule, &match);
1752 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1753 match.mask->tos & 0x3);
1754 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1755 match.key->tos & 0x3);
bcef735c 1756
8f256622
PNA		 1757 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1758 match.mask->tos >> 2);
1759 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1760 match.key->tos >> 2);
bcef735c 1761
8f256622
PNA		 1762 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1763 match.mask->ttl);
1764 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1765 match.key->ttl);
e98bedf5 1766
8f256622 1767 if (match.mask->ttl &&
e98bedf5
EB		 1768 !MLX5_CAP_ESW_FLOWTABLE_FDB
1769 (priv->mdev,
1770 ft_field_support.outer_ipv4_ttl)) {
1771 NL_SET_ERR_MSG_MOD(extack,
1772 "Matching on TTL is not supported");
1773 return -EOPNOTSUPP;
1774 }
1775
bcef735c
OG		 1776 }
1777
bbd00f7e
HHZ		 1778 /* Enforce DMAC when offloading incoming tunneled flows.
1779 * Flow counters require a match on the DMAC.
1780 */
1781 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1782 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1783 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1784 dmac_47_16), priv->netdev->dev_addr);
1785
1786 /* let software handle IP fragments */
1787 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1788 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1789
1790 return 0;
1791}
1792
8377629e
EB		 1793static void *get_match_headers_criteria(u32 flags,
1794 struct mlx5_flow_spec *spec)
1795{
1796 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1797 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1798 inner_headers) :
1799 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1800 outer_headers);
1801}
1802
1803static void *get_match_headers_value(u32 flags,
1804 struct mlx5_flow_spec *spec)
1805{
1806 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1807 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1808 inner_headers) :
1809 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1810 outer_headers);
1811}
1812
6d65bc64 1813static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1814 struct flow_cls_offload *f)
1815{
1816 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1817 struct netlink_ext_ack *extack = f->common.extack;
1818 struct net_device *ingress_dev;
1819 struct flow_match_meta match;
1820
1821 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1822 return 0;
1823
1824 flow_rule_match_meta(rule, &match);
1825 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1826 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
1827 return -EINVAL;
1828 }
1829
1830 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1831 match.key->ingress_ifindex);
1832 if (!ingress_dev) {
1833 NL_SET_ERR_MSG_MOD(extack,
1834 "Can't find the ingress port to match on");
1835 return -EINVAL;
1836 }
1837
1838 if (ingress_dev != filter_dev) {
1839 NL_SET_ERR_MSG_MOD(extack,
1840 "Can't match on the ingress filter port");
1841 return -EINVAL;
1842 }
1843
1844 return 0;
1845}
1846
de0af0bf
RD		 1847static int __parse_cls_flower(struct mlx5e_priv *priv,
1848 struct mlx5_flow_spec *spec,
f9e30088 1849 struct flow_cls_offload *f,
54c177ca 1850 struct net_device *filter_dev,
93b3586e 1851 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 1852{
e98bedf5 1853 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1854 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1855 outer_headers);
1856 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1857 outer_headers);
699e96dd
JL		 1858 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1859 misc_parameters);
1860 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1861 misc_parameters);
f9e30088 1862 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1863 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1864 u16 addr_type = 0;
1865 u8 ip_proto = 0;
93b3586e 1866 u8 *match_level;
6d65bc64 1867 int err;
e3a2b7ed 1868
93b3586e 1869 match_level = outer_match_level;
de0af0bf 1870
8f256622 1871 if (dissector->used_keys &
3d144578
VB		 1872 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1873 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1874 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1875 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1876 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1877 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1878 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1879 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1880 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1881 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1882 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1883 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1884 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1885 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1886 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1887 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1888 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1889 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1890 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1891 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1892 dissector->used_keys);
e3a2b7ed
AV		 1893 return -EOPNOTSUPP;
1894 }
1895
075973c7 1896 if (mlx5e_get_tc_tun(filter_dev)) {
93b3586e
HN		 1897 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1898 outer_match_level))
bbd00f7e 1899 return -EOPNOTSUPP;
bbd00f7e 1900
93b3586e 1901 /* At this point, header pointers should point to the inner
bbd00f7e
HHZ		 1902 * headers, outer header were already set by parse_tunnel_attr
1903 */
93b3586e 1904 match_level = inner_match_level;
8377629e
EB		 1905 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1906 spec);
1907 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1908 spec);
bbd00f7e
HHZ		 1909 }
1910
6d65bc64 1911 err = mlx5e_flower_parse_meta(filter_dev, f);
1912 if (err)
1913 return err;
1914
8f256622
PNA		 1915 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1916 struct flow_match_basic match;
1917
1918 flow_rule_match_basic(rule, &match);
d3a80bb5 1919 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1920 ntohs(match.mask->n_proto));
d3a80bb5 1921 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1922 ntohs(match.key->n_proto));
e3a2b7ed 1923
8f256622 1924 if (match.mask->n_proto)
d708f902 1925 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1926 }
35a605db
EB		 1927 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1928 is_vlan_dev(filter_dev)) {
1929 struct flow_dissector_key_vlan filter_dev_mask;
1930 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1931 struct flow_match_vlan match;
1932
35a605db
EB		 1933 if (is_vlan_dev(filter_dev)) {
1934 match.key = &filter_dev_key;
1935 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1936 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1937 match.key->vlan_priority = 0;
1938 match.mask = &filter_dev_mask;
1939 memset(match.mask, 0xff, sizeof(*match.mask));
1940 match.mask->vlan_priority = 0;
1941 } else {
1942 flow_rule_match_vlan(rule, &match);
1943 }
8f256622
PNA		 1944 if (match.mask->vlan_id ||
1945 match.mask->vlan_priority ||
1946 match.mask->vlan_tpid) {
1947 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1948 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1949 svlan_tag, 1);
1950 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1951 svlan_tag, 1);
1952 } else {
1953 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1954 cvlan_tag, 1);
1955 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1956 cvlan_tag, 1);
1957 }
095b6cfd 1958
8f256622
PNA		 1959 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1960 match.mask->vlan_id);
1961 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1962 match.key->vlan_id);
358d79a4 1963
8f256622
PNA		 1964 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1965 match.mask->vlan_priority);
1966 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1967 match.key->vlan_priority);
54782900 1968
d708f902 1969 *match_level = MLX5_MATCH_L2;
54782900 1970 }
d3a80bb5 1971 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 1972 /* cvlan_tag enabled in match criteria and
1973 * disabled in match value means both S & C tags
1974 * don't exist (untagged of both)
1975 */
cee26487 1976 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1977 *match_level = MLX5_MATCH_L2;
54782900
OG		 1978 }
1979
8f256622
PNA		 1980 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1981 struct flow_match_vlan match;
1982
12d5cbf8 1983 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1984 if (match.mask->vlan_id ||
1985 match.mask->vlan_priority ||
1986 match.mask->vlan_tpid) {
1987 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1988 MLX5_SET(fte_match_set_misc, misc_c,
1989 outer_second_svlan_tag, 1);
1990 MLX5_SET(fte_match_set_misc, misc_v,
1991 outer_second_svlan_tag, 1);
1992 } else {
1993 MLX5_SET(fte_match_set_misc, misc_c,
1994 outer_second_cvlan_tag, 1);
1995 MLX5_SET(fte_match_set_misc, misc_v,
1996 outer_second_cvlan_tag, 1);
1997 }
1998
1999 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2000 match.mask->vlan_id);
699e96dd 2001 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2002 match.key->vlan_id);
699e96dd 2003 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2004 match.mask->vlan_priority);
699e96dd 2005 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2006 match.key->vlan_priority);
699e96dd
JL		 2007
2008 *match_level = MLX5_MATCH_L2;
2009 }
2010 }
2011
8f256622
PNA		 2012 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2013 struct flow_match_eth_addrs match;
54782900 2014
8f256622 2015 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2016 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2017 dmac_47_16),
8f256622 2018 match.mask->dst);
d3a80bb5
OG		 2019 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2020 dmac_47_16),
8f256622 2021 match.key->dst);
d3a80bb5
OG		 2022
2023 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2024 smac_47_16),
8f256622 2025 match.mask->src);
d3a80bb5
OG		 2026 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2027 smac_47_16),
8f256622 2028 match.key->src);
d3a80bb5 2029
8f256622
PNA		 2030 if (!is_zero_ether_addr(match.mask->src) ||
2031 !is_zero_ether_addr(match.mask->dst))
d708f902 2032 *match_level = MLX5_MATCH_L2;
54782900
OG		 2033 }
2034
8f256622
PNA		 2035 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2036 struct flow_match_control match;
54782900 2037
8f256622
PNA		 2038 flow_rule_match_control(rule, &match);
2039 addr_type = match.key->addr_type;
54782900
OG		 2040
2041 /* the HW doesn't support frag first/later */
8f256622 2042 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2043 return -EOPNOTSUPP;
2044
8f256622 2045 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2046 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2047 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2048 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2049
2050 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2051 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2052 *match_level = MLX5_MATCH_L2;
54782900
OG		 2053 /* *** L2 attributes parsing up to here *** */
2054 else
83621b7d 2055 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2056 }
2057 }
2058
8f256622
PNA		 2059 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2060 struct flow_match_basic match;
2061
2062 flow_rule_match_basic(rule, &match);
2063 ip_proto = match.key->ip_proto;
54782900
OG		 2064
2065 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2066 match.mask->ip_proto);
54782900 2067 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2068 match.key->ip_proto);
54782900 2069
8f256622 2070 if (match.mask->ip_proto)
d708f902 2071 *match_level = MLX5_MATCH_L3;
54782900
OG		 2072 }
2073
e3a2b7ed 2074 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2075 struct flow_match_ipv4_addrs match;
e3a2b7ed 2076
8f256622 2077 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2078 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2079 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2080 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2081 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2082 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2083 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2084 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2085 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2086 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2087 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2088 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2089 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2090
8f256622 2091 if (match.mask->src || match.mask->dst)
d708f902 2092 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2093 }
2094
2095 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2096 struct flow_match_ipv6_addrs match;
e3a2b7ed 2097
8f256622 2098 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2099 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2100 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2101 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2102 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2103 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2104 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2105
2106 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2107 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2108 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2109 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2110 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2111 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2112
8f256622
PNA		 2113 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2114 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2115 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2116 }
2117
8f256622
PNA		 2118 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2119 struct flow_match_ip match;
1f97a526 2120
8f256622
PNA		 2121 flow_rule_match_ip(rule, &match);
2122 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2123 match.mask->tos & 0x3);
2124 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2125 match.key->tos & 0x3);
1f97a526 2126
8f256622
PNA		 2127 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2128 match.mask->tos >> 2);
2129 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2130 match.key->tos >> 2);
1f97a526 2131
8f256622
PNA		 2132 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2133 match.mask->ttl);
2134 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2135 match.key->ttl);
1f97a526 2136
8f256622 2137 if (match.mask->ttl &&
a8ade55f 2138 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2139 ft_field_support.outer_ipv4_ttl)) {
2140 NL_SET_ERR_MSG_MOD(extack,
2141 "Matching on TTL is not supported");
1f97a526 2142 return -EOPNOTSUPP;
e98bedf5 2143 }
a8ade55f 2144
8f256622 2145 if (match.mask->tos || match.mask->ttl)
d708f902 2146 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2147 }
2148
54782900
OG		 2149 /* *** L3 attributes parsing up to here *** */
2150
8f256622
PNA		 2151 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2152 struct flow_match_ports match;
2153
2154 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2155 switch (ip_proto) {
2156 case IPPROTO_TCP:
2157 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2158 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2159 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2160 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2161
2162 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2163 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2164 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2165 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2166 break;
2167
2168 case IPPROTO_UDP:
2169 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2170 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2171 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2172 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2173
2174 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2175 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2176 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2177 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2178 break;
2179 default:
e98bedf5
EB		 2180 NL_SET_ERR_MSG_MOD(extack,
2181 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2182 netdev_err(priv->netdev,
2183 "Only UDP and TCP transport are supported\n");
2184 return -EINVAL;
2185 }
de0af0bf 2186
8f256622 2187 if (match.mask->src || match.mask->dst)
d708f902 2188 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2189 }
2190
8f256622
PNA		 2191 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2192 struct flow_match_tcp match;
e77834ec 2193
8f256622 2194 flow_rule_match_tcp(rule, &match);
e77834ec 2195 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2196 ntohs(match.mask->flags));
e77834ec 2197 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2198 ntohs(match.key->flags));
e77834ec 2199
8f256622 2200 if (match.mask->flags)
d708f902 2201 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2202 }
2203
e3a2b7ed
AV		 2204 return 0;
2205}
2206
de0af0bf 2207static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2208 struct mlx5e_tc_flow *flow,
de0af0bf 2209 struct mlx5_flow_spec *spec,
f9e30088 2210 struct flow_cls_offload *f,
54c177ca 2211 struct net_device *filter_dev)
de0af0bf 2212{
93b3586e 2213 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2214 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2215 struct mlx5_core_dev *dev = priv->mdev;
2216 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2217 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2218 struct mlx5_eswitch_rep *rep;
226f2ca3 2219 bool is_eswitch_flow;
de0af0bf
RD		 2220 int err;
2221
93b3586e
HN		 2222 inner_match_level = MLX5_MATCH_NONE;
2223 outer_match_level = MLX5_MATCH_NONE;
2224
2225 err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2226 &outer_match_level);
2227 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2228 outer_match_level : inner_match_level;
de0af0bf 2229
226f2ca3
VB		 2230 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2231 if (!err && is_eswitch_flow) {
1d447a39 2232 rep = rpriv->rep;
b05af6aa 2233 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2234 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2235 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2236 NL_SET_ERR_MSG_MOD(extack,
2237 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2238 netdev_warn(priv->netdev,
2239 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2240 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2241 return -EOPNOTSUPP;
2242 }
2243 }
2244
226f2ca3 2245 if (is_eswitch_flow) {
93b3586e
HN		 2246 flow->esw_attr->inner_match_level = inner_match_level;
2247 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2248 } else {
93b3586e 2249 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2250 }
38aa51c1 2251
de0af0bf
RD		 2252 return err;
2253}
2254
d79b6df6
OG		 2255struct pedit_headers {
2256 struct ethhdr eth;
0eb69bb9 2257 struct vlan_hdr vlan;
d79b6df6
OG		 2258 struct iphdr ip4;
2259 struct ipv6hdr ip6;
2260 struct tcphdr tcp;
2261 struct udphdr udp;
2262};
2263
c500c86b
PNA		 2264struct pedit_headers_action {
2265 struct pedit_headers vals;
2266 struct pedit_headers masks;
2267 u32 pedits;
2268};
2269
d79b6df6 2270static int pedit_header_offsets[] = {
73867881
PNA		 2271 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2272 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2273 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2274 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2275 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2276};
2277
2278#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2279
2280static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2281 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2282{
2283 u32 *curr_pmask, *curr_pval;
2284
c500c86b
PNA		 2285 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2286 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2287
2288 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2289 goto out_err;
2290
2291 *curr_pmask |= mask;
2292 *curr_pval |= (val & mask);
2293
2294 return 0;
2295
2296out_err:
2297 return -EOPNOTSUPP;
2298}
2299
2300struct mlx5_fields {
2301 u8 field;
88f30bbc
DL		 2302 u8 field_bsize;
2303 u32 field_mask;
d79b6df6 2304 u32 offset;
27c11b6b 2305 u32 match_offset;
d79b6df6
OG		 2306};
2307
88f30bbc
DL		 2308#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2309 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2310 offsetof(struct pedit_headers, field) + (off), \
2311 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2312
2ef86872
EB		 2313/* masked values are the same and there are no rewrites that do not have a
2314 * match.
2315 */
2316#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2317 type matchmaskx = *(type *)(matchmaskp); \
2318 type matchvalx = *(type *)(matchvalp); \
2319 type maskx = *(type *)(maskp); \
2320 type valx = *(type *)(valp); \
2321 \
2322 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2323 matchmaskx)); \
2324})
2325
27c11b6b 2326static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2327 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2328{
2329 bool same = false;
2330
88f30bbc
DL		 2331 switch (bsize) {
2332 case 8:
2ef86872 2333 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2334 break;
88f30bbc 2335 case 16:
2ef86872 2336 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2337 break;
88f30bbc 2338 case 32:
2ef86872 2339 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2340 break;
2341 }
2342
2343 return same;
2344}
a8e4f0c4 2345
d79b6df6 2346static struct mlx5_fields fields[] = {
88f30bbc
DL		 2347 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2348 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2349 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2350 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2351 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2352 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2353
ab9341b5 2354 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2355 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2356 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2357 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2358
2359 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2360 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2361 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2362 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2363 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2364 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2365 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2366 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2367 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2368 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2369 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2370 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2371 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2372 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2373 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2374 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2375 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
27c11b6b 2376
88f30bbc
DL		 2377 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2378 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2379 /* in linux iphdr tcp_flags is 8 bits long */
2380 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2381
88f30bbc
DL		 2382 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2383 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2384};
2385
218d05ce
TZ		 2386/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2387 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2388 * says how many HW actions were actually parsed.
d79b6df6 2389 */
c500c86b 2390static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2391 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2392 u32 *action_flags,
e98bedf5 2393 struct netlink_ext_ack *extack)
d79b6df6
OG		 2394{
2395 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 2396 int i, action_size, nactions, max_actions, first, last, next_z;
88f30bbc
DL		 2397 void *headers_c, *headers_v, *action, *vals_p;
2398 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
d79b6df6 2399 struct mlx5_fields *f;
d79b6df6 2400 unsigned long mask;
2b64beba
OG		 2401 __be32 mask_be32;
2402 __be16 mask_be16;
88f30bbc
DL		 2403 u8 cmd;
2404
2405 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2406 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2407
73867881
PNA		 2408 set_masks = &hdrs[0].masks;
2409 add_masks = &hdrs[1].masks;
2410 set_vals = &hdrs[0].vals;
2411 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2412
2413 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2414 action = parse_attr->mod_hdr_actions +
2415 parse_attr->num_mod_hdr_actions * action_size;
2416
2417 max_actions = parse_attr->max_mod_hdr_actions;
2418 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2419
2420 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2421 bool skip;
2422
d79b6df6
OG		 2423 f = &fields[i];
2424 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2425 s_mask = 0;
2426 a_mask = 0;
d79b6df6
OG		 2427
2428 s_masks_p = (void *)set_masks + f->offset;
2429 a_masks_p = (void *)add_masks + f->offset;
2430
88f30bbc
DL		 2431 s_mask = *s_masks_p & f->field_mask;
2432 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2433
2434 if (!s_mask && !a_mask) /* nothing to offload here */
2435 continue;
2436
2437 if (s_mask && a_mask) {
e98bedf5
EB		 2438 NL_SET_ERR_MSG_MOD(extack,
2439 "can't set and add to the same HW field");
d79b6df6
OG		 2440 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2441 return -EOPNOTSUPP;
2442 }
2443
2444 if (nactions == max_actions) {
e98bedf5
EB		 2445 NL_SET_ERR_MSG_MOD(extack,
2446 "too many pedit actions, can't offload");
d79b6df6
OG		 2447 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2448 return -EOPNOTSUPP;
2449 }
2450
27c11b6b 2451 skip = false;
d79b6df6 2452 if (s_mask) {
27c11b6b
EB		 2453 void *match_mask = headers_c + f->match_offset;
2454 void *match_val = headers_v + f->match_offset;
2455
d79b6df6
OG		 2456 cmd = MLX5_ACTION_TYPE_SET;
2457 mask = s_mask;
2458 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2459 /* don't rewrite if we have a match on the same value */
2460 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2461 match_mask, f->field_bsize))
27c11b6b 2462 skip = true;
d79b6df6 2463 /* clear to denote we consumed this field */
88f30bbc 2464 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2465 } else {
2466 cmd = MLX5_ACTION_TYPE_ADD;
2467 mask = a_mask;
2468 vals_p = (void *)add_vals + f->offset;
27c11b6b 2469 /* add 0 is no change */
88f30bbc 2470 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2471 skip = true;
d79b6df6 2472 /* clear to denote we consumed this field */
88f30bbc 2473 *a_masks_p &= ~f->field_mask;
d79b6df6 2474 }
27c11b6b
EB		 2475 if (skip)
2476 continue;
d79b6df6 2477
88f30bbc 2478 if (f->field_bsize == 32) {
2b64beba
OG		 2479 mask_be32 = *(__be32 *)&mask;
2480 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
88f30bbc 2481 } else if (f->field_bsize == 16) {
2b64beba
OG		 2482 mask_be16 = *(__be16 *)&mask;
2483 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2484 }
2485
88f30bbc
DL		 2486 first = find_first_bit(&mask, f->field_bsize);
2487 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2488 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2489 if (first < next_z && next_z < last) {
e98bedf5
EB		 2490 NL_SET_ERR_MSG_MOD(extack,
2491 "rewrite of few sub-fields isn't supported");
2b64beba 2492 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2493 mask);
2494 return -EOPNOTSUPP;
2495 }
2496
2497 MLX5_SET(set_action_in, action, action_type, cmd);
2498 MLX5_SET(set_action_in, action, field, f->field);
2499
2500 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2501 int start;
2502
2503 /* if field is bit sized it can start not from first bit */
2504 start = find_first_bit((unsigned long *)&f->field_mask,
2505 f->field_bsize);
2506
2507 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2508 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2509 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2510 }
2511
88f30bbc 2512 if (f->field_bsize == 32)
2b64beba 2513 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2514 else if (f->field_bsize == 16)
2b64beba 2515 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2516 else if (f->field_bsize == 8)
2b64beba 2517 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2518
2519 action += action_size;
2520 nactions++;
2521 }
2522
2523 parse_attr->num_mod_hdr_actions = nactions;
2524 return 0;
2525}
2526
2cc1cb1d
TZ		 2527static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2528 int namespace)
2529{
2530 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2531 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2532 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2533 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2534}
2535
d79b6df6 2536static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2537 struct pedit_headers_action *hdrs,
2538 int namespace,
d79b6df6
OG		 2539 struct mlx5e_tc_flow_parse_attr *parse_attr)
2540{
2541 int nkeys, action_size, max_actions;
2542
c500c86b
PNA		 2543 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2544 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2545 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2546
2cc1cb1d 2547 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2548 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2549 max_actions = min(max_actions, nkeys * 16);
2550
2551 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2552 if (!parse_attr->mod_hdr_actions)
2553 return -ENOMEM;
2554
218d05ce 2555 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2556 return 0;
2557}
2558
2559static const struct pedit_headers zero_masks = {};
2560
2561static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2562 const struct flow_action_entry *act, int namespace,
e98bedf5 2563 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2564 struct pedit_headers_action *hdrs,
e98bedf5 2565 struct netlink_ext_ack *extack)
d79b6df6 2566{
73867881
PNA		 2567 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2568 int err = -EOPNOTSUPP;
d79b6df6 2569 u32 mask, val, offset;
73867881 2570 u8 htype;
d79b6df6 2571
73867881
PNA		 2572 htype = act->mangle.htype;
2573 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2574
73867881
PNA		 2575 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2576 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2577 goto out_err;
2578 }
d79b6df6 2579
2cc1cb1d
TZ		 2580 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2581 NL_SET_ERR_MSG_MOD(extack,
2582 "The pedit offload action is not supported");
2583 goto out_err;
2584 }
2585
73867881
PNA		 2586 mask = act->mangle.mask;
2587 val = act->mangle.val;
2588 offset = act->mangle.offset;
d79b6df6 2589
73867881
PNA		 2590 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2591 if (err)
2592 goto out_err;
c500c86b 2593
73867881 2594 hdrs[cmd].pedits++;
d79b6df6 2595
c500c86b
PNA		 2596 return 0;
2597out_err:
2598 return err;
2599}
2600
2601static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2602 struct mlx5e_tc_flow_parse_attr *parse_attr,
2603 struct pedit_headers_action *hdrs,
27c11b6b 2604 u32 *action_flags,
c500c86b
PNA		 2605 struct netlink_ext_ack *extack)
2606{
2607 struct pedit_headers *cmd_masks;
2608 int err;
2609 u8 cmd;
2610
218d05ce 2611 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2612 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2613 if (err)
2614 goto out_err;
2615 }
d79b6df6 2616
27c11b6b 2617 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2618 if (err < 0)
2619 goto out_dealloc_parsed_actions;
2620
2621 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2622 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2623 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2624 NL_SET_ERR_MSG_MOD(extack,
2625 "attempt to offload an unsupported field");
b3a433de 2626 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2627 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2628 16, 1, cmd_masks, sizeof(zero_masks), true);
2629 err = -EOPNOTSUPP;
2630 goto out_dealloc_parsed_actions;
2631 }
2632 }
2633
2634 return 0;
2635
2636out_dealloc_parsed_actions:
2637 kfree(parse_attr->mod_hdr_actions);
2638out_err:
2639 return err;
2640}
2641
e98bedf5
EB		 2642static bool csum_offload_supported(struct mlx5e_priv *priv,
2643 u32 action,
2644 u32 update_flags,
2645 struct netlink_ext_ack *extack)
26c02749
OG		 2646{
2647 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2648 TCA_CSUM_UPDATE_FLAG_UDP;
2649
2650 /* The HW recalcs checksums only if re-writing headers */
2651 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2652 NL_SET_ERR_MSG_MOD(extack,
2653 "TC csum action is only offloaded with pedit");
26c02749
OG		 2654 netdev_warn(priv->netdev,
2655 "TC csum action is only offloaded with pedit\n");
2656 return false;
2657 }
2658
2659 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2660 NL_SET_ERR_MSG_MOD(extack,
2661 "can't offload TC csum action for some header/s");
26c02749
OG		 2662 netdev_warn(priv->netdev,
2663 "can't offload TC csum action for some header/s - flags %#x\n",
2664 update_flags);
2665 return false;
2666 }
2667
2668 return true;
2669}
2670
8998576b
DL		 2671struct ip_ttl_word {
2672 __u8 ttl;
2673 __u8 protocol;
2674 __sum16 check;
2675};
2676
2677struct ipv6_hoplimit_word {
2678 __be16 payload_len;
2679 __u8 nexthdr;
2680 __u8 hop_limit;
2681};
2682
2683static bool is_action_keys_supported(const struct flow_action_entry *act)
2684{
2685 u32 mask, offset;
2686 u8 htype;
2687
2688 htype = act->mangle.htype;
2689 offset = act->mangle.offset;
2690 mask = ~act->mangle.mask;
2691 /* For IPv4 & IPv6 header check 4 byte word,
2692 * to determine that modified fields
2693 * are NOT ttl & hop_limit only.
2694 */
2695 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2696 struct ip_ttl_word *ttl_word =
2697 (struct ip_ttl_word *)&mask;
2698
2699 if (offset != offsetof(struct iphdr, ttl) ||
2700 ttl_word->protocol ||
2701 ttl_word->check) {
2702 return true;
2703 }
2704 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2705 struct ipv6_hoplimit_word *hoplimit_word =
2706 (struct ipv6_hoplimit_word *)&mask;
2707
2708 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2709 hoplimit_word->payload_len ||
2710 hoplimit_word->nexthdr) {
2711 return true;
2712 }
2713 }
2714 return false;
2715}
2716
bdd66ac0 2717static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2718 struct flow_action *flow_action,
1651925d 2719 u32 actions,
e98bedf5 2720 struct netlink_ext_ack *extack)
bdd66ac0 2721{
73867881 2722 const struct flow_action_entry *act;
bdd66ac0 2723 bool modify_ip_header;
bdd66ac0
OG		 2724 void *headers_v;
2725 u16 ethertype;
8998576b 2726 u8 ip_proto;
73867881 2727 int i;
bdd66ac0 2728
8377629e 2729 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2730 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2731
2732 /* for non-IP we only re-write MACs, so we're okay */
2733 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2734 goto out_ok;
2735
2736 modify_ip_header = false;
73867881
PNA		 2737 flow_action_for_each(i, act, flow_action) {
2738 if (act->id != FLOW_ACTION_MANGLE &&
2739 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2740 continue;
2741
8998576b 2742 if (is_action_keys_supported(act)) {
73867881
PNA		 2743 modify_ip_header = true;
2744 break;
bdd66ac0
OG		 2745 }
2746 }
2747
2748 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2749 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2750 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2751 NL_SET_ERR_MSG_MOD(extack,
2752 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2753 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2754 return false;
2755 }
2756
2757out_ok:
2758 return true;
2759}
2760
2761static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2762 struct flow_action *flow_action,
bdd66ac0 2763 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2764 struct mlx5e_tc_flow *flow,
2765 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2766{
2767 u32 actions;
2768
226f2ca3 2769 if (mlx5e_is_eswitch_flow(flow))
bdd66ac0
OG		 2770 actions = flow->esw_attr->action;
2771 else
2772 actions = flow->nic_attr->action;
2773
226f2ca3 2774 if (flow_flag_test(flow, EGRESS) &&
35a605db 2775 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
6830b468
TZ		 2776 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2777 (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
7e29392e
RD		 2778 return false;
2779
bdd66ac0 2780 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2781 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2782 flow_action, actions,
e98bedf5 2783 extack);
bdd66ac0
OG		 2784
2785 return true;
2786}
2787
5c65c564
OG		 2788static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2789{
2790 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2791 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2792
2793 fmdev = priv->mdev;
2794 pmdev = peer_priv->mdev;
2795
59c9d35e
AH		 2796 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2797 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2798
816f6706 2799 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2800}
2801
bdc837ee
EB		 2802static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2803 const struct flow_action_entry *act,
2804 struct mlx5e_tc_flow_parse_attr *parse_attr,
2805 struct pedit_headers_action *hdrs,
2806 u32 *action, struct netlink_ext_ack *extack)
2807{
2808 u16 mask16 = VLAN_VID_MASK;
2809 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2810 const struct flow_action_entry pedit_act = {
2811 .id = FLOW_ACTION_MANGLE,
2812 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2813 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2814 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2815 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2816 };
6fca9d1e 2817 u8 match_prio_mask, match_prio_val;
bf2f3bca 2818 void *headers_c, *headers_v;
bdc837ee
EB		 2819 int err;
2820
bf2f3bca
EB		 2821 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2822 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2823
2824 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2825 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2826 NL_SET_ERR_MSG_MOD(extack,
2827 "VLAN rewrite action must have VLAN protocol match");
2828 return -EOPNOTSUPP;
2829 }
2830
6fca9d1e
EB		 2831 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2832 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2833 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2834 NL_SET_ERR_MSG_MOD(extack,
2835 "Changing VLAN prio is not supported");
bdc837ee
EB		 2836 return -EOPNOTSUPP;
2837 }
2838
2839 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2840 hdrs, NULL);
2841 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2842
2843 return err;
2844}
2845
0bac1194
EB		 2846static int
2847add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2848 struct mlx5e_tc_flow_parse_attr *parse_attr,
2849 struct pedit_headers_action *hdrs,
2850 u32 *action, struct netlink_ext_ack *extack)
2851{
2852 const struct flow_action_entry prio_tag_act = {
2853 .vlan.vid = 0,
2854 .vlan.prio =
2855 MLX5_GET(fte_match_set_lyr_2_4,
2856 get_match_headers_value(*action,
2857 &parse_attr->spec),
2858 first_prio) &
2859 MLX5_GET(fte_match_set_lyr_2_4,
2860 get_match_headers_criteria(*action,
2861 &parse_attr->spec),
2862 first_prio),
2863 };
2864
2865 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2866 &prio_tag_act, parse_attr, hdrs, action,
2867 extack);
2868}
2869
73867881
PNA		 2870static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2871 struct flow_action *flow_action,
aa0cbbae 2872 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2873 struct mlx5e_tc_flow *flow,
2874 struct netlink_ext_ack *extack)
e3a2b7ed 2875{
aa0cbbae 2876 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2877 struct pedit_headers_action hdrs[2] = {};
2878 const struct flow_action_entry *act;
1cab1cd7 2879 u32 action = 0;
244cd96a 2880 int err, i;
e3a2b7ed 2881
73867881 2882 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2883 return -EINVAL;
2884
3bc4b7bf 2885 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2886
73867881
PNA		 2887 flow_action_for_each(i, act, flow_action) {
2888 switch (act->id) {
15fc92ec
TZ		 2889 case FLOW_ACTION_ACCEPT:
2890 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2891 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2892 break;
73867881 2893 case FLOW_ACTION_DROP:
1cab1cd7 2894 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2895 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2896 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2897 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2898 break;
2899 case FLOW_ACTION_MANGLE:
2900 case FLOW_ACTION_ADD:
2901 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2902 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2903 if (err)
2904 return err;
2905
1cab1cd7
OG		 2906 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2907 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2908 break;
bdc837ee
EB		 2909 case FLOW_ACTION_VLAN_MANGLE:
2910 err = add_vlan_rewrite_action(priv,
2911 MLX5_FLOW_NAMESPACE_KERNEL,
2912 act, parse_attr, hdrs,
2913 &action, extack);
2914 if (err)
2915 return err;
2916
2917 break;
73867881 2918 case FLOW_ACTION_CSUM:
1cab1cd7 2919 if (csum_offload_supported(priv, action,
73867881 2920 act->csum_flags,
e98bedf5 2921 extack))
73867881 2922 break;
26c02749
OG		 2923
2924 return -EOPNOTSUPP;
73867881
PNA		 2925 case FLOW_ACTION_REDIRECT: {
2926 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2927
2928 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2929 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2930 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 2931 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 2932 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2933 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2934 } else {
e98bedf5
EB		 2935 NL_SET_ERR_MSG_MOD(extack,
2936 "device is not on same HW, can't offload");
5c65c564
OG		 2937 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2938 peer_dev->name);
2939 return -EINVAL;
2940 }
73867881
PNA		 2941 }
2942 break;
2943 case FLOW_ACTION_MARK: {
2944 u32 mark = act->mark;
e3a2b7ed
AV		 2945
2946 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2947 NL_SET_ERR_MSG_MOD(extack,
2948 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2949 return -EINVAL;
2950 }
2951
3bc4b7bf 2952 attr->flow_tag = mark;
1cab1cd7 2953 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2954 }
2955 break;
2956 default:
2cc1cb1d
TZ		 2957 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2958 return -EOPNOTSUPP;
e3a2b7ed 2959 }
e3a2b7ed
AV		 2960 }
2961
c500c86b
PNA		 2962 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2963 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2964 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2965 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2966 if (err)
2967 return err;
27c11b6b
EB		 2968 /* in case all pedit actions are skipped, remove the MOD_HDR
2969 * flag.
2970 */
e7739a60 2971 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2972 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2973 kfree(parse_attr->mod_hdr_actions);
2974 }
c500c86b
PNA		 2975 }
2976
1cab1cd7 2977 attr->action = action;
73867881 2978 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2979 return -EOPNOTSUPP;
2980
e3a2b7ed
AV		 2981 return 0;
2982}
2983
7f1a546e 2984struct encap_key {
1f6da306 2985 const struct ip_tunnel_key *ip_tun_key;
d386939a 2986 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2987};
2988
2989static inline int cmp_encap_info(struct encap_key *a,
2990 struct encap_key *b)
a54e20b4 2991{
7f1a546e 2992 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2993 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2994}
2995
7f1a546e 2996static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2997{
7f1a546e 2998 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2999 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3000}
3001
a54e20b4 3002
b1d90e6b
RL		 3003static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3004 struct net_device *peer_netdev)
3005{
3006 struct mlx5e_priv *peer_priv;
3007
3008 peer_priv = netdev_priv(peer_netdev);
3009
3010 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 3011 mlx5e_eswitch_rep(priv->netdev) &&
3012 mlx5e_eswitch_rep(peer_netdev) &&
3013 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3014}
3015
32f3671f 3016
f5bc2c5d 3017
948993f2
VB		 3018bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3019{
3020 return refcount_inc_not_zero(&e->refcnt);
3021}
3022
3023static struct mlx5e_encap_entry *
3024mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3025 uintptr_t hash_key)
3026{
3027 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3028 struct mlx5e_encap_entry *e;
3029 struct encap_key e_key;
3030
3031 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3032 encap_hlist, hash_key) {
3033 e_key.ip_tun_key = &e->tun_info->key;
3034 e_key.tc_tunnel = e->tunnel;
3035 if (!cmp_encap_info(&e_key, key) &&
3036 mlx5e_encap_take(e))
3037 return e;
3038 }
3039
3040 return NULL;
3041}
3042
2a4b6526
VB		 3043static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3044{
3045 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3046
3047 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3048}
3049
554fe75c
DL		 3050static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3051 struct mlx5e_tc_flow *flow,
3052 int out_index,
3053 struct mlx5e_encap_entry *e,
3054 struct netlink_ext_ack *extack)
3055{
3056 int i;
3057
3058 for (i = 0; i < out_index; i++) {
3059 if (flow->encaps[i].e != e)
3060 continue;
3061 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3062 netdev_err(priv->netdev, "can't duplicate encap action\n");
3063 return true;
3064 }
3065
3066 return false;
3067}
3068
a54e20b4 3069static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3070 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3071 struct net_device *mirred_dev,
3072 int out_index,
8c4dc42b 3073 struct netlink_ext_ack *extack,
0ad060ee
RD		 3074 struct net_device **encap_dev,
3075 bool *encap_valid)
a54e20b4
HHZ		 3076{
3077 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3078 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3079 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3080 const struct ip_tunnel_info *tun_info;
948993f2 3081 struct encap_key key;
c1ae1152 3082 struct mlx5e_encap_entry *e;
733d4f36 3083 unsigned short family;
a54e20b4 3084 uintptr_t hash_key;
54c177ca 3085 int err = 0;
a54e20b4 3086
733d4f36 3087 parse_attr = attr->parse_attr;
1f6da306 3088 tun_info = parse_attr->tun_info[out_index];
733d4f36 3089 family = ip_tunnel_info_af(tun_info);
7f1a546e 3090 key.ip_tun_key = &tun_info->key;
d386939a 3091 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3092 if (!key.tc_tunnel) {
3093 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3094 return -EOPNOTSUPP;
3095 }
733d4f36 3096
7f1a546e 3097 hash_key = hash_encap_info(&key);
a54e20b4 3098
61086f39 3099 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3100 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3101
b2812089 3102 /* must verify if encap is valid or not */
d589e785 3103 if (e) {
554fe75c
DL		 3104 /* Check that entry was not already attached to this flow */
3105 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3106 err = -EOPNOTSUPP;
3107 goto out_err;
3108 }
3109
d589e785
VB		 3110 mutex_unlock(&esw->offloads.encap_tbl_lock);
3111 wait_for_completion(&e->res_ready);
3112
3113 /* Protect against concurrent neigh update. */
3114 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3115 if (e->compl_result < 0) {
d589e785
VB		 3116 err = -EREMOTEIO;
3117 goto out_err;
3118 }
45247bf2 3119 goto attach_flow;
d589e785 3120 }
a54e20b4
HHZ		 3121
3122 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3123 if (!e) {
3124 err = -ENOMEM;
3125 goto out_err;
3126 }
a54e20b4 3127
948993f2 3128 refcount_set(&e->refcnt, 1);
d589e785
VB		 3129 init_completion(&e->res_ready);
3130
2a4b6526
VB		 3131 tun_info = dup_tun_info(tun_info);
3132 if (!tun_info) {
3133 err = -ENOMEM;
3134 goto out_err_init;
3135 }
1f6da306 3136 e->tun_info = tun_info;
101f4de9 3137 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3138 if (err)
3139 goto out_err_init;
54c177ca 3140
a54e20b4 3141 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3142 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3143 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3144
ce99f6b9 3145 if (family == AF_INET)
101f4de9 3146 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3147 else if (family == AF_INET6)
101f4de9 3148 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3149
d589e785
VB		 3150 /* Protect against concurrent neigh update. */
3151 mutex_lock(&esw->offloads.encap_tbl_lock);
3152 complete_all(&e->res_ready);
3153 if (err) {
3154 e->compl_result = err;
a54e20b4 3155 goto out_err;
d589e785 3156 }
3c140dd5 3157 e->compl_result = 1;
a54e20b4 3158
45247bf2 3159attach_flow:
948993f2 3160 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3161 list_add(&flow->encaps[out_index].list, &e->flows);
3162 flow->encaps[out_index].index = out_index;
45247bf2 3163 *encap_dev = e->out_dev;
8c4dc42b 3164 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3165 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3166 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3167 *encap_valid = true;
8c4dc42b 3168 } else {
0ad060ee 3169 *encap_valid = false;
8c4dc42b 3170 }
61086f39 3171 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3172
232c0013 3173 return err;
a54e20b4
HHZ		 3174
3175out_err:
61086f39 3176 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3177 if (e)
3178 mlx5e_encap_put(priv, e);
a54e20b4 3179 return err;
2a4b6526
VB		 3180
3181out_err_init:
3182 mutex_unlock(&esw->offloads.encap_tbl_lock);
3183 kfree(tun_info);
3184 kfree(e);
3185 return err;
a54e20b4
HHZ		 3186}
3187
1482bd3d 3188static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3189 const struct flow_action_entry *act,
1482bd3d
JL		 3190 struct mlx5_esw_flow_attr *attr,
3191 u32 *action)
3192{
cc495188
JL		 3193 u8 vlan_idx = attr->total_vlan;
3194
3195 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3196 return -EOPNOTSUPP;
3197
73867881
PNA		 3198 switch (act->id) {
3199 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3200 if (vlan_idx) {
3201 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3202 MLX5_FS_VLAN_DEPTH))
3203 return -EOPNOTSUPP;
3204
3205 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3206 } else {
3207 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3208 }
73867881
PNA		 3209 break;
3210 case FLOW_ACTION_VLAN_PUSH:
3211 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3212 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3213 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3214 if (!attr->vlan_proto[vlan_idx])
3215 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3216
3217 if (vlan_idx) {
3218 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3219 MLX5_FS_VLAN_DEPTH))
3220 return -EOPNOTSUPP;
3221
3222 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3223 } else {
3224 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3225 (act->vlan.proto != htons(ETH_P_8021Q) ||
3226 act->vlan.prio))
cc495188
JL		 3227 return -EOPNOTSUPP;
3228
3229 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3230 }
73867881
PNA		 3231 break;
3232 default:
bdc837ee 3233 return -EINVAL;
1482bd3d
JL		 3234 }
3235
cc495188
JL		 3236 attr->total_vlan = vlan_idx + 1;
3237
1482bd3d
JL		 3238 return 0;
3239}
3240
278748a9
EB		 3241static int add_vlan_push_action(struct mlx5e_priv *priv,
3242 struct mlx5_esw_flow_attr *attr,
3243 struct net_device **out_dev,
3244 u32 *action)
3245{
3246 struct net_device *vlan_dev = *out_dev;
3247 struct flow_action_entry vlan_act = {
3248 .id = FLOW_ACTION_VLAN_PUSH,
3249 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3250 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3251 .vlan.prio = 0,
3252 };
3253 int err;
3254
3255 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3256 if (err)
3257 return err;
3258
3259 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3260 dev_get_iflink(vlan_dev));
3261 if (is_vlan_dev(*out_dev))
3262 err = add_vlan_push_action(priv, attr, out_dev, action);
3263
3264 return err;
3265}
3266
35a605db
EB		 3267static int add_vlan_pop_action(struct mlx5e_priv *priv,
3268 struct mlx5_esw_flow_attr *attr,
3269 u32 *action)
3270{
f3b0a18b 3271 int nest_level = attr->parse_attr->filter_dev->lower_level;
35a605db
EB		 3272 struct flow_action_entry vlan_act = {
3273 .id = FLOW_ACTION_VLAN_POP,
3274 };
3275 int err = 0;
3276
3277 while (nest_level--) {
3278 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3279 if (err)
3280 return err;
3281 }
3282
3283 return err;
3284}
3285
f6dc1264
PB		 3286bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3287 struct net_device *out_dev)
3288{
3289 if (is_merged_eswitch_dev(priv, out_dev))
3290 return true;
3291
3292 return mlx5e_eswitch_rep(out_dev) &&
3293 same_hw_devs(priv, netdev_priv(out_dev));
3294}
3295
554fe75c
DL		 3296static bool is_duplicated_output_device(struct net_device *dev,
3297 struct net_device *out_dev,
3298 int *ifindexes, int if_count,
3299 struct netlink_ext_ack *extack)
3300{
3301 int i;
3302
3303 for (i = 0; i < if_count; i++) {
3304 if (ifindexes[i] == out_dev->ifindex) {
3305 NL_SET_ERR_MSG_MOD(extack,
3306 "can't duplicate output to same device");
3307 netdev_err(dev, "can't duplicate output to same device: %s\n",
3308 out_dev->name);
3309 return true;
3310 }
3311 }
3312
3313 return false;
3314}
3315
73867881
PNA		 3316static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3317 struct flow_action *flow_action,
e98bedf5
EB		 3318 struct mlx5e_tc_flow *flow,
3319 struct netlink_ext_ack *extack)
03a9d11e 3320{
73867881 3321 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3322 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3323 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3324 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3325 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3326 const struct ip_tunnel_info *info = NULL;
554fe75c 3327 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3328 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3329 const struct flow_action_entry *act;
554fe75c 3330 int err, i, if_count = 0;
a54e20b4 3331 bool encap = false;
1cab1cd7 3332 u32 action = 0;
03a9d11e 3333
73867881 3334 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3335 return -EINVAL;
3336
73867881
PNA		 3337 flow_action_for_each(i, act, flow_action) {
3338 switch (act->id) {
3339 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3340 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3341 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3342 break;
3343 case FLOW_ACTION_MANGLE:
3344 case FLOW_ACTION_ADD:
3345 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 3346 parse_attr, hdrs, extack);
d7e75a32
OG		 3347 if (err)
3348 return err;
3349
1cab1cd7 3350 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 3351 attr->split_count = attr->out_count;
73867881
PNA		 3352 break;
3353 case FLOW_ACTION_CSUM:
1cab1cd7 3354 if (csum_offload_supported(priv, action,
73867881
PNA		 3355 act->csum_flags, extack))
3356 break;
26c02749
OG		 3357
3358 return -EOPNOTSUPP;
73867881
PNA		 3359 case FLOW_ACTION_REDIRECT:
3360 case FLOW_ACTION_MIRRED: {
03a9d11e 3361 struct mlx5e_priv *out_priv;
592d3651 3362 struct net_device *out_dev;
03a9d11e 3363
73867881 3364 out_dev = act->dev;
ef381359
OS		 3365 if (!out_dev) {
3366 /* out_dev is NULL when filters with
3367 * non-existing mirred device are replayed to
3368 * the driver.
3369 */
3370 return -EINVAL;
3371 }
03a9d11e 3372
84179981
PB		 3373 if (ft_flow && out_dev == priv->netdev) {
3374 /* Ignore forward to self rules generated
3375 * by adding both mlx5 devs to the flow table
3376 * block on a normal nft offload setup.
3377 */
3378 return -EOPNOTSUPP;
3379 }
3380
592d3651 3381 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3382 NL_SET_ERR_MSG_MOD(extack,
3383 "can't support more output ports, can't offload forwarding");
592d3651
CM		 3384 pr_err("can't support more than %d output ports, can't offload forwarding\n",
3385 attr->out_count);
3386 return -EOPNOTSUPP;
3387 }
3388
f493f155
EB		 3389 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3390 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 3391 if (encap) {
3392 parse_attr->mirred_ifindex[attr->out_count] =
3393 out_dev->ifindex;
3394 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3395 if (!parse_attr->tun_info[attr->out_count])
3396 return -ENOMEM;
3397 encap = false;
3398 attr->dests[attr->out_count].flags |=
3399 MLX5_ESW_DEST_ENCAP;
3400 attr->out_count++;
3401 /* attr->dests[].rep is resolved when we
3402 * handle encap
3403 */
3404 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3405 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3406 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3407 struct net_device *uplink_upper;
7ba58ba7 3408
554fe75c
DL		 3409 if (is_duplicated_output_device(priv->netdev,
3410 out_dev,
3411 ifindexes,
3412 if_count,
3413 extack))
3414 return -EOPNOTSUPP;
3415
3416 ifindexes[if_count] = out_dev->ifindex;
3417 if_count++;
3418
fa833bd5
VB		 3419 rcu_read_lock();
3420 uplink_upper =
3421 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3422 if (uplink_upper &&
3423 netif_is_lag_master(uplink_upper) &&
3424 uplink_upper == out_dev)
3425 out_dev = uplink_dev;
fa833bd5 3426 rcu_read_unlock();
7ba58ba7 3427
278748a9
EB		 3428 if (is_vlan_dev(out_dev)) {
3429 err = add_vlan_push_action(priv, attr,
3430 &out_dev,
3431 &action);
3432 if (err)
3433 return err;
3434 }
f6dc1264 3435
35a605db
EB		 3436 if (is_vlan_dev(parse_attr->filter_dev)) {
3437 err = add_vlan_pop_action(priv, attr,
3438 &action);
3439 if (err)
3440 return err;
3441 }
278748a9 3442
f6dc1264
PB		 3443 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3444 NL_SET_ERR_MSG_MOD(extack,
3445 "devices are not on same switch HW, can't offload forwarding");
3446 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3447 priv->netdev->name, out_dev->name);
a0646c88 3448 return -EOPNOTSUPP;
f6dc1264 3449 }
a0646c88 3450
a54e20b4 3451 out_priv = netdev_priv(out_dev);
1d447a39 3452 rpriv = out_priv->ppriv;
df65a573
EB		 3453 attr->dests[attr->out_count].rep = rpriv->rep;
3454 attr->dests[attr->out_count].mdev = out_priv->mdev;
3455 attr->out_count++;
ef381359
OS		 3456 } else if (parse_attr->filter_dev != priv->netdev) {
3457 /* All mlx5 devices are called to configure
3458 * high level device filters. Therefore, the
3459 * *attempt* to install a filter on invalid
3460 * eswitch should not trigger an explicit error
3461 */
3462 return -EINVAL;
a54e20b4 3463 } else {
e98bedf5
EB		 3464 NL_SET_ERR_MSG_MOD(extack,
3465 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 3466 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3467 priv->netdev->name, out_dev->name);
3468 return -EINVAL;
3469 }
73867881
PNA		 3470 }
3471 break;
3472 case FLOW_ACTION_TUNNEL_ENCAP:
3473 info = act->tunnel;
a54e20b4
HHZ		 3474 if (info)
3475 encap = true;
3476 else
3477 return -EOPNOTSUPP;
1482bd3d 3478
73867881
PNA		 3479 break;
3480 case FLOW_ACTION_VLAN_PUSH:
3481 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3482 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3483 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3484 /* Replace vlan pop+push with vlan modify */
3485 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3486 err = add_vlan_rewrite_action(priv,
3487 MLX5_FLOW_NAMESPACE_FDB,
3488 act, parse_attr, hdrs,
3489 &action, extack);
3490 } else {
3491 err = parse_tc_vlan_action(priv, act, attr, &action);
3492 }
1482bd3d
JL		 3493 if (err)
3494 return err;
3495
bdc837ee
EB		 3496 attr->split_count = attr->out_count;
3497 break;
3498 case FLOW_ACTION_VLAN_MANGLE:
3499 err = add_vlan_rewrite_action(priv,
3500 MLX5_FLOW_NAMESPACE_FDB,
3501 act, parse_attr, hdrs,
3502 &action, extack);
3503 if (err)
3504 return err;
3505
e85e02ba 3506 attr->split_count = attr->out_count;
73867881
PNA		 3507 break;
3508 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 3509 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 3510 break;
3511 case FLOW_ACTION_GOTO: {
3512 u32 dest_chain = act->chain_index;
39ac237c 3513 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
bf07aa73 3514
84179981
PB		 3515 if (ft_flow) {
3516 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3517 return -EOPNOTSUPP;
3518 }
bf07aa73
PB		 3519 if (dest_chain <= attr->chain) {
3520 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3521 return -EOPNOTSUPP;
3522 }
3523 if (dest_chain > max_chain) {
3524 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3525 return -EOPNOTSUPP;
3526 }
e88afe75 3527 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 3528 attr->dest_chain = dest_chain;
73867881
PNA		 3529 break;
3530 }
3531 default:
2cc1cb1d
TZ		 3532 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3533 return -EOPNOTSUPP;
bf07aa73 3534 }
03a9d11e 3535 }
bdd66ac0 3536
0bac1194
EB		 3537 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3538 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3539 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3540 * tag rewrite.
3541 */
3542 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3543 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3544 &action, extack);
3545 if (err)
3546 return err;
3547 }
3548
c500c86b
PNA		 3549 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3550 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3551 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3552 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3553 if (err)
3554 return err;
27c11b6b
EB		 3555 /* in case all pedit actions are skipped, remove the MOD_HDR
3556 * flag. we might have set split_count either by pedit or
3557 * pop/push. if there is no pop/push either, reset it too.
3558 */
3559 if (parse_attr->num_mod_hdr_actions == 0) {
3560 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3561 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3562 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3563 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3564 attr->split_count = 0;
3565 }
c500c86b
PNA		 3566 }
3567
1cab1cd7 3568 attr->action = action;
73867881 3569 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3570 return -EOPNOTSUPP;
3571
e88afe75
OG		 3572 if (attr->dest_chain) {
3573 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3574 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3575 return -EOPNOTSUPP;
3576 }
3577 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3578 }
3579
ae2741e2
VB		 3580 if (!(attr->action &
3581 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3582 NL_SET_ERR_MSG(extack, "Rule must have at least one forward/drop action");
3583 return -EOPNOTSUPP;
3584 }
3585
e85e02ba 3586 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3587 NL_SET_ERR_MSG_MOD(extack,
3588 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3589 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3590 return -EOPNOTSUPP;
3591 }
3592
31c8eba5 3593 return 0;
03a9d11e
OG		 3594}
3595
226f2ca3 3596static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3597{
226f2ca3 3598 unsigned long __flow_flags = 0;
60bd4af8 3599
226f2ca3
VB		 3600 if (flags & MLX5_TC_FLAG(INGRESS))
3601 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3602 if (flags & MLX5_TC_FLAG(EGRESS))
3603 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3604
226f2ca3
VB		 3605 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3606 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3607 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3608 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3609 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3610 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3611
60bd4af8
OG		 3612 *flow_flags = __flow_flags;
3613}
3614
05866c82
OG		 3615static const struct rhashtable_params tc_ht_params = {
3616 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3617 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3618 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3619 .automatic_shrinking = true,
3620};
3621
226f2ca3
VB		 3622static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3623 unsigned long flags)
05866c82 3624{
655dc3d2
OG		 3625 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3626 struct mlx5e_rep_priv *uplink_rpriv;
3627
226f2ca3 3628 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3629 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3630 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3631 } else /* NIC offload */
655dc3d2 3632 return &priv->fs.tc.ht;
05866c82
OG		 3633}
3634
04de7dda
RD		 3635static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3636{
1418ddd9 3637 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3638 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3639 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3640 bool act_is_encap = !!(attr->action &
3641 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3642 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3643 MLX5_DEVCOM_ESW_OFFLOADS);
3644
10fbb1cd
RD		 3645 if (!esw_paired)
3646 return false;
3647
3648 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3649 mlx5_lag_is_multipath(attr->in_mdev)) &&
3650 (is_rep_ingress || act_is_encap))
3651 return true;
3652
3653 return false;
04de7dda
RD		 3654}
3655
a88780a9
RD		 3656static int
3657mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3658 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3659 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3660 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3661{
17091853 3662 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3663 struct mlx5e_tc_flow *flow;
5a7e5bcb 3664 int out_index, err;
e3a2b7ed 3665
65ba8fb7 3666 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3667 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3668 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3669 err = -ENOMEM;
3670 goto err_free;
3671 }
3672
3673 flow->cookie = f->cookie;
65ba8fb7 3674 flow->flags = flow_flags;
655dc3d2 3675 flow->priv = priv;
5a7e5bcb
VB		 3676 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3677 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3678 INIT_LIST_HEAD(&flow->mod_hdr);
3679 INIT_LIST_HEAD(&flow->hairpin);
3680 refcount_set(&flow->refcnt, 1);
95435ad7 3681 init_completion(&flow->init_done);
e3a2b7ed 3682
a88780a9
RD		 3683 *__flow = flow;
3684 *__parse_attr = parse_attr;
3685
3686 return 0;
3687
3688err_free:
3689 kfree(flow);
3690 kvfree(parse_attr);
3691 return err;
3692}
3693
988ab9c7
TZ		 3694static void
3695mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3696 struct mlx5e_priv *priv,
3697 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3698 struct flow_cls_offload *f,
988ab9c7
TZ		 3699 struct mlx5_eswitch_rep *in_rep,
3700 struct mlx5_core_dev *in_mdev)
3701{
3702 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3703
3704 esw_attr->parse_attr = parse_attr;
3705 esw_attr->chain = f->common.chain_index;
ef01adae 3706 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 3707
3708 esw_attr->in_rep = in_rep;
3709 esw_attr->in_mdev = in_mdev;
3710
3711 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3712 MLX5_COUNTER_SOURCE_ESWITCH)
3713 esw_attr->counter_dev = in_mdev;
3714 else
3715 esw_attr->counter_dev = priv->mdev;
3716}
3717
71129676 3718static struct mlx5e_tc_flow *
04de7dda 3719__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3720 struct flow_cls_offload *f,
226f2ca3 3721 unsigned long flow_flags,
04de7dda
RD		 3722 struct net_device *filter_dev,
3723 struct mlx5_eswitch_rep *in_rep,
71129676 3724 struct mlx5_core_dev *in_mdev)
a88780a9 3725{
f9e30088 3726 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3727 struct netlink_ext_ack *extack = f->common.extack;
3728 struct mlx5e_tc_flow_parse_attr *parse_attr;
3729 struct mlx5e_tc_flow *flow;
3730 int attr_size, err;
e3a2b7ed 3731
226f2ca3 3732 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3733 attr_size = sizeof(struct mlx5_esw_flow_attr);
3734 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3735 &parse_attr, &flow);
3736 if (err)
3737 goto out;
988ab9c7 3738
d11afc26 3739 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3740 mlx5e_flow_esw_attr_init(flow->esw_attr,
3741 priv, parse_attr,
3742 f, in_rep, in_mdev);
3743
54c177ca
OS		 3744 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3745 f, filter_dev);
d11afc26
OS		 3746 if (err)
3747 goto err_free;
a88780a9 3748
6f9af8ff 3749 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3750 if (err)
3751 goto err_free;
3752
7040632d 3753 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 3754 complete_all(&flow->init_done);
ef06c9ee
RD		 3755 if (err) {
3756 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3757 goto err_free;
3758
b4a23329 3759 add_unready_flow(flow);
ef06c9ee 3760 }
e3a2b7ed 3761
71129676 3762 return flow;
a88780a9
RD		 3763
3764err_free:
5a7e5bcb 3765 mlx5e_flow_put(priv, flow);
a88780a9 3766out:
71129676 3767 return ERR_PTR(err);
a88780a9
RD		 3768}
3769
f9e30088 3770static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3771 struct mlx5e_tc_flow *flow,
226f2ca3 3772 unsigned long flow_flags)
04de7dda
RD		 3773{
3774 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3775 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3776 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3777 struct mlx5e_tc_flow_parse_attr *parse_attr;
3778 struct mlx5e_rep_priv *peer_urpriv;
3779 struct mlx5e_tc_flow *peer_flow;
3780 struct mlx5_core_dev *in_mdev;
3781 int err = 0;
3782
3783 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3784 if (!peer_esw)
3785 return -ENODEV;
3786
3787 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3788 peer_priv = netdev_priv(peer_urpriv->netdev);
3789
3790 /* in_mdev is assigned of which the packet originated from.
3791 * So packets redirected to uplink use the same mdev of the
3792 * original flow and packets redirected from uplink use the
3793 * peer mdev.
3794 */
b05af6aa 3795 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3796 in_mdev = peer_priv->mdev;
3797 else
3798 in_mdev = priv->mdev;
3799
3800 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3801 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3802 parse_attr->filter_dev,
3803 flow->esw_attr->in_rep, in_mdev);
3804 if (IS_ERR(peer_flow)) {
3805 err = PTR_ERR(peer_flow);
04de7dda 3806 goto out;
71129676 3807 }
04de7dda
RD		 3808
3809 flow->peer_flow = peer_flow;
226f2ca3 3810 flow_flag_set(flow, DUP);
04de7dda
RD		 3811 mutex_lock(&esw->offloads.peer_mutex);
3812 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3813 mutex_unlock(&esw->offloads.peer_mutex);
3814
3815out:
3816 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3817 return err;
3818}
3819
3820static int
3821mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3822 struct flow_cls_offload *f,
226f2ca3 3823 unsigned long flow_flags,
04de7dda
RD		 3824 struct net_device *filter_dev,
3825 struct mlx5e_tc_flow **__flow)
3826{
3827 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3828 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3829 struct mlx5_core_dev *in_mdev = priv->mdev;
3830 struct mlx5e_tc_flow *flow;
3831 int err;
3832
71129676
JG		 3833 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3834 in_mdev);
3835 if (IS_ERR(flow))
3836 return PTR_ERR(flow);
04de7dda
RD		 3837
3838 if (is_peer_flow_needed(flow)) {
95dc1902 3839 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3840 if (err) {
3841 mlx5e_tc_del_fdb_flow(priv, flow);
3842 goto out;
3843 }
3844 }
3845
3846 *__flow = flow;
3847
3848 return 0;
3849
3850out:
3851 return err;
3852}
3853
a88780a9
RD		 3854static int
3855mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3856 struct flow_cls_offload *f,
226f2ca3 3857 unsigned long flow_flags,
d11afc26 3858 struct net_device *filter_dev,
a88780a9
RD		 3859 struct mlx5e_tc_flow **__flow)
3860{
f9e30088 3861 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3862 struct netlink_ext_ack *extack = f->common.extack;
3863 struct mlx5e_tc_flow_parse_attr *parse_attr;
3864 struct mlx5e_tc_flow *flow;
3865 int attr_size, err;
3866
bf07aa73
PB		 3867 /* multi-chain not supported for NIC rules */
3868 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3869 return -EOPNOTSUPP;
3870
226f2ca3 3871 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3872 attr_size = sizeof(struct mlx5_nic_flow_attr);
3873 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3874 &parse_attr, &flow);
3875 if (err)
3876 goto out;
3877
d11afc26 3878 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3879 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3880 f, filter_dev);
d11afc26
OS		 3881 if (err)
3882 goto err_free;
3883
73867881 3884 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3885 if (err)
3886 goto err_free;
3887
3888 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3889 if (err)
3890 goto err_free;
3891
226f2ca3 3892 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3893 kvfree(parse_attr);
3894 *__flow = flow;
3895
3896 return 0;
e3a2b7ed 3897
e3a2b7ed 3898err_free:
5a7e5bcb 3899 mlx5e_flow_put(priv, flow);
17091853 3900 kvfree(parse_attr);
a88780a9
RD		 3901out:
3902 return err;
3903}
3904
3905static int
3906mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3907 struct flow_cls_offload *f,
226f2ca3 3908 unsigned long flags,
d11afc26 3909 struct net_device *filter_dev,
a88780a9
RD		 3910 struct mlx5e_tc_flow **flow)
3911{
3912 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3913 unsigned long flow_flags;
a88780a9
RD		 3914 int err;
3915
3916 get_flags(flags, &flow_flags);
3917
bf07aa73
PB		 3918 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3919 return -EOPNOTSUPP;
3920
f6455de0 3921 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3922 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3923 filter_dev, flow);
a88780a9 3924 else
d11afc26
OS		 3925 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3926 filter_dev, flow);
a88780a9
RD		 3927
3928 return err;
3929}
3930
71d82d2a 3931int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3932 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3933{
3934 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3935 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3936 struct mlx5e_tc_flow *flow;
3937 int err = 0;
3938
c5d326b2
VB		 3939 rcu_read_lock();
3940 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3941 rcu_read_unlock();
a88780a9
RD		 3942 if (flow) {
3943 NL_SET_ERR_MSG_MOD(extack,
3944 "flow cookie already exists, ignoring");
3945 netdev_warn_once(priv->netdev,
3946 "flow cookie %lx already exists, ignoring\n",
3947 f->cookie);
0e1c1a2f 3948 err = -EEXIST;
a88780a9
RD		 3949 goto out;
3950 }
3951
7a978759 3952 trace_mlx5e_configure_flower(f);
d11afc26 3953 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3954 if (err)
3955 goto out;
3956
c5d326b2 3957 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3958 if (err)
3959 goto err_free;
3960
3961 return 0;
3962
3963err_free:
5a7e5bcb 3964 mlx5e_flow_put(priv, flow);
a88780a9 3965out:
e3a2b7ed
AV		 3966 return err;
3967}
3968
8f8ae895
OG		 3969static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3970{
226f2ca3
VB		 3971 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3972 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 3973
226f2ca3
VB		 3974 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3975 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 3976}
3977
71d82d2a 3978int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3979 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 3980{
d9ee0491 3981 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3982 struct mlx5e_tc_flow *flow;
c5d326b2 3983 int err;
e3a2b7ed 3984
c5d326b2 3985 rcu_read_lock();
ab818362 3986 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 3987 if (!flow || !same_flow_direction(flow, flags)) {
3988 err = -EINVAL;
3989 goto errout;
3990 }
e3a2b7ed 3991
c5d326b2
VB		 3992 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3993 * set.
3994 */
3995 if (flow_flag_test_and_set(flow, DELETED)) {
3996 err = -EINVAL;
3997 goto errout;
3998 }
05866c82 3999 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4000 rcu_read_unlock();
e3a2b7ed 4001
7a978759 4002 trace_mlx5e_delete_flower(f);
5a7e5bcb 4003 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4004
4005 return 0;
c5d326b2
VB		 4006
4007errout:
4008 rcu_read_unlock();
4009 return err;
e3a2b7ed
AV		 4010}
4011
71d82d2a 4012int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4013 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4014{
04de7dda 4015 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4016 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4017 struct mlx5_eswitch *peer_esw;
aad7e08d 4018 struct mlx5e_tc_flow *flow;
aad7e08d 4019 struct mlx5_fc *counter;
316d5f72
RD		 4020 u64 lastuse = 0;
4021 u64 packets = 0;
4022 u64 bytes = 0;
5a7e5bcb 4023 int err = 0;
aad7e08d 4024
c5d326b2
VB		 4025 rcu_read_lock();
4026 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4027 tc_ht_params));
4028 rcu_read_unlock();
5a7e5bcb
VB		 4029 if (IS_ERR(flow))
4030 return PTR_ERR(flow);
4031
4032 if (!same_flow_direction(flow, flags)) {
4033 err = -EINVAL;
4034 goto errout;
4035 }
aad7e08d 4036
226f2ca3 4037 if (mlx5e_is_offloaded_flow(flow)) {
316d5f72
RD		 4038 counter = mlx5e_tc_get_counter(flow);
4039 if (!counter)
5a7e5bcb 4040 goto errout;
aad7e08d 4041
316d5f72
RD		 4042 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4043 }
aad7e08d 4044
316d5f72
RD		 4045 /* Under multipath it's possible for one rule to be currently
4046 * un-offloaded while the other rule is offloaded.
4047 */
04de7dda
RD		 4048 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4049 if (!peer_esw)
4050 goto out;
4051
226f2ca3
VB		 4052 if (flow_flag_test(flow, DUP) &&
4053 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4054 u64 bytes2;
4055 u64 packets2;
4056 u64 lastuse2;
4057
4058 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4059 if (!counter)
4060 goto no_peer_counter;
04de7dda
RD		 4061 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4062
4063 bytes += bytes2;
4064 packets += packets2;
4065 lastuse = max_t(u64, lastuse, lastuse2);
4066 }
4067
316d5f72 4068no_peer_counter:
04de7dda 4069 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4070out:
3b1903ef 4071 flow_stats_update(&f->stats, bytes, packets, lastuse);
7a978759 4072 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4073errout:
4074 mlx5e_flow_put(priv, flow);
4075 return err;
aad7e08d
AV		 4076}
4077
fcb64c0f
EC		 4078static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4079 struct netlink_ext_ack *extack)
4080{
4081 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4082 struct mlx5_eswitch *esw;
4083 u16 vport_num;
4084 u32 rate_mbps;
4085 int err;
4086
e401a184
EC		 4087 vport_num = rpriv->rep->vport;
4088 if (vport_num >= MLX5_VPORT_ECPF) {
4089 NL_SET_ERR_MSG_MOD(extack,
4090 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4091 return -EOPNOTSUPP;
4092 }
4093
fcb64c0f
EC		 4094 esw = priv->mdev->priv.eswitch;
4095 /* rate is given in bytes/sec.
4096 * First convert to bits/sec and then round to the nearest mbit/secs.
4097 * mbit means million bits.
4098 * Moreover, if rate is non zero we choose to configure to a minimum of
4099 * 1 mbit/sec.
4100 */
4101 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
fcb64c0f
EC		 4102 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4103 if (err)
4104 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4105
4106 return err;
4107}
4108
4109static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4110 struct flow_action *flow_action,
4111 struct netlink_ext_ack *extack)
4112{
4113 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4114 const struct flow_action_entry *act;
4115 int err;
4116 int i;
4117
4118 if (!flow_action_has_entries(flow_action)) {
4119 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4120 return -EINVAL;
4121 }
4122
4123 if (!flow_offload_has_one_action(flow_action)) {
4124 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4125 return -EOPNOTSUPP;
4126 }
4127
4128 flow_action_for_each(i, act, flow_action) {
4129 switch (act->id) {
4130 case FLOW_ACTION_POLICE:
4131 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4132 if (err)
4133 return err;
4134
4135 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4136 break;
4137 default:
4138 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4139 return -EOPNOTSUPP;
4140 }
4141 }
4142
4143 return 0;
4144}
4145
4146int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4147 struct tc_cls_matchall_offload *ma)
4148{
4149 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4150
7b83355f 4151 if (ma->common.prio != 1) {
fcb64c0f
EC		 4152 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4153 return -EINVAL;
4154 }
4155
4156 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4157}
4158
4159int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4160 struct tc_cls_matchall_offload *ma)
4161{
4162 struct netlink_ext_ack *extack = ma->common.extack;
4163
4164 return apply_police_params(priv, 0, extack);
4165}
4166
4167void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4168 struct tc_cls_matchall_offload *ma)
4169{
4170 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4171 struct rtnl_link_stats64 cur_stats;
4172 u64 dbytes;
4173 u64 dpkts;
4174
4175 cur_stats = priv->stats.vf_vport;
4176 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4177 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4178 rpriv->prev_vf_vport_stats = cur_stats;
4179 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4180}
4181
4d8fcf21
AH		 4182static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4183 struct mlx5e_priv *peer_priv)
4184{
4185 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4186 struct mlx5e_hairpin_entry *hpe, *tmp;
4187 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4188 u16 peer_vhca_id;
4189 int bkt;
4190
4191 if (!same_hw_devs(priv, peer_priv))
4192 return;
4193
4194 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4195
b32accda 4196 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4197 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4198 if (refcount_inc_not_zero(&hpe->refcnt))
4199 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4200 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4201
4202 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4203 wait_for_completion(&hpe->res_ready);
4204 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4205 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4206
4207 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4208 }
4209}
4210
4211static int mlx5e_tc_netdev_event(struct notifier_block *this,
4212 unsigned long event, void *ptr)
4213{
4214 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4215 struct mlx5e_flow_steering *fs;
4216 struct mlx5e_priv *peer_priv;
4217 struct mlx5e_tc_table *tc;
4218 struct mlx5e_priv *priv;
4219
4220 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4221 event != NETDEV_UNREGISTER ||
4222 ndev->reg_state == NETREG_REGISTERED)
4223 return NOTIFY_DONE;
4224
4225 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4226 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4227 priv = container_of(fs, struct mlx5e_priv, fs);
4228 peer_priv = netdev_priv(ndev);
4229 if (priv == peer_priv ||
4230 !(priv->netdev->features & NETIF_F_HW_TC))
4231 return NOTIFY_DONE;
4232
4233 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4234
4235 return NOTIFY_DONE;
4236}
4237
655dc3d2 4238int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4239{
acff797c 4240 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4241 int err;
e8f887ac 4242
b6fac0b4 4243 mutex_init(&tc->t_lock);
d2faae25 4244 mutex_init(&tc->mod_hdr.lock);
dd58edc3 4245 hash_init(tc->mod_hdr.hlist);
b32accda 4246 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4247 hash_init(tc->hairpin_tbl);
11c9c548 4248
4d8fcf21
AH		 4249 err = rhashtable_init(&tc->ht, &tc_ht_params);
4250 if (err)
4251 return err;
4252
4253 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4254 err = register_netdevice_notifier_dev_net(priv->netdev,
4255 &tc->netdevice_nb,
4256 &tc->netdevice_nn);
4257 if (err) {
4d8fcf21
AH		 4258 tc->netdevice_nb.notifier_call = NULL;
4259 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4260 }
4261
4262 return err;
e8f887ac
AV		 4263}
4264
4265static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4266{
4267 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4268 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4269
961e8979 4270 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4271 kfree(flow);
4272}
4273
655dc3d2 4274void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4275{
acff797c 4276 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4277
4d8fcf21 4278 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4279 unregister_netdevice_notifier_dev_net(priv->netdev,
4280 &tc->netdevice_nb,
4281 &tc->netdevice_nn);
4d8fcf21 4282
d2faae25 4283 mutex_destroy(&tc->mod_hdr.lock);
b32accda
VB		 4284 mutex_destroy(&tc->hairpin_tbl_lock);
4285
d9ee0491 4286 rhashtable_destroy(&tc->ht);
e8f887ac 4287
acff797c
MG		 4288 if (!IS_ERR_OR_NULL(tc->t)) {
4289 mlx5_destroy_flow_table(tc->t);
4290 tc->t = NULL;
e8f887ac 4291 }
b6fac0b4 4292 mutex_destroy(&tc->t_lock);
e8f887ac 4293}
655dc3d2
OG		 4294
4295int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4296{
4297 return rhashtable_init(tc_ht, &tc_ht_params);
4298}
4299
4300void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4301{
4302 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4303}
01252a27 4304
226f2ca3 4305int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4306{
d9ee0491 4307 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4308
4309 return atomic_read(&tc_ht->nelems);
4310}
04de7dda
RD		 4311
4312void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4313{
4314 struct mlx5e_tc_flow *flow, *tmp;
4315
4316 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4317 __mlx5e_tc_del_fdb_peer_flow(flow);
4318}
b4a23329
RD		 4319
4320void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4321{
4322 struct mlx5_rep_uplink_priv *rpriv =
4323 container_of(work, struct mlx5_rep_uplink_priv,
4324 reoffload_flows_work);
4325 struct mlx5e_tc_flow *flow, *tmp;
4326
ad86755b 4327 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4328 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4329 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4330 unready_flow_del(flow);
b4a23329 4331 }
ad86755b 4332 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4333}
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