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e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e 41#include <net/tc_act/tc_mirred.h>
776b12b6 42#include <net/tc_act/tc_vlan.h>
bbd00f7e 43#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 44#include <net/tc_act/tc_pedit.h>
26c02749 45#include <net/tc_act/tc_csum.h>
f6dfb4c3 46#include <net/arp.h>
3616d08b 47#include <net/ipv6_stubs.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
3f6d08d1 52#include "fs_core.h"
2c81bfd5 53#include "en/port.h"
101f4de9 54#include "en/tc_tun.h"
04de7dda 55#include "lib/devcom.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
d9ee0491
OG		 72 MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD,
73 MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD,
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2),
77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3),
78 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4),
ef06c9ee 79 MLX5E_TC_FLOW_NOT_READY = BIT(MLX5E_TC_FLOW_BASE + 5),
65ba8fb7
OG		 80};
81
e4ad91f2
CM		 82#define MLX5E_TC_MAX_SPLITS 1
83
79baaec7
EB		 84/* Helper struct for accessing a struct containing list_head array.
85 * Containing struct
86 * |- Helper array
87 * [0] Helper item 0
88 * |- list_head item 0
89 * |- index (0)
90 * [1] Helper item 1
91 * |- list_head item 1
92 * |- index (1)
93 * To access the containing struct from one of the list_head items:
94 * 1. Get the helper item from the list_head item using
95 * helper item =
96 * container_of(list_head item, helper struct type, list_head field)
97 * 2. Get the contining struct from the helper item and its index in the array:
98 * containing struct =
99 * container_of(helper item, containing struct type, helper field[index])
100 */
101struct encap_flow_item {
102 struct list_head list;
103 int index;
104};
105
e8f887ac
AV		 106struct mlx5e_tc_flow {
107 struct rhash_head node;
655dc3d2 108 struct mlx5e_priv *priv;
e8f887ac 109 u64 cookie;
5dbe906f 110 u16 flags;
e4ad91f2 111 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 112 /* Flow can be associated with multiple encap IDs.
113 * The number of encaps is bounded by the number of supported
114 * destinations.
115 */
116 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 117 struct mlx5e_tc_flow *peer_flow;
11c9c548 118 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 119 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 120 struct list_head peer; /* flows with peer flow */
b4a23329 121 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
3bc4b7bf
OG		 122 union {
123 struct mlx5_esw_flow_attr esw_attr[0];
124 struct mlx5_nic_flow_attr nic_attr[0];
125 };
e8f887ac
AV		 126};
127
17091853 128struct mlx5e_tc_flow_parse_attr {
98b66cb1 129 struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 130 struct net_device *filter_dev;
17091853 131 struct mlx5_flow_spec spec;
d79b6df6 132 int num_mod_hdr_actions;
218d05ce 133 int max_mod_hdr_actions;
d79b6df6 134 void *mod_hdr_actions;
98b66cb1 135 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 136};
137
acff797c 138#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 139#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 140
77ab67b7
OG		 141struct mlx5e_hairpin {
142 struct mlx5_hairpin *pair;
143
144 struct mlx5_core_dev *func_mdev;
3f6d08d1 145 struct mlx5e_priv *func_priv;
77ab67b7
OG		 146 u32 tdn;
147 u32 tirn;
3f6d08d1
OG		 148
149 int num_channels;
150 struct mlx5e_rqt indir_rqt;
151 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
152 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 153};
154
5c65c564
OG		 155struct mlx5e_hairpin_entry {
156 /* a node of a hash table which keeps all the hairpin entries */
157 struct hlist_node hairpin_hlist;
158
159 /* flows sharing the same hairpin */
160 struct list_head flows;
161
d8822868 162 u16 peer_vhca_id;
106be53b 163 u8 prio;
5c65c564
OG		 164 struct mlx5e_hairpin *hp;
165};
166
11c9c548
OG		 167struct mod_hdr_key {
168 int num_actions;
169 void *actions;
170};
171
172struct mlx5e_mod_hdr_entry {
173 /* a node of a hash table which keeps all the mod_hdr entries */
174 struct hlist_node mod_hdr_hlist;
175
176 /* flows sharing the same mod_hdr entry */
177 struct list_head flows;
178
179 struct mod_hdr_key key;
180
181 u32 mod_hdr_id;
182};
183
184#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
185
186static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
187{
188 return jhash(key->actions,
189 key->num_actions * MLX5_MH_ACT_SZ, 0);
190}
191
192static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
193 struct mod_hdr_key *b)
194{
195 if (a->num_actions != b->num_actions)
196 return 1;
197
198 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
199}
200
201static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
202 struct mlx5e_tc_flow *flow,
203 struct mlx5e_tc_flow_parse_attr *parse_attr)
204{
205 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
206 int num_actions, actions_size, namespace, err;
207 struct mlx5e_mod_hdr_entry *mh;
208 struct mod_hdr_key key;
209 bool found = false;
210 u32 hash_key;
211
212 num_actions = parse_attr->num_mod_hdr_actions;
213 actions_size = MLX5_MH_ACT_SZ * num_actions;
214
215 key.actions = parse_attr->mod_hdr_actions;
216 key.num_actions = num_actions;
217
218 hash_key = hash_mod_hdr_info(&key);
219
220 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
221 namespace = MLX5_FLOW_NAMESPACE_FDB;
222 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
223 mod_hdr_hlist, hash_key) {
224 if (!cmp_mod_hdr_info(&mh->key, &key)) {
225 found = true;
226 break;
227 }
228 }
229 } else {
230 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
231 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
232 mod_hdr_hlist, hash_key) {
233 if (!cmp_mod_hdr_info(&mh->key, &key)) {
234 found = true;
235 break;
236 }
237 }
238 }
239
240 if (found)
241 goto attach_flow;
242
243 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
244 if (!mh)
245 return -ENOMEM;
246
247 mh->key.actions = (void *)mh + sizeof(*mh);
248 memcpy(mh->key.actions, key.actions, actions_size);
249 mh->key.num_actions = num_actions;
250 INIT_LIST_HEAD(&mh->flows);
251
252 err = mlx5_modify_header_alloc(priv->mdev, namespace,
253 mh->key.num_actions,
254 mh->key.actions,
255 &mh->mod_hdr_id);
256 if (err)
257 goto out_err;
258
259 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
260 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
261 else
262 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
263
264attach_flow:
265 list_add(&flow->mod_hdr, &mh->flows);
266 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
267 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
268 else
269 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
270
271 return 0;
272
273out_err:
274 kfree(mh);
275 return err;
276}
277
278static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
279 struct mlx5e_tc_flow *flow)
280{
281 struct list_head *next = flow->mod_hdr.next;
282
283 list_del(&flow->mod_hdr);
284
285 if (list_empty(next)) {
286 struct mlx5e_mod_hdr_entry *mh;
287
288 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
289
290 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
291 hash_del(&mh->mod_hdr_hlist);
292 kfree(mh);
293 }
294}
295
77ab67b7
OG		 296static
297struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
298{
299 struct net_device *netdev;
300 struct mlx5e_priv *priv;
301
302 netdev = __dev_get_by_index(net, ifindex);
303 priv = netdev_priv(netdev);
304 return priv->mdev;
305}
306
307static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
308{
309 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
310 void *tirc;
311 int err;
312
313 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
314 if (err)
315 goto alloc_tdn_err;
316
317 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
318
319 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 320 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 321 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
322
323 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
324 if (err)
325 goto create_tir_err;
326
327 return 0;
328
329create_tir_err:
330 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
331alloc_tdn_err:
332 return err;
333}
334
335static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
336{
337 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
338 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
339}
340
3f6d08d1
OG		 341static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
342{
343 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
344 struct mlx5e_priv *priv = hp->func_priv;
345 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
346
347 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
348 hp->num_channels);
349
350 for (i = 0; i < sz; i++) {
351 ix = i;
bbeb53b8 352 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 353 ix = mlx5e_bits_invert(i, ilog2(sz));
354 ix = indirection_rqt[ix];
355 rqn = hp->pair->rqn[ix];
356 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
357 }
358}
359
360static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
361{
362 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
363 struct mlx5e_priv *priv = hp->func_priv;
364 struct mlx5_core_dev *mdev = priv->mdev;
365 void *rqtc;
366 u32 *in;
367
368 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
369 in = kvzalloc(inlen, GFP_KERNEL);
370 if (!in)
371 return -ENOMEM;
372
373 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
374
375 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
376 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
377
378 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
379
380 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
381 if (!err)
382 hp->indir_rqt.enabled = true;
383
384 kvfree(in);
385 return err;
386}
387
388static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
389{
390 struct mlx5e_priv *priv = hp->func_priv;
391 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
392 int tt, i, err;
393 void *tirc;
394
395 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 396 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
397
3f6d08d1
OG		 398 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
399 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
400
401 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
402 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
403 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 404 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
405
3f6d08d1
OG		 406 err = mlx5_core_create_tir(hp->func_mdev, in,
407 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
408 if (err) {
409 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
410 goto err_destroy_tirs;
411 }
412 }
413 return 0;
414
415err_destroy_tirs:
416 for (i = 0; i < tt; i++)
417 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
418 return err;
419}
420
421static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
422{
423 int tt;
424
425 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
426 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
427}
428
429static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
430 struct ttc_params *ttc_params)
431{
432 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
433 int tt;
434
435 memset(ttc_params, 0, sizeof(*ttc_params));
436
437 ttc_params->any_tt_tirn = hp->tirn;
438
439 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
440 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
441
442 ft_attr->max_fte = MLX5E_NUM_TT;
443 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
444 ft_attr->prio = MLX5E_TC_PRIO;
445}
446
447static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
448{
449 struct mlx5e_priv *priv = hp->func_priv;
450 struct ttc_params ttc_params;
451 int err;
452
453 err = mlx5e_hairpin_create_indirect_rqt(hp);
454 if (err)
455 return err;
456
457 err = mlx5e_hairpin_create_indirect_tirs(hp);
458 if (err)
459 goto err_create_indirect_tirs;
460
461 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
462 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
463 if (err)
464 goto err_create_ttc_table;
465
466 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
467 hp->num_channels, hp->ttc.ft.t->id);
468
469 return 0;
470
471err_create_ttc_table:
472 mlx5e_hairpin_destroy_indirect_tirs(hp);
473err_create_indirect_tirs:
474 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
475
476 return err;
477}
478
479static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
480{
481 struct mlx5e_priv *priv = hp->func_priv;
482
483 mlx5e_destroy_ttc_table(priv, &hp->ttc);
484 mlx5e_hairpin_destroy_indirect_tirs(hp);
485 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
486}
487
77ab67b7
OG		 488static struct mlx5e_hairpin *
489mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
490 int peer_ifindex)
491{
492 struct mlx5_core_dev *func_mdev, *peer_mdev;
493 struct mlx5e_hairpin *hp;
494 struct mlx5_hairpin *pair;
495 int err;
496
497 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
498 if (!hp)
499 return ERR_PTR(-ENOMEM);
500
501 func_mdev = priv->mdev;
502 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
503
504 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
505 if (IS_ERR(pair)) {
506 err = PTR_ERR(pair);
507 goto create_pair_err;
508 }
509 hp->pair = pair;
510 hp->func_mdev = func_mdev;
3f6d08d1
OG		 511 hp->func_priv = priv;
512 hp->num_channels = params->num_channels;
77ab67b7
OG		 513
514 err = mlx5e_hairpin_create_transport(hp);
515 if (err)
516 goto create_transport_err;
517
3f6d08d1
OG		 518 if (hp->num_channels > 1) {
519 err = mlx5e_hairpin_rss_init(hp);
520 if (err)
521 goto rss_init_err;
522 }
523
77ab67b7
OG		 524 return hp;
525
3f6d08d1
OG		 526rss_init_err:
527 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 528create_transport_err:
529 mlx5_core_hairpin_destroy(hp->pair);
530create_pair_err:
531 kfree(hp);
532 return ERR_PTR(err);
533}
534
535static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
536{
3f6d08d1
OG		 537 if (hp->num_channels > 1)
538 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 539 mlx5e_hairpin_destroy_transport(hp);
540 mlx5_core_hairpin_destroy(hp->pair);
541 kvfree(hp);
542}
543
106be53b
OG		 544static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
545{
546 return (peer_vhca_id << 16 | prio);
547}
548
5c65c564 549static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 550 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 551{
552 struct mlx5e_hairpin_entry *hpe;
106be53b 553 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 554
555 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 556 hairpin_hlist, hash_key) {
557 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 558 return hpe;
559 }
560
561 return NULL;
562}
563
106be53b
OG		 564#define UNKNOWN_MATCH_PRIO 8
565
566static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 567 struct mlx5_flow_spec *spec, u8 *match_prio,
568 struct netlink_ext_ack *extack)
106be53b
OG		 569{
570 void *headers_c, *headers_v;
571 u8 prio_val, prio_mask = 0;
572 bool vlan_present;
573
574#ifdef CONFIG_MLX5_CORE_EN_DCB
575 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 576 NL_SET_ERR_MSG_MOD(extack,
577 "only PCP trust state supported for hairpin");
106be53b
OG		 578 return -EOPNOTSUPP;
579 }
580#endif
581 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
582 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
583
584 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
585 if (vlan_present) {
586 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
587 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
588 }
589
590 if (!vlan_present || !prio_mask) {
591 prio_val = UNKNOWN_MATCH_PRIO;
592 } else if (prio_mask != 0x7) {
e98bedf5
EB		 593 NL_SET_ERR_MSG_MOD(extack,
594 "masked priority match not supported for hairpin");
106be53b
OG		 595 return -EOPNOTSUPP;
596 }
597
598 *match_prio = prio_val;
599 return 0;
600}
601
5c65c564
OG		 602static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
603 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 604 struct mlx5e_tc_flow_parse_attr *parse_attr,
605 struct netlink_ext_ack *extack)
5c65c564 606{
98b66cb1 607 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 608 struct mlx5_hairpin_params params;
d8822868 609 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 610 struct mlx5e_hairpin_entry *hpe;
611 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 612 u64 link_speed64;
613 u32 link_speed;
106be53b 614 u8 match_prio;
d8822868 615 u16 peer_id;
5c65c564
OG		 616 int err;
617
d8822868
OG		 618 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
619 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 620 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 621 return -EOPNOTSUPP;
622 }
623
d8822868 624 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 625 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
626 extack);
106be53b
OG		 627 if (err)
628 return err;
629 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 630 if (hpe)
631 goto attach_flow;
632
633 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
634 if (!hpe)
635 return -ENOMEM;
636
637 INIT_LIST_HEAD(&hpe->flows);
d8822868 638 hpe->peer_vhca_id = peer_id;
106be53b 639 hpe->prio = match_prio;
5c65c564
OG		 640
641 params.log_data_size = 15;
642 params.log_data_size = min_t(u8, params.log_data_size,
643 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
644 params.log_data_size = max_t(u8, params.log_data_size,
645 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 646
eb9180f7
OG		 647 params.log_num_packets = params.log_data_size -
648 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
649 params.log_num_packets = min_t(u8, params.log_num_packets,
650 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
651
652 params.q_counter = priv->q_counter;
3f6d08d1 653 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 654 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 655 link_speed = max_t(u32, link_speed, 50000);
656 link_speed64 = link_speed;
657 do_div(link_speed64, 50000);
658 params.num_channels = link_speed64;
659
5c65c564
OG		 660 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
661 if (IS_ERR(hp)) {
662 err = PTR_ERR(hp);
663 goto create_hairpin_err;
664 }
665
eb9180f7 666 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 667 hp->tirn, hp->pair->rqn[0],
668 dev_name(hp->pair->peer_mdev->device),
eb9180f7 669 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 670
671 hpe->hp = hp;
106be53b
OG		 672 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
673 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 674
675attach_flow:
3f6d08d1
OG		 676 if (hpe->hp->num_channels > 1) {
677 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
678 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
679 } else {
680 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
681 }
5c65c564 682 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 683
5c65c564
OG		 684 return 0;
685
686create_hairpin_err:
687 kfree(hpe);
688 return err;
689}
690
691static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
692 struct mlx5e_tc_flow *flow)
693{
694 struct list_head *next = flow->hairpin.next;
695
696 list_del(&flow->hairpin);
697
698 /* no more hairpin flows for us, release the hairpin pair */
699 if (list_empty(next)) {
700 struct mlx5e_hairpin_entry *hpe;
701
702 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
703
704 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
27b942fb 705 dev_name(hpe->hp->pair->peer_mdev->device));
5c65c564
OG		 706
707 mlx5e_hairpin_destroy(hpe->hp);
708 hash_del(&hpe->hairpin_hlist);
709 kfree(hpe);
710 }
711}
712
c83954ab 713static int
74491de9 714mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 715 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 716 struct mlx5e_tc_flow *flow,
717 struct netlink_ext_ack *extack)
e8f887ac 718{
aa0cbbae 719 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 720 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 721 struct mlx5_flow_destination dest[2] = {};
66958ed9 722 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 723 .action = attr->action,
724 .flow_tag = attr->flow_tag,
60786f09 725 .reformat_id = 0,
42f7ad67 726 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 727 };
aad7e08d 728 struct mlx5_fc *counter = NULL;
e8f887ac 729 bool table_created = false;
5c65c564 730 int err, dest_ix = 0;
e8f887ac 731
3f6d08d1 732 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 733 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 734 if (err) {
3f6d08d1
OG		 735 goto err_add_hairpin_flow;
736 }
737 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
738 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
739 dest[dest_ix].ft = attr->hairpin_ft;
740 } else {
5c65c564
OG		 741 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
742 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 743 }
744 dest_ix++;
3f6d08d1
OG		 745 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
746 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
747 dest[dest_ix].ft = priv->fs.vlan.ft.t;
748 dest_ix++;
5c65c564 749 }
aad7e08d 750
5c65c564
OG		 751 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
752 counter = mlx5_fc_create(dev, true);
753 if (IS_ERR(counter)) {
c83954ab 754 err = PTR_ERR(counter);
5c65c564
OG		 755 goto err_fc_create;
756 }
757 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 758 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 759 dest_ix++;
b8aee822 760 attr->counter = counter;
aad7e08d
AV		 761 }
762
2f4fe4ca 763 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 764 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 765 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 766 kfree(parse_attr->mod_hdr_actions);
c83954ab 767 if (err)
2f4fe4ca 768 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 769 }
770
acff797c 771 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 772 int tc_grp_size, tc_tbl_size;
773 u32 max_flow_counter;
774
775 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
776 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
777
778 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
779
780 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
781 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
782
acff797c
MG		 783 priv->fs.tc.t =
784 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
785 MLX5E_TC_PRIO,
21b9c144 786 tc_tbl_size,
acff797c 787 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 788 MLX5E_TC_FT_LEVEL, 0);
acff797c 789 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 790 NL_SET_ERR_MSG_MOD(extack,
791 "Failed to create tc offload table\n");
e8f887ac
AV		 792 netdev_err(priv->netdev,
793 "Failed to create tc offload table\n");
c83954ab 794 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 795 goto err_create_ft;
e8f887ac
AV		 796 }
797
798 table_created = true;
799 }
800
38aa51c1
OG		 801 if (attr->match_level != MLX5_MATCH_NONE)
802 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
803
c83954ab
RL		 804 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
805 &flow_act, dest, dest_ix);
aad7e08d 806
c83954ab
RL		 807 if (IS_ERR(flow->rule[0])) {
808 err = PTR_ERR(flow->rule[0]);
aad7e08d 809 goto err_add_rule;
c83954ab 810 }
aad7e08d 811
c83954ab 812 return 0;
e8f887ac 813
aad7e08d
AV		 814err_add_rule:
815 if (table_created) {
acff797c
MG		 816 mlx5_destroy_flow_table(priv->fs.tc.t);
817 priv->fs.tc.t = NULL;
e8f887ac 818 }
aad7e08d 819err_create_ft:
2f4fe4ca 820 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 821 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 822err_create_mod_hdr_id:
aad7e08d 823 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 824err_fc_create:
825 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
826 mlx5e_hairpin_flow_del(priv, flow);
827err_add_hairpin_flow:
c83954ab 828 return err;
e8f887ac
AV		 829}
830
d85cdccb
OG		 831static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
832 struct mlx5e_tc_flow *flow)
833{
513f8f7f 834 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 835 struct mlx5_fc *counter = NULL;
836
b8aee822 837 counter = attr->counter;
e4ad91f2 838 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 839 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 840
d9ee0491 841 if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) {
d85cdccb
OG		 842 mlx5_destroy_flow_table(priv->fs.tc.t);
843 priv->fs.tc.t = NULL;
844 }
2f4fe4ca 845
513f8f7f 846 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 847 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 848
849 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
850 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 851}
852
aa0cbbae 853static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 854 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 855
3c37745e 856static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 857 struct mlx5e_tc_flow *flow,
733d4f36
RD		 858 struct net_device *mirred_dev,
859 int out_index,
8c4dc42b 860 struct netlink_ext_ack *extack,
0ad060ee
RD		 861 struct net_device **encap_dev,
862 bool *encap_valid);
3c37745e 863
6d2a3ed0
OG		 864static struct mlx5_flow_handle *
865mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
866 struct mlx5e_tc_flow *flow,
867 struct mlx5_flow_spec *spec,
868 struct mlx5_esw_flow_attr *attr)
869{
870 struct mlx5_flow_handle *rule;
871
872 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
873 if (IS_ERR(rule))
874 return rule;
875
e85e02ba 876 if (attr->split_count) {
6d2a3ed0
OG		 877 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
878 if (IS_ERR(flow->rule[1])) {
879 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
880 return flow->rule[1];
881 }
882 }
883
884 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
885 return rule;
886}
887
888static void
889mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
890 struct mlx5e_tc_flow *flow,
891 struct mlx5_esw_flow_attr *attr)
892{
893 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
894
e85e02ba 895 if (attr->split_count)
6d2a3ed0
OG		 896 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
897
898 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
899}
900
5dbe906f
PB		 901static struct mlx5_flow_handle *
902mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
903 struct mlx5e_tc_flow *flow,
904 struct mlx5_flow_spec *spec,
905 struct mlx5_esw_flow_attr *slow_attr)
906{
907 struct mlx5_flow_handle *rule;
908
909 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 910 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 911 slow_attr->split_count = 0;
154e62ab 912 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 913
914 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
915 if (!IS_ERR(rule))
916 flow->flags |= MLX5E_TC_FLOW_SLOW;
917
918 return rule;
919}
920
921static void
922mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
923 struct mlx5e_tc_flow *flow,
924 struct mlx5_esw_flow_attr *slow_attr)
925{
926 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 927 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 928 slow_attr->split_count = 0;
154e62ab 929 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 930 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
931 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
932}
933
b4a23329
RD		 934static void add_unready_flow(struct mlx5e_tc_flow *flow)
935{
936 struct mlx5_rep_uplink_priv *uplink_priv;
937 struct mlx5e_rep_priv *rpriv;
938 struct mlx5_eswitch *esw;
939
940 esw = flow->priv->mdev->priv.eswitch;
941 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
942 uplink_priv = &rpriv->uplink_priv;
943
944 flow->flags |= MLX5E_TC_FLOW_NOT_READY;
945 list_add_tail(&flow->unready, &uplink_priv->unready_flows);
946}
947
948static void remove_unready_flow(struct mlx5e_tc_flow *flow)
949{
950 list_del(&flow->unready);
951 flow->flags &= ~MLX5E_TC_FLOW_NOT_READY;
952}
953
c83954ab 954static int
74491de9 955mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 956 struct mlx5e_tc_flow *flow,
957 struct netlink_ext_ack *extack)
adb4c123
OG		 958{
959 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 960 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 961 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 962 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 963 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 964 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 965 struct mlx5_fc *counter = NULL;
3c37745e
OG		 966 struct mlx5e_rep_priv *rpriv;
967 struct mlx5e_priv *out_priv;
0ad060ee
RD		 968 bool encap_valid = true;
969 int err = 0;
f493f155 970 int out_index;
8b32580d 971
d14f6f2a
OG		 972 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
973 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
974 return -EOPNOTSUPP;
975 }
bf07aa73
PB		 976
977 if (attr->chain > max_chain) {
978 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
979 err = -EOPNOTSUPP;
980 goto err_max_prio_chain;
981 }
982
983 if (attr->prio > max_prio) {
984 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
985 err = -EOPNOTSUPP;
986 goto err_max_prio_chain;
987 }
e52c2802 988
f493f155 989 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 990 int mirred_ifindex;
991
f493f155
EB		 992 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
993 continue;
994
7040632d 995 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 996 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 997 mirred_ifindex);
733d4f36 998 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 999 extack, &encap_dev, &encap_valid);
1000 if (err)
c83954ab 1001 goto err_attach_encap;
0ad060ee 1002
3c37745e
OG		 1003 out_priv = netdev_priv(encap_dev);
1004 rpriv = out_priv->ppriv;
1cc26d74
EB		 1005 attr->dests[out_index].rep = rpriv->rep;
1006 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1007 }
1008
8b32580d 1009 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1010 if (err)
aa0cbbae 1011 goto err_add_vlan;
adb4c123 1012
d7e75a32 1013 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1014 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1015 kfree(parse_attr->mod_hdr_actions);
c83954ab 1016 if (err)
d7e75a32 1017 goto err_mod_hdr;
d7e75a32
OG		 1018 }
1019
b8aee822 1020 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1021 counter = mlx5_fc_create(attr->counter_dev, true);
b8aee822 1022 if (IS_ERR(counter)) {
c83954ab 1023 err = PTR_ERR(counter);
b8aee822
MB		 1024 goto err_create_counter;
1025 }
1026
1027 attr->counter = counter;
1028 }
1029
0ad060ee
RD		 1030 /* we get here if one of the following takes place:
1031 * (1) there's no error
1032 * (2) there's an encap action and we don't have valid neigh
3c37745e 1033 */
0ad060ee 1034 if (!encap_valid) {
5dbe906f
PB		 1035 /* continue with goto slow path rule instead */
1036 struct mlx5_esw_flow_attr slow_attr;
1037
1038 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1039 } else {
6d2a3ed0 1040 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1041 }
c83954ab 1042
5dbe906f
PB		 1043 if (IS_ERR(flow->rule[0])) {
1044 err = PTR_ERR(flow->rule[0]);
1045 goto err_add_rule;
1046 }
1047
1048 return 0;
aa0cbbae
OG		 1049
1050err_add_rule:
f9392795 1051 mlx5_fc_destroy(attr->counter_dev, counter);
b8aee822 1052err_create_counter:
513f8f7f 1053 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1054 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 1055err_mod_hdr:
aa0cbbae
OG		 1056 mlx5_eswitch_del_vlan_action(esw, attr);
1057err_add_vlan:
f493f155 1058 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1059 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1060 mlx5e_detach_encap(priv, flow, out_index);
3c37745e 1061err_attach_encap:
bf07aa73 1062err_max_prio_chain:
c83954ab 1063 return err;
aa0cbbae 1064}
d85cdccb
OG		 1065
1066static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1067 struct mlx5e_tc_flow *flow)
1068{
1069 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1070 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1071 struct mlx5_esw_flow_attr slow_attr;
f493f155 1072 int out_index;
d85cdccb 1073
ef06c9ee 1074 if (flow->flags & MLX5E_TC_FLOW_NOT_READY) {
b4a23329 1075 remove_unready_flow(flow);
ef06c9ee
RD		 1076 kvfree(attr->parse_attr);
1077 return;
1078 }
1079
5dbe906f
PB		 1080 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1081 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1082 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1083 else
1084 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1085 }
d85cdccb 1086
513f8f7f 1087 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1088
f493f155 1089 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1090 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1091 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1092 kvfree(attr->parse_attr);
d7e75a32 1093
513f8f7f 1094 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1095 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1096
1097 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1098 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1099}
1100
232c0013
HHZ		 1101void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1102 struct mlx5e_encap_entry *e)
1103{
3c37745e 1104 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1105 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1106 struct mlx5_flow_handle *rule;
1107 struct mlx5_flow_spec *spec;
79baaec7 1108 struct encap_flow_item *efi;
232c0013
HHZ		 1109 struct mlx5e_tc_flow *flow;
1110 int err;
1111
54c177ca
OS		 1112 err = mlx5_packet_reformat_alloc(priv->mdev,
1113 e->reformat_type,
60786f09 1114 e->encap_size, e->encap_header,
31ca3648 1115 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1116 &e->encap_id);
232c0013
HHZ		 1117 if (err) {
1118 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1119 err);
1120 return;
1121 }
1122 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1123 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1124
79baaec7 1125 list_for_each_entry(efi, &e->flows, list) {
8c4dc42b
EB		 1126 bool all_flow_encaps_valid = true;
1127 int i;
1128
79baaec7 1129 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
3c37745e 1130 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1131 spec = &esw_attr->parse_attr->spec;
1132
8c4dc42b
EB		 1133 esw_attr->dests[efi->index].encap_id = e->encap_id;
1134 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1135 /* Flow can be associated with multiple encap entries.
1136 * Before offloading the flow verify that all of them have
1137 * a valid neighbour.
1138 */
1139 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1140 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1141 continue;
1142 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1143 all_flow_encaps_valid = false;
1144 break;
1145 }
1146 }
1147 /* Do not offload flows with unresolved neighbors */
1148 if (!all_flow_encaps_valid)
1149 continue;
5dbe906f 1150 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1151 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1152 if (IS_ERR(rule)) {
1153 err = PTR_ERR(rule);
232c0013
HHZ		 1154 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1155 err);
1156 continue;
1157 }
5dbe906f
PB		 1158
1159 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1160 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1161 flow->rule[0] = rule;
232c0013
HHZ		 1162 }
1163}
1164
1165void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1166 struct mlx5e_encap_entry *e)
1167{
3c37745e 1168 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1169 struct mlx5_esw_flow_attr slow_attr;
1170 struct mlx5_flow_handle *rule;
1171 struct mlx5_flow_spec *spec;
79baaec7 1172 struct encap_flow_item *efi;
232c0013 1173 struct mlx5e_tc_flow *flow;
5dbe906f 1174 int err;
232c0013 1175
79baaec7
EB		 1176 list_for_each_entry(efi, &e->flows, list) {
1177 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5dbe906f
PB		 1178 spec = &flow->esw_attr->parse_attr->spec;
1179
1180 /* update from encap rule to slow path rule */
1181 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1182 /* mark the flow's encap dest as non-valid */
1183 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1184
1185 if (IS_ERR(rule)) {
1186 err = PTR_ERR(rule);
1187 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1188 err);
1189 continue;
1190 }
1191
1192 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1193 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1194 flow->rule[0] = rule;
232c0013
HHZ		 1195 }
1196
61c806da
OG		 1197 /* we know that the encap is valid */
1198 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1199 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1200}
1201
b8aee822
MB		 1202static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1203{
1204 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1205 return flow->esw_attr->counter;
1206 else
1207 return flow->nic_attr->counter;
1208}
1209
f6dfb4c3
HHZ		 1210void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1211{
1212 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1213 u64 bytes, packets, lastuse = 0;
1214 struct mlx5e_tc_flow *flow;
1215 struct mlx5e_encap_entry *e;
1216 struct mlx5_fc *counter;
1217 struct neigh_table *tbl;
1218 bool neigh_used = false;
1219 struct neighbour *n;
1220
1221 if (m_neigh->family == AF_INET)
1222 tbl = &arp_tbl;
1223#if IS_ENABLED(CONFIG_IPV6)
1224 else if (m_neigh->family == AF_INET6)
423c9db2 1225 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1226#endif
1227 else
1228 return;
1229
1230 list_for_each_entry(e, &nhe->encap_list, encap_list) {
79baaec7 1231 struct encap_flow_item *efi;
f6dfb4c3
HHZ		 1232 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1233 continue;
79baaec7
EB		 1234 list_for_each_entry(efi, &e->flows, list) {
1235 flow = container_of(efi, struct mlx5e_tc_flow,
1236 encaps[efi->index]);
f6dfb4c3 1237 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1238 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1239 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1240 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1241 neigh_used = true;
1242 break;
1243 }
1244 }
1245 }
e36d4810
RD		 1246 if (neigh_used)
1247 break;
f6dfb4c3
HHZ		 1248 }
1249
1250 if (neigh_used) {
1251 nhe->reported_lastuse = jiffies;
1252
1253 /* find the relevant neigh according to the cached device and
1254 * dst ip pair
1255 */
1256 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1257 if (!n)
f6dfb4c3 1258 return;
f6dfb4c3
HHZ		 1259
1260 neigh_event_send(n, NULL);
1261 neigh_release(n);
1262 }
1263}
1264
d85cdccb 1265static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1266 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1267{
8c4dc42b 1268 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1269
8c4dc42b 1270 list_del(&flow->encaps[out_index].list);
5067b602 1271 if (list_empty(next)) {
c1ae1152 1272 struct mlx5e_encap_entry *e;
5067b602 1273
c1ae1152 1274 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1275 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1276
1277 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1278 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1279
cdc5a7f3 1280 hash_del_rcu(&e->encap_hlist);
232c0013 1281 kfree(e->encap_header);
5067b602
RD		 1282 kfree(e);
1283 }
1284}
1285
04de7dda
RD		 1286static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1287{
1288 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1289
1290 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1291 !(flow->flags & MLX5E_TC_FLOW_DUP))
1292 return;
1293
1294 mutex_lock(&esw->offloads.peer_mutex);
1295 list_del(&flow->peer);
1296 mutex_unlock(&esw->offloads.peer_mutex);
1297
1298 flow->flags &= ~MLX5E_TC_FLOW_DUP;
1299
1300 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1301 kvfree(flow->peer_flow);
1302 flow->peer_flow = NULL;
1303}
1304
1305static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1306{
1307 struct mlx5_core_dev *dev = flow->priv->mdev;
1308 struct mlx5_devcom *devcom = dev->priv.devcom;
1309 struct mlx5_eswitch *peer_esw;
1310
1311 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1312 if (!peer_esw)
1313 return;
1314
1315 __mlx5e_tc_del_fdb_peer_flow(flow);
1316 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1317}
1318
e8f887ac 1319static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1320 struct mlx5e_tc_flow *flow)
e8f887ac 1321{
04de7dda
RD		 1322 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1323 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1324 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1325 } else {
d85cdccb 1326 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1327 }
e8f887ac
AV		 1328}
1329
bbd00f7e
HHZ		 1330
1331static int parse_tunnel_attr(struct mlx5e_priv *priv,
1332 struct mlx5_flow_spec *spec,
54c177ca 1333 struct tc_cls_flower_offload *f,
6363651d 1334 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1335{
e98bedf5 1336 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1337 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1338 outer_headers);
1339 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1340 outer_headers);
8f256622
PNA		 1341 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1342 struct flow_match_control enc_control;
1343 int err;
2e72eb43 1344
101f4de9 1345 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1346 headers_c, headers_v, match_level);
54c177ca
OS		 1347 if (err) {
1348 NL_SET_ERR_MSG_MOD(extack,
1349 "failed to parse tunnel attributes");
101f4de9 1350 return err;
bbd00f7e
HHZ		 1351 }
1352
8f256622
PNA		 1353 flow_rule_match_enc_control(rule, &enc_control);
1354
1355 if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1356 struct flow_match_ipv4_addrs match;
1357
1358 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1359 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1360 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1361 ntohl(match.mask->src));
bbd00f7e
HHZ		 1362 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1363 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1364 ntohl(match.key->src));
bbd00f7e
HHZ		 1365
1366 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1367 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1368 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1369 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1370 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1371 ntohl(match.key->dst));
bbd00f7e 1372
2e72eb43
OG		 1373 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
8f256622
PNA		 1375 } else if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1376 struct flow_match_ipv6_addrs match;
19f44401 1377
8f256622 1378 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1379 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1380 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1381 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1382 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1383 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1384 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1385
1386 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1387 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1388 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1389 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1390 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1391 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1392
1393 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1394 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1395 }
bbd00f7e 1396
8f256622
PNA		 1397 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1398 struct flow_match_ip match;
bcef735c 1399
8f256622
PNA		 1400 flow_rule_match_enc_ip(rule, &match);
1401 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1402 match.mask->tos & 0x3);
1403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1404 match.key->tos & 0x3);
bcef735c 1405
8f256622
PNA		 1406 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1407 match.mask->tos >> 2);
1408 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1409 match.key->tos >> 2);
bcef735c 1410
8f256622
PNA		 1411 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1412 match.mask->ttl);
1413 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1414 match.key->ttl);
e98bedf5 1415
8f256622 1416 if (match.mask->ttl &&
e98bedf5
EB		 1417 !MLX5_CAP_ESW_FLOWTABLE_FDB
1418 (priv->mdev,
1419 ft_field_support.outer_ipv4_ttl)) {
1420 NL_SET_ERR_MSG_MOD(extack,
1421 "Matching on TTL is not supported");
1422 return -EOPNOTSUPP;
1423 }
1424
bcef735c
OG		 1425 }
1426
bbd00f7e
HHZ		 1427 /* Enforce DMAC when offloading incoming tunneled flows.
1428 * Flow counters require a match on the DMAC.
1429 */
1430 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1431 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1432 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1433 dmac_47_16), priv->netdev->dev_addr);
1434
1435 /* let software handle IP fragments */
1436 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1437 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1438
1439 return 0;
1440}
1441
8377629e
EB		 1442static void *get_match_headers_criteria(u32 flags,
1443 struct mlx5_flow_spec *spec)
1444{
1445 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1446 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1447 inner_headers) :
1448 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1449 outer_headers);
1450}
1451
1452static void *get_match_headers_value(u32 flags,
1453 struct mlx5_flow_spec *spec)
1454{
1455 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1456 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1457 inner_headers) :
1458 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1459 outer_headers);
1460}
1461
de0af0bf
RD		 1462static int __parse_cls_flower(struct mlx5e_priv *priv,
1463 struct mlx5_flow_spec *spec,
1464 struct tc_cls_flower_offload *f,
54c177ca 1465 struct net_device *filter_dev,
6363651d 1466 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1467{
e98bedf5 1468 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1469 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1470 outer_headers);
1471 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1472 outer_headers);
699e96dd
JL		 1473 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1474 misc_parameters);
1475 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1476 misc_parameters);
8f256622
PNA		 1477 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1478 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1479 u16 addr_type = 0;
1480 u8 ip_proto = 0;
1481
d708f902 1482 *match_level = MLX5_MATCH_NONE;
de0af0bf 1483
8f256622 1484 if (dissector->used_keys &
e3a2b7ed
AV		 1485 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1486 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1487 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1488 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1489 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1490 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1491 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1492 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1493 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1494 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1495 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1496 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1497 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1498 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1499 BIT(FLOW_DISSECTOR_KEY_IP) |
1500 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1501 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1502 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1503 dissector->used_keys);
e3a2b7ed
AV		 1504 return -EOPNOTSUPP;
1505 }
1506
8f256622
PNA		 1507 if ((flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1508 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1509 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1510 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1511 struct flow_match_control match;
1512
1513 flow_rule_match_enc_control(rule, &match);
1514 switch (match.key->addr_type) {
bbd00f7e 1515 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1516 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
6363651d 1517 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e
HHZ		 1518 return -EOPNOTSUPP;
1519 break;
1520 default:
1521 return -EOPNOTSUPP;
1522 }
1523
1524 /* In decap flow, header pointers should point to the inner
1525 * headers, outer header were already set by parse_tunnel_attr
1526 */
8377629e
EB		 1527 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1528 spec);
1529 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1530 spec);
bbd00f7e
HHZ		 1531 }
1532
8f256622
PNA		 1533 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1534 struct flow_match_basic match;
1535
1536 flow_rule_match_basic(rule, &match);
d3a80bb5 1537 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1538 ntohs(match.mask->n_proto));
d3a80bb5 1539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1540 ntohs(match.key->n_proto));
e3a2b7ed 1541
8f256622 1542 if (match.mask->n_proto)
d708f902 1543 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1544 }
35a605db
EB		 1545 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1546 is_vlan_dev(filter_dev)) {
1547 struct flow_dissector_key_vlan filter_dev_mask;
1548 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1549 struct flow_match_vlan match;
1550
35a605db
EB		 1551 if (is_vlan_dev(filter_dev)) {
1552 match.key = &filter_dev_key;
1553 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1554 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1555 match.key->vlan_priority = 0;
1556 match.mask = &filter_dev_mask;
1557 memset(match.mask, 0xff, sizeof(*match.mask));
1558 match.mask->vlan_priority = 0;
1559 } else {
1560 flow_rule_match_vlan(rule, &match);
1561 }
8f256622
PNA		 1562 if (match.mask->vlan_id ||
1563 match.mask->vlan_priority ||
1564 match.mask->vlan_tpid) {
1565 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1566 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1567 svlan_tag, 1);
1568 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1569 svlan_tag, 1);
1570 } else {
1571 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1572 cvlan_tag, 1);
1573 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1574 cvlan_tag, 1);
1575 }
095b6cfd 1576
8f256622
PNA		 1577 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1578 match.mask->vlan_id);
1579 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1580 match.key->vlan_id);
358d79a4 1581
8f256622
PNA		 1582 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1583 match.mask->vlan_priority);
1584 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1585 match.key->vlan_priority);
54782900 1586
d708f902 1587 *match_level = MLX5_MATCH_L2;
54782900 1588 }
d3a80bb5 1589 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1590 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1591 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1592 *match_level = MLX5_MATCH_L2;
54782900
OG		 1593 }
1594
8f256622
PNA		 1595 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1596 struct flow_match_vlan match;
1597
1598 flow_rule_match_vlan(rule, &match);
1599 if (match.mask->vlan_id ||
1600 match.mask->vlan_priority ||
1601 match.mask->vlan_tpid) {
1602 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1603 MLX5_SET(fte_match_set_misc, misc_c,
1604 outer_second_svlan_tag, 1);
1605 MLX5_SET(fte_match_set_misc, misc_v,
1606 outer_second_svlan_tag, 1);
1607 } else {
1608 MLX5_SET(fte_match_set_misc, misc_c,
1609 outer_second_cvlan_tag, 1);
1610 MLX5_SET(fte_match_set_misc, misc_v,
1611 outer_second_cvlan_tag, 1);
1612 }
1613
1614 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1615 match.mask->vlan_id);
699e96dd 1616 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1617 match.key->vlan_id);
699e96dd 1618 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1619 match.mask->vlan_priority);
699e96dd 1620 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1621 match.key->vlan_priority);
699e96dd
JL		 1622
1623 *match_level = MLX5_MATCH_L2;
1624 }
1625 }
1626
8f256622
PNA		 1627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1628 struct flow_match_eth_addrs match;
54782900 1629
8f256622 1630 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1631 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1632 dmac_47_16),
8f256622 1633 match.mask->dst);
d3a80bb5
OG		 1634 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1635 dmac_47_16),
8f256622 1636 match.key->dst);
d3a80bb5
OG		 1637
1638 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1639 smac_47_16),
8f256622 1640 match.mask->src);
d3a80bb5
OG		 1641 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1642 smac_47_16),
8f256622 1643 match.key->src);
d3a80bb5 1644
8f256622
PNA		 1645 if (!is_zero_ether_addr(match.mask->src) ||
1646 !is_zero_ether_addr(match.mask->dst))
d708f902 1647 *match_level = MLX5_MATCH_L2;
54782900
OG		 1648 }
1649
8f256622
PNA		 1650 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1651 struct flow_match_control match;
54782900 1652
8f256622
PNA		 1653 flow_rule_match_control(rule, &match);
1654 addr_type = match.key->addr_type;
54782900
OG		 1655
1656 /* the HW doesn't support frag first/later */
8f256622 1657 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1658 return -EOPNOTSUPP;
1659
8f256622 1660 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1663 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1664
1665 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1666 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1667 *match_level = MLX5_MATCH_L2;
54782900
OG		 1668 /* *** L2 attributes parsing up to here *** */
1669 else
83621b7d 1670 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1671 }
1672 }
1673
8f256622
PNA		 1674 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1675 struct flow_match_basic match;
1676
1677 flow_rule_match_basic(rule, &match);
1678 ip_proto = match.key->ip_proto;
54782900
OG		 1679
1680 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1681 match.mask->ip_proto);
54782900 1682 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1683 match.key->ip_proto);
54782900 1684
8f256622 1685 if (match.mask->ip_proto)
d708f902 1686 *match_level = MLX5_MATCH_L3;
54782900
OG		 1687 }
1688
e3a2b7ed 1689 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1690 struct flow_match_ipv4_addrs match;
e3a2b7ed 1691
8f256622 1692 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1693 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1694 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1695 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1696 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1697 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1698 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1699 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1700 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1701 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1702 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1703 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1704 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1705
8f256622 1706 if (match.mask->src || match.mask->dst)
d708f902 1707 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1708 }
1709
1710 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1711 struct flow_match_ipv6_addrs match;
e3a2b7ed 1712
8f256622 1713 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1714 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1715 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1716 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1717 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1718 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1719 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1720
1721 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1722 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1723 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1724 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1725 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1726 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1727
8f256622
PNA		 1728 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1729 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1730 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1731 }
1732
8f256622
PNA		 1733 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1734 struct flow_match_ip match;
1f97a526 1735
8f256622
PNA		 1736 flow_rule_match_ip(rule, &match);
1737 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1738 match.mask->tos & 0x3);
1739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1740 match.key->tos & 0x3);
1f97a526 1741
8f256622
PNA		 1742 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1743 match.mask->tos >> 2);
1744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1745 match.key->tos >> 2);
1f97a526 1746
8f256622
PNA		 1747 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1748 match.mask->ttl);
1749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1750 match.key->ttl);
1f97a526 1751
8f256622 1752 if (match.mask->ttl &&
a8ade55f 1753 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1754 ft_field_support.outer_ipv4_ttl)) {
1755 NL_SET_ERR_MSG_MOD(extack,
1756 "Matching on TTL is not supported");
1f97a526 1757 return -EOPNOTSUPP;
e98bedf5 1758 }
a8ade55f 1759
8f256622 1760 if (match.mask->tos || match.mask->ttl)
d708f902 1761 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1762 }
1763
54782900
OG		 1764 /* *** L3 attributes parsing up to here *** */
1765
8f256622
PNA		 1766 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1767 struct flow_match_ports match;
1768
1769 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1770 switch (ip_proto) {
1771 case IPPROTO_TCP:
1772 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1773 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1774 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1775 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1776
1777 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1778 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1779 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1780 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1781 break;
1782
1783 case IPPROTO_UDP:
1784 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1785 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1786 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1787 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1788
1789 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1790 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1791 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1792 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1793 break;
1794 default:
e98bedf5
EB		 1795 NL_SET_ERR_MSG_MOD(extack,
1796 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1797 netdev_err(priv->netdev,
1798 "Only UDP and TCP transport are supported\n");
1799 return -EINVAL;
1800 }
de0af0bf 1801
8f256622 1802 if (match.mask->src || match.mask->dst)
d708f902 1803 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1804 }
1805
8f256622
PNA		 1806 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1807 struct flow_match_tcp match;
e77834ec 1808
8f256622 1809 flow_rule_match_tcp(rule, &match);
e77834ec 1810 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1811 ntohs(match.mask->flags));
e77834ec 1812 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1813 ntohs(match.key->flags));
e77834ec 1814
8f256622 1815 if (match.mask->flags)
d708f902 1816 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1817 }
1818
e3a2b7ed
AV		 1819 return 0;
1820}
1821
de0af0bf 1822static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1823 struct mlx5e_tc_flow *flow,
de0af0bf 1824 struct mlx5_flow_spec *spec,
54c177ca
OS		 1825 struct tc_cls_flower_offload *f,
1826 struct net_device *filter_dev)
de0af0bf 1827{
e98bedf5 1828 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1829 struct mlx5_core_dev *dev = priv->mdev;
1830 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1831 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1832 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1833 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1834 int err;
1835
6363651d 1836 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 1837
1d447a39
SM		 1838 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1839 rep = rpriv->rep;
b05af6aa 1840 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 1841 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1842 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1843 NL_SET_ERR_MSG_MOD(extack,
1844 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1845 netdev_warn(priv->netdev,
1846 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1847 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1848 return -EOPNOTSUPP;
1849 }
1850 }
1851
6363651d 1852 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
38aa51c1 1853 flow->esw_attr->match_level = match_level;
6363651d
OG		 1854 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1855 } else {
38aa51c1 1856 flow->nic_attr->match_level = match_level;
6363651d 1857 }
38aa51c1 1858
de0af0bf
RD		 1859 return err;
1860}
1861
d79b6df6
OG		 1862struct pedit_headers {
1863 struct ethhdr eth;
0eb69bb9 1864 struct vlan_hdr vlan;
d79b6df6
OG		 1865 struct iphdr ip4;
1866 struct ipv6hdr ip6;
1867 struct tcphdr tcp;
1868 struct udphdr udp;
1869};
1870
c500c86b
PNA		 1871struct pedit_headers_action {
1872 struct pedit_headers vals;
1873 struct pedit_headers masks;
1874 u32 pedits;
1875};
1876
d79b6df6 1877static int pedit_header_offsets[] = {
73867881
PNA		 1878 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1879 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1880 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1881 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1882 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 1883};
1884
1885#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1886
1887static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 1888 struct pedit_headers_action *hdrs)
d79b6df6
OG		 1889{
1890 u32 *curr_pmask, *curr_pval;
1891
c500c86b
PNA		 1892 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
1893 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 1894
1895 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1896 goto out_err;
1897
1898 *curr_pmask |= mask;
1899 *curr_pval |= (val & mask);
1900
1901 return 0;
1902
1903out_err:
1904 return -EOPNOTSUPP;
1905}
1906
1907struct mlx5_fields {
1908 u8 field;
1909 u8 size;
1910 u32 offset;
27c11b6b 1911 u32 match_offset;
d79b6df6
OG		 1912};
1913
27c11b6b
EB		 1914#define OFFLOAD(fw_field, size, field, off, match_field) \
1915 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
1916 offsetof(struct pedit_headers, field) + (off), \
1917 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
1918
1919static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
1920 void *matchmaskp, int size)
1921{
1922 bool same = false;
1923
1924 switch (size) {
1925 case sizeof(u8):
1926 same = ((*(u8 *)valp) & (*(u8 *)maskp)) ==
1927 ((*(u8 *)matchvalp) & (*(u8 *)matchmaskp));
1928 break;
1929 case sizeof(u16):
1930 same = ((*(u16 *)valp) & (*(u16 *)maskp)) ==
1931 ((*(u16 *)matchvalp) & (*(u16 *)matchmaskp));
1932 break;
1933 case sizeof(u32):
1934 same = ((*(u32 *)valp) & (*(u32 *)maskp)) ==
1935 ((*(u32 *)matchvalp) & (*(u32 *)matchmaskp));
1936 break;
1937 }
1938
1939 return same;
1940}
a8e4f0c4 1941
d79b6df6 1942static struct mlx5_fields fields[] = {
27c11b6b
EB		 1943 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
1944 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
1945 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
1946 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
1947 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
1948 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
1949
1950 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
1951 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
1952 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1953
1954 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
1955 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
1956 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
1957 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
1958 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
1959 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
1960 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
1961 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
1962 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
1963 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
1964 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
1965 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
1966 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
1967 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
1968 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
1969 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
1970 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
1971
1972 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
1973 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
1974 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
1975
1976 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
1977 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
d79b6df6
OG		 1978};
1979
218d05ce
TZ		 1980/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
1981 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
1982 * says how many HW actions were actually parsed.
d79b6df6 1983 */
c500c86b 1984static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 1985 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 1986 u32 *action_flags,
e98bedf5 1987 struct netlink_ext_ack *extack)
d79b6df6
OG		 1988{
1989 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
27c11b6b
EB		 1990 void *headers_c = get_match_headers_criteria(*action_flags,
1991 &parse_attr->spec);
1992 void *headers_v = get_match_headers_value(*action_flags,
1993 &parse_attr->spec);
2b64beba 1994 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1995 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1996 struct mlx5_fields *f;
1997 u8 cmd, field_bsize;
e3ca4e05 1998 u32 s_mask, a_mask;
d79b6df6 1999 unsigned long mask;
2b64beba
OG		 2000 __be32 mask_be32;
2001 __be16 mask_be16;
d79b6df6
OG		 2002 void *action;
2003
73867881
PNA		 2004 set_masks = &hdrs[0].masks;
2005 add_masks = &hdrs[1].masks;
2006 set_vals = &hdrs[0].vals;
2007 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2008
2009 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2010 action = parse_attr->mod_hdr_actions +
2011 parse_attr->num_mod_hdr_actions * action_size;
2012
2013 max_actions = parse_attr->max_mod_hdr_actions;
2014 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2015
2016 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2017 bool skip;
2018
d79b6df6
OG		 2019 f = &fields[i];
2020 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2021 s_mask = 0;
2022 a_mask = 0;
d79b6df6
OG		 2023
2024 s_masks_p = (void *)set_masks + f->offset;
2025 a_masks_p = (void *)add_masks + f->offset;
2026
2027 memcpy(&s_mask, s_masks_p, f->size);
2028 memcpy(&a_mask, a_masks_p, f->size);
2029
2030 if (!s_mask && !a_mask) /* nothing to offload here */
2031 continue;
2032
2033 if (s_mask && a_mask) {
e98bedf5
EB		 2034 NL_SET_ERR_MSG_MOD(extack,
2035 "can't set and add to the same HW field");
d79b6df6
OG		 2036 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2037 return -EOPNOTSUPP;
2038 }
2039
2040 if (nactions == max_actions) {
e98bedf5
EB		 2041 NL_SET_ERR_MSG_MOD(extack,
2042 "too many pedit actions, can't offload");
d79b6df6
OG		 2043 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2044 return -EOPNOTSUPP;
2045 }
2046
27c11b6b 2047 skip = false;
d79b6df6 2048 if (s_mask) {
27c11b6b
EB		 2049 void *match_mask = headers_c + f->match_offset;
2050 void *match_val = headers_v + f->match_offset;
2051
d79b6df6
OG		 2052 cmd = MLX5_ACTION_TYPE_SET;
2053 mask = s_mask;
2054 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2055 /* don't rewrite if we have a match on the same value */
2056 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2057 match_mask, f->size))
2058 skip = true;
d79b6df6
OG		 2059 /* clear to denote we consumed this field */
2060 memset(s_masks_p, 0, f->size);
2061 } else {
27c11b6b
EB		 2062 u32 zero = 0;
2063
d79b6df6
OG		 2064 cmd = MLX5_ACTION_TYPE_ADD;
2065 mask = a_mask;
2066 vals_p = (void *)add_vals + f->offset;
27c11b6b
EB		 2067 /* add 0 is no change */
2068 if (!memcmp(vals_p, &zero, f->size))
2069 skip = true;
d79b6df6
OG		 2070 /* clear to denote we consumed this field */
2071 memset(a_masks_p, 0, f->size);
2072 }
27c11b6b
EB		 2073 if (skip)
2074 continue;
d79b6df6 2075
d79b6df6 2076 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2077
2b64beba
OG		 2078 if (field_bsize == 32) {
2079 mask_be32 = *(__be32 *)&mask;
2080 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2081 } else if (field_bsize == 16) {
2082 mask_be16 = *(__be16 *)&mask;
2083 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2084 }
2085
d79b6df6 2086 first = find_first_bit(&mask, field_bsize);
2b64beba 2087 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2088 last = find_last_bit(&mask, field_bsize);
2b64beba 2089 if (first < next_z && next_z < last) {
e98bedf5
EB		 2090 NL_SET_ERR_MSG_MOD(extack,
2091 "rewrite of few sub-fields isn't supported");
2b64beba 2092 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2093 mask);
2094 return -EOPNOTSUPP;
2095 }
2096
2097 MLX5_SET(set_action_in, action, action_type, cmd);
2098 MLX5_SET(set_action_in, action, field, f->field);
2099
2100 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2101 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2102 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2103 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2104 }
2105
2106 if (field_bsize == 32)
2b64beba 2107 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2108 else if (field_bsize == 16)
2b64beba 2109 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2110 else if (field_bsize == 8)
2b64beba 2111 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2112
2113 action += action_size;
2114 nactions++;
2115 }
2116
2117 parse_attr->num_mod_hdr_actions = nactions;
2118 return 0;
2119}
2120
2cc1cb1d
TZ		 2121static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2122 int namespace)
2123{
2124 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2125 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2126 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2127 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2128}
2129
d79b6df6 2130static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2131 struct pedit_headers_action *hdrs,
2132 int namespace,
d79b6df6
OG		 2133 struct mlx5e_tc_flow_parse_attr *parse_attr)
2134{
2135 int nkeys, action_size, max_actions;
2136
c500c86b
PNA		 2137 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2138 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2139 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2140
2cc1cb1d 2141 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2142 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2143 max_actions = min(max_actions, nkeys * 16);
2144
2145 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2146 if (!parse_attr->mod_hdr_actions)
2147 return -ENOMEM;
2148
218d05ce 2149 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2150 return 0;
2151}
2152
2153static const struct pedit_headers zero_masks = {};
2154
2155static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2156 const struct flow_action_entry *act, int namespace,
e98bedf5 2157 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2158 struct pedit_headers_action *hdrs,
e98bedf5 2159 struct netlink_ext_ack *extack)
d79b6df6 2160{
73867881
PNA		 2161 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2162 int err = -EOPNOTSUPP;
d79b6df6 2163 u32 mask, val, offset;
73867881 2164 u8 htype;
d79b6df6 2165
73867881
PNA		 2166 htype = act->mangle.htype;
2167 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2168
73867881
PNA		 2169 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2170 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2171 goto out_err;
2172 }
d79b6df6 2173
2cc1cb1d
TZ		 2174 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2175 NL_SET_ERR_MSG_MOD(extack,
2176 "The pedit offload action is not supported");
2177 goto out_err;
2178 }
2179
73867881
PNA		 2180 mask = act->mangle.mask;
2181 val = act->mangle.val;
2182 offset = act->mangle.offset;
d79b6df6 2183
73867881
PNA		 2184 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2185 if (err)
2186 goto out_err;
c500c86b 2187
73867881 2188 hdrs[cmd].pedits++;
d79b6df6 2189
c500c86b
PNA		 2190 return 0;
2191out_err:
2192 return err;
2193}
2194
2195static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2196 struct mlx5e_tc_flow_parse_attr *parse_attr,
2197 struct pedit_headers_action *hdrs,
27c11b6b 2198 u32 *action_flags,
c500c86b
PNA		 2199 struct netlink_ext_ack *extack)
2200{
2201 struct pedit_headers *cmd_masks;
2202 int err;
2203 u8 cmd;
2204
218d05ce 2205 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2206 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2207 if (err)
2208 goto out_err;
2209 }
d79b6df6 2210
27c11b6b 2211 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2212 if (err < 0)
2213 goto out_dealloc_parsed_actions;
2214
2215 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2216 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2217 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2218 NL_SET_ERR_MSG_MOD(extack,
2219 "attempt to offload an unsupported field");
b3a433de 2220 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2221 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2222 16, 1, cmd_masks, sizeof(zero_masks), true);
2223 err = -EOPNOTSUPP;
2224 goto out_dealloc_parsed_actions;
2225 }
2226 }
2227
2228 return 0;
2229
2230out_dealloc_parsed_actions:
2231 kfree(parse_attr->mod_hdr_actions);
2232out_err:
2233 return err;
2234}
2235
e98bedf5
EB		 2236static bool csum_offload_supported(struct mlx5e_priv *priv,
2237 u32 action,
2238 u32 update_flags,
2239 struct netlink_ext_ack *extack)
26c02749
OG		 2240{
2241 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2242 TCA_CSUM_UPDATE_FLAG_UDP;
2243
2244 /* The HW recalcs checksums only if re-writing headers */
2245 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2246 NL_SET_ERR_MSG_MOD(extack,
2247 "TC csum action is only offloaded with pedit");
26c02749
OG		 2248 netdev_warn(priv->netdev,
2249 "TC csum action is only offloaded with pedit\n");
2250 return false;
2251 }
2252
2253 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2254 NL_SET_ERR_MSG_MOD(extack,
2255 "can't offload TC csum action for some header/s");
26c02749
OG		 2256 netdev_warn(priv->netdev,
2257 "can't offload TC csum action for some header/s - flags %#x\n",
2258 update_flags);
2259 return false;
2260 }
2261
2262 return true;
2263}
2264
8998576b
DL		 2265struct ip_ttl_word {
2266 __u8 ttl;
2267 __u8 protocol;
2268 __sum16 check;
2269};
2270
2271struct ipv6_hoplimit_word {
2272 __be16 payload_len;
2273 __u8 nexthdr;
2274 __u8 hop_limit;
2275};
2276
2277static bool is_action_keys_supported(const struct flow_action_entry *act)
2278{
2279 u32 mask, offset;
2280 u8 htype;
2281
2282 htype = act->mangle.htype;
2283 offset = act->mangle.offset;
2284 mask = ~act->mangle.mask;
2285 /* For IPv4 & IPv6 header check 4 byte word,
2286 * to determine that modified fields
2287 * are NOT ttl & hop_limit only.
2288 */
2289 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2290 struct ip_ttl_word *ttl_word =
2291 (struct ip_ttl_word *)&mask;
2292
2293 if (offset != offsetof(struct iphdr, ttl) ||
2294 ttl_word->protocol ||
2295 ttl_word->check) {
2296 return true;
2297 }
2298 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2299 struct ipv6_hoplimit_word *hoplimit_word =
2300 (struct ipv6_hoplimit_word *)&mask;
2301
2302 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2303 hoplimit_word->payload_len ||
2304 hoplimit_word->nexthdr) {
2305 return true;
2306 }
2307 }
2308 return false;
2309}
2310
bdd66ac0 2311static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2312 struct flow_action *flow_action,
1651925d 2313 u32 actions,
e98bedf5 2314 struct netlink_ext_ack *extack)
bdd66ac0 2315{
73867881 2316 const struct flow_action_entry *act;
bdd66ac0 2317 bool modify_ip_header;
bdd66ac0
OG		 2318 void *headers_v;
2319 u16 ethertype;
8998576b 2320 u8 ip_proto;
73867881 2321 int i;
bdd66ac0 2322
8377629e 2323 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2324 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2325
2326 /* for non-IP we only re-write MACs, so we're okay */
2327 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2328 goto out_ok;
2329
2330 modify_ip_header = false;
73867881
PNA		 2331 flow_action_for_each(i, act, flow_action) {
2332 if (act->id != FLOW_ACTION_MANGLE &&
2333 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2334 continue;
2335
8998576b 2336 if (is_action_keys_supported(act)) {
73867881
PNA		 2337 modify_ip_header = true;
2338 break;
bdd66ac0
OG		 2339 }
2340 }
2341
2342 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2343 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2344 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2345 NL_SET_ERR_MSG_MOD(extack,
2346 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2347 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2348 return false;
2349 }
2350
2351out_ok:
2352 return true;
2353}
2354
2355static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2356 struct flow_action *flow_action,
bdd66ac0 2357 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2358 struct mlx5e_tc_flow *flow,
2359 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2360{
2361 u32 actions;
2362
2363 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2364 actions = flow->esw_attr->action;
2365 else
2366 actions = flow->nic_attr->action;
2367
7e29392e 2368 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
35a605db
EB		 2369 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2370 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)))
7e29392e
RD		 2371 return false;
2372
bdd66ac0 2373 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2374 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2375 flow_action, actions,
e98bedf5 2376 extack);
bdd66ac0
OG		 2377
2378 return true;
2379}
2380
5c65c564
OG		 2381static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2382{
2383 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2384 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2385
2386 fmdev = priv->mdev;
2387 pmdev = peer_priv->mdev;
2388
59c9d35e
AH		 2389 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2390 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2391
816f6706 2392 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2393}
2394
bdc837ee
EB		 2395static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2396 const struct flow_action_entry *act,
2397 struct mlx5e_tc_flow_parse_attr *parse_attr,
2398 struct pedit_headers_action *hdrs,
2399 u32 *action, struct netlink_ext_ack *extack)
2400{
2401 u16 mask16 = VLAN_VID_MASK;
2402 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2403 const struct flow_action_entry pedit_act = {
2404 .id = FLOW_ACTION_MANGLE,
2405 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2406 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2407 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2408 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2409 };
6fca9d1e 2410 u8 match_prio_mask, match_prio_val;
bf2f3bca 2411 void *headers_c, *headers_v;
bdc837ee
EB		 2412 int err;
2413
bf2f3bca
EB		 2414 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2415 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2416
2417 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2418 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2419 NL_SET_ERR_MSG_MOD(extack,
2420 "VLAN rewrite action must have VLAN protocol match");
2421 return -EOPNOTSUPP;
2422 }
2423
6fca9d1e
EB		 2424 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2425 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2426 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2427 NL_SET_ERR_MSG_MOD(extack,
2428 "Changing VLAN prio is not supported");
bdc837ee
EB		 2429 return -EOPNOTSUPP;
2430 }
2431
2432 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2433 hdrs, NULL);
2434 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2435
2436 return err;
2437}
2438
73867881
PNA		 2439static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2440 struct flow_action *flow_action,
aa0cbbae 2441 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2442 struct mlx5e_tc_flow *flow,
2443 struct netlink_ext_ack *extack)
e3a2b7ed 2444{
aa0cbbae 2445 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2446 struct pedit_headers_action hdrs[2] = {};
2447 const struct flow_action_entry *act;
1cab1cd7 2448 u32 action = 0;
244cd96a 2449 int err, i;
e3a2b7ed 2450
73867881 2451 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2452 return -EINVAL;
2453
3bc4b7bf 2454 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2455
73867881
PNA		 2456 flow_action_for_each(i, act, flow_action) {
2457 switch (act->id) {
2458 case FLOW_ACTION_DROP:
1cab1cd7 2459 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2460 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2461 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2462 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2463 break;
2464 case FLOW_ACTION_MANGLE:
2465 case FLOW_ACTION_ADD:
2466 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2467 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2468 if (err)
2469 return err;
2470
1cab1cd7
OG		 2471 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2472 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2473 break;
bdc837ee
EB		 2474 case FLOW_ACTION_VLAN_MANGLE:
2475 err = add_vlan_rewrite_action(priv,
2476 MLX5_FLOW_NAMESPACE_KERNEL,
2477 act, parse_attr, hdrs,
2478 &action, extack);
2479 if (err)
2480 return err;
2481
2482 break;
73867881 2483 case FLOW_ACTION_CSUM:
1cab1cd7 2484 if (csum_offload_supported(priv, action,
73867881 2485 act->csum_flags,
e98bedf5 2486 extack))
73867881 2487 break;
26c02749
OG		 2488
2489 return -EOPNOTSUPP;
73867881
PNA		 2490 case FLOW_ACTION_REDIRECT: {
2491 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2492
2493 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2494 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2495 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
5c65c564 2496 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2497 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2498 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2499 } else {
e98bedf5
EB		 2500 NL_SET_ERR_MSG_MOD(extack,
2501 "device is not on same HW, can't offload");
5c65c564
OG		 2502 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2503 peer_dev->name);
2504 return -EINVAL;
2505 }
73867881
PNA		 2506 }
2507 break;
2508 case FLOW_ACTION_MARK: {
2509 u32 mark = act->mark;
e3a2b7ed
AV		 2510
2511 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2512 NL_SET_ERR_MSG_MOD(extack,
2513 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2514 return -EINVAL;
2515 }
2516
3bc4b7bf 2517 attr->flow_tag = mark;
1cab1cd7 2518 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2519 }
2520 break;
2521 default:
2cc1cb1d
TZ		 2522 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2523 return -EOPNOTSUPP;
e3a2b7ed 2524 }
e3a2b7ed
AV		 2525 }
2526
c500c86b
PNA		 2527 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2528 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2529 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2530 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2531 if (err)
2532 return err;
27c11b6b
EB		 2533 /* in case all pedit actions are skipped, remove the MOD_HDR
2534 * flag.
2535 */
2536 if (parse_attr->num_mod_hdr_actions == 0)
2537 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c500c86b
PNA		 2538 }
2539
1cab1cd7 2540 attr->action = action;
73867881 2541 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2542 return -EOPNOTSUPP;
2543
e3a2b7ed
AV		 2544 return 0;
2545}
2546
7f1a546e
EB		 2547struct encap_key {
2548 struct ip_tunnel_key *ip_tun_key;
2549 int tunnel_type;
2550};
2551
2552static inline int cmp_encap_info(struct encap_key *a,
2553 struct encap_key *b)
a54e20b4 2554{
7f1a546e
EB		 2555 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
2556 a->tunnel_type != b->tunnel_type;
a54e20b4
HHZ		 2557}
2558
7f1a546e 2559static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2560{
7f1a546e
EB		 2561 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
2562 key->tunnel_type);
a54e20b4
HHZ		 2563}
2564
a54e20b4 2565
b1d90e6b
RL		 2566static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2567 struct net_device *peer_netdev)
2568{
2569 struct mlx5e_priv *peer_priv;
2570
2571 peer_priv = netdev_priv(peer_netdev);
2572
2573 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2574 mlx5e_eswitch_rep(priv->netdev) &&
2575 mlx5e_eswitch_rep(peer_netdev) &&
2576 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2577}
2578
32f3671f 2579
f5bc2c5d 2580
a54e20b4 2581static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 2582 struct mlx5e_tc_flow *flow,
733d4f36
RD		 2583 struct net_device *mirred_dev,
2584 int out_index,
8c4dc42b 2585 struct netlink_ext_ack *extack,
0ad060ee
RD		 2586 struct net_device **encap_dev,
2587 bool *encap_valid)
a54e20b4
HHZ		 2588{
2589 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 2590 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36
RD		 2591 struct mlx5e_tc_flow_parse_attr *parse_attr;
2592 struct ip_tunnel_info *tun_info;
7f1a546e 2593 struct encap_key key, e_key;
c1ae1152 2594 struct mlx5e_encap_entry *e;
733d4f36 2595 unsigned short family;
a54e20b4
HHZ		 2596 uintptr_t hash_key;
2597 bool found = false;
54c177ca 2598 int err = 0;
a54e20b4 2599
733d4f36
RD		 2600 parse_attr = attr->parse_attr;
2601 tun_info = &parse_attr->tun_info[out_index];
2602 family = ip_tunnel_info_af(tun_info);
7f1a546e
EB		 2603 key.ip_tun_key = &tun_info->key;
2604 key.tunnel_type = mlx5e_tc_tun_get_type(mirred_dev);
733d4f36 2605
7f1a546e 2606 hash_key = hash_encap_info(&key);
a54e20b4
HHZ		 2607
2608 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2609 encap_hlist, hash_key) {
7f1a546e
EB		 2610 e_key.ip_tun_key = &e->tun_info.key;
2611 e_key.tunnel_type = e->tunnel_type;
2612 if (!cmp_encap_info(&e_key, &key)) {
a54e20b4
HHZ		 2613 found = true;
2614 break;
2615 }
2616 }
2617
b2812089 2618 /* must verify if encap is valid or not */
45247bf2
OG		 2619 if (found)
2620 goto attach_flow;
a54e20b4
HHZ		 2621
2622 e = kzalloc(sizeof(*e), GFP_KERNEL);
2623 if (!e)
2624 return -ENOMEM;
2625
76f7444d 2626 e->tun_info = *tun_info;
101f4de9 2627 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2628 if (err)
2629 goto out_err;
2630
a54e20b4
HHZ		 2631 INIT_LIST_HEAD(&e->flows);
2632
ce99f6b9 2633 if (family == AF_INET)
101f4de9 2634 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2635 else if (family == AF_INET6)
101f4de9 2636 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2637
0ad060ee 2638 if (err)
a54e20b4
HHZ		 2639 goto out_err;
2640
a54e20b4
HHZ		 2641 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2642
45247bf2 2643attach_flow:
8c4dc42b
EB		 2644 list_add(&flow->encaps[out_index].list, &e->flows);
2645 flow->encaps[out_index].index = out_index;
45247bf2 2646 *encap_dev = e->out_dev;
8c4dc42b
EB		 2647 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2648 attr->dests[out_index].encap_id = e->encap_id;
2649 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 2650 *encap_valid = true;
8c4dc42b 2651 } else {
0ad060ee 2652 *encap_valid = false;
8c4dc42b 2653 }
45247bf2 2654
232c0013 2655 return err;
a54e20b4
HHZ		 2656
2657out_err:
2658 kfree(e);
2659 return err;
2660}
2661
1482bd3d 2662static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2663 const struct flow_action_entry *act,
1482bd3d
JL		 2664 struct mlx5_esw_flow_attr *attr,
2665 u32 *action)
2666{
cc495188
JL		 2667 u8 vlan_idx = attr->total_vlan;
2668
2669 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2670 return -EOPNOTSUPP;
2671
73867881
PNA		 2672 switch (act->id) {
2673 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2674 if (vlan_idx) {
2675 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2676 MLX5_FS_VLAN_DEPTH))
2677 return -EOPNOTSUPP;
2678
2679 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2680 } else {
2681 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2682 }
73867881
PNA		 2683 break;
2684 case FLOW_ACTION_VLAN_PUSH:
2685 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2686 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2687 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2688 if (!attr->vlan_proto[vlan_idx])
2689 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2690
2691 if (vlan_idx) {
2692 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2693 MLX5_FS_VLAN_DEPTH))
2694 return -EOPNOTSUPP;
2695
2696 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2697 } else {
2698 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2699 (act->vlan.proto != htons(ETH_P_8021Q) ||
2700 act->vlan.prio))
cc495188
JL		 2701 return -EOPNOTSUPP;
2702
2703 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2704 }
73867881
PNA		 2705 break;
2706 default:
bdc837ee 2707 return -EINVAL;
1482bd3d
JL		 2708 }
2709
cc495188
JL		 2710 attr->total_vlan = vlan_idx + 1;
2711
1482bd3d
JL		 2712 return 0;
2713}
2714
278748a9
EB		 2715static int add_vlan_push_action(struct mlx5e_priv *priv,
2716 struct mlx5_esw_flow_attr *attr,
2717 struct net_device **out_dev,
2718 u32 *action)
2719{
2720 struct net_device *vlan_dev = *out_dev;
2721 struct flow_action_entry vlan_act = {
2722 .id = FLOW_ACTION_VLAN_PUSH,
2723 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
2724 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
2725 .vlan.prio = 0,
2726 };
2727 int err;
2728
2729 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2730 if (err)
2731 return err;
2732
2733 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
2734 dev_get_iflink(vlan_dev));
2735 if (is_vlan_dev(*out_dev))
2736 err = add_vlan_push_action(priv, attr, out_dev, action);
2737
2738 return err;
2739}
2740
35a605db
EB		 2741static int add_vlan_pop_action(struct mlx5e_priv *priv,
2742 struct mlx5_esw_flow_attr *attr,
2743 u32 *action)
2744{
2745 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
2746 struct flow_action_entry vlan_act = {
2747 .id = FLOW_ACTION_VLAN_POP,
2748 };
2749 int err = 0;
2750
2751 while (nest_level--) {
2752 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2753 if (err)
2754 return err;
2755 }
2756
2757 return err;
2758}
2759
73867881
PNA		 2760static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2761 struct flow_action *flow_action,
e98bedf5
EB		 2762 struct mlx5e_tc_flow *flow,
2763 struct netlink_ext_ack *extack)
03a9d11e 2764{
73867881 2765 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2766 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2767 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 2768 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 2769 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2770 const struct ip_tunnel_info *info = NULL;
2771 const struct flow_action_entry *act;
a54e20b4 2772 bool encap = false;
1cab1cd7 2773 u32 action = 0;
244cd96a 2774 int err, i;
03a9d11e 2775
73867881 2776 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2777 return -EINVAL;
2778
1d447a39 2779 attr->in_rep = rpriv->rep;
10ff5359 2780 attr->in_mdev = priv->mdev;
03a9d11e 2781
73867881
PNA		 2782 flow_action_for_each(i, act, flow_action) {
2783 switch (act->id) {
2784 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2785 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2786 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2787 break;
2788 case FLOW_ACTION_MANGLE:
2789 case FLOW_ACTION_ADD:
2790 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 2791 parse_attr, hdrs, extack);
d7e75a32
OG		 2792 if (err)
2793 return err;
2794
1cab1cd7 2795 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2796 attr->split_count = attr->out_count;
73867881
PNA		 2797 break;
2798 case FLOW_ACTION_CSUM:
1cab1cd7 2799 if (csum_offload_supported(priv, action,
73867881
PNA		 2800 act->csum_flags, extack))
2801 break;
26c02749
OG		 2802
2803 return -EOPNOTSUPP;
73867881
PNA		 2804 case FLOW_ACTION_REDIRECT:
2805 case FLOW_ACTION_MIRRED: {
03a9d11e 2806 struct mlx5e_priv *out_priv;
592d3651 2807 struct net_device *out_dev;
03a9d11e 2808
73867881 2809 out_dev = act->dev;
ef381359
OS		 2810 if (!out_dev) {
2811 /* out_dev is NULL when filters with
2812 * non-existing mirred device are replayed to
2813 * the driver.
2814 */
2815 return -EINVAL;
2816 }
03a9d11e 2817
592d3651 2818 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2819 NL_SET_ERR_MSG_MOD(extack,
2820 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2821 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2822 attr->out_count);
2823 return -EOPNOTSUPP;
2824 }
2825
f493f155
EB		 2826 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2827 MLX5_FLOW_CONTEXT_ACTION_COUNT;
6dcfa234
FF		 2828 if (netdev_port_same_parent_id(priv->netdev,
2829 out_dev) ||
b1d90e6b 2830 is_merged_eswitch_dev(priv, out_dev)) {
7ba58ba7
RL		 2831 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2832 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
2833 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev);
2834
2835 if (uplink_upper &&
2836 netif_is_lag_master(uplink_upper) &&
2837 uplink_upper == out_dev)
2838 out_dev = uplink_dev;
2839
278748a9
EB		 2840 if (is_vlan_dev(out_dev)) {
2841 err = add_vlan_push_action(priv, attr,
2842 &out_dev,
2843 &action);
2844 if (err)
2845 return err;
2846 }
35a605db
EB		 2847 if (is_vlan_dev(parse_attr->filter_dev)) {
2848 err = add_vlan_pop_action(priv, attr,
2849 &action);
2850 if (err)
2851 return err;
2852 }
278748a9 2853
a0646c88
EB		 2854 if (!mlx5e_eswitch_rep(out_dev))
2855 return -EOPNOTSUPP;
2856
a54e20b4 2857 out_priv = netdev_priv(out_dev);
1d447a39 2858 rpriv = out_priv->ppriv;
df65a573
EB		 2859 attr->dests[attr->out_count].rep = rpriv->rep;
2860 attr->dests[attr->out_count].mdev = out_priv->mdev;
2861 attr->out_count++;
a54e20b4 2862 } else if (encap) {
8c4dc42b
EB		 2863 parse_attr->mirred_ifindex[attr->out_count] =
2864 out_dev->ifindex;
2865 parse_attr->tun_info[attr->out_count] = *info;
2866 encap = false;
f493f155
EB		 2867 attr->dests[attr->out_count].flags |=
2868 MLX5_ESW_DEST_ENCAP;
1cc26d74 2869 attr->out_count++;
df65a573
EB		 2870 /* attr->dests[].rep is resolved when we
2871 * handle encap
2872 */
ef381359
OS		 2873 } else if (parse_attr->filter_dev != priv->netdev) {
2874 /* All mlx5 devices are called to configure
2875 * high level device filters. Therefore, the
2876 * *attempt* to install a filter on invalid
2877 * eswitch should not trigger an explicit error
2878 */
2879 return -EINVAL;
a54e20b4 2880 } else {
e98bedf5
EB		 2881 NL_SET_ERR_MSG_MOD(extack,
2882 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2883 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2884 priv->netdev->name, out_dev->name);
2885 return -EINVAL;
2886 }
73867881
PNA		 2887 }
2888 break;
2889 case FLOW_ACTION_TUNNEL_ENCAP:
2890 info = act->tunnel;
a54e20b4
HHZ		 2891 if (info)
2892 encap = true;
2893 else
2894 return -EOPNOTSUPP;
1482bd3d 2895
73867881
PNA		 2896 break;
2897 case FLOW_ACTION_VLAN_PUSH:
2898 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 2899 if (act->id == FLOW_ACTION_VLAN_PUSH &&
2900 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
2901 /* Replace vlan pop+push with vlan modify */
2902 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2903 err = add_vlan_rewrite_action(priv,
2904 MLX5_FLOW_NAMESPACE_FDB,
2905 act, parse_attr, hdrs,
2906 &action, extack);
2907 } else {
2908 err = parse_tc_vlan_action(priv, act, attr, &action);
2909 }
1482bd3d
JL		 2910 if (err)
2911 return err;
2912
bdc837ee
EB		 2913 attr->split_count = attr->out_count;
2914 break;
2915 case FLOW_ACTION_VLAN_MANGLE:
2916 err = add_vlan_rewrite_action(priv,
2917 MLX5_FLOW_NAMESPACE_FDB,
2918 act, parse_attr, hdrs,
2919 &action, extack);
2920 if (err)
2921 return err;
2922
e85e02ba 2923 attr->split_count = attr->out_count;
73867881
PNA		 2924 break;
2925 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 2926 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 2927 break;
2928 case FLOW_ACTION_GOTO: {
2929 u32 dest_chain = act->chain_index;
bf07aa73
PB		 2930 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2931
2932 if (dest_chain <= attr->chain) {
2933 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2934 return -EOPNOTSUPP;
2935 }
2936 if (dest_chain > max_chain) {
2937 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2938 return -EOPNOTSUPP;
2939 }
e88afe75 2940 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 2941 attr->dest_chain = dest_chain;
73867881
PNA		 2942 break;
2943 }
2944 default:
2cc1cb1d
TZ		 2945 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2946 return -EOPNOTSUPP;
bf07aa73 2947 }
03a9d11e 2948 }
bdd66ac0 2949
c500c86b
PNA		 2950 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2951 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 2952 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 2953 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2954 if (err)
2955 return err;
27c11b6b
EB		 2956 /* in case all pedit actions are skipped, remove the MOD_HDR
2957 * flag. we might have set split_count either by pedit or
2958 * pop/push. if there is no pop/push either, reset it too.
2959 */
2960 if (parse_attr->num_mod_hdr_actions == 0) {
2961 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2962 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2963 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
2964 attr->split_count = 0;
2965 }
c500c86b
PNA		 2966 }
2967
1cab1cd7 2968 attr->action = action;
73867881 2969 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2970 return -EOPNOTSUPP;
2971
e88afe75
OG		 2972 if (attr->dest_chain) {
2973 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2974 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
2975 return -EOPNOTSUPP;
2976 }
2977 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2978 }
2979
e85e02ba 2980 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2981 NL_SET_ERR_MSG_MOD(extack,
2982 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2983 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2984 return -EOPNOTSUPP;
2985 }
2986
31c8eba5 2987 return 0;
03a9d11e
OG		 2988}
2989
5dbe906f 2990static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2991{
5dbe906f 2992 u16 __flow_flags = 0;
60bd4af8
OG		 2993
2994 if (flags & MLX5E_TC_INGRESS)
2995 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2996 if (flags & MLX5E_TC_EGRESS)
2997 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2998
d9ee0491
OG		 2999 if (flags & MLX5E_TC_ESW_OFFLOAD)
3000 __flow_flags |= MLX5E_TC_FLOW_ESWITCH;
3001 if (flags & MLX5E_TC_NIC_OFFLOAD)
3002 __flow_flags |= MLX5E_TC_FLOW_NIC;
3003
60bd4af8
OG		 3004 *flow_flags = __flow_flags;
3005}
3006
05866c82
OG		 3007static const struct rhashtable_params tc_ht_params = {
3008 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3009 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3010 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3011 .automatic_shrinking = true,
3012};
3013
d9ee0491 3014static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags)
05866c82 3015{
655dc3d2
OG		 3016 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3017 struct mlx5e_rep_priv *uplink_rpriv;
3018
d9ee0491 3019 if (flags & MLX5E_TC_ESW_OFFLOAD) {
655dc3d2 3020 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3021 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3022 } else /* NIC offload */
655dc3d2 3023 return &priv->fs.tc.ht;
05866c82
OG		 3024}
3025
04de7dda
RD		 3026static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3027{
1418ddd9 3028 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3029 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
1418ddd9
AH		 3030 flow->flags & MLX5E_TC_FLOW_INGRESS;
3031 bool act_is_encap = !!(attr->action &
3032 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3033 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3034 MLX5_DEVCOM_ESW_OFFLOADS);
3035
10fbb1cd
RD		 3036 if (!esw_paired)
3037 return false;
3038
3039 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3040 mlx5_lag_is_multipath(attr->in_mdev)) &&
3041 (is_rep_ingress || act_is_encap))
3042 return true;
3043
3044 return false;
04de7dda
RD		 3045}
3046
a88780a9
RD		 3047static int
3048mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 3049 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 3050 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3051 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3052{
17091853 3053 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3054 struct mlx5e_tc_flow *flow;
a88780a9 3055 int err;
e3a2b7ed 3056
65ba8fb7 3057 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3058 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3059 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3060 err = -ENOMEM;
3061 goto err_free;
3062 }
3063
3064 flow->cookie = f->cookie;
65ba8fb7 3065 flow->flags = flow_flags;
655dc3d2 3066 flow->priv = priv;
e3a2b7ed 3067
a88780a9
RD		 3068 *__flow = flow;
3069 *__parse_attr = parse_attr;
3070
3071 return 0;
3072
3073err_free:
3074 kfree(flow);
3075 kvfree(parse_attr);
3076 return err;
3077}
3078
988ab9c7
TZ		 3079static void
3080mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3081 struct mlx5e_priv *priv,
3082 struct mlx5e_tc_flow_parse_attr *parse_attr,
3083 struct tc_cls_flower_offload *f,
3084 struct mlx5_eswitch_rep *in_rep,
3085 struct mlx5_core_dev *in_mdev)
3086{
3087 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3088
3089 esw_attr->parse_attr = parse_attr;
3090 esw_attr->chain = f->common.chain_index;
3091 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
3092
3093 esw_attr->in_rep = in_rep;
3094 esw_attr->in_mdev = in_mdev;
3095
3096 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3097 MLX5_COUNTER_SOURCE_ESWITCH)
3098 esw_attr->counter_dev = in_mdev;
3099 else
3100 esw_attr->counter_dev = priv->mdev;
3101}
3102
71129676 3103static struct mlx5e_tc_flow *
04de7dda
RD		 3104__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3105 struct tc_cls_flower_offload *f,
3106 u16 flow_flags,
3107 struct net_device *filter_dev,
3108 struct mlx5_eswitch_rep *in_rep,
71129676 3109 struct mlx5_core_dev *in_mdev)
a88780a9 3110{
73867881 3111 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 3112 struct netlink_ext_ack *extack = f->common.extack;
3113 struct mlx5e_tc_flow_parse_attr *parse_attr;
3114 struct mlx5e_tc_flow *flow;
3115 int attr_size, err;
e3a2b7ed 3116
a88780a9
RD		 3117 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
3118 attr_size = sizeof(struct mlx5_esw_flow_attr);
3119 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3120 &parse_attr, &flow);
3121 if (err)
3122 goto out;
988ab9c7 3123
d11afc26 3124 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3125 mlx5e_flow_esw_attr_init(flow->esw_attr,
3126 priv, parse_attr,
3127 f, in_rep, in_mdev);
3128
54c177ca
OS		 3129 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3130 f, filter_dev);
d11afc26
OS		 3131 if (err)
3132 goto err_free;
a88780a9 3133
6f9af8ff 3134 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3135 if (err)
3136 goto err_free;
3137
7040632d 3138 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
ef06c9ee
RD		 3139 if (err) {
3140 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3141 goto err_free;
3142
b4a23329 3143 add_unready_flow(flow);
ef06c9ee 3144 }
e3a2b7ed 3145
71129676 3146 return flow;
a88780a9
RD		 3147
3148err_free:
3149 kfree(flow);
3150 kvfree(parse_attr);
3151out:
71129676 3152 return ERR_PTR(err);
a88780a9
RD		 3153}
3154
04de7dda 3155static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
95dc1902
RD		 3156 struct mlx5e_tc_flow *flow,
3157 u16 flow_flags)
04de7dda
RD		 3158{
3159 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3160 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3161 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3162 struct mlx5e_tc_flow_parse_attr *parse_attr;
3163 struct mlx5e_rep_priv *peer_urpriv;
3164 struct mlx5e_tc_flow *peer_flow;
3165 struct mlx5_core_dev *in_mdev;
3166 int err = 0;
3167
3168 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3169 if (!peer_esw)
3170 return -ENODEV;
3171
3172 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3173 peer_priv = netdev_priv(peer_urpriv->netdev);
3174
3175 /* in_mdev is assigned of which the packet originated from.
3176 * So packets redirected to uplink use the same mdev of the
3177 * original flow and packets redirected from uplink use the
3178 * peer mdev.
3179 */
b05af6aa 3180 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3181 in_mdev = peer_priv->mdev;
3182 else
3183 in_mdev = priv->mdev;
3184
3185 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3186 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3187 parse_attr->filter_dev,
3188 flow->esw_attr->in_rep, in_mdev);
3189 if (IS_ERR(peer_flow)) {
3190 err = PTR_ERR(peer_flow);
04de7dda 3191 goto out;
71129676 3192 }
04de7dda
RD		 3193
3194 flow->peer_flow = peer_flow;
3195 flow->flags |= MLX5E_TC_FLOW_DUP;
3196 mutex_lock(&esw->offloads.peer_mutex);
3197 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3198 mutex_unlock(&esw->offloads.peer_mutex);
3199
3200out:
3201 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3202 return err;
3203}
3204
3205static int
3206mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3207 struct tc_cls_flower_offload *f,
3208 u16 flow_flags,
3209 struct net_device *filter_dev,
3210 struct mlx5e_tc_flow **__flow)
3211{
3212 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3213 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3214 struct mlx5_core_dev *in_mdev = priv->mdev;
3215 struct mlx5e_tc_flow *flow;
3216 int err;
3217
71129676
JG		 3218 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3219 in_mdev);
3220 if (IS_ERR(flow))
3221 return PTR_ERR(flow);
04de7dda
RD		 3222
3223 if (is_peer_flow_needed(flow)) {
95dc1902 3224 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3225 if (err) {
3226 mlx5e_tc_del_fdb_flow(priv, flow);
3227 goto out;
3228 }
3229 }
3230
3231 *__flow = flow;
3232
3233 return 0;
3234
3235out:
3236 return err;
3237}
3238
a88780a9
RD		 3239static int
3240mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3241 struct tc_cls_flower_offload *f,
5dbe906f 3242 u16 flow_flags,
d11afc26 3243 struct net_device *filter_dev,
a88780a9
RD		 3244 struct mlx5e_tc_flow **__flow)
3245{
73867881 3246 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 3247 struct netlink_ext_ack *extack = f->common.extack;
3248 struct mlx5e_tc_flow_parse_attr *parse_attr;
3249 struct mlx5e_tc_flow *flow;
3250 int attr_size, err;
3251
bf07aa73
PB		 3252 /* multi-chain not supported for NIC rules */
3253 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3254 return -EOPNOTSUPP;
3255
a88780a9
RD		 3256 flow_flags |= MLX5E_TC_FLOW_NIC;
3257 attr_size = sizeof(struct mlx5_nic_flow_attr);
3258 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3259 &parse_attr, &flow);
3260 if (err)
3261 goto out;
3262
d11afc26 3263 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3264 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3265 f, filter_dev);
d11afc26
OS		 3266 if (err)
3267 goto err_free;
3268
73867881 3269 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3270 if (err)
3271 goto err_free;
3272
3273 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3274 if (err)
3275 goto err_free;
3276
3277 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
3278 kvfree(parse_attr);
3279 *__flow = flow;
3280
3281 return 0;
e3a2b7ed 3282
e3a2b7ed 3283err_free:
a88780a9 3284 kfree(flow);
17091853 3285 kvfree(parse_attr);
a88780a9
RD		 3286out:
3287 return err;
3288}
3289
3290static int
3291mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3292 struct tc_cls_flower_offload *f,
3293 int flags,
d11afc26 3294 struct net_device *filter_dev,
a88780a9
RD		 3295 struct mlx5e_tc_flow **flow)
3296{
3297 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 3298 u16 flow_flags;
a88780a9
RD		 3299 int err;
3300
3301 get_flags(flags, &flow_flags);
3302
bf07aa73
PB		 3303 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3304 return -EOPNOTSUPP;
3305
a88780a9 3306 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 3307 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3308 filter_dev, flow);
a88780a9 3309 else
d11afc26
OS		 3310 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3311 filter_dev, flow);
a88780a9
RD		 3312
3313 return err;
3314}
3315
71d82d2a 3316int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 3317 struct tc_cls_flower_offload *f, int flags)
3318{
3319 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3320 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3321 struct mlx5e_tc_flow *flow;
3322 int err = 0;
3323
3324 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3325 if (flow) {
3326 NL_SET_ERR_MSG_MOD(extack,
3327 "flow cookie already exists, ignoring");
3328 netdev_warn_once(priv->netdev,
3329 "flow cookie %lx already exists, ignoring\n",
3330 f->cookie);
3331 goto out;
3332 }
3333
d11afc26 3334 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3335 if (err)
3336 goto out;
3337
3338 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
3339 if (err)
3340 goto err_free;
3341
3342 return 0;
3343
3344err_free:
3345 mlx5e_tc_del_flow(priv, flow);
232c0013 3346 kfree(flow);
a88780a9 3347out:
e3a2b7ed
AV		 3348 return err;
3349}
3350
8f8ae895
OG		 3351#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
3352#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
3353
3354static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3355{
3356 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
3357 return true;
3358
3359 return false;
3360}
3361
71d82d2a 3362int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3363 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3364{
d9ee0491 3365 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3366 struct mlx5e_tc_flow *flow;
e3a2b7ed 3367
05866c82 3368 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3369 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3370 return -EINVAL;
3371
05866c82 3372 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3373
961e8979 3374 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3375
3376 kfree(flow);
3377
3378 return 0;
3379}
3380
71d82d2a 3381int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3382 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3383{
04de7dda 3384 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3385 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3386 struct mlx5_eswitch *peer_esw;
aad7e08d 3387 struct mlx5e_tc_flow *flow;
aad7e08d 3388 struct mlx5_fc *counter;
316d5f72
RD		 3389 u64 lastuse = 0;
3390 u64 packets = 0;
3391 u64 bytes = 0;
aad7e08d 3392
05866c82 3393 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3394 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3395 return -EINVAL;
3396
316d5f72
RD		 3397 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
3398 counter = mlx5e_tc_get_counter(flow);
3399 if (!counter)
3400 return 0;
aad7e08d 3401
316d5f72
RD		 3402 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3403 }
aad7e08d 3404
316d5f72
RD		 3405 /* Under multipath it's possible for one rule to be currently
3406 * un-offloaded while the other rule is offloaded.
3407 */
04de7dda
RD		 3408 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3409 if (!peer_esw)
3410 goto out;
3411
3412 if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3413 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3414 u64 bytes2;
3415 u64 packets2;
3416 u64 lastuse2;
3417
3418 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3419 if (!counter)
3420 goto no_peer_counter;
04de7dda
RD		 3421 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3422
3423 bytes += bytes2;
3424 packets += packets2;
3425 lastuse = max_t(u64, lastuse, lastuse2);
3426 }
3427
316d5f72 3428no_peer_counter:
04de7dda 3429 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3430out:
3b1903ef 3431 flow_stats_update(&f->stats, bytes, packets, lastuse);
fed06ee8 3432
aad7e08d
AV		 3433 return 0;
3434}
3435
4d8fcf21
AH		 3436static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3437 struct mlx5e_priv *peer_priv)
3438{
3439 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3440 struct mlx5e_hairpin_entry *hpe;
3441 u16 peer_vhca_id;
3442 int bkt;
3443
3444 if (!same_hw_devs(priv, peer_priv))
3445 return;
3446
3447 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3448
3449 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3450 if (hpe->peer_vhca_id == peer_vhca_id)
3451 hpe->hp->pair->peer_gone = true;
3452 }
3453}
3454
3455static int mlx5e_tc_netdev_event(struct notifier_block *this,
3456 unsigned long event, void *ptr)
3457{
3458 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3459 struct mlx5e_flow_steering *fs;
3460 struct mlx5e_priv *peer_priv;
3461 struct mlx5e_tc_table *tc;
3462 struct mlx5e_priv *priv;
3463
3464 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3465 event != NETDEV_UNREGISTER ||
3466 ndev->reg_state == NETREG_REGISTERED)
3467 return NOTIFY_DONE;
3468
3469 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3470 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3471 priv = container_of(fs, struct mlx5e_priv, fs);
3472 peer_priv = netdev_priv(ndev);
3473 if (priv == peer_priv ||
3474 !(priv->netdev->features & NETIF_F_HW_TC))
3475 return NOTIFY_DONE;
3476
3477 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3478
3479 return NOTIFY_DONE;
3480}
3481
655dc3d2 3482int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3483{
acff797c 3484 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3485 int err;
e8f887ac 3486
11c9c548 3487 hash_init(tc->mod_hdr_tbl);
5c65c564 3488 hash_init(tc->hairpin_tbl);
11c9c548 3489
4d8fcf21
AH		 3490 err = rhashtable_init(&tc->ht, &tc_ht_params);
3491 if (err)
3492 return err;
3493
3494 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3495 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3496 tc->netdevice_nb.notifier_call = NULL;
3497 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3498 }
3499
3500 return err;
e8f887ac
AV		 3501}
3502
3503static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3504{
3505 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3506 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3507
961e8979 3508 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3509 kfree(flow);
3510}
3511
655dc3d2 3512void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3513{
acff797c 3514 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3515
4d8fcf21
AH		 3516 if (tc->netdevice_nb.notifier_call)
3517 unregister_netdevice_notifier(&tc->netdevice_nb);
3518
d9ee0491 3519 rhashtable_destroy(&tc->ht);
e8f887ac 3520
acff797c
MG		 3521 if (!IS_ERR_OR_NULL(tc->t)) {
3522 mlx5_destroy_flow_table(tc->t);
3523 tc->t = NULL;
e8f887ac
AV		 3524 }
3525}
655dc3d2
OG		 3526
3527int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3528{
3529 return rhashtable_init(tc_ht, &tc_ht_params);
3530}
3531
3532void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3533{
3534 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3535}
01252a27 3536
d9ee0491 3537int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags)
01252a27 3538{
d9ee0491 3539 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3540
3541 return atomic_read(&tc_ht->nelems);
3542}
04de7dda
RD		 3543
3544void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3545{
3546 struct mlx5e_tc_flow *flow, *tmp;
3547
3548 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3549 __mlx5e_tc_del_fdb_peer_flow(flow);
3550}
b4a23329
RD		 3551
3552void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
3553{
3554 struct mlx5_rep_uplink_priv *rpriv =
3555 container_of(work, struct mlx5_rep_uplink_priv,
3556 reoffload_flows_work);
3557 struct mlx5e_tc_flow *flow, *tmp;
3558
3559 rtnl_lock();
3560 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
3561 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
3562 remove_unready_flow(flow);
3563 }
3564 rtnl_unlock();
3565}
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