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net/mlx5: Hairpin pair core object setup
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
e8f887ac 54
3bc4b7bf
OG		 55struct mlx5_nic_flow_attr {
56 u32 action;
57 u32 flow_tag;
2f4fe4ca 58 u32 mod_hdr_id;
3bc4b7bf
OG		 59};
60
65ba8fb7
OG		 61enum {
62 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 63 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 64 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
65ba8fb7
OG		 65};
66
e8f887ac
AV		 67struct mlx5e_tc_flow {
68 struct rhash_head node;
69 u64 cookie;
65ba8fb7 70 u8 flags;
74491de9 71 struct mlx5_flow_handle *rule;
11c9c548
OG		 72 struct list_head encap; /* flows sharing the same encap ID */
73 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
3bc4b7bf
OG		 74 union {
75 struct mlx5_esw_flow_attr esw_attr[0];
76 struct mlx5_nic_flow_attr nic_attr[0];
77 };
e8f887ac
AV		 78};
79
17091853 80struct mlx5e_tc_flow_parse_attr {
3c37745e 81 struct ip_tunnel_info tun_info;
17091853 82 struct mlx5_flow_spec spec;
d79b6df6
OG		 83 int num_mod_hdr_actions;
84 void *mod_hdr_actions;
3c37745e 85 int mirred_ifindex;
17091853
OG		 86};
87
a54e20b4
HHZ		 88enum {
89 MLX5_HEADER_TYPE_VXLAN = 0x0,
90 MLX5_HEADER_TYPE_NVGRE = 0x1,
91};
92
acff797c 93#define MLX5E_TC_TABLE_NUM_GROUPS 4
21b9c144 94#define MLX5E_TC_TABLE_MAX_GROUP_SIZE (1 << 16)
e8f887ac 95
11c9c548
OG		 96struct mod_hdr_key {
97 int num_actions;
98 void *actions;
99};
100
101struct mlx5e_mod_hdr_entry {
102 /* a node of a hash table which keeps all the mod_hdr entries */
103 struct hlist_node mod_hdr_hlist;
104
105 /* flows sharing the same mod_hdr entry */
106 struct list_head flows;
107
108 struct mod_hdr_key key;
109
110 u32 mod_hdr_id;
111};
112
113#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
114
115static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
116{
117 return jhash(key->actions,
118 key->num_actions * MLX5_MH_ACT_SZ, 0);
119}
120
121static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
122 struct mod_hdr_key *b)
123{
124 if (a->num_actions != b->num_actions)
125 return 1;
126
127 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
128}
129
130static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
131 struct mlx5e_tc_flow *flow,
132 struct mlx5e_tc_flow_parse_attr *parse_attr)
133{
134 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
135 int num_actions, actions_size, namespace, err;
136 struct mlx5e_mod_hdr_entry *mh;
137 struct mod_hdr_key key;
138 bool found = false;
139 u32 hash_key;
140
141 num_actions = parse_attr->num_mod_hdr_actions;
142 actions_size = MLX5_MH_ACT_SZ * num_actions;
143
144 key.actions = parse_attr->mod_hdr_actions;
145 key.num_actions = num_actions;
146
147 hash_key = hash_mod_hdr_info(&key);
148
149 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
150 namespace = MLX5_FLOW_NAMESPACE_FDB;
151 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
152 mod_hdr_hlist, hash_key) {
153 if (!cmp_mod_hdr_info(&mh->key, &key)) {
154 found = true;
155 break;
156 }
157 }
158 } else {
159 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
160 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
161 mod_hdr_hlist, hash_key) {
162 if (!cmp_mod_hdr_info(&mh->key, &key)) {
163 found = true;
164 break;
165 }
166 }
167 }
168
169 if (found)
170 goto attach_flow;
171
172 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
173 if (!mh)
174 return -ENOMEM;
175
176 mh->key.actions = (void *)mh + sizeof(*mh);
177 memcpy(mh->key.actions, key.actions, actions_size);
178 mh->key.num_actions = num_actions;
179 INIT_LIST_HEAD(&mh->flows);
180
181 err = mlx5_modify_header_alloc(priv->mdev, namespace,
182 mh->key.num_actions,
183 mh->key.actions,
184 &mh->mod_hdr_id);
185 if (err)
186 goto out_err;
187
188 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
189 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
190 else
191 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
192
193attach_flow:
194 list_add(&flow->mod_hdr, &mh->flows);
195 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
196 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
197 else
198 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
199
200 return 0;
201
202out_err:
203 kfree(mh);
204 return err;
205}
206
207static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
208 struct mlx5e_tc_flow *flow)
209{
210 struct list_head *next = flow->mod_hdr.next;
211
212 list_del(&flow->mod_hdr);
213
214 if (list_empty(next)) {
215 struct mlx5e_mod_hdr_entry *mh;
216
217 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
218
219 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
220 hash_del(&mh->mod_hdr_hlist);
221 kfree(mh);
222 }
223}
224
74491de9
MB		 225static struct mlx5_flow_handle *
226mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 227 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 228 struct mlx5e_tc_flow *flow)
e8f887ac 229{
aa0cbbae 230 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 231 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 232 struct mlx5_flow_destination dest = {};
66958ed9 233 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 234 .action = attr->action,
235 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 236 .encap_id = 0,
237 };
aad7e08d 238 struct mlx5_fc *counter = NULL;
74491de9 239 struct mlx5_flow_handle *rule;
e8f887ac 240 bool table_created = false;
2f4fe4ca 241 int err;
e8f887ac 242
3bc4b7bf 243 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV		 244 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
245 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 246 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV		 247 counter = mlx5_fc_create(dev, true);
248 if (IS_ERR(counter))
249 return ERR_CAST(counter);
250
251 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
252 dest.counter = counter;
253 }
254
2f4fe4ca 255 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 256 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 257 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 258 kfree(parse_attr->mod_hdr_actions);
259 if (err) {
260 rule = ERR_PTR(err);
261 goto err_create_mod_hdr_id;
262 }
263 }
264
acff797c 265 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 266 int tc_grp_size, tc_tbl_size;
267 u32 max_flow_counter;
268
269 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
270 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
271
272 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
273
274 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
275 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
276
acff797c
MG		 277 priv->fs.tc.t =
278 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
279 MLX5E_TC_PRIO,
21b9c144 280 tc_tbl_size,
acff797c 281 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 282 0, 0);
acff797c 283 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 284 netdev_err(priv->netdev,
285 "Failed to create tc offload table\n");
aad7e08d
AV		 286 rule = ERR_CAST(priv->fs.tc.t);
287 goto err_create_ft;
e8f887ac
AV		 288 }
289
290 table_created = true;
291 }
292
17091853
OG		 293 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
294 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
295 &flow_act, &dest, 1);
aad7e08d
AV		 296
297 if (IS_ERR(rule))
298 goto err_add_rule;
299
300 return rule;
e8f887ac 301
aad7e08d
AV		 302err_add_rule:
303 if (table_created) {
acff797c
MG		 304 mlx5_destroy_flow_table(priv->fs.tc.t);
305 priv->fs.tc.t = NULL;
e8f887ac 306 }
aad7e08d 307err_create_ft:
2f4fe4ca 308 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 309 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 310err_create_mod_hdr_id:
aad7e08d 311 mlx5_fc_destroy(dev, counter);
e8f887ac
AV		 312
313 return rule;
314}
315
d85cdccb
OG		 316static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
317 struct mlx5e_tc_flow *flow)
318{
513f8f7f 319 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 320 struct mlx5_fc *counter = NULL;
321
aa0cbbae
OG		 322 counter = mlx5_flow_rule_counter(flow->rule);
323 mlx5_del_flow_rules(flow->rule);
324 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG		 325
326 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
327 mlx5_destroy_flow_table(priv->fs.tc.t);
328 priv->fs.tc.t = NULL;
329 }
2f4fe4ca 330
513f8f7f 331 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 332 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 333}
334
aa0cbbae
OG		 335static void mlx5e_detach_encap(struct mlx5e_priv *priv,
336 struct mlx5e_tc_flow *flow);
337
3c37745e
OG		 338static int mlx5e_attach_encap(struct mlx5e_priv *priv,
339 struct ip_tunnel_info *tun_info,
340 struct net_device *mirred_dev,
341 struct net_device **encap_dev,
342 struct mlx5e_tc_flow *flow);
343
74491de9
MB		 344static struct mlx5_flow_handle *
345mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 346 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 347 struct mlx5e_tc_flow *flow)
adb4c123
OG		 348{
349 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 350 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e
OG		 351 struct net_device *out_dev, *encap_dev = NULL;
352 struct mlx5_flow_handle *rule = NULL;
353 struct mlx5e_rep_priv *rpriv;
354 struct mlx5e_priv *out_priv;
8b32580d
OG		 355 int err;
356
3c37745e
OG		 357 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
358 out_dev = __dev_get_by_index(dev_net(priv->netdev),
359 attr->parse_attr->mirred_ifindex);
360 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
361 out_dev, &encap_dev, flow);
362 if (err) {
363 rule = ERR_PTR(err);
364 if (err != -EAGAIN)
365 goto err_attach_encap;
366 }
367 out_priv = netdev_priv(encap_dev);
368 rpriv = out_priv->ppriv;
369 attr->out_rep = rpriv->rep;
370 }
371
8b32580d 372 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 373 if (err) {
374 rule = ERR_PTR(err);
375 goto err_add_vlan;
376 }
adb4c123 377
d7e75a32 378 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 379 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 380 kfree(parse_attr->mod_hdr_actions);
381 if (err) {
382 rule = ERR_PTR(err);
383 goto err_mod_hdr;
384 }
385 }
386
3c37745e
OG		 387 /* we get here if (1) there's no error (rule being null) or when
388 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
389 */
390 if (rule != ERR_PTR(-EAGAIN)) {
391 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
392 if (IS_ERR(rule))
393 goto err_add_rule;
394 }
aa0cbbae
OG		 395 return rule;
396
397err_add_rule:
513f8f7f 398 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 399 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 400err_mod_hdr:
aa0cbbae
OG		 401 mlx5_eswitch_del_vlan_action(esw, attr);
402err_add_vlan:
403 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
404 mlx5e_detach_encap(priv, flow);
3c37745e 405err_attach_encap:
aa0cbbae
OG		 406 return rule;
407}
d85cdccb
OG		 408
409static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
410 struct mlx5e_tc_flow *flow)
411{
412 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 413 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 414
232c0013
HHZ		 415 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
416 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 417 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 418 }
d85cdccb 419
513f8f7f 420 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 421
513f8f7f 422 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 423 mlx5e_detach_encap(priv, flow);
513f8f7f 424 kvfree(attr->parse_attr);
232c0013 425 }
d7e75a32 426
513f8f7f 427 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 428 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 429}
430
232c0013
HHZ		 431void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
432 struct mlx5e_encap_entry *e)
433{
3c37745e
OG		 434 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
435 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 436 struct mlx5e_tc_flow *flow;
437 int err;
438
439 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
440 e->encap_size, e->encap_header,
441 &e->encap_id);
442 if (err) {
443 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
444 err);
445 return;
446 }
447 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 448 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 449
450 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 451 esw_attr = flow->esw_attr;
452 esw_attr->encap_id = e->encap_id;
453 flow->rule = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
232c0013
HHZ		 454 if (IS_ERR(flow->rule)) {
455 err = PTR_ERR(flow->rule);
456 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
457 err);
458 continue;
459 }
460 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
461 }
462}
463
464void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
465 struct mlx5e_encap_entry *e)
466{
3c37745e 467 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 468 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 469
470 list_for_each_entry(flow, &e->flows, encap) {
471 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
472 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
3c37745e 473 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
232c0013
HHZ		 474 }
475 }
476
477 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
478 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
479 mlx5_encap_dealloc(priv->mdev, e->encap_id);
480 }
481}
482
f6dfb4c3
HHZ		 483void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
484{
485 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
486 u64 bytes, packets, lastuse = 0;
487 struct mlx5e_tc_flow *flow;
488 struct mlx5e_encap_entry *e;
489 struct mlx5_fc *counter;
490 struct neigh_table *tbl;
491 bool neigh_used = false;
492 struct neighbour *n;
493
494 if (m_neigh->family == AF_INET)
495 tbl = &arp_tbl;
496#if IS_ENABLED(CONFIG_IPV6)
497 else if (m_neigh->family == AF_INET6)
498 tbl = ipv6_stub->nd_tbl;
499#endif
500 else
501 return;
502
503 list_for_each_entry(e, &nhe->encap_list, encap_list) {
504 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
505 continue;
506 list_for_each_entry(flow, &e->flows, encap) {
507 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
508 counter = mlx5_flow_rule_counter(flow->rule);
509 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
510 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
511 neigh_used = true;
512 break;
513 }
514 }
515 }
516 }
517
518 if (neigh_used) {
519 nhe->reported_lastuse = jiffies;
520
521 /* find the relevant neigh according to the cached device and
522 * dst ip pair
523 */
524 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
525 if (!n) {
526 WARN(1, "The neighbour already freed\n");
527 return;
528 }
529
530 neigh_event_send(n, NULL);
531 neigh_release(n);
532 }
533}
534
d85cdccb
OG		 535static void mlx5e_detach_encap(struct mlx5e_priv *priv,
536 struct mlx5e_tc_flow *flow)
537{
5067b602
RD		 538 struct list_head *next = flow->encap.next;
539
540 list_del(&flow->encap);
541 if (list_empty(next)) {
c1ae1152 542 struct mlx5e_encap_entry *e;
5067b602 543
c1ae1152 544 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 545 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
546
547 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 548 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 549
cdc5a7f3 550 hash_del_rcu(&e->encap_hlist);
232c0013 551 kfree(e->encap_header);
5067b602
RD		 552 kfree(e);
553 }
554}
555
e8f887ac 556static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 557 struct mlx5e_tc_flow *flow)
e8f887ac 558{
d85cdccb
OG		 559 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
560 mlx5e_tc_del_fdb_flow(priv, flow);
561 else
562 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 563}
564
bbd00f7e
HHZ		 565static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
566 struct tc_cls_flower_offload *f)
567{
568 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
569 outer_headers);
570 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
571 outer_headers);
572 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
573 misc_parameters);
574 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
575 misc_parameters);
576
577 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
578 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
579
580 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
581 struct flow_dissector_key_keyid *key =
582 skb_flow_dissector_target(f->dissector,
583 FLOW_DISSECTOR_KEY_ENC_KEYID,
584 f->key);
585 struct flow_dissector_key_keyid *mask =
586 skb_flow_dissector_target(f->dissector,
587 FLOW_DISSECTOR_KEY_ENC_KEYID,
588 f->mask);
589 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
590 be32_to_cpu(mask->keyid));
591 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
592 be32_to_cpu(key->keyid));
593 }
594}
595
596static int parse_tunnel_attr(struct mlx5e_priv *priv,
597 struct mlx5_flow_spec *spec,
598 struct tc_cls_flower_offload *f)
599{
600 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
601 outer_headers);
602 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
603 outer_headers);
604
2e72eb43
OG		 605 struct flow_dissector_key_control *enc_control =
606 skb_flow_dissector_target(f->dissector,
607 FLOW_DISSECTOR_KEY_ENC_CONTROL,
608 f->key);
609
bbd00f7e
HHZ		 610 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
611 struct flow_dissector_key_ports *key =
612 skb_flow_dissector_target(f->dissector,
613 FLOW_DISSECTOR_KEY_ENC_PORTS,
614 f->key);
615 struct flow_dissector_key_ports *mask =
616 skb_flow_dissector_target(f->dissector,
617 FLOW_DISSECTOR_KEY_ENC_PORTS,
618 f->mask);
1ad9a00a 619 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4 620 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5ed99fb4 621 struct net_device *up_dev = uplink_rpriv->netdev;
1ad9a00a 622 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 623
624 /* Full udp dst port must be given */
625 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 626 goto vxlan_match_offload_err;
bbd00f7e 627
1ad9a00a 628 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 629 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
630 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 631 else {
632 netdev_warn(priv->netdev,
633 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 634 return -EOPNOTSUPP;
2fcd82e9 635 }
bbd00f7e
HHZ		 636
637 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
638 udp_dport, ntohs(mask->dst));
639 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
640 udp_dport, ntohs(key->dst));
641
cd377663
OG		 642 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
643 udp_sport, ntohs(mask->src));
644 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
645 udp_sport, ntohs(key->src));
bbd00f7e 646 } else { /* udp dst port must be given */
2fcd82e9
OG		 647vxlan_match_offload_err:
648 netdev_warn(priv->netdev,
649 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
650 return -EOPNOTSUPP;
bbd00f7e
HHZ		 651 }
652
2e72eb43 653 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 654 struct flow_dissector_key_ipv4_addrs *key =
655 skb_flow_dissector_target(f->dissector,
656 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
657 f->key);
658 struct flow_dissector_key_ipv4_addrs *mask =
659 skb_flow_dissector_target(f->dissector,
660 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
661 f->mask);
662 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
663 src_ipv4_src_ipv6.ipv4_layout.ipv4,
664 ntohl(mask->src));
665 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
666 src_ipv4_src_ipv6.ipv4_layout.ipv4,
667 ntohl(key->src));
668
669 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
670 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
671 ntohl(mask->dst));
672 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
673 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
674 ntohl(key->dst));
bbd00f7e 675
2e72eb43
OG		 676 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 678 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
679 struct flow_dissector_key_ipv6_addrs *key =
680 skb_flow_dissector_target(f->dissector,
681 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
682 f->key);
683 struct flow_dissector_key_ipv6_addrs *mask =
684 skb_flow_dissector_target(f->dissector,
685 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
686 f->mask);
687
688 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
689 src_ipv4_src_ipv6.ipv6_layout.ipv6),
690 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
691 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
692 src_ipv4_src_ipv6.ipv6_layout.ipv6),
693 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
694
695 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
696 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
697 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
698 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
699 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
700 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
701
702 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
703 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 704 }
bbd00f7e
HHZ		 705
706 /* Enforce DMAC when offloading incoming tunneled flows.
707 * Flow counters require a match on the DMAC.
708 */
709 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
710 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
711 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
712 dmac_47_16), priv->netdev->dev_addr);
713
714 /* let software handle IP fragments */
715 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
716 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
717
718 return 0;
719}
720
de0af0bf
RD		 721static int __parse_cls_flower(struct mlx5e_priv *priv,
722 struct mlx5_flow_spec *spec,
723 struct tc_cls_flower_offload *f,
724 u8 *min_inline)
e3a2b7ed 725{
c5bb1730
MG		 726 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
727 outer_headers);
728 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
729 outer_headers);
e3a2b7ed
AV		 730 u16 addr_type = 0;
731 u8 ip_proto = 0;
732
de0af0bf
RD		 733 *min_inline = MLX5_INLINE_MODE_L2;
734
e3a2b7ed
AV		 735 if (f->dissector->used_keys &
736 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
737 BIT(FLOW_DISSECTOR_KEY_BASIC) |
738 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 739 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 740 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
741 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 742 BIT(FLOW_DISSECTOR_KEY_PORTS) |
743 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
744 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
745 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
746 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 747 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 748 BIT(FLOW_DISSECTOR_KEY_TCP) |
749 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 750 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
751 f->dissector->used_keys);
752 return -EOPNOTSUPP;
753 }
754
bbd00f7e
HHZ		 755 if ((dissector_uses_key(f->dissector,
756 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
757 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
758 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
759 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
760 struct flow_dissector_key_control *key =
761 skb_flow_dissector_target(f->dissector,
762 FLOW_DISSECTOR_KEY_ENC_CONTROL,
763 f->key);
764 switch (key->addr_type) {
765 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 766 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 767 if (parse_tunnel_attr(priv, spec, f))
768 return -EOPNOTSUPP;
769 break;
770 default:
771 return -EOPNOTSUPP;
772 }
773
774 /* In decap flow, header pointers should point to the inner
775 * headers, outer header were already set by parse_tunnel_attr
776 */
777 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
778 inner_headers);
779 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
780 inner_headers);
781 }
782
e3a2b7ed
AV		 783 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
784 struct flow_dissector_key_control *key =
785 skb_flow_dissector_target(f->dissector,
1dbd0d37 786 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 787 f->key);
3f7d0eb4
OG		 788
789 struct flow_dissector_key_control *mask =
790 skb_flow_dissector_target(f->dissector,
791 FLOW_DISSECTOR_KEY_CONTROL,
792 f->mask);
e3a2b7ed 793 addr_type = key->addr_type;
3f7d0eb4
OG		 794
795 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
796 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
797 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
798 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG		 799
800 /* the HW doesn't need L3 inline to match on frag=no */
801 if (key->flags & FLOW_DIS_IS_FRAGMENT)
802 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 803 }
e3a2b7ed
AV		 804 }
805
806 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
807 struct flow_dissector_key_basic *key =
808 skb_flow_dissector_target(f->dissector,
809 FLOW_DISSECTOR_KEY_BASIC,
810 f->key);
811 struct flow_dissector_key_basic *mask =
812 skb_flow_dissector_target(f->dissector,
813 FLOW_DISSECTOR_KEY_BASIC,
814 f->mask);
815 ip_proto = key->ip_proto;
816
817 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
818 ntohs(mask->n_proto));
819 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
820 ntohs(key->n_proto));
821
822 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
823 mask->ip_proto);
824 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
825 key->ip_proto);
de0af0bf
RD		 826
827 if (mask->ip_proto)
828 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 829 }
830
831 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
832 struct flow_dissector_key_eth_addrs *key =
833 skb_flow_dissector_target(f->dissector,
834 FLOW_DISSECTOR_KEY_ETH_ADDRS,
835 f->key);
836 struct flow_dissector_key_eth_addrs *mask =
837 skb_flow_dissector_target(f->dissector,
838 FLOW_DISSECTOR_KEY_ETH_ADDRS,
839 f->mask);
840
841 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
842 dmac_47_16),
843 mask->dst);
844 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
845 dmac_47_16),
846 key->dst);
847
848 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
849 smac_47_16),
850 mask->src);
851 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
852 smac_47_16),
853 key->src);
854 }
855
095b6cfd
OG		 856 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
857 struct flow_dissector_key_vlan *key =
858 skb_flow_dissector_target(f->dissector,
859 FLOW_DISSECTOR_KEY_VLAN,
860 f->key);
861 struct flow_dissector_key_vlan *mask =
862 skb_flow_dissector_target(f->dissector,
863 FLOW_DISSECTOR_KEY_VLAN,
864 f->mask);
358d79a4 865 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 866 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
867 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 868
869 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
870 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 871
872 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
873 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG		 874 }
875 }
876
e3a2b7ed
AV		 877 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
878 struct flow_dissector_key_ipv4_addrs *key =
879 skb_flow_dissector_target(f->dissector,
880 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
881 f->key);
882 struct flow_dissector_key_ipv4_addrs *mask =
883 skb_flow_dissector_target(f->dissector,
884 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
885 f->mask);
886
887 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
888 src_ipv4_src_ipv6.ipv4_layout.ipv4),
889 &mask->src, sizeof(mask->src));
890 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
891 src_ipv4_src_ipv6.ipv4_layout.ipv4),
892 &key->src, sizeof(key->src));
893 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
894 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
895 &mask->dst, sizeof(mask->dst));
896 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
897 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
898 &key->dst, sizeof(key->dst));
de0af0bf
RD		 899
900 if (mask->src || mask->dst)
901 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 902 }
903
904 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
905 struct flow_dissector_key_ipv6_addrs *key =
906 skb_flow_dissector_target(f->dissector,
907 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
908 f->key);
909 struct flow_dissector_key_ipv6_addrs *mask =
910 skb_flow_dissector_target(f->dissector,
911 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
912 f->mask);
913
914 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
915 src_ipv4_src_ipv6.ipv6_layout.ipv6),
916 &mask->src, sizeof(mask->src));
917 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
918 src_ipv4_src_ipv6.ipv6_layout.ipv6),
919 &key->src, sizeof(key->src));
920
921 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
922 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
923 &mask->dst, sizeof(mask->dst));
924 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
925 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
926 &key->dst, sizeof(key->dst));
de0af0bf
RD		 927
928 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
929 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
930 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 931 }
932
1f97a526
OG		 933 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
934 struct flow_dissector_key_ip *key =
935 skb_flow_dissector_target(f->dissector,
936 FLOW_DISSECTOR_KEY_IP,
937 f->key);
938 struct flow_dissector_key_ip *mask =
939 skb_flow_dissector_target(f->dissector,
940 FLOW_DISSECTOR_KEY_IP,
941 f->mask);
942
943 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
944 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
945
946 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
947 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
948
a8ade55f
OG		 949 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
950 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 951
a8ade55f
OG		 952 if (mask->ttl &&
953 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
954 ft_field_support.outer_ipv4_ttl))
1f97a526 955 return -EOPNOTSUPP;
a8ade55f
OG		 956
957 if (mask->tos || mask->ttl)
958 *min_inline = MLX5_INLINE_MODE_IP;
1f97a526
OG		 959 }
960
e3a2b7ed
AV		 961 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
962 struct flow_dissector_key_ports *key =
963 skb_flow_dissector_target(f->dissector,
964 FLOW_DISSECTOR_KEY_PORTS,
965 f->key);
966 struct flow_dissector_key_ports *mask =
967 skb_flow_dissector_target(f->dissector,
968 FLOW_DISSECTOR_KEY_PORTS,
969 f->mask);
970 switch (ip_proto) {
971 case IPPROTO_TCP:
972 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
973 tcp_sport, ntohs(mask->src));
974 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
975 tcp_sport, ntohs(key->src));
976
977 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
978 tcp_dport, ntohs(mask->dst));
979 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
980 tcp_dport, ntohs(key->dst));
981 break;
982
983 case IPPROTO_UDP:
984 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
985 udp_sport, ntohs(mask->src));
986 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
987 udp_sport, ntohs(key->src));
988
989 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
990 udp_dport, ntohs(mask->dst));
991 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
992 udp_dport, ntohs(key->dst));
993 break;
994 default:
995 netdev_err(priv->netdev,
996 "Only UDP and TCP transport are supported\n");
997 return -EINVAL;
998 }
de0af0bf
RD		 999
1000 if (mask->src || mask->dst)
1001 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV		 1002 }
1003
e77834ec
OG		 1004 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1005 struct flow_dissector_key_tcp *key =
1006 skb_flow_dissector_target(f->dissector,
1007 FLOW_DISSECTOR_KEY_TCP,
1008 f->key);
1009 struct flow_dissector_key_tcp *mask =
1010 skb_flow_dissector_target(f->dissector,
1011 FLOW_DISSECTOR_KEY_TCP,
1012 f->mask);
1013
1014 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1015 ntohs(mask->flags));
1016 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1017 ntohs(key->flags));
1018
1019 if (mask->flags)
1020 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
1021 }
1022
e3a2b7ed
AV		 1023 return 0;
1024}
1025
de0af0bf 1026static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1027 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1028 struct mlx5_flow_spec *spec,
1029 struct tc_cls_flower_offload *f)
1030{
1031 struct mlx5_core_dev *dev = priv->mdev;
1032 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1033 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1034 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1035 u8 min_inline;
1036 int err;
1037
1038 err = __parse_cls_flower(priv, spec, f, &min_inline);
1039
1d447a39
SM		 1040 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1041 rep = rpriv->rep;
1042 if (rep->vport != FDB_UPLINK_VPORT &&
1043 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1044 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD		 1045 netdev_warn(priv->netdev,
1046 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1047 min_inline, esw->offloads.inline_mode);
1048 return -EOPNOTSUPP;
1049 }
1050 }
1051
1052 return err;
1053}
1054
d79b6df6
OG		 1055struct pedit_headers {
1056 struct ethhdr eth;
1057 struct iphdr ip4;
1058 struct ipv6hdr ip6;
1059 struct tcphdr tcp;
1060 struct udphdr udp;
1061};
1062
1063static int pedit_header_offsets[] = {
1064 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1065 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1066 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1067 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1068 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1069};
1070
1071#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1072
1073static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1074 struct pedit_headers *masks,
1075 struct pedit_headers *vals)
1076{
1077 u32 *curr_pmask, *curr_pval;
1078
1079 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1080 goto out_err;
1081
1082 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1083 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1084
1085 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1086 goto out_err;
1087
1088 *curr_pmask |= mask;
1089 *curr_pval |= (val & mask);
1090
1091 return 0;
1092
1093out_err:
1094 return -EOPNOTSUPP;
1095}
1096
1097struct mlx5_fields {
1098 u8 field;
1099 u8 size;
1100 u32 offset;
1101};
1102
a8e4f0c4
OG		 1103#define OFFLOAD(fw_field, size, field, off) \
1104 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1105
d79b6df6 1106static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1107 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1108 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1109 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1110 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1111 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1112 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1113
1114 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1115 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1116 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1117
1118 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1119 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1120 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1121 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1122 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1123 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1124 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1125 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1126 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1127
1128 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1129 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1130 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1131
1132 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1133 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1134};
1135
1136/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1137 * max from the SW pedit action. On success, it says how many HW actions were
1138 * actually parsed.
1139 */
1140static int offload_pedit_fields(struct pedit_headers *masks,
1141 struct pedit_headers *vals,
1142 struct mlx5e_tc_flow_parse_attr *parse_attr)
1143{
1144 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1145 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1146 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1147 struct mlx5_fields *f;
1148 u8 cmd, field_bsize;
e3ca4e05 1149 u32 s_mask, a_mask;
d79b6df6 1150 unsigned long mask;
2b64beba
OG		 1151 __be32 mask_be32;
1152 __be16 mask_be16;
d79b6df6
OG		 1153 void *action;
1154
1155 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1156 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1157 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1158 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1159
1160 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1161 action = parse_attr->mod_hdr_actions;
1162 max_actions = parse_attr->num_mod_hdr_actions;
1163 nactions = 0;
1164
1165 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1166 f = &fields[i];
1167 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1168 s_mask = 0;
1169 a_mask = 0;
d79b6df6
OG		 1170
1171 s_masks_p = (void *)set_masks + f->offset;
1172 a_masks_p = (void *)add_masks + f->offset;
1173
1174 memcpy(&s_mask, s_masks_p, f->size);
1175 memcpy(&a_mask, a_masks_p, f->size);
1176
1177 if (!s_mask && !a_mask) /* nothing to offload here */
1178 continue;
1179
1180 if (s_mask && a_mask) {
1181 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1182 return -EOPNOTSUPP;
1183 }
1184
1185 if (nactions == max_actions) {
1186 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1187 return -EOPNOTSUPP;
1188 }
1189
1190 if (s_mask) {
1191 cmd = MLX5_ACTION_TYPE_SET;
1192 mask = s_mask;
1193 vals_p = (void *)set_vals + f->offset;
1194 /* clear to denote we consumed this field */
1195 memset(s_masks_p, 0, f->size);
1196 } else {
1197 cmd = MLX5_ACTION_TYPE_ADD;
1198 mask = a_mask;
1199 vals_p = (void *)add_vals + f->offset;
1200 /* clear to denote we consumed this field */
1201 memset(a_masks_p, 0, f->size);
1202 }
1203
d79b6df6 1204 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1205
2b64beba
OG		 1206 if (field_bsize == 32) {
1207 mask_be32 = *(__be32 *)&mask;
1208 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1209 } else if (field_bsize == 16) {
1210 mask_be16 = *(__be16 *)&mask;
1211 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1212 }
1213
d79b6df6 1214 first = find_first_bit(&mask, field_bsize);
2b64beba 1215 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1216 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1217 if (first < next_z && next_z < last) {
1218 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1219 mask);
1220 return -EOPNOTSUPP;
1221 }
1222
1223 MLX5_SET(set_action_in, action, action_type, cmd);
1224 MLX5_SET(set_action_in, action, field, f->field);
1225
1226 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1227 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1228 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1229 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1230 }
1231
1232 if (field_bsize == 32)
2b64beba 1233 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1234 else if (field_bsize == 16)
2b64beba 1235 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1236 else if (field_bsize == 8)
2b64beba 1237 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1238
1239 action += action_size;
1240 nactions++;
1241 }
1242
1243 parse_attr->num_mod_hdr_actions = nactions;
1244 return 0;
1245}
1246
1247static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1248 const struct tc_action *a, int namespace,
1249 struct mlx5e_tc_flow_parse_attr *parse_attr)
1250{
1251 int nkeys, action_size, max_actions;
1252
1253 nkeys = tcf_pedit_nkeys(a);
1254 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1255
1256 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1257 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1258 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1259 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1260
1261 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1262 max_actions = min(max_actions, nkeys * 16);
1263
1264 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1265 if (!parse_attr->mod_hdr_actions)
1266 return -ENOMEM;
1267
1268 parse_attr->num_mod_hdr_actions = max_actions;
1269 return 0;
1270}
1271
1272static const struct pedit_headers zero_masks = {};
1273
1274static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1275 const struct tc_action *a, int namespace,
1276 struct mlx5e_tc_flow_parse_attr *parse_attr)
1277{
1278 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1279 int nkeys, i, err = -EOPNOTSUPP;
1280 u32 mask, val, offset;
1281 u8 cmd, htype;
1282
1283 nkeys = tcf_pedit_nkeys(a);
1284
1285 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1286 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1287
1288 for (i = 0; i < nkeys; i++) {
1289 htype = tcf_pedit_htype(a, i);
1290 cmd = tcf_pedit_cmd(a, i);
1291 err = -EOPNOTSUPP; /* can't be all optimistic */
1292
1293 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1294 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1295 goto out_err;
1296 }
1297
1298 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1299 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1300 goto out_err;
1301 }
1302
1303 mask = tcf_pedit_mask(a, i);
1304 val = tcf_pedit_val(a, i);
1305 offset = tcf_pedit_offset(a, i);
1306
1307 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1308 if (err)
1309 goto out_err;
1310 }
1311
1312 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1313 if (err)
1314 goto out_err;
1315
1316 err = offload_pedit_fields(masks, vals, parse_attr);
1317 if (err < 0)
1318 goto out_dealloc_parsed_actions;
1319
1320 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1321 cmd_masks = &masks[cmd];
1322 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1323 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1324 cmd);
1325 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1326 16, 1, cmd_masks, sizeof(zero_masks), true);
1327 err = -EOPNOTSUPP;
1328 goto out_dealloc_parsed_actions;
1329 }
1330 }
1331
1332 return 0;
1333
1334out_dealloc_parsed_actions:
1335 kfree(parse_attr->mod_hdr_actions);
1336out_err:
1337 return err;
1338}
1339
26c02749
OG		 1340static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1341{
1342 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1343 TCA_CSUM_UPDATE_FLAG_UDP;
1344
1345 /* The HW recalcs checksums only if re-writing headers */
1346 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1347 netdev_warn(priv->netdev,
1348 "TC csum action is only offloaded with pedit\n");
1349 return false;
1350 }
1351
1352 if (update_flags & ~prot_flags) {
1353 netdev_warn(priv->netdev,
1354 "can't offload TC csum action for some header/s - flags %#x\n",
1355 update_flags);
1356 return false;
1357 }
1358
1359 return true;
1360}
1361
bdd66ac0
OG		 1362static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1363 struct tcf_exts *exts)
1364{
1365 const struct tc_action *a;
1366 bool modify_ip_header;
1367 LIST_HEAD(actions);
1368 u8 htype, ip_proto;
1369 void *headers_v;
1370 u16 ethertype;
1371 int nkeys, i;
1372
1373 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1374 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1375
1376 /* for non-IP we only re-write MACs, so we're okay */
1377 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1378 goto out_ok;
1379
1380 modify_ip_header = false;
1381 tcf_exts_to_list(exts, &actions);
1382 list_for_each_entry(a, &actions, list) {
1383 if (!is_tcf_pedit(a))
1384 continue;
1385
1386 nkeys = tcf_pedit_nkeys(a);
1387 for (i = 0; i < nkeys; i++) {
1388 htype = tcf_pedit_htype(a, i);
1389 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1390 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1391 modify_ip_header = true;
1392 break;
1393 }
1394 }
1395 }
1396
1397 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1398 if (modify_ip_header && ip_proto != IPPROTO_TCP && ip_proto != IPPROTO_UDP) {
1399 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1400 return false;
1401 }
1402
1403out_ok:
1404 return true;
1405}
1406
1407static bool actions_match_supported(struct mlx5e_priv *priv,
1408 struct tcf_exts *exts,
1409 struct mlx5e_tc_flow_parse_attr *parse_attr,
1410 struct mlx5e_tc_flow *flow)
1411{
1412 u32 actions;
1413
1414 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1415 actions = flow->esw_attr->action;
1416 else
1417 actions = flow->nic_attr->action;
1418
1419 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1420 return modify_header_match_supported(&parse_attr->spec, exts);
1421
1422 return true;
1423}
1424
5c40348c 1425static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1426 struct mlx5e_tc_flow_parse_attr *parse_attr,
1427 struct mlx5e_tc_flow *flow)
e3a2b7ed 1428{
aa0cbbae 1429 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1430 const struct tc_action *a;
22dc13c8 1431 LIST_HEAD(actions);
2f4fe4ca 1432 int err;
e3a2b7ed 1433
3bcc0cec 1434 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 1435 return -EINVAL;
1436
3bc4b7bf
OG		 1437 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1438 attr->action = 0;
e3a2b7ed 1439
22dc13c8
WC		 1440 tcf_exts_to_list(exts, &actions);
1441 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1442 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1443 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1444 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1445 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1446 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1447 continue;
1448 }
1449
2f4fe4ca
OG		 1450 if (is_tcf_pedit(a)) {
1451 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1452 parse_attr);
1453 if (err)
1454 return err;
1455
1456 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1457 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1458 continue;
1459 }
1460
26c02749
OG		 1461 if (is_tcf_csum(a)) {
1462 if (csum_offload_supported(priv, attr->action,
1463 tcf_csum_update_flags(a)))
1464 continue;
1465
1466 return -EOPNOTSUPP;
1467 }
1468
e3a2b7ed
AV		 1469 if (is_tcf_skbedit_mark(a)) {
1470 u32 mark = tcf_skbedit_mark(a);
1471
1472 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1473 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1474 mark);
1475 return -EINVAL;
1476 }
1477
3bc4b7bf
OG		 1478 attr->flow_tag = mark;
1479 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 1480 continue;
1481 }
1482
1483 return -EINVAL;
1484 }
1485
bdd66ac0
OG		 1486 if (!actions_match_supported(priv, exts, parse_attr, flow))
1487 return -EOPNOTSUPP;
1488
e3a2b7ed
AV		 1489 return 0;
1490}
1491
76f7444d
OG		 1492static inline int cmp_encap_info(struct ip_tunnel_key *a,
1493 struct ip_tunnel_key *b)
a54e20b4
HHZ		 1494{
1495 return memcmp(a, b, sizeof(*a));
1496}
1497
76f7444d 1498static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1499{
76f7444d 1500 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 1501}
1502
1503static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1504 struct net_device *mirred_dev,
1505 struct net_device **out_dev,
1506 struct flowi4 *fl4,
1507 struct neighbour **out_n,
a54e20b4
HHZ		 1508 int *out_ttl)
1509{
3e621b19 1510 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 1511 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 1512 struct rtable *rt;
1513 struct neighbour *n = NULL;
a54e20b4
HHZ		 1514
1515#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 1516 int ret;
1517
a54e20b4 1518 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 1519 ret = PTR_ERR_OR_ZERO(rt);
1520 if (ret)
1521 return ret;
a54e20b4
HHZ		 1522#else
1523 return -EOPNOTSUPP;
1524#endif
a4b97ab4 1525 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 1526 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1527 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 1528 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 1529 else
1530 *out_dev = rt->dst.dev;
a54e20b4 1531
75c33da8 1532 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 1533 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1534 ip_rt_put(rt);
1535 if (!n)
1536 return -ENOMEM;
1537
1538 *out_n = n;
a54e20b4
HHZ		 1539 return 0;
1540}
1541
ce99f6b9
OG		 1542static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1543 struct net_device *mirred_dev,
1544 struct net_device **out_dev,
1545 struct flowi6 *fl6,
1546 struct neighbour **out_n,
1547 int *out_ttl)
1548{
1549 struct neighbour *n = NULL;
1550 struct dst_entry *dst;
1551
1552#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 1553 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 1554 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1555 int ret;
1556
08820528
PB		 1557 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
1558 fl6);
1559 if (ret < 0)
ce99f6b9 1560 return ret;
ce99f6b9
OG		 1561
1562 *out_ttl = ip6_dst_hoplimit(dst);
1563
a4b97ab4 1564 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 1565 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1566 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 1567 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 1568 else
1569 *out_dev = dst->dev;
1570#else
1571 return -EOPNOTSUPP;
1572#endif
1573
1574 n = dst_neigh_lookup(dst, &fl6->daddr);
1575 dst_release(dst);
1576 if (!n)
1577 return -ENOMEM;
1578
1579 *out_n = n;
1580 return 0;
1581}
1582
32f3671f
OG		 1583static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1584 char buf[], int encap_size,
1585 unsigned char h_dest[ETH_ALEN],
1586 int ttl,
1587 __be32 daddr,
1588 __be32 saddr,
1589 __be16 udp_dst_port,
1590 __be32 vx_vni)
a54e20b4 1591{
a54e20b4
HHZ		 1592 struct ethhdr *eth = (struct ethhdr *)buf;
1593 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1594 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1595 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1596
1597 memset(buf, 0, encap_size);
1598
1599 ether_addr_copy(eth->h_dest, h_dest);
1600 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1601 eth->h_proto = htons(ETH_P_IP);
1602
1603 ip->daddr = daddr;
1604 ip->saddr = saddr;
1605
1606 ip->ttl = ttl;
1607 ip->protocol = IPPROTO_UDP;
1608 ip->version = 0x4;
1609 ip->ihl = 0x5;
1610
1611 udp->dest = udp_dst_port;
1612 vxh->vx_flags = VXLAN_HF_VNI;
1613 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 1614}
1615
225aabaf
OG		 1616static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1617 char buf[], int encap_size,
1618 unsigned char h_dest[ETH_ALEN],
1619 int ttl,
1620 struct in6_addr *daddr,
1621 struct in6_addr *saddr,
1622 __be16 udp_dst_port,
1623 __be32 vx_vni)
ce99f6b9 1624{
ce99f6b9
OG		 1625 struct ethhdr *eth = (struct ethhdr *)buf;
1626 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1627 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1628 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1629
1630 memset(buf, 0, encap_size);
1631
1632 ether_addr_copy(eth->h_dest, h_dest);
1633 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1634 eth->h_proto = htons(ETH_P_IPV6);
1635
1636 ip6_flow_hdr(ip6h, 0, 0);
1637 /* the HW fills up ipv6 payload len */
1638 ip6h->nexthdr = IPPROTO_UDP;
1639 ip6h->hop_limit = ttl;
1640 ip6h->daddr = *daddr;
1641 ip6h->saddr = *saddr;
1642
1643 udp->dest = udp_dst_port;
1644 vxh->vx_flags = VXLAN_HF_VNI;
1645 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 1646}
1647
a54e20b4
HHZ		 1648static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1649 struct net_device *mirred_dev,
1a8552bd 1650 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 1651{
1652 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1653 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1654 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1655 struct net_device *out_dev;
a42485eb 1656 struct neighbour *n = NULL;
a54e20b4 1657 struct flowi4 fl4 = {};
a54e20b4 1658 char *encap_header;
32f3671f 1659 int ttl, err;
033354d5 1660 u8 nud_state;
32f3671f
OG		 1661
1662 if (max_encap_size < ipv4_encap_size) {
1663 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1664 ipv4_encap_size, max_encap_size);
1665 return -EOPNOTSUPP;
1666 }
a54e20b4 1667
32f3671f 1668 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 1669 if (!encap_header)
1670 return -ENOMEM;
1671
1672 switch (e->tunnel_type) {
1673 case MLX5_HEADER_TYPE_VXLAN:
1674 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1675 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 1676 break;
1677 default:
1678 err = -EOPNOTSUPP;
ace74321 1679 goto free_encap;
a54e20b4 1680 }
9a941117 1681 fl4.flowi4_tos = tun_key->tos;
76f7444d 1682 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1683 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1684
1a8552bd 1685 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1686 &fl4, &n, &ttl);
a54e20b4 1687 if (err)
ace74321 1688 goto free_encap;
a54e20b4 1689
232c0013
HHZ		 1690 /* used by mlx5e_detach_encap to lookup a neigh hash table
1691 * entry in the neigh hash table when a user deletes a rule
1692 */
1693 e->m_neigh.dev = n->dev;
f6dfb4c3 1694 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 1695 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1696 e->out_dev = out_dev;
1697
1698 /* It's importent to add the neigh to the hash table before checking
1699 * the neigh validity state. So if we'll get a notification, in case the
1700 * neigh changes it's validity state, we would find the relevant neigh
1701 * in the hash.
1702 */
1703 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1704 if (err)
ace74321 1705 goto free_encap;
232c0013 1706
033354d5
HHZ		 1707 read_lock_bh(&n->lock);
1708 nud_state = n->nud_state;
1709 ether_addr_copy(e->h_dest, n->ha);
1710 read_unlock_bh(&n->lock);
1711
a54e20b4
HHZ		 1712 switch (e->tunnel_type) {
1713 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1714 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 1715 ipv4_encap_size, e->h_dest, ttl,
1716 fl4.daddr,
1717 fl4.saddr, tun_key->tp_dst,
1718 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 1719 break;
1720 default:
1721 err = -EOPNOTSUPP;
232c0013
HHZ		 1722 goto destroy_neigh_entry;
1723 }
1724 e->encap_size = ipv4_encap_size;
1725 e->encap_header = encap_header;
1726
1727 if (!(nud_state & NUD_VALID)) {
1728 neigh_event_send(n, NULL);
27902f08
WY		 1729 err = -EAGAIN;
1730 goto out;
a54e20b4
HHZ		 1731 }
1732
1733 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1734 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 1735 if (err)
1736 goto destroy_neigh_entry;
1737
1738 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1739 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 1740 neigh_release(n);
1741 return err;
1742
1743destroy_neigh_entry:
1744 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 1745free_encap:
a54e20b4 1746 kfree(encap_header);
ace74321 1747out:
232c0013
HHZ		 1748 if (n)
1749 neigh_release(n);
a54e20b4
HHZ		 1750 return err;
1751}
1752
ce99f6b9
OG		 1753static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1754 struct net_device *mirred_dev,
1a8552bd 1755 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 1756{
1757 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1758 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1759 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1760 struct net_device *out_dev;
ce99f6b9
OG		 1761 struct neighbour *n = NULL;
1762 struct flowi6 fl6 = {};
1763 char *encap_header;
225aabaf 1764 int err, ttl = 0;
033354d5 1765 u8 nud_state;
ce99f6b9 1766
225aabaf
OG		 1767 if (max_encap_size < ipv6_encap_size) {
1768 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1769 ipv6_encap_size, max_encap_size);
1770 return -EOPNOTSUPP;
1771 }
ce99f6b9 1772
225aabaf 1773 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 1774 if (!encap_header)
1775 return -ENOMEM;
1776
1777 switch (e->tunnel_type) {
1778 case MLX5_HEADER_TYPE_VXLAN:
1779 fl6.flowi6_proto = IPPROTO_UDP;
1780 fl6.fl6_dport = tun_key->tp_dst;
1781 break;
1782 default:
1783 err = -EOPNOTSUPP;
ace74321 1784 goto free_encap;
ce99f6b9
OG		 1785 }
1786
1787 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1788 fl6.daddr = tun_key->u.ipv6.dst;
1789 fl6.saddr = tun_key->u.ipv6.src;
1790
1a8552bd 1791 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 1792 &fl6, &n, &ttl);
1793 if (err)
ace74321 1794 goto free_encap;
ce99f6b9 1795
232c0013
HHZ		 1796 /* used by mlx5e_detach_encap to lookup a neigh hash table
1797 * entry in the neigh hash table when a user deletes a rule
1798 */
1799 e->m_neigh.dev = n->dev;
f6dfb4c3 1800 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 1801 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1802 e->out_dev = out_dev;
1803
1804 /* It's importent to add the neigh to the hash table before checking
1805 * the neigh validity state. So if we'll get a notification, in case the
1806 * neigh changes it's validity state, we would find the relevant neigh
1807 * in the hash.
1808 */
1809 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1810 if (err)
ace74321 1811 goto free_encap;
232c0013 1812
033354d5
HHZ		 1813 read_lock_bh(&n->lock);
1814 nud_state = n->nud_state;
1815 ether_addr_copy(e->h_dest, n->ha);
1816 read_unlock_bh(&n->lock);
1817
ce99f6b9
OG		 1818 switch (e->tunnel_type) {
1819 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1820 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 1821 ipv6_encap_size, e->h_dest, ttl,
1822 &fl6.daddr,
1823 &fl6.saddr, tun_key->tp_dst,
1824 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 1825 break;
1826 default:
1827 err = -EOPNOTSUPP;
232c0013
HHZ		 1828 goto destroy_neigh_entry;
1829 }
1830
1831 e->encap_size = ipv6_encap_size;
1832 e->encap_header = encap_header;
1833
1834 if (!(nud_state & NUD_VALID)) {
1835 neigh_event_send(n, NULL);
27902f08
WY		 1836 err = -EAGAIN;
1837 goto out;
ce99f6b9
OG		 1838 }
1839
1840 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1841 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 1842 if (err)
1843 goto destroy_neigh_entry;
1844
1845 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1846 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 1847 neigh_release(n);
1848 return err;
1849
1850destroy_neigh_entry:
1851 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 1852free_encap:
ce99f6b9 1853 kfree(encap_header);
ace74321 1854out:
232c0013
HHZ		 1855 if (n)
1856 neigh_release(n);
ce99f6b9
OG		 1857 return err;
1858}
1859
a54e20b4
HHZ		 1860static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1861 struct ip_tunnel_info *tun_info,
1862 struct net_device *mirred_dev,
45247bf2
OG		 1863 struct net_device **encap_dev,
1864 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 1865{
1866 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4
MB		 1867 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
1868 REP_ETH);
5ed99fb4 1869 struct net_device *up_dev = uplink_rpriv->netdev;
a54e20b4 1870 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 1871 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1872 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 1873 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 1874 struct mlx5e_encap_entry *e;
45247bf2 1875 int tunnel_type, err = 0;
a54e20b4
HHZ		 1876 uintptr_t hash_key;
1877 bool found = false;
a54e20b4 1878
2fcd82e9 1879 /* udp dst port must be set */
a54e20b4 1880 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1881 goto vxlan_encap_offload_err;
a54e20b4 1882
cd377663 1883 /* setting udp src port isn't supported */
2fcd82e9
OG		 1884 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1885vxlan_encap_offload_err:
1886 netdev_warn(priv->netdev,
1887 "must set udp dst port and not set udp src port\n");
cd377663 1888 return -EOPNOTSUPP;
2fcd82e9 1889 }
cd377663 1890
1ad9a00a 1891 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1892 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 1893 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1894 } else {
2fcd82e9
OG		 1895 netdev_warn(priv->netdev,
1896 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 1897 return -EOPNOTSUPP;
1898 }
1899
76f7444d 1900 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 1901
1902 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1903 encap_hlist, hash_key) {
76f7444d 1904 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 1905 found = true;
1906 break;
1907 }
1908 }
1909
b2812089 1910 /* must verify if encap is valid or not */
45247bf2
OG		 1911 if (found)
1912 goto attach_flow;
a54e20b4
HHZ		 1913
1914 e = kzalloc(sizeof(*e), GFP_KERNEL);
1915 if (!e)
1916 return -ENOMEM;
1917
76f7444d 1918 e->tun_info = *tun_info;
a54e20b4
HHZ		 1919 e->tunnel_type = tunnel_type;
1920 INIT_LIST_HEAD(&e->flows);
1921
ce99f6b9 1922 if (family == AF_INET)
1a8552bd 1923 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 1924 else if (family == AF_INET6)
1a8552bd 1925 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 1926
232c0013 1927 if (err && err != -EAGAIN)
a54e20b4
HHZ		 1928 goto out_err;
1929
a54e20b4
HHZ		 1930 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1931
45247bf2
OG		 1932attach_flow:
1933 list_add(&flow->encap, &e->flows);
1934 *encap_dev = e->out_dev;
232c0013
HHZ		 1935 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1936 attr->encap_id = e->encap_id;
b2812089
VB		 1937 else
1938 err = -EAGAIN;
45247bf2 1939
232c0013 1940 return err;
a54e20b4
HHZ		 1941
1942out_err:
1943 kfree(e);
1944 return err;
1945}
1946
03a9d11e 1947static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1948 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1949 struct mlx5e_tc_flow *flow)
03a9d11e 1950{
ecf5bb79 1951 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1952 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1953 struct ip_tunnel_info *info = NULL;
03a9d11e 1954 const struct tc_action *a;
22dc13c8 1955 LIST_HEAD(actions);
a54e20b4 1956 bool encap = false;
232c0013 1957 int err = 0;
03a9d11e 1958
3bcc0cec 1959 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 1960 return -EINVAL;
1961
776b12b6 1962 memset(attr, 0, sizeof(*attr));
1d447a39 1963 attr->in_rep = rpriv->rep;
03a9d11e 1964
22dc13c8
WC		 1965 tcf_exts_to_list(exts, &actions);
1966 list_for_each_entry(a, &actions, list) {
03a9d11e 1967 if (is_tcf_gact_shot(a)) {
8b32580d
OG		 1968 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1969 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 1970 continue;
1971 }
1972
d7e75a32
OG		 1973 if (is_tcf_pedit(a)) {
1974 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1975 parse_attr);
1976 if (err)
1977 return err;
1978
1979 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1980 continue;
1981 }
1982
26c02749
OG		 1983 if (is_tcf_csum(a)) {
1984 if (csum_offload_supported(priv, attr->action,
1985 tcf_csum_update_flags(a)))
1986 continue;
1987
1988 return -EOPNOTSUPP;
1989 }
1990
5724b8b5 1991 if (is_tcf_mirred_egress_redirect(a)) {
3c37745e 1992 struct net_device *out_dev;
03a9d11e 1993 struct mlx5e_priv *out_priv;
03a9d11e 1994
9f8a739e 1995 out_dev = tcf_mirred_dev(a);
03a9d11e 1996
a54e20b4
HHZ		 1997 if (switchdev_port_same_parent_id(priv->netdev,
1998 out_dev)) {
1999 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2000 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2001 out_priv = netdev_priv(out_dev);
1d447a39
SM		 2002 rpriv = out_priv->ppriv;
2003 attr->out_rep = rpriv->rep;
a54e20b4 2004 } else if (encap) {
9f8a739e 2005 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2006 parse_attr->tun_info = *info;
2007 attr->parse_attr = parse_attr;
a54e20b4
HHZ		 2008 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2009 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2010 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2011 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2012 } else {
03a9d11e
OG		 2013 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2014 priv->netdev->name, out_dev->name);
2015 return -EINVAL;
2016 }
a54e20b4
HHZ		 2017 continue;
2018 }
03a9d11e 2019
a54e20b4
HHZ		 2020 if (is_tcf_tunnel_set(a)) {
2021 info = tcf_tunnel_info(a);
2022 if (info)
2023 encap = true;
2024 else
2025 return -EOPNOTSUPP;
03a9d11e
OG		 2026 continue;
2027 }
2028
8b32580d 2029 if (is_tcf_vlan(a)) {
09c91ddf 2030 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 2031 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 2032 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG		 2033 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
2034 return -EOPNOTSUPP;
2035
2036 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2037 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG		 2038 } else { /* action is TCA_VLAN_ACT_MODIFY */
2039 return -EOPNOTSUPP;
8b32580d
OG		 2040 }
2041 continue;
2042 }
2043
bbd00f7e
HHZ		 2044 if (is_tcf_tunnel_release(a)) {
2045 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2046 continue;
2047 }
2048
03a9d11e
OG		 2049 return -EINVAL;
2050 }
bdd66ac0
OG		 2051
2052 if (!actions_match_supported(priv, exts, parse_attr, flow))
2053 return -EOPNOTSUPP;
2054
232c0013 2055 return err;
03a9d11e
OG		 2056}
2057
5fd9fc4e 2058int mlx5e_configure_flower(struct mlx5e_priv *priv,
e3a2b7ed
AV		 2059 struct tc_cls_flower_offload *f)
2060{
3bc4b7bf 2061 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2062 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 2063 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 2064 struct mlx5e_tc_flow *flow;
2065 int attr_size, err = 0;
65ba8fb7 2066 u8 flow_flags = 0;
e3a2b7ed 2067
65ba8fb7
OG		 2068 if (esw && esw->mode == SRIOV_OFFLOADS) {
2069 flow_flags = MLX5E_TC_FLOW_ESWITCH;
2070 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 2071 } else {
2072 flow_flags = MLX5E_TC_FLOW_NIC;
2073 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2074 }
e3a2b7ed 2075
65ba8fb7 2076 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2077 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2078 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2079 err = -ENOMEM;
2080 goto err_free;
2081 }
2082
2083 flow->cookie = f->cookie;
65ba8fb7 2084 flow->flags = flow_flags;
e3a2b7ed 2085
17091853 2086 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2087 if (err < 0)
2088 goto err_free;
2089
65ba8fb7 2090 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 2091 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 2092 if (err < 0)
3c37745e 2093 goto err_free;
aa0cbbae 2094 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 2095 } else {
aa0cbbae 2096 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 2097 if (err < 0)
2098 goto err_free;
aa0cbbae 2099 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 2100 }
e3a2b7ed 2101
e3a2b7ed
AV		 2102 if (IS_ERR(flow->rule)) {
2103 err = PTR_ERR(flow->rule);
3c37745e
OG		 2104 if (err != -EAGAIN)
2105 goto err_free;
e3a2b7ed
AV		 2106 }
2107
3c37745e
OG		 2108 if (err != -EAGAIN)
2109 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2110
5c40348c
OG		 2111 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2112 tc->ht_params);
2113 if (err)
2114 goto err_del_rule;
2115
232c0013
HHZ		 2116 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
2117 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2118 kvfree(parse_attr);
2119 return err;
e3a2b7ed 2120
5c40348c 2121err_del_rule:
5e86397a 2122 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2123
2124err_free:
17091853 2125 kvfree(parse_attr);
232c0013 2126 kfree(flow);
e3a2b7ed
AV		 2127 return err;
2128}
2129
2130int mlx5e_delete_flower(struct mlx5e_priv *priv,
2131 struct tc_cls_flower_offload *f)
2132{
2133 struct mlx5e_tc_flow *flow;
acff797c 2134 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2135
2136 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2137 tc->ht_params);
2138 if (!flow)
2139 return -EINVAL;
2140
2141 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2142
961e8979 2143 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2144
2145 kfree(flow);
2146
2147 return 0;
2148}
2149
aad7e08d
AV		 2150int mlx5e_stats_flower(struct mlx5e_priv *priv,
2151 struct tc_cls_flower_offload *f)
2152{
2153 struct mlx5e_tc_table *tc = &priv->fs.tc;
2154 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2155 struct mlx5_fc *counter;
2156 u64 bytes;
2157 u64 packets;
2158 u64 lastuse;
2159
2160 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2161 tc->ht_params);
2162 if (!flow)
2163 return -EINVAL;
2164
0b67a38f
HHZ		 2165 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2166 return 0;
2167
aad7e08d
AV		 2168 counter = mlx5_flow_rule_counter(flow->rule);
2169 if (!counter)
2170 return 0;
2171
2172 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2173
d897a638 2174 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2175
aad7e08d
AV		 2176 return 0;
2177}
2178
e8f887ac
AV		 2179static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2180 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2181 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2182 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2183 .automatic_shrinking = true,
2184};
2185
2186int mlx5e_tc_init(struct mlx5e_priv *priv)
2187{
acff797c 2188 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2189
11c9c548
OG		 2190 hash_init(tc->mod_hdr_tbl);
2191
e8f887ac
AV		 2192 tc->ht_params = mlx5e_tc_flow_ht_params;
2193 return rhashtable_init(&tc->ht, &tc->ht_params);
2194}
2195
2196static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2197{
2198 struct mlx5e_tc_flow *flow = ptr;
2199 struct mlx5e_priv *priv = arg;
2200
961e8979 2201 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2202 kfree(flow);
2203}
2204
2205void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2206{
acff797c 2207 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2208
2209 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2210
acff797c
MG		 2211 if (!IS_ERR_OR_NULL(tc->t)) {
2212 mlx5_destroy_flow_table(tc->t);
2213 tc->t = NULL;
e8f887ac
AV		 2214 }
2215}
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