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net/mlx5e: Make the log friendly when decapsulation offload not supported
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e 41#include <net/tc_act/tc_mirred.h>
776b12b6 42#include <net/tc_act/tc_vlan.h>
bbd00f7e 43#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 44#include <net/tc_act/tc_pedit.h>
26c02749 45#include <net/tc_act/tc_csum.h>
f6dfb4c3 46#include <net/arp.h>
3616d08b 47#include <net/ipv6_stubs.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
3f6d08d1 52#include "fs_core.h"
2c81bfd5 53#include "en/port.h"
101f4de9 54#include "en/tc_tun.h"
04de7dda 55#include "lib/devcom.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
d9ee0491
OG		 72 MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD,
73 MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD,
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2),
77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3),
78 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4),
ef06c9ee 79 MLX5E_TC_FLOW_NOT_READY = BIT(MLX5E_TC_FLOW_BASE + 5),
65ba8fb7
OG		 80};
81
e4ad91f2
CM		 82#define MLX5E_TC_MAX_SPLITS 1
83
79baaec7
EB		 84/* Helper struct for accessing a struct containing list_head array.
85 * Containing struct
86 * |- Helper array
87 * [0] Helper item 0
88 * |- list_head item 0
89 * |- index (0)
90 * [1] Helper item 1
91 * |- list_head item 1
92 * |- index (1)
93 * To access the containing struct from one of the list_head items:
94 * 1. Get the helper item from the list_head item using
95 * helper item =
96 * container_of(list_head item, helper struct type, list_head field)
97 * 2. Get the contining struct from the helper item and its index in the array:
98 * containing struct =
99 * container_of(helper item, containing struct type, helper field[index])
100 */
101struct encap_flow_item {
102 struct list_head list;
103 int index;
104};
105
e8f887ac
AV		 106struct mlx5e_tc_flow {
107 struct rhash_head node;
655dc3d2 108 struct mlx5e_priv *priv;
e8f887ac 109 u64 cookie;
5dbe906f 110 u16 flags;
e4ad91f2 111 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 112 /* Flow can be associated with multiple encap IDs.
113 * The number of encaps is bounded by the number of supported
114 * destinations.
115 */
116 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 117 struct mlx5e_tc_flow *peer_flow;
11c9c548 118 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 119 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 120 struct list_head peer; /* flows with peer flow */
b4a23329 121 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
3bc4b7bf
OG		 122 union {
123 struct mlx5_esw_flow_attr esw_attr[0];
124 struct mlx5_nic_flow_attr nic_attr[0];
125 };
e8f887ac
AV		 126};
127
17091853 128struct mlx5e_tc_flow_parse_attr {
98b66cb1 129 struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 130 struct net_device *filter_dev;
17091853 131 struct mlx5_flow_spec spec;
d79b6df6 132 int num_mod_hdr_actions;
218d05ce 133 int max_mod_hdr_actions;
d79b6df6 134 void *mod_hdr_actions;
98b66cb1 135 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 136};
137
acff797c 138#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 139#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 140
77ab67b7
OG		 141struct mlx5e_hairpin {
142 struct mlx5_hairpin *pair;
143
144 struct mlx5_core_dev *func_mdev;
3f6d08d1 145 struct mlx5e_priv *func_priv;
77ab67b7
OG		 146 u32 tdn;
147 u32 tirn;
3f6d08d1
OG		 148
149 int num_channels;
150 struct mlx5e_rqt indir_rqt;
151 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
152 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 153};
154
5c65c564
OG		 155struct mlx5e_hairpin_entry {
156 /* a node of a hash table which keeps all the hairpin entries */
157 struct hlist_node hairpin_hlist;
158
159 /* flows sharing the same hairpin */
160 struct list_head flows;
161
d8822868 162 u16 peer_vhca_id;
106be53b 163 u8 prio;
5c65c564
OG		 164 struct mlx5e_hairpin *hp;
165};
166
11c9c548
OG		 167struct mod_hdr_key {
168 int num_actions;
169 void *actions;
170};
171
172struct mlx5e_mod_hdr_entry {
173 /* a node of a hash table which keeps all the mod_hdr entries */
174 struct hlist_node mod_hdr_hlist;
175
176 /* flows sharing the same mod_hdr entry */
177 struct list_head flows;
178
179 struct mod_hdr_key key;
180
181 u32 mod_hdr_id;
182};
183
184#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
185
186static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
187{
188 return jhash(key->actions,
189 key->num_actions * MLX5_MH_ACT_SZ, 0);
190}
191
192static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
193 struct mod_hdr_key *b)
194{
195 if (a->num_actions != b->num_actions)
196 return 1;
197
198 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
199}
200
201static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
202 struct mlx5e_tc_flow *flow,
203 struct mlx5e_tc_flow_parse_attr *parse_attr)
204{
205 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
206 int num_actions, actions_size, namespace, err;
207 struct mlx5e_mod_hdr_entry *mh;
208 struct mod_hdr_key key;
209 bool found = false;
210 u32 hash_key;
211
212 num_actions = parse_attr->num_mod_hdr_actions;
213 actions_size = MLX5_MH_ACT_SZ * num_actions;
214
215 key.actions = parse_attr->mod_hdr_actions;
216 key.num_actions = num_actions;
217
218 hash_key = hash_mod_hdr_info(&key);
219
220 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
221 namespace = MLX5_FLOW_NAMESPACE_FDB;
222 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
223 mod_hdr_hlist, hash_key) {
224 if (!cmp_mod_hdr_info(&mh->key, &key)) {
225 found = true;
226 break;
227 }
228 }
229 } else {
230 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
231 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
232 mod_hdr_hlist, hash_key) {
233 if (!cmp_mod_hdr_info(&mh->key, &key)) {
234 found = true;
235 break;
236 }
237 }
238 }
239
240 if (found)
241 goto attach_flow;
242
243 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
244 if (!mh)
245 return -ENOMEM;
246
247 mh->key.actions = (void *)mh + sizeof(*mh);
248 memcpy(mh->key.actions, key.actions, actions_size);
249 mh->key.num_actions = num_actions;
250 INIT_LIST_HEAD(&mh->flows);
251
252 err = mlx5_modify_header_alloc(priv->mdev, namespace,
253 mh->key.num_actions,
254 mh->key.actions,
255 &mh->mod_hdr_id);
256 if (err)
257 goto out_err;
258
259 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
260 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
261 else
262 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
263
264attach_flow:
265 list_add(&flow->mod_hdr, &mh->flows);
266 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
267 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
268 else
269 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
270
271 return 0;
272
273out_err:
274 kfree(mh);
275 return err;
276}
277
278static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
279 struct mlx5e_tc_flow *flow)
280{
281 struct list_head *next = flow->mod_hdr.next;
282
283 list_del(&flow->mod_hdr);
284
285 if (list_empty(next)) {
286 struct mlx5e_mod_hdr_entry *mh;
287
288 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
289
290 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
291 hash_del(&mh->mod_hdr_hlist);
292 kfree(mh);
293 }
294}
295
77ab67b7
OG		 296static
297struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
298{
299 struct net_device *netdev;
300 struct mlx5e_priv *priv;
301
302 netdev = __dev_get_by_index(net, ifindex);
303 priv = netdev_priv(netdev);
304 return priv->mdev;
305}
306
307static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
308{
309 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
310 void *tirc;
311 int err;
312
313 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
314 if (err)
315 goto alloc_tdn_err;
316
317 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
318
319 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 320 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 321 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
322
323 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
324 if (err)
325 goto create_tir_err;
326
327 return 0;
328
329create_tir_err:
330 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
331alloc_tdn_err:
332 return err;
333}
334
335static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
336{
337 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
338 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
339}
340
3f6d08d1
OG		 341static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
342{
343 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
344 struct mlx5e_priv *priv = hp->func_priv;
345 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
346
347 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
348 hp->num_channels);
349
350 for (i = 0; i < sz; i++) {
351 ix = i;
bbeb53b8 352 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 353 ix = mlx5e_bits_invert(i, ilog2(sz));
354 ix = indirection_rqt[ix];
355 rqn = hp->pair->rqn[ix];
356 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
357 }
358}
359
360static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
361{
362 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
363 struct mlx5e_priv *priv = hp->func_priv;
364 struct mlx5_core_dev *mdev = priv->mdev;
365 void *rqtc;
366 u32 *in;
367
368 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
369 in = kvzalloc(inlen, GFP_KERNEL);
370 if (!in)
371 return -ENOMEM;
372
373 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
374
375 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
376 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
377
378 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
379
380 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
381 if (!err)
382 hp->indir_rqt.enabled = true;
383
384 kvfree(in);
385 return err;
386}
387
388static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
389{
390 struct mlx5e_priv *priv = hp->func_priv;
391 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
392 int tt, i, err;
393 void *tirc;
394
395 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 396 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
397
3f6d08d1
OG		 398 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
399 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
400
401 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
402 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
403 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 404 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
405
3f6d08d1
OG		 406 err = mlx5_core_create_tir(hp->func_mdev, in,
407 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
408 if (err) {
409 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
410 goto err_destroy_tirs;
411 }
412 }
413 return 0;
414
415err_destroy_tirs:
416 for (i = 0; i < tt; i++)
417 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
418 return err;
419}
420
421static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
422{
423 int tt;
424
425 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
426 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
427}
428
429static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
430 struct ttc_params *ttc_params)
431{
432 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
433 int tt;
434
435 memset(ttc_params, 0, sizeof(*ttc_params));
436
437 ttc_params->any_tt_tirn = hp->tirn;
438
439 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
440 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
441
442 ft_attr->max_fte = MLX5E_NUM_TT;
443 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
444 ft_attr->prio = MLX5E_TC_PRIO;
445}
446
447static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
448{
449 struct mlx5e_priv *priv = hp->func_priv;
450 struct ttc_params ttc_params;
451 int err;
452
453 err = mlx5e_hairpin_create_indirect_rqt(hp);
454 if (err)
455 return err;
456
457 err = mlx5e_hairpin_create_indirect_tirs(hp);
458 if (err)
459 goto err_create_indirect_tirs;
460
461 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
462 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
463 if (err)
464 goto err_create_ttc_table;
465
466 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
467 hp->num_channels, hp->ttc.ft.t->id);
468
469 return 0;
470
471err_create_ttc_table:
472 mlx5e_hairpin_destroy_indirect_tirs(hp);
473err_create_indirect_tirs:
474 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
475
476 return err;
477}
478
479static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
480{
481 struct mlx5e_priv *priv = hp->func_priv;
482
483 mlx5e_destroy_ttc_table(priv, &hp->ttc);
484 mlx5e_hairpin_destroy_indirect_tirs(hp);
485 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
486}
487
77ab67b7
OG		 488static struct mlx5e_hairpin *
489mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
490 int peer_ifindex)
491{
492 struct mlx5_core_dev *func_mdev, *peer_mdev;
493 struct mlx5e_hairpin *hp;
494 struct mlx5_hairpin *pair;
495 int err;
496
497 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
498 if (!hp)
499 return ERR_PTR(-ENOMEM);
500
501 func_mdev = priv->mdev;
502 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
503
504 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
505 if (IS_ERR(pair)) {
506 err = PTR_ERR(pair);
507 goto create_pair_err;
508 }
509 hp->pair = pair;
510 hp->func_mdev = func_mdev;
3f6d08d1
OG		 511 hp->func_priv = priv;
512 hp->num_channels = params->num_channels;
77ab67b7
OG		 513
514 err = mlx5e_hairpin_create_transport(hp);
515 if (err)
516 goto create_transport_err;
517
3f6d08d1
OG		 518 if (hp->num_channels > 1) {
519 err = mlx5e_hairpin_rss_init(hp);
520 if (err)
521 goto rss_init_err;
522 }
523
77ab67b7
OG		 524 return hp;
525
3f6d08d1
OG		 526rss_init_err:
527 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 528create_transport_err:
529 mlx5_core_hairpin_destroy(hp->pair);
530create_pair_err:
531 kfree(hp);
532 return ERR_PTR(err);
533}
534
535static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
536{
3f6d08d1
OG		 537 if (hp->num_channels > 1)
538 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 539 mlx5e_hairpin_destroy_transport(hp);
540 mlx5_core_hairpin_destroy(hp->pair);
541 kvfree(hp);
542}
543
106be53b
OG		 544static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
545{
546 return (peer_vhca_id << 16 | prio);
547}
548
5c65c564 549static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 550 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 551{
552 struct mlx5e_hairpin_entry *hpe;
106be53b 553 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 554
555 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 556 hairpin_hlist, hash_key) {
557 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 558 return hpe;
559 }
560
561 return NULL;
562}
563
106be53b
OG		 564#define UNKNOWN_MATCH_PRIO 8
565
566static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 567 struct mlx5_flow_spec *spec, u8 *match_prio,
568 struct netlink_ext_ack *extack)
106be53b
OG		 569{
570 void *headers_c, *headers_v;
571 u8 prio_val, prio_mask = 0;
572 bool vlan_present;
573
574#ifdef CONFIG_MLX5_CORE_EN_DCB
575 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 576 NL_SET_ERR_MSG_MOD(extack,
577 "only PCP trust state supported for hairpin");
106be53b
OG		 578 return -EOPNOTSUPP;
579 }
580#endif
581 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
582 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
583
584 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
585 if (vlan_present) {
586 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
587 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
588 }
589
590 if (!vlan_present || !prio_mask) {
591 prio_val = UNKNOWN_MATCH_PRIO;
592 } else if (prio_mask != 0x7) {
e98bedf5
EB		 593 NL_SET_ERR_MSG_MOD(extack,
594 "masked priority match not supported for hairpin");
106be53b
OG		 595 return -EOPNOTSUPP;
596 }
597
598 *match_prio = prio_val;
599 return 0;
600}
601
5c65c564
OG		 602static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
603 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 604 struct mlx5e_tc_flow_parse_attr *parse_attr,
605 struct netlink_ext_ack *extack)
5c65c564 606{
98b66cb1 607 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 608 struct mlx5_hairpin_params params;
d8822868 609 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 610 struct mlx5e_hairpin_entry *hpe;
611 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 612 u64 link_speed64;
613 u32 link_speed;
106be53b 614 u8 match_prio;
d8822868 615 u16 peer_id;
5c65c564
OG		 616 int err;
617
d8822868
OG		 618 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
619 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 620 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 621 return -EOPNOTSUPP;
622 }
623
d8822868 624 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 625 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
626 extack);
106be53b
OG		 627 if (err)
628 return err;
629 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 630 if (hpe)
631 goto attach_flow;
632
633 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
634 if (!hpe)
635 return -ENOMEM;
636
637 INIT_LIST_HEAD(&hpe->flows);
d8822868 638 hpe->peer_vhca_id = peer_id;
106be53b 639 hpe->prio = match_prio;
5c65c564
OG		 640
641 params.log_data_size = 15;
642 params.log_data_size = min_t(u8, params.log_data_size,
643 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
644 params.log_data_size = max_t(u8, params.log_data_size,
645 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 646
eb9180f7
OG		 647 params.log_num_packets = params.log_data_size -
648 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
649 params.log_num_packets = min_t(u8, params.log_num_packets,
650 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
651
652 params.q_counter = priv->q_counter;
3f6d08d1 653 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 654 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 655 link_speed = max_t(u32, link_speed, 50000);
656 link_speed64 = link_speed;
657 do_div(link_speed64, 50000);
658 params.num_channels = link_speed64;
659
5c65c564
OG		 660 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
661 if (IS_ERR(hp)) {
662 err = PTR_ERR(hp);
663 goto create_hairpin_err;
664 }
665
eb9180f7 666 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 667 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 668 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 669
670 hpe->hp = hp;
106be53b
OG		 671 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
672 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 673
674attach_flow:
3f6d08d1
OG		 675 if (hpe->hp->num_channels > 1) {
676 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
677 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
678 } else {
679 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
680 }
5c65c564 681 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 682
5c65c564
OG		 683 return 0;
684
685create_hairpin_err:
686 kfree(hpe);
687 return err;
688}
689
690static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
691 struct mlx5e_tc_flow *flow)
692{
693 struct list_head *next = flow->hairpin.next;
694
695 list_del(&flow->hairpin);
696
697 /* no more hairpin flows for us, release the hairpin pair */
698 if (list_empty(next)) {
699 struct mlx5e_hairpin_entry *hpe;
700
701 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
702
703 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
704 hpe->hp->pair->peer_mdev->priv.name);
705
706 mlx5e_hairpin_destroy(hpe->hp);
707 hash_del(&hpe->hairpin_hlist);
708 kfree(hpe);
709 }
710}
711
c83954ab 712static int
74491de9 713mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 714 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 715 struct mlx5e_tc_flow *flow,
716 struct netlink_ext_ack *extack)
e8f887ac 717{
aa0cbbae 718 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 719 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 720 struct mlx5_flow_destination dest[2] = {};
66958ed9 721 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 722 .action = attr->action,
723 .flow_tag = attr->flow_tag,
60786f09 724 .reformat_id = 0,
42f7ad67 725 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 726 };
aad7e08d 727 struct mlx5_fc *counter = NULL;
e8f887ac 728 bool table_created = false;
5c65c564 729 int err, dest_ix = 0;
e8f887ac 730
3f6d08d1 731 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 732 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 733 if (err) {
3f6d08d1
OG		 734 goto err_add_hairpin_flow;
735 }
736 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
737 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
738 dest[dest_ix].ft = attr->hairpin_ft;
739 } else {
5c65c564
OG		 740 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
741 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 742 }
743 dest_ix++;
3f6d08d1
OG		 744 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
745 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
746 dest[dest_ix].ft = priv->fs.vlan.ft.t;
747 dest_ix++;
5c65c564 748 }
aad7e08d 749
5c65c564
OG		 750 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
751 counter = mlx5_fc_create(dev, true);
752 if (IS_ERR(counter)) {
c83954ab 753 err = PTR_ERR(counter);
5c65c564
OG		 754 goto err_fc_create;
755 }
756 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 757 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 758 dest_ix++;
b8aee822 759 attr->counter = counter;
aad7e08d
AV		 760 }
761
2f4fe4ca 762 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 763 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 764 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 765 kfree(parse_attr->mod_hdr_actions);
c83954ab 766 if (err)
2f4fe4ca 767 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 768 }
769
acff797c 770 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 771 int tc_grp_size, tc_tbl_size;
772 u32 max_flow_counter;
773
774 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
775 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
776
777 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
778
779 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
780 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
781
acff797c
MG		 782 priv->fs.tc.t =
783 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
784 MLX5E_TC_PRIO,
21b9c144 785 tc_tbl_size,
acff797c 786 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 787 MLX5E_TC_FT_LEVEL, 0);
acff797c 788 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 789 NL_SET_ERR_MSG_MOD(extack,
790 "Failed to create tc offload table\n");
e8f887ac
AV		 791 netdev_err(priv->netdev,
792 "Failed to create tc offload table\n");
c83954ab 793 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 794 goto err_create_ft;
e8f887ac
AV		 795 }
796
797 table_created = true;
798 }
799
38aa51c1
OG		 800 if (attr->match_level != MLX5_MATCH_NONE)
801 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
802
c83954ab
RL		 803 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
804 &flow_act, dest, dest_ix);
aad7e08d 805
c83954ab
RL		 806 if (IS_ERR(flow->rule[0])) {
807 err = PTR_ERR(flow->rule[0]);
aad7e08d 808 goto err_add_rule;
c83954ab 809 }
aad7e08d 810
c83954ab 811 return 0;
e8f887ac 812
aad7e08d
AV		 813err_add_rule:
814 if (table_created) {
acff797c
MG		 815 mlx5_destroy_flow_table(priv->fs.tc.t);
816 priv->fs.tc.t = NULL;
e8f887ac 817 }
aad7e08d 818err_create_ft:
2f4fe4ca 819 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 820 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 821err_create_mod_hdr_id:
aad7e08d 822 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 823err_fc_create:
824 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
825 mlx5e_hairpin_flow_del(priv, flow);
826err_add_hairpin_flow:
c83954ab 827 return err;
e8f887ac
AV		 828}
829
d85cdccb
OG		 830static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
831 struct mlx5e_tc_flow *flow)
832{
513f8f7f 833 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 834 struct mlx5_fc *counter = NULL;
835
b8aee822 836 counter = attr->counter;
e4ad91f2 837 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 838 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 839
d9ee0491 840 if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) {
d85cdccb
OG		 841 mlx5_destroy_flow_table(priv->fs.tc.t);
842 priv->fs.tc.t = NULL;
843 }
2f4fe4ca 844
513f8f7f 845 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 846 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 847
848 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
849 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 850}
851
aa0cbbae 852static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 853 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 854
3c37745e 855static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 856 struct mlx5e_tc_flow *flow,
733d4f36
RD		 857 struct net_device *mirred_dev,
858 int out_index,
8c4dc42b 859 struct netlink_ext_ack *extack,
0ad060ee
RD		 860 struct net_device **encap_dev,
861 bool *encap_valid);
3c37745e 862
6d2a3ed0
OG		 863static struct mlx5_flow_handle *
864mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
865 struct mlx5e_tc_flow *flow,
866 struct mlx5_flow_spec *spec,
867 struct mlx5_esw_flow_attr *attr)
868{
869 struct mlx5_flow_handle *rule;
870
871 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
872 if (IS_ERR(rule))
873 return rule;
874
e85e02ba 875 if (attr->split_count) {
6d2a3ed0
OG		 876 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
877 if (IS_ERR(flow->rule[1])) {
878 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
879 return flow->rule[1];
880 }
881 }
882
883 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
884 return rule;
885}
886
887static void
888mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
889 struct mlx5e_tc_flow *flow,
890 struct mlx5_esw_flow_attr *attr)
891{
892 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
893
e85e02ba 894 if (attr->split_count)
6d2a3ed0
OG		 895 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
896
897 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
898}
899
5dbe906f
PB		 900static struct mlx5_flow_handle *
901mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
902 struct mlx5e_tc_flow *flow,
903 struct mlx5_flow_spec *spec,
904 struct mlx5_esw_flow_attr *slow_attr)
905{
906 struct mlx5_flow_handle *rule;
907
908 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 909 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 910 slow_attr->split_count = 0;
154e62ab 911 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 912
913 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
914 if (!IS_ERR(rule))
915 flow->flags |= MLX5E_TC_FLOW_SLOW;
916
917 return rule;
918}
919
920static void
921mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
922 struct mlx5e_tc_flow *flow,
923 struct mlx5_esw_flow_attr *slow_attr)
924{
925 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 926 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 927 slow_attr->split_count = 0;
154e62ab 928 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 929 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
930 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
931}
932
b4a23329
RD		 933static void add_unready_flow(struct mlx5e_tc_flow *flow)
934{
935 struct mlx5_rep_uplink_priv *uplink_priv;
936 struct mlx5e_rep_priv *rpriv;
937 struct mlx5_eswitch *esw;
938
939 esw = flow->priv->mdev->priv.eswitch;
940 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
941 uplink_priv = &rpriv->uplink_priv;
942
943 flow->flags |= MLX5E_TC_FLOW_NOT_READY;
944 list_add_tail(&flow->unready, &uplink_priv->unready_flows);
945}
946
947static void remove_unready_flow(struct mlx5e_tc_flow *flow)
948{
949 list_del(&flow->unready);
950 flow->flags &= ~MLX5E_TC_FLOW_NOT_READY;
951}
952
c83954ab 953static int
74491de9 954mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 955 struct mlx5e_tc_flow *flow,
956 struct netlink_ext_ack *extack)
adb4c123
OG		 957{
958 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 959 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 960 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 961 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 962 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 963 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 964 struct mlx5_fc *counter = NULL;
3c37745e
OG		 965 struct mlx5e_rep_priv *rpriv;
966 struct mlx5e_priv *out_priv;
0ad060ee
RD		 967 bool encap_valid = true;
968 int err = 0;
f493f155 969 int out_index;
8b32580d 970
d14f6f2a
OG		 971 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
972 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
973 return -EOPNOTSUPP;
974 }
bf07aa73
PB		 975
976 if (attr->chain > max_chain) {
977 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
978 err = -EOPNOTSUPP;
979 goto err_max_prio_chain;
980 }
981
982 if (attr->prio > max_prio) {
983 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
984 err = -EOPNOTSUPP;
985 goto err_max_prio_chain;
986 }
e52c2802 987
f493f155 988 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 989 int mirred_ifindex;
990
f493f155
EB		 991 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
992 continue;
993
7040632d 994 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 995 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 996 mirred_ifindex);
733d4f36 997 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 998 extack, &encap_dev, &encap_valid);
999 if (err)
c83954ab 1000 goto err_attach_encap;
0ad060ee 1001
3c37745e
OG		 1002 out_priv = netdev_priv(encap_dev);
1003 rpriv = out_priv->ppriv;
1cc26d74
EB		 1004 attr->dests[out_index].rep = rpriv->rep;
1005 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1006 }
1007
8b32580d 1008 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1009 if (err)
aa0cbbae 1010 goto err_add_vlan;
adb4c123 1011
d7e75a32 1012 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1013 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1014 kfree(parse_attr->mod_hdr_actions);
c83954ab 1015 if (err)
d7e75a32 1016 goto err_mod_hdr;
d7e75a32
OG		 1017 }
1018
b8aee822 1019 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1020 counter = mlx5_fc_create(attr->counter_dev, true);
b8aee822 1021 if (IS_ERR(counter)) {
c83954ab 1022 err = PTR_ERR(counter);
b8aee822
MB		 1023 goto err_create_counter;
1024 }
1025
1026 attr->counter = counter;
1027 }
1028
0ad060ee
RD		 1029 /* we get here if one of the following takes place:
1030 * (1) there's no error
1031 * (2) there's an encap action and we don't have valid neigh
3c37745e 1032 */
0ad060ee 1033 if (!encap_valid) {
5dbe906f
PB		 1034 /* continue with goto slow path rule instead */
1035 struct mlx5_esw_flow_attr slow_attr;
1036
1037 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1038 } else {
6d2a3ed0 1039 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1040 }
c83954ab 1041
5dbe906f
PB		 1042 if (IS_ERR(flow->rule[0])) {
1043 err = PTR_ERR(flow->rule[0]);
1044 goto err_add_rule;
1045 }
1046
1047 return 0;
aa0cbbae
OG		 1048
1049err_add_rule:
f9392795 1050 mlx5_fc_destroy(attr->counter_dev, counter);
b8aee822 1051err_create_counter:
513f8f7f 1052 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1053 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 1054err_mod_hdr:
aa0cbbae
OG		 1055 mlx5_eswitch_del_vlan_action(esw, attr);
1056err_add_vlan:
f493f155 1057 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1058 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1059 mlx5e_detach_encap(priv, flow, out_index);
3c37745e 1060err_attach_encap:
bf07aa73 1061err_max_prio_chain:
c83954ab 1062 return err;
aa0cbbae 1063}
d85cdccb
OG		 1064
1065static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1066 struct mlx5e_tc_flow *flow)
1067{
1068 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1069 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1070 struct mlx5_esw_flow_attr slow_attr;
f493f155 1071 int out_index;
d85cdccb 1072
ef06c9ee 1073 if (flow->flags & MLX5E_TC_FLOW_NOT_READY) {
b4a23329 1074 remove_unready_flow(flow);
ef06c9ee
RD		 1075 kvfree(attr->parse_attr);
1076 return;
1077 }
1078
5dbe906f
PB		 1079 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1080 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1081 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1082 else
1083 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1084 }
d85cdccb 1085
513f8f7f 1086 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1087
f493f155 1088 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1089 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1090 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1091 kvfree(attr->parse_attr);
d7e75a32 1092
513f8f7f 1093 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1094 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1095
1096 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1097 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1098}
1099
232c0013
HHZ		 1100void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1101 struct mlx5e_encap_entry *e)
1102{
3c37745e 1103 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1104 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1105 struct mlx5_flow_handle *rule;
1106 struct mlx5_flow_spec *spec;
79baaec7 1107 struct encap_flow_item *efi;
232c0013
HHZ		 1108 struct mlx5e_tc_flow *flow;
1109 int err;
1110
54c177ca
OS		 1111 err = mlx5_packet_reformat_alloc(priv->mdev,
1112 e->reformat_type,
60786f09 1113 e->encap_size, e->encap_header,
31ca3648 1114 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1115 &e->encap_id);
232c0013
HHZ		 1116 if (err) {
1117 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1118 err);
1119 return;
1120 }
1121 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1122 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1123
79baaec7 1124 list_for_each_entry(efi, &e->flows, list) {
8c4dc42b
EB		 1125 bool all_flow_encaps_valid = true;
1126 int i;
1127
79baaec7 1128 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
3c37745e 1129 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1130 spec = &esw_attr->parse_attr->spec;
1131
8c4dc42b
EB		 1132 esw_attr->dests[efi->index].encap_id = e->encap_id;
1133 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1134 /* Flow can be associated with multiple encap entries.
1135 * Before offloading the flow verify that all of them have
1136 * a valid neighbour.
1137 */
1138 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1139 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1140 continue;
1141 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1142 all_flow_encaps_valid = false;
1143 break;
1144 }
1145 }
1146 /* Do not offload flows with unresolved neighbors */
1147 if (!all_flow_encaps_valid)
1148 continue;
5dbe906f 1149 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1150 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1151 if (IS_ERR(rule)) {
1152 err = PTR_ERR(rule);
232c0013
HHZ		 1153 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1154 err);
1155 continue;
1156 }
5dbe906f
PB		 1157
1158 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1159 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1160 flow->rule[0] = rule;
232c0013
HHZ		 1161 }
1162}
1163
1164void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1165 struct mlx5e_encap_entry *e)
1166{
3c37745e 1167 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1168 struct mlx5_esw_flow_attr slow_attr;
1169 struct mlx5_flow_handle *rule;
1170 struct mlx5_flow_spec *spec;
79baaec7 1171 struct encap_flow_item *efi;
232c0013 1172 struct mlx5e_tc_flow *flow;
5dbe906f 1173 int err;
232c0013 1174
79baaec7
EB		 1175 list_for_each_entry(efi, &e->flows, list) {
1176 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5dbe906f
PB		 1177 spec = &flow->esw_attr->parse_attr->spec;
1178
1179 /* update from encap rule to slow path rule */
1180 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1181 /* mark the flow's encap dest as non-valid */
1182 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1183
1184 if (IS_ERR(rule)) {
1185 err = PTR_ERR(rule);
1186 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1187 err);
1188 continue;
1189 }
1190
1191 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1192 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1193 flow->rule[0] = rule;
232c0013
HHZ		 1194 }
1195
61c806da
OG		 1196 /* we know that the encap is valid */
1197 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1198 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1199}
1200
b8aee822
MB		 1201static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1202{
1203 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1204 return flow->esw_attr->counter;
1205 else
1206 return flow->nic_attr->counter;
1207}
1208
f6dfb4c3
HHZ		 1209void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1210{
1211 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1212 u64 bytes, packets, lastuse = 0;
1213 struct mlx5e_tc_flow *flow;
1214 struct mlx5e_encap_entry *e;
1215 struct mlx5_fc *counter;
1216 struct neigh_table *tbl;
1217 bool neigh_used = false;
1218 struct neighbour *n;
1219
1220 if (m_neigh->family == AF_INET)
1221 tbl = &arp_tbl;
1222#if IS_ENABLED(CONFIG_IPV6)
1223 else if (m_neigh->family == AF_INET6)
423c9db2 1224 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1225#endif
1226 else
1227 return;
1228
1229 list_for_each_entry(e, &nhe->encap_list, encap_list) {
79baaec7 1230 struct encap_flow_item *efi;
f6dfb4c3
HHZ		 1231 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1232 continue;
79baaec7
EB		 1233 list_for_each_entry(efi, &e->flows, list) {
1234 flow = container_of(efi, struct mlx5e_tc_flow,
1235 encaps[efi->index]);
f6dfb4c3 1236 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1237 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1238 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1239 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1240 neigh_used = true;
1241 break;
1242 }
1243 }
1244 }
e36d4810
RD		 1245 if (neigh_used)
1246 break;
f6dfb4c3
HHZ		 1247 }
1248
1249 if (neigh_used) {
1250 nhe->reported_lastuse = jiffies;
1251
1252 /* find the relevant neigh according to the cached device and
1253 * dst ip pair
1254 */
1255 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1256 if (!n)
f6dfb4c3 1257 return;
f6dfb4c3
HHZ		 1258
1259 neigh_event_send(n, NULL);
1260 neigh_release(n);
1261 }
1262}
1263
d85cdccb 1264static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1265 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1266{
8c4dc42b 1267 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1268
8c4dc42b 1269 list_del(&flow->encaps[out_index].list);
5067b602 1270 if (list_empty(next)) {
c1ae1152 1271 struct mlx5e_encap_entry *e;
5067b602 1272
c1ae1152 1273 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1274 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1275
1276 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1277 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1278
cdc5a7f3 1279 hash_del_rcu(&e->encap_hlist);
232c0013 1280 kfree(e->encap_header);
5067b602
RD		 1281 kfree(e);
1282 }
1283}
1284
04de7dda
RD		 1285static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1286{
1287 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1288
1289 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1290 !(flow->flags & MLX5E_TC_FLOW_DUP))
1291 return;
1292
1293 mutex_lock(&esw->offloads.peer_mutex);
1294 list_del(&flow->peer);
1295 mutex_unlock(&esw->offloads.peer_mutex);
1296
1297 flow->flags &= ~MLX5E_TC_FLOW_DUP;
1298
1299 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1300 kvfree(flow->peer_flow);
1301 flow->peer_flow = NULL;
1302}
1303
1304static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1305{
1306 struct mlx5_core_dev *dev = flow->priv->mdev;
1307 struct mlx5_devcom *devcom = dev->priv.devcom;
1308 struct mlx5_eswitch *peer_esw;
1309
1310 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1311 if (!peer_esw)
1312 return;
1313
1314 __mlx5e_tc_del_fdb_peer_flow(flow);
1315 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1316}
1317
e8f887ac 1318static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1319 struct mlx5e_tc_flow *flow)
e8f887ac 1320{
04de7dda
RD		 1321 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1322 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1323 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1324 } else {
d85cdccb 1325 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1326 }
e8f887ac
AV		 1327}
1328
bbd00f7e
HHZ		 1329
1330static int parse_tunnel_attr(struct mlx5e_priv *priv,
1331 struct mlx5_flow_spec *spec,
54c177ca 1332 struct tc_cls_flower_offload *f,
6363651d 1333 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1334{
e98bedf5 1335 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1336 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1337 outer_headers);
1338 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1339 outer_headers);
8f256622
PNA		 1340 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1341 struct flow_match_control enc_control;
1342 int err;
2e72eb43 1343
101f4de9 1344 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1345 headers_c, headers_v, match_level);
54c177ca
OS		 1346 if (err) {
1347 NL_SET_ERR_MSG_MOD(extack,
1348 "failed to parse tunnel attributes");
101f4de9 1349 return err;
bbd00f7e
HHZ		 1350 }
1351
8f256622
PNA		 1352 flow_rule_match_enc_control(rule, &enc_control);
1353
1354 if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1355 struct flow_match_ipv4_addrs match;
1356
1357 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1358 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1359 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1360 ntohl(match.mask->src));
bbd00f7e
HHZ		 1361 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1362 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1363 ntohl(match.key->src));
bbd00f7e
HHZ		 1364
1365 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1366 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1367 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1368 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1369 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1370 ntohl(match.key->dst));
bbd00f7e 1371
2e72eb43
OG		 1372 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1373 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
8f256622
PNA		 1374 } else if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1375 struct flow_match_ipv6_addrs match;
19f44401 1376
8f256622 1377 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1378 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1379 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1380 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1381 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1382 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1383 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1384
1385 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1386 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1387 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1388 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1389 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1390 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1391
1392 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1393 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1394 }
bbd00f7e 1395
8f256622
PNA		 1396 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1397 struct flow_match_ip match;
bcef735c 1398
8f256622
PNA		 1399 flow_rule_match_enc_ip(rule, &match);
1400 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1401 match.mask->tos & 0x3);
1402 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1403 match.key->tos & 0x3);
bcef735c 1404
8f256622
PNA		 1405 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1406 match.mask->tos >> 2);
1407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1408 match.key->tos >> 2);
bcef735c 1409
8f256622
PNA		 1410 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1411 match.mask->ttl);
1412 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1413 match.key->ttl);
e98bedf5 1414
8f256622 1415 if (match.mask->ttl &&
e98bedf5
EB		 1416 !MLX5_CAP_ESW_FLOWTABLE_FDB
1417 (priv->mdev,
1418 ft_field_support.outer_ipv4_ttl)) {
1419 NL_SET_ERR_MSG_MOD(extack,
1420 "Matching on TTL is not supported");
1421 return -EOPNOTSUPP;
1422 }
1423
bcef735c
OG		 1424 }
1425
bbd00f7e
HHZ		 1426 /* Enforce DMAC when offloading incoming tunneled flows.
1427 * Flow counters require a match on the DMAC.
1428 */
1429 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1430 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1431 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1432 dmac_47_16), priv->netdev->dev_addr);
1433
1434 /* let software handle IP fragments */
1435 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1436 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1437
1438 return 0;
1439}
1440
de0af0bf
RD		 1441static int __parse_cls_flower(struct mlx5e_priv *priv,
1442 struct mlx5_flow_spec *spec,
1443 struct tc_cls_flower_offload *f,
54c177ca 1444 struct net_device *filter_dev,
6363651d 1445 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1446{
e98bedf5 1447 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1448 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1449 outer_headers);
1450 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1451 outer_headers);
699e96dd
JL		 1452 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1453 misc_parameters);
1454 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1455 misc_parameters);
8f256622
PNA		 1456 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1457 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1458 u16 addr_type = 0;
1459 u8 ip_proto = 0;
1460
d708f902 1461 *match_level = MLX5_MATCH_NONE;
de0af0bf 1462
8f256622 1463 if (dissector->used_keys &
e3a2b7ed
AV		 1464 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1465 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1466 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1467 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1468 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1469 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1470 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1471 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1472 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1473 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1474 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1475 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1476 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1477 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1478 BIT(FLOW_DISSECTOR_KEY_IP) |
1479 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1480 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1481 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1482 dissector->used_keys);
e3a2b7ed
AV		 1483 return -EOPNOTSUPP;
1484 }
1485
8f256622
PNA		 1486 if ((flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1487 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1488 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1489 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1490 struct flow_match_control match;
1491
1492 flow_rule_match_enc_control(rule, &match);
1493 switch (match.key->addr_type) {
bbd00f7e 1494 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1495 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
6363651d 1496 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e
HHZ		 1497 return -EOPNOTSUPP;
1498 break;
1499 default:
1500 return -EOPNOTSUPP;
1501 }
1502
1503 /* In decap flow, header pointers should point to the inner
1504 * headers, outer header were already set by parse_tunnel_attr
1505 */
1506 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1507 inner_headers);
1508 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1509 inner_headers);
1510 }
1511
8f256622
PNA		 1512 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1513 struct flow_match_basic match;
1514
1515 flow_rule_match_basic(rule, &match);
d3a80bb5 1516 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1517 ntohs(match.mask->n_proto));
d3a80bb5 1518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1519 ntohs(match.key->n_proto));
e3a2b7ed 1520
8f256622 1521 if (match.mask->n_proto)
d708f902 1522 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1523 }
1524
8f256622
PNA		 1525 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1526 struct flow_match_vlan match;
1527
1528 flow_rule_match_vlan(rule, &match);
1529 if (match.mask->vlan_id ||
1530 match.mask->vlan_priority ||
1531 match.mask->vlan_tpid) {
1532 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1533 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1534 svlan_tag, 1);
1535 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1536 svlan_tag, 1);
1537 } else {
1538 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1539 cvlan_tag, 1);
1540 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1541 cvlan_tag, 1);
1542 }
095b6cfd 1543
8f256622
PNA		 1544 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1545 match.mask->vlan_id);
1546 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1547 match.key->vlan_id);
358d79a4 1548
8f256622
PNA		 1549 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1550 match.mask->vlan_priority);
1551 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1552 match.key->vlan_priority);
54782900 1553
d708f902 1554 *match_level = MLX5_MATCH_L2;
54782900 1555 }
d3a80bb5 1556 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1557 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1558 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1559 *match_level = MLX5_MATCH_L2;
54782900
OG		 1560 }
1561
8f256622
PNA		 1562 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1563 struct flow_match_vlan match;
1564
1565 flow_rule_match_vlan(rule, &match);
1566 if (match.mask->vlan_id ||
1567 match.mask->vlan_priority ||
1568 match.mask->vlan_tpid) {
1569 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1570 MLX5_SET(fte_match_set_misc, misc_c,
1571 outer_second_svlan_tag, 1);
1572 MLX5_SET(fte_match_set_misc, misc_v,
1573 outer_second_svlan_tag, 1);
1574 } else {
1575 MLX5_SET(fte_match_set_misc, misc_c,
1576 outer_second_cvlan_tag, 1);
1577 MLX5_SET(fte_match_set_misc, misc_v,
1578 outer_second_cvlan_tag, 1);
1579 }
1580
1581 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1582 match.mask->vlan_id);
699e96dd 1583 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1584 match.key->vlan_id);
699e96dd 1585 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1586 match.mask->vlan_priority);
699e96dd 1587 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1588 match.key->vlan_priority);
699e96dd
JL		 1589
1590 *match_level = MLX5_MATCH_L2;
1591 }
1592 }
1593
8f256622
PNA		 1594 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1595 struct flow_match_eth_addrs match;
54782900 1596
8f256622 1597 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1598 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1599 dmac_47_16),
8f256622 1600 match.mask->dst);
d3a80bb5
OG		 1601 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1602 dmac_47_16),
8f256622 1603 match.key->dst);
d3a80bb5
OG		 1604
1605 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1606 smac_47_16),
8f256622 1607 match.mask->src);
d3a80bb5
OG		 1608 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1609 smac_47_16),
8f256622 1610 match.key->src);
d3a80bb5 1611
8f256622
PNA		 1612 if (!is_zero_ether_addr(match.mask->src) ||
1613 !is_zero_ether_addr(match.mask->dst))
d708f902 1614 *match_level = MLX5_MATCH_L2;
54782900
OG		 1615 }
1616
8f256622
PNA		 1617 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1618 struct flow_match_control match;
54782900 1619
8f256622
PNA		 1620 flow_rule_match_control(rule, &match);
1621 addr_type = match.key->addr_type;
54782900
OG		 1622
1623 /* the HW doesn't support frag first/later */
8f256622 1624 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1625 return -EOPNOTSUPP;
1626
8f256622 1627 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1628 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1629 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1630 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1631
1632 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1633 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1634 *match_level = MLX5_MATCH_L2;
54782900
OG		 1635 /* *** L2 attributes parsing up to here *** */
1636 else
83621b7d 1637 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1638 }
1639 }
1640
8f256622
PNA		 1641 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1642 struct flow_match_basic match;
1643
1644 flow_rule_match_basic(rule, &match);
1645 ip_proto = match.key->ip_proto;
54782900
OG		 1646
1647 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1648 match.mask->ip_proto);
54782900 1649 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1650 match.key->ip_proto);
54782900 1651
8f256622 1652 if (match.mask->ip_proto)
d708f902 1653 *match_level = MLX5_MATCH_L3;
54782900
OG		 1654 }
1655
e3a2b7ed 1656 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1657 struct flow_match_ipv4_addrs match;
e3a2b7ed 1658
8f256622 1659 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1660 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1661 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1662 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1663 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1664 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1665 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1666 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1667 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1668 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1669 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1670 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1671 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1672
8f256622 1673 if (match.mask->src || match.mask->dst)
d708f902 1674 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1675 }
1676
1677 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1678 struct flow_match_ipv6_addrs match;
e3a2b7ed 1679
8f256622 1680 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1681 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1682 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1683 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1684 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1685 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1686 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1687
1688 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1689 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1690 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1691 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1692 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1693 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1694
8f256622
PNA		 1695 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1696 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1697 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1698 }
1699
8f256622
PNA		 1700 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1701 struct flow_match_ip match;
1f97a526 1702
8f256622
PNA		 1703 flow_rule_match_ip(rule, &match);
1704 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1705 match.mask->tos & 0x3);
1706 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1707 match.key->tos & 0x3);
1f97a526 1708
8f256622
PNA		 1709 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1710 match.mask->tos >> 2);
1711 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1712 match.key->tos >> 2);
1f97a526 1713
8f256622
PNA		 1714 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1715 match.mask->ttl);
1716 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1717 match.key->ttl);
1f97a526 1718
8f256622 1719 if (match.mask->ttl &&
a8ade55f 1720 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1721 ft_field_support.outer_ipv4_ttl)) {
1722 NL_SET_ERR_MSG_MOD(extack,
1723 "Matching on TTL is not supported");
1f97a526 1724 return -EOPNOTSUPP;
e98bedf5 1725 }
a8ade55f 1726
8f256622 1727 if (match.mask->tos || match.mask->ttl)
d708f902 1728 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1729 }
1730
54782900
OG		 1731 /* *** L3 attributes parsing up to here *** */
1732
8f256622
PNA		 1733 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1734 struct flow_match_ports match;
1735
1736 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1737 switch (ip_proto) {
1738 case IPPROTO_TCP:
1739 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1740 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1741 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1742 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1743
1744 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1745 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1746 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1747 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1748 break;
1749
1750 case IPPROTO_UDP:
1751 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1752 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1753 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1754 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1755
1756 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1757 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1758 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1759 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1760 break;
1761 default:
e98bedf5
EB		 1762 NL_SET_ERR_MSG_MOD(extack,
1763 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1764 netdev_err(priv->netdev,
1765 "Only UDP and TCP transport are supported\n");
1766 return -EINVAL;
1767 }
de0af0bf 1768
8f256622 1769 if (match.mask->src || match.mask->dst)
d708f902 1770 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1771 }
1772
8f256622
PNA		 1773 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1774 struct flow_match_tcp match;
e77834ec 1775
8f256622 1776 flow_rule_match_tcp(rule, &match);
e77834ec 1777 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1778 ntohs(match.mask->flags));
e77834ec 1779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1780 ntohs(match.key->flags));
e77834ec 1781
8f256622 1782 if (match.mask->flags)
d708f902 1783 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1784 }
1785
e3a2b7ed
AV		 1786 return 0;
1787}
1788
de0af0bf 1789static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1790 struct mlx5e_tc_flow *flow,
de0af0bf 1791 struct mlx5_flow_spec *spec,
54c177ca
OS		 1792 struct tc_cls_flower_offload *f,
1793 struct net_device *filter_dev)
de0af0bf 1794{
e98bedf5 1795 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1796 struct mlx5_core_dev *dev = priv->mdev;
1797 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1798 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1799 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1800 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1801 int err;
1802
6363651d 1803 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 1804
1d447a39
SM		 1805 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1806 rep = rpriv->rep;
b05af6aa 1807 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 1808 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1809 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1810 NL_SET_ERR_MSG_MOD(extack,
1811 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1812 netdev_warn(priv->netdev,
1813 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1814 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1815 return -EOPNOTSUPP;
1816 }
1817 }
1818
6363651d 1819 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
38aa51c1 1820 flow->esw_attr->match_level = match_level;
6363651d
OG		 1821 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1822 } else {
38aa51c1 1823 flow->nic_attr->match_level = match_level;
6363651d 1824 }
38aa51c1 1825
de0af0bf
RD		 1826 return err;
1827}
1828
d79b6df6
OG		 1829struct pedit_headers {
1830 struct ethhdr eth;
0eb69bb9 1831 struct vlan_hdr vlan;
d79b6df6
OG		 1832 struct iphdr ip4;
1833 struct ipv6hdr ip6;
1834 struct tcphdr tcp;
1835 struct udphdr udp;
1836};
1837
c500c86b
PNA		 1838struct pedit_headers_action {
1839 struct pedit_headers vals;
1840 struct pedit_headers masks;
1841 u32 pedits;
1842};
1843
d79b6df6 1844static int pedit_header_offsets[] = {
73867881
PNA		 1845 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1846 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1847 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1848 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1849 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 1850};
1851
1852#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1853
1854static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 1855 struct pedit_headers_action *hdrs)
d79b6df6
OG		 1856{
1857 u32 *curr_pmask, *curr_pval;
1858
c500c86b
PNA		 1859 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
1860 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 1861
1862 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1863 goto out_err;
1864
1865 *curr_pmask |= mask;
1866 *curr_pval |= (val & mask);
1867
1868 return 0;
1869
1870out_err:
1871 return -EOPNOTSUPP;
1872}
1873
1874struct mlx5_fields {
1875 u8 field;
1876 u8 size;
1877 u32 offset;
1878};
1879
a8e4f0c4
OG		 1880#define OFFLOAD(fw_field, size, field, off) \
1881 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1882
d79b6df6 1883static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1884 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1885 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1886 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1887 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1888 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
0eb69bb9 1889 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0),
a8e4f0c4
OG		 1890
1891 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1892 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1893 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1894
1895 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1896 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1897 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1898 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1899 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1900 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1901 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1902 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1903 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1904
1905 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1906 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1907 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1908
1909 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1910 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1911};
1912
218d05ce
TZ		 1913/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
1914 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
1915 * says how many HW actions were actually parsed.
d79b6df6 1916 */
c500c86b 1917static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5
EB		 1918 struct mlx5e_tc_flow_parse_attr *parse_attr,
1919 struct netlink_ext_ack *extack)
d79b6df6
OG		 1920{
1921 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1922 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1923 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1924 struct mlx5_fields *f;
1925 u8 cmd, field_bsize;
e3ca4e05 1926 u32 s_mask, a_mask;
d79b6df6 1927 unsigned long mask;
2b64beba
OG		 1928 __be32 mask_be32;
1929 __be16 mask_be16;
d79b6df6
OG		 1930 void *action;
1931
73867881
PNA		 1932 set_masks = &hdrs[0].masks;
1933 add_masks = &hdrs[1].masks;
1934 set_vals = &hdrs[0].vals;
1935 add_vals = &hdrs[1].vals;
d79b6df6
OG		 1936
1937 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 1938 action = parse_attr->mod_hdr_actions +
1939 parse_attr->num_mod_hdr_actions * action_size;
1940
1941 max_actions = parse_attr->max_mod_hdr_actions;
1942 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 1943
1944 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1945 f = &fields[i];
1946 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1947 s_mask = 0;
1948 a_mask = 0;
d79b6df6
OG		 1949
1950 s_masks_p = (void *)set_masks + f->offset;
1951 a_masks_p = (void *)add_masks + f->offset;
1952
1953 memcpy(&s_mask, s_masks_p, f->size);
1954 memcpy(&a_mask, a_masks_p, f->size);
1955
1956 if (!s_mask && !a_mask) /* nothing to offload here */
1957 continue;
1958
1959 if (s_mask && a_mask) {
e98bedf5
EB		 1960 NL_SET_ERR_MSG_MOD(extack,
1961 "can't set and add to the same HW field");
d79b6df6
OG		 1962 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1963 return -EOPNOTSUPP;
1964 }
1965
1966 if (nactions == max_actions) {
e98bedf5
EB		 1967 NL_SET_ERR_MSG_MOD(extack,
1968 "too many pedit actions, can't offload");
d79b6df6
OG		 1969 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1970 return -EOPNOTSUPP;
1971 }
1972
1973 if (s_mask) {
1974 cmd = MLX5_ACTION_TYPE_SET;
1975 mask = s_mask;
1976 vals_p = (void *)set_vals + f->offset;
1977 /* clear to denote we consumed this field */
1978 memset(s_masks_p, 0, f->size);
1979 } else {
1980 cmd = MLX5_ACTION_TYPE_ADD;
1981 mask = a_mask;
1982 vals_p = (void *)add_vals + f->offset;
1983 /* clear to denote we consumed this field */
1984 memset(a_masks_p, 0, f->size);
1985 }
1986
d79b6df6 1987 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1988
2b64beba
OG		 1989 if (field_bsize == 32) {
1990 mask_be32 = *(__be32 *)&mask;
1991 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1992 } else if (field_bsize == 16) {
1993 mask_be16 = *(__be16 *)&mask;
1994 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1995 }
1996
d79b6df6 1997 first = find_first_bit(&mask, field_bsize);
2b64beba 1998 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1999 last = find_last_bit(&mask, field_bsize);
2b64beba 2000 if (first < next_z && next_z < last) {
e98bedf5
EB		 2001 NL_SET_ERR_MSG_MOD(extack,
2002 "rewrite of few sub-fields isn't supported");
2b64beba 2003 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2004 mask);
2005 return -EOPNOTSUPP;
2006 }
2007
2008 MLX5_SET(set_action_in, action, action_type, cmd);
2009 MLX5_SET(set_action_in, action, field, f->field);
2010
2011 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2012 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2013 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2014 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2015 }
2016
2017 if (field_bsize == 32)
2b64beba 2018 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2019 else if (field_bsize == 16)
2b64beba 2020 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2021 else if (field_bsize == 8)
2b64beba 2022 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2023
2024 action += action_size;
2025 nactions++;
2026 }
2027
2028 parse_attr->num_mod_hdr_actions = nactions;
2029 return 0;
2030}
2031
2032static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2033 struct pedit_headers_action *hdrs,
2034 int namespace,
d79b6df6
OG		 2035 struct mlx5e_tc_flow_parse_attr *parse_attr)
2036{
2037 int nkeys, action_size, max_actions;
2038
c500c86b
PNA		 2039 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2040 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2041 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2042
2043 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2044 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2045 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2046 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2047
2048 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2049 max_actions = min(max_actions, nkeys * 16);
2050
2051 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2052 if (!parse_attr->mod_hdr_actions)
2053 return -ENOMEM;
2054
218d05ce 2055 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2056 return 0;
2057}
2058
2059static const struct pedit_headers zero_masks = {};
2060
2061static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2062 const struct flow_action_entry *act, int namespace,
e98bedf5 2063 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2064 struct pedit_headers_action *hdrs,
e98bedf5 2065 struct netlink_ext_ack *extack)
d79b6df6 2066{
73867881
PNA		 2067 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2068 int err = -EOPNOTSUPP;
d79b6df6 2069 u32 mask, val, offset;
73867881 2070 u8 htype;
d79b6df6 2071
73867881
PNA		 2072 htype = act->mangle.htype;
2073 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2074
73867881
PNA		 2075 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2076 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2077 goto out_err;
2078 }
d79b6df6 2079
73867881
PNA		 2080 mask = act->mangle.mask;
2081 val = act->mangle.val;
2082 offset = act->mangle.offset;
d79b6df6 2083
73867881
PNA		 2084 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2085 if (err)
2086 goto out_err;
c500c86b 2087
73867881 2088 hdrs[cmd].pedits++;
d79b6df6 2089
c500c86b
PNA		 2090 return 0;
2091out_err:
2092 return err;
2093}
2094
2095static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2096 struct mlx5e_tc_flow_parse_attr *parse_attr,
2097 struct pedit_headers_action *hdrs,
2098 struct netlink_ext_ack *extack)
2099{
2100 struct pedit_headers *cmd_masks;
2101 int err;
2102 u8 cmd;
2103
218d05ce 2104 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2105 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2106 if (err)
2107 goto out_err;
2108 }
d79b6df6 2109
c500c86b 2110 err = offload_pedit_fields(hdrs, parse_attr, extack);
d79b6df6
OG		 2111 if (err < 0)
2112 goto out_dealloc_parsed_actions;
2113
2114 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2115 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2116 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2117 NL_SET_ERR_MSG_MOD(extack,
2118 "attempt to offload an unsupported field");
b3a433de 2119 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2120 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2121 16, 1, cmd_masks, sizeof(zero_masks), true);
2122 err = -EOPNOTSUPP;
2123 goto out_dealloc_parsed_actions;
2124 }
2125 }
2126
2127 return 0;
2128
2129out_dealloc_parsed_actions:
2130 kfree(parse_attr->mod_hdr_actions);
2131out_err:
2132 return err;
2133}
2134
e98bedf5
EB		 2135static bool csum_offload_supported(struct mlx5e_priv *priv,
2136 u32 action,
2137 u32 update_flags,
2138 struct netlink_ext_ack *extack)
26c02749
OG		 2139{
2140 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2141 TCA_CSUM_UPDATE_FLAG_UDP;
2142
2143 /* The HW recalcs checksums only if re-writing headers */
2144 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2145 NL_SET_ERR_MSG_MOD(extack,
2146 "TC csum action is only offloaded with pedit");
26c02749
OG		 2147 netdev_warn(priv->netdev,
2148 "TC csum action is only offloaded with pedit\n");
2149 return false;
2150 }
2151
2152 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2153 NL_SET_ERR_MSG_MOD(extack,
2154 "can't offload TC csum action for some header/s");
26c02749
OG		 2155 netdev_warn(priv->netdev,
2156 "can't offload TC csum action for some header/s - flags %#x\n",
2157 update_flags);
2158 return false;
2159 }
2160
2161 return true;
2162}
2163
bdd66ac0 2164static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2165 struct flow_action *flow_action,
1651925d 2166 u32 actions,
e98bedf5 2167 struct netlink_ext_ack *extack)
bdd66ac0 2168{
73867881 2169 const struct flow_action_entry *act;
bdd66ac0 2170 bool modify_ip_header;
bdd66ac0
OG		 2171 u8 htype, ip_proto;
2172 void *headers_v;
2173 u16 ethertype;
73867881 2174 int i;
bdd66ac0 2175
1651925d
GS		 2176 if (actions & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2177 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2178 else
2179 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2180
bdd66ac0
OG		 2181 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2182
2183 /* for non-IP we only re-write MACs, so we're okay */
2184 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2185 goto out_ok;
2186
2187 modify_ip_header = false;
73867881
PNA		 2188 flow_action_for_each(i, act, flow_action) {
2189 if (act->id != FLOW_ACTION_MANGLE &&
2190 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2191 continue;
2192
73867881
PNA		 2193 htype = act->mangle.htype;
2194 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4 ||
2195 htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2196 modify_ip_header = true;
2197 break;
bdd66ac0
OG		 2198 }
2199 }
2200
2201 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2202 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2203 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2204 NL_SET_ERR_MSG_MOD(extack,
2205 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2206 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2207 return false;
2208 }
2209
2210out_ok:
2211 return true;
2212}
2213
2214static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2215 struct flow_action *flow_action,
bdd66ac0 2216 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2217 struct mlx5e_tc_flow *flow,
2218 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2219{
2220 u32 actions;
2221
2222 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2223 actions = flow->esw_attr->action;
2224 else
2225 actions = flow->nic_attr->action;
2226
7e29392e
RD		 2227 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2228 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2229 return false;
2230
bdd66ac0 2231 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2232 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2233 flow_action, actions,
e98bedf5 2234 extack);
bdd66ac0
OG		 2235
2236 return true;
2237}
2238
5c65c564
OG		 2239static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2240{
2241 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2242 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2243
2244 fmdev = priv->mdev;
2245 pmdev = peer_priv->mdev;
2246
59c9d35e
AH		 2247 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2248 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2249
816f6706 2250 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2251}
2252
bdc837ee
EB		 2253static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2254 const struct flow_action_entry *act,
2255 struct mlx5e_tc_flow_parse_attr *parse_attr,
2256 struct pedit_headers_action *hdrs,
2257 u32 *action, struct netlink_ext_ack *extack)
2258{
2259 u16 mask16 = VLAN_VID_MASK;
2260 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2261 const struct flow_action_entry pedit_act = {
2262 .id = FLOW_ACTION_MANGLE,
2263 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2264 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2265 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2266 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2267 };
2268 int err;
2269
2270 if (act->vlan.prio) {
2271 NL_SET_ERR_MSG_MOD(extack, "Setting VLAN prio is not supported");
2272 return -EOPNOTSUPP;
2273 }
2274
2275 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2276 hdrs, NULL);
2277 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2278
2279 return err;
2280}
2281
73867881
PNA		 2282static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2283 struct flow_action *flow_action,
aa0cbbae 2284 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2285 struct mlx5e_tc_flow *flow,
2286 struct netlink_ext_ack *extack)
e3a2b7ed 2287{
aa0cbbae 2288 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2289 struct pedit_headers_action hdrs[2] = {};
2290 const struct flow_action_entry *act;
1cab1cd7 2291 u32 action = 0;
244cd96a 2292 int err, i;
e3a2b7ed 2293
73867881 2294 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2295 return -EINVAL;
2296
3bc4b7bf 2297 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2298
73867881
PNA		 2299 flow_action_for_each(i, act, flow_action) {
2300 switch (act->id) {
2301 case FLOW_ACTION_DROP:
1cab1cd7 2302 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2303 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2304 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2305 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2306 break;
2307 case FLOW_ACTION_MANGLE:
2308 case FLOW_ACTION_ADD:
2309 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2310 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2311 if (err)
2312 return err;
2313
1cab1cd7
OG		 2314 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2315 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2316 break;
bdc837ee
EB		 2317 case FLOW_ACTION_VLAN_MANGLE:
2318 err = add_vlan_rewrite_action(priv,
2319 MLX5_FLOW_NAMESPACE_KERNEL,
2320 act, parse_attr, hdrs,
2321 &action, extack);
2322 if (err)
2323 return err;
2324
2325 break;
73867881 2326 case FLOW_ACTION_CSUM:
1cab1cd7 2327 if (csum_offload_supported(priv, action,
73867881 2328 act->csum_flags,
e98bedf5 2329 extack))
73867881 2330 break;
26c02749
OG		 2331
2332 return -EOPNOTSUPP;
73867881
PNA		 2333 case FLOW_ACTION_REDIRECT: {
2334 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2335
2336 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2337 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2338 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
5c65c564 2339 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2340 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2341 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2342 } else {
e98bedf5
EB		 2343 NL_SET_ERR_MSG_MOD(extack,
2344 "device is not on same HW, can't offload");
5c65c564
OG		 2345 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2346 peer_dev->name);
2347 return -EINVAL;
2348 }
73867881
PNA		 2349 }
2350 break;
2351 case FLOW_ACTION_MARK: {
2352 u32 mark = act->mark;
e3a2b7ed
AV		 2353
2354 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2355 NL_SET_ERR_MSG_MOD(extack,
2356 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2357 return -EINVAL;
2358 }
2359
3bc4b7bf 2360 attr->flow_tag = mark;
1cab1cd7 2361 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2362 }
2363 break;
2364 default:
2365 return -EINVAL;
e3a2b7ed 2366 }
e3a2b7ed
AV		 2367 }
2368
c500c86b
PNA		 2369 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2370 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2371 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2372 parse_attr, hdrs, extack);
2373 if (err)
2374 return err;
2375 }
2376
1cab1cd7 2377 attr->action = action;
73867881 2378 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2379 return -EOPNOTSUPP;
2380
e3a2b7ed
AV		 2381 return 0;
2382}
2383
76f7444d
OG		 2384static inline int cmp_encap_info(struct ip_tunnel_key *a,
2385 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2386{
2387 return memcmp(a, b, sizeof(*a));
2388}
2389
76f7444d 2390static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2391{
76f7444d 2392 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2393}
2394
a54e20b4 2395
b1d90e6b
RL		 2396static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2397 struct net_device *peer_netdev)
2398{
2399 struct mlx5e_priv *peer_priv;
2400
2401 peer_priv = netdev_priv(peer_netdev);
2402
2403 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2404 mlx5e_eswitch_rep(priv->netdev) &&
2405 mlx5e_eswitch_rep(peer_netdev) &&
2406 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2407}
2408
32f3671f 2409
f5bc2c5d 2410
a54e20b4 2411static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 2412 struct mlx5e_tc_flow *flow,
733d4f36
RD		 2413 struct net_device *mirred_dev,
2414 int out_index,
8c4dc42b 2415 struct netlink_ext_ack *extack,
0ad060ee
RD		 2416 struct net_device **encap_dev,
2417 bool *encap_valid)
a54e20b4
HHZ		 2418{
2419 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 2420 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36
RD		 2421 struct mlx5e_tc_flow_parse_attr *parse_attr;
2422 struct ip_tunnel_info *tun_info;
2423 struct ip_tunnel_key *key;
c1ae1152 2424 struct mlx5e_encap_entry *e;
733d4f36 2425 unsigned short family;
a54e20b4
HHZ		 2426 uintptr_t hash_key;
2427 bool found = false;
54c177ca 2428 int err = 0;
a54e20b4 2429
733d4f36
RD		 2430 parse_attr = attr->parse_attr;
2431 tun_info = &parse_attr->tun_info[out_index];
2432 family = ip_tunnel_info_af(tun_info);
2433 key = &tun_info->key;
2434
76f7444d 2435 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2436
2437 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2438 encap_hlist, hash_key) {
76f7444d 2439 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2440 found = true;
2441 break;
2442 }
2443 }
2444
b2812089 2445 /* must verify if encap is valid or not */
45247bf2
OG		 2446 if (found)
2447 goto attach_flow;
a54e20b4
HHZ		 2448
2449 e = kzalloc(sizeof(*e), GFP_KERNEL);
2450 if (!e)
2451 return -ENOMEM;
2452
76f7444d 2453 e->tun_info = *tun_info;
101f4de9 2454 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2455 if (err)
2456 goto out_err;
2457
a54e20b4
HHZ		 2458 INIT_LIST_HEAD(&e->flows);
2459
ce99f6b9 2460 if (family == AF_INET)
101f4de9 2461 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2462 else if (family == AF_INET6)
101f4de9 2463 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2464
0ad060ee 2465 if (err)
a54e20b4
HHZ		 2466 goto out_err;
2467
a54e20b4
HHZ		 2468 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2469
45247bf2 2470attach_flow:
8c4dc42b
EB		 2471 list_add(&flow->encaps[out_index].list, &e->flows);
2472 flow->encaps[out_index].index = out_index;
45247bf2 2473 *encap_dev = e->out_dev;
8c4dc42b
EB		 2474 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2475 attr->dests[out_index].encap_id = e->encap_id;
2476 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 2477 *encap_valid = true;
8c4dc42b 2478 } else {
0ad060ee 2479 *encap_valid = false;
8c4dc42b 2480 }
45247bf2 2481
232c0013 2482 return err;
a54e20b4
HHZ		 2483
2484out_err:
2485 kfree(e);
2486 return err;
2487}
2488
1482bd3d 2489static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2490 const struct flow_action_entry *act,
1482bd3d
JL		 2491 struct mlx5_esw_flow_attr *attr,
2492 u32 *action)
2493{
cc495188
JL		 2494 u8 vlan_idx = attr->total_vlan;
2495
2496 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2497 return -EOPNOTSUPP;
2498
73867881
PNA		 2499 switch (act->id) {
2500 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2501 if (vlan_idx) {
2502 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2503 MLX5_FS_VLAN_DEPTH))
2504 return -EOPNOTSUPP;
2505
2506 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2507 } else {
2508 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2509 }
73867881
PNA		 2510 break;
2511 case FLOW_ACTION_VLAN_PUSH:
2512 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2513 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2514 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2515 if (!attr->vlan_proto[vlan_idx])
2516 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2517
2518 if (vlan_idx) {
2519 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2520 MLX5_FS_VLAN_DEPTH))
2521 return -EOPNOTSUPP;
2522
2523 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2524 } else {
2525 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2526 (act->vlan.proto != htons(ETH_P_8021Q) ||
2527 act->vlan.prio))
cc495188
JL		 2528 return -EOPNOTSUPP;
2529
2530 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2531 }
73867881
PNA		 2532 break;
2533 default:
bdc837ee 2534 return -EINVAL;
1482bd3d
JL		 2535 }
2536
cc495188
JL		 2537 attr->total_vlan = vlan_idx + 1;
2538
1482bd3d
JL		 2539 return 0;
2540}
2541
73867881
PNA		 2542static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2543 struct flow_action *flow_action,
d7e75a32 2544 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2545 struct mlx5e_tc_flow *flow,
2546 struct netlink_ext_ack *extack)
03a9d11e 2547{
73867881 2548 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2549 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2550 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2551 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2552 const struct ip_tunnel_info *info = NULL;
2553 const struct flow_action_entry *act;
a54e20b4 2554 bool encap = false;
1cab1cd7 2555 u32 action = 0;
244cd96a 2556 int err, i;
03a9d11e 2557
73867881 2558 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2559 return -EINVAL;
2560
1d447a39 2561 attr->in_rep = rpriv->rep;
10ff5359 2562 attr->in_mdev = priv->mdev;
03a9d11e 2563
73867881
PNA		 2564 flow_action_for_each(i, act, flow_action) {
2565 switch (act->id) {
2566 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2567 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2568 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2569 break;
2570 case FLOW_ACTION_MANGLE:
2571 case FLOW_ACTION_ADD:
2572 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 2573 parse_attr, hdrs, extack);
d7e75a32
OG		 2574 if (err)
2575 return err;
2576
1cab1cd7 2577 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2578 attr->split_count = attr->out_count;
73867881
PNA		 2579 break;
2580 case FLOW_ACTION_CSUM:
1cab1cd7 2581 if (csum_offload_supported(priv, action,
73867881
PNA		 2582 act->csum_flags, extack))
2583 break;
26c02749
OG		 2584
2585 return -EOPNOTSUPP;
73867881
PNA		 2586 case FLOW_ACTION_REDIRECT:
2587 case FLOW_ACTION_MIRRED: {
03a9d11e 2588 struct mlx5e_priv *out_priv;
592d3651 2589 struct net_device *out_dev;
03a9d11e 2590
73867881 2591 out_dev = act->dev;
ef381359
OS		 2592 if (!out_dev) {
2593 /* out_dev is NULL when filters with
2594 * non-existing mirred device are replayed to
2595 * the driver.
2596 */
2597 return -EINVAL;
2598 }
03a9d11e 2599
592d3651 2600 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2601 NL_SET_ERR_MSG_MOD(extack,
2602 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2603 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2604 attr->out_count);
2605 return -EOPNOTSUPP;
2606 }
2607
f493f155
EB		 2608 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2609 MLX5_FLOW_CONTEXT_ACTION_COUNT;
6dcfa234
FF		 2610 if (netdev_port_same_parent_id(priv->netdev,
2611 out_dev) ||
b1d90e6b 2612 is_merged_eswitch_dev(priv, out_dev)) {
7ba58ba7
RL		 2613 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2614 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
2615 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev);
2616
2617 if (uplink_upper &&
2618 netif_is_lag_master(uplink_upper) &&
2619 uplink_upper == out_dev)
2620 out_dev = uplink_dev;
2621
a0646c88
EB		 2622 if (!mlx5e_eswitch_rep(out_dev))
2623 return -EOPNOTSUPP;
2624
a54e20b4 2625 out_priv = netdev_priv(out_dev);
1d447a39 2626 rpriv = out_priv->ppriv;
df65a573
EB		 2627 attr->dests[attr->out_count].rep = rpriv->rep;
2628 attr->dests[attr->out_count].mdev = out_priv->mdev;
2629 attr->out_count++;
a54e20b4 2630 } else if (encap) {
8c4dc42b
EB		 2631 parse_attr->mirred_ifindex[attr->out_count] =
2632 out_dev->ifindex;
2633 parse_attr->tun_info[attr->out_count] = *info;
2634 encap = false;
3c37745e 2635 attr->parse_attr = parse_attr;
f493f155
EB		 2636 attr->dests[attr->out_count].flags |=
2637 MLX5_ESW_DEST_ENCAP;
1cc26d74 2638 attr->out_count++;
df65a573
EB		 2639 /* attr->dests[].rep is resolved when we
2640 * handle encap
2641 */
ef381359
OS		 2642 } else if (parse_attr->filter_dev != priv->netdev) {
2643 /* All mlx5 devices are called to configure
2644 * high level device filters. Therefore, the
2645 * *attempt* to install a filter on invalid
2646 * eswitch should not trigger an explicit error
2647 */
2648 return -EINVAL;
a54e20b4 2649 } else {
e98bedf5
EB		 2650 NL_SET_ERR_MSG_MOD(extack,
2651 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2652 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2653 priv->netdev->name, out_dev->name);
2654 return -EINVAL;
2655 }
73867881
PNA		 2656 }
2657 break;
2658 case FLOW_ACTION_TUNNEL_ENCAP:
2659 info = act->tunnel;
a54e20b4
HHZ		 2660 if (info)
2661 encap = true;
2662 else
2663 return -EOPNOTSUPP;
1482bd3d 2664
73867881
PNA		 2665 break;
2666 case FLOW_ACTION_VLAN_PUSH:
2667 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 2668 if (act->id == FLOW_ACTION_VLAN_PUSH &&
2669 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
2670 /* Replace vlan pop+push with vlan modify */
2671 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2672 err = add_vlan_rewrite_action(priv,
2673 MLX5_FLOW_NAMESPACE_FDB,
2674 act, parse_attr, hdrs,
2675 &action, extack);
2676 } else {
2677 err = parse_tc_vlan_action(priv, act, attr, &action);
2678 }
1482bd3d
JL		 2679 if (err)
2680 return err;
2681
bdc837ee
EB		 2682 attr->split_count = attr->out_count;
2683 break;
2684 case FLOW_ACTION_VLAN_MANGLE:
2685 err = add_vlan_rewrite_action(priv,
2686 MLX5_FLOW_NAMESPACE_FDB,
2687 act, parse_attr, hdrs,
2688 &action, extack);
2689 if (err)
2690 return err;
2691
e85e02ba 2692 attr->split_count = attr->out_count;
73867881
PNA		 2693 break;
2694 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 2695 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 2696 break;
2697 case FLOW_ACTION_GOTO: {
2698 u32 dest_chain = act->chain_index;
bf07aa73
PB		 2699 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2700
2701 if (dest_chain <= attr->chain) {
2702 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2703 return -EOPNOTSUPP;
2704 }
2705 if (dest_chain > max_chain) {
2706 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2707 return -EOPNOTSUPP;
2708 }
e88afe75 2709 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 2710 attr->dest_chain = dest_chain;
73867881
PNA		 2711 break;
2712 }
2713 default:
2714 return -EINVAL;
bf07aa73 2715 }
03a9d11e 2716 }
bdd66ac0 2717
c500c86b
PNA		 2718 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2719 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2720 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2721 parse_attr, hdrs, extack);
2722 if (err)
2723 return err;
2724 }
2725
1cab1cd7 2726 attr->action = action;
73867881 2727 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2728 return -EOPNOTSUPP;
2729
e88afe75
OG		 2730 if (attr->dest_chain) {
2731 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2732 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
2733 return -EOPNOTSUPP;
2734 }
2735 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2736 }
2737
e85e02ba 2738 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2739 NL_SET_ERR_MSG_MOD(extack,
2740 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2741 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2742 return -EOPNOTSUPP;
2743 }
2744
31c8eba5 2745 return 0;
03a9d11e
OG		 2746}
2747
5dbe906f 2748static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2749{
5dbe906f 2750 u16 __flow_flags = 0;
60bd4af8
OG		 2751
2752 if (flags & MLX5E_TC_INGRESS)
2753 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2754 if (flags & MLX5E_TC_EGRESS)
2755 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2756
d9ee0491
OG		 2757 if (flags & MLX5E_TC_ESW_OFFLOAD)
2758 __flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2759 if (flags & MLX5E_TC_NIC_OFFLOAD)
2760 __flow_flags |= MLX5E_TC_FLOW_NIC;
2761
60bd4af8
OG		 2762 *flow_flags = __flow_flags;
2763}
2764
05866c82
OG		 2765static const struct rhashtable_params tc_ht_params = {
2766 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2767 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2768 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2769 .automatic_shrinking = true,
2770};
2771
d9ee0491 2772static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags)
05866c82 2773{
655dc3d2
OG		 2774 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2775 struct mlx5e_rep_priv *uplink_rpriv;
2776
d9ee0491 2777 if (flags & MLX5E_TC_ESW_OFFLOAD) {
655dc3d2 2778 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 2779 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 2780 } else /* NIC offload */
655dc3d2 2781 return &priv->fs.tc.ht;
05866c82
OG		 2782}
2783
04de7dda
RD		 2784static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
2785{
1418ddd9 2786 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 2787 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
1418ddd9
AH		 2788 flow->flags & MLX5E_TC_FLOW_INGRESS;
2789 bool act_is_encap = !!(attr->action &
2790 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
2791 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
2792 MLX5_DEVCOM_ESW_OFFLOADS);
2793
10fbb1cd
RD		 2794 if (!esw_paired)
2795 return false;
2796
2797 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
2798 mlx5_lag_is_multipath(attr->in_mdev)) &&
2799 (is_rep_ingress || act_is_encap))
2800 return true;
2801
2802 return false;
04de7dda
RD		 2803}
2804
a88780a9
RD		 2805static int
2806mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 2807 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 2808 struct mlx5e_tc_flow_parse_attr **__parse_attr,
2809 struct mlx5e_tc_flow **__flow)
e3a2b7ed 2810{
17091853 2811 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 2812 struct mlx5e_tc_flow *flow;
a88780a9 2813 int err;
e3a2b7ed 2814
65ba8fb7 2815 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2816 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2817 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2818 err = -ENOMEM;
2819 goto err_free;
2820 }
2821
2822 flow->cookie = f->cookie;
65ba8fb7 2823 flow->flags = flow_flags;
655dc3d2 2824 flow->priv = priv;
e3a2b7ed 2825
a88780a9
RD		 2826 *__flow = flow;
2827 *__parse_attr = parse_attr;
2828
2829 return 0;
2830
2831err_free:
2832 kfree(flow);
2833 kvfree(parse_attr);
2834 return err;
2835}
2836
988ab9c7
TZ		 2837static void
2838mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
2839 struct mlx5e_priv *priv,
2840 struct mlx5e_tc_flow_parse_attr *parse_attr,
2841 struct tc_cls_flower_offload *f,
2842 struct mlx5_eswitch_rep *in_rep,
2843 struct mlx5_core_dev *in_mdev)
2844{
2845 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2846
2847 esw_attr->parse_attr = parse_attr;
2848 esw_attr->chain = f->common.chain_index;
2849 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
2850
2851 esw_attr->in_rep = in_rep;
2852 esw_attr->in_mdev = in_mdev;
2853
2854 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
2855 MLX5_COUNTER_SOURCE_ESWITCH)
2856 esw_attr->counter_dev = in_mdev;
2857 else
2858 esw_attr->counter_dev = priv->mdev;
2859}
2860
71129676 2861static struct mlx5e_tc_flow *
04de7dda
RD		 2862__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2863 struct tc_cls_flower_offload *f,
2864 u16 flow_flags,
2865 struct net_device *filter_dev,
2866 struct mlx5_eswitch_rep *in_rep,
71129676 2867 struct mlx5_core_dev *in_mdev)
a88780a9 2868{
73867881 2869 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 2870 struct netlink_ext_ack *extack = f->common.extack;
2871 struct mlx5e_tc_flow_parse_attr *parse_attr;
2872 struct mlx5e_tc_flow *flow;
2873 int attr_size, err;
e3a2b7ed 2874
a88780a9
RD		 2875 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2876 attr_size = sizeof(struct mlx5_esw_flow_attr);
2877 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2878 &parse_attr, &flow);
2879 if (err)
2880 goto out;
988ab9c7 2881
d11afc26 2882 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 2883 mlx5e_flow_esw_attr_init(flow->esw_attr,
2884 priv, parse_attr,
2885 f, in_rep, in_mdev);
2886
54c177ca
OS		 2887 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2888 f, filter_dev);
d11afc26
OS		 2889 if (err)
2890 goto err_free;
a88780a9 2891
73867881 2892 err = parse_tc_fdb_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 2893 if (err)
2894 goto err_free;
2895
7040632d 2896 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
ef06c9ee
RD		 2897 if (err) {
2898 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
2899 goto err_free;
2900
b4a23329 2901 add_unready_flow(flow);
ef06c9ee 2902 }
e3a2b7ed 2903
71129676 2904 return flow;
a88780a9
RD		 2905
2906err_free:
2907 kfree(flow);
2908 kvfree(parse_attr);
2909out:
71129676 2910 return ERR_PTR(err);
a88780a9
RD		 2911}
2912
04de7dda 2913static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
95dc1902
RD		 2914 struct mlx5e_tc_flow *flow,
2915 u16 flow_flags)
04de7dda
RD		 2916{
2917 struct mlx5e_priv *priv = flow->priv, *peer_priv;
2918 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
2919 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
2920 struct mlx5e_tc_flow_parse_attr *parse_attr;
2921 struct mlx5e_rep_priv *peer_urpriv;
2922 struct mlx5e_tc_flow *peer_flow;
2923 struct mlx5_core_dev *in_mdev;
2924 int err = 0;
2925
2926 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2927 if (!peer_esw)
2928 return -ENODEV;
2929
2930 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
2931 peer_priv = netdev_priv(peer_urpriv->netdev);
2932
2933 /* in_mdev is assigned of which the packet originated from.
2934 * So packets redirected to uplink use the same mdev of the
2935 * original flow and packets redirected from uplink use the
2936 * peer mdev.
2937 */
b05af6aa 2938 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 2939 in_mdev = peer_priv->mdev;
2940 else
2941 in_mdev = priv->mdev;
2942
2943 parse_attr = flow->esw_attr->parse_attr;
95dc1902 2944 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 2945 parse_attr->filter_dev,
2946 flow->esw_attr->in_rep, in_mdev);
2947 if (IS_ERR(peer_flow)) {
2948 err = PTR_ERR(peer_flow);
04de7dda 2949 goto out;
71129676 2950 }
04de7dda
RD		 2951
2952 flow->peer_flow = peer_flow;
2953 flow->flags |= MLX5E_TC_FLOW_DUP;
2954 mutex_lock(&esw->offloads.peer_mutex);
2955 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
2956 mutex_unlock(&esw->offloads.peer_mutex);
2957
2958out:
2959 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2960 return err;
2961}
2962
2963static int
2964mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2965 struct tc_cls_flower_offload *f,
2966 u16 flow_flags,
2967 struct net_device *filter_dev,
2968 struct mlx5e_tc_flow **__flow)
2969{
2970 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2971 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
2972 struct mlx5_core_dev *in_mdev = priv->mdev;
2973 struct mlx5e_tc_flow *flow;
2974 int err;
2975
71129676
JG		 2976 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
2977 in_mdev);
2978 if (IS_ERR(flow))
2979 return PTR_ERR(flow);
04de7dda
RD		 2980
2981 if (is_peer_flow_needed(flow)) {
95dc1902 2982 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 2983 if (err) {
2984 mlx5e_tc_del_fdb_flow(priv, flow);
2985 goto out;
2986 }
2987 }
2988
2989 *__flow = flow;
2990
2991 return 0;
2992
2993out:
2994 return err;
2995}
2996
a88780a9
RD		 2997static int
2998mlx5e_add_nic_flow(struct mlx5e_priv *priv,
2999 struct tc_cls_flower_offload *f,
5dbe906f 3000 u16 flow_flags,
d11afc26 3001 struct net_device *filter_dev,
a88780a9
RD		 3002 struct mlx5e_tc_flow **__flow)
3003{
73867881 3004 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 3005 struct netlink_ext_ack *extack = f->common.extack;
3006 struct mlx5e_tc_flow_parse_attr *parse_attr;
3007 struct mlx5e_tc_flow *flow;
3008 int attr_size, err;
3009
bf07aa73
PB		 3010 /* multi-chain not supported for NIC rules */
3011 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3012 return -EOPNOTSUPP;
3013
a88780a9
RD		 3014 flow_flags |= MLX5E_TC_FLOW_NIC;
3015 attr_size = sizeof(struct mlx5_nic_flow_attr);
3016 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3017 &parse_attr, &flow);
3018 if (err)
3019 goto out;
3020
d11afc26 3021 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3022 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3023 f, filter_dev);
d11afc26
OS		 3024 if (err)
3025 goto err_free;
3026
73867881 3027 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3028 if (err)
3029 goto err_free;
3030
3031 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3032 if (err)
3033 goto err_free;
3034
3035 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
3036 kvfree(parse_attr);
3037 *__flow = flow;
3038
3039 return 0;
e3a2b7ed 3040
e3a2b7ed 3041err_free:
a88780a9 3042 kfree(flow);
17091853 3043 kvfree(parse_attr);
a88780a9
RD		 3044out:
3045 return err;
3046}
3047
3048static int
3049mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3050 struct tc_cls_flower_offload *f,
3051 int flags,
d11afc26 3052 struct net_device *filter_dev,
a88780a9
RD		 3053 struct mlx5e_tc_flow **flow)
3054{
3055 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 3056 u16 flow_flags;
a88780a9
RD		 3057 int err;
3058
3059 get_flags(flags, &flow_flags);
3060
bf07aa73
PB		 3061 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3062 return -EOPNOTSUPP;
3063
a88780a9 3064 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 3065 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3066 filter_dev, flow);
a88780a9 3067 else
d11afc26
OS		 3068 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3069 filter_dev, flow);
a88780a9
RD		 3070
3071 return err;
3072}
3073
71d82d2a 3074int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 3075 struct tc_cls_flower_offload *f, int flags)
3076{
3077 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3078 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3079 struct mlx5e_tc_flow *flow;
3080 int err = 0;
3081
3082 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3083 if (flow) {
3084 NL_SET_ERR_MSG_MOD(extack,
3085 "flow cookie already exists, ignoring");
3086 netdev_warn_once(priv->netdev,
3087 "flow cookie %lx already exists, ignoring\n",
3088 f->cookie);
3089 goto out;
3090 }
3091
d11afc26 3092 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3093 if (err)
3094 goto out;
3095
3096 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
3097 if (err)
3098 goto err_free;
3099
3100 return 0;
3101
3102err_free:
3103 mlx5e_tc_del_flow(priv, flow);
232c0013 3104 kfree(flow);
a88780a9 3105out:
e3a2b7ed
AV		 3106 return err;
3107}
3108
8f8ae895
OG		 3109#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
3110#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
3111
3112static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3113{
3114 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
3115 return true;
3116
3117 return false;
3118}
3119
71d82d2a 3120int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3121 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3122{
d9ee0491 3123 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3124 struct mlx5e_tc_flow *flow;
e3a2b7ed 3125
05866c82 3126 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3127 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3128 return -EINVAL;
3129
05866c82 3130 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3131
961e8979 3132 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3133
3134 kfree(flow);
3135
3136 return 0;
3137}
3138
71d82d2a 3139int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3140 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3141{
04de7dda 3142 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3143 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3144 struct mlx5_eswitch *peer_esw;
aad7e08d 3145 struct mlx5e_tc_flow *flow;
aad7e08d 3146 struct mlx5_fc *counter;
316d5f72
RD		 3147 u64 lastuse = 0;
3148 u64 packets = 0;
3149 u64 bytes = 0;
aad7e08d 3150
05866c82 3151 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3152 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3153 return -EINVAL;
3154
316d5f72
RD		 3155 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
3156 counter = mlx5e_tc_get_counter(flow);
3157 if (!counter)
3158 return 0;
aad7e08d 3159
316d5f72
RD		 3160 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3161 }
aad7e08d 3162
316d5f72
RD		 3163 /* Under multipath it's possible for one rule to be currently
3164 * un-offloaded while the other rule is offloaded.
3165 */
04de7dda
RD		 3166 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3167 if (!peer_esw)
3168 goto out;
3169
3170 if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3171 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3172 u64 bytes2;
3173 u64 packets2;
3174 u64 lastuse2;
3175
3176 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3177 if (!counter)
3178 goto no_peer_counter;
04de7dda
RD		 3179 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3180
3181 bytes += bytes2;
3182 packets += packets2;
3183 lastuse = max_t(u64, lastuse, lastuse2);
3184 }
3185
316d5f72 3186no_peer_counter:
04de7dda 3187 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3188out:
3b1903ef 3189 flow_stats_update(&f->stats, bytes, packets, lastuse);
fed06ee8 3190
aad7e08d
AV		 3191 return 0;
3192}
3193
4d8fcf21
AH		 3194static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3195 struct mlx5e_priv *peer_priv)
3196{
3197 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3198 struct mlx5e_hairpin_entry *hpe;
3199 u16 peer_vhca_id;
3200 int bkt;
3201
3202 if (!same_hw_devs(priv, peer_priv))
3203 return;
3204
3205 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3206
3207 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3208 if (hpe->peer_vhca_id == peer_vhca_id)
3209 hpe->hp->pair->peer_gone = true;
3210 }
3211}
3212
3213static int mlx5e_tc_netdev_event(struct notifier_block *this,
3214 unsigned long event, void *ptr)
3215{
3216 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3217 struct mlx5e_flow_steering *fs;
3218 struct mlx5e_priv *peer_priv;
3219 struct mlx5e_tc_table *tc;
3220 struct mlx5e_priv *priv;
3221
3222 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3223 event != NETDEV_UNREGISTER ||
3224 ndev->reg_state == NETREG_REGISTERED)
3225 return NOTIFY_DONE;
3226
3227 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3228 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3229 priv = container_of(fs, struct mlx5e_priv, fs);
3230 peer_priv = netdev_priv(ndev);
3231 if (priv == peer_priv ||
3232 !(priv->netdev->features & NETIF_F_HW_TC))
3233 return NOTIFY_DONE;
3234
3235 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3236
3237 return NOTIFY_DONE;
3238}
3239
655dc3d2 3240int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3241{
acff797c 3242 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3243 int err;
e8f887ac 3244
11c9c548 3245 hash_init(tc->mod_hdr_tbl);
5c65c564 3246 hash_init(tc->hairpin_tbl);
11c9c548 3247
4d8fcf21
AH		 3248 err = rhashtable_init(&tc->ht, &tc_ht_params);
3249 if (err)
3250 return err;
3251
3252 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3253 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3254 tc->netdevice_nb.notifier_call = NULL;
3255 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3256 }
3257
3258 return err;
e8f887ac
AV		 3259}
3260
3261static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3262{
3263 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3264 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3265
961e8979 3266 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3267 kfree(flow);
3268}
3269
655dc3d2 3270void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3271{
acff797c 3272 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3273
4d8fcf21
AH		 3274 if (tc->netdevice_nb.notifier_call)
3275 unregister_netdevice_notifier(&tc->netdevice_nb);
3276
d9ee0491 3277 rhashtable_destroy(&tc->ht);
e8f887ac 3278
acff797c
MG		 3279 if (!IS_ERR_OR_NULL(tc->t)) {
3280 mlx5_destroy_flow_table(tc->t);
3281 tc->t = NULL;
e8f887ac
AV		 3282 }
3283}
655dc3d2
OG		 3284
3285int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3286{
3287 return rhashtable_init(tc_ht, &tc_ht_params);
3288}
3289
3290void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3291{
3292 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3293}
01252a27 3294
d9ee0491 3295int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags)
01252a27 3296{
d9ee0491 3297 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3298
3299 return atomic_read(&tc_ht->nelems);
3300}
04de7dda
RD		 3301
3302void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3303{
3304 struct mlx5e_tc_flow *flow, *tmp;
3305
3306 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3307 __mlx5e_tc_del_fdb_peer_flow(flow);
3308}
b4a23329
RD		 3309
3310void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
3311{
3312 struct mlx5_rep_uplink_priv *rpriv =
3313 container_of(work, struct mlx5_rep_uplink_priv,
3314 reoffload_flows_work);
3315 struct mlx5e_tc_flow *flow, *tmp;
3316
3317 rtnl_lock();
3318 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
3319 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
3320 remove_unready_flow(flow);
3321 }
3322 rtnl_unlock();
3323}
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