]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5e: Extendable vport representor netdev private data
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
a54e20b4 46#include <net/vxlan.h>
e8f887ac
AV		 47#include "en.h"
48#include "en_tc.h"
1d447a39 49#include "en_rep.h"
03a9d11e 50#include "eswitch.h"
bbd00f7e 51#include "vxlan.h"
e8f887ac 52
3bc4b7bf
OG		 53struct mlx5_nic_flow_attr {
54 u32 action;
55 u32 flow_tag;
2f4fe4ca 56 u32 mod_hdr_id;
3bc4b7bf
OG		 57};
58
65ba8fb7
OG		 59enum {
60 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 61 MLX5E_TC_FLOW_NIC = BIT(1),
65ba8fb7
OG		 62};
63
e8f887ac
AV		 64struct mlx5e_tc_flow {
65 struct rhash_head node;
66 u64 cookie;
65ba8fb7 67 u8 flags;
74491de9 68 struct mlx5_flow_handle *rule;
a54e20b4 69 struct list_head encap; /* flows sharing the same encap */
3bc4b7bf
OG		 70 union {
71 struct mlx5_esw_flow_attr esw_attr[0];
72 struct mlx5_nic_flow_attr nic_attr[0];
73 };
e8f887ac
AV		 74};
75
17091853
OG		 76struct mlx5e_tc_flow_parse_attr {
77 struct mlx5_flow_spec spec;
d79b6df6
OG		 78 int num_mod_hdr_actions;
79 void *mod_hdr_actions;
17091853
OG		 80};
81
a54e20b4
HHZ		 82enum {
83 MLX5_HEADER_TYPE_VXLAN = 0x0,
84 MLX5_HEADER_TYPE_NVGRE = 0x1,
85};
86
acff797c
MG		 87#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
88#define MLX5E_TC_TABLE_NUM_GROUPS 4
e8f887ac 89
74491de9
MB		 90static struct mlx5_flow_handle *
91mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 92 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 93 struct mlx5e_tc_flow *flow)
e8f887ac 94{
aa0cbbae 95 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 96 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 97 struct mlx5_flow_destination dest = {};
66958ed9 98 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 99 .action = attr->action,
100 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 101 .encap_id = 0,
102 };
aad7e08d 103 struct mlx5_fc *counter = NULL;
74491de9 104 struct mlx5_flow_handle *rule;
e8f887ac 105 bool table_created = false;
2f4fe4ca 106 int err;
e8f887ac 107
3bc4b7bf 108 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV		 109 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
110 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 111 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV		 112 counter = mlx5_fc_create(dev, true);
113 if (IS_ERR(counter))
114 return ERR_CAST(counter);
115
116 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
117 dest.counter = counter;
118 }
119
2f4fe4ca
OG		 120 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
121 err = mlx5_modify_header_alloc(dev, MLX5_FLOW_NAMESPACE_KERNEL,
122 parse_attr->num_mod_hdr_actions,
123 parse_attr->mod_hdr_actions,
124 &attr->mod_hdr_id);
d7e75a32 125 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 126 kfree(parse_attr->mod_hdr_actions);
127 if (err) {
128 rule = ERR_PTR(err);
129 goto err_create_mod_hdr_id;
130 }
131 }
132
acff797c
MG		 133 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
134 priv->fs.tc.t =
135 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
136 MLX5E_TC_PRIO,
137 MLX5E_TC_TABLE_NUM_ENTRIES,
138 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 139 0, 0);
acff797c 140 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 141 netdev_err(priv->netdev,
142 "Failed to create tc offload table\n");
aad7e08d
AV		 143 rule = ERR_CAST(priv->fs.tc.t);
144 goto err_create_ft;
e8f887ac
AV		 145 }
146
147 table_created = true;
148 }
149
17091853
OG		 150 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
151 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
152 &flow_act, &dest, 1);
aad7e08d
AV		 153
154 if (IS_ERR(rule))
155 goto err_add_rule;
156
157 return rule;
e8f887ac 158
aad7e08d
AV		 159err_add_rule:
160 if (table_created) {
acff797c
MG		 161 mlx5_destroy_flow_table(priv->fs.tc.t);
162 priv->fs.tc.t = NULL;
e8f887ac 163 }
aad7e08d 164err_create_ft:
2f4fe4ca
OG		 165 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
166 mlx5_modify_header_dealloc(priv->mdev,
167 attr->mod_hdr_id);
168err_create_mod_hdr_id:
aad7e08d 169 mlx5_fc_destroy(dev, counter);
e8f887ac
AV		 170
171 return rule;
172}
173
d85cdccb
OG		 174static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
175 struct mlx5e_tc_flow *flow)
176{
177 struct mlx5_fc *counter = NULL;
178
aa0cbbae
OG		 179 counter = mlx5_flow_rule_counter(flow->rule);
180 mlx5_del_flow_rules(flow->rule);
181 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG		 182
183 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
184 mlx5_destroy_flow_table(priv->fs.tc.t);
185 priv->fs.tc.t = NULL;
186 }
2f4fe4ca
OG		 187
188 if (flow->nic_attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
189 mlx5_modify_header_dealloc(priv->mdev,
190 flow->nic_attr->mod_hdr_id);
d85cdccb
OG		 191}
192
aa0cbbae
OG		 193static void mlx5e_detach_encap(struct mlx5e_priv *priv,
194 struct mlx5e_tc_flow *flow);
195
74491de9
MB		 196static struct mlx5_flow_handle *
197mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 198 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 199 struct mlx5e_tc_flow *flow)
adb4c123
OG		 200{
201 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae
OG		 202 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
203 struct mlx5_flow_handle *rule;
8b32580d
OG		 204 int err;
205
206 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 207 if (err) {
208 rule = ERR_PTR(err);
209 goto err_add_vlan;
210 }
adb4c123 211
d7e75a32
OG		 212 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
213 err = mlx5_modify_header_alloc(priv->mdev, MLX5_FLOW_NAMESPACE_FDB,
214 parse_attr->num_mod_hdr_actions,
215 parse_attr->mod_hdr_actions,
216 &attr->mod_hdr_id);
217 kfree(parse_attr->mod_hdr_actions);
218 if (err) {
219 rule = ERR_PTR(err);
220 goto err_mod_hdr;
221 }
222 }
223
aa0cbbae
OG		 224 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
225 if (IS_ERR(rule))
226 goto err_add_rule;
adb4c123 227
aa0cbbae
OG		 228 return rule;
229
230err_add_rule:
d7e75a32
OG		 231 if (flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
232 mlx5_modify_header_dealloc(priv->mdev,
233 attr->mod_hdr_id);
234err_mod_hdr:
aa0cbbae
OG		 235 mlx5_eswitch_del_vlan_action(esw, attr);
236err_add_vlan:
237 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
238 mlx5e_detach_encap(priv, flow);
aa0cbbae
OG		 239 return rule;
240}
d85cdccb
OG		 241
242static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
243 struct mlx5e_tc_flow *flow)
244{
245 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 246 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 247
ecf5bb79 248 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
d85cdccb 249
ecf5bb79 250 mlx5_eswitch_del_vlan_action(esw, flow->esw_attr);
d85cdccb 251
ecf5bb79 252 if (flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
d85cdccb 253 mlx5e_detach_encap(priv, flow);
d7e75a32
OG		 254
255 if (flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
256 mlx5_modify_header_dealloc(priv->mdev,
257 attr->mod_hdr_id);
d85cdccb
OG		 258}
259
260static void mlx5e_detach_encap(struct mlx5e_priv *priv,
261 struct mlx5e_tc_flow *flow)
262{
5067b602
RD		 263 struct list_head *next = flow->encap.next;
264
265 list_del(&flow->encap);
266 if (list_empty(next)) {
267 struct mlx5_encap_entry *e;
268
269 e = list_entry(next, struct mlx5_encap_entry, flows);
270 if (e->n) {
271 mlx5_encap_dealloc(priv->mdev, e->encap_id);
272 neigh_release(e->n);
273 }
274 hlist_del_rcu(&e->encap_hlist);
275 kfree(e);
276 }
277}
278
e8f887ac 279static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 280 struct mlx5e_tc_flow *flow)
e8f887ac 281{
d85cdccb
OG		 282 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
283 mlx5e_tc_del_fdb_flow(priv, flow);
284 else
285 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 286}
287
bbd00f7e
HHZ		 288static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
289 struct tc_cls_flower_offload *f)
290{
291 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
292 outer_headers);
293 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
294 outer_headers);
295 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
296 misc_parameters);
297 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
298 misc_parameters);
299
300 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
301 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
302
303 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
304 struct flow_dissector_key_keyid *key =
305 skb_flow_dissector_target(f->dissector,
306 FLOW_DISSECTOR_KEY_ENC_KEYID,
307 f->key);
308 struct flow_dissector_key_keyid *mask =
309 skb_flow_dissector_target(f->dissector,
310 FLOW_DISSECTOR_KEY_ENC_KEYID,
311 f->mask);
312 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
313 be32_to_cpu(mask->keyid));
314 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
315 be32_to_cpu(key->keyid));
316 }
317}
318
319static int parse_tunnel_attr(struct mlx5e_priv *priv,
320 struct mlx5_flow_spec *spec,
321 struct tc_cls_flower_offload *f)
322{
323 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
324 outer_headers);
325 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
326 outer_headers);
327
2e72eb43
OG		 328 struct flow_dissector_key_control *enc_control =
329 skb_flow_dissector_target(f->dissector,
330 FLOW_DISSECTOR_KEY_ENC_CONTROL,
331 f->key);
332
bbd00f7e
HHZ		 333 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
334 struct flow_dissector_key_ports *key =
335 skb_flow_dissector_target(f->dissector,
336 FLOW_DISSECTOR_KEY_ENC_PORTS,
337 f->key);
338 struct flow_dissector_key_ports *mask =
339 skb_flow_dissector_target(f->dissector,
340 FLOW_DISSECTOR_KEY_ENC_PORTS,
341 f->mask);
1ad9a00a
PB		 342 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
343 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
344 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 345
346 /* Full udp dst port must be given */
347 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 348 goto vxlan_match_offload_err;
bbd00f7e 349
1ad9a00a 350 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 351 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
352 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 353 else {
354 netdev_warn(priv->netdev,
355 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 356 return -EOPNOTSUPP;
2fcd82e9 357 }
bbd00f7e
HHZ		 358
359 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
360 udp_dport, ntohs(mask->dst));
361 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
362 udp_dport, ntohs(key->dst));
363
cd377663
OG		 364 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
365 udp_sport, ntohs(mask->src));
366 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
367 udp_sport, ntohs(key->src));
bbd00f7e 368 } else { /* udp dst port must be given */
2fcd82e9
OG		 369vxlan_match_offload_err:
370 netdev_warn(priv->netdev,
371 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
372 return -EOPNOTSUPP;
bbd00f7e
HHZ		 373 }
374
2e72eb43 375 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 376 struct flow_dissector_key_ipv4_addrs *key =
377 skb_flow_dissector_target(f->dissector,
378 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
379 f->key);
380 struct flow_dissector_key_ipv4_addrs *mask =
381 skb_flow_dissector_target(f->dissector,
382 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
383 f->mask);
384 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
385 src_ipv4_src_ipv6.ipv4_layout.ipv4,
386 ntohl(mask->src));
387 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
388 src_ipv4_src_ipv6.ipv4_layout.ipv4,
389 ntohl(key->src));
390
391 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
392 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
393 ntohl(mask->dst));
394 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
395 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
396 ntohl(key->dst));
bbd00f7e 397
2e72eb43
OG		 398 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
399 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 400 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
401 struct flow_dissector_key_ipv6_addrs *key =
402 skb_flow_dissector_target(f->dissector,
403 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
404 f->key);
405 struct flow_dissector_key_ipv6_addrs *mask =
406 skb_flow_dissector_target(f->dissector,
407 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
408 f->mask);
409
410 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
411 src_ipv4_src_ipv6.ipv6_layout.ipv6),
412 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
413 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
414 src_ipv4_src_ipv6.ipv6_layout.ipv6),
415 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
416
417 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
418 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
419 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
420 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
421 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
422 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
423
424 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
425 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 426 }
bbd00f7e
HHZ		 427
428 /* Enforce DMAC when offloading incoming tunneled flows.
429 * Flow counters require a match on the DMAC.
430 */
431 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
432 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
433 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
434 dmac_47_16), priv->netdev->dev_addr);
435
436 /* let software handle IP fragments */
437 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
438 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
439
440 return 0;
441}
442
de0af0bf
RD		 443static int __parse_cls_flower(struct mlx5e_priv *priv,
444 struct mlx5_flow_spec *spec,
445 struct tc_cls_flower_offload *f,
446 u8 *min_inline)
e3a2b7ed 447{
c5bb1730
MG		 448 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
449 outer_headers);
450 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
451 outer_headers);
e3a2b7ed
AV		 452 u16 addr_type = 0;
453 u8 ip_proto = 0;
454
de0af0bf
RD		 455 *min_inline = MLX5_INLINE_MODE_L2;
456
e3a2b7ed
AV		 457 if (f->dissector->used_keys &
458 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
459 BIT(FLOW_DISSECTOR_KEY_BASIC) |
460 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 461 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 462 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
463 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 464 BIT(FLOW_DISSECTOR_KEY_PORTS) |
465 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
466 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
467 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
468 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
469 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL))) {
e3a2b7ed
AV		 470 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
471 f->dissector->used_keys);
472 return -EOPNOTSUPP;
473 }
474
bbd00f7e
HHZ		 475 if ((dissector_uses_key(f->dissector,
476 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
477 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
478 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
479 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
480 struct flow_dissector_key_control *key =
481 skb_flow_dissector_target(f->dissector,
482 FLOW_DISSECTOR_KEY_ENC_CONTROL,
483 f->key);
484 switch (key->addr_type) {
485 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 486 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 487 if (parse_tunnel_attr(priv, spec, f))
488 return -EOPNOTSUPP;
489 break;
490 default:
491 return -EOPNOTSUPP;
492 }
493
494 /* In decap flow, header pointers should point to the inner
495 * headers, outer header were already set by parse_tunnel_attr
496 */
497 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
498 inner_headers);
499 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
500 inner_headers);
501 }
502
e3a2b7ed
AV		 503 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
504 struct flow_dissector_key_control *key =
505 skb_flow_dissector_target(f->dissector,
1dbd0d37 506 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 507 f->key);
3f7d0eb4
OG		 508
509 struct flow_dissector_key_control *mask =
510 skb_flow_dissector_target(f->dissector,
511 FLOW_DISSECTOR_KEY_CONTROL,
512 f->mask);
e3a2b7ed 513 addr_type = key->addr_type;
3f7d0eb4
OG		 514
515 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
516 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
517 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
518 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG		 519
520 /* the HW doesn't need L3 inline to match on frag=no */
521 if (key->flags & FLOW_DIS_IS_FRAGMENT)
522 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 523 }
e3a2b7ed
AV		 524 }
525
526 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
527 struct flow_dissector_key_basic *key =
528 skb_flow_dissector_target(f->dissector,
529 FLOW_DISSECTOR_KEY_BASIC,
530 f->key);
531 struct flow_dissector_key_basic *mask =
532 skb_flow_dissector_target(f->dissector,
533 FLOW_DISSECTOR_KEY_BASIC,
534 f->mask);
535 ip_proto = key->ip_proto;
536
537 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
538 ntohs(mask->n_proto));
539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
540 ntohs(key->n_proto));
541
542 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
543 mask->ip_proto);
544 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
545 key->ip_proto);
de0af0bf
RD		 546
547 if (mask->ip_proto)
548 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 549 }
550
551 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
552 struct flow_dissector_key_eth_addrs *key =
553 skb_flow_dissector_target(f->dissector,
554 FLOW_DISSECTOR_KEY_ETH_ADDRS,
555 f->key);
556 struct flow_dissector_key_eth_addrs *mask =
557 skb_flow_dissector_target(f->dissector,
558 FLOW_DISSECTOR_KEY_ETH_ADDRS,
559 f->mask);
560
561 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
562 dmac_47_16),
563 mask->dst);
564 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
565 dmac_47_16),
566 key->dst);
567
568 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
569 smac_47_16),
570 mask->src);
571 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
572 smac_47_16),
573 key->src);
574 }
575
095b6cfd
OG		 576 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
577 struct flow_dissector_key_vlan *key =
578 skb_flow_dissector_target(f->dissector,
579 FLOW_DISSECTOR_KEY_VLAN,
580 f->key);
581 struct flow_dissector_key_vlan *mask =
582 skb_flow_dissector_target(f->dissector,
583 FLOW_DISSECTOR_KEY_VLAN,
584 f->mask);
358d79a4 585 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 586 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
587 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 588
589 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
590 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 591
592 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG		 594 }
595 }
596
e3a2b7ed
AV		 597 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
598 struct flow_dissector_key_ipv4_addrs *key =
599 skb_flow_dissector_target(f->dissector,
600 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
601 f->key);
602 struct flow_dissector_key_ipv4_addrs *mask =
603 skb_flow_dissector_target(f->dissector,
604 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
605 f->mask);
606
607 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
608 src_ipv4_src_ipv6.ipv4_layout.ipv4),
609 &mask->src, sizeof(mask->src));
610 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
611 src_ipv4_src_ipv6.ipv4_layout.ipv4),
612 &key->src, sizeof(key->src));
613 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
614 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
615 &mask->dst, sizeof(mask->dst));
616 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
617 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
618 &key->dst, sizeof(key->dst));
de0af0bf
RD		 619
620 if (mask->src || mask->dst)
621 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 622 }
623
624 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
625 struct flow_dissector_key_ipv6_addrs *key =
626 skb_flow_dissector_target(f->dissector,
627 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
628 f->key);
629 struct flow_dissector_key_ipv6_addrs *mask =
630 skb_flow_dissector_target(f->dissector,
631 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
632 f->mask);
633
634 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
635 src_ipv4_src_ipv6.ipv6_layout.ipv6),
636 &mask->src, sizeof(mask->src));
637 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
638 src_ipv4_src_ipv6.ipv6_layout.ipv6),
639 &key->src, sizeof(key->src));
640
641 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
642 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
643 &mask->dst, sizeof(mask->dst));
644 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
645 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
646 &key->dst, sizeof(key->dst));
de0af0bf
RD		 647
648 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
649 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
650 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 651 }
652
653 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
654 struct flow_dissector_key_ports *key =
655 skb_flow_dissector_target(f->dissector,
656 FLOW_DISSECTOR_KEY_PORTS,
657 f->key);
658 struct flow_dissector_key_ports *mask =
659 skb_flow_dissector_target(f->dissector,
660 FLOW_DISSECTOR_KEY_PORTS,
661 f->mask);
662 switch (ip_proto) {
663 case IPPROTO_TCP:
664 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
665 tcp_sport, ntohs(mask->src));
666 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
667 tcp_sport, ntohs(key->src));
668
669 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
670 tcp_dport, ntohs(mask->dst));
671 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
672 tcp_dport, ntohs(key->dst));
673 break;
674
675 case IPPROTO_UDP:
676 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
677 udp_sport, ntohs(mask->src));
678 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
679 udp_sport, ntohs(key->src));
680
681 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
682 udp_dport, ntohs(mask->dst));
683 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
684 udp_dport, ntohs(key->dst));
685 break;
686 default:
687 netdev_err(priv->netdev,
688 "Only UDP and TCP transport are supported\n");
689 return -EINVAL;
690 }
de0af0bf
RD		 691
692 if (mask->src || mask->dst)
693 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV		 694 }
695
696 return 0;
697}
698
de0af0bf 699static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 700 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 701 struct mlx5_flow_spec *spec,
702 struct tc_cls_flower_offload *f)
703{
704 struct mlx5_core_dev *dev = priv->mdev;
705 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 706 struct mlx5e_rep_priv *rpriv = priv->ppriv;
707 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 708 u8 min_inline;
709 int err;
710
711 err = __parse_cls_flower(priv, spec, f, &min_inline);
712
1d447a39
SM		 713 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
714 rep = rpriv->rep;
715 if (rep->vport != FDB_UPLINK_VPORT &&
716 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
717 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD		 718 netdev_warn(priv->netdev,
719 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
720 min_inline, esw->offloads.inline_mode);
721 return -EOPNOTSUPP;
722 }
723 }
724
725 return err;
726}
727
d79b6df6
OG		 728struct pedit_headers {
729 struct ethhdr eth;
730 struct iphdr ip4;
731 struct ipv6hdr ip6;
732 struct tcphdr tcp;
733 struct udphdr udp;
734};
735
736static int pedit_header_offsets[] = {
737 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
738 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
739 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
740 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
741 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
742};
743
744#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
745
746static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
747 struct pedit_headers *masks,
748 struct pedit_headers *vals)
749{
750 u32 *curr_pmask, *curr_pval;
751
752 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
753 goto out_err;
754
755 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
756 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
757
758 if (*curr_pmask & mask) /* disallow acting twice on the same location */
759 goto out_err;
760
761 *curr_pmask |= mask;
762 *curr_pval |= (val & mask);
763
764 return 0;
765
766out_err:
767 return -EOPNOTSUPP;
768}
769
770struct mlx5_fields {
771 u8 field;
772 u8 size;
773 u32 offset;
774};
775
776static struct mlx5_fields fields[] = {
777 {MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_dest[0])},
778 {MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_dest[4])},
779 {MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_source[0])},
780 {MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_source[4])},
781 {MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE, 2, offsetof(struct pedit_headers, eth.h_proto)},
782
783 {MLX5_ACTION_IN_FIELD_OUT_IP_DSCP, 1, offsetof(struct pedit_headers, ip4.tos)},
784 {MLX5_ACTION_IN_FIELD_OUT_IP_TTL, 1, offsetof(struct pedit_headers, ip4.ttl)},
785 {MLX5_ACTION_IN_FIELD_OUT_SIPV4, 4, offsetof(struct pedit_headers, ip4.saddr)},
786 {MLX5_ACTION_IN_FIELD_OUT_DIPV4, 4, offsetof(struct pedit_headers, ip4.daddr)},
787
788 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[0])},
789 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[1])},
790 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[2])},
791 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[3])},
792 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[0])},
793 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[1])},
794 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[2])},
795 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[3])},
796
797 {MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT, 2, offsetof(struct pedit_headers, tcp.source)},
798 {MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT, 2, offsetof(struct pedit_headers, tcp.dest)},
799 {MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS, 1, offsetof(struct pedit_headers, tcp.ack_seq) + 5},
800
801 {MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT, 2, offsetof(struct pedit_headers, udp.source)},
802 {MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT, 2, offsetof(struct pedit_headers, udp.dest)},
803};
804
805/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
806 * max from the SW pedit action. On success, it says how many HW actions were
807 * actually parsed.
808 */
809static int offload_pedit_fields(struct pedit_headers *masks,
810 struct pedit_headers *vals,
811 struct mlx5e_tc_flow_parse_attr *parse_attr)
812{
813 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
814 int i, action_size, nactions, max_actions, first, last;
815 void *s_masks_p, *a_masks_p, *vals_p;
816 u32 s_mask, a_mask, val;
817 struct mlx5_fields *f;
818 u8 cmd, field_bsize;
819 unsigned long mask;
820 void *action;
821
822 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
823 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
824 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
825 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
826
827 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
828 action = parse_attr->mod_hdr_actions;
829 max_actions = parse_attr->num_mod_hdr_actions;
830 nactions = 0;
831
832 for (i = 0; i < ARRAY_SIZE(fields); i++) {
833 f = &fields[i];
834 /* avoid seeing bits set from previous iterations */
835 s_mask = a_mask = mask = val = 0;
836
837 s_masks_p = (void *)set_masks + f->offset;
838 a_masks_p = (void *)add_masks + f->offset;
839
840 memcpy(&s_mask, s_masks_p, f->size);
841 memcpy(&a_mask, a_masks_p, f->size);
842
843 if (!s_mask && !a_mask) /* nothing to offload here */
844 continue;
845
846 if (s_mask && a_mask) {
847 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
848 return -EOPNOTSUPP;
849 }
850
851 if (nactions == max_actions) {
852 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
853 return -EOPNOTSUPP;
854 }
855
856 if (s_mask) {
857 cmd = MLX5_ACTION_TYPE_SET;
858 mask = s_mask;
859 vals_p = (void *)set_vals + f->offset;
860 /* clear to denote we consumed this field */
861 memset(s_masks_p, 0, f->size);
862 } else {
863 cmd = MLX5_ACTION_TYPE_ADD;
864 mask = a_mask;
865 vals_p = (void *)add_vals + f->offset;
866 /* clear to denote we consumed this field */
867 memset(a_masks_p, 0, f->size);
868 }
869
870 memcpy(&val, vals_p, f->size);
871
872 field_bsize = f->size * BITS_PER_BYTE;
873 first = find_first_bit(&mask, field_bsize);
874 last = find_last_bit(&mask, field_bsize);
875 if (first > 0 || last != (field_bsize - 1)) {
876 printk(KERN_WARNING "mlx5: partial rewrite (mask %lx) is currently not offloaded\n",
877 mask);
878 return -EOPNOTSUPP;
879 }
880
881 MLX5_SET(set_action_in, action, action_type, cmd);
882 MLX5_SET(set_action_in, action, field, f->field);
883
884 if (cmd == MLX5_ACTION_TYPE_SET) {
885 MLX5_SET(set_action_in, action, offset, 0);
886 /* length is num of bits to be written, zero means length of 32 */
887 MLX5_SET(set_action_in, action, length, field_bsize);
888 }
889
890 if (field_bsize == 32)
891 MLX5_SET(set_action_in, action, data, ntohl(val));
892 else if (field_bsize == 16)
893 MLX5_SET(set_action_in, action, data, ntohs(val));
894 else if (field_bsize == 8)
895 MLX5_SET(set_action_in, action, data, val);
896
897 action += action_size;
898 nactions++;
899 }
900
901 parse_attr->num_mod_hdr_actions = nactions;
902 return 0;
903}
904
905static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
906 const struct tc_action *a, int namespace,
907 struct mlx5e_tc_flow_parse_attr *parse_attr)
908{
909 int nkeys, action_size, max_actions;
910
911 nkeys = tcf_pedit_nkeys(a);
912 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
913
914 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
915 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
916 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
917 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
918
919 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
920 max_actions = min(max_actions, nkeys * 16);
921
922 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
923 if (!parse_attr->mod_hdr_actions)
924 return -ENOMEM;
925
926 parse_attr->num_mod_hdr_actions = max_actions;
927 return 0;
928}
929
930static const struct pedit_headers zero_masks = {};
931
932static int parse_tc_pedit_action(struct mlx5e_priv *priv,
933 const struct tc_action *a, int namespace,
934 struct mlx5e_tc_flow_parse_attr *parse_attr)
935{
936 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
937 int nkeys, i, err = -EOPNOTSUPP;
938 u32 mask, val, offset;
939 u8 cmd, htype;
940
941 nkeys = tcf_pedit_nkeys(a);
942
943 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
944 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
945
946 for (i = 0; i < nkeys; i++) {
947 htype = tcf_pedit_htype(a, i);
948 cmd = tcf_pedit_cmd(a, i);
949 err = -EOPNOTSUPP; /* can't be all optimistic */
950
951 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
952 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
953 goto out_err;
954 }
955
956 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
957 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
958 goto out_err;
959 }
960
961 mask = tcf_pedit_mask(a, i);
962 val = tcf_pedit_val(a, i);
963 offset = tcf_pedit_offset(a, i);
964
965 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
966 if (err)
967 goto out_err;
968 }
969
970 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
971 if (err)
972 goto out_err;
973
974 err = offload_pedit_fields(masks, vals, parse_attr);
975 if (err < 0)
976 goto out_dealloc_parsed_actions;
977
978 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
979 cmd_masks = &masks[cmd];
980 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
981 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
982 cmd);
983 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
984 16, 1, cmd_masks, sizeof(zero_masks), true);
985 err = -EOPNOTSUPP;
986 goto out_dealloc_parsed_actions;
987 }
988 }
989
990 return 0;
991
992out_dealloc_parsed_actions:
993 kfree(parse_attr->mod_hdr_actions);
994out_err:
995 return err;
996}
997
5c40348c 998static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 999 struct mlx5e_tc_flow_parse_attr *parse_attr,
1000 struct mlx5e_tc_flow *flow)
e3a2b7ed 1001{
aa0cbbae 1002 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1003 const struct tc_action *a;
22dc13c8 1004 LIST_HEAD(actions);
2f4fe4ca 1005 int err;
e3a2b7ed
AV		 1006
1007 if (tc_no_actions(exts))
1008 return -EINVAL;
1009
3bc4b7bf
OG		 1010 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1011 attr->action = 0;
e3a2b7ed 1012
22dc13c8
WC		 1013 tcf_exts_to_list(exts, &actions);
1014 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1015 /* Only support a single action per rule */
3bc4b7bf 1016 if (attr->action)
e3a2b7ed
AV		 1017 return -EINVAL;
1018
1019 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1020 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1021 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1022 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1023 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1024 continue;
1025 }
1026
2f4fe4ca
OG		 1027 if (is_tcf_pedit(a)) {
1028 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1029 parse_attr);
1030 if (err)
1031 return err;
1032
1033 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1034 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1035 continue;
1036 }
1037
e3a2b7ed
AV		 1038 if (is_tcf_skbedit_mark(a)) {
1039 u32 mark = tcf_skbedit_mark(a);
1040
1041 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1042 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1043 mark);
1044 return -EINVAL;
1045 }
1046
3bc4b7bf
OG		 1047 attr->flow_tag = mark;
1048 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 1049 continue;
1050 }
1051
1052 return -EINVAL;
1053 }
1054
1055 return 0;
1056}
1057
76f7444d
OG		 1058static inline int cmp_encap_info(struct ip_tunnel_key *a,
1059 struct ip_tunnel_key *b)
a54e20b4
HHZ		 1060{
1061 return memcmp(a, b, sizeof(*a));
1062}
1063
76f7444d 1064static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1065{
76f7444d 1066 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 1067}
1068
1069static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1070 struct net_device *mirred_dev,
1071 struct net_device **out_dev,
1072 struct flowi4 *fl4,
1073 struct neighbour **out_n,
a54e20b4
HHZ		 1074 int *out_ttl)
1075{
3e621b19 1076 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a54e20b4
HHZ		 1077 struct rtable *rt;
1078 struct neighbour *n = NULL;
a54e20b4
HHZ		 1079
1080#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 1081 int ret;
1082
a54e20b4 1083 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 1084 ret = PTR_ERR_OR_ZERO(rt);
1085 if (ret)
1086 return ret;
a54e20b4
HHZ		 1087#else
1088 return -EOPNOTSUPP;
1089#endif
3e621b19
HHZ		 1090 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1091 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
1092 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1093 else
1094 *out_dev = rt->dst.dev;
a54e20b4 1095
75c33da8 1096 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 1097 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1098 ip_rt_put(rt);
1099 if (!n)
1100 return -ENOMEM;
1101
1102 *out_n = n;
a54e20b4
HHZ		 1103 return 0;
1104}
1105
ce99f6b9
OG		 1106static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1107 struct net_device *mirred_dev,
1108 struct net_device **out_dev,
1109 struct flowi6 *fl6,
1110 struct neighbour **out_n,
1111 int *out_ttl)
1112{
1113 struct neighbour *n = NULL;
1114 struct dst_entry *dst;
1115
1116#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
1117 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1118 int ret;
1119
1120 dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
321fa4ff
AB		 1121 ret = dst->error;
1122 if (ret) {
ce99f6b9
OG		 1123 dst_release(dst);
1124 return ret;
1125 }
1126
1127 *out_ttl = ip6_dst_hoplimit(dst);
1128
1129 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1130 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
1131 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1132 else
1133 *out_dev = dst->dev;
1134#else
1135 return -EOPNOTSUPP;
1136#endif
1137
1138 n = dst_neigh_lookup(dst, &fl6->daddr);
1139 dst_release(dst);
1140 if (!n)
1141 return -ENOMEM;
1142
1143 *out_n = n;
1144 return 0;
1145}
1146
32f3671f
OG		 1147static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1148 char buf[], int encap_size,
1149 unsigned char h_dest[ETH_ALEN],
1150 int ttl,
1151 __be32 daddr,
1152 __be32 saddr,
1153 __be16 udp_dst_port,
1154 __be32 vx_vni)
a54e20b4 1155{
a54e20b4
HHZ		 1156 struct ethhdr *eth = (struct ethhdr *)buf;
1157 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1158 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1159 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1160
1161 memset(buf, 0, encap_size);
1162
1163 ether_addr_copy(eth->h_dest, h_dest);
1164 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1165 eth->h_proto = htons(ETH_P_IP);
1166
1167 ip->daddr = daddr;
1168 ip->saddr = saddr;
1169
1170 ip->ttl = ttl;
1171 ip->protocol = IPPROTO_UDP;
1172 ip->version = 0x4;
1173 ip->ihl = 0x5;
1174
1175 udp->dest = udp_dst_port;
1176 vxh->vx_flags = VXLAN_HF_VNI;
1177 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 1178}
1179
225aabaf
OG		 1180static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1181 char buf[], int encap_size,
1182 unsigned char h_dest[ETH_ALEN],
1183 int ttl,
1184 struct in6_addr *daddr,
1185 struct in6_addr *saddr,
1186 __be16 udp_dst_port,
1187 __be32 vx_vni)
ce99f6b9 1188{
ce99f6b9
OG		 1189 struct ethhdr *eth = (struct ethhdr *)buf;
1190 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1191 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1192 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1193
1194 memset(buf, 0, encap_size);
1195
1196 ether_addr_copy(eth->h_dest, h_dest);
1197 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1198 eth->h_proto = htons(ETH_P_IPV6);
1199
1200 ip6_flow_hdr(ip6h, 0, 0);
1201 /* the HW fills up ipv6 payload len */
1202 ip6h->nexthdr = IPPROTO_UDP;
1203 ip6h->hop_limit = ttl;
1204 ip6h->daddr = *daddr;
1205 ip6h->saddr = *saddr;
1206
1207 udp->dest = udp_dst_port;
1208 vxh->vx_flags = VXLAN_HF_VNI;
1209 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 1210}
1211
a54e20b4
HHZ		 1212static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1213 struct net_device *mirred_dev,
1214 struct mlx5_encap_entry *e,
1215 struct net_device **out_dev)
1216{
1217 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1218 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1219 struct ip_tunnel_key *tun_key = &e->tun_info.key;
a42485eb 1220 struct neighbour *n = NULL;
a54e20b4 1221 struct flowi4 fl4 = {};
a54e20b4 1222 char *encap_header;
32f3671f
OG		 1223 int ttl, err;
1224
1225 if (max_encap_size < ipv4_encap_size) {
1226 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1227 ipv4_encap_size, max_encap_size);
1228 return -EOPNOTSUPP;
1229 }
a54e20b4 1230
32f3671f 1231 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 1232 if (!encap_header)
1233 return -ENOMEM;
1234
1235 switch (e->tunnel_type) {
1236 case MLX5_HEADER_TYPE_VXLAN:
1237 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1238 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 1239 break;
1240 default:
1241 err = -EOPNOTSUPP;
1242 goto out;
1243 }
9a941117 1244 fl4.flowi4_tos = tun_key->tos;
76f7444d 1245 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1246 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4
HHZ		 1247
1248 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, out_dev,
9a941117 1249 &fl4, &n, &ttl);
a54e20b4
HHZ		 1250 if (err)
1251 goto out;
1252
a54e20b4 1253 if (!(n->nud_state & NUD_VALID)) {
a42485eb
OG		 1254 pr_warn("%s: can't offload, neighbour to %pI4 invalid\n", __func__, &fl4.daddr);
1255 err = -EOPNOTSUPP;
a54e20b4
HHZ		 1256 goto out;
1257 }
1258
75c33da8
OG		 1259 e->n = n;
1260 e->out_dev = *out_dev;
1261
a54e20b4
HHZ		 1262 neigh_ha_snapshot(e->h_dest, n, *out_dev);
1263
1264 switch (e->tunnel_type) {
1265 case MLX5_HEADER_TYPE_VXLAN:
32f3671f
OG		 1266 gen_vxlan_header_ipv4(*out_dev, encap_header,
1267 ipv4_encap_size, e->h_dest, ttl,
1268 fl4.daddr,
1269 fl4.saddr, tun_key->tp_dst,
1270 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 1271 break;
1272 default:
1273 err = -EOPNOTSUPP;
1274 goto out;
1275 }
1276
1277 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1278 ipv4_encap_size, encap_header, &e->encap_id);
a54e20b4 1279out:
a42485eb
OG		 1280 if (err && n)
1281 neigh_release(n);
a54e20b4
HHZ		 1282 kfree(encap_header);
1283 return err;
1284}
1285
ce99f6b9
OG		 1286static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1287 struct net_device *mirred_dev,
1288 struct mlx5_encap_entry *e,
1289 struct net_device **out_dev)
1290
1291{
1292 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1293 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1294 struct ip_tunnel_key *tun_key = &e->tun_info.key;
ce99f6b9
OG		 1295 struct neighbour *n = NULL;
1296 struct flowi6 fl6 = {};
1297 char *encap_header;
225aabaf 1298 int err, ttl = 0;
ce99f6b9 1299
225aabaf
OG		 1300 if (max_encap_size < ipv6_encap_size) {
1301 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1302 ipv6_encap_size, max_encap_size);
1303 return -EOPNOTSUPP;
1304 }
ce99f6b9 1305
225aabaf 1306 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 1307 if (!encap_header)
1308 return -ENOMEM;
1309
1310 switch (e->tunnel_type) {
1311 case MLX5_HEADER_TYPE_VXLAN:
1312 fl6.flowi6_proto = IPPROTO_UDP;
1313 fl6.fl6_dport = tun_key->tp_dst;
1314 break;
1315 default:
1316 err = -EOPNOTSUPP;
1317 goto out;
1318 }
1319
1320 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1321 fl6.daddr = tun_key->u.ipv6.dst;
1322 fl6.saddr = tun_key->u.ipv6.src;
1323
1324 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, out_dev,
1325 &fl6, &n, &ttl);
1326 if (err)
1327 goto out;
1328
1329 if (!(n->nud_state & NUD_VALID)) {
1330 pr_warn("%s: can't offload, neighbour to %pI6 invalid\n", __func__, &fl6.daddr);
1331 err = -EOPNOTSUPP;
1332 goto out;
1333 }
1334
1335 e->n = n;
1336 e->out_dev = *out_dev;
1337
1338 neigh_ha_snapshot(e->h_dest, n, *out_dev);
1339
1340 switch (e->tunnel_type) {
1341 case MLX5_HEADER_TYPE_VXLAN:
225aabaf
OG		 1342 gen_vxlan_header_ipv6(*out_dev, encap_header,
1343 ipv6_encap_size, e->h_dest, ttl,
1344 &fl6.daddr,
1345 &fl6.saddr, tun_key->tp_dst,
1346 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 1347 break;
1348 default:
1349 err = -EOPNOTSUPP;
1350 goto out;
1351 }
1352
1353 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1354 ipv6_encap_size, encap_header, &e->encap_id);
ce99f6b9
OG		 1355out:
1356 if (err && n)
1357 neigh_release(n);
1358 kfree(encap_header);
1359 return err;
1360}
1361
a54e20b4
HHZ		 1362static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1363 struct ip_tunnel_info *tun_info,
1364 struct net_device *mirred_dev,
1365 struct mlx5_esw_flow_attr *attr)
1366{
1367 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1ad9a00a
PB		 1368 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
1369 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
a54e20b4
HHZ		 1370 unsigned short family = ip_tunnel_info_af(tun_info);
1371 struct ip_tunnel_key *key = &tun_info->key;
a54e20b4
HHZ		 1372 struct mlx5_encap_entry *e;
1373 struct net_device *out_dev;
ce99f6b9 1374 int tunnel_type, err = -EOPNOTSUPP;
a54e20b4
HHZ		 1375 uintptr_t hash_key;
1376 bool found = false;
a54e20b4 1377
2fcd82e9 1378 /* udp dst port must be set */
a54e20b4 1379 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1380 goto vxlan_encap_offload_err;
a54e20b4 1381
cd377663 1382 /* setting udp src port isn't supported */
2fcd82e9
OG		 1383 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1384vxlan_encap_offload_err:
1385 netdev_warn(priv->netdev,
1386 "must set udp dst port and not set udp src port\n");
cd377663 1387 return -EOPNOTSUPP;
2fcd82e9 1388 }
cd377663 1389
1ad9a00a 1390 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1391 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 1392 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1393 } else {
2fcd82e9
OG		 1394 netdev_warn(priv->netdev,
1395 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 1396 return -EOPNOTSUPP;
1397 }
1398
76f7444d 1399 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 1400
1401 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1402 encap_hlist, hash_key) {
76f7444d 1403 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 1404 found = true;
1405 break;
1406 }
1407 }
1408
1409 if (found) {
1410 attr->encap = e;
1411 return 0;
1412 }
1413
1414 e = kzalloc(sizeof(*e), GFP_KERNEL);
1415 if (!e)
1416 return -ENOMEM;
1417
76f7444d 1418 e->tun_info = *tun_info;
a54e20b4
HHZ		 1419 e->tunnel_type = tunnel_type;
1420 INIT_LIST_HEAD(&e->flows);
1421
ce99f6b9
OG		 1422 if (family == AF_INET)
1423 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e, &out_dev);
1424 else if (family == AF_INET6)
1425 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e, &out_dev);
1426
a54e20b4
HHZ		 1427 if (err)
1428 goto out_err;
1429
1430 attr->encap = e;
1431 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1432
1433 return err;
1434
1435out_err:
1436 kfree(e);
1437 return err;
1438}
1439
03a9d11e 1440static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1441 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1442 struct mlx5e_tc_flow *flow)
03a9d11e 1443{
ecf5bb79 1444 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1445 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1446 struct ip_tunnel_info *info = NULL;
03a9d11e 1447 const struct tc_action *a;
22dc13c8 1448 LIST_HEAD(actions);
a54e20b4
HHZ		 1449 bool encap = false;
1450 int err;
03a9d11e
OG		 1451
1452 if (tc_no_actions(exts))
1453 return -EINVAL;
1454
776b12b6 1455 memset(attr, 0, sizeof(*attr));
1d447a39 1456 attr->in_rep = rpriv->rep;
03a9d11e 1457
22dc13c8
WC		 1458 tcf_exts_to_list(exts, &actions);
1459 list_for_each_entry(a, &actions, list) {
03a9d11e 1460 if (is_tcf_gact_shot(a)) {
8b32580d
OG		 1461 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1462 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 1463 continue;
1464 }
1465
d7e75a32
OG		 1466 if (is_tcf_pedit(a)) {
1467 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1468 parse_attr);
1469 if (err)
1470 return err;
1471
1472 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1473 continue;
1474 }
1475
5724b8b5 1476 if (is_tcf_mirred_egress_redirect(a)) {
03a9d11e
OG		 1477 int ifindex = tcf_mirred_ifindex(a);
1478 struct net_device *out_dev;
1479 struct mlx5e_priv *out_priv;
03a9d11e
OG		 1480
1481 out_dev = __dev_get_by_index(dev_net(priv->netdev), ifindex);
1482
a54e20b4
HHZ		 1483 if (switchdev_port_same_parent_id(priv->netdev,
1484 out_dev)) {
1485 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1486 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1487 out_priv = netdev_priv(out_dev);
1d447a39
SM		 1488 rpriv = out_priv->ppriv;
1489 attr->out_rep = rpriv->rep;
a54e20b4
HHZ		 1490 } else if (encap) {
1491 err = mlx5e_attach_encap(priv, info,
1492 out_dev, attr);
1493 if (err)
1494 return err;
1495 list_add(&flow->encap, &attr->encap->flows);
1496 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
1497 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1498 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1499 out_priv = netdev_priv(attr->encap->out_dev);
1d447a39
SM		 1500 rpriv = out_priv->ppriv;
1501 attr->out_rep = rpriv->rep;
a54e20b4 1502 } else {
03a9d11e
OG		 1503 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
1504 priv->netdev->name, out_dev->name);
1505 return -EINVAL;
1506 }
a54e20b4
HHZ		 1507 continue;
1508 }
03a9d11e 1509
a54e20b4
HHZ		 1510 if (is_tcf_tunnel_set(a)) {
1511 info = tcf_tunnel_info(a);
1512 if (info)
1513 encap = true;
1514 else
1515 return -EOPNOTSUPP;
03a9d11e
OG		 1516 continue;
1517 }
1518
8b32580d 1519 if (is_tcf_vlan(a)) {
09c91ddf 1520 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 1521 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 1522 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG		 1523 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1524 return -EOPNOTSUPP;
1525
1526 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1527 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG		 1528 } else { /* action is TCA_VLAN_ACT_MODIFY */
1529 return -EOPNOTSUPP;
8b32580d
OG		 1530 }
1531 continue;
1532 }
1533
bbd00f7e
HHZ		 1534 if (is_tcf_tunnel_release(a)) {
1535 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1536 continue;
1537 }
1538
03a9d11e
OG		 1539 return -EINVAL;
1540 }
1541 return 0;
1542}
1543
e3a2b7ed
AV		 1544int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol,
1545 struct tc_cls_flower_offload *f)
1546{
3bc4b7bf 1547 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 1548 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 1549 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 1550 struct mlx5e_tc_flow *flow;
1551 int attr_size, err = 0;
65ba8fb7 1552 u8 flow_flags = 0;
e3a2b7ed 1553
65ba8fb7
OG		 1554 if (esw && esw->mode == SRIOV_OFFLOADS) {
1555 flow_flags = MLX5E_TC_FLOW_ESWITCH;
1556 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 1557 } else {
1558 flow_flags = MLX5E_TC_FLOW_NIC;
1559 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 1560 }
e3a2b7ed 1561
65ba8fb7 1562 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
17091853
OG		 1563 parse_attr = mlx5_vzalloc(sizeof(*parse_attr));
1564 if (!parse_attr || !flow) {
e3a2b7ed
AV		 1565 err = -ENOMEM;
1566 goto err_free;
1567 }
1568
1569 flow->cookie = f->cookie;
65ba8fb7 1570 flow->flags = flow_flags;
e3a2b7ed 1571
17091853 1572 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 1573 if (err < 0)
1574 goto err_free;
1575
65ba8fb7 1576 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 1577 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 1578 if (err < 0)
1579 goto err_free;
aa0cbbae 1580 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 1581 } else {
aa0cbbae 1582 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 1583 if (err < 0)
1584 goto err_free;
aa0cbbae 1585 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 1586 }
e3a2b7ed 1587
e3a2b7ed
AV		 1588 if (IS_ERR(flow->rule)) {
1589 err = PTR_ERR(flow->rule);
aa0cbbae 1590 goto err_free;
e3a2b7ed
AV		 1591 }
1592
5c40348c
OG		 1593 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1594 tc->ht_params);
1595 if (err)
1596 goto err_del_rule;
1597
e3a2b7ed
AV		 1598 goto out;
1599
5c40348c 1600err_del_rule:
5e86397a 1601 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 1602
1603err_free:
53636068 1604 kfree(flow);
e3a2b7ed 1605out:
17091853 1606 kvfree(parse_attr);
e3a2b7ed
AV		 1607 return err;
1608}
1609
1610int mlx5e_delete_flower(struct mlx5e_priv *priv,
1611 struct tc_cls_flower_offload *f)
1612{
1613 struct mlx5e_tc_flow *flow;
acff797c 1614 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 1615
1616 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
1617 tc->ht_params);
1618 if (!flow)
1619 return -EINVAL;
1620
1621 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
1622
961e8979 1623 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed 1624
a54e20b4 1625
e3a2b7ed
AV		 1626 kfree(flow);
1627
1628 return 0;
1629}
1630
aad7e08d
AV		 1631int mlx5e_stats_flower(struct mlx5e_priv *priv,
1632 struct tc_cls_flower_offload *f)
1633{
1634 struct mlx5e_tc_table *tc = &priv->fs.tc;
1635 struct mlx5e_tc_flow *flow;
1636 struct tc_action *a;
1637 struct mlx5_fc *counter;
22dc13c8 1638 LIST_HEAD(actions);
aad7e08d
AV		 1639 u64 bytes;
1640 u64 packets;
1641 u64 lastuse;
1642
1643 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
1644 tc->ht_params);
1645 if (!flow)
1646 return -EINVAL;
1647
1648 counter = mlx5_flow_rule_counter(flow->rule);
1649 if (!counter)
1650 return 0;
1651
1652 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1653
fed06ee8
OG		 1654 preempt_disable();
1655
22dc13c8
WC		 1656 tcf_exts_to_list(f->exts, &actions);
1657 list_for_each_entry(a, &actions, list)
aad7e08d
AV		 1658 tcf_action_stats_update(a, bytes, packets, lastuse);
1659
fed06ee8
OG		 1660 preempt_enable();
1661
aad7e08d
AV		 1662 return 0;
1663}
1664
e8f887ac
AV		 1665static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
1666 .head_offset = offsetof(struct mlx5e_tc_flow, node),
1667 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
1668 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
1669 .automatic_shrinking = true,
1670};
1671
1672int mlx5e_tc_init(struct mlx5e_priv *priv)
1673{
acff797c 1674 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 1675
1676 tc->ht_params = mlx5e_tc_flow_ht_params;
1677 return rhashtable_init(&tc->ht, &tc->ht_params);
1678}
1679
1680static void _mlx5e_tc_del_flow(void *ptr, void *arg)
1681{
1682 struct mlx5e_tc_flow *flow = ptr;
1683 struct mlx5e_priv *priv = arg;
1684
961e8979 1685 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 1686 kfree(flow);
1687}
1688
1689void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
1690{
acff797c 1691 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 1692
1693 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
1694
acff797c
MG		 1695 if (!IS_ERR_OR_NULL(tc->t)) {
1696 mlx5_destroy_flow_table(tc->t);
1697 tc->t = NULL;
e8f887ac
AV		 1698 }
1699}
ubuntu-bionic-kernel mirror