]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
flow_offload: add support for packet-per-second policing
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
3f6d08d1 60#include "fs_core.h"
2c81bfd5 61#include "en/port.h"
101f4de9 62#include "en/tc_tun.h"
0a7fcb78 63#include "en/mapping.h"
4c3844d9 64#include "en/tc_ct.h"
b2fdf3d0 65#include "en/mod_hdr.h"
0d9f9647
VB		 66#include "en/tc_priv.h"
67#include "en/tc_tun_encap.h"
04de7dda 68#include "lib/devcom.h"
9272e3df 69#include "lib/geneve.h"
ae430332 70#include "lib/fs_chains.h"
7a978759 71#include "diag/en_tc_tracepoint.h"
1fe3e316 72#include <asm/div64.h>
e8f887ac 73
6a064674 74#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 75#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 76
acff797c 77#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 78#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 79
8f1e0b97
PB		 80struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
81 [CHAIN_TO_REG] = {
82 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
83 .moffset = 0,
84 .mlen = 2,
85 },
10742efc
VB		 86 [VPORT_TO_REG] = {
87 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
88 .moffset = 2,
89 .mlen = 2,
90 },
0a7fcb78
PB		 91 [TUNNEL_TO_REG] = {
92 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521 93 .moffset = 1,
48d216e5 94 .mlen = ((ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS) / 8),
0a7fcb78
PB		 95 .soffset = MLX5_BYTE_OFF(fte_match_param,
96 misc_parameters_2.metadata_reg_c_1),
97 },
4c3844d9 98 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 99 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 100 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
101 [MARK_TO_REG] = mark_to_reg_ct,
102 [LABELS_TO_REG] = labels_to_reg_ct,
103 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 104 /* For NIC rules we store the retore metadata directly
105 * into reg_b that is passed to SW since we don't
106 * jump between steering domains.
107 */
108 [NIC_CHAIN_TO_REG] = {
109 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
110 .moffset = 0,
111 .mlen = 2,
112 },
aedd133d 113 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 114};
115
9ba33339
RD		 116/* To avoid false lock dependency warning set the tc_ht lock
117 * class different than the lock class of the ht being used when deleting
118 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
119 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
120 * it's different than the ht->mutex here.
121 */
122static struct lock_class_key tc_ht_lock_key;
123
0a7fcb78
PB		 124static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
125
126void
127mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
128 enum mlx5e_tc_attr_to_reg type,
129 u32 data,
130 u32 mask)
131{
132 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
133 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
134 void *headers_c = spec->match_criteria;
135 void *headers_v = spec->match_value;
136 void *fmask, *fval;
137
138 fmask = headers_c + soffset;
139 fval = headers_v + soffset;
140
58ff18e1
SM		 141 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
142 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 143
144 memcpy(fmask, &mask, match_len);
145 memcpy(fval, &data, match_len);
146
147 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
148}
149
7e36feeb
PB		 150void
151mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
152 enum mlx5e_tc_attr_to_reg type,
153 u32 *data,
154 u32 *mask)
155{
156 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
157 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
158 void *headers_c = spec->match_criteria;
159 void *headers_v = spec->match_value;
160 void *fmask, *fval;
161
162 fmask = headers_c + soffset;
163 fval = headers_v + soffset;
164
165 memcpy(mask, fmask, match_len);
166 memcpy(data, fval, match_len);
167
168 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
169 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
170}
171
0a7fcb78 172int
c7b9038d
VB		 173mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
174 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
175 enum mlx5_flow_namespace_type ns,
176 enum mlx5e_tc_attr_to_reg type,
177 u32 data)
0a7fcb78
PB		 178{
179 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
180 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
181 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
182 char *modact;
183 int err;
184
aedd133d 185 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 186 if (err)
187 return err;
188
189 modact = mod_hdr_acts->actions +
190 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
191
192 /* Firmware has 5bit length field and 0 means 32bits */
193 if (mlen == 4)
194 mlen = 0;
195
196 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
197 MLX5_SET(set_action_in, modact, field, mfield);
198 MLX5_SET(set_action_in, modact, offset, moffset * 8);
199 MLX5_SET(set_action_in, modact, length, mlen * 8);
200 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 201 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 202 mod_hdr_acts->num_actions++;
203
c7b9038d 204 return err;
0a7fcb78
PB		 205}
206
aedd133d
AL		 207static struct mlx5_tc_ct_priv *
208get_ct_priv(struct mlx5e_priv *priv)
209{
210 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
211 struct mlx5_rep_uplink_priv *uplink_priv;
212 struct mlx5e_rep_priv *uplink_rpriv;
213
e8711402 214 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 215 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
216 uplink_priv = &uplink_rpriv->uplink_priv;
217
218 return uplink_priv->ct_priv;
219 }
220
221 return priv->fs.tc.ct;
222}
223
224struct mlx5_flow_handle *
225mlx5_tc_rule_insert(struct mlx5e_priv *priv,
226 struct mlx5_flow_spec *spec,
227 struct mlx5_flow_attr *attr)
228{
229 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
230
e8711402 231 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 232 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
233
234 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
235}
236
237void
238mlx5_tc_rule_delete(struct mlx5e_priv *priv,
239 struct mlx5_flow_handle *rule,
240 struct mlx5_flow_attr *attr)
241{
242 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
243
e8711402 244 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 245 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
246
247 return;
248 }
249
250 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
251}
252
c7b9038d
VB		 253int
254mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
255 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
256 enum mlx5_flow_namespace_type ns,
257 enum mlx5e_tc_attr_to_reg type,
258 u32 data)
259{
260 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
261
262 return ret < 0 ? ret : 0;
263}
264
265void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
266 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
267 enum mlx5e_tc_attr_to_reg type,
268 int act_id, u32 data)
269{
270 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
271 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
272 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
273 char *modact;
274
275 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
276
277 /* Firmware has 5bit length field and 0 means 32bits */
278 if (mlen == 4)
279 mlen = 0;
280
281 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
282 MLX5_SET(set_action_in, modact, field, mfield);
283 MLX5_SET(set_action_in, modact, offset, moffset * 8);
284 MLX5_SET(set_action_in, modact, length, mlen * 8);
285 MLX5_SET(set_action_in, modact, data, data);
286}
287
77ab67b7
OG		 288struct mlx5e_hairpin {
289 struct mlx5_hairpin *pair;
290
291 struct mlx5_core_dev *func_mdev;
3f6d08d1 292 struct mlx5e_priv *func_priv;
77ab67b7
OG		 293 u32 tdn;
294 u32 tirn;
3f6d08d1
OG		 295
296 int num_channels;
297 struct mlx5e_rqt indir_rqt;
298 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
299 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 300};
301
5c65c564
OG		 302struct mlx5e_hairpin_entry {
303 /* a node of a hash table which keeps all the hairpin entries */
304 struct hlist_node hairpin_hlist;
305
73edca73
VB		 306 /* protects flows list */
307 spinlock_t flows_lock;
5c65c564
OG		 308 /* flows sharing the same hairpin */
309 struct list_head flows;
db76ca24
VB		 310 /* hpe's that were not fully initialized when dead peer update event
311 * function traversed them.
312 */
313 struct list_head dead_peer_wait_list;
5c65c564 314
d8822868 315 u16 peer_vhca_id;
106be53b 316 u8 prio;
5c65c564 317 struct mlx5e_hairpin *hp;
e4f9abbd 318 refcount_t refcnt;
db76ca24 319 struct completion res_ready;
5c65c564
OG		 320};
321
5a7e5bcb
VB		 322static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
323 struct mlx5e_tc_flow *flow);
324
0d9f9647 325struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 326{
327 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
328 return ERR_PTR(-EINVAL);
329 return flow;
330}
331
0d9f9647 332void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 333{
334 if (refcount_dec_and_test(&flow->refcnt)) {
335 mlx5e_tc_del_flow(priv, flow);
c5d326b2 336 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 337 }
338}
339
aedd133d 340bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 341{
342 return flow_flag_test(flow, ESWITCH);
343}
344
84179981
PB		 345static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
346{
347 return flow_flag_test(flow, FT);
348}
349
0d9f9647 350bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 351{
352 return flow_flag_test(flow, OFFLOADED);
353}
354
b2fdf3d0 355static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 356{
b2fdf3d0
PB		 357 return mlx5e_is_eswitch_flow(flow) ?
358 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 359}
360
dd58edc3 361static struct mod_hdr_tbl *
b2fdf3d0 362get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 363{
364 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
365
b2fdf3d0
PB		 366 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
367 &esw->offloads.mod_hdr :
dd58edc3
VB		 368 &priv->fs.tc.mod_hdr;
369}
370
11c9c548
OG		 371static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
372 struct mlx5e_tc_flow *flow,
373 struct mlx5e_tc_flow_parse_attr *parse_attr)
374{
b2fdf3d0
PB		 375 struct mlx5_modify_hdr *modify_hdr;
376 struct mlx5e_mod_hdr_handle *mh;
11c9c548 377
b2fdf3d0
PB		 378 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
379 get_flow_name_space(flow),
380 &parse_attr->mod_hdr_acts);
381 if (IS_ERR(mh))
382 return PTR_ERR(mh);
11c9c548 383
b2fdf3d0 384 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 385 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 386 flow->mh = mh;
11c9c548
OG		 387
388 return 0;
11c9c548
OG		 389}
390
391static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
392 struct mlx5e_tc_flow *flow)
393{
5a7e5bcb 394 /* flow wasn't fully initialized */
dd58edc3 395 if (!flow->mh)
5a7e5bcb
VB		 396 return;
397
b2fdf3d0
PB		 398 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
399 flow->mh);
dd58edc3 400 flow->mh = NULL;
11c9c548
OG		 401}
402
77ab67b7
OG		 403static
404struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
405{
406 struct net_device *netdev;
407 struct mlx5e_priv *priv;
408
409 netdev = __dev_get_by_index(net, ifindex);
410 priv = netdev_priv(netdev);
411 return priv->mdev;
412}
413
414static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
415{
e0b4b472 416 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 417 void *tirc;
418 int err;
419
420 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
421 if (err)
422 goto alloc_tdn_err;
423
424 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
425
426 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 427 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 428 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
429
e0b4b472 430 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 431 if (err)
432 goto create_tir_err;
433
434 return 0;
435
436create_tir_err:
437 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
438alloc_tdn_err:
439 return err;
440}
441
442static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
443{
444 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
445 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
446}
447
2119bda6 448static int mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
3f6d08d1 449{
2119bda6 450 u32 *indirection_rqt, rqn;
3f6d08d1
OG		 451 struct mlx5e_priv *priv = hp->func_priv;
452 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
453
2119bda6
AB		 454 indirection_rqt = kzalloc(sz, GFP_KERNEL);
455 if (!indirection_rqt)
456 return -ENOMEM;
457
3f6d08d1
OG		 458 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
459 hp->num_channels);
460
461 for (i = 0; i < sz; i++) {
462 ix = i;
bbeb53b8 463 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 464 ix = mlx5e_bits_invert(i, ilog2(sz));
465 ix = indirection_rqt[ix];
466 rqn = hp->pair->rqn[ix];
467 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
468 }
2119bda6
AB		 469
470 kfree(indirection_rqt);
471 return 0;
3f6d08d1
OG		 472}
473
474static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
475{
476 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
477 struct mlx5e_priv *priv = hp->func_priv;
478 struct mlx5_core_dev *mdev = priv->mdev;
479 void *rqtc;
480 u32 *in;
481
482 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
483 in = kvzalloc(inlen, GFP_KERNEL);
484 if (!in)
485 return -ENOMEM;
486
487 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
488
489 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
490 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
491
2119bda6
AB		 492 err = mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
493 if (err)
494 goto out;
3f6d08d1
OG		 495
496 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
497 if (!err)
498 hp->indir_rqt.enabled = true;
499
2119bda6 500out:
3f6d08d1
OG		 501 kvfree(in);
502 return err;
503}
504
505static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
506{
507 struct mlx5e_priv *priv = hp->func_priv;
508 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
509 int tt, i, err;
510 void *tirc;
511
512 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 513 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
514
3f6d08d1
OG		 515 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
516 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
517
518 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
519 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
520 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 521 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
522
3f6d08d1 523 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 524 &hp->indir_tirn[tt]);
3f6d08d1
OG		 525 if (err) {
526 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
527 goto err_destroy_tirs;
528 }
529 }
530 return 0;
531
532err_destroy_tirs:
533 for (i = 0; i < tt; i++)
534 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
535 return err;
536}
537
538static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
539{
540 int tt;
541
542 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
543 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
544}
545
546static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
547 struct ttc_params *ttc_params)
548{
549 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
550 int tt;
551
552 memset(ttc_params, 0, sizeof(*ttc_params));
553
554 ttc_params->any_tt_tirn = hp->tirn;
555
556 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
557 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
558
6412bb39 559 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 560 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
561 ft_attr->prio = MLX5E_TC_PRIO;
562}
563
564static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
565{
566 struct mlx5e_priv *priv = hp->func_priv;
567 struct ttc_params ttc_params;
568 int err;
569
570 err = mlx5e_hairpin_create_indirect_rqt(hp);
571 if (err)
572 return err;
573
574 err = mlx5e_hairpin_create_indirect_tirs(hp);
575 if (err)
576 goto err_create_indirect_tirs;
577
578 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
579 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
580 if (err)
581 goto err_create_ttc_table;
582
583 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
584 hp->num_channels, hp->ttc.ft.t->id);
585
586 return 0;
587
588err_create_ttc_table:
589 mlx5e_hairpin_destroy_indirect_tirs(hp);
590err_create_indirect_tirs:
591 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
592
593 return err;
594}
595
596static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
597{
598 struct mlx5e_priv *priv = hp->func_priv;
599
600 mlx5e_destroy_ttc_table(priv, &hp->ttc);
601 mlx5e_hairpin_destroy_indirect_tirs(hp);
602 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
603}
604
77ab67b7
OG		 605static struct mlx5e_hairpin *
606mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
607 int peer_ifindex)
608{
609 struct mlx5_core_dev *func_mdev, *peer_mdev;
610 struct mlx5e_hairpin *hp;
611 struct mlx5_hairpin *pair;
612 int err;
613
614 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
615 if (!hp)
616 return ERR_PTR(-ENOMEM);
617
618 func_mdev = priv->mdev;
619 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
620
621 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
622 if (IS_ERR(pair)) {
623 err = PTR_ERR(pair);
624 goto create_pair_err;
625 }
626 hp->pair = pair;
627 hp->func_mdev = func_mdev;
3f6d08d1
OG		 628 hp->func_priv = priv;
629 hp->num_channels = params->num_channels;
77ab67b7
OG		 630
631 err = mlx5e_hairpin_create_transport(hp);
632 if (err)
633 goto create_transport_err;
634
3f6d08d1
OG		 635 if (hp->num_channels > 1) {
636 err = mlx5e_hairpin_rss_init(hp);
637 if (err)
638 goto rss_init_err;
639 }
640
77ab67b7
OG		 641 return hp;
642
3f6d08d1
OG		 643rss_init_err:
644 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 645create_transport_err:
646 mlx5_core_hairpin_destroy(hp->pair);
647create_pair_err:
648 kfree(hp);
649 return ERR_PTR(err);
650}
651
652static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
653{
3f6d08d1
OG		 654 if (hp->num_channels > 1)
655 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 656 mlx5e_hairpin_destroy_transport(hp);
657 mlx5_core_hairpin_destroy(hp->pair);
658 kvfree(hp);
659}
660
106be53b
OG		 661static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
662{
663 return (peer_vhca_id << 16 | prio);
664}
665
5c65c564 666static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 667 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 668{
669 struct mlx5e_hairpin_entry *hpe;
106be53b 670 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 671
672 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 673 hairpin_hlist, hash_key) {
e4f9abbd
VB		 674 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
675 refcount_inc(&hpe->refcnt);
5c65c564 676 return hpe;
e4f9abbd 677 }
5c65c564
OG		 678 }
679
680 return NULL;
681}
682
e4f9abbd
VB		 683static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
684 struct mlx5e_hairpin_entry *hpe)
685{
686 /* no more hairpin flows for us, release the hairpin pair */
b32accda 687 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 688 return;
b32accda
VB		 689 hash_del(&hpe->hairpin_hlist);
690 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 691
db76ca24
VB		 692 if (!IS_ERR_OR_NULL(hpe->hp)) {
693 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
694 dev_name(hpe->hp->pair->peer_mdev->device));
695
696 mlx5e_hairpin_destroy(hpe->hp);
697 }
e4f9abbd
VB		 698
699 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 700 kfree(hpe);
701}
702
106be53b
OG		 703#define UNKNOWN_MATCH_PRIO 8
704
705static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 706 struct mlx5_flow_spec *spec, u8 *match_prio,
707 struct netlink_ext_ack *extack)
106be53b
OG		 708{
709 void *headers_c, *headers_v;
710 u8 prio_val, prio_mask = 0;
711 bool vlan_present;
712
713#ifdef CONFIG_MLX5_CORE_EN_DCB
714 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 715 NL_SET_ERR_MSG_MOD(extack,
716 "only PCP trust state supported for hairpin");
106be53b
OG		 717 return -EOPNOTSUPP;
718 }
719#endif
720 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
721 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
722
723 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
724 if (vlan_present) {
725 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
726 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
727 }
728
729 if (!vlan_present || !prio_mask) {
730 prio_val = UNKNOWN_MATCH_PRIO;
731 } else if (prio_mask != 0x7) {
e98bedf5
EB		 732 NL_SET_ERR_MSG_MOD(extack,
733 "masked priority match not supported for hairpin");
106be53b
OG		 734 return -EOPNOTSUPP;
735 }
736
737 *match_prio = prio_val;
738 return 0;
739}
740
5c65c564
OG		 741static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
742 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 743 struct mlx5e_tc_flow_parse_attr *parse_attr,
744 struct netlink_ext_ack *extack)
5c65c564 745{
98b66cb1 746 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 747 struct mlx5_hairpin_params params;
d8822868 748 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 749 struct mlx5e_hairpin_entry *hpe;
750 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 751 u64 link_speed64;
752 u32 link_speed;
106be53b 753 u8 match_prio;
d8822868 754 u16 peer_id;
5c65c564
OG		 755 int err;
756
d8822868
OG		 757 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
758 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 759 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 760 return -EOPNOTSUPP;
761 }
762
d8822868 763 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 764 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
765 extack);
106be53b
OG		 766 if (err)
767 return err;
b32accda
VB		 768
769 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 770 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 771 if (hpe) {
772 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
773 wait_for_completion(&hpe->res_ready);
774
775 if (IS_ERR(hpe->hp)) {
776 err = -EREMOTEIO;
777 goto out_err;
778 }
5c65c564 779 goto attach_flow;
db76ca24 780 }
5c65c564
OG		 781
782 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 783 if (!hpe) {
db76ca24
VB		 784 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
785 return -ENOMEM;
b32accda 786 }
5c65c564 787
73edca73 788 spin_lock_init(&hpe->flows_lock);
5c65c564 789 INIT_LIST_HEAD(&hpe->flows);
db76ca24 790 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 791 hpe->peer_vhca_id = peer_id;
106be53b 792 hpe->prio = match_prio;
e4f9abbd 793 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 794 init_completion(&hpe->res_ready);
795
796 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
797 hash_hairpin_info(peer_id, match_prio));
798 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 799
800 params.log_data_size = 15;
801 params.log_data_size = min_t(u8, params.log_data_size,
802 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
803 params.log_data_size = max_t(u8, params.log_data_size,
804 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 805
eb9180f7
OG		 806 params.log_num_packets = params.log_data_size -
807 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
808 params.log_num_packets = min_t(u8, params.log_num_packets,
809 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
810
811 params.q_counter = priv->q_counter;
3f6d08d1 812 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 813 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 814 link_speed = max_t(u32, link_speed, 50000);
815 link_speed64 = link_speed;
816 do_div(link_speed64, 50000);
817 params.num_channels = link_speed64;
818
5c65c564 819 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 820 hpe->hp = hp;
821 complete_all(&hpe->res_ready);
5c65c564
OG		 822 if (IS_ERR(hp)) {
823 err = PTR_ERR(hp);
db76ca24 824 goto out_err;
5c65c564
OG		 825 }
826
eb9180f7 827 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 828 hp->tirn, hp->pair->rqn[0],
829 dev_name(hp->pair->peer_mdev->device),
eb9180f7 830 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 831
5c65c564 832attach_flow:
3f6d08d1 833 if (hpe->hp->num_channels > 1) {
226f2ca3 834 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 835 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 836 } else {
c620b772 837 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 838 }
b32accda 839
e4f9abbd 840 flow->hpe = hpe;
73edca73 841 spin_lock(&hpe->flows_lock);
5c65c564 842 list_add(&flow->hairpin, &hpe->flows);
73edca73 843 spin_unlock(&hpe->flows_lock);
3f6d08d1 844
5c65c564
OG		 845 return 0;
846
db76ca24
VB		 847out_err:
848 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 849 return err;
850}
851
852static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
853 struct mlx5e_tc_flow *flow)
854{
5a7e5bcb 855 /* flow wasn't fully initialized */
e4f9abbd 856 if (!flow->hpe)
5a7e5bcb
VB		 857 return;
858
73edca73 859 spin_lock(&flow->hpe->flows_lock);
5c65c564 860 list_del(&flow->hairpin);
73edca73
VB		 861 spin_unlock(&flow->hpe->flows_lock);
862
e4f9abbd
VB		 863 mlx5e_hairpin_put(priv, flow->hpe);
864 flow->hpe = NULL;
5c65c564
OG		 865}
866
08247066
AL		 867struct mlx5_flow_handle *
868mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
869 struct mlx5_flow_spec *spec,
c620b772 870 struct mlx5_flow_attr *attr)
e8f887ac 871{
08247066 872 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 873 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 874 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 875 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 876 struct mlx5_flow_destination dest[2] = {};
66958ed9 877 struct mlx5_flow_act flow_act = {
3bc4b7bf 878 .action = attr->action,
bb0ee7dc 879 .flags = FLOW_ACT_NO_APPEND,
66958ed9 880 };
08247066 881 struct mlx5_flow_handle *rule;
c7569097 882 struct mlx5_flow_table *ft;
08247066 883 int dest_ix = 0;
e8f887ac 884
bb0ee7dc 885 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 886 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 887
aedd133d
AL		 888 if (attr->dest_ft) {
889 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
890 dest[dest_ix].ft = attr->dest_ft;
891 dest_ix++;
892 } else if (nic_attr->hairpin_ft) {
08247066 893 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 894 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 895 dest_ix++;
c620b772 896 } else if (nic_attr->hairpin_tirn) {
08247066 897 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 898 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 899 dest_ix++;
3f6d08d1
OG		 900 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
901 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 902 if (attr->dest_chain) {
903 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
904 attr->dest_chain, 1,
905 MLX5E_TC_FT_LEVEL);
906 if (IS_ERR(dest[dest_ix].ft))
907 return ERR_CAST(dest[dest_ix].ft);
908 } else {
909 dest[dest_ix].ft = priv->fs.vlan.ft.t;
910 }
3f6d08d1 911 dest_ix++;
5c65c564 912 }
aad7e08d 913
c7569097
AL		 914 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
915 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
916 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
917
08247066 918 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 919 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 920 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 921 dest_ix++;
aad7e08d
AV		 922 }
923
08247066 924 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 925 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 926
6a064674
AL		 927 mutex_lock(&tc->t_lock);
928 if (IS_ERR_OR_NULL(tc->t)) {
929 /* Create the root table here if doesn't exist yet */
930 tc->t =
c7569097 931 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 932
933 if (IS_ERR(tc->t)) {
934 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 935 netdev_err(priv->netdev,
936 "Failed to create tc offload table\n");
c7569097
AL		 937 rule = ERR_CAST(priv->fs.tc.t);
938 goto err_ft_get;
e8f887ac 939 }
e8f887ac 940 }
08247066 941 mutex_unlock(&tc->t_lock);
e8f887ac 942
aedd133d
AL		 943 if (attr->chain || attr->prio)
944 ft = mlx5_chains_get_table(nic_chains,
945 attr->chain, attr->prio,
946 MLX5E_TC_FT_LEVEL);
947 else
948 ft = attr->ft;
949
c7569097
AL		 950 if (IS_ERR(ft)) {
951 rule = ERR_CAST(ft);
952 goto err_ft_get;
953 }
954
c620b772 955 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 956 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 957
c7569097 958 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 959 &flow_act, dest, dest_ix);
960 if (IS_ERR(rule))
c7569097 961 goto err_rule;
08247066
AL		 962
963 return rule;
c7569097
AL		 964
965err_rule:
aedd133d
AL		 966 if (attr->chain || attr->prio)
967 mlx5_chains_put_table(nic_chains,
968 attr->chain, attr->prio,
969 MLX5E_TC_FT_LEVEL);
c7569097
AL		 970err_ft_get:
971 if (attr->dest_chain)
972 mlx5_chains_put_table(nic_chains,
973 attr->dest_chain, 1,
974 MLX5E_TC_FT_LEVEL);
975
976 return ERR_CAST(rule);
08247066
AL		 977}
978
979static int
980mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
981 struct mlx5e_tc_flow_parse_attr *parse_attr,
982 struct mlx5e_tc_flow *flow,
983 struct netlink_ext_ack *extack)
984{
c620b772 985 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 986 struct mlx5_core_dev *dev = priv->mdev;
987 struct mlx5_fc *counter = NULL;
988 int err;
989
990 if (flow_flag_test(flow, HAIRPIN)) {
991 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
992 if (err)
993 return err;
994 }
995
996 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
997 counter = mlx5_fc_create(dev, true);
998 if (IS_ERR(counter))
999 return PTR_ERR(counter);
1000
1001 attr->counter = counter;
1002 }
1003
1004 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1005 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1006 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1007 if (err)
1008 return err;
1009 }
1010
aedd133d
AL		 1011 if (flow_flag_test(flow, CT))
1012 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1013 attr, &parse_attr->mod_hdr_acts);
1014 else
1015 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1016 attr);
aad7e08d 1017
a2b7189b 1018 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1019}
1020
08247066 1021void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1022 struct mlx5_flow_handle *rule,
1023 struct mlx5_flow_attr *attr)
08247066 1024{
c7569097
AL		 1025 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1026
08247066 1027 mlx5_del_flow_rules(rule);
c7569097 1028
aedd133d
AL		 1029 if (attr->chain || attr->prio)
1030 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1031 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1032
1033 if (attr->dest_chain)
1034 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1035 MLX5E_TC_FT_LEVEL);
08247066
AL		 1036}
1037
d85cdccb
OG		 1038static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1039 struct mlx5e_tc_flow *flow)
1040{
c620b772 1041 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1042 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1043
c7569097
AL		 1044 flow_flag_clear(flow, OFFLOADED);
1045
aedd133d
AL		 1046 if (flow_flag_test(flow, CT))
1047 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1048 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1049 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1050
c7569097
AL		 1051 /* Remove root table if no rules are left to avoid
1052 * extra steering hops.
1053 */
b6fac0b4 1054 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1055 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1056 !IS_ERR_OR_NULL(tc->t)) {
1057 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1058 priv->fs.tc.t = NULL;
1059 }
b6fac0b4 1060 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1061
aedd133d
AL		 1062 kvfree(attr->parse_attr);
1063
513f8f7f 1064 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1065 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1066
aedd133d
AL		 1067 mlx5_fc_destroy(priv->mdev, attr->counter);
1068
226f2ca3 1069 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1070 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1071
1072 kfree(flow->attr);
d85cdccb
OG		 1073}
1074
0d9f9647 1075struct mlx5_flow_handle *
6d2a3ed0
OG		 1076mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1077 struct mlx5e_tc_flow *flow,
1078 struct mlx5_flow_spec *spec,
c620b772 1079 struct mlx5_flow_attr *attr)
6d2a3ed0 1080{
1ef3018f 1081 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1082 struct mlx5_flow_handle *rule;
4c3844d9 1083
89e39467
PB		 1084 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1085 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1086
1ef3018f
PB		 1087 if (flow_flag_test(flow, CT)) {
1088 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1089
69e2916e 1090 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1091 flow, spec, attr,
1ef3018f 1092 mod_hdr_acts);
69e2916e
PB		 1093 } else {
1094 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1095 }
6d2a3ed0 1096
6d2a3ed0
OG		 1097 if (IS_ERR(rule))
1098 return rule;
1099
c620b772 1100 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1101 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1102 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1103 if (flow_flag_test(flow, CT))
1104 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1105 else
1106 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1107 return flow->rule[1];
1108 }
1109 }
1110
6d2a3ed0
OG		 1111 return rule;
1112}
1113
0d9f9647
VB		 1114void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1115 struct mlx5e_tc_flow *flow,
1116 struct mlx5_flow_attr *attr)
6d2a3ed0 1117{
226f2ca3 1118 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1119
89e39467
PB		 1120 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1121 goto offload_rule_0;
1122
4c3844d9 1123 if (flow_flag_test(flow, CT)) {
aedd133d 1124 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1125 return;
1126 }
1127
c620b772 1128 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1129 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1130
89e39467 1131offload_rule_0:
6d2a3ed0
OG		 1132 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1133}
1134
0d9f9647 1135struct mlx5_flow_handle *
5dbe906f
PB		 1136mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1137 struct mlx5e_tc_flow *flow,
178f69b4 1138 struct mlx5_flow_spec *spec)
5dbe906f 1139{
c620b772 1140 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1141 struct mlx5_flow_handle *rule;
1142
c620b772
AL		 1143 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1144 if (!slow_attr)
1145 return ERR_PTR(-ENOMEM);
5dbe906f 1146
c620b772
AL		 1147 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1148 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1149 slow_attr->esw_attr->split_count = 0;
1150 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1151
1152 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1153 if (!IS_ERR(rule))
226f2ca3 1154 flow_flag_set(flow, SLOW);
5dbe906f 1155
c620b772
AL		 1156 kfree(slow_attr);
1157
5dbe906f
PB		 1158 return rule;
1159}
1160
0d9f9647
VB		 1161void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1162 struct mlx5e_tc_flow *flow)
5dbe906f 1163{
c620b772 1164 struct mlx5_flow_attr *slow_attr;
178f69b4 1165
c620b772 1166 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1167 if (!slow_attr) {
1168 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1169 return;
1170 }
c620b772
AL		 1171
1172 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1173 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1174 slow_attr->esw_attr->split_count = 0;
1175 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1176 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1177 flow_flag_clear(flow, SLOW);
c620b772 1178 kfree(slow_attr);
5dbe906f
PB		 1179}
1180
ad86755b
VB		 1181/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1182 * function.
1183 */
1184static void unready_flow_add(struct mlx5e_tc_flow *flow,
1185 struct list_head *unready_flows)
1186{
1187 flow_flag_set(flow, NOT_READY);
1188 list_add_tail(&flow->unready, unready_flows);
1189}
1190
1191/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1192 * function.
1193 */
1194static void unready_flow_del(struct mlx5e_tc_flow *flow)
1195{
1196 list_del(&flow->unready);
1197 flow_flag_clear(flow, NOT_READY);
1198}
1199
b4a23329
RD		 1200static void add_unready_flow(struct mlx5e_tc_flow *flow)
1201{
1202 struct mlx5_rep_uplink_priv *uplink_priv;
1203 struct mlx5e_rep_priv *rpriv;
1204 struct mlx5_eswitch *esw;
1205
1206 esw = flow->priv->mdev->priv.eswitch;
1207 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1208 uplink_priv = &rpriv->uplink_priv;
1209
ad86755b
VB		 1210 mutex_lock(&uplink_priv->unready_flows_lock);
1211 unready_flow_add(flow, &uplink_priv->unready_flows);
1212 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1213}
1214
1215static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1216{
ad86755b
VB		 1217 struct mlx5_rep_uplink_priv *uplink_priv;
1218 struct mlx5e_rep_priv *rpriv;
1219 struct mlx5_eswitch *esw;
1220
1221 esw = flow->priv->mdev->priv.eswitch;
1222 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1223 uplink_priv = &rpriv->uplink_priv;
1224
1225 mutex_lock(&uplink_priv->unready_flows_lock);
1226 unready_flow_del(flow);
1227 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1228}
1229
10742efc
VB		 1230static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1231
a508728a 1232bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1233{
1234 struct mlx5_core_dev *out_mdev, *route_mdev;
1235 struct mlx5e_priv *out_priv, *route_priv;
1236
1237 out_priv = netdev_priv(out_dev);
1238 out_mdev = out_priv->mdev;
1239 route_priv = netdev_priv(route_dev);
1240 route_mdev = route_priv->mdev;
1241
1242 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1243 route_mdev->coredev_type != MLX5_COREDEV_VF)
1244 return false;
1245
1246 return same_hw_devs(out_priv, route_priv);
1247}
1248
a508728a 1249int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1250{
1251 struct mlx5e_priv *out_priv, *route_priv;
1252 struct mlx5_core_dev *route_mdev;
1253 struct mlx5_eswitch *esw;
1254 u16 vhca_id;
1255 int err;
1256
1257 out_priv = netdev_priv(out_dev);
1258 esw = out_priv->mdev->priv.eswitch;
1259 route_priv = netdev_priv(route_dev);
1260 route_mdev = route_priv->mdev;
1261
1262 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1263 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1264 return err;
1265}
1266
c7b9038d
VB		 1267int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1268 struct mlx5e_tc_flow_parse_attr *parse_attr,
1269 struct mlx5e_tc_flow *flow)
1270{
1271 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1272 struct mlx5_modify_hdr *mod_hdr;
1273
1274 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1275 get_flow_name_space(flow),
1276 mod_hdr_acts->num_actions,
1277 mod_hdr_acts->actions);
1278 if (IS_ERR(mod_hdr))
1279 return PTR_ERR(mod_hdr);
1280
1281 WARN_ON(flow->attr->modify_hdr);
1282 flow->attr->modify_hdr = mod_hdr;
1283
1284 return 0;
1285}
1286
c83954ab 1287static int
74491de9 1288mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1289 struct mlx5e_tc_flow *flow,
1290 struct netlink_ext_ack *extack)
adb4c123
OG		 1291{
1292 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1293 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1294 struct mlx5e_tc_flow_parse_attr *parse_attr;
1295 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1296 bool vf_tun = false, encap_valid = true;
c620b772 1297 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1298 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1299 struct mlx5e_rep_priv *rpriv;
1300 struct mlx5e_priv *out_priv;
39ac237c 1301 u32 max_prio, max_chain;
0ad060ee 1302 int err = 0;
f493f155 1303 int out_index;
8b32580d 1304
84179981
PB		 1305 /* We check chain range only for tc flows.
1306 * For ft flows, we checked attr->chain was originally 0 and set it to
1307 * FDB_FT_CHAIN which is outside tc range.
1308 * See mlx5e_rep_setup_ft_cb().
1309 */
ae430332 1310 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1311 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1312 NL_SET_ERR_MSG_MOD(extack,
1313 "Requested chain is out of supported range");
8914add2
VB		 1314 err = -EOPNOTSUPP;
1315 goto err_out;
bf07aa73
PB		 1316 }
1317
ae430332 1318 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1319 if (attr->prio > max_prio) {
61644c3d
RD		 1320 NL_SET_ERR_MSG_MOD(extack,
1321 "Requested priority is out of supported range");
8914add2
VB		 1322 err = -EOPNOTSUPP;
1323 goto err_out;
bf07aa73 1324 }
e52c2802 1325
777bb800
VB		 1326 if (flow_flag_test(flow, TUN_RX)) {
1327 err = mlx5e_attach_decap_route(priv, flow);
1328 if (err)
8914add2 1329 goto err_out;
777bb800
VB		 1330 }
1331
14e6b038
EC		 1332 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1333 err = mlx5e_attach_decap(priv, flow, extack);
1334 if (err)
8914add2 1335 goto err_out;
14e6b038
EC		 1336 }
1337
c620b772
AL		 1338 parse_attr = attr->parse_attr;
1339 esw_attr = attr->esw_attr;
1340
f493f155 1341 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1342 int mirred_ifindex;
1343
c620b772 1344 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1345 continue;
1346
7040632d 1347 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1348 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1349 mirred_ifindex);
733d4f36 1350 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1351 extack, &encap_dev, &encap_valid);
1352 if (err)
8914add2 1353 goto err_out;
0ad060ee 1354
8914add2
VB		 1355 if (esw_attr->dests[out_index].flags &
1356 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1357 vf_tun = true;
3c37745e
OG		 1358 out_priv = netdev_priv(encap_dev);
1359 rpriv = out_priv->ppriv;
c620b772
AL		 1360 esw_attr->dests[out_index].rep = rpriv->rep;
1361 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1362 }
1363
8b32580d 1364 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1365 if (err)
8914add2 1366 goto err_out;
adb4c123 1367
d5a3c2b6
RD		 1368 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1369 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1370 if (vf_tun) {
1371 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1372 if (err)
1373 goto err_out;
1374 } else {
1375 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1376 if (err)
1377 goto err_out;
1378 }
d7e75a32
OG		 1379 }
1380
b8aee822 1381 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1382 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1383 if (IS_ERR(counter)) {
1384 err = PTR_ERR(counter);
1385 goto err_out;
1386 }
b8aee822
MB		 1387
1388 attr->counter = counter;
1389 }
1390
0ad060ee
RD		 1391 /* we get here if one of the following takes place:
1392 * (1) there's no error
1393 * (2) there's an encap action and we don't have valid neigh
3c37745e 1394 */
bc1d75fa 1395 if (!encap_valid)
178f69b4 1396 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1397 else
6d2a3ed0 1398 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1399
8914add2
VB		 1400 if (IS_ERR(flow->rule[0])) {
1401 err = PTR_ERR(flow->rule[0]);
1402 goto err_out;
1403 }
1404 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1405
1406 return 0;
8914add2
VB		 1407
1408err_out:
1409 flow_flag_set(flow, FAILED);
1410 return err;
aa0cbbae 1411}
d85cdccb 1412
9272e3df
YK		 1413static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1414{
c620b772 1415 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1416 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1417 spec->match_value,
1418 misc_parameters_3);
1419 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1420 headers_v,
1421 geneve_tlv_option_0_data);
1422
1423 return !!geneve_tlv_opt_0_data;
1424}
1425
d85cdccb
OG		 1426static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1427 struct mlx5e_tc_flow *flow)
1428{
1429 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1430 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1431 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1432 bool vf_tun = false;
f493f155 1433 int out_index;
d85cdccb 1434
777bb800 1435 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1436 mlx5e_put_flow_tunnel_id(flow);
1437
12a240a4 1438 if (flow_flag_test(flow, NOT_READY))
b4a23329 1439 remove_unready_flow(flow);
ef06c9ee 1440
226f2ca3
VB		 1441 if (mlx5e_is_offloaded_flow(flow)) {
1442 if (flow_flag_test(flow, SLOW))
178f69b4 1443 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1444 else
1445 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1446 }
d85cdccb 1447
9272e3df
YK		 1448 if (mlx5_flow_has_geneve_opt(flow))
1449 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1450
513f8f7f 1451 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1452
777bb800
VB		 1453 if (flow->decap_route)
1454 mlx5e_detach_decap_route(priv, flow);
1455
1456 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1457 if (esw_attr->dests[out_index].flags &
1458 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1459 vf_tun = true;
777bb800 1460 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1461 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1462 kfree(attr->parse_attr->tun_info[out_index]);
1463 }
777bb800 1464 }
d7e75a32 1465
aedd133d 1466 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1467
c7b9038d
VB		 1468 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1469 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1470 if (vf_tun && attr->modify_hdr)
1471 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1472 else
1473 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1474 }
8914add2
VB		 1475 kvfree(attr->parse_attr);
1476 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1477
1478 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1479 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1480
1481 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1482 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1483
1484 kfree(flow->attr);
d85cdccb
OG		 1485}
1486
0d9f9647 1487struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1488{
c620b772 1489 return flow->attr->counter;
b8aee822
MB		 1490}
1491
6a06c2f7 1492/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1493void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1494{
1495 struct mlx5e_tc_flow *flow, *tmp;
1496
1497 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1498 mlx5e_flow_put(priv, flow);
1499}
1500
04de7dda
RD		 1501static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1502{
1503 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1504
226f2ca3
VB		 1505 if (!flow_flag_test(flow, ESWITCH) ||
1506 !flow_flag_test(flow, DUP))
04de7dda
RD		 1507 return;
1508
1509 mutex_lock(&esw->offloads.peer_mutex);
1510 list_del(&flow->peer);
1511 mutex_unlock(&esw->offloads.peer_mutex);
1512
226f2ca3 1513 flow_flag_clear(flow, DUP);
04de7dda 1514
eb252c3a
RD		 1515 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1516 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1517 kfree(flow->peer_flow);
1518 }
1519
04de7dda
RD		 1520 flow->peer_flow = NULL;
1521}
1522
1523static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1524{
1525 struct mlx5_core_dev *dev = flow->priv->mdev;
1526 struct mlx5_devcom *devcom = dev->priv.devcom;
1527 struct mlx5_eswitch *peer_esw;
1528
1529 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1530 if (!peer_esw)
1531 return;
1532
1533 __mlx5e_tc_del_fdb_peer_flow(flow);
1534 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1535}
1536
e8f887ac 1537static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1538 struct mlx5e_tc_flow *flow)
e8f887ac 1539{
226f2ca3 1540 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1541 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1542 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1543 } else {
d85cdccb 1544 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1545 }
e8f887ac
AV		 1546}
1547
0a7fcb78
PB		 1548static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1549{
1550 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1551 struct flow_action *flow_action = &rule->action;
1552 const struct flow_action_entry *act;
1553 int i;
1554
1555 flow_action_for_each(i, act, flow_action) {
1556 switch (act->id) {
1557 case FLOW_ACTION_GOTO:
1558 return true;
1559 default:
1560 continue;
1561 }
1562 }
1563
1564 return false;
1565}
bbd00f7e 1566
0a7fcb78
PB		 1567static int
1568enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1569 struct flow_dissector_key_enc_opts *opts,
1570 struct netlink_ext_ack *extack,
1571 bool *dont_care)
1572{
1573 struct geneve_opt *opt;
1574 int off = 0;
1575
1576 *dont_care = true;
1577
1578 while (opts->len > off) {
1579 opt = (struct geneve_opt *)&opts->data[off];
1580
1581 if (!(*dont_care) || opt->opt_class || opt->type ||
1582 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1583 *dont_care = false;
1584
c51323ee 1585 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1586 opt->type != U8_MAX) {
0a7fcb78
PB		 1587 NL_SET_ERR_MSG(extack,
1588 "Partial match of tunnel options in chain > 0 isn't supported");
1589 netdev_warn(priv->netdev,
1590 "Partial match of tunnel options in chain > 0 isn't supported");
1591 return -EOPNOTSUPP;
1592 }
1593 }
1594
1595 off += sizeof(struct geneve_opt) + opt->length * 4;
1596 }
1597
1598 return 0;
1599}
1600
1601#define COPY_DISSECTOR(rule, diss_key, dst)\
1602({ \
1603 struct flow_rule *__rule = (rule);\
1604 typeof(dst) __dst = dst;\
1605\
1606 memcpy(__dst,\
1607 skb_flow_dissector_target(__rule->match.dissector,\
1608 diss_key,\
1609 __rule->match.key),\
1610 sizeof(*__dst));\
1611})
1612
1613static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1614 struct mlx5e_tc_flow *flow,
1615 struct flow_cls_offload *f,
1616 struct net_device *filter_dev)
bbd00f7e 1617{
f9e30088 1618 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1619 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1620 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1621 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1622 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1623 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1624 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1625 struct mlx5e_rep_priv *uplink_rpriv;
1626 struct tunnel_match_key tunnel_key;
1627 bool enc_opts_is_dont_care = true;
1628 u32 tun_id, enc_opts_id = 0;
1629 struct mlx5_eswitch *esw;
1630 u32 value, mask;
8f256622 1631 int err;
2e72eb43 1632
0a7fcb78
PB		 1633 esw = priv->mdev->priv.eswitch;
1634 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1635 uplink_priv = &uplink_rpriv->uplink_priv;
1636
1637 memset(&tunnel_key, 0, sizeof(tunnel_key));
1638 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1639 &tunnel_key.enc_control);
1640 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1641 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1642 &tunnel_key.enc_ipv4);
1643 else
1644 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1645 &tunnel_key.enc_ipv6);
1646 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1647 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1648 &tunnel_key.enc_tp);
1649 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1650 &tunnel_key.enc_key_id);
1651 tunnel_key.filter_ifindex = filter_dev->ifindex;
1652
1653 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1654 if (err)
101f4de9 1655 return err;
bbd00f7e 1656
0a7fcb78
PB		 1657 flow_rule_match_enc_opts(rule, &enc_opts_match);
1658 err = enc_opts_is_dont_care_or_full_match(priv,
1659 enc_opts_match.mask,
1660 extack,
1661 &enc_opts_is_dont_care);
1662 if (err)
1663 goto err_enc_opts;
fe1587a7 1664
0a7fcb78 1665 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1666 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1667 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1668 sizeof(*enc_opts_match.key));
1669 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1670 sizeof(*enc_opts_match.mask));
1671
0a7fcb78 1672 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1673 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1674 if (err)
1675 goto err_enc_opts;
1676 }
fe1587a7 1677
0a7fcb78
PB		 1678 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1679 mask = enc_opts_id ? TUNNEL_ID_MASK :
1680 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1681
0a7fcb78
PB		 1682 if (attr->chain) {
1683 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1684 TUNNEL_TO_REG, value, mask);
1685 } else {
1686 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1687 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1688 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1689 TUNNEL_TO_REG, value);
1690 if (err)
1691 goto err_set;
fe1587a7 1692
0a7fcb78 1693 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1694 }
bbd00f7e 1695
0a7fcb78
PB		 1696 flow->tunnel_id = value;
1697 return 0;
bcef735c 1698
0a7fcb78
PB		 1699err_set:
1700 if (enc_opts_id)
1701 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1702 enc_opts_id);
1703err_enc_opts:
1704 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1705 return err;
1706}
bcef735c 1707
0a7fcb78
PB		 1708static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1709{
1710 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1711 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1712 struct mlx5_rep_uplink_priv *uplink_priv;
1713 struct mlx5e_rep_priv *uplink_rpriv;
1714 struct mlx5_eswitch *esw;
bcef735c 1715
0a7fcb78
PB		 1716 esw = flow->priv->mdev->priv.eswitch;
1717 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1718 uplink_priv = &uplink_rpriv->uplink_priv;
1719
1720 if (tun_id)
1721 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1722 if (enc_opts_id)
1723 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1724 enc_opts_id);
1725}
e98bedf5 1726
4c3844d9
PB		 1727u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1728{
1729 return flow->tunnel_id;
1730}
1731
fca53304
EB		 1732void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1733 struct flow_match_basic *match, bool outer,
1734 void *headers_c, void *headers_v)
1735{
1736 bool ip_version_cap;
1737
1738 ip_version_cap = outer ?
1739 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1740 ft_field_support.outer_ip_version) :
1741 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1742 ft_field_support.inner_ip_version);
1743
1744 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1745 (match->key->n_proto == htons(ETH_P_IP) ||
1746 match->key->n_proto == htons(ETH_P_IPV6))) {
1747 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1748 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1749 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1750 } else {
1751 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1752 ntohs(match->mask->n_proto));
1753 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1754 ntohs(match->key->n_proto));
1755 }
4a5d5d73
EB		 1756}
1757
0d9f9647 1758u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1759{
1760 void *headers_v;
1761 u16 ethertype;
1762 u8 ip_version;
1763
1764 if (outer)
1765 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1766 else
1767 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1768
1769 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1770 /* Return ip_version converted from ethertype anyway */
1771 if (!ip_version) {
1772 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1773 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1774 ip_version = 4;
1775 else if (ethertype == ETH_P_IPV6)
1776 ip_version = 6;
1777 }
1778 return ip_version;
1779}
1780
bbd00f7e 1781static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1782 struct mlx5e_tc_flow *flow,
bbd00f7e 1783 struct mlx5_flow_spec *spec,
f9e30088 1784 struct flow_cls_offload *f,
0a7fcb78
PB		 1785 struct net_device *filter_dev,
1786 u8 *match_level,
1787 bool *match_inner)
bbd00f7e 1788{
a508728a 1789 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1790 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1791 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1792 bool needs_mapping, sets_mapping;
8f256622 1793 int err;
2e72eb43 1794
0a7fcb78
PB		 1795 if (!mlx5e_is_eswitch_flow(flow))
1796 return -EOPNOTSUPP;
1797
c620b772
AL		 1798 needs_mapping = !!flow->attr->chain;
1799 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 1800 *match_inner = !needs_mapping;
1801
1802 if ((needs_mapping || sets_mapping) &&
636bb968 1803 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1804 NL_SET_ERR_MSG(extack,
636bb968 1805 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1806 netdev_warn(priv->netdev,
636bb968 1807 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1808 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1809 }
1810
c620b772 1811 if (!flow->attr->chain) {
0a7fcb78
PB		 1812 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1813 match_level);
1814 if (err) {
e98bedf5 1815 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1816 "Failed to parse tunnel attributes");
1817 netdev_warn(priv->netdev,
1818 "Failed to parse tunnel attributes");
1819 return err;
e98bedf5
EB		 1820 }
1821
14e6b038
EC		 1822 /* With mpls over udp we decapsulate using packet reformat
1823 * object
1824 */
1825 if (!netif_is_bareudp(filter_dev))
c620b772 1826 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1827 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1828 if (err)
1829 return err;
1830 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1831 struct mlx5_flow_spec *tmp_spec;
1832
1833 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1834 if (!tmp_spec) {
1835 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1836 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1837 return -ENOMEM;
1838 }
1839 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1840
1841 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1842 if (err) {
1843 kvfree(tmp_spec);
1844 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1845 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1846 return err;
1847 }
1848 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1849 kvfree(tmp_spec);
1850 if (err)
1851 return err;
bcef735c
OG		 1852 }
1853
0a7fcb78
PB		 1854 if (!needs_mapping && !sets_mapping)
1855 return 0;
bbd00f7e 1856
0a7fcb78 1857 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1858}
bbd00f7e 1859
0a7fcb78 1860static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1861{
0a7fcb78
PB		 1862 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1863 inner_headers);
bbd00f7e
HHZ		 1864}
1865
0a7fcb78 1866static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1867{
0a7fcb78
PB		 1868 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1869 inner_headers);
1870}
1871
1872static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1873{
1874 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1875 outer_headers);
1876}
1877
1878static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1879{
1880 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1881 outer_headers);
8377629e
EB		 1882}
1883
1884static void *get_match_headers_value(u32 flags,
1885 struct mlx5_flow_spec *spec)
1886{
1887 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1888 get_match_inner_headers_value(spec) :
1889 get_match_outer_headers_value(spec);
1890}
1891
1892static void *get_match_headers_criteria(u32 flags,
1893 struct mlx5_flow_spec *spec)
1894{
1895 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1896 get_match_inner_headers_criteria(spec) :
1897 get_match_outer_headers_criteria(spec);
8377629e
EB		 1898}
1899
6d65bc64 1900static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1901 struct flow_cls_offload *f)
1902{
1903 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1904 struct netlink_ext_ack *extack = f->common.extack;
1905 struct net_device *ingress_dev;
1906 struct flow_match_meta match;
1907
1908 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1909 return 0;
1910
1911 flow_rule_match_meta(rule, &match);
1912 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1913 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 1914 return -EOPNOTSUPP;
6d65bc64 1915 }
1916
1917 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1918 match.key->ingress_ifindex);
1919 if (!ingress_dev) {
1920 NL_SET_ERR_MSG_MOD(extack,
1921 "Can't find the ingress port to match on");
a683012a 1922 return -ENOENT;
6d65bc64 1923 }
1924
1925 if (ingress_dev != filter_dev) {
1926 NL_SET_ERR_MSG_MOD(extack,
1927 "Can't match on the ingress filter port");
a683012a 1928 return -EOPNOTSUPP;
6d65bc64 1929 }
1930
1931 return 0;
1932}
1933
72046a91
EC		 1934static bool skip_key_basic(struct net_device *filter_dev,
1935 struct flow_cls_offload *f)
1936{
1937 /* When doing mpls over udp decap, the user needs to provide
1938 * MPLS_UC as the protocol in order to be able to match on mpls
1939 * label fields. However, the actual ethertype is IP so we want to
1940 * avoid matching on this, otherwise we'll fail the match.
1941 */
1942 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
1943 return true;
1944
1945 return false;
1946}
1947
de0af0bf 1948static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 1949 struct mlx5e_tc_flow *flow,
de0af0bf 1950 struct mlx5_flow_spec *spec,
f9e30088 1951 struct flow_cls_offload *f,
54c177ca 1952 struct net_device *filter_dev,
93b3586e 1953 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 1954{
e98bedf5 1955 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1956 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1957 outer_headers);
1958 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1959 outer_headers);
699e96dd
JL		 1960 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1961 misc_parameters);
1962 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1963 misc_parameters);
a3222a2d
MD		 1964 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1965 misc_parameters_3);
1966 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1967 misc_parameters_3);
f9e30088 1968 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1969 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1970 u16 addr_type = 0;
1971 u8 ip_proto = 0;
93b3586e 1972 u8 *match_level;
6d65bc64 1973 int err;
e3a2b7ed 1974
93b3586e 1975 match_level = outer_match_level;
de0af0bf 1976
8f256622 1977 if (dissector->used_keys &
3d144578
VB		 1978 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1979 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1980 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1981 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1982 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1983 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1984 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1985 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1986 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1987 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1988 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1989 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1990 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1991 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1992 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1993 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 1994 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 1995 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 1996 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 1997 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 1998 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 1999 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2000 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2001 dissector->used_keys);
e3a2b7ed
AV		 2002 return -EOPNOTSUPP;
2003 }
2004
075973c7 2005 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2006 bool match_inner = false;
bbd00f7e 2007
0a7fcb78
PB		 2008 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2009 outer_match_level, &match_inner);
2010 if (err)
2011 return err;
2012
2013 if (match_inner) {
2014 /* header pointers should point to the inner headers
2015 * if the packet was decapsulated already.
2016 * outer headers are set by parse_tunnel_attr.
2017 */
2018 match_level = inner_match_level;
2019 headers_c = get_match_inner_headers_criteria(spec);
2020 headers_v = get_match_inner_headers_value(spec);
2021 }
bbd00f7e
HHZ		 2022 }
2023
6d65bc64 2024 err = mlx5e_flower_parse_meta(filter_dev, f);
2025 if (err)
2026 return err;
2027
72046a91
EC		 2028 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2029 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2030 struct flow_match_basic match;
2031
2032 flow_rule_match_basic(rule, &match);
fca53304
EB		 2033 mlx5e_tc_set_ethertype(priv->mdev, &match,
2034 match_level == outer_match_level,
2035 headers_c, headers_v);
e3a2b7ed 2036
8f256622 2037 if (match.mask->n_proto)
d708f902 2038 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2039 }
35a605db
EB		 2040 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2041 is_vlan_dev(filter_dev)) {
2042 struct flow_dissector_key_vlan filter_dev_mask;
2043 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2044 struct flow_match_vlan match;
2045
35a605db
EB		 2046 if (is_vlan_dev(filter_dev)) {
2047 match.key = &filter_dev_key;
2048 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2049 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2050 match.key->vlan_priority = 0;
2051 match.mask = &filter_dev_mask;
2052 memset(match.mask, 0xff, sizeof(*match.mask));
2053 match.mask->vlan_priority = 0;
2054 } else {
2055 flow_rule_match_vlan(rule, &match);
2056 }
8f256622
PNA		 2057 if (match.mask->vlan_id ||
2058 match.mask->vlan_priority ||
2059 match.mask->vlan_tpid) {
2060 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2061 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2062 svlan_tag, 1);
2063 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2064 svlan_tag, 1);
2065 } else {
2066 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2067 cvlan_tag, 1);
2068 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2069 cvlan_tag, 1);
2070 }
095b6cfd 2071
8f256622
PNA		 2072 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2073 match.mask->vlan_id);
2074 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2075 match.key->vlan_id);
358d79a4 2076
8f256622
PNA		 2077 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2078 match.mask->vlan_priority);
2079 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2080 match.key->vlan_priority);
54782900 2081
d708f902 2082 *match_level = MLX5_MATCH_L2;
54782900 2083 }
d3a80bb5 2084 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2085 /* cvlan_tag enabled in match criteria and
2086 * disabled in match value means both S & C tags
2087 * don't exist (untagged of both)
2088 */
cee26487 2089 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2090 *match_level = MLX5_MATCH_L2;
54782900
OG		 2091 }
2092
8f256622
PNA		 2093 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2094 struct flow_match_vlan match;
2095
12d5cbf8 2096 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2097 if (match.mask->vlan_id ||
2098 match.mask->vlan_priority ||
2099 match.mask->vlan_tpid) {
2100 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2101 MLX5_SET(fte_match_set_misc, misc_c,
2102 outer_second_svlan_tag, 1);
2103 MLX5_SET(fte_match_set_misc, misc_v,
2104 outer_second_svlan_tag, 1);
2105 } else {
2106 MLX5_SET(fte_match_set_misc, misc_c,
2107 outer_second_cvlan_tag, 1);
2108 MLX5_SET(fte_match_set_misc, misc_v,
2109 outer_second_cvlan_tag, 1);
2110 }
2111
2112 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2113 match.mask->vlan_id);
699e96dd 2114 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2115 match.key->vlan_id);
699e96dd 2116 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2117 match.mask->vlan_priority);
699e96dd 2118 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2119 match.key->vlan_priority);
699e96dd
JL		 2120
2121 *match_level = MLX5_MATCH_L2;
0faddfe6 2122 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2123 }
2124 }
2125
8f256622
PNA		 2126 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2127 struct flow_match_eth_addrs match;
54782900 2128
8f256622 2129 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2130 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2131 dmac_47_16),
8f256622 2132 match.mask->dst);
d3a80bb5
OG		 2133 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2134 dmac_47_16),
8f256622 2135 match.key->dst);
d3a80bb5
OG		 2136
2137 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2138 smac_47_16),
8f256622 2139 match.mask->src);
d3a80bb5
OG		 2140 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2141 smac_47_16),
8f256622 2142 match.key->src);
d3a80bb5 2143
8f256622
PNA		 2144 if (!is_zero_ether_addr(match.mask->src) ||
2145 !is_zero_ether_addr(match.mask->dst))
d708f902 2146 *match_level = MLX5_MATCH_L2;
54782900
OG		 2147 }
2148
8f256622
PNA		 2149 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2150 struct flow_match_control match;
54782900 2151
8f256622
PNA		 2152 flow_rule_match_control(rule, &match);
2153 addr_type = match.key->addr_type;
54782900
OG		 2154
2155 /* the HW doesn't support frag first/later */
8f256622 2156 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2157 return -EOPNOTSUPP;
2158
8f256622 2159 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2160 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2161 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2162 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2163
2164 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2165 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2166 *match_level = MLX5_MATCH_L2;
54782900
OG		 2167 /* *** L2 attributes parsing up to here *** */
2168 else
83621b7d 2169 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2170 }
2171 }
2172
8f256622
PNA		 2173 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2174 struct flow_match_basic match;
2175
2176 flow_rule_match_basic(rule, &match);
2177 ip_proto = match.key->ip_proto;
54782900
OG		 2178
2179 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2180 match.mask->ip_proto);
54782900 2181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2182 match.key->ip_proto);
54782900 2183
8f256622 2184 if (match.mask->ip_proto)
d708f902 2185 *match_level = MLX5_MATCH_L3;
54782900
OG		 2186 }
2187
e3a2b7ed 2188 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2189 struct flow_match_ipv4_addrs match;
e3a2b7ed 2190
8f256622 2191 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2192 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2193 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2194 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2195 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2196 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2197 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2198 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2199 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2200 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2201 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2202 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2203 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2204
8f256622 2205 if (match.mask->src || match.mask->dst)
d708f902 2206 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2207 }
2208
2209 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2210 struct flow_match_ipv6_addrs match;
e3a2b7ed 2211
8f256622 2212 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2213 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2214 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2215 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2216 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2217 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2218 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2219
2220 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2221 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2222 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2223 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2224 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2225 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2226
8f256622
PNA		 2227 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2228 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2229 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2230 }
2231
8f256622
PNA		 2232 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2233 struct flow_match_ip match;
1f97a526 2234
8f256622
PNA		 2235 flow_rule_match_ip(rule, &match);
2236 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2237 match.mask->tos & 0x3);
2238 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2239 match.key->tos & 0x3);
1f97a526 2240
8f256622
PNA		 2241 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2242 match.mask->tos >> 2);
2243 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2244 match.key->tos >> 2);
1f97a526 2245
8f256622
PNA		 2246 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2247 match.mask->ttl);
2248 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2249 match.key->ttl);
1f97a526 2250
8f256622 2251 if (match.mask->ttl &&
a8ade55f 2252 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2253 ft_field_support.outer_ipv4_ttl)) {
2254 NL_SET_ERR_MSG_MOD(extack,
2255 "Matching on TTL is not supported");
1f97a526 2256 return -EOPNOTSUPP;
e98bedf5 2257 }
a8ade55f 2258
8f256622 2259 if (match.mask->tos || match.mask->ttl)
d708f902 2260 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2261 }
2262
54782900
OG		 2263 /* *** L3 attributes parsing up to here *** */
2264
8f256622
PNA		 2265 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2266 struct flow_match_ports match;
2267
2268 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2269 switch (ip_proto) {
2270 case IPPROTO_TCP:
2271 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2272 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2273 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2274 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2275
2276 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2277 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2278 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2279 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2280 break;
2281
2282 case IPPROTO_UDP:
2283 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2284 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2285 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2286 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2287
2288 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2289 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2290 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2291 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2292 break;
2293 default:
e98bedf5
EB		 2294 NL_SET_ERR_MSG_MOD(extack,
2295 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2296 netdev_err(priv->netdev,
2297 "Only UDP and TCP transport are supported\n");
2298 return -EINVAL;
2299 }
de0af0bf 2300
8f256622 2301 if (match.mask->src || match.mask->dst)
d708f902 2302 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2303 }
2304
8f256622
PNA		 2305 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2306 struct flow_match_tcp match;
e77834ec 2307
8f256622 2308 flow_rule_match_tcp(rule, &match);
e77834ec 2309 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2310 ntohs(match.mask->flags));
e77834ec 2311 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2312 ntohs(match.key->flags));
e77834ec 2313
8f256622 2314 if (match.mask->flags)
d708f902 2315 *match_level = MLX5_MATCH_L4;
e77834ec 2316 }
a3222a2d
MD		 2317 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2318 struct flow_match_icmp match;
e77834ec 2319
a3222a2d
MD		 2320 flow_rule_match_icmp(rule, &match);
2321 switch (ip_proto) {
2322 case IPPROTO_ICMP:
2323 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2324 MLX5_FLEX_PROTO_ICMP))
2325 return -EOPNOTSUPP;
2326 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2327 match.mask->type);
2328 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2329 match.key->type);
2330 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2331 match.mask->code);
2332 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2333 match.key->code);
2334 break;
2335 case IPPROTO_ICMPV6:
2336 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2337 MLX5_FLEX_PROTO_ICMPV6))
2338 return -EOPNOTSUPP;
2339 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2340 match.mask->type);
2341 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2342 match.key->type);
2343 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2344 match.mask->code);
2345 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2346 match.key->code);
2347 break;
2348 default:
2349 NL_SET_ERR_MSG_MOD(extack,
2350 "Code and type matching only with ICMP and ICMPv6");
2351 netdev_err(priv->netdev,
2352 "Code and type matching only with ICMP and ICMPv6\n");
2353 return -EINVAL;
2354 }
2355 if (match.mask->code || match.mask->type) {
2356 *match_level = MLX5_MATCH_L4;
2357 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2358 }
2359 }
e3a2b7ed
AV		 2360 return 0;
2361}
2362
de0af0bf 2363static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2364 struct mlx5e_tc_flow *flow,
de0af0bf 2365 struct mlx5_flow_spec *spec,
f9e30088 2366 struct flow_cls_offload *f,
54c177ca 2367 struct net_device *filter_dev)
de0af0bf 2368{
93b3586e 2369 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2370 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2371 struct mlx5_core_dev *dev = priv->mdev;
2372 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2373 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2374 struct mlx5_eswitch_rep *rep;
226f2ca3 2375 bool is_eswitch_flow;
de0af0bf
RD		 2376 int err;
2377
93b3586e
HN		 2378 inner_match_level = MLX5_MATCH_NONE;
2379 outer_match_level = MLX5_MATCH_NONE;
2380
0a7fcb78
PB		 2381 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2382 &inner_match_level, &outer_match_level);
93b3586e
HN		 2383 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2384 outer_match_level : inner_match_level;
de0af0bf 2385
226f2ca3
VB		 2386 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2387 if (!err && is_eswitch_flow) {
1d447a39 2388 rep = rpriv->rep;
b05af6aa 2389 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2390 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2391 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2392 NL_SET_ERR_MSG_MOD(extack,
2393 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2394 netdev_warn(priv->netdev,
2395 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2396 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2397 return -EOPNOTSUPP;
2398 }
2399 }
2400
c620b772
AL		 2401 flow->attr->inner_match_level = inner_match_level;
2402 flow->attr->outer_match_level = outer_match_level;
2403
38aa51c1 2404
de0af0bf
RD		 2405 return err;
2406}
2407
d79b6df6
OG		 2408struct pedit_headers {
2409 struct ethhdr eth;
0eb69bb9 2410 struct vlan_hdr vlan;
d79b6df6
OG		 2411 struct iphdr ip4;
2412 struct ipv6hdr ip6;
2413 struct tcphdr tcp;
2414 struct udphdr udp;
2415};
2416
c500c86b
PNA		 2417struct pedit_headers_action {
2418 struct pedit_headers vals;
2419 struct pedit_headers masks;
2420 u32 pedits;
2421};
2422
d79b6df6 2423static int pedit_header_offsets[] = {
73867881
PNA		 2424 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2425 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2426 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2427 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2428 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2429};
2430
2431#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2432
2433static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2434 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2435{
2436 u32 *curr_pmask, *curr_pval;
2437
c500c86b
PNA		 2438 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2439 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2440
2441 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2442 goto out_err;
2443
2444 *curr_pmask |= mask;
2445 *curr_pval |= (val & mask);
2446
2447 return 0;
2448
2449out_err:
2450 return -EOPNOTSUPP;
2451}
2452
2453struct mlx5_fields {
2454 u8 field;
88f30bbc
DL		 2455 u8 field_bsize;
2456 u32 field_mask;
d79b6df6 2457 u32 offset;
27c11b6b 2458 u32 match_offset;
d79b6df6
OG		 2459};
2460
88f30bbc
DL		 2461#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2462 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2463 offsetof(struct pedit_headers, field) + (off), \
2464 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2465
2ef86872
EB		 2466/* masked values are the same and there are no rewrites that do not have a
2467 * match.
2468 */
2469#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2470 type matchmaskx = *(type *)(matchmaskp); \
2471 type matchvalx = *(type *)(matchvalp); \
2472 type maskx = *(type *)(maskp); \
2473 type valx = *(type *)(valp); \
2474 \
2475 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2476 matchmaskx)); \
2477})
2478
27c11b6b 2479static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2480 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2481{
2482 bool same = false;
2483
88f30bbc
DL		 2484 switch (bsize) {
2485 case 8:
2ef86872 2486 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2487 break;
88f30bbc 2488 case 16:
2ef86872 2489 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2490 break;
88f30bbc 2491 case 32:
2ef86872 2492 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2493 break;
2494 }
2495
2496 return same;
2497}
a8e4f0c4 2498
d79b6df6 2499static struct mlx5_fields fields[] = {
88f30bbc
DL		 2500 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2501 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2502 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2503 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2504 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2505 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2506
ab9341b5 2507 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2508 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2509 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2510 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2511
2512 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2513 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2514 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2515 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2516 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2517 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2518 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2519 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2520 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2521 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2522 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2523 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2524 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2525 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2526 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2527 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2528 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2529 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2530
88f30bbc
DL		 2531 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2532 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2533 /* in linux iphdr tcp_flags is 8 bits long */
2534 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2535
88f30bbc
DL		 2536 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2537 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2538};
2539
82198d8b
MD		 2540static unsigned long mask_to_le(unsigned long mask, int size)
2541{
2542 __be32 mask_be32;
2543 __be16 mask_be16;
2544
2545 if (size == 32) {
2546 mask_be32 = (__force __be32)(mask);
2547 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2548 } else if (size == 16) {
2549 mask_be32 = (__force __be32)(mask);
2550 mask_be16 = *(__be16 *)&mask_be32;
2551 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2552 }
2553
2554 return mask;
2555}
6ae4a6a5
PB		 2556static int offload_pedit_fields(struct mlx5e_priv *priv,
2557 int namespace,
2558 struct pedit_headers_action *hdrs,
e98bedf5 2559 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2560 u32 *action_flags,
e98bedf5 2561 struct netlink_ext_ack *extack)
d79b6df6
OG		 2562{
2563 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2564 int i, action_size, first, last, next_z;
88f30bbc
DL		 2565 void *headers_c, *headers_v, *action, *vals_p;
2566 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2567 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2568 struct mlx5_fields *f;
82198d8b 2569 unsigned long mask, field_mask;
6ae4a6a5 2570 int err;
88f30bbc
DL		 2571 u8 cmd;
2572
6ae4a6a5 2573 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2574 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2575 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2576
73867881
PNA		 2577 set_masks = &hdrs[0].masks;
2578 add_masks = &hdrs[1].masks;
2579 set_vals = &hdrs[0].vals;
2580 add_vals = &hdrs[1].vals;
d79b6df6 2581
d65dbedf 2582 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2583
2584 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2585 bool skip;
2586
d79b6df6
OG		 2587 f = &fields[i];
2588 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2589 s_mask = 0;
2590 a_mask = 0;
d79b6df6
OG		 2591
2592 s_masks_p = (void *)set_masks + f->offset;
2593 a_masks_p = (void *)add_masks + f->offset;
2594
88f30bbc
DL		 2595 s_mask = *s_masks_p & f->field_mask;
2596 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2597
2598 if (!s_mask && !a_mask) /* nothing to offload here */
2599 continue;
2600
2601 if (s_mask && a_mask) {
e98bedf5
EB		 2602 NL_SET_ERR_MSG_MOD(extack,
2603 "can't set and add to the same HW field");
d79b6df6
OG		 2604 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2605 return -EOPNOTSUPP;
2606 }
2607
27c11b6b 2608 skip = false;
d79b6df6 2609 if (s_mask) {
27c11b6b
EB		 2610 void *match_mask = headers_c + f->match_offset;
2611 void *match_val = headers_v + f->match_offset;
2612
d79b6df6
OG		 2613 cmd = MLX5_ACTION_TYPE_SET;
2614 mask = s_mask;
2615 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2616 /* don't rewrite if we have a match on the same value */
2617 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2618 match_mask, f->field_bsize))
27c11b6b 2619 skip = true;
d79b6df6 2620 /* clear to denote we consumed this field */
88f30bbc 2621 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2622 } else {
2623 cmd = MLX5_ACTION_TYPE_ADD;
2624 mask = a_mask;
2625 vals_p = (void *)add_vals + f->offset;
27c11b6b 2626 /* add 0 is no change */
88f30bbc 2627 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2628 skip = true;
d79b6df6 2629 /* clear to denote we consumed this field */
88f30bbc 2630 *a_masks_p &= ~f->field_mask;
d79b6df6 2631 }
27c11b6b
EB		 2632 if (skip)
2633 continue;
d79b6df6 2634
82198d8b 2635 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2636
88f30bbc
DL		 2637 first = find_first_bit(&mask, f->field_bsize);
2638 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2639 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2640 if (first < next_z && next_z < last) {
e98bedf5
EB		 2641 NL_SET_ERR_MSG_MOD(extack,
2642 "rewrite of few sub-fields isn't supported");
2b64beba 2643 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2644 mask);
2645 return -EOPNOTSUPP;
2646 }
2647
6ae4a6a5
PB		 2648 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2649 if (err) {
2650 NL_SET_ERR_MSG_MOD(extack,
2651 "too many pedit actions, can't offload");
2652 mlx5_core_warn(priv->mdev,
2653 "mlx5: parsed %d pedit actions, can't do more\n",
2654 mod_acts->num_actions);
2655 return err;
2656 }
2657
2658 action = mod_acts->actions +
2659 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2660 MLX5_SET(set_action_in, action, action_type, cmd);
2661 MLX5_SET(set_action_in, action, field, f->field);
2662
2663 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2664 int start;
2665
82198d8b
MD		 2666 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2667
88f30bbc 2668 /* if field is bit sized it can start not from first bit */
82198d8b 2669 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2670
2671 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2672 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2673 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2674 }
2675
88f30bbc 2676 if (f->field_bsize == 32)
2b64beba 2677 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2678 else if (f->field_bsize == 16)
2b64beba 2679 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2680 else if (f->field_bsize == 8)
2b64beba 2681 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2682
6ae4a6a5 2683 ++mod_acts->num_actions;
d79b6df6
OG		 2684 }
2685
d79b6df6
OG		 2686 return 0;
2687}
2688
2cc1cb1d
TZ		 2689static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2690 int namespace)
2691{
2692 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2693 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2694 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2695 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2696}
2697
6ae4a6a5
PB		 2698int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2699 int namespace,
2700 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2701{
6ae4a6a5
PB		 2702 int action_size, new_num_actions, max_hw_actions;
2703 size_t new_sz, old_sz;
2704 void *ret;
d79b6df6 2705
6ae4a6a5
PB		 2706 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2707 return 0;
d79b6df6 2708
d65dbedf 2709 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2710
6ae4a6a5
PB		 2711 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2712 namespace);
2713 new_num_actions = min(max_hw_actions,
2714 mod_hdr_acts->actions ?
2715 mod_hdr_acts->max_actions * 2 : 1);
2716 if (mod_hdr_acts->max_actions == new_num_actions)
2717 return -ENOSPC;
2718
2719 new_sz = action_size * new_num_actions;
2720 old_sz = mod_hdr_acts->max_actions * action_size;
2721 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2722 if (!ret)
d79b6df6
OG		 2723 return -ENOMEM;
2724
6ae4a6a5
PB		 2725 memset(ret + old_sz, 0, new_sz - old_sz);
2726 mod_hdr_acts->actions = ret;
2727 mod_hdr_acts->max_actions = new_num_actions;
2728
d79b6df6
OG		 2729 return 0;
2730}
2731
6ae4a6a5
PB		 2732void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2733{
2734 kfree(mod_hdr_acts->actions);
2735 mod_hdr_acts->actions = NULL;
2736 mod_hdr_acts->num_actions = 0;
2737 mod_hdr_acts->max_actions = 0;
2738}
2739
d79b6df6
OG		 2740static const struct pedit_headers zero_masks = {};
2741
582234b4
EC		 2742static int
2743parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2744 const struct flow_action_entry *act, int namespace,
2745 struct mlx5e_tc_flow_parse_attr *parse_attr,
2746 struct pedit_headers_action *hdrs,
2747 struct netlink_ext_ack *extack)
d79b6df6 2748{
73867881
PNA		 2749 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2750 int err = -EOPNOTSUPP;
d79b6df6 2751 u32 mask, val, offset;
73867881 2752 u8 htype;
d79b6df6 2753
73867881
PNA		 2754 htype = act->mangle.htype;
2755 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2756
73867881
PNA		 2757 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2758 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2759 goto out_err;
2760 }
d79b6df6 2761
2cc1cb1d
TZ		 2762 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2763 NL_SET_ERR_MSG_MOD(extack,
2764 "The pedit offload action is not supported");
2765 goto out_err;
2766 }
2767
73867881
PNA		 2768 mask = act->mangle.mask;
2769 val = act->mangle.val;
2770 offset = act->mangle.offset;
d79b6df6 2771
73867881
PNA		 2772 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2773 if (err)
2774 goto out_err;
c500c86b 2775
73867881 2776 hdrs[cmd].pedits++;
d79b6df6 2777
c500c86b
PNA		 2778 return 0;
2779out_err:
2780 return err;
2781}
2782
582234b4
EC		 2783static int
2784parse_pedit_to_reformat(struct mlx5e_priv *priv,
2785 const struct flow_action_entry *act,
2786 struct mlx5e_tc_flow_parse_attr *parse_attr,
2787 struct netlink_ext_ack *extack)
2788{
2789 u32 mask, val, offset;
2790 u32 *p;
2791
2792 if (act->id != FLOW_ACTION_MANGLE)
2793 return -EOPNOTSUPP;
2794
2795 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2796 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2797 return -EOPNOTSUPP;
2798 }
2799
2800 mask = ~act->mangle.mask;
2801 val = act->mangle.val;
2802 offset = act->mangle.offset;
2803 p = (u32 *)&parse_attr->eth;
2804 *(p + (offset >> 2)) |= (val & mask);
2805
2806 return 0;
2807}
2808
2809static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2810 const struct flow_action_entry *act, int namespace,
2811 struct mlx5e_tc_flow_parse_attr *parse_attr,
2812 struct pedit_headers_action *hdrs,
2813 struct mlx5e_tc_flow *flow,
2814 struct netlink_ext_ack *extack)
2815{
2816 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2817 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2818
2819 return parse_pedit_to_modify_hdr(priv, act, namespace,
2820 parse_attr, hdrs, extack);
2821}
2822
c500c86b
PNA		 2823static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2824 struct mlx5e_tc_flow_parse_attr *parse_attr,
2825 struct pedit_headers_action *hdrs,
27c11b6b 2826 u32 *action_flags,
c500c86b
PNA		 2827 struct netlink_ext_ack *extack)
2828{
2829 struct pedit_headers *cmd_masks;
2830 int err;
2831 u8 cmd;
2832
6ae4a6a5
PB		 2833 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2834 action_flags, extack);
d79b6df6
OG		 2835 if (err < 0)
2836 goto out_dealloc_parsed_actions;
2837
2838 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2839 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2840 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2841 NL_SET_ERR_MSG_MOD(extack,
2842 "attempt to offload an unsupported field");
b3a433de 2843 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2844 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2845 16, 1, cmd_masks, sizeof(zero_masks), true);
2846 err = -EOPNOTSUPP;
2847 goto out_dealloc_parsed_actions;
2848 }
2849 }
2850
2851 return 0;
2852
2853out_dealloc_parsed_actions:
6ae4a6a5 2854 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2855 return err;
2856}
2857
e98bedf5
EB		 2858static bool csum_offload_supported(struct mlx5e_priv *priv,
2859 u32 action,
2860 u32 update_flags,
2861 struct netlink_ext_ack *extack)
26c02749
OG		 2862{
2863 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2864 TCA_CSUM_UPDATE_FLAG_UDP;
2865
2866 /* The HW recalcs checksums only if re-writing headers */
2867 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2868 NL_SET_ERR_MSG_MOD(extack,
2869 "TC csum action is only offloaded with pedit");
26c02749
OG		 2870 netdev_warn(priv->netdev,
2871 "TC csum action is only offloaded with pedit\n");
2872 return false;
2873 }
2874
2875 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2876 NL_SET_ERR_MSG_MOD(extack,
2877 "can't offload TC csum action for some header/s");
26c02749
OG		 2878 netdev_warn(priv->netdev,
2879 "can't offload TC csum action for some header/s - flags %#x\n",
2880 update_flags);
2881 return false;
2882 }
2883
2884 return true;
2885}
2886
8998576b
DL		 2887struct ip_ttl_word {
2888 __u8 ttl;
2889 __u8 protocol;
2890 __sum16 check;
2891};
2892
2893struct ipv6_hoplimit_word {
2894 __be16 payload_len;
2895 __u8 nexthdr;
2896 __u8 hop_limit;
2897};
2898
4c3844d9
PB		 2899static int is_action_keys_supported(const struct flow_action_entry *act,
2900 bool ct_flow, bool *modify_ip_header,
7e36feeb 2901 bool *modify_tuple,
4c3844d9 2902 struct netlink_ext_ack *extack)
8998576b
DL		 2903{
2904 u32 mask, offset;
2905 u8 htype;
2906
2907 htype = act->mangle.htype;
2908 offset = act->mangle.offset;
2909 mask = ~act->mangle.mask;
2910 /* For IPv4 & IPv6 header check 4 byte word,
2911 * to determine that modified fields
2912 * are NOT ttl & hop_limit only.
2913 */
2914 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2915 struct ip_ttl_word *ttl_word =
2916 (struct ip_ttl_word *)&mask;
2917
2918 if (offset != offsetof(struct iphdr, ttl) ||
2919 ttl_word->protocol ||
2920 ttl_word->check) {
4c3844d9
PB		 2921 *modify_ip_header = true;
2922 }
2923
7e36feeb
PB		 2924 if (offset >= offsetof(struct iphdr, saddr))
2925 *modify_tuple = true;
2926
2927 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 2928 NL_SET_ERR_MSG_MOD(extack,
2929 "can't offload re-write of ipv4 address with action ct");
2930 return -EOPNOTSUPP;
8998576b
DL		 2931 }
2932 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2933 struct ipv6_hoplimit_word *hoplimit_word =
2934 (struct ipv6_hoplimit_word *)&mask;
2935
2936 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2937 hoplimit_word->payload_len ||
2938 hoplimit_word->nexthdr) {
4c3844d9
PB		 2939 *modify_ip_header = true;
2940 }
2941
7e36feeb
PB		 2942 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
2943 *modify_tuple = true;
2944
2945 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 2946 NL_SET_ERR_MSG_MOD(extack,
2947 "can't offload re-write of ipv6 address with action ct");
2948 return -EOPNOTSUPP;
8998576b 2949 }
7e36feeb
PB		 2950 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2951 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
2952 *modify_tuple = true;
2953 if (ct_flow) {
2954 NL_SET_ERR_MSG_MOD(extack,
2955 "can't offload re-write of transport header ports with action ct");
2956 return -EOPNOTSUPP;
2957 }
8998576b 2958 }
4c3844d9
PB		 2959
2960 return 0;
8998576b
DL		 2961}
2962
3d486ec4
OS		 2963static bool modify_header_match_supported(struct mlx5e_priv *priv,
2964 struct mlx5_flow_spec *spec,
73867881 2965 struct flow_action *flow_action,
4c3844d9 2966 u32 actions, bool ct_flow,
7e36feeb 2967 bool ct_clear,
e98bedf5 2968 struct netlink_ext_ack *extack)
bdd66ac0 2969{
73867881 2970 const struct flow_action_entry *act;
7e36feeb 2971 bool modify_ip_header, modify_tuple;
fca53304 2972 void *headers_c;
bdd66ac0
OG		 2973 void *headers_v;
2974 u16 ethertype;
8998576b 2975 u8 ip_proto;
4c3844d9 2976 int i, err;
bdd66ac0 2977
fca53304 2978 headers_c = get_match_headers_criteria(actions, spec);
8377629e 2979 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2980 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2981
2982 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 2983 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
2984 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 2985 goto out_ok;
2986
2987 modify_ip_header = false;
7e36feeb 2988 modify_tuple = false;
73867881
PNA		 2989 flow_action_for_each(i, act, flow_action) {
2990 if (act->id != FLOW_ACTION_MANGLE &&
2991 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2992 continue;
2993
4c3844d9 2994 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 2995 &modify_ip_header,
2996 &modify_tuple, extack);
4c3844d9
PB		 2997 if (err)
2998 return err;
bdd66ac0
OG		 2999 }
3000
7e36feeb
PB		 3001 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3002 * (or after clear action), as otherwise, since the tuple is changed,
3003 * we can't restore ct state
3004 */
3005 if (!ct_clear && modify_tuple &&
89fbdbae 3006 mlx5_tc_ct_add_no_trk_match(spec)) {
7e36feeb
PB		 3007 NL_SET_ERR_MSG_MOD(extack,
3008 "can't offload tuple modify header with ct matches");
3009 netdev_info(priv->netdev,
3010 "can't offload tuple modify header with ct matches");
3011 return false;
3012 }
3013
bdd66ac0 3014 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3015 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3016 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3017 NL_SET_ERR_MSG_MOD(extack,
3018 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3019 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3020 ip_proto);
bdd66ac0
OG		 3021 return false;
3022 }
3023
3024out_ok:
3025 return true;
3026}
3027
3028static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3029 struct flow_action *flow_action,
bdd66ac0 3030 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3031 struct mlx5e_tc_flow *flow,
3032 struct netlink_ext_ack *extack)
bdd66ac0 3033{
a7c119bd 3034 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3035 u32 actions;
3036
c620b772
AL		 3037 ct_clear = flow->attr->ct_attr.ct_action &
3038 TCA_CT_ACT_CLEAR;
3039 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3040 actions = flow->attr->action;
3041
4c3844d9 3042 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3043 if (flow->attr->esw_attr->split_count && ct_flow &&
3044 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3045 /* All registers used by ct are cleared when using
3046 * split rules.
3047 */
3048 NL_SET_ERR_MSG_MOD(extack,
3049 "Can't offload mirroring with action ct");
49397b80 3050 return false;
4c3844d9 3051 }
4c3844d9 3052 }
bdd66ac0
OG		 3053
3054 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3055 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3056 flow_action, actions,
7e36feeb
PB		 3057 ct_flow, ct_clear,
3058 extack);
bdd66ac0
OG		 3059
3060 return true;
3061}
3062
32134847
MD		 3063static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3064{
3065 return priv->mdev == peer_priv->mdev;
3066}
3067
5c65c564
OG		 3068static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3069{
3070 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3071 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3072
3073 fmdev = priv->mdev;
3074 pmdev = peer_priv->mdev;
3075
59c9d35e
AH		 3076 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3077 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3078
816f6706 3079 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3080}
3081
bdc837ee
EB		 3082static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3083 const struct flow_action_entry *act,
3084 struct mlx5e_tc_flow_parse_attr *parse_attr,
3085 struct pedit_headers_action *hdrs,
3086 u32 *action, struct netlink_ext_ack *extack)
3087{
3088 u16 mask16 = VLAN_VID_MASK;
3089 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3090 const struct flow_action_entry pedit_act = {
3091 .id = FLOW_ACTION_MANGLE,
3092 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3093 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3094 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3095 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3096 };
6fca9d1e 3097 u8 match_prio_mask, match_prio_val;
bf2f3bca 3098 void *headers_c, *headers_v;
bdc837ee
EB		 3099 int err;
3100
bf2f3bca
EB		 3101 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3102 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3103
3104 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3105 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3106 NL_SET_ERR_MSG_MOD(extack,
3107 "VLAN rewrite action must have VLAN protocol match");
3108 return -EOPNOTSUPP;
3109 }
3110
6fca9d1e
EB		 3111 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3112 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3113 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3114 NL_SET_ERR_MSG_MOD(extack,
3115 "Changing VLAN prio is not supported");
bdc837ee
EB		 3116 return -EOPNOTSUPP;
3117 }
3118
582234b4 3119 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3120 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3121
3122 return err;
3123}
3124
0bac1194
EB		 3125static int
3126add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3127 struct mlx5e_tc_flow_parse_attr *parse_attr,
3128 struct pedit_headers_action *hdrs,
3129 u32 *action, struct netlink_ext_ack *extack)
3130{
3131 const struct flow_action_entry prio_tag_act = {
3132 .vlan.vid = 0,
3133 .vlan.prio =
3134 MLX5_GET(fte_match_set_lyr_2_4,
3135 get_match_headers_value(*action,
3136 &parse_attr->spec),
3137 first_prio) &
3138 MLX5_GET(fte_match_set_lyr_2_4,
3139 get_match_headers_criteria(*action,
3140 &parse_attr->spec),
3141 first_prio),
3142 };
3143
3144 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3145 &prio_tag_act, parse_attr, hdrs, action,
3146 extack);
3147}
3148
c7569097
AL		 3149static int validate_goto_chain(struct mlx5e_priv *priv,
3150 struct mlx5e_tc_flow *flow,
3151 const struct flow_action_entry *act,
3152 u32 actions,
3153 struct netlink_ext_ack *extack)
3154{
3155 bool is_esw = mlx5e_is_eswitch_flow(flow);
3156 struct mlx5_flow_attr *attr = flow->attr;
3157 bool ft_flow = mlx5e_is_ft_flow(flow);
3158 u32 dest_chain = act->chain_index;
3159 struct mlx5_fs_chains *chains;
3160 struct mlx5_eswitch *esw;
3161 u32 reformat_and_fwd;
3162 u32 max_chain;
3163
3164 esw = priv->mdev->priv.eswitch;
3165 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3166 max_chain = mlx5_chains_get_chain_range(chains);
3167 reformat_and_fwd = is_esw ?
3168 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3169 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3170
3171 if (ft_flow) {
3172 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3173 return -EOPNOTSUPP;
3174 }
3175
3176 if (!mlx5_chains_backwards_supported(chains) &&
3177 dest_chain <= attr->chain) {
3178 NL_SET_ERR_MSG_MOD(extack,
3179 "Goto lower numbered chain isn't supported");
3180 return -EOPNOTSUPP;
3181 }
3182
3183 if (dest_chain > max_chain) {
3184 NL_SET_ERR_MSG_MOD(extack,
3185 "Requested destination chain is out of supported range");
3186 return -EOPNOTSUPP;
3187 }
3188
3189 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3190 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3191 !reformat_and_fwd) {
3192 NL_SET_ERR_MSG_MOD(extack,
3193 "Goto chain is not allowed if action has reformat or decap");
3194 return -EOPNOTSUPP;
3195 }
3196
3197 return 0;
3198}
3199
73867881
PNA		 3200static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3201 struct flow_action *flow_action,
aa0cbbae 3202 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3203 struct mlx5e_tc_flow *flow,
3204 struct netlink_ext_ack *extack)
e3a2b7ed 3205{
c620b772 3206 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3207 struct pedit_headers_action hdrs[2] = {};
3208 const struct flow_action_entry *act;
c620b772 3209 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3210 u32 action = 0;
244cd96a 3211 int err, i;
e3a2b7ed 3212
73867881 3213 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3214 return -EINVAL;
3215
53eca1f3
JK		 3216 if (!flow_action_hw_stats_check(flow_action, extack,
3217 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3218 return -EOPNOTSUPP;
3219
c620b772
AL		 3220 nic_attr = attr->nic_attr;
3221
3222 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3223
73867881
PNA		 3224 flow_action_for_each(i, act, flow_action) {
3225 switch (act->id) {
15fc92ec
TZ		 3226 case FLOW_ACTION_ACCEPT:
3227 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3228 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3229 break;
73867881 3230 case FLOW_ACTION_DROP:
1cab1cd7 3231 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3232 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3233 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3234 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3235 break;
3236 case FLOW_ACTION_MANGLE:
3237 case FLOW_ACTION_ADD:
3238 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3239 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3240 if (err)
3241 return err;
3242
c7569097 3243 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3244 break;
bdc837ee
EB		 3245 case FLOW_ACTION_VLAN_MANGLE:
3246 err = add_vlan_rewrite_action(priv,
3247 MLX5_FLOW_NAMESPACE_KERNEL,
3248 act, parse_attr, hdrs,
3249 &action, extack);
3250 if (err)
3251 return err;
3252
3253 break;
73867881 3254 case FLOW_ACTION_CSUM:
1cab1cd7 3255 if (csum_offload_supported(priv, action,
73867881 3256 act->csum_flags,
e98bedf5 3257 extack))
73867881 3258 break;
26c02749
OG		 3259
3260 return -EOPNOTSUPP;
73867881
PNA		 3261 case FLOW_ACTION_REDIRECT: {
3262 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3263
3264 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3265 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3266 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3267 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3268 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3269 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3270 } else {
e98bedf5
EB		 3271 NL_SET_ERR_MSG_MOD(extack,
3272 "device is not on same HW, can't offload");
5c65c564
OG		 3273 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3274 peer_dev->name);
3275 return -EINVAL;
3276 }
73867881
PNA		 3277 }
3278 break;
3279 case FLOW_ACTION_MARK: {
3280 u32 mark = act->mark;
e3a2b7ed
AV		 3281
3282 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3283 NL_SET_ERR_MSG_MOD(extack,
3284 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3285 return -EINVAL;
3286 }
3287
c620b772 3288 nic_attr->flow_tag = mark;
1cab1cd7 3289 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3290 }
3291 break;
c7569097
AL		 3292 case FLOW_ACTION_GOTO:
3293 err = validate_goto_chain(priv, flow, act, action,
3294 extack);
3295 if (err)
3296 return err;
3297
3298 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3299 attr->dest_chain = act->chain_index;
3300 break;
aedd133d
AL		 3301 case FLOW_ACTION_CT:
3302 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3303 if (err)
3304 return err;
3305
3306 flow_flag_set(flow, CT);
3307 break;
73867881 3308 default:
2cc1cb1d
TZ		 3309 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3310 return -EOPNOTSUPP;
e3a2b7ed 3311 }
e3a2b7ed
AV		 3312 }
3313
c500c86b
PNA		 3314 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3315 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3316 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3317 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3318 if (err)
3319 return err;
27c11b6b
EB		 3320 /* in case all pedit actions are skipped, remove the MOD_HDR
3321 * flag.
3322 */
6ae4a6a5 3323 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3324 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3325 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3326 }
c500c86b
PNA		 3327 }
3328
1cab1cd7 3329 attr->action = action;
c7569097
AL		 3330
3331 if (attr->dest_chain) {
3332 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3333 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3334 return -EOPNOTSUPP;
3335 }
3336 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3337 }
3338
3339 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3340 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3341
73867881 3342 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3343 return -EOPNOTSUPP;
3344
e3a2b7ed
AV		 3345 return 0;
3346}
3347
32134847 3348static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3349 struct net_device *peer_netdev)
3350{
3351 struct mlx5e_priv *peer_priv;
3352
3353 peer_priv = netdev_priv(peer_netdev);
3354
3355 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3356 mlx5e_eswitch_vf_rep(priv->netdev) &&
3357 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3358 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3359}
3360
1482bd3d 3361static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3362 const struct flow_action_entry *act,
1482bd3d
JL		 3363 struct mlx5_esw_flow_attr *attr,
3364 u32 *action)
3365{
cc495188
JL		 3366 u8 vlan_idx = attr->total_vlan;
3367
3368 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3369 return -EOPNOTSUPP;
3370
73867881
PNA		 3371 switch (act->id) {
3372 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3373 if (vlan_idx) {
3374 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3375 MLX5_FS_VLAN_DEPTH))
3376 return -EOPNOTSUPP;
3377
3378 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3379 } else {
3380 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3381 }
73867881
PNA		 3382 break;
3383 case FLOW_ACTION_VLAN_PUSH:
3384 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3385 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3386 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3387 if (!attr->vlan_proto[vlan_idx])
3388 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3389
3390 if (vlan_idx) {
3391 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3392 MLX5_FS_VLAN_DEPTH))
3393 return -EOPNOTSUPP;
3394
3395 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3396 } else {
3397 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3398 (act->vlan.proto != htons(ETH_P_8021Q) ||
3399 act->vlan.prio))
cc495188
JL		 3400 return -EOPNOTSUPP;
3401
3402 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3403 }
73867881
PNA		 3404 break;
3405 default:
bdc837ee 3406 return -EINVAL;
1482bd3d
JL		 3407 }
3408
cc495188
JL		 3409 attr->total_vlan = vlan_idx + 1;
3410
1482bd3d
JL		 3411 return 0;
3412}
3413
d34eb2fc
OG		 3414static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3415 struct net_device *out_dev)
3416{
3417 struct net_device *fdb_out_dev = out_dev;
3418 struct net_device *uplink_upper;
3419
3420 rcu_read_lock();
3421 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3422 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3423 uplink_upper == out_dev) {
3424 fdb_out_dev = uplink_dev;
3425 } else if (netif_is_lag_master(out_dev)) {
3426 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3427 if (fdb_out_dev &&
3428 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3429 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3430 fdb_out_dev = NULL;
3431 }
3432 rcu_read_unlock();
3433 return fdb_out_dev;
3434}
3435
278748a9 3436static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3437 struct mlx5_flow_attr *attr,
278748a9
EB		 3438 struct net_device **out_dev,
3439 u32 *action)
3440{
3441 struct net_device *vlan_dev = *out_dev;
3442 struct flow_action_entry vlan_act = {
3443 .id = FLOW_ACTION_VLAN_PUSH,
3444 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3445 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3446 .vlan.prio = 0,
3447 };
3448 int err;
3449
c620b772 3450 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3451 if (err)
3452 return err;
3453
3454 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3455 dev_get_iflink(vlan_dev));
3456 if (is_vlan_dev(*out_dev))
3457 err = add_vlan_push_action(priv, attr, out_dev, action);
3458
3459 return err;
3460}
3461
35a605db 3462static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3463 struct mlx5_flow_attr *attr,
35a605db
EB		 3464 u32 *action)
3465{
35a605db
EB		 3466 struct flow_action_entry vlan_act = {
3467 .id = FLOW_ACTION_VLAN_POP,
3468 };
70f478ca 3469 int nest_level, err = 0;
35a605db 3470
70f478ca
DL		 3471 nest_level = attr->parse_attr->filter_dev->lower_level -
3472 priv->netdev->lower_level;
35a605db 3473 while (nest_level--) {
c620b772 3474 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3475 if (err)
3476 return err;
3477 }
3478
3479 return err;
3480}
3481
32134847
MD		 3482static bool same_hw_reps(struct mlx5e_priv *priv,
3483 struct net_device *peer_netdev)
3484{
3485 struct mlx5e_priv *peer_priv;
3486
3487 peer_priv = netdev_priv(peer_netdev);
3488
3489 return mlx5e_eswitch_rep(priv->netdev) &&
3490 mlx5e_eswitch_rep(peer_netdev) &&
3491 same_hw_devs(priv, peer_priv);
3492}
3493
3494static bool is_lag_dev(struct mlx5e_priv *priv,
3495 struct net_device *peer_netdev)
3496{
3497 return ((mlx5_lag_is_sriov(priv->mdev) ||
3498 mlx5_lag_is_multipath(priv->mdev)) &&
3499 same_hw_reps(priv, peer_netdev));
3500}
3501
f6dc1264
PB		 3502bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3503 struct net_device *out_dev)
3504{
32134847
MD		 3505 if (is_merged_eswitch_vfs(priv, out_dev))
3506 return true;
3507
3508 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3509 return true;
3510
3511 return mlx5e_eswitch_rep(out_dev) &&
32134847 3512 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3513}
3514
554fe75c
DL		 3515static bool is_duplicated_output_device(struct net_device *dev,
3516 struct net_device *out_dev,
3517 int *ifindexes, int if_count,
3518 struct netlink_ext_ack *extack)
3519{
3520 int i;
3521
3522 for (i = 0; i < if_count; i++) {
3523 if (ifindexes[i] == out_dev->ifindex) {
3524 NL_SET_ERR_MSG_MOD(extack,
3525 "can't duplicate output to same device");
3526 netdev_err(dev, "can't duplicate output to same device: %s\n",
3527 out_dev->name);
3528 return true;
3529 }
3530 }
3531
3532 return false;
3533}
3534
613f53fe
EC		 3535static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3536 struct mlx5e_tc_flow *flow,
3537 struct net_device *out_dev,
3538 struct netlink_ext_ack *extack)
3539{
c620b772 3540 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3541 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3542 struct mlx5e_rep_priv *rep_priv;
3543
3544 /* Forwarding non encapsulated traffic between
3545 * uplink ports is allowed only if
3546 * termination_table_raw_traffic cap is set.
3547 *
c620b772 3548 * Input vport was stored attr->in_rep.
613f53fe
EC		 3549 * In LAG case, *priv* is the private data of
3550 * uplink which may be not the input vport.
3551 */
3552 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3553
3554 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3555 mlx5e_eswitch_uplink_rep(out_dev)))
3556 return 0;
3557
3558 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3559 termination_table_raw_traffic)) {
3560 NL_SET_ERR_MSG_MOD(extack,
3561 "devices are both uplink, can't offload forwarding");
3562 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3563 priv->netdev->name, out_dev->name);
3564 return -EOPNOTSUPP;
3565 } else if (out_dev != rep_priv->netdev) {
3566 NL_SET_ERR_MSG_MOD(extack,
3567 "devices are not the same uplink, can't offload forwarding");
3568 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3569 priv->netdev->name, out_dev->name);
3570 return -EOPNOTSUPP;
3571 }
3572 return 0;
3573}
3574
73867881
PNA		 3575static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3576 struct flow_action *flow_action,
e98bedf5 3577 struct mlx5e_tc_flow *flow,
14e6b038
EC		 3578 struct netlink_ext_ack *extack,
3579 struct net_device *filter_dev)
03a9d11e 3580{
73867881 3581 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3582 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3583 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3584 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3585 const struct ip_tunnel_info *info = NULL;
c620b772 3586 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3587 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3588 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3589 const struct flow_action_entry *act;
c620b772 3590 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 3591 bool encap = false, decap = false;
3592 u32 action = attr->action;
554fe75c 3593 int err, i, if_count = 0;
f828ca6a 3594 bool mpls_push = false;
03a9d11e 3595
73867881 3596 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3597 return -EINVAL;
3598
53eca1f3
JK		 3599 if (!flow_action_hw_stats_check(flow_action, extack,
3600 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3601 return -EOPNOTSUPP;
3602
c620b772
AL		 3603 esw_attr = attr->esw_attr;
3604 parse_attr = attr->parse_attr;
3605
73867881
PNA		 3606 flow_action_for_each(i, act, flow_action) {
3607 switch (act->id) {
3608 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3609 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3610 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3611 break;
f0288210
EC		 3612 case FLOW_ACTION_TRAP:
3613 if (!flow_offload_has_one_action(flow_action)) {
3614 NL_SET_ERR_MSG_MOD(extack,
3615 "action trap is supported as a sole action only");
3616 return -EOPNOTSUPP;
3617 }
3618 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3619 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3620 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3621 break;
f828ca6a
EC		 3622 case FLOW_ACTION_MPLS_PUSH:
3623 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3624 reformat_l2_to_l3_tunnel) ||
3625 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3626 NL_SET_ERR_MSG_MOD(extack,
3627 "mpls push is supported only for mpls_uc protocol");
3628 return -EOPNOTSUPP;
3629 }
3630 mpls_push = true;
3631 break;
14e6b038
EC		 3632 case FLOW_ACTION_MPLS_POP:
3633 /* we only support mpls pop if it is the first action
3634 * and the filter net device is bareudp. Subsequent
3635 * actions can be pedit and the last can be mirred
3636 * egress redirect.
3637 */
3638 if (i) {
3639 NL_SET_ERR_MSG_MOD(extack,
3640 "mpls pop supported only as first action");
3641 return -EOPNOTSUPP;
3642 }
3643 if (!netif_is_bareudp(filter_dev)) {
3644 NL_SET_ERR_MSG_MOD(extack,
3645 "mpls pop supported only on bareudp devices");
3646 return -EOPNOTSUPP;
3647 }
3648
3649 parse_attr->eth.h_proto = act->mpls_pop.proto;
3650 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3651 flow_flag_set(flow, L3_TO_L2_DECAP);
3652 break;
73867881
PNA		 3653 case FLOW_ACTION_MANGLE:
3654 case FLOW_ACTION_ADD:
3655 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3656 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3657 if (err)
3658 return err;
3659
582234b4
EC		 3660 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3661 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3662 esw_attr->split_count = esw_attr->out_count;
582234b4 3663 }
73867881
PNA		 3664 break;
3665 case FLOW_ACTION_CSUM:
1cab1cd7 3666 if (csum_offload_supported(priv, action,
73867881
PNA		 3667 act->csum_flags, extack))
3668 break;
26c02749
OG		 3669
3670 return -EOPNOTSUPP;
73867881
PNA		 3671 case FLOW_ACTION_REDIRECT:
3672 case FLOW_ACTION_MIRRED: {
03a9d11e 3673 struct mlx5e_priv *out_priv;
592d3651 3674 struct net_device *out_dev;
03a9d11e 3675
73867881 3676 out_dev = act->dev;
ef381359
OS		 3677 if (!out_dev) {
3678 /* out_dev is NULL when filters with
3679 * non-existing mirred device are replayed to
3680 * the driver.
3681 */
3682 return -EINVAL;
3683 }
03a9d11e 3684
f828ca6a
EC		 3685 if (mpls_push && !netif_is_bareudp(out_dev)) {
3686 NL_SET_ERR_MSG_MOD(extack,
3687 "mpls is supported only through a bareudp device");
3688 return -EOPNOTSUPP;
3689 }
3690
84179981
PB		 3691 if (ft_flow && out_dev == priv->netdev) {
3692 /* Ignore forward to self rules generated
3693 * by adding both mlx5 devs to the flow table
3694 * block on a normal nft offload setup.
3695 */
3696 return -EOPNOTSUPP;
3697 }
3698
c620b772 3699 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3700 NL_SET_ERR_MSG_MOD(extack,
3701 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3702 netdev_warn(priv->netdev,
3703 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3704 esw_attr->out_count);
592d3651
CM		 3705 return -EOPNOTSUPP;
3706 }
3707
f493f155
EB		 3708 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3709 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3710 if (encap) {
c620b772 3711 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3712 out_dev->ifindex;
0d9f9647
VB		 3713 parse_attr->tun_info[esw_attr->out_count] =
3714 mlx5e_dup_tun_info(info);
c620b772 3715 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3716 return -ENOMEM;
3717 encap = false;
c620b772 3718 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3719 MLX5_ESW_DEST_ENCAP;
c620b772 3720 esw_attr->out_count++;
b6a4ac24
VB		 3721 /* attr->dests[].rep is resolved when we
3722 * handle encap
3723 */
3724 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3725 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3726 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3727
554fe75c
DL		 3728 if (is_duplicated_output_device(priv->netdev,
3729 out_dev,
3730 ifindexes,
3731 if_count,
3732 extack))
3733 return -EOPNOTSUPP;
3734
3735 ifindexes[if_count] = out_dev->ifindex;
3736 if_count++;
3737
d34eb2fc
OG		 3738 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3739 if (!out_dev)
3740 return -ENODEV;
7ba58ba7 3741
278748a9
EB		 3742 if (is_vlan_dev(out_dev)) {
3743 err = add_vlan_push_action(priv, attr,
3744 &out_dev,
3745 &action);
3746 if (err)
3747 return err;
3748 }
f6dc1264 3749
35a605db
EB		 3750 if (is_vlan_dev(parse_attr->filter_dev)) {
3751 err = add_vlan_pop_action(priv, attr,
3752 &action);
3753 if (err)
3754 return err;
3755 }
278748a9 3756
613f53fe
EC		 3757 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3758 if (err)
3759 return err;
ffec9702 3760
f6dc1264
PB		 3761 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3762 NL_SET_ERR_MSG_MOD(extack,
3763 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3764 return -EOPNOTSUPP;
f6dc1264 3765 }
a0646c88 3766
a54e20b4 3767 out_priv = netdev_priv(out_dev);
1d447a39 3768 rpriv = out_priv->ppriv;
c620b772
AL		 3769 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3770 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3771 esw_attr->out_count++;
ef381359
OS		 3772 } else if (parse_attr->filter_dev != priv->netdev) {
3773 /* All mlx5 devices are called to configure
3774 * high level device filters. Therefore, the
3775 * *attempt* to install a filter on invalid
3776 * eswitch should not trigger an explicit error
3777 */
3778 return -EINVAL;
a54e20b4 3779 } else {
e98bedf5
EB		 3780 NL_SET_ERR_MSG_MOD(extack,
3781 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3782 netdev_warn(priv->netdev,
3783 "devices %s %s not on same switch HW, can't offload forwarding\n",
3784 priv->netdev->name,
3785 out_dev->name);
03a9d11e
OG		 3786 return -EINVAL;
3787 }
73867881
PNA		 3788 }
3789 break;
3790 case FLOW_ACTION_TUNNEL_ENCAP:
3791 info = act->tunnel;
a54e20b4
HHZ		 3792 if (info)
3793 encap = true;
3794 else
3795 return -EOPNOTSUPP;
1482bd3d 3796
73867881
PNA		 3797 break;
3798 case FLOW_ACTION_VLAN_PUSH:
3799 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3800 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3801 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3802 /* Replace vlan pop+push with vlan modify */
3803 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3804 err = add_vlan_rewrite_action(priv,
3805 MLX5_FLOW_NAMESPACE_FDB,
3806 act, parse_attr, hdrs,
3807 &action, extack);
3808 } else {
c620b772 3809 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3810 }
1482bd3d
JL		 3811 if (err)
3812 return err;
3813
c620b772 3814 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3815 break;
3816 case FLOW_ACTION_VLAN_MANGLE:
3817 err = add_vlan_rewrite_action(priv,
3818 MLX5_FLOW_NAMESPACE_FDB,
3819 act, parse_attr, hdrs,
3820 &action, extack);
3821 if (err)
3822 return err;
3823
c620b772 3824 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3825 break;
3826 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3827 decap = true;
73867881 3828 break;
2fbbc30d 3829 case FLOW_ACTION_GOTO:
c7569097
AL		 3830 err = validate_goto_chain(priv, flow, act, action,
3831 extack);
2fbbc30d
EC		 3832 if (err)
3833 return err;
bf07aa73 3834
e88afe75 3835 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 3836 attr->dest_chain = act->chain_index;
73867881 3837 break;
4c3844d9 3838 case FLOW_ACTION_CT:
aedd133d 3839 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 3840 if (err)
3841 return err;
3842
3843 flow_flag_set(flow, CT);
69e2916e 3844 esw_attr->split_count = esw_attr->out_count;
4c3844d9 3845 break;
73867881 3846 default:
2cc1cb1d
TZ		 3847 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3848 return -EOPNOTSUPP;
bf07aa73 3849 }
03a9d11e 3850 }
bdd66ac0 3851
a508728a
VB		 3852 /* always set IP version for indirect table handling */
3853 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3854
0bac1194
EB		 3855 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3856 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3857 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3858 * tag rewrite.
3859 */
3860 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3861 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3862 &action, extack);
3863 if (err)
3864 return err;
3865 }
3866
c500c86b
PNA		 3867 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3868 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3869 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3870 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3871 if (err)
3872 return err;
27c11b6b
EB		 3873 /* in case all pedit actions are skipped, remove the MOD_HDR
3874 * flag. we might have set split_count either by pedit or
3875 * pop/push. if there is no pop/push either, reset it too.
3876 */
6ae4a6a5 3877 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3878 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3879 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 3880 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3881 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 3882 esw_attr->split_count = 0;
27c11b6b 3883 }
c500c86b
PNA		 3884 }
3885
1cab1cd7 3886 attr->action = action;
73867881 3887 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3888 return -EOPNOTSUPP;
3889
e88afe75 3890 if (attr->dest_chain) {
0a7fcb78
PB		 3891 if (decap) {
3892 /* It can be supported if we'll create a mapping for
3893 * the tunnel device only (without tunnel), and set
3894 * this tunnel id with this decap flow.
3895 *
3896 * On restore (miss), we'll just set this saved tunnel
3897 * device.
3898 */
3899
3900 NL_SET_ERR_MSG(extack,
3901 "Decap with goto isn't supported");
3902 netdev_warn(priv->netdev,
3903 "Decap with goto isn't supported");
3904 return -EOPNOTSUPP;
3905 }
3906
e88afe75
OG		 3907 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3908 }
3909
ae2741e2
VB		 3910 if (!(attr->action &
3911 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 3912 NL_SET_ERR_MSG_MOD(extack,
3913 "Rule must have at least one forward/drop action");
ae2741e2
VB		 3914 return -EOPNOTSUPP;
3915 }
3916
c620b772 3917 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3918 NL_SET_ERR_MSG_MOD(extack,
3919 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3920 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3921 return -EOPNOTSUPP;
3922 }
3923
31c8eba5 3924 return 0;
03a9d11e
OG		 3925}
3926
226f2ca3 3927static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3928{
226f2ca3 3929 unsigned long __flow_flags = 0;
60bd4af8 3930
226f2ca3
VB		 3931 if (flags & MLX5_TC_FLAG(INGRESS))
3932 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3933 if (flags & MLX5_TC_FLAG(EGRESS))
3934 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3935
226f2ca3
VB		 3936 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3937 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3938 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3939 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3940 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3941 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3942
60bd4af8
OG		 3943 *flow_flags = __flow_flags;
3944}
3945
05866c82
OG		 3946static const struct rhashtable_params tc_ht_params = {
3947 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3948 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3949 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3950 .automatic_shrinking = true,
3951};
3952
226f2ca3
VB		 3953static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3954 unsigned long flags)
05866c82 3955{
655dc3d2
OG		 3956 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3957 struct mlx5e_rep_priv *uplink_rpriv;
3958
226f2ca3 3959 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3960 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3961 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3962 } else /* NIC offload */
655dc3d2 3963 return &priv->fs.tc.ht;
05866c82
OG		 3964}
3965
04de7dda
RD		 3966static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3967{
c620b772
AL		 3968 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3969 struct mlx5_flow_attr *attr = flow->attr;
3970 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3971 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3972 bool act_is_encap = !!(attr->action &
3973 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 3974 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 3975 MLX5_DEVCOM_ESW_OFFLOADS);
3976
10fbb1cd
RD		 3977 if (!esw_paired)
3978 return false;
3979
c620b772
AL		 3980 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
3981 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 3982 (is_rep_ingress || act_is_encap))
3983 return true;
3984
3985 return false;
04de7dda
RD		 3986}
3987
c620b772
AL		 3988struct mlx5_flow_attr *
3989mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
3990{
3991 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
3992 sizeof(struct mlx5_esw_flow_attr) :
3993 sizeof(struct mlx5_nic_flow_attr);
3994 struct mlx5_flow_attr *attr;
3995
3996 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
3997}
3998
a88780a9
RD		 3999static int
4000mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4001 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4002 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4003 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4004{
17091853 4005 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4006 struct mlx5_flow_attr *attr;
3bc4b7bf 4007 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4008 int err = -ENOMEM;
4009 int out_index;
e3a2b7ed 4010
c620b772 4011 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4012 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4013 if (!parse_attr || !flow)
4014 goto err_free;
c620b772
AL		 4015
4016 flow->flags = flow_flags;
4017 flow->cookie = f->cookie;
4018 flow->priv = priv;
4019
4020 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4021 if (!attr)
e3a2b7ed 4022 goto err_free;
ff7ea04a 4023
c620b772 4024 flow->attr = attr;
e3a2b7ed 4025
5a7e5bcb
VB		 4026 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4027 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4028 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4029 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4030 refcount_set(&flow->refcnt, 1);
95435ad7 4031 init_completion(&flow->init_done);
e3a2b7ed 4032
a88780a9
RD		 4033 *__flow = flow;
4034 *__parse_attr = parse_attr;
4035
4036 return 0;
4037
4038err_free:
4039 kfree(flow);
4040 kvfree(parse_attr);
4041 return err;
4042}
4043
c7569097
AL		 4044static void
4045mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4046 struct mlx5e_tc_flow_parse_attr *parse_attr,
4047 struct flow_cls_offload *f)
4048{
4049 attr->parse_attr = parse_attr;
4050 attr->chain = f->common.chain_index;
4051 attr->prio = f->common.prio;
4052}
4053
988ab9c7 4054static void
c620b772 4055mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4056 struct mlx5e_priv *priv,
4057 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4058 struct flow_cls_offload *f,
988ab9c7
TZ		 4059 struct mlx5_eswitch_rep *in_rep,
4060 struct mlx5_core_dev *in_mdev)
4061{
4062 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4063 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4064
c7569097 4065 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4066
4067 esw_attr->in_rep = in_rep;
4068 esw_attr->in_mdev = in_mdev;
4069
4070 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4071 MLX5_COUNTER_SOURCE_ESWITCH)
4072 esw_attr->counter_dev = in_mdev;
4073 else
4074 esw_attr->counter_dev = priv->mdev;
4075}
4076
71129676 4077static struct mlx5e_tc_flow *
04de7dda 4078__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4079 struct flow_cls_offload *f,
226f2ca3 4080 unsigned long flow_flags,
04de7dda
RD		 4081 struct net_device *filter_dev,
4082 struct mlx5_eswitch_rep *in_rep,
71129676 4083 struct mlx5_core_dev *in_mdev)
a88780a9 4084{
f9e30088 4085 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4086 struct netlink_ext_ack *extack = f->common.extack;
4087 struct mlx5e_tc_flow_parse_attr *parse_attr;
4088 struct mlx5e_tc_flow *flow;
4089 int attr_size, err;
e3a2b7ed 4090
226f2ca3 4091 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4092 attr_size = sizeof(struct mlx5_esw_flow_attr);
4093 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4094 &parse_attr, &flow);
4095 if (err)
4096 goto out;
988ab9c7 4097
d11afc26 4098 parse_attr->filter_dev = filter_dev;
c620b772 4099 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4100 priv, parse_attr,
4101 f, in_rep, in_mdev);
4102
54c177ca
OS		 4103 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4104 f, filter_dev);
d11afc26
OS		 4105 if (err)
4106 goto err_free;
a88780a9 4107
7e36feeb 4108 /* actions validation depends on parsing the ct matches first */
aedd133d 4109 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4110 &flow->attr->ct_attr, extack);
a88780a9
RD		 4111 if (err)
4112 goto err_free;
4113
7e36feeb 4114 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4115 if (err)
4116 goto err_free;
4117
7040632d 4118 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4119 complete_all(&flow->init_done);
ef06c9ee
RD		 4120 if (err) {
4121 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4122 goto err_free;
4123
b4a23329 4124 add_unready_flow(flow);
ef06c9ee 4125 }
e3a2b7ed 4126
71129676 4127 return flow;
a88780a9
RD		 4128
4129err_free:
5a7e5bcb 4130 mlx5e_flow_put(priv, flow);
a88780a9 4131out:
71129676 4132 return ERR_PTR(err);
a88780a9
RD		 4133}
4134
f9e30088 4135static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4136 struct mlx5e_tc_flow *flow,
226f2ca3 4137 unsigned long flow_flags)
04de7dda
RD		 4138{
4139 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4140 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4141 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4142 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4143 struct mlx5e_tc_flow_parse_attr *parse_attr;
4144 struct mlx5e_rep_priv *peer_urpriv;
4145 struct mlx5e_tc_flow *peer_flow;
4146 struct mlx5_core_dev *in_mdev;
4147 int err = 0;
4148
4149 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4150 if (!peer_esw)
4151 return -ENODEV;
4152
4153 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4154 peer_priv = netdev_priv(peer_urpriv->netdev);
4155
4156 /* in_mdev is assigned of which the packet originated from.
4157 * So packets redirected to uplink use the same mdev of the
4158 * original flow and packets redirected from uplink use the
4159 * peer mdev.
4160 */
c620b772 4161 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4162 in_mdev = peer_priv->mdev;
4163 else
4164 in_mdev = priv->mdev;
4165
c620b772 4166 parse_attr = flow->attr->parse_attr;
95dc1902 4167 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4168 parse_attr->filter_dev,
c620b772 4169 attr->in_rep, in_mdev);
71129676
JG		 4170 if (IS_ERR(peer_flow)) {
4171 err = PTR_ERR(peer_flow);
04de7dda 4172 goto out;
71129676 4173 }
04de7dda
RD		 4174
4175 flow->peer_flow = peer_flow;
226f2ca3 4176 flow_flag_set(flow, DUP);
04de7dda
RD		 4177 mutex_lock(&esw->offloads.peer_mutex);
4178 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4179 mutex_unlock(&esw->offloads.peer_mutex);
4180
4181out:
4182 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4183 return err;
4184}
4185
4186static int
4187mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4188 struct flow_cls_offload *f,
226f2ca3 4189 unsigned long flow_flags,
04de7dda
RD		 4190 struct net_device *filter_dev,
4191 struct mlx5e_tc_flow **__flow)
4192{
4193 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4194 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4195 struct mlx5_core_dev *in_mdev = priv->mdev;
4196 struct mlx5e_tc_flow *flow;
4197 int err;
4198
71129676
JG		 4199 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4200 in_mdev);
4201 if (IS_ERR(flow))
4202 return PTR_ERR(flow);
04de7dda
RD		 4203
4204 if (is_peer_flow_needed(flow)) {
95dc1902 4205 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4206 if (err) {
4207 mlx5e_tc_del_fdb_flow(priv, flow);
4208 goto out;
4209 }
4210 }
4211
4212 *__flow = flow;
4213
4214 return 0;
4215
4216out:
4217 return err;
4218}
4219
a88780a9
RD		 4220static int
4221mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4222 struct flow_cls_offload *f,
226f2ca3 4223 unsigned long flow_flags,
d11afc26 4224 struct net_device *filter_dev,
a88780a9
RD		 4225 struct mlx5e_tc_flow **__flow)
4226{
f9e30088 4227 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4228 struct netlink_ext_ack *extack = f->common.extack;
4229 struct mlx5e_tc_flow_parse_attr *parse_attr;
4230 struct mlx5e_tc_flow *flow;
4231 int attr_size, err;
4232
c7569097
AL		 4233 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4234 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4235 return -EOPNOTSUPP;
4236 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4237 return -EOPNOTSUPP;
c7569097 4238 }
bf07aa73 4239
226f2ca3 4240 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4241 attr_size = sizeof(struct mlx5_nic_flow_attr);
4242 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4243 &parse_attr, &flow);
4244 if (err)
4245 goto out;
4246
d11afc26 4247 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4248 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4249
54c177ca
OS		 4250 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4251 f, filter_dev);
d11afc26
OS		 4252 if (err)
4253 goto err_free;
4254
aedd133d
AL		 4255 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4256 &flow->attr->ct_attr, extack);
4257 if (err)
4258 goto err_free;
4259
73867881 4260 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4261 if (err)
4262 goto err_free;
4263
4264 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4265 if (err)
4266 goto err_free;
4267
226f2ca3 4268 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4269 *__flow = flow;
4270
4271 return 0;
e3a2b7ed 4272
e3a2b7ed 4273err_free:
8914add2 4274 flow_flag_set(flow, FAILED);
e68e28b4 4275 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4276 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4277out:
4278 return err;
4279}
4280
4281static int
4282mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4283 struct flow_cls_offload *f,
226f2ca3 4284 unsigned long flags,
d11afc26 4285 struct net_device *filter_dev,
a88780a9
RD		 4286 struct mlx5e_tc_flow **flow)
4287{
4288 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4289 unsigned long flow_flags;
a88780a9
RD		 4290 int err;
4291
4292 get_flags(flags, &flow_flags);
4293
bf07aa73
PB		 4294 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4295 return -EOPNOTSUPP;
4296
f6455de0 4297 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4298 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4299 filter_dev, flow);
a88780a9 4300 else
d11afc26
OS		 4301 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4302 filter_dev, flow);
a88780a9
RD		 4303
4304 return err;
4305}
4306
553f9328
VP		 4307static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4308 struct mlx5e_rep_priv *rpriv)
4309{
4310 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4311 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4312 * function is called from NIC mode.
553f9328 4313 */
2fb15e72 4314 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4315}
4316
71d82d2a 4317int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4318 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4319{
4320 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4321 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4322 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4323 struct mlx5e_tc_flow *flow;
4324 int err = 0;
4325
c5d326b2
VB		 4326 rcu_read_lock();
4327 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4328 if (flow) {
553f9328
VP		 4329 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4330 * just return 0.
4331 */
4332 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4333 goto rcu_unlock;
553f9328 4334
a88780a9
RD		 4335 NL_SET_ERR_MSG_MOD(extack,
4336 "flow cookie already exists, ignoring");
4337 netdev_warn_once(priv->netdev,
4338 "flow cookie %lx already exists, ignoring\n",
4339 f->cookie);
0e1c1a2f 4340 err = -EEXIST;
c1aea9e1 4341 goto rcu_unlock;
a88780a9 4342 }
c1aea9e1
VB		 4343rcu_unlock:
4344 rcu_read_unlock();
4345 if (flow)
4346 goto out;
a88780a9 4347
7a978759 4348 trace_mlx5e_configure_flower(f);
d11afc26 4349 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4350 if (err)
4351 goto out;
4352
553f9328
VP		 4353 /* Flow rule offloaded to non-uplink representor sharing tc block,
4354 * set the flow's owner dev.
4355 */
4356 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4357 flow->orig_dev = dev;
4358
c5d326b2 4359 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4360 if (err)
4361 goto err_free;
4362
4363 return 0;
4364
4365err_free:
5a7e5bcb 4366 mlx5e_flow_put(priv, flow);
a88780a9 4367out:
e3a2b7ed
AV		 4368 return err;
4369}
4370
8f8ae895
OG		 4371static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4372{
226f2ca3
VB		 4373 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4374 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4375
226f2ca3
VB		 4376 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4377 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4378}
4379
71d82d2a 4380int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4381 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4382{
d9ee0491 4383 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4384 struct mlx5e_tc_flow *flow;
c5d326b2 4385 int err;
e3a2b7ed 4386
c5d326b2 4387 rcu_read_lock();
ab818362 4388 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4389 if (!flow || !same_flow_direction(flow, flags)) {
4390 err = -EINVAL;
4391 goto errout;
4392 }
e3a2b7ed 4393
c5d326b2
VB		 4394 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4395 * set.
4396 */
4397 if (flow_flag_test_and_set(flow, DELETED)) {
4398 err = -EINVAL;
4399 goto errout;
4400 }
05866c82 4401 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4402 rcu_read_unlock();
e3a2b7ed 4403
7a978759 4404 trace_mlx5e_delete_flower(f);
5a7e5bcb 4405 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4406
4407 return 0;
c5d326b2
VB		 4408
4409errout:
4410 rcu_read_unlock();
4411 return err;
e3a2b7ed
AV		 4412}
4413
71d82d2a 4414int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4415 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4416{
04de7dda 4417 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4418 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4419 struct mlx5_eswitch *peer_esw;
aad7e08d 4420 struct mlx5e_tc_flow *flow;
aad7e08d 4421 struct mlx5_fc *counter;
316d5f72
RD		 4422 u64 lastuse = 0;
4423 u64 packets = 0;
4424 u64 bytes = 0;
5a7e5bcb 4425 int err = 0;
aad7e08d 4426
c5d326b2
VB		 4427 rcu_read_lock();
4428 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4429 tc_ht_params));
4430 rcu_read_unlock();
5a7e5bcb
VB		 4431 if (IS_ERR(flow))
4432 return PTR_ERR(flow);
4433
4434 if (!same_flow_direction(flow, flags)) {
4435 err = -EINVAL;
4436 goto errout;
4437 }
aad7e08d 4438
4c3844d9 4439 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4440 counter = mlx5e_tc_get_counter(flow);
4441 if (!counter)
5a7e5bcb 4442 goto errout;
aad7e08d 4443
316d5f72
RD		 4444 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4445 }
aad7e08d 4446
316d5f72
RD		 4447 /* Under multipath it's possible for one rule to be currently
4448 * un-offloaded while the other rule is offloaded.
4449 */
04de7dda
RD		 4450 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4451 if (!peer_esw)
4452 goto out;
4453
226f2ca3
VB		 4454 if (flow_flag_test(flow, DUP) &&
4455 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4456 u64 bytes2;
4457 u64 packets2;
4458 u64 lastuse2;
4459
4460 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4461 if (!counter)
4462 goto no_peer_counter;
04de7dda
RD		 4463 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4464
4465 bytes += bytes2;
4466 packets += packets2;
4467 lastuse = max_t(u64, lastuse, lastuse2);
4468 }
4469
316d5f72 4470no_peer_counter:
04de7dda 4471 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4472out:
4b61d3e8 4473 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4474 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4475 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4476errout:
4477 mlx5e_flow_put(priv, flow);
4478 return err;
aad7e08d
AV		 4479}
4480
1fe3e316 4481static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4482 struct netlink_ext_ack *extack)
4483{
4484 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4485 struct mlx5_eswitch *esw;
1fe3e316 4486 u32 rate_mbps = 0;
fcb64c0f 4487 u16 vport_num;
fcb64c0f
EC		 4488 int err;
4489
e401a184
EC		 4490 vport_num = rpriv->rep->vport;
4491 if (vport_num >= MLX5_VPORT_ECPF) {
4492 NL_SET_ERR_MSG_MOD(extack,
4493 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4494 return -EOPNOTSUPP;
4495 }
4496
fcb64c0f
EC		 4497 esw = priv->mdev->priv.eswitch;
4498 /* rate is given in bytes/sec.
4499 * First convert to bits/sec and then round to the nearest mbit/secs.
4500 * mbit means million bits.
4501 * Moreover, if rate is non zero we choose to configure to a minimum of
4502 * 1 mbit/sec.
4503 */
1fe3e316
PP		 4504 if (rate) {
4505 rate = (rate * BITS_PER_BYTE) + 500000;
0e22bfb7 4506 rate_mbps = max_t(u64, do_div(rate, 1000000), 1);
1fe3e316
PP		 4507 }
4508
fcb64c0f
EC		 4509 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4510 if (err)
4511 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4512
4513 return err;
4514}
4515
4516static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4517 struct flow_action *flow_action,
4518 struct netlink_ext_ack *extack)
4519{
4520 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4521 const struct flow_action_entry *act;
4522 int err;
4523 int i;
4524
4525 if (!flow_action_has_entries(flow_action)) {
4526 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4527 return -EINVAL;
4528 }
4529
4530 if (!flow_offload_has_one_action(flow_action)) {
4531 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4532 return -EOPNOTSUPP;
4533 }
4534
53eca1f3 4535 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4536 return -EOPNOTSUPP;
4537
fcb64c0f
EC		 4538 flow_action_for_each(i, act, flow_action) {
4539 switch (act->id) {
4540 case FLOW_ACTION_POLICE:
4541 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4542 if (err)
4543 return err;
4544
4545 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4546 break;
4547 default:
4548 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4549 return -EOPNOTSUPP;
4550 }
4551 }
4552
4553 return 0;
4554}
4555
4556int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4557 struct tc_cls_matchall_offload *ma)
4558{
b5f814cc 4559 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4560 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4561
b5f814cc
EC		 4562 if (!mlx5_esw_qos_enabled(esw)) {
4563 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4564 return -EOPNOTSUPP;
4565 }
4566
7b83355f 4567 if (ma->common.prio != 1) {
fcb64c0f
EC		 4568 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4569 return -EINVAL;
4570 }
4571
4572 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4573}
4574
4575int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4576 struct tc_cls_matchall_offload *ma)
4577{
4578 struct netlink_ext_ack *extack = ma->common.extack;
4579
4580 return apply_police_params(priv, 0, extack);
4581}
4582
4583void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4584 struct tc_cls_matchall_offload *ma)
4585{
4586 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4587 struct rtnl_link_stats64 cur_stats;
4588 u64 dbytes;
4589 u64 dpkts;
4590
4591 cur_stats = priv->stats.vf_vport;
4592 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4593 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4594 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4595 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4596 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4597}
4598
4d8fcf21
AH		 4599static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4600 struct mlx5e_priv *peer_priv)
4601{
4602 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4603 struct mlx5e_hairpin_entry *hpe, *tmp;
4604 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4605 u16 peer_vhca_id;
4606 int bkt;
4607
4608 if (!same_hw_devs(priv, peer_priv))
4609 return;
4610
4611 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4612
b32accda 4613 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4614 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4615 if (refcount_inc_not_zero(&hpe->refcnt))
4616 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4617 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4618
4619 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4620 wait_for_completion(&hpe->res_ready);
4621 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4622 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4623
4624 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4625 }
4626}
4627
4628static int mlx5e_tc_netdev_event(struct notifier_block *this,
4629 unsigned long event, void *ptr)
4630{
4631 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4632 struct mlx5e_flow_steering *fs;
4633 struct mlx5e_priv *peer_priv;
4634 struct mlx5e_tc_table *tc;
4635 struct mlx5e_priv *priv;
4636
4637 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4638 event != NETDEV_UNREGISTER ||
4639 ndev->reg_state == NETREG_REGISTERED)
4640 return NOTIFY_DONE;
4641
4642 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4643 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4644 priv = container_of(fs, struct mlx5e_priv, fs);
4645 peer_priv = netdev_priv(ndev);
4646 if (priv == peer_priv ||
4647 !(priv->netdev->features & NETIF_F_HW_TC))
4648 return NOTIFY_DONE;
4649
4650 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4651
4652 return NOTIFY_DONE;
4653}
4654
6a064674
AL		 4655static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4656{
4657 int tc_grp_size, tc_tbl_size;
4658 u32 max_flow_counter;
4659
4660 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4661 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4662
4663 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4664
4665 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4666 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4667
4668 return tc_tbl_size;
4669}
4670
655dc3d2 4671int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4672{
acff797c 4673 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674
AL		 4674 struct mlx5_core_dev *dev = priv->mdev;
4675 struct mlx5_chains_attr attr = {};
4d8fcf21 4676 int err;
e8f887ac 4677
b2fdf3d0 4678 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4679 mutex_init(&tc->t_lock);
b32accda 4680 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4681 hash_init(tc->hairpin_tbl);
11c9c548 4682
4d8fcf21
AH		 4683 err = rhashtable_init(&tc->ht, &tc_ht_params);
4684 if (err)
4685 return err;
4686
9ba33339
RD		 4687 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4688
c7569097
AL		 4689 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4690 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4691 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
4692 attr.max_restore_tag = MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4693 }
6a064674
AL		 4694 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4695 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4696 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
4697 attr.default_ft = priv->fs.vlan.ft.t;
4698
4699 tc->chains = mlx5_chains_create(dev, &attr);
4700 if (IS_ERR(tc->chains)) {
4701 err = PTR_ERR(tc->chains);
4702 goto err_chains;
4703 }
4704
aedd133d
AL		 4705 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
4706 MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4707
4d8fcf21 4708 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4709 err = register_netdevice_notifier_dev_net(priv->netdev,
4710 &tc->netdevice_nb,
4711 &tc->netdevice_nn);
4712 if (err) {
4d8fcf21
AH		 4713 tc->netdevice_nb.notifier_call = NULL;
4714 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4715 goto err_reg;
4d8fcf21
AH		 4716 }
4717
6a064674
AL		 4718 return 0;
4719
4720err_reg:
aedd133d 4721 mlx5_tc_ct_clean(tc->ct);
6a064674
AL		 4722 mlx5_chains_destroy(tc->chains);
4723err_chains:
4724 rhashtable_destroy(&tc->ht);
4d8fcf21 4725 return err;
e8f887ac
AV		 4726}
4727
4728static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4729{
4730 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4731 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4732
961e8979 4733 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4734 kfree(flow);
4735}
4736
655dc3d2 4737void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4738{
acff797c 4739 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4740
4d8fcf21 4741 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4742 unregister_netdevice_notifier_dev_net(priv->netdev,
4743 &tc->netdevice_nb,
4744 &tc->netdevice_nn);
4d8fcf21 4745
b2fdf3d0 4746 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4747 mutex_destroy(&tc->hairpin_tbl_lock);
4748
6a064674 4749 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4750
acff797c 4751 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4752 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4753 tc->t = NULL;
e8f887ac 4754 }
b6fac0b4 4755 mutex_destroy(&tc->t_lock);
6a064674 4756
aedd133d 4757 mlx5_tc_ct_clean(tc->ct);
6a064674 4758 mlx5_chains_destroy(tc->chains);
e8f887ac 4759}
655dc3d2
OG		 4760
4761int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4762{
d7a42ad0 4763 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4764 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4765 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4766 struct mapping_ctx *mapping;
aedd133d
AL		 4767 struct mlx5_eswitch *esw;
4768 struct mlx5e_priv *priv;
4769 int err = 0;
0a7fcb78
PB		 4770
4771 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4772 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4773 priv = netdev_priv(rpriv->netdev);
4774 esw = priv->mdev->priv.eswitch;
0a7fcb78 4775
aedd133d
AL		 4776 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4777 esw_chains(esw),
4778 &esw->offloads.mod_hdr,
4779 MLX5_FLOW_NAMESPACE_FDB);
4c3844d9 4780
0a7fcb78
PB		 4781 mapping = mapping_create(sizeof(struct tunnel_match_key),
4782 TUNNEL_INFO_BITS_MASK, true);
4783 if (IS_ERR(mapping)) {
4784 err = PTR_ERR(mapping);
4785 goto err_tun_mapping;
4786 }
4787 uplink_priv->tunnel_mapping = mapping;
4788
8e404fef
VB		 4789 /* 0xFFF is reserved for stack devices slow path table mark */
4790 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 4791 if (IS_ERR(mapping)) {
4792 err = PTR_ERR(mapping);
4793 goto err_enc_opts_mapping;
4794 }
4795 uplink_priv->tunnel_enc_opts_mapping = mapping;
4796
4797 err = rhashtable_init(tc_ht, &tc_ht_params);
4798 if (err)
4799 goto err_ht_init;
4800
9ba33339
RD		 4801 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4802
8914add2 4803 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4804 if (IS_ERR(uplink_priv->encap)) {
4805 err = PTR_ERR(uplink_priv->encap);
8914add2 4806 goto err_register_fib_notifier;
2b6c3c1e 4807 }
8914add2 4808
2b6c3c1e 4809 return 0;
0a7fcb78 4810
8914add2
VB		 4811err_register_fib_notifier:
4812 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 4813err_ht_init:
4814 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4815err_enc_opts_mapping:
4816 mapping_destroy(uplink_priv->tunnel_mapping);
4817err_tun_mapping:
aedd133d 4818 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 4819 netdev_warn(priv->netdev,
4820 "Failed to initialize tc (eswitch), err: %d", err);
4821 return err;
655dc3d2
OG		 4822}
4823
4824void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4825{
0a7fcb78
PB		 4826 struct mlx5_rep_uplink_priv *uplink_priv;
4827
0a7fcb78 4828 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 4829
8914add2
VB		 4830 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4831 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4832
0a7fcb78
PB		 4833 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4834 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 4835
aedd133d 4836 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 4837}
01252a27 4838
226f2ca3 4839int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4840{
d9ee0491 4841 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4842
4843 return atomic_read(&tc_ht->nelems);
4844}
04de7dda
RD		 4845
4846void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4847{
4848 struct mlx5e_tc_flow *flow, *tmp;
4849
4850 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4851 __mlx5e_tc_del_fdb_peer_flow(flow);
4852}
b4a23329
RD		 4853
4854void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4855{
4856 struct mlx5_rep_uplink_priv *rpriv =
4857 container_of(work, struct mlx5_rep_uplink_priv,
4858 reoffload_flows_work);
4859 struct mlx5e_tc_flow *flow, *tmp;
4860
ad86755b 4861 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4862 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4863 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4864 unready_flow_del(flow);
b4a23329 4865 }
ad86755b 4866 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4867}
e2394a61
VB		 4868
4869static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
4870 struct flow_cls_offload *cls_flower,
4871 unsigned long flags)
4872{
4873 switch (cls_flower->command) {
4874 case FLOW_CLS_REPLACE:
4875 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
4876 flags);
4877 case FLOW_CLS_DESTROY:
4878 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
4879 flags);
4880 case FLOW_CLS_STATS:
4881 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
4882 flags);
4883 default:
4884 return -EOPNOTSUPP;
4885 }
4886}
4887
4888int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4889 void *cb_priv)
4890{
4891 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
4892 struct mlx5e_priv *priv = cb_priv;
4893
4894 switch (type) {
4895 case TC_SETUP_CLSFLOWER:
4896 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
4897 default:
4898 return -EOPNOTSUPP;
4899 }
4900}
c7569097
AL		 4901
4902bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
4903 struct sk_buff *skb)
4904{
4905#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 4906 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 4907 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 4908 struct mlx5e_tc_table *tc = &priv->fs.tc;
c7569097
AL		 4909 struct tc_skb_ext *tc_skb_ext;
4910 int err;
4911
4912 reg_b = be32_to_cpu(cqe->ft_metadata);
4913
4914 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4915
4916 err = mlx5_get_chain_for_tag(nic_chains(priv), chain_tag, &chain);
4917 if (err) {
4918 netdev_dbg(priv->netdev,
4919 "Couldn't find chain for chain tag: %d, err: %d\n",
4920 chain_tag, err);
4921 return false;
4922 }
4923
4924 if (chain) {
4925 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
4926 if (WARN_ON(!tc_skb_ext))
4927 return false;
4928
4929 tc_skb_ext->chain = chain;
aedd133d
AL		 4930
4931 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 4932 ESW_ZONE_ID_MASK;
aedd133d
AL		 4933
4934 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
4935 zone_restore_id))
4936 return false;
c7569097
AL		 4937 }
4938#endif /* CONFIG_NET_TC_SKB_EXT */
4939
4940 return true;
4941}
Ubuntu Jammy Linux kernel mirror