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e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
3f6d08d1 60#include "fs_core.h"
2c81bfd5 61#include "en/port.h"
101f4de9 62#include "en/tc_tun.h"
0a7fcb78 63#include "en/mapping.h"
4c3844d9 64#include "en/tc_ct.h"
b2fdf3d0 65#include "en/mod_hdr.h"
04de7dda 66#include "lib/devcom.h"
9272e3df 67#include "lib/geneve.h"
ae430332 68#include "lib/fs_chains.h"
7a978759 69#include "diag/en_tc_tracepoint.h"
1fe3e316 70#include <asm/div64.h>
e8f887ac 71
6a064674 72#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 73#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
226f2ca3 74#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 75
65ba8fb7 76enum {
226f2ca3
VB		 77 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
78 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
79 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 80 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 81 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
82 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
83 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
84 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
85 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
86 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
87 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 88 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 89 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
14e6b038 90 MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8,
65ba8fb7
OG		 91};
92
e4ad91f2
CM		 93#define MLX5E_TC_MAX_SPLITS 1
94
79baaec7
EB		 95/* Helper struct for accessing a struct containing list_head array.
96 * Containing struct
97 * |- Helper array
98 * [0] Helper item 0
99 * |- list_head item 0
100 * |- index (0)
101 * [1] Helper item 1
102 * |- list_head item 1
103 * |- index (1)
104 * To access the containing struct from one of the list_head items:
105 * 1. Get the helper item from the list_head item using
106 * helper item =
107 * container_of(list_head item, helper struct type, list_head field)
108 * 2. Get the contining struct from the helper item and its index in the array:
109 * containing struct =
110 * container_of(helper item, containing struct type, helper field[index])
111 */
112struct encap_flow_item {
948993f2 113 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 114 struct list_head list;
115 int index;
116};
117
e8f887ac
AV		 118struct mlx5e_tc_flow {
119 struct rhash_head node;
655dc3d2 120 struct mlx5e_priv *priv;
e8f887ac 121 u64 cookie;
226f2ca3 122 unsigned long flags;
e4ad91f2 123 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
14e6b038
EC		 124
125 /* flows sharing the same reformat object - currently mpls decap */
126 struct list_head l3_to_l2_reformat;
127 struct mlx5e_decap_entry *decap_reformat;
128
79baaec7
EB		 129 /* Flow can be associated with multiple encap IDs.
130 * The number of encaps is bounded by the number of supported
131 * destinations.
132 */
133 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 134 struct mlx5e_tc_flow *peer_flow;
b2fdf3d0 135 struct mlx5e_mod_hdr_handle *mh; /* attached mod header instance */
e4f9abbd 136 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 137 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 138 struct list_head peer; /* flows with peer flow */
b4a23329 139 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
553f9328 140 struct net_device *orig_dev; /* netdev adding flow first */
2a1f1768 141 int tmp_efi_index;
6a06c2f7 142 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 143 refcount_t refcnt;
c5d326b2 144 struct rcu_head rcu_head;
95435ad7 145 struct completion init_done;
0a7fcb78 146 int tunnel_id; /* the mapped tunnel id of this flow */
c620b772 147 struct mlx5_flow_attr *attr;
e8f887ac
AV		 148};
149
17091853 150struct mlx5e_tc_flow_parse_attr {
1f6da306 151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 152 struct net_device *filter_dev;
17091853 153 struct mlx5_flow_spec spec;
6ae4a6a5 154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
14e6b038 156 struct ethhdr eth;
17091853
OG		 157};
158
acff797c 159#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 160#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 161
8f1e0b97
PB		 162struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
163 [CHAIN_TO_REG] = {
164 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
165 .moffset = 0,
166 .mlen = 2,
167 },
0a7fcb78
PB		 168 [TUNNEL_TO_REG] = {
169 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521
PB		 170 .moffset = 1,
171 .mlen = 3,
0a7fcb78
PB		 172 .soffset = MLX5_BYTE_OFF(fte_match_param,
173 misc_parameters_2.metadata_reg_c_1),
174 },
4c3844d9 175 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 176 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 177 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
178 [MARK_TO_REG] = mark_to_reg_ct,
179 [LABELS_TO_REG] = labels_to_reg_ct,
180 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 181 /* For NIC rules we store the retore metadata directly
182 * into reg_b that is passed to SW since we don't
183 * jump between steering domains.
184 */
185 [NIC_CHAIN_TO_REG] = {
186 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
187 .moffset = 0,
188 .mlen = 2,
189 },
aedd133d 190 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 191};
192
0a7fcb78
PB		 193static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
194
195void
196mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
197 enum mlx5e_tc_attr_to_reg type,
198 u32 data,
199 u32 mask)
200{
201 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
202 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
203 void *headers_c = spec->match_criteria;
204 void *headers_v = spec->match_value;
205 void *fmask, *fval;
206
207 fmask = headers_c + soffset;
208 fval = headers_v + soffset;
209
58ff18e1
SM		 210 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
211 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 212
213 memcpy(fmask, &mask, match_len);
214 memcpy(fval, &data, match_len);
215
216 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
217}
218
7e36feeb
PB		 219void
220mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
221 enum mlx5e_tc_attr_to_reg type,
222 u32 *data,
223 u32 *mask)
224{
225 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
226 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
227 void *headers_c = spec->match_criteria;
228 void *headers_v = spec->match_value;
229 void *fmask, *fval;
230
231 fmask = headers_c + soffset;
232 fval = headers_v + soffset;
233
234 memcpy(mask, fmask, match_len);
235 memcpy(data, fval, match_len);
236
237 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
238 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
239}
240
0a7fcb78
PB		 241int
242mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
243 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
aedd133d 244 enum mlx5_flow_namespace_type ns,
0a7fcb78
PB		 245 enum mlx5e_tc_attr_to_reg type,
246 u32 data)
247{
248 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
249 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
250 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
251 char *modact;
252 int err;
253
aedd133d 254 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 255 if (err)
256 return err;
257
258 modact = mod_hdr_acts->actions +
259 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
260
261 /* Firmware has 5bit length field and 0 means 32bits */
262 if (mlen == 4)
263 mlen = 0;
264
265 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
266 MLX5_SET(set_action_in, modact, field, mfield);
267 MLX5_SET(set_action_in, modact, offset, moffset * 8);
268 MLX5_SET(set_action_in, modact, length, mlen * 8);
269 MLX5_SET(set_action_in, modact, data, data);
270 mod_hdr_acts->num_actions++;
271
272 return 0;
273}
274
aedd133d
AL		 275static struct mlx5_tc_ct_priv *
276get_ct_priv(struct mlx5e_priv *priv)
277{
278 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
279 struct mlx5_rep_uplink_priv *uplink_priv;
280 struct mlx5e_rep_priv *uplink_rpriv;
281
e8711402 282 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 283 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
284 uplink_priv = &uplink_rpriv->uplink_priv;
285
286 return uplink_priv->ct_priv;
287 }
288
289 return priv->fs.tc.ct;
290}
291
292struct mlx5_flow_handle *
293mlx5_tc_rule_insert(struct mlx5e_priv *priv,
294 struct mlx5_flow_spec *spec,
295 struct mlx5_flow_attr *attr)
296{
297 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
298
e8711402 299 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 300 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
301
302 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
303}
304
305void
306mlx5_tc_rule_delete(struct mlx5e_priv *priv,
307 struct mlx5_flow_handle *rule,
308 struct mlx5_flow_attr *attr)
309{
310 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
311
e8711402 312 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 313 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
314
315 return;
316 }
317
318 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
319}
320
77ab67b7
OG		 321struct mlx5e_hairpin {
322 struct mlx5_hairpin *pair;
323
324 struct mlx5_core_dev *func_mdev;
3f6d08d1 325 struct mlx5e_priv *func_priv;
77ab67b7
OG		 326 u32 tdn;
327 u32 tirn;
3f6d08d1
OG		 328
329 int num_channels;
330 struct mlx5e_rqt indir_rqt;
331 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
332 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 333};
334
5c65c564
OG		 335struct mlx5e_hairpin_entry {
336 /* a node of a hash table which keeps all the hairpin entries */
337 struct hlist_node hairpin_hlist;
338
73edca73
VB		 339 /* protects flows list */
340 spinlock_t flows_lock;
5c65c564
OG		 341 /* flows sharing the same hairpin */
342 struct list_head flows;
db76ca24
VB		 343 /* hpe's that were not fully initialized when dead peer update event
344 * function traversed them.
345 */
346 struct list_head dead_peer_wait_list;
5c65c564 347
d8822868 348 u16 peer_vhca_id;
106be53b 349 u8 prio;
5c65c564 350 struct mlx5e_hairpin *hp;
e4f9abbd 351 refcount_t refcnt;
db76ca24 352 struct completion res_ready;
5c65c564
OG		 353};
354
5a7e5bcb
VB		 355static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
356 struct mlx5e_tc_flow *flow);
357
358static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
359{
360 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
361 return ERR_PTR(-EINVAL);
362 return flow;
363}
364
365static void mlx5e_flow_put(struct mlx5e_priv *priv,
366 struct mlx5e_tc_flow *flow)
367{
368 if (refcount_dec_and_test(&flow->refcnt)) {
369 mlx5e_tc_del_flow(priv, flow);
c5d326b2 370 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 371 }
372}
373
226f2ca3
VB		 374static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
375{
376 /* Complete all memory stores before setting bit. */
377 smp_mb__before_atomic();
378 set_bit(flag, &flow->flags);
379}
380
381#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
382
c5d326b2
VB		 383static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
384 unsigned long flag)
385{
386 /* test_and_set_bit() provides all necessary barriers */
387 return test_and_set_bit(flag, &flow->flags);
388}
389
390#define flow_flag_test_and_set(flow, flag) \
391 __flow_flag_test_and_set(flow, \
392 MLX5E_TC_FLOW_FLAG_##flag)
393
226f2ca3
VB		 394static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
395{
396 /* Complete all memory stores before clearing bit. */
397 smp_mb__before_atomic();
398 clear_bit(flag, &flow->flags);
399}
400
401#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
402 MLX5E_TC_FLOW_FLAG_##flag)
403
404static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
405{
406 bool ret = test_bit(flag, &flow->flags);
407
408 /* Read fields of flow structure only after checking flags. */
409 smp_mb__after_atomic();
410 return ret;
411}
412
413#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
414 MLX5E_TC_FLOW_FLAG_##flag)
415
aedd133d 416bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 417{
418 return flow_flag_test(flow, ESWITCH);
419}
420
84179981
PB		 421static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
422{
423 return flow_flag_test(flow, FT);
424}
425
226f2ca3
VB		 426static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
427{
428 return flow_flag_test(flow, OFFLOADED);
429}
430
b2fdf3d0 431static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 432{
b2fdf3d0
PB		 433 return mlx5e_is_eswitch_flow(flow) ?
434 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 435}
436
dd58edc3 437static struct mod_hdr_tbl *
b2fdf3d0 438get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 439{
440 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
441
b2fdf3d0
PB		 442 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
443 &esw->offloads.mod_hdr :
dd58edc3
VB		 444 &priv->fs.tc.mod_hdr;
445}
446
11c9c548
OG		 447static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
448 struct mlx5e_tc_flow *flow,
449 struct mlx5e_tc_flow_parse_attr *parse_attr)
450{
b2fdf3d0
PB		 451 struct mlx5_modify_hdr *modify_hdr;
452 struct mlx5e_mod_hdr_handle *mh;
11c9c548 453
b2fdf3d0
PB		 454 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
455 get_flow_name_space(flow),
456 &parse_attr->mod_hdr_acts);
457 if (IS_ERR(mh))
458 return PTR_ERR(mh);
11c9c548 459
b2fdf3d0 460 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 461 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 462 flow->mh = mh;
11c9c548
OG		 463
464 return 0;
11c9c548
OG		 465}
466
467static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
468 struct mlx5e_tc_flow *flow)
469{
5a7e5bcb 470 /* flow wasn't fully initialized */
dd58edc3 471 if (!flow->mh)
5a7e5bcb
VB		 472 return;
473
b2fdf3d0
PB		 474 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
475 flow->mh);
dd58edc3 476 flow->mh = NULL;
11c9c548
OG		 477}
478
77ab67b7
OG		 479static
480struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
481{
482 struct net_device *netdev;
483 struct mlx5e_priv *priv;
484
485 netdev = __dev_get_by_index(net, ifindex);
486 priv = netdev_priv(netdev);
487 return priv->mdev;
488}
489
490static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
491{
e0b4b472 492 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 493 void *tirc;
494 int err;
495
496 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
497 if (err)
498 goto alloc_tdn_err;
499
500 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
501
502 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 503 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 504 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
505
e0b4b472 506 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 507 if (err)
508 goto create_tir_err;
509
510 return 0;
511
512create_tir_err:
513 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
514alloc_tdn_err:
515 return err;
516}
517
518static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
519{
520 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
521 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
522}
523
3f6d08d1
OG		 524static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
525{
526 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
527 struct mlx5e_priv *priv = hp->func_priv;
528 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
529
530 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
531 hp->num_channels);
532
533 for (i = 0; i < sz; i++) {
534 ix = i;
bbeb53b8 535 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 536 ix = mlx5e_bits_invert(i, ilog2(sz));
537 ix = indirection_rqt[ix];
538 rqn = hp->pair->rqn[ix];
539 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
540 }
541}
542
543static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
544{
545 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
546 struct mlx5e_priv *priv = hp->func_priv;
547 struct mlx5_core_dev *mdev = priv->mdev;
548 void *rqtc;
549 u32 *in;
550
551 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
552 in = kvzalloc(inlen, GFP_KERNEL);
553 if (!in)
554 return -ENOMEM;
555
556 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
557
558 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
559 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
560
561 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
562
563 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
564 if (!err)
565 hp->indir_rqt.enabled = true;
566
567 kvfree(in);
568 return err;
569}
570
571static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
572{
573 struct mlx5e_priv *priv = hp->func_priv;
574 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
575 int tt, i, err;
576 void *tirc;
577
578 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 579 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
580
3f6d08d1
OG		 581 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
582 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
583
584 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
585 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
586 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 587 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
588
3f6d08d1 589 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 590 &hp->indir_tirn[tt]);
3f6d08d1
OG		 591 if (err) {
592 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
593 goto err_destroy_tirs;
594 }
595 }
596 return 0;
597
598err_destroy_tirs:
599 for (i = 0; i < tt; i++)
600 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
601 return err;
602}
603
604static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
605{
606 int tt;
607
608 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
609 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
610}
611
612static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
613 struct ttc_params *ttc_params)
614{
615 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
616 int tt;
617
618 memset(ttc_params, 0, sizeof(*ttc_params));
619
620 ttc_params->any_tt_tirn = hp->tirn;
621
622 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
623 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
624
6412bb39 625 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 626 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
627 ft_attr->prio = MLX5E_TC_PRIO;
628}
629
630static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
631{
632 struct mlx5e_priv *priv = hp->func_priv;
633 struct ttc_params ttc_params;
634 int err;
635
636 err = mlx5e_hairpin_create_indirect_rqt(hp);
637 if (err)
638 return err;
639
640 err = mlx5e_hairpin_create_indirect_tirs(hp);
641 if (err)
642 goto err_create_indirect_tirs;
643
644 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
645 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
646 if (err)
647 goto err_create_ttc_table;
648
649 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
650 hp->num_channels, hp->ttc.ft.t->id);
651
652 return 0;
653
654err_create_ttc_table:
655 mlx5e_hairpin_destroy_indirect_tirs(hp);
656err_create_indirect_tirs:
657 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
658
659 return err;
660}
661
662static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
663{
664 struct mlx5e_priv *priv = hp->func_priv;
665
666 mlx5e_destroy_ttc_table(priv, &hp->ttc);
667 mlx5e_hairpin_destroy_indirect_tirs(hp);
668 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
669}
670
77ab67b7
OG		 671static struct mlx5e_hairpin *
672mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
673 int peer_ifindex)
674{
675 struct mlx5_core_dev *func_mdev, *peer_mdev;
676 struct mlx5e_hairpin *hp;
677 struct mlx5_hairpin *pair;
678 int err;
679
680 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
681 if (!hp)
682 return ERR_PTR(-ENOMEM);
683
684 func_mdev = priv->mdev;
685 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
686
687 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
688 if (IS_ERR(pair)) {
689 err = PTR_ERR(pair);
690 goto create_pair_err;
691 }
692 hp->pair = pair;
693 hp->func_mdev = func_mdev;
3f6d08d1
OG		 694 hp->func_priv = priv;
695 hp->num_channels = params->num_channels;
77ab67b7
OG		 696
697 err = mlx5e_hairpin_create_transport(hp);
698 if (err)
699 goto create_transport_err;
700
3f6d08d1
OG		 701 if (hp->num_channels > 1) {
702 err = mlx5e_hairpin_rss_init(hp);
703 if (err)
704 goto rss_init_err;
705 }
706
77ab67b7
OG		 707 return hp;
708
3f6d08d1
OG		 709rss_init_err:
710 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 711create_transport_err:
712 mlx5_core_hairpin_destroy(hp->pair);
713create_pair_err:
714 kfree(hp);
715 return ERR_PTR(err);
716}
717
718static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
719{
3f6d08d1
OG		 720 if (hp->num_channels > 1)
721 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 722 mlx5e_hairpin_destroy_transport(hp);
723 mlx5_core_hairpin_destroy(hp->pair);
724 kvfree(hp);
725}
726
106be53b
OG		 727static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
728{
729 return (peer_vhca_id << 16 | prio);
730}
731
5c65c564 732static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 733 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 734{
735 struct mlx5e_hairpin_entry *hpe;
106be53b 736 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 737
738 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 739 hairpin_hlist, hash_key) {
e4f9abbd
VB		 740 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
741 refcount_inc(&hpe->refcnt);
5c65c564 742 return hpe;
e4f9abbd 743 }
5c65c564
OG		 744 }
745
746 return NULL;
747}
748
e4f9abbd
VB		 749static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
750 struct mlx5e_hairpin_entry *hpe)
751{
752 /* no more hairpin flows for us, release the hairpin pair */
b32accda 753 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 754 return;
b32accda
VB		 755 hash_del(&hpe->hairpin_hlist);
756 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 757
db76ca24
VB		 758 if (!IS_ERR_OR_NULL(hpe->hp)) {
759 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
760 dev_name(hpe->hp->pair->peer_mdev->device));
761
762 mlx5e_hairpin_destroy(hpe->hp);
763 }
e4f9abbd
VB		 764
765 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 766 kfree(hpe);
767}
768
106be53b
OG		 769#define UNKNOWN_MATCH_PRIO 8
770
771static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 772 struct mlx5_flow_spec *spec, u8 *match_prio,
773 struct netlink_ext_ack *extack)
106be53b
OG		 774{
775 void *headers_c, *headers_v;
776 u8 prio_val, prio_mask = 0;
777 bool vlan_present;
778
779#ifdef CONFIG_MLX5_CORE_EN_DCB
780 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 781 NL_SET_ERR_MSG_MOD(extack,
782 "only PCP trust state supported for hairpin");
106be53b
OG		 783 return -EOPNOTSUPP;
784 }
785#endif
786 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
787 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
788
789 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
790 if (vlan_present) {
791 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
792 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
793 }
794
795 if (!vlan_present || !prio_mask) {
796 prio_val = UNKNOWN_MATCH_PRIO;
797 } else if (prio_mask != 0x7) {
e98bedf5
EB		 798 NL_SET_ERR_MSG_MOD(extack,
799 "masked priority match not supported for hairpin");
106be53b
OG		 800 return -EOPNOTSUPP;
801 }
802
803 *match_prio = prio_val;
804 return 0;
805}
806
5c65c564
OG		 807static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
808 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 809 struct mlx5e_tc_flow_parse_attr *parse_attr,
810 struct netlink_ext_ack *extack)
5c65c564 811{
98b66cb1 812 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 813 struct mlx5_hairpin_params params;
d8822868 814 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 815 struct mlx5e_hairpin_entry *hpe;
816 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 817 u64 link_speed64;
818 u32 link_speed;
106be53b 819 u8 match_prio;
d8822868 820 u16 peer_id;
5c65c564
OG		 821 int err;
822
d8822868
OG		 823 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
824 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 825 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 826 return -EOPNOTSUPP;
827 }
828
d8822868 829 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 830 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
831 extack);
106be53b
OG		 832 if (err)
833 return err;
b32accda
VB		 834
835 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 836 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 837 if (hpe) {
838 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
839 wait_for_completion(&hpe->res_ready);
840
841 if (IS_ERR(hpe->hp)) {
842 err = -EREMOTEIO;
843 goto out_err;
844 }
5c65c564 845 goto attach_flow;
db76ca24 846 }
5c65c564
OG		 847
848 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 849 if (!hpe) {
db76ca24
VB		 850 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
851 return -ENOMEM;
b32accda 852 }
5c65c564 853
73edca73 854 spin_lock_init(&hpe->flows_lock);
5c65c564 855 INIT_LIST_HEAD(&hpe->flows);
db76ca24 856 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 857 hpe->peer_vhca_id = peer_id;
106be53b 858 hpe->prio = match_prio;
e4f9abbd 859 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 860 init_completion(&hpe->res_ready);
861
862 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
863 hash_hairpin_info(peer_id, match_prio));
864 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 865
866 params.log_data_size = 15;
867 params.log_data_size = min_t(u8, params.log_data_size,
868 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
869 params.log_data_size = max_t(u8, params.log_data_size,
870 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 871
eb9180f7
OG		 872 params.log_num_packets = params.log_data_size -
873 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
874 params.log_num_packets = min_t(u8, params.log_num_packets,
875 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
876
877 params.q_counter = priv->q_counter;
3f6d08d1 878 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 879 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 880 link_speed = max_t(u32, link_speed, 50000);
881 link_speed64 = link_speed;
882 do_div(link_speed64, 50000);
883 params.num_channels = link_speed64;
884
5c65c564 885 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 886 hpe->hp = hp;
887 complete_all(&hpe->res_ready);
5c65c564
OG		 888 if (IS_ERR(hp)) {
889 err = PTR_ERR(hp);
db76ca24 890 goto out_err;
5c65c564
OG		 891 }
892
eb9180f7 893 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 894 hp->tirn, hp->pair->rqn[0],
895 dev_name(hp->pair->peer_mdev->device),
eb9180f7 896 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 897
5c65c564 898attach_flow:
3f6d08d1 899 if (hpe->hp->num_channels > 1) {
226f2ca3 900 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 901 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 902 } else {
c620b772 903 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 904 }
b32accda 905
e4f9abbd 906 flow->hpe = hpe;
73edca73 907 spin_lock(&hpe->flows_lock);
5c65c564 908 list_add(&flow->hairpin, &hpe->flows);
73edca73 909 spin_unlock(&hpe->flows_lock);
3f6d08d1 910
5c65c564
OG		 911 return 0;
912
db76ca24
VB		 913out_err:
914 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 915 return err;
916}
917
918static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
919 struct mlx5e_tc_flow *flow)
920{
5a7e5bcb 921 /* flow wasn't fully initialized */
e4f9abbd 922 if (!flow->hpe)
5a7e5bcb
VB		 923 return;
924
73edca73 925 spin_lock(&flow->hpe->flows_lock);
5c65c564 926 list_del(&flow->hairpin);
73edca73
VB		 927 spin_unlock(&flow->hpe->flows_lock);
928
e4f9abbd
VB		 929 mlx5e_hairpin_put(priv, flow->hpe);
930 flow->hpe = NULL;
5c65c564
OG		 931}
932
08247066
AL		 933struct mlx5_flow_handle *
934mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
935 struct mlx5_flow_spec *spec,
c620b772 936 struct mlx5_flow_attr *attr)
e8f887ac 937{
08247066 938 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 939 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 940 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 941 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 942 struct mlx5_flow_destination dest[2] = {};
66958ed9 943 struct mlx5_flow_act flow_act = {
3bc4b7bf 944 .action = attr->action,
bb0ee7dc 945 .flags = FLOW_ACT_NO_APPEND,
66958ed9 946 };
08247066 947 struct mlx5_flow_handle *rule;
c7569097 948 struct mlx5_flow_table *ft;
08247066 949 int dest_ix = 0;
e8f887ac 950
bb0ee7dc 951 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 952 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 953
aedd133d
AL		 954 if (attr->dest_ft) {
955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
956 dest[dest_ix].ft = attr->dest_ft;
957 dest_ix++;
958 } else if (nic_attr->hairpin_ft) {
08247066 959 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 960 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 961 dest_ix++;
c620b772 962 } else if (nic_attr->hairpin_tirn) {
08247066 963 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 964 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 965 dest_ix++;
3f6d08d1
OG		 966 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
967 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 968 if (attr->dest_chain) {
969 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
970 attr->dest_chain, 1,
971 MLX5E_TC_FT_LEVEL);
972 if (IS_ERR(dest[dest_ix].ft))
973 return ERR_CAST(dest[dest_ix].ft);
974 } else {
975 dest[dest_ix].ft = priv->fs.vlan.ft.t;
976 }
3f6d08d1 977 dest_ix++;
5c65c564 978 }
aad7e08d 979
c7569097
AL		 980 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
981 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
982 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
983
08247066 984 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 985 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 986 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 987 dest_ix++;
aad7e08d
AV		 988 }
989
08247066 990 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 991 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 992
6a064674
AL		 993 mutex_lock(&tc->t_lock);
994 if (IS_ERR_OR_NULL(tc->t)) {
995 /* Create the root table here if doesn't exist yet */
996 tc->t =
c7569097 997 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 998
999 if (IS_ERR(tc->t)) {
1000 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 1001 netdev_err(priv->netdev,
1002 "Failed to create tc offload table\n");
c7569097
AL		 1003 rule = ERR_CAST(priv->fs.tc.t);
1004 goto err_ft_get;
e8f887ac 1005 }
e8f887ac 1006 }
08247066 1007 mutex_unlock(&tc->t_lock);
e8f887ac 1008
aedd133d
AL		 1009 if (attr->chain || attr->prio)
1010 ft = mlx5_chains_get_table(nic_chains,
1011 attr->chain, attr->prio,
1012 MLX5E_TC_FT_LEVEL);
1013 else
1014 ft = attr->ft;
1015
c7569097
AL		 1016 if (IS_ERR(ft)) {
1017 rule = ERR_CAST(ft);
1018 goto err_ft_get;
1019 }
1020
c620b772 1021 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1022 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1023
c7569097 1024 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1025 &flow_act, dest, dest_ix);
1026 if (IS_ERR(rule))
c7569097 1027 goto err_rule;
08247066
AL		 1028
1029 return rule;
c7569097
AL		 1030
1031err_rule:
aedd133d
AL		 1032 if (attr->chain || attr->prio)
1033 mlx5_chains_put_table(nic_chains,
1034 attr->chain, attr->prio,
1035 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1036err_ft_get:
1037 if (attr->dest_chain)
1038 mlx5_chains_put_table(nic_chains,
1039 attr->dest_chain, 1,
1040 MLX5E_TC_FT_LEVEL);
1041
1042 return ERR_CAST(rule);
08247066
AL		 1043}
1044
1045static int
1046mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1047 struct mlx5e_tc_flow_parse_attr *parse_attr,
1048 struct mlx5e_tc_flow *flow,
1049 struct netlink_ext_ack *extack)
1050{
c620b772 1051 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1052 struct mlx5_core_dev *dev = priv->mdev;
1053 struct mlx5_fc *counter = NULL;
1054 int err;
1055
1056 if (flow_flag_test(flow, HAIRPIN)) {
1057 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1058 if (err)
1059 return err;
1060 }
1061
1062 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1063 counter = mlx5_fc_create(dev, true);
1064 if (IS_ERR(counter))
1065 return PTR_ERR(counter);
1066
1067 attr->counter = counter;
1068 }
1069
1070 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1071 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1072 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1073 if (err)
1074 return err;
1075 }
1076
aedd133d
AL		 1077 if (flow_flag_test(flow, CT))
1078 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1079 attr, &parse_attr->mod_hdr_acts);
1080 else
1081 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1082 attr);
aad7e08d 1083
a2b7189b 1084 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1085}
1086
08247066 1087void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1088 struct mlx5_flow_handle *rule,
1089 struct mlx5_flow_attr *attr)
08247066 1090{
c7569097
AL		 1091 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1092
08247066 1093 mlx5_del_flow_rules(rule);
c7569097 1094
aedd133d
AL		 1095 if (attr->chain || attr->prio)
1096 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1097 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1098
1099 if (attr->dest_chain)
1100 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1101 MLX5E_TC_FT_LEVEL);
08247066
AL		 1102}
1103
d85cdccb
OG		 1104static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1105 struct mlx5e_tc_flow *flow)
1106{
c620b772 1107 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1108 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1109
c7569097
AL		 1110 flow_flag_clear(flow, OFFLOADED);
1111
aedd133d
AL		 1112 if (flow_flag_test(flow, CT))
1113 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1114 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1115 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1116
c7569097
AL		 1117 /* Remove root table if no rules are left to avoid
1118 * extra steering hops.
1119 */
b6fac0b4 1120 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1121 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1122 !IS_ERR_OR_NULL(tc->t)) {
1123 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1124 priv->fs.tc.t = NULL;
1125 }
b6fac0b4 1126 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1127
aedd133d
AL		 1128 kvfree(attr->parse_attr);
1129
513f8f7f 1130 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1131 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1132
aedd133d
AL		 1133 mlx5_fc_destroy(priv->mdev, attr->counter);
1134
226f2ca3 1135 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1136 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1137
1138 kfree(flow->attr);
d85cdccb
OG		 1139}
1140
aa0cbbae 1141static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1142 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1143
3c37745e 1144static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1145 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1146 struct net_device *mirred_dev,
1147 int out_index,
8c4dc42b 1148 struct netlink_ext_ack *extack,
0ad060ee
RD		 1149 struct net_device **encap_dev,
1150 bool *encap_valid);
14e6b038
EC		 1151static int mlx5e_attach_decap(struct mlx5e_priv *priv,
1152 struct mlx5e_tc_flow *flow,
1153 struct netlink_ext_ack *extack);
1154static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1155 struct mlx5e_tc_flow *flow);
3c37745e 1156
6d2a3ed0
OG		 1157static struct mlx5_flow_handle *
1158mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1159 struct mlx5e_tc_flow *flow,
1160 struct mlx5_flow_spec *spec,
c620b772 1161 struct mlx5_flow_attr *attr)
6d2a3ed0 1162{
1ef3018f 1163 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1164 struct mlx5_flow_handle *rule;
4c3844d9 1165
1ef3018f
PB		 1166 if (flow_flag_test(flow, CT)) {
1167 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1168
aedd133d
AL		 1169 return mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
1170 flow, spec, attr,
1ef3018f
PB		 1171 mod_hdr_acts);
1172 }
6d2a3ed0
OG		 1173
1174 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1175 if (IS_ERR(rule))
1176 return rule;
1177
c620b772 1178 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1179 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1180 if (IS_ERR(flow->rule[1])) {
1181 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1182 return flow->rule[1];
1183 }
1184 }
1185
6d2a3ed0
OG		 1186 return rule;
1187}
1188
1189static void
1190mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1191 struct mlx5e_tc_flow *flow,
c620b772 1192 struct mlx5_flow_attr *attr)
6d2a3ed0 1193{
226f2ca3 1194 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1195
4c3844d9 1196 if (flow_flag_test(flow, CT)) {
aedd133d 1197 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1198 return;
1199 }
1200
c620b772 1201 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1202 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1203
1204 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1205}
1206
5dbe906f
PB		 1207static struct mlx5_flow_handle *
1208mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1209 struct mlx5e_tc_flow *flow,
178f69b4 1210 struct mlx5_flow_spec *spec)
5dbe906f 1211{
c620b772 1212 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1213 struct mlx5_flow_handle *rule;
1214
c620b772
AL		 1215 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1216 if (!slow_attr)
1217 return ERR_PTR(-ENOMEM);
5dbe906f 1218
c620b772
AL		 1219 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1220 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1221 slow_attr->esw_attr->split_count = 0;
1222 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1223
1224 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1225 if (!IS_ERR(rule))
226f2ca3 1226 flow_flag_set(flow, SLOW);
5dbe906f 1227
c620b772
AL		 1228 kfree(slow_attr);
1229
5dbe906f
PB		 1230 return rule;
1231}
1232
1233static void
1234mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1235 struct mlx5e_tc_flow *flow)
5dbe906f 1236{
c620b772 1237 struct mlx5_flow_attr *slow_attr;
178f69b4 1238
c620b772 1239 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1240 if (!slow_attr) {
1241 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1242 return;
1243 }
c620b772
AL		 1244
1245 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1246 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1247 slow_attr->esw_attr->split_count = 0;
1248 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1249 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1250 flow_flag_clear(flow, SLOW);
c620b772 1251 kfree(slow_attr);
5dbe906f
PB		 1252}
1253
ad86755b
VB		 1254/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1255 * function.
1256 */
1257static void unready_flow_add(struct mlx5e_tc_flow *flow,
1258 struct list_head *unready_flows)
1259{
1260 flow_flag_set(flow, NOT_READY);
1261 list_add_tail(&flow->unready, unready_flows);
1262}
1263
1264/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1265 * function.
1266 */
1267static void unready_flow_del(struct mlx5e_tc_flow *flow)
1268{
1269 list_del(&flow->unready);
1270 flow_flag_clear(flow, NOT_READY);
1271}
1272
b4a23329
RD		 1273static void add_unready_flow(struct mlx5e_tc_flow *flow)
1274{
1275 struct mlx5_rep_uplink_priv *uplink_priv;
1276 struct mlx5e_rep_priv *rpriv;
1277 struct mlx5_eswitch *esw;
1278
1279 esw = flow->priv->mdev->priv.eswitch;
1280 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1281 uplink_priv = &rpriv->uplink_priv;
1282
ad86755b
VB		 1283 mutex_lock(&uplink_priv->unready_flows_lock);
1284 unready_flow_add(flow, &uplink_priv->unready_flows);
1285 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1286}
1287
1288static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1289{
ad86755b
VB		 1290 struct mlx5_rep_uplink_priv *uplink_priv;
1291 struct mlx5e_rep_priv *rpriv;
1292 struct mlx5_eswitch *esw;
1293
1294 esw = flow->priv->mdev->priv.eswitch;
1295 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1296 uplink_priv = &rpriv->uplink_priv;
1297
1298 mutex_lock(&uplink_priv->unready_flows_lock);
1299 unready_flow_del(flow);
1300 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1301}
1302
c83954ab 1303static int
74491de9 1304mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1305 struct mlx5e_tc_flow *flow,
1306 struct netlink_ext_ack *extack)
adb4c123
OG		 1307{
1308 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1309 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1310 struct mlx5e_tc_flow_parse_attr *parse_attr;
1311 struct mlx5_flow_attr *attr = flow->attr;
1312 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1313 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1314 struct mlx5e_rep_priv *rpriv;
1315 struct mlx5e_priv *out_priv;
0ad060ee 1316 bool encap_valid = true;
39ac237c 1317 u32 max_prio, max_chain;
0ad060ee 1318 int err = 0;
f493f155 1319 int out_index;
8b32580d 1320
ae430332 1321 if (!mlx5_chains_prios_supported(esw_chains(esw)) && attr->prio != 1) {
61644c3d
RD		 1322 NL_SET_ERR_MSG_MOD(extack,
1323 "E-switch priorities unsupported, upgrade FW");
d14f6f2a
OG		 1324 return -EOPNOTSUPP;
1325 }
bf07aa73 1326
84179981
PB		 1327 /* We check chain range only for tc flows.
1328 * For ft flows, we checked attr->chain was originally 0 and set it to
1329 * FDB_FT_CHAIN which is outside tc range.
1330 * See mlx5e_rep_setup_ft_cb().
1331 */
ae430332 1332 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1333 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1334 NL_SET_ERR_MSG_MOD(extack,
1335 "Requested chain is out of supported range");
5a7e5bcb 1336 return -EOPNOTSUPP;
bf07aa73
PB		 1337 }
1338
ae430332 1339 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1340 if (attr->prio > max_prio) {
61644c3d
RD		 1341 NL_SET_ERR_MSG_MOD(extack,
1342 "Requested priority is out of supported range");
5a7e5bcb 1343 return -EOPNOTSUPP;
bf07aa73 1344 }
e52c2802 1345
14e6b038
EC		 1346 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1347 err = mlx5e_attach_decap(priv, flow, extack);
1348 if (err)
1349 return err;
1350 }
1351
c620b772
AL		 1352 parse_attr = attr->parse_attr;
1353 esw_attr = attr->esw_attr;
1354
f493f155 1355 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1356 int mirred_ifindex;
1357
c620b772 1358 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1359 continue;
1360
7040632d 1361 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1362 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1363 mirred_ifindex);
733d4f36 1364 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1365 extack, &encap_dev, &encap_valid);
1366 if (err)
5a7e5bcb 1367 return err;
0ad060ee 1368
3c37745e
OG		 1369 out_priv = netdev_priv(encap_dev);
1370 rpriv = out_priv->ppriv;
c620b772
AL		 1371 esw_attr->dests[out_index].rep = rpriv->rep;
1372 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1373 }
1374
8b32580d 1375 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1376 if (err)
5a7e5bcb 1377 return err;
adb4c123 1378
d5a3c2b6
RD		 1379 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1380 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1a9527bb 1381 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1382 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1383 if (err)
5a7e5bcb 1384 return err;
d7e75a32
OG		 1385 }
1386
b8aee822 1387 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1388 counter = mlx5_fc_create(esw_attr->counter_dev, true);
5a7e5bcb
VB		 1389 if (IS_ERR(counter))
1390 return PTR_ERR(counter);
b8aee822
MB		 1391
1392 attr->counter = counter;
1393 }
1394
0ad060ee
RD		 1395 /* we get here if one of the following takes place:
1396 * (1) there's no error
1397 * (2) there's an encap action and we don't have valid neigh
3c37745e 1398 */
bc1d75fa 1399 if (!encap_valid)
178f69b4 1400 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1401 else
6d2a3ed0 1402 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1403
5a7e5bcb
VB		 1404 if (IS_ERR(flow->rule[0]))
1405 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1406 else
1407 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1408
1409 return 0;
aa0cbbae 1410}
d85cdccb 1411
9272e3df
YK		 1412static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1413{
c620b772 1414 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1415 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1416 spec->match_value,
1417 misc_parameters_3);
1418 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1419 headers_v,
1420 geneve_tlv_option_0_data);
1421
1422 return !!geneve_tlv_opt_0_data;
1423}
1424
d85cdccb
OG		 1425static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1426 struct mlx5e_tc_flow *flow)
1427{
1428 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1429 struct mlx5_flow_attr *attr = flow->attr;
f493f155 1430 int out_index;
d85cdccb 1431
0a7fcb78
PB		 1432 mlx5e_put_flow_tunnel_id(flow);
1433
12a240a4 1434 if (flow_flag_test(flow, NOT_READY))
b4a23329 1435 remove_unready_flow(flow);
ef06c9ee 1436
226f2ca3
VB		 1437 if (mlx5e_is_offloaded_flow(flow)) {
1438 if (flow_flag_test(flow, SLOW))
178f69b4 1439 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1440 else
1441 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1442 }
d85cdccb 1443
9272e3df
YK		 1444 if (mlx5_flow_has_geneve_opt(flow))
1445 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1446
513f8f7f 1447 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1448
f493f155 1449 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
c620b772 1450 if (attr->esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1451 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1452 kfree(attr->parse_attr->tun_info[out_index]);
1453 }
f493f155 1454 kvfree(attr->parse_attr);
d7e75a32 1455
aedd133d 1456 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1457
513f8f7f 1458 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1459 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1460
1461 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
c620b772 1462 mlx5_fc_destroy(attr->esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1463
1464 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1465 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1466
1467 kfree(flow->attr);
d85cdccb
OG		 1468}
1469
232c0013 1470void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1471 struct mlx5e_encap_entry *e,
1472 struct list_head *flow_list)
232c0013 1473{
3c37745e 1474 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1475 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0 1476 struct mlx5_flow_handle *rule;
c620b772 1477 struct mlx5_flow_attr *attr;
6d2a3ed0 1478 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1479 struct mlx5e_tc_flow *flow;
1480 int err;
1481
2b688ea5
MG		 1482 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1483 e->reformat_type,
1484 e->encap_size, e->encap_header,
1485 MLX5_FLOW_NAMESPACE_FDB);
1486 if (IS_ERR(e->pkt_reformat)) {
1487 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1488 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1489 return;
1490 }
1491 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1492 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1493
2a1f1768 1494 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1495 bool all_flow_encaps_valid = true;
1496 int i;
1497
95435ad7
VB		 1498 if (!mlx5e_is_offloaded_flow(flow))
1499 continue;
c620b772
AL		 1500 attr = flow->attr;
1501 esw_attr = attr->esw_attr;
1502 spec = &attr->parse_attr->spec;
6d2a3ed0 1503
2b688ea5 1504 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1505 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1506 /* Flow can be associated with multiple encap entries.
1507 * Before offloading the flow verify that all of them have
1508 * a valid neighbour.
1509 */
1510 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1511 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1512 continue;
1513 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1514 all_flow_encaps_valid = false;
1515 break;
1516 }
1517 }
1518 /* Do not offload flows with unresolved neighbors */
1519 if (!all_flow_encaps_valid)
2a1f1768 1520 continue;
5dbe906f 1521 /* update from slow path rule to encap rule */
c620b772 1522 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, attr);
6d2a3ed0
OG		 1523 if (IS_ERR(rule)) {
1524 err = PTR_ERR(rule);
232c0013
HHZ		 1525 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1526 err);
2a1f1768 1527 continue;
232c0013 1528 }
5dbe906f 1529
178f69b4 1530 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1531 flow->rule[0] = rule;
226f2ca3
VB		 1532 /* was unset when slow path rule removed */
1533 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1534 }
1535}
1536
1537void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1538 struct mlx5e_encap_entry *e,
1539 struct list_head *flow_list)
232c0013 1540{
3c37745e 1541 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1542 struct mlx5_esw_flow_attr *esw_attr;
5dbe906f 1543 struct mlx5_flow_handle *rule;
c620b772 1544 struct mlx5_flow_attr *attr;
5dbe906f 1545 struct mlx5_flow_spec *spec;
232c0013 1546 struct mlx5e_tc_flow *flow;
5dbe906f 1547 int err;
232c0013 1548
2a1f1768 1549 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1550 if (!mlx5e_is_offloaded_flow(flow))
1551 continue;
c620b772
AL		 1552 attr = flow->attr;
1553 esw_attr = attr->esw_attr;
1554 spec = &attr->parse_attr->spec;
5dbe906f
PB		 1555
1556 /* update from encap rule to slow path rule */
178f69b4 1557 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1558 /* mark the flow's encap dest as non-valid */
c620b772 1559 esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1560
1561 if (IS_ERR(rule)) {
1562 err = PTR_ERR(rule);
1563 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1564 err);
2a1f1768 1565 continue;
5dbe906f
PB		 1566 }
1567
c620b772 1568 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
5dbe906f 1569 flow->rule[0] = rule;
226f2ca3
VB		 1570 /* was unset when fast path rule removed */
1571 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1572 }
1573
61c806da
OG		 1574 /* we know that the encap is valid */
1575 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1576 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1577}
1578
b8aee822
MB		 1579static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1580{
c620b772 1581 return flow->attr->counter;
b8aee822
MB		 1582}
1583
2a1f1768
VB		 1584/* Takes reference to all flows attached to encap and adds the flows to
1585 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1586 */
1587void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1588{
1589 struct encap_flow_item *efi;
1590 struct mlx5e_tc_flow *flow;
1591
1592 list_for_each_entry(efi, &e->flows, list) {
1593 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1594 if (IS_ERR(mlx5e_flow_get(flow)))
1595 continue;
95435ad7 1596 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1597
1598 flow->tmp_efi_index = efi->index;
1599 list_add(&flow->tmp_list, flow_list);
1600 }
1601}
1602
6a06c2f7 1603/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1604void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1605{
1606 struct mlx5e_tc_flow *flow, *tmp;
1607
1608 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1609 mlx5e_flow_put(priv, flow);
1610}
1611
ac0d9176
VB		 1612static struct mlx5e_encap_entry *
1613mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1614 struct mlx5e_encap_entry *e)
1615{
1616 struct mlx5e_encap_entry *next = NULL;
1617
1618retry:
1619 rcu_read_lock();
1620
1621 /* find encap with non-zero reference counter value */
1622 for (next = e ?
1623 list_next_or_null_rcu(&nhe->encap_list,
1624 &e->encap_list,
1625 struct mlx5e_encap_entry,
1626 encap_list) :
1627 list_first_or_null_rcu(&nhe->encap_list,
1628 struct mlx5e_encap_entry,
1629 encap_list);
1630 next;
1631 next = list_next_or_null_rcu(&nhe->encap_list,
1632 &next->encap_list,
1633 struct mlx5e_encap_entry,
1634 encap_list))
1635 if (mlx5e_encap_take(next))
1636 break;
1637
1638 rcu_read_unlock();
1639
1640 /* release starting encap */
1641 if (e)
1642 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1643 if (!next)
1644 return next;
1645
1646 /* wait for encap to be fully initialized */
1647 wait_for_completion(&next->res_ready);
1648 /* continue searching if encap entry is not in valid state after completion */
1649 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1650 e = next;
1651 goto retry;
1652 }
1653
1654 return next;
1655}
1656
f6dfb4c3
HHZ		 1657void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1658{
1659 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1660 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1661 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1662 struct mlx5_fc *counter;
1663 struct neigh_table *tbl;
1664 bool neigh_used = false;
1665 struct neighbour *n;
90bb7692 1666 u64 lastuse;
f6dfb4c3
HHZ		 1667
1668 if (m_neigh->family == AF_INET)
1669 tbl = &arp_tbl;
1670#if IS_ENABLED(CONFIG_IPV6)
1671 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1672 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1673#endif
1674 else
1675 return;
1676
ac0d9176
VB		 1677 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1678 * next one.
1679 */
1680 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1681 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1682 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1683 struct mlx5_eswitch *esw;
1684 LIST_HEAD(flow_list);
948993f2 1685
6a06c2f7
VB		 1686 esw = priv->mdev->priv.eswitch;
1687 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1688 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1689 flow = container_of(efi, struct mlx5e_tc_flow,
1690 encaps[efi->index]);
5a7e5bcb
VB		 1691 if (IS_ERR(mlx5e_flow_get(flow)))
1692 continue;
6a06c2f7 1693 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1694
226f2ca3 1695 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1696 counter = mlx5e_tc_get_counter(flow);
90bb7692 1697 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1698 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1699 neigh_used = true;
1700 break;
1701 }
1702 }
1703 }
6a06c2f7 1704 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1705
6a06c2f7 1706 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1707 if (neigh_used) {
1708 /* release current encap before breaking the loop */
6a06c2f7 1709 mlx5e_encap_put(priv, e);
e36d4810 1710 break;
ac0d9176 1711 }
f6dfb4c3
HHZ		 1712 }
1713
c786fe59
VB		 1714 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1715
f6dfb4c3
HHZ		 1716 if (neigh_used) {
1717 nhe->reported_lastuse = jiffies;
1718
1719 /* find the relevant neigh according to the cached device and
1720 * dst ip pair
1721 */
1722 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1723 if (!n)
f6dfb4c3 1724 return;
f6dfb4c3
HHZ		 1725
1726 neigh_event_send(n, NULL);
1727 neigh_release(n);
1728 }
1729}
1730
61086f39 1731static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1732{
948993f2 1733 WARN_ON(!list_empty(&e->flows));
948993f2 1734
3c140dd5
VB		 1735 if (e->compl_result > 0) {
1736 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1737
1738 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1739 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1740 }
948993f2 1741
2a4b6526 1742 kfree(e->tun_info);
948993f2 1743 kfree(e->encap_header);
ac0d9176 1744 kfree_rcu(e, rcu);
948993f2
VB		 1745}
1746
14e6b038
EC		 1747static void mlx5e_decap_dealloc(struct mlx5e_priv *priv,
1748 struct mlx5e_decap_entry *d)
1749{
1750 WARN_ON(!list_empty(&d->flows));
1751
1752 if (!d->compl_result)
1753 mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat);
1754
1755 kfree_rcu(d, rcu);
1756}
1757
61086f39
VB		 1758void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1759{
1760 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1761
1762 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1763 return;
1764 hash_del_rcu(&e->encap_hlist);
1765 mutex_unlock(&esw->offloads.encap_tbl_lock);
1766
1767 mlx5e_encap_dealloc(priv, e);
1768}
1769
14e6b038
EC		 1770static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d)
1771{
1772 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1773
1774 if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock))
1775 return;
1776 hash_del_rcu(&d->hlist);
1777 mutex_unlock(&esw->offloads.decap_tbl_lock);
1778
1779 mlx5e_decap_dealloc(priv, d);
1780}
1781
d85cdccb 1782static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1783 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1784{
61086f39
VB		 1785 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1786 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1787
5a7e5bcb 1788 /* flow wasn't fully initialized */
61086f39 1789 if (!e)
5a7e5bcb
VB		 1790 return;
1791
61086f39 1792 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1793 list_del(&flow->encaps[out_index].list);
948993f2 1794 flow->encaps[out_index].e = NULL;
61086f39
VB		 1795 if (!refcount_dec_and_test(&e->refcnt)) {
1796 mutex_unlock(&esw->offloads.encap_tbl_lock);
1797 return;
1798 }
1799 hash_del_rcu(&e->encap_hlist);
1800 mutex_unlock(&esw->offloads.encap_tbl_lock);
1801
1802 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1803}
1804
14e6b038
EC		 1805static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1806 struct mlx5e_tc_flow *flow)
1807{
1808 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1809 struct mlx5e_decap_entry *d = flow->decap_reformat;
1810
1811 if (!d)
1812 return;
1813
1814 mutex_lock(&esw->offloads.decap_tbl_lock);
1815 list_del(&flow->l3_to_l2_reformat);
1816 flow->decap_reformat = NULL;
1817
1818 if (!refcount_dec_and_test(&d->refcnt)) {
1819 mutex_unlock(&esw->offloads.decap_tbl_lock);
1820 return;
1821 }
1822 hash_del_rcu(&d->hlist);
1823 mutex_unlock(&esw->offloads.decap_tbl_lock);
1824
1825 mlx5e_decap_dealloc(priv, d);
1826}
1827
04de7dda
RD		 1828static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1829{
1830 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1831
226f2ca3
VB		 1832 if (!flow_flag_test(flow, ESWITCH) ||
1833 !flow_flag_test(flow, DUP))
04de7dda
RD		 1834 return;
1835
1836 mutex_lock(&esw->offloads.peer_mutex);
1837 list_del(&flow->peer);
1838 mutex_unlock(&esw->offloads.peer_mutex);
1839
226f2ca3 1840 flow_flag_clear(flow, DUP);
04de7dda 1841
eb252c3a
RD		 1842 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1843 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1844 kfree(flow->peer_flow);
1845 }
1846
04de7dda
RD		 1847 flow->peer_flow = NULL;
1848}
1849
1850static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1851{
1852 struct mlx5_core_dev *dev = flow->priv->mdev;
1853 struct mlx5_devcom *devcom = dev->priv.devcom;
1854 struct mlx5_eswitch *peer_esw;
1855
1856 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1857 if (!peer_esw)
1858 return;
1859
1860 __mlx5e_tc_del_fdb_peer_flow(flow);
1861 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1862}
1863
e8f887ac 1864static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1865 struct mlx5e_tc_flow *flow)
e8f887ac 1866{
226f2ca3 1867 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1868 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1869 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1870 } else {
d85cdccb 1871 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1872 }
e8f887ac
AV		 1873}
1874
0a7fcb78
PB		 1875static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1876{
1877 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1878 struct flow_action *flow_action = &rule->action;
1879 const struct flow_action_entry *act;
1880 int i;
1881
1882 flow_action_for_each(i, act, flow_action) {
1883 switch (act->id) {
1884 case FLOW_ACTION_GOTO:
1885 return true;
1886 default:
1887 continue;
1888 }
1889 }
1890
1891 return false;
1892}
bbd00f7e 1893
0a7fcb78
PB		 1894static int
1895enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1896 struct flow_dissector_key_enc_opts *opts,
1897 struct netlink_ext_ack *extack,
1898 bool *dont_care)
1899{
1900 struct geneve_opt *opt;
1901 int off = 0;
1902
1903 *dont_care = true;
1904
1905 while (opts->len > off) {
1906 opt = (struct geneve_opt *)&opts->data[off];
1907
1908 if (!(*dont_care) || opt->opt_class || opt->type ||
1909 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1910 *dont_care = false;
1911
c51323ee 1912 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1913 opt->type != U8_MAX) {
0a7fcb78
PB		 1914 NL_SET_ERR_MSG(extack,
1915 "Partial match of tunnel options in chain > 0 isn't supported");
1916 netdev_warn(priv->netdev,
1917 "Partial match of tunnel options in chain > 0 isn't supported");
1918 return -EOPNOTSUPP;
1919 }
1920 }
1921
1922 off += sizeof(struct geneve_opt) + opt->length * 4;
1923 }
1924
1925 return 0;
1926}
1927
1928#define COPY_DISSECTOR(rule, diss_key, dst)\
1929({ \
1930 struct flow_rule *__rule = (rule);\
1931 typeof(dst) __dst = dst;\
1932\
1933 memcpy(__dst,\
1934 skb_flow_dissector_target(__rule->match.dissector,\
1935 diss_key,\
1936 __rule->match.key),\
1937 sizeof(*__dst));\
1938})
1939
1940static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1941 struct mlx5e_tc_flow *flow,
1942 struct flow_cls_offload *f,
1943 struct net_device *filter_dev)
bbd00f7e 1944{
f9e30088 1945 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1946 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1947 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1948 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1949 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1950 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1951 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1952 struct mlx5e_rep_priv *uplink_rpriv;
1953 struct tunnel_match_key tunnel_key;
1954 bool enc_opts_is_dont_care = true;
1955 u32 tun_id, enc_opts_id = 0;
1956 struct mlx5_eswitch *esw;
1957 u32 value, mask;
8f256622 1958 int err;
2e72eb43 1959
0a7fcb78
PB		 1960 esw = priv->mdev->priv.eswitch;
1961 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1962 uplink_priv = &uplink_rpriv->uplink_priv;
1963
1964 memset(&tunnel_key, 0, sizeof(tunnel_key));
1965 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1966 &tunnel_key.enc_control);
1967 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1968 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1969 &tunnel_key.enc_ipv4);
1970 else
1971 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1972 &tunnel_key.enc_ipv6);
1973 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1974 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1975 &tunnel_key.enc_tp);
1976 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1977 &tunnel_key.enc_key_id);
1978 tunnel_key.filter_ifindex = filter_dev->ifindex;
1979
1980 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1981 if (err)
101f4de9 1982 return err;
bbd00f7e 1983
0a7fcb78
PB		 1984 flow_rule_match_enc_opts(rule, &enc_opts_match);
1985 err = enc_opts_is_dont_care_or_full_match(priv,
1986 enc_opts_match.mask,
1987 extack,
1988 &enc_opts_is_dont_care);
1989 if (err)
1990 goto err_enc_opts;
fe1587a7 1991
0a7fcb78 1992 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1993 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1994 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1995 sizeof(*enc_opts_match.key));
1996 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1997 sizeof(*enc_opts_match.mask));
1998
0a7fcb78 1999 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 2000 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 2001 if (err)
2002 goto err_enc_opts;
2003 }
fe1587a7 2004
0a7fcb78
PB		 2005 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2006 mask = enc_opts_id ? TUNNEL_ID_MASK :
2007 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 2008
0a7fcb78
PB		 2009 if (attr->chain) {
2010 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2011 TUNNEL_TO_REG, value, mask);
2012 } else {
2013 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2014 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 2015 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 2016 TUNNEL_TO_REG, value);
2017 if (err)
2018 goto err_set;
fe1587a7 2019
0a7fcb78 2020 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 2021 }
bbd00f7e 2022
0a7fcb78
PB		 2023 flow->tunnel_id = value;
2024 return 0;
bcef735c 2025
0a7fcb78
PB		 2026err_set:
2027 if (enc_opts_id)
2028 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2029 enc_opts_id);
2030err_enc_opts:
2031 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2032 return err;
2033}
bcef735c 2034
0a7fcb78
PB		 2035static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2036{
2037 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
2038 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
2039 struct mlx5_rep_uplink_priv *uplink_priv;
2040 struct mlx5e_rep_priv *uplink_rpriv;
2041 struct mlx5_eswitch *esw;
bcef735c 2042
0a7fcb78
PB		 2043 esw = flow->priv->mdev->priv.eswitch;
2044 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2045 uplink_priv = &uplink_rpriv->uplink_priv;
2046
2047 if (tun_id)
2048 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2049 if (enc_opts_id)
2050 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2051 enc_opts_id);
2052}
e98bedf5 2053
4c3844d9
PB		 2054u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
2055{
2056 return flow->tunnel_id;
2057}
2058
fca53304
EB		 2059void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2060 struct flow_match_basic *match, bool outer,
2061 void *headers_c, void *headers_v)
2062{
2063 bool ip_version_cap;
2064
2065 ip_version_cap = outer ?
2066 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2067 ft_field_support.outer_ip_version) :
2068 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2069 ft_field_support.inner_ip_version);
2070
2071 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2072 (match->key->n_proto == htons(ETH_P_IP) ||
2073 match->key->n_proto == htons(ETH_P_IPV6))) {
2074 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2075 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2076 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2077 } else {
2078 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2079 ntohs(match->mask->n_proto));
2080 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2081 ntohs(match->key->n_proto));
2082 }
4a5d5d73
EB		 2083}
2084
bbd00f7e 2085static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2086 struct mlx5e_tc_flow *flow,
bbd00f7e 2087 struct mlx5_flow_spec *spec,
f9e30088 2088 struct flow_cls_offload *f,
0a7fcb78
PB		 2089 struct net_device *filter_dev,
2090 u8 *match_level,
2091 bool *match_inner)
bbd00f7e 2092{
0a7fcb78 2093 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2094 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2095 bool needs_mapping, sets_mapping;
8f256622 2096 int err;
2e72eb43 2097
0a7fcb78
PB		 2098 if (!mlx5e_is_eswitch_flow(flow))
2099 return -EOPNOTSUPP;
2100
c620b772
AL		 2101 needs_mapping = !!flow->attr->chain;
2102 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 2103 *match_inner = !needs_mapping;
2104
2105 if ((needs_mapping || sets_mapping) &&
636bb968 2106 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 2107 NL_SET_ERR_MSG(extack,
636bb968 2108 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2109 netdev_warn(priv->netdev,
636bb968 2110 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2111 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2112 }
2113
c620b772 2114 if (!flow->attr->chain) {
0a7fcb78
PB		 2115 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2116 match_level);
2117 if (err) {
e98bedf5 2118 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2119 "Failed to parse tunnel attributes");
2120 netdev_warn(priv->netdev,
2121 "Failed to parse tunnel attributes");
2122 return err;
e98bedf5
EB		 2123 }
2124
14e6b038
EC		 2125 /* With mpls over udp we decapsulate using packet reformat
2126 * object
2127 */
2128 if (!netif_is_bareudp(filter_dev))
c620b772 2129 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 2130 }
2131
0a7fcb78
PB		 2132 if (!needs_mapping && !sets_mapping)
2133 return 0;
bbd00f7e 2134
0a7fcb78 2135 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2136}
bbd00f7e 2137
0a7fcb78 2138static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2139{
0a7fcb78
PB		 2140 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2141 inner_headers);
bbd00f7e
HHZ		 2142}
2143
0a7fcb78 2144static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2145{
0a7fcb78
PB		 2146 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2147 inner_headers);
2148}
2149
2150static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2151{
2152 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2153 outer_headers);
2154}
2155
2156static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2157{
2158 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2159 outer_headers);
8377629e
EB		 2160}
2161
2162static void *get_match_headers_value(u32 flags,
2163 struct mlx5_flow_spec *spec)
2164{
2165 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2166 get_match_inner_headers_value(spec) :
2167 get_match_outer_headers_value(spec);
2168}
2169
2170static void *get_match_headers_criteria(u32 flags,
2171 struct mlx5_flow_spec *spec)
2172{
2173 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2174 get_match_inner_headers_criteria(spec) :
2175 get_match_outer_headers_criteria(spec);
8377629e
EB		 2176}
2177
6d65bc64 2178static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2179 struct flow_cls_offload *f)
2180{
2181 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2182 struct netlink_ext_ack *extack = f->common.extack;
2183 struct net_device *ingress_dev;
2184 struct flow_match_meta match;
2185
2186 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2187 return 0;
2188
2189 flow_rule_match_meta(rule, &match);
2190 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2191 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2192 return -EOPNOTSUPP;
6d65bc64 2193 }
2194
2195 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2196 match.key->ingress_ifindex);
2197 if (!ingress_dev) {
2198 NL_SET_ERR_MSG_MOD(extack,
2199 "Can't find the ingress port to match on");
a683012a 2200 return -ENOENT;
6d65bc64 2201 }
2202
2203 if (ingress_dev != filter_dev) {
2204 NL_SET_ERR_MSG_MOD(extack,
2205 "Can't match on the ingress filter port");
a683012a 2206 return -EOPNOTSUPP;
6d65bc64 2207 }
2208
2209 return 0;
2210}
2211
72046a91
EC		 2212static bool skip_key_basic(struct net_device *filter_dev,
2213 struct flow_cls_offload *f)
2214{
2215 /* When doing mpls over udp decap, the user needs to provide
2216 * MPLS_UC as the protocol in order to be able to match on mpls
2217 * label fields. However, the actual ethertype is IP so we want to
2218 * avoid matching on this, otherwise we'll fail the match.
2219 */
2220 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2221 return true;
2222
2223 return false;
2224}
2225
de0af0bf 2226static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2227 struct mlx5e_tc_flow *flow,
de0af0bf 2228 struct mlx5_flow_spec *spec,
f9e30088 2229 struct flow_cls_offload *f,
54c177ca 2230 struct net_device *filter_dev,
93b3586e 2231 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2232{
e98bedf5 2233 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2234 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2235 outer_headers);
2236 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2237 outer_headers);
699e96dd
JL		 2238 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2239 misc_parameters);
2240 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2241 misc_parameters);
f9e30088 2242 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2243 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2244 u16 addr_type = 0;
2245 u8 ip_proto = 0;
93b3586e 2246 u8 *match_level;
6d65bc64 2247 int err;
e3a2b7ed 2248
93b3586e 2249 match_level = outer_match_level;
de0af0bf 2250
8f256622 2251 if (dissector->used_keys &
3d144578
VB		 2252 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2253 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2254 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2255 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2256 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2257 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2258 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2259 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2260 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2261 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2262 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2263 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2264 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2265 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2266 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2267 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2268 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2269 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91
EC		 2270 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2271 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2272 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 2273 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 2274 dissector->used_keys);
e3a2b7ed
AV		 2275 return -EOPNOTSUPP;
2276 }
2277
075973c7 2278 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2279 bool match_inner = false;
bbd00f7e 2280
0a7fcb78
PB		 2281 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2282 outer_match_level, &match_inner);
2283 if (err)
2284 return err;
2285
2286 if (match_inner) {
2287 /* header pointers should point to the inner headers
2288 * if the packet was decapsulated already.
2289 * outer headers are set by parse_tunnel_attr.
2290 */
2291 match_level = inner_match_level;
2292 headers_c = get_match_inner_headers_criteria(spec);
2293 headers_v = get_match_inner_headers_value(spec);
2294 }
bbd00f7e
HHZ		 2295 }
2296
6d65bc64 2297 err = mlx5e_flower_parse_meta(filter_dev, f);
2298 if (err)
2299 return err;
2300
72046a91
EC		 2301 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2302 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2303 struct flow_match_basic match;
2304
2305 flow_rule_match_basic(rule, &match);
fca53304
EB		 2306 mlx5e_tc_set_ethertype(priv->mdev, &match,
2307 match_level == outer_match_level,
2308 headers_c, headers_v);
e3a2b7ed 2309
8f256622 2310 if (match.mask->n_proto)
d708f902 2311 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2312 }
35a605db
EB		 2313 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2314 is_vlan_dev(filter_dev)) {
2315 struct flow_dissector_key_vlan filter_dev_mask;
2316 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2317 struct flow_match_vlan match;
2318
35a605db
EB		 2319 if (is_vlan_dev(filter_dev)) {
2320 match.key = &filter_dev_key;
2321 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2322 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2323 match.key->vlan_priority = 0;
2324 match.mask = &filter_dev_mask;
2325 memset(match.mask, 0xff, sizeof(*match.mask));
2326 match.mask->vlan_priority = 0;
2327 } else {
2328 flow_rule_match_vlan(rule, &match);
2329 }
8f256622
PNA		 2330 if (match.mask->vlan_id ||
2331 match.mask->vlan_priority ||
2332 match.mask->vlan_tpid) {
2333 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2334 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2335 svlan_tag, 1);
2336 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2337 svlan_tag, 1);
2338 } else {
2339 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2340 cvlan_tag, 1);
2341 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2342 cvlan_tag, 1);
2343 }
095b6cfd 2344
8f256622
PNA		 2345 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2346 match.mask->vlan_id);
2347 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2348 match.key->vlan_id);
358d79a4 2349
8f256622
PNA		 2350 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2351 match.mask->vlan_priority);
2352 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2353 match.key->vlan_priority);
54782900 2354
d708f902 2355 *match_level = MLX5_MATCH_L2;
54782900 2356 }
d3a80bb5 2357 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2358 /* cvlan_tag enabled in match criteria and
2359 * disabled in match value means both S & C tags
2360 * don't exist (untagged of both)
2361 */
cee26487 2362 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2363 *match_level = MLX5_MATCH_L2;
54782900
OG		 2364 }
2365
8f256622
PNA		 2366 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2367 struct flow_match_vlan match;
2368
12d5cbf8 2369 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2370 if (match.mask->vlan_id ||
2371 match.mask->vlan_priority ||
2372 match.mask->vlan_tpid) {
2373 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2374 MLX5_SET(fte_match_set_misc, misc_c,
2375 outer_second_svlan_tag, 1);
2376 MLX5_SET(fte_match_set_misc, misc_v,
2377 outer_second_svlan_tag, 1);
2378 } else {
2379 MLX5_SET(fte_match_set_misc, misc_c,
2380 outer_second_cvlan_tag, 1);
2381 MLX5_SET(fte_match_set_misc, misc_v,
2382 outer_second_cvlan_tag, 1);
2383 }
2384
2385 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2386 match.mask->vlan_id);
699e96dd 2387 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2388 match.key->vlan_id);
699e96dd 2389 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2390 match.mask->vlan_priority);
699e96dd 2391 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2392 match.key->vlan_priority);
699e96dd
JL		 2393
2394 *match_level = MLX5_MATCH_L2;
0faddfe6 2395 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2396 }
2397 }
2398
8f256622
PNA		 2399 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2400 struct flow_match_eth_addrs match;
54782900 2401
8f256622 2402 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2403 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2404 dmac_47_16),
8f256622 2405 match.mask->dst);
d3a80bb5
OG		 2406 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2407 dmac_47_16),
8f256622 2408 match.key->dst);
d3a80bb5
OG		 2409
2410 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2411 smac_47_16),
8f256622 2412 match.mask->src);
d3a80bb5
OG		 2413 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2414 smac_47_16),
8f256622 2415 match.key->src);
d3a80bb5 2416
8f256622
PNA		 2417 if (!is_zero_ether_addr(match.mask->src) ||
2418 !is_zero_ether_addr(match.mask->dst))
d708f902 2419 *match_level = MLX5_MATCH_L2;
54782900
OG		 2420 }
2421
8f256622
PNA		 2422 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2423 struct flow_match_control match;
54782900 2424
8f256622
PNA		 2425 flow_rule_match_control(rule, &match);
2426 addr_type = match.key->addr_type;
54782900
OG		 2427
2428 /* the HW doesn't support frag first/later */
8f256622 2429 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2430 return -EOPNOTSUPP;
2431
8f256622 2432 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2433 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2434 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2435 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2436
2437 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2438 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2439 *match_level = MLX5_MATCH_L2;
54782900
OG		 2440 /* *** L2 attributes parsing up to here *** */
2441 else
83621b7d 2442 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2443 }
2444 }
2445
8f256622
PNA		 2446 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2447 struct flow_match_basic match;
2448
2449 flow_rule_match_basic(rule, &match);
2450 ip_proto = match.key->ip_proto;
54782900
OG		 2451
2452 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2453 match.mask->ip_proto);
54782900 2454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2455 match.key->ip_proto);
54782900 2456
8f256622 2457 if (match.mask->ip_proto)
d708f902 2458 *match_level = MLX5_MATCH_L3;
54782900
OG		 2459 }
2460
e3a2b7ed 2461 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2462 struct flow_match_ipv4_addrs match;
e3a2b7ed 2463
8f256622 2464 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2465 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2466 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2467 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2468 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2469 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2470 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2471 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2472 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2473 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2474 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2475 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2476 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2477
8f256622 2478 if (match.mask->src || match.mask->dst)
d708f902 2479 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2480 }
2481
2482 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2483 struct flow_match_ipv6_addrs match;
e3a2b7ed 2484
8f256622 2485 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2486 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2487 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2488 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2489 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2490 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2491 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2492
2493 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2494 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2495 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2496 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2497 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2498 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2499
8f256622
PNA		 2500 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2501 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2502 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2503 }
2504
8f256622
PNA		 2505 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2506 struct flow_match_ip match;
1f97a526 2507
8f256622
PNA		 2508 flow_rule_match_ip(rule, &match);
2509 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2510 match.mask->tos & 0x3);
2511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2512 match.key->tos & 0x3);
1f97a526 2513
8f256622
PNA		 2514 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2515 match.mask->tos >> 2);
2516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2517 match.key->tos >> 2);
1f97a526 2518
8f256622
PNA		 2519 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2520 match.mask->ttl);
2521 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2522 match.key->ttl);
1f97a526 2523
8f256622 2524 if (match.mask->ttl &&
a8ade55f 2525 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2526 ft_field_support.outer_ipv4_ttl)) {
2527 NL_SET_ERR_MSG_MOD(extack,
2528 "Matching on TTL is not supported");
1f97a526 2529 return -EOPNOTSUPP;
e98bedf5 2530 }
a8ade55f 2531
8f256622 2532 if (match.mask->tos || match.mask->ttl)
d708f902 2533 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2534 }
2535
54782900
OG		 2536 /* *** L3 attributes parsing up to here *** */
2537
8f256622
PNA		 2538 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2539 struct flow_match_ports match;
2540
2541 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2542 switch (ip_proto) {
2543 case IPPROTO_TCP:
2544 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2545 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2546 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2547 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2548
2549 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2550 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2551 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2552 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2553 break;
2554
2555 case IPPROTO_UDP:
2556 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2557 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2558 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2559 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2560
2561 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2562 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2563 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2564 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2565 break;
2566 default:
e98bedf5
EB		 2567 NL_SET_ERR_MSG_MOD(extack,
2568 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2569 netdev_err(priv->netdev,
2570 "Only UDP and TCP transport are supported\n");
2571 return -EINVAL;
2572 }
de0af0bf 2573
8f256622 2574 if (match.mask->src || match.mask->dst)
d708f902 2575 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2576 }
2577
8f256622
PNA		 2578 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2579 struct flow_match_tcp match;
e77834ec 2580
8f256622 2581 flow_rule_match_tcp(rule, &match);
e77834ec 2582 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2583 ntohs(match.mask->flags));
e77834ec 2584 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2585 ntohs(match.key->flags));
e77834ec 2586
8f256622 2587 if (match.mask->flags)
d708f902 2588 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2589 }
2590
e3a2b7ed
AV		 2591 return 0;
2592}
2593
de0af0bf 2594static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2595 struct mlx5e_tc_flow *flow,
de0af0bf 2596 struct mlx5_flow_spec *spec,
f9e30088 2597 struct flow_cls_offload *f,
54c177ca 2598 struct net_device *filter_dev)
de0af0bf 2599{
93b3586e 2600 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2601 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2602 struct mlx5_core_dev *dev = priv->mdev;
2603 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2604 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2605 struct mlx5_eswitch_rep *rep;
226f2ca3 2606 bool is_eswitch_flow;
de0af0bf
RD		 2607 int err;
2608
93b3586e
HN		 2609 inner_match_level = MLX5_MATCH_NONE;
2610 outer_match_level = MLX5_MATCH_NONE;
2611
0a7fcb78
PB		 2612 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2613 &inner_match_level, &outer_match_level);
93b3586e
HN		 2614 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2615 outer_match_level : inner_match_level;
de0af0bf 2616
226f2ca3
VB		 2617 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2618 if (!err && is_eswitch_flow) {
1d447a39 2619 rep = rpriv->rep;
b05af6aa 2620 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2621 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2622 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2623 NL_SET_ERR_MSG_MOD(extack,
2624 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2625 netdev_warn(priv->netdev,
2626 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2627 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2628 return -EOPNOTSUPP;
2629 }
2630 }
2631
c620b772
AL		 2632 flow->attr->inner_match_level = inner_match_level;
2633 flow->attr->outer_match_level = outer_match_level;
2634
38aa51c1 2635
de0af0bf
RD		 2636 return err;
2637}
2638
d79b6df6
OG		 2639struct pedit_headers {
2640 struct ethhdr eth;
0eb69bb9 2641 struct vlan_hdr vlan;
d79b6df6
OG		 2642 struct iphdr ip4;
2643 struct ipv6hdr ip6;
2644 struct tcphdr tcp;
2645 struct udphdr udp;
2646};
2647
c500c86b
PNA		 2648struct pedit_headers_action {
2649 struct pedit_headers vals;
2650 struct pedit_headers masks;
2651 u32 pedits;
2652};
2653
d79b6df6 2654static int pedit_header_offsets[] = {
73867881
PNA		 2655 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2656 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2657 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2658 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2659 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2660};
2661
2662#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2663
2664static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2665 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2666{
2667 u32 *curr_pmask, *curr_pval;
2668
c500c86b
PNA		 2669 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2670 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2671
2672 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2673 goto out_err;
2674
2675 *curr_pmask |= mask;
2676 *curr_pval |= (val & mask);
2677
2678 return 0;
2679
2680out_err:
2681 return -EOPNOTSUPP;
2682}
2683
2684struct mlx5_fields {
2685 u8 field;
88f30bbc
DL		 2686 u8 field_bsize;
2687 u32 field_mask;
d79b6df6 2688 u32 offset;
27c11b6b 2689 u32 match_offset;
d79b6df6
OG		 2690};
2691
88f30bbc
DL		 2692#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2693 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2694 offsetof(struct pedit_headers, field) + (off), \
2695 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2696
2ef86872
EB		 2697/* masked values are the same and there are no rewrites that do not have a
2698 * match.
2699 */
2700#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2701 type matchmaskx = *(type *)(matchmaskp); \
2702 type matchvalx = *(type *)(matchvalp); \
2703 type maskx = *(type *)(maskp); \
2704 type valx = *(type *)(valp); \
2705 \
2706 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2707 matchmaskx)); \
2708})
2709
27c11b6b 2710static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2711 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2712{
2713 bool same = false;
2714
88f30bbc
DL		 2715 switch (bsize) {
2716 case 8:
2ef86872 2717 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2718 break;
88f30bbc 2719 case 16:
2ef86872 2720 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2721 break;
88f30bbc 2722 case 32:
2ef86872 2723 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2724 break;
2725 }
2726
2727 return same;
2728}
a8e4f0c4 2729
d79b6df6 2730static struct mlx5_fields fields[] = {
88f30bbc
DL		 2731 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2732 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2733 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2734 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2735 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2736 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2737
ab9341b5 2738 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2739 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2740 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2741 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2742
2743 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2744 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2745 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2746 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2747 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2748 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2749 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2750 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2751 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2752 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2753 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2754 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2755 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2756 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2757 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2758 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2759 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2760 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2761
88f30bbc
DL		 2762 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2763 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2764 /* in linux iphdr tcp_flags is 8 bits long */
2765 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2766
88f30bbc
DL		 2767 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2768 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2769};
2770
82198d8b
MD		 2771static unsigned long mask_to_le(unsigned long mask, int size)
2772{
2773 __be32 mask_be32;
2774 __be16 mask_be16;
2775
2776 if (size == 32) {
2777 mask_be32 = (__force __be32)(mask);
2778 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2779 } else if (size == 16) {
2780 mask_be32 = (__force __be32)(mask);
2781 mask_be16 = *(__be16 *)&mask_be32;
2782 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2783 }
2784
2785 return mask;
2786}
6ae4a6a5
PB		 2787static int offload_pedit_fields(struct mlx5e_priv *priv,
2788 int namespace,
2789 struct pedit_headers_action *hdrs,
e98bedf5 2790 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2791 u32 *action_flags,
e98bedf5 2792 struct netlink_ext_ack *extack)
d79b6df6
OG		 2793{
2794 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2795 int i, action_size, first, last, next_z;
88f30bbc
DL		 2796 void *headers_c, *headers_v, *action, *vals_p;
2797 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2798 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2799 struct mlx5_fields *f;
82198d8b 2800 unsigned long mask, field_mask;
6ae4a6a5 2801 int err;
88f30bbc
DL		 2802 u8 cmd;
2803
6ae4a6a5 2804 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2805 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2806 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2807
73867881
PNA		 2808 set_masks = &hdrs[0].masks;
2809 add_masks = &hdrs[1].masks;
2810 set_vals = &hdrs[0].vals;
2811 add_vals = &hdrs[1].vals;
d79b6df6 2812
d65dbedf 2813 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2814
2815 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2816 bool skip;
2817
d79b6df6
OG		 2818 f = &fields[i];
2819 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2820 s_mask = 0;
2821 a_mask = 0;
d79b6df6
OG		 2822
2823 s_masks_p = (void *)set_masks + f->offset;
2824 a_masks_p = (void *)add_masks + f->offset;
2825
88f30bbc
DL		 2826 s_mask = *s_masks_p & f->field_mask;
2827 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2828
2829 if (!s_mask && !a_mask) /* nothing to offload here */
2830 continue;
2831
2832 if (s_mask && a_mask) {
e98bedf5
EB		 2833 NL_SET_ERR_MSG_MOD(extack,
2834 "can't set and add to the same HW field");
d79b6df6
OG		 2835 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2836 return -EOPNOTSUPP;
2837 }
2838
27c11b6b 2839 skip = false;
d79b6df6 2840 if (s_mask) {
27c11b6b
EB		 2841 void *match_mask = headers_c + f->match_offset;
2842 void *match_val = headers_v + f->match_offset;
2843
d79b6df6
OG		 2844 cmd = MLX5_ACTION_TYPE_SET;
2845 mask = s_mask;
2846 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2847 /* don't rewrite if we have a match on the same value */
2848 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2849 match_mask, f->field_bsize))
27c11b6b 2850 skip = true;
d79b6df6 2851 /* clear to denote we consumed this field */
88f30bbc 2852 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2853 } else {
2854 cmd = MLX5_ACTION_TYPE_ADD;
2855 mask = a_mask;
2856 vals_p = (void *)add_vals + f->offset;
27c11b6b 2857 /* add 0 is no change */
88f30bbc 2858 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2859 skip = true;
d79b6df6 2860 /* clear to denote we consumed this field */
88f30bbc 2861 *a_masks_p &= ~f->field_mask;
d79b6df6 2862 }
27c11b6b
EB		 2863 if (skip)
2864 continue;
d79b6df6 2865
82198d8b 2866 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2867
88f30bbc
DL		 2868 first = find_first_bit(&mask, f->field_bsize);
2869 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2870 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2871 if (first < next_z && next_z < last) {
e98bedf5
EB		 2872 NL_SET_ERR_MSG_MOD(extack,
2873 "rewrite of few sub-fields isn't supported");
2b64beba 2874 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2875 mask);
2876 return -EOPNOTSUPP;
2877 }
2878
6ae4a6a5
PB		 2879 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2880 if (err) {
2881 NL_SET_ERR_MSG_MOD(extack,
2882 "too many pedit actions, can't offload");
2883 mlx5_core_warn(priv->mdev,
2884 "mlx5: parsed %d pedit actions, can't do more\n",
2885 mod_acts->num_actions);
2886 return err;
2887 }
2888
2889 action = mod_acts->actions +
2890 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2891 MLX5_SET(set_action_in, action, action_type, cmd);
2892 MLX5_SET(set_action_in, action, field, f->field);
2893
2894 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2895 int start;
2896
82198d8b
MD		 2897 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2898
88f30bbc 2899 /* if field is bit sized it can start not from first bit */
82198d8b 2900 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2901
2902 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2903 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2904 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2905 }
2906
88f30bbc 2907 if (f->field_bsize == 32)
2b64beba 2908 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2909 else if (f->field_bsize == 16)
2b64beba 2910 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2911 else if (f->field_bsize == 8)
2b64beba 2912 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2913
6ae4a6a5 2914 ++mod_acts->num_actions;
d79b6df6
OG		 2915 }
2916
d79b6df6
OG		 2917 return 0;
2918}
2919
2cc1cb1d
TZ		 2920static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2921 int namespace)
2922{
2923 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2924 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2925 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2926 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2927}
2928
6ae4a6a5
PB		 2929int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2930 int namespace,
2931 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2932{
6ae4a6a5
PB		 2933 int action_size, new_num_actions, max_hw_actions;
2934 size_t new_sz, old_sz;
2935 void *ret;
d79b6df6 2936
6ae4a6a5
PB		 2937 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2938 return 0;
d79b6df6 2939
d65dbedf 2940 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2941
6ae4a6a5
PB		 2942 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2943 namespace);
2944 new_num_actions = min(max_hw_actions,
2945 mod_hdr_acts->actions ?
2946 mod_hdr_acts->max_actions * 2 : 1);
2947 if (mod_hdr_acts->max_actions == new_num_actions)
2948 return -ENOSPC;
2949
2950 new_sz = action_size * new_num_actions;
2951 old_sz = mod_hdr_acts->max_actions * action_size;
2952 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2953 if (!ret)
d79b6df6
OG		 2954 return -ENOMEM;
2955
6ae4a6a5
PB		 2956 memset(ret + old_sz, 0, new_sz - old_sz);
2957 mod_hdr_acts->actions = ret;
2958 mod_hdr_acts->max_actions = new_num_actions;
2959
d79b6df6
OG		 2960 return 0;
2961}
2962
6ae4a6a5
PB		 2963void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2964{
2965 kfree(mod_hdr_acts->actions);
2966 mod_hdr_acts->actions = NULL;
2967 mod_hdr_acts->num_actions = 0;
2968 mod_hdr_acts->max_actions = 0;
2969}
2970
d79b6df6
OG		 2971static const struct pedit_headers zero_masks = {};
2972
582234b4
EC		 2973static int
2974parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2975 const struct flow_action_entry *act, int namespace,
2976 struct mlx5e_tc_flow_parse_attr *parse_attr,
2977 struct pedit_headers_action *hdrs,
2978 struct netlink_ext_ack *extack)
d79b6df6 2979{
73867881
PNA		 2980 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2981 int err = -EOPNOTSUPP;
d79b6df6 2982 u32 mask, val, offset;
73867881 2983 u8 htype;
d79b6df6 2984
73867881
PNA		 2985 htype = act->mangle.htype;
2986 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2987
73867881
PNA		 2988 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2989 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2990 goto out_err;
2991 }
d79b6df6 2992
2cc1cb1d
TZ		 2993 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2994 NL_SET_ERR_MSG_MOD(extack,
2995 "The pedit offload action is not supported");
2996 goto out_err;
2997 }
2998
73867881
PNA		 2999 mask = act->mangle.mask;
3000 val = act->mangle.val;
3001 offset = act->mangle.offset;
d79b6df6 3002
73867881
PNA		 3003 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
3004 if (err)
3005 goto out_err;
c500c86b 3006
73867881 3007 hdrs[cmd].pedits++;
d79b6df6 3008
c500c86b
PNA		 3009 return 0;
3010out_err:
3011 return err;
3012}
3013
582234b4
EC		 3014static int
3015parse_pedit_to_reformat(struct mlx5e_priv *priv,
3016 const struct flow_action_entry *act,
3017 struct mlx5e_tc_flow_parse_attr *parse_attr,
3018 struct netlink_ext_ack *extack)
3019{
3020 u32 mask, val, offset;
3021 u32 *p;
3022
3023 if (act->id != FLOW_ACTION_MANGLE)
3024 return -EOPNOTSUPP;
3025
3026 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
3027 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
3028 return -EOPNOTSUPP;
3029 }
3030
3031 mask = ~act->mangle.mask;
3032 val = act->mangle.val;
3033 offset = act->mangle.offset;
3034 p = (u32 *)&parse_attr->eth;
3035 *(p + (offset >> 2)) |= (val & mask);
3036
3037 return 0;
3038}
3039
3040static int parse_tc_pedit_action(struct mlx5e_priv *priv,
3041 const struct flow_action_entry *act, int namespace,
3042 struct mlx5e_tc_flow_parse_attr *parse_attr,
3043 struct pedit_headers_action *hdrs,
3044 struct mlx5e_tc_flow *flow,
3045 struct netlink_ext_ack *extack)
3046{
3047 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
3048 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
3049
3050 return parse_pedit_to_modify_hdr(priv, act, namespace,
3051 parse_attr, hdrs, extack);
3052}
3053
c500c86b
PNA		 3054static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3055 struct mlx5e_tc_flow_parse_attr *parse_attr,
3056 struct pedit_headers_action *hdrs,
27c11b6b 3057 u32 *action_flags,
c500c86b
PNA		 3058 struct netlink_ext_ack *extack)
3059{
3060 struct pedit_headers *cmd_masks;
3061 int err;
3062 u8 cmd;
3063
6ae4a6a5
PB		 3064 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
3065 action_flags, extack);
d79b6df6
OG		 3066 if (err < 0)
3067 goto out_dealloc_parsed_actions;
3068
3069 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 3070 cmd_masks = &hdrs[cmd].masks;
d79b6df6 3071 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 3072 NL_SET_ERR_MSG_MOD(extack,
3073 "attempt to offload an unsupported field");
b3a433de 3074 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3075 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3076 16, 1, cmd_masks, sizeof(zero_masks), true);
3077 err = -EOPNOTSUPP;
3078 goto out_dealloc_parsed_actions;
3079 }
3080 }
3081
3082 return 0;
3083
3084out_dealloc_parsed_actions:
6ae4a6a5 3085 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3086 return err;
3087}
3088
e98bedf5
EB		 3089static bool csum_offload_supported(struct mlx5e_priv *priv,
3090 u32 action,
3091 u32 update_flags,
3092 struct netlink_ext_ack *extack)
26c02749
OG		 3093{
3094 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3095 TCA_CSUM_UPDATE_FLAG_UDP;
3096
3097 /* The HW recalcs checksums only if re-writing headers */
3098 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3099 NL_SET_ERR_MSG_MOD(extack,
3100 "TC csum action is only offloaded with pedit");
26c02749
OG		 3101 netdev_warn(priv->netdev,
3102 "TC csum action is only offloaded with pedit\n");
3103 return false;
3104 }
3105
3106 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3107 NL_SET_ERR_MSG_MOD(extack,
3108 "can't offload TC csum action for some header/s");
26c02749
OG		 3109 netdev_warn(priv->netdev,
3110 "can't offload TC csum action for some header/s - flags %#x\n",
3111 update_flags);
3112 return false;
3113 }
3114
3115 return true;
3116}
3117
8998576b
DL		 3118struct ip_ttl_word {
3119 __u8 ttl;
3120 __u8 protocol;
3121 __sum16 check;
3122};
3123
3124struct ipv6_hoplimit_word {
3125 __be16 payload_len;
3126 __u8 nexthdr;
3127 __u8 hop_limit;
3128};
3129
4c3844d9
PB		 3130static int is_action_keys_supported(const struct flow_action_entry *act,
3131 bool ct_flow, bool *modify_ip_header,
7e36feeb 3132 bool *modify_tuple,
4c3844d9 3133 struct netlink_ext_ack *extack)
8998576b
DL		 3134{
3135 u32 mask, offset;
3136 u8 htype;
3137
3138 htype = act->mangle.htype;
3139 offset = act->mangle.offset;
3140 mask = ~act->mangle.mask;
3141 /* For IPv4 & IPv6 header check 4 byte word,
3142 * to determine that modified fields
3143 * are NOT ttl & hop_limit only.
3144 */
3145 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3146 struct ip_ttl_word *ttl_word =
3147 (struct ip_ttl_word *)&mask;
3148
3149 if (offset != offsetof(struct iphdr, ttl) ||
3150 ttl_word->protocol ||
3151 ttl_word->check) {
4c3844d9
PB		 3152 *modify_ip_header = true;
3153 }
3154
7e36feeb
PB		 3155 if (offset >= offsetof(struct iphdr, saddr))
3156 *modify_tuple = true;
3157
3158 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3159 NL_SET_ERR_MSG_MOD(extack,
3160 "can't offload re-write of ipv4 address with action ct");
3161 return -EOPNOTSUPP;
8998576b
DL		 3162 }
3163 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3164 struct ipv6_hoplimit_word *hoplimit_word =
3165 (struct ipv6_hoplimit_word *)&mask;
3166
3167 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3168 hoplimit_word->payload_len ||
3169 hoplimit_word->nexthdr) {
4c3844d9
PB		 3170 *modify_ip_header = true;
3171 }
3172
7e36feeb
PB		 3173 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3174 *modify_tuple = true;
3175
3176 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3177 NL_SET_ERR_MSG_MOD(extack,
3178 "can't offload re-write of ipv6 address with action ct");
3179 return -EOPNOTSUPP;
8998576b 3180 }
7e36feeb
PB		 3181 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3182 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3183 *modify_tuple = true;
3184 if (ct_flow) {
3185 NL_SET_ERR_MSG_MOD(extack,
3186 "can't offload re-write of transport header ports with action ct");
3187 return -EOPNOTSUPP;
3188 }
8998576b 3189 }
4c3844d9
PB		 3190
3191 return 0;
8998576b
DL		 3192}
3193
3d486ec4
OS		 3194static bool modify_header_match_supported(struct mlx5e_priv *priv,
3195 struct mlx5_flow_spec *spec,
73867881 3196 struct flow_action *flow_action,
4c3844d9 3197 u32 actions, bool ct_flow,
7e36feeb 3198 bool ct_clear,
e98bedf5 3199 struct netlink_ext_ack *extack)
bdd66ac0 3200{
73867881 3201 const struct flow_action_entry *act;
7e36feeb 3202 bool modify_ip_header, modify_tuple;
fca53304 3203 void *headers_c;
bdd66ac0
OG		 3204 void *headers_v;
3205 u16 ethertype;
8998576b 3206 u8 ip_proto;
4c3844d9 3207 int i, err;
bdd66ac0 3208
fca53304 3209 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3210 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3211 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3212
3213 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3214 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3215 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3216 goto out_ok;
3217
3218 modify_ip_header = false;
7e36feeb 3219 modify_tuple = false;
73867881
PNA		 3220 flow_action_for_each(i, act, flow_action) {
3221 if (act->id != FLOW_ACTION_MANGLE &&
3222 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3223 continue;
3224
4c3844d9 3225 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3226 &modify_ip_header,
3227 &modify_tuple, extack);
4c3844d9
PB		 3228 if (err)
3229 return err;
bdd66ac0
OG		 3230 }
3231
7e36feeb
PB		 3232 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3233 * (or after clear action), as otherwise, since the tuple is changed,
3234 * we can't restore ct state
3235 */
3236 if (!ct_clear && modify_tuple &&
89fbdbae 3237 mlx5_tc_ct_add_no_trk_match(spec)) {
7e36feeb
PB		 3238 NL_SET_ERR_MSG_MOD(extack,
3239 "can't offload tuple modify header with ct matches");
3240 netdev_info(priv->netdev,
3241 "can't offload tuple modify header with ct matches");
3242 return false;
3243 }
3244
bdd66ac0 3245 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3246 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3247 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3248 NL_SET_ERR_MSG_MOD(extack,
3249 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3250 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3251 ip_proto);
bdd66ac0
OG		 3252 return false;
3253 }
3254
3255out_ok:
3256 return true;
3257}
3258
3259static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3260 struct flow_action *flow_action,
bdd66ac0 3261 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3262 struct mlx5e_tc_flow *flow,
3263 struct netlink_ext_ack *extack)
bdd66ac0 3264{
a7c119bd 3265 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3266 u32 actions;
3267
c620b772
AL		 3268 ct_clear = flow->attr->ct_attr.ct_action &
3269 TCA_CT_ACT_CLEAR;
3270 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3271 actions = flow->attr->action;
3272
4c3844d9 3273 if (mlx5e_is_eswitch_flow(flow)) {
c620b772 3274 if (flow->attr->esw_attr->split_count && ct_flow) {
4c3844d9
PB		 3275 /* All registers used by ct are cleared when using
3276 * split rules.
3277 */
3278 NL_SET_ERR_MSG_MOD(extack,
3279 "Can't offload mirroring with action ct");
49397b80 3280 return false;
4c3844d9 3281 }
4c3844d9 3282 }
bdd66ac0
OG		 3283
3284 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3285 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3286 flow_action, actions,
7e36feeb
PB		 3287 ct_flow, ct_clear,
3288 extack);
bdd66ac0
OG		 3289
3290 return true;
3291}
3292
32134847
MD		 3293static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3294{
3295 return priv->mdev == peer_priv->mdev;
3296}
3297
5c65c564
OG		 3298static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3299{
3300 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3301 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3302
3303 fmdev = priv->mdev;
3304 pmdev = peer_priv->mdev;
3305
59c9d35e
AH		 3306 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3307 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3308
816f6706 3309 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3310}
3311
bdc837ee
EB		 3312static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3313 const struct flow_action_entry *act,
3314 struct mlx5e_tc_flow_parse_attr *parse_attr,
3315 struct pedit_headers_action *hdrs,
3316 u32 *action, struct netlink_ext_ack *extack)
3317{
3318 u16 mask16 = VLAN_VID_MASK;
3319 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3320 const struct flow_action_entry pedit_act = {
3321 .id = FLOW_ACTION_MANGLE,
3322 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3323 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3324 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3325 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3326 };
6fca9d1e 3327 u8 match_prio_mask, match_prio_val;
bf2f3bca 3328 void *headers_c, *headers_v;
bdc837ee
EB		 3329 int err;
3330
bf2f3bca
EB		 3331 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3332 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3333
3334 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3335 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3336 NL_SET_ERR_MSG_MOD(extack,
3337 "VLAN rewrite action must have VLAN protocol match");
3338 return -EOPNOTSUPP;
3339 }
3340
6fca9d1e
EB		 3341 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3342 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3343 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3344 NL_SET_ERR_MSG_MOD(extack,
3345 "Changing VLAN prio is not supported");
bdc837ee
EB		 3346 return -EOPNOTSUPP;
3347 }
3348
582234b4 3349 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3350 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3351
3352 return err;
3353}
3354
0bac1194
EB		 3355static int
3356add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3357 struct mlx5e_tc_flow_parse_attr *parse_attr,
3358 struct pedit_headers_action *hdrs,
3359 u32 *action, struct netlink_ext_ack *extack)
3360{
3361 const struct flow_action_entry prio_tag_act = {
3362 .vlan.vid = 0,
3363 .vlan.prio =
3364 MLX5_GET(fte_match_set_lyr_2_4,
3365 get_match_headers_value(*action,
3366 &parse_attr->spec),
3367 first_prio) &
3368 MLX5_GET(fte_match_set_lyr_2_4,
3369 get_match_headers_criteria(*action,
3370 &parse_attr->spec),
3371 first_prio),
3372 };
3373
3374 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3375 &prio_tag_act, parse_attr, hdrs, action,
3376 extack);
3377}
3378
c7569097
AL		 3379static int validate_goto_chain(struct mlx5e_priv *priv,
3380 struct mlx5e_tc_flow *flow,
3381 const struct flow_action_entry *act,
3382 u32 actions,
3383 struct netlink_ext_ack *extack)
3384{
3385 bool is_esw = mlx5e_is_eswitch_flow(flow);
3386 struct mlx5_flow_attr *attr = flow->attr;
3387 bool ft_flow = mlx5e_is_ft_flow(flow);
3388 u32 dest_chain = act->chain_index;
3389 struct mlx5_fs_chains *chains;
3390 struct mlx5_eswitch *esw;
3391 u32 reformat_and_fwd;
3392 u32 max_chain;
3393
3394 esw = priv->mdev->priv.eswitch;
3395 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3396 max_chain = mlx5_chains_get_chain_range(chains);
3397 reformat_and_fwd = is_esw ?
3398 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3399 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3400
3401 if (ft_flow) {
3402 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3403 return -EOPNOTSUPP;
3404 }
3405
3406 if (!mlx5_chains_backwards_supported(chains) &&
3407 dest_chain <= attr->chain) {
3408 NL_SET_ERR_MSG_MOD(extack,
3409 "Goto lower numbered chain isn't supported");
3410 return -EOPNOTSUPP;
3411 }
3412
3413 if (dest_chain > max_chain) {
3414 NL_SET_ERR_MSG_MOD(extack,
3415 "Requested destination chain is out of supported range");
3416 return -EOPNOTSUPP;
3417 }
3418
3419 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3420 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3421 !reformat_and_fwd) {
3422 NL_SET_ERR_MSG_MOD(extack,
3423 "Goto chain is not allowed if action has reformat or decap");
3424 return -EOPNOTSUPP;
3425 }
3426
3427 return 0;
3428}
3429
73867881
PNA		 3430static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3431 struct flow_action *flow_action,
aa0cbbae 3432 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3433 struct mlx5e_tc_flow *flow,
3434 struct netlink_ext_ack *extack)
e3a2b7ed 3435{
c620b772 3436 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3437 struct pedit_headers_action hdrs[2] = {};
3438 const struct flow_action_entry *act;
c620b772 3439 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3440 u32 action = 0;
244cd96a 3441 int err, i;
e3a2b7ed 3442
73867881 3443 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3444 return -EINVAL;
3445
53eca1f3
JK		 3446 if (!flow_action_hw_stats_check(flow_action, extack,
3447 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3448 return -EOPNOTSUPP;
3449
c620b772
AL		 3450 nic_attr = attr->nic_attr;
3451
3452 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3453
73867881
PNA		 3454 flow_action_for_each(i, act, flow_action) {
3455 switch (act->id) {
15fc92ec
TZ		 3456 case FLOW_ACTION_ACCEPT:
3457 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3458 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3459 break;
73867881 3460 case FLOW_ACTION_DROP:
1cab1cd7 3461 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3462 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3463 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3464 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3465 break;
3466 case FLOW_ACTION_MANGLE:
3467 case FLOW_ACTION_ADD:
3468 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3469 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3470 if (err)
3471 return err;
3472
c7569097 3473 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3474 break;
bdc837ee
EB		 3475 case FLOW_ACTION_VLAN_MANGLE:
3476 err = add_vlan_rewrite_action(priv,
3477 MLX5_FLOW_NAMESPACE_KERNEL,
3478 act, parse_attr, hdrs,
3479 &action, extack);
3480 if (err)
3481 return err;
3482
3483 break;
73867881 3484 case FLOW_ACTION_CSUM:
1cab1cd7 3485 if (csum_offload_supported(priv, action,
73867881 3486 act->csum_flags,
e98bedf5 3487 extack))
73867881 3488 break;
26c02749
OG		 3489
3490 return -EOPNOTSUPP;
73867881
PNA		 3491 case FLOW_ACTION_REDIRECT: {
3492 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3493
3494 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3495 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3496 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3497 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3498 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3499 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3500 } else {
e98bedf5
EB		 3501 NL_SET_ERR_MSG_MOD(extack,
3502 "device is not on same HW, can't offload");
5c65c564
OG		 3503 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3504 peer_dev->name);
3505 return -EINVAL;
3506 }
73867881
PNA		 3507 }
3508 break;
3509 case FLOW_ACTION_MARK: {
3510 u32 mark = act->mark;
e3a2b7ed
AV		 3511
3512 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3513 NL_SET_ERR_MSG_MOD(extack,
3514 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3515 return -EINVAL;
3516 }
3517
c620b772 3518 nic_attr->flow_tag = mark;
1cab1cd7 3519 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3520 }
3521 break;
c7569097
AL		 3522 case FLOW_ACTION_GOTO:
3523 err = validate_goto_chain(priv, flow, act, action,
3524 extack);
3525 if (err)
3526 return err;
3527
3528 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3529 attr->dest_chain = act->chain_index;
3530 break;
aedd133d
AL		 3531 case FLOW_ACTION_CT:
3532 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3533 if (err)
3534 return err;
3535
3536 flow_flag_set(flow, CT);
3537 break;
73867881 3538 default:
2cc1cb1d
TZ		 3539 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3540 return -EOPNOTSUPP;
e3a2b7ed 3541 }
e3a2b7ed
AV		 3542 }
3543
c500c86b
PNA		 3544 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3545 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3546 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3547 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3548 if (err)
3549 return err;
27c11b6b
EB		 3550 /* in case all pedit actions are skipped, remove the MOD_HDR
3551 * flag.
3552 */
6ae4a6a5 3553 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3554 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3555 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3556 }
c500c86b
PNA		 3557 }
3558
1cab1cd7 3559 attr->action = action;
c7569097
AL		 3560
3561 if (attr->dest_chain) {
3562 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3563 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3564 return -EOPNOTSUPP;
3565 }
3566 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3567 }
3568
3569 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3570 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3571
73867881 3572 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3573 return -EOPNOTSUPP;
3574
e3a2b7ed
AV		 3575 return 0;
3576}
3577
7f1a546e 3578struct encap_key {
1f6da306 3579 const struct ip_tunnel_key *ip_tun_key;
d386939a 3580 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3581};
3582
3583static inline int cmp_encap_info(struct encap_key *a,
3584 struct encap_key *b)
a54e20b4 3585{
7f1a546e 3586 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3587 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3588}
3589
14e6b038
EC		 3590static inline int cmp_decap_info(struct mlx5e_decap_key *a,
3591 struct mlx5e_decap_key *b)
3592{
3593 return memcmp(&a->key, &b->key, sizeof(b->key));
3594}
3595
7f1a546e 3596static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3597{
7f1a546e 3598 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3599 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3600}
3601
14e6b038
EC		 3602static inline int hash_decap_info(struct mlx5e_decap_key *key)
3603{
3604 return jhash(&key->key, sizeof(key->key), 0);
3605}
a54e20b4 3606
32134847 3607static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3608 struct net_device *peer_netdev)
3609{
3610 struct mlx5e_priv *peer_priv;
3611
3612 peer_priv = netdev_priv(peer_netdev);
3613
3614 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3615 mlx5e_eswitch_vf_rep(priv->netdev) &&
3616 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3617 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3618}
3619
948993f2
VB		 3620bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3621{
3622 return refcount_inc_not_zero(&e->refcnt);
3623}
3624
14e6b038
EC		 3625static bool mlx5e_decap_take(struct mlx5e_decap_entry *e)
3626{
3627 return refcount_inc_not_zero(&e->refcnt);
3628}
3629
948993f2
VB		 3630static struct mlx5e_encap_entry *
3631mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3632 uintptr_t hash_key)
3633{
3634 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3635 struct mlx5e_encap_entry *e;
3636 struct encap_key e_key;
3637
3638 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3639 encap_hlist, hash_key) {
3640 e_key.ip_tun_key = &e->tun_info->key;
3641 e_key.tc_tunnel = e->tunnel;
3642 if (!cmp_encap_info(&e_key, key) &&
3643 mlx5e_encap_take(e))
3644 return e;
3645 }
3646
3647 return NULL;
3648}
3649
14e6b038
EC		 3650static struct mlx5e_decap_entry *
3651mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key,
3652 uintptr_t hash_key)
3653{
3654 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3655 struct mlx5e_decap_key r_key;
3656 struct mlx5e_decap_entry *e;
3657
3658 hash_for_each_possible_rcu(esw->offloads.decap_tbl, e,
3659 hlist, hash_key) {
3660 r_key = e->key;
3661 if (!cmp_decap_info(&r_key, key) &&
3662 mlx5e_decap_take(e))
3663 return e;
3664 }
3665 return NULL;
3666}
3667
2a4b6526
VB		 3668static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3669{
3670 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3671
3672 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3673}
3674
554fe75c
DL		 3675static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3676 struct mlx5e_tc_flow *flow,
3677 int out_index,
3678 struct mlx5e_encap_entry *e,
3679 struct netlink_ext_ack *extack)
3680{
3681 int i;
3682
3683 for (i = 0; i < out_index; i++) {
3684 if (flow->encaps[i].e != e)
3685 continue;
3686 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3687 netdev_err(priv->netdev, "can't duplicate encap action\n");
3688 return true;
3689 }
3690
3691 return false;
3692}
3693
a54e20b4 3694static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3695 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3696 struct net_device *mirred_dev,
3697 int out_index,
8c4dc42b 3698 struct netlink_ext_ack *extack,
0ad060ee
RD		 3699 struct net_device **encap_dev,
3700 bool *encap_valid)
a54e20b4
HHZ		 3701{
3702 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
733d4f36 3703 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3704 struct mlx5_flow_attr *attr = flow->attr;
1f6da306 3705 const struct ip_tunnel_info *tun_info;
948993f2 3706 struct encap_key key;
c1ae1152 3707 struct mlx5e_encap_entry *e;
733d4f36 3708 unsigned short family;
a54e20b4 3709 uintptr_t hash_key;
54c177ca 3710 int err = 0;
a54e20b4 3711
733d4f36 3712 parse_attr = attr->parse_attr;
1f6da306 3713 tun_info = parse_attr->tun_info[out_index];
733d4f36 3714 family = ip_tunnel_info_af(tun_info);
7f1a546e 3715 key.ip_tun_key = &tun_info->key;
d386939a 3716 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3717 if (!key.tc_tunnel) {
3718 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3719 return -EOPNOTSUPP;
3720 }
733d4f36 3721
7f1a546e 3722 hash_key = hash_encap_info(&key);
a54e20b4 3723
61086f39 3724 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3725 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3726
b2812089 3727 /* must verify if encap is valid or not */
d589e785 3728 if (e) {
554fe75c
DL		 3729 /* Check that entry was not already attached to this flow */
3730 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3731 err = -EOPNOTSUPP;
3732 goto out_err;
3733 }
3734
d589e785
VB		 3735 mutex_unlock(&esw->offloads.encap_tbl_lock);
3736 wait_for_completion(&e->res_ready);
3737
3738 /* Protect against concurrent neigh update. */
3739 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3740 if (e->compl_result < 0) {
d589e785
VB		 3741 err = -EREMOTEIO;
3742 goto out_err;
3743 }
45247bf2 3744 goto attach_flow;
d589e785 3745 }
a54e20b4
HHZ		 3746
3747 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3748 if (!e) {
3749 err = -ENOMEM;
3750 goto out_err;
3751 }
a54e20b4 3752
948993f2 3753 refcount_set(&e->refcnt, 1);
d589e785
VB		 3754 init_completion(&e->res_ready);
3755
2a4b6526
VB		 3756 tun_info = dup_tun_info(tun_info);
3757 if (!tun_info) {
3758 err = -ENOMEM;
3759 goto out_err_init;
3760 }
1f6da306 3761 e->tun_info = tun_info;
101f4de9 3762 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3763 if (err)
3764 goto out_err_init;
54c177ca 3765
a54e20b4 3766 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3767 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3768 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3769
ce99f6b9 3770 if (family == AF_INET)
101f4de9 3771 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3772 else if (family == AF_INET6)
101f4de9 3773 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3774
d589e785
VB		 3775 /* Protect against concurrent neigh update. */
3776 mutex_lock(&esw->offloads.encap_tbl_lock);
3777 complete_all(&e->res_ready);
3778 if (err) {
3779 e->compl_result = err;
a54e20b4 3780 goto out_err;
d589e785 3781 }
3c140dd5 3782 e->compl_result = 1;
a54e20b4 3783
45247bf2 3784attach_flow:
948993f2 3785 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3786 list_add(&flow->encaps[out_index].list, &e->flows);
3787 flow->encaps[out_index].index = out_index;
45247bf2 3788 *encap_dev = e->out_dev;
8c4dc42b 3789 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
c620b772
AL		 3790 attr->esw_attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3791 attr->esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3792 *encap_valid = true;
8c4dc42b 3793 } else {
0ad060ee 3794 *encap_valid = false;
8c4dc42b 3795 }
61086f39 3796 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3797
232c0013 3798 return err;
a54e20b4
HHZ		 3799
3800out_err:
61086f39 3801 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3802 if (e)
3803 mlx5e_encap_put(priv, e);
a54e20b4 3804 return err;
2a4b6526
VB		 3805
3806out_err_init:
3807 mutex_unlock(&esw->offloads.encap_tbl_lock);
3808 kfree(tun_info);
3809 kfree(e);
3810 return err;
a54e20b4
HHZ		 3811}
3812
14e6b038
EC		 3813static int mlx5e_attach_decap(struct mlx5e_priv *priv,
3814 struct mlx5e_tc_flow *flow,
3815 struct netlink_ext_ack *extack)
3816{
3817 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3818 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
14e6b038
EC		 3819 struct mlx5e_tc_flow_parse_attr *parse_attr;
3820 struct mlx5e_decap_entry *d;
3821 struct mlx5e_decap_key key;
3822 uintptr_t hash_key;
28619046 3823 int err = 0;
14e6b038 3824
c620b772 3825 parse_attr = flow->attr->parse_attr;
14e6b038
EC		 3826 if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {
3827 NL_SET_ERR_MSG_MOD(extack,
3828 "encap header larger than max supported");
3829 return -EOPNOTSUPP;
3830 }
3831
3832 key.key = parse_attr->eth;
3833 hash_key = hash_decap_info(&key);
3834 mutex_lock(&esw->offloads.decap_tbl_lock);
3835 d = mlx5e_decap_get(priv, &key, hash_key);
3836 if (d) {
3837 mutex_unlock(&esw->offloads.decap_tbl_lock);
3838 wait_for_completion(&d->res_ready);
3839 mutex_lock(&esw->offloads.decap_tbl_lock);
3840 if (d->compl_result) {
3841 err = -EREMOTEIO;
3842 goto out_free;
3843 }
3844 goto found;
3845 }
3846
3847 d = kzalloc(sizeof(*d), GFP_KERNEL);
3848 if (!d) {
3849 err = -ENOMEM;
3850 goto out_err;
3851 }
3852
3853 d->key = key;
3854 refcount_set(&d->refcnt, 1);
3855 init_completion(&d->res_ready);
3856 INIT_LIST_HEAD(&d->flows);
3857 hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key);
3858 mutex_unlock(&esw->offloads.decap_tbl_lock);
3859
3860 d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
3861 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2,
3862 sizeof(parse_attr->eth),
3863 &parse_attr->eth,
3864 MLX5_FLOW_NAMESPACE_FDB);
3865 if (IS_ERR(d->pkt_reformat)) {
3866 err = PTR_ERR(d->pkt_reformat);
3867 d->compl_result = err;
3868 }
3869 mutex_lock(&esw->offloads.decap_tbl_lock);
3870 complete_all(&d->res_ready);
3871 if (err)
3872 goto out_free;
3873
3874found:
3875 flow->decap_reformat = d;
3876 attr->decap_pkt_reformat = d->pkt_reformat;
3877 list_add(&flow->l3_to_l2_reformat, &d->flows);
3878 mutex_unlock(&esw->offloads.decap_tbl_lock);
3879 return 0;
3880
3881out_free:
3882 mutex_unlock(&esw->offloads.decap_tbl_lock);
3883 mlx5e_decap_put(priv, d);
3884 return err;
3885
3886out_err:
3887 mutex_unlock(&esw->offloads.decap_tbl_lock);
3888 return err;
3889}
3890
1482bd3d 3891static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3892 const struct flow_action_entry *act,
1482bd3d
JL		 3893 struct mlx5_esw_flow_attr *attr,
3894 u32 *action)
3895{
cc495188
JL		 3896 u8 vlan_idx = attr->total_vlan;
3897
3898 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3899 return -EOPNOTSUPP;
3900
73867881
PNA		 3901 switch (act->id) {
3902 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3903 if (vlan_idx) {
3904 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3905 MLX5_FS_VLAN_DEPTH))
3906 return -EOPNOTSUPP;
3907
3908 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3909 } else {
3910 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3911 }
73867881
PNA		 3912 break;
3913 case FLOW_ACTION_VLAN_PUSH:
3914 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3915 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3916 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3917 if (!attr->vlan_proto[vlan_idx])
3918 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3919
3920 if (vlan_idx) {
3921 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3922 MLX5_FS_VLAN_DEPTH))
3923 return -EOPNOTSUPP;
3924
3925 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3926 } else {
3927 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3928 (act->vlan.proto != htons(ETH_P_8021Q) ||
3929 act->vlan.prio))
cc495188
JL		 3930 return -EOPNOTSUPP;
3931
3932 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3933 }
73867881
PNA		 3934 break;
3935 default:
bdc837ee 3936 return -EINVAL;
1482bd3d
JL		 3937 }
3938
cc495188
JL		 3939 attr->total_vlan = vlan_idx + 1;
3940
1482bd3d
JL		 3941 return 0;
3942}
3943
d34eb2fc
OG		 3944static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3945 struct net_device *out_dev)
3946{
3947 struct net_device *fdb_out_dev = out_dev;
3948 struct net_device *uplink_upper;
3949
3950 rcu_read_lock();
3951 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3952 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3953 uplink_upper == out_dev) {
3954 fdb_out_dev = uplink_dev;
3955 } else if (netif_is_lag_master(out_dev)) {
3956 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3957 if (fdb_out_dev &&
3958 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3959 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3960 fdb_out_dev = NULL;
3961 }
3962 rcu_read_unlock();
3963 return fdb_out_dev;
3964}
3965
278748a9 3966static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3967 struct mlx5_flow_attr *attr,
278748a9
EB		 3968 struct net_device **out_dev,
3969 u32 *action)
3970{
3971 struct net_device *vlan_dev = *out_dev;
3972 struct flow_action_entry vlan_act = {
3973 .id = FLOW_ACTION_VLAN_PUSH,
3974 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3975 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3976 .vlan.prio = 0,
3977 };
3978 int err;
3979
c620b772 3980 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3981 if (err)
3982 return err;
3983
3984 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3985 dev_get_iflink(vlan_dev));
3986 if (is_vlan_dev(*out_dev))
3987 err = add_vlan_push_action(priv, attr, out_dev, action);
3988
3989 return err;
3990}
3991
35a605db 3992static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3993 struct mlx5_flow_attr *attr,
35a605db
EB		 3994 u32 *action)
3995{
35a605db
EB		 3996 struct flow_action_entry vlan_act = {
3997 .id = FLOW_ACTION_VLAN_POP,
3998 };
70f478ca 3999 int nest_level, err = 0;
35a605db 4000
70f478ca
DL		 4001 nest_level = attr->parse_attr->filter_dev->lower_level -
4002 priv->netdev->lower_level;
35a605db 4003 while (nest_level--) {
c620b772 4004 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 4005 if (err)
4006 return err;
4007 }
4008
4009 return err;
4010}
4011
32134847
MD		 4012static bool same_hw_reps(struct mlx5e_priv *priv,
4013 struct net_device *peer_netdev)
4014{
4015 struct mlx5e_priv *peer_priv;
4016
4017 peer_priv = netdev_priv(peer_netdev);
4018
4019 return mlx5e_eswitch_rep(priv->netdev) &&
4020 mlx5e_eswitch_rep(peer_netdev) &&
4021 same_hw_devs(priv, peer_priv);
4022}
4023
4024static bool is_lag_dev(struct mlx5e_priv *priv,
4025 struct net_device *peer_netdev)
4026{
4027 return ((mlx5_lag_is_sriov(priv->mdev) ||
4028 mlx5_lag_is_multipath(priv->mdev)) &&
4029 same_hw_reps(priv, peer_netdev));
4030}
4031
f6dc1264
PB		 4032bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4033 struct net_device *out_dev)
4034{
32134847
MD		 4035 if (is_merged_eswitch_vfs(priv, out_dev))
4036 return true;
4037
4038 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 4039 return true;
4040
4041 return mlx5e_eswitch_rep(out_dev) &&
32134847 4042 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 4043}
4044
554fe75c
DL		 4045static bool is_duplicated_output_device(struct net_device *dev,
4046 struct net_device *out_dev,
4047 int *ifindexes, int if_count,
4048 struct netlink_ext_ack *extack)
4049{
4050 int i;
4051
4052 for (i = 0; i < if_count; i++) {
4053 if (ifindexes[i] == out_dev->ifindex) {
4054 NL_SET_ERR_MSG_MOD(extack,
4055 "can't duplicate output to same device");
4056 netdev_err(dev, "can't duplicate output to same device: %s\n",
4057 out_dev->name);
4058 return true;
4059 }
4060 }
4061
4062 return false;
4063}
4064
613f53fe
EC		 4065static int verify_uplink_forwarding(struct mlx5e_priv *priv,
4066 struct mlx5e_tc_flow *flow,
4067 struct net_device *out_dev,
4068 struct netlink_ext_ack *extack)
4069{
c620b772 4070 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 4071 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 4072 struct mlx5e_rep_priv *rep_priv;
4073
4074 /* Forwarding non encapsulated traffic between
4075 * uplink ports is allowed only if
4076 * termination_table_raw_traffic cap is set.
4077 *
c620b772 4078 * Input vport was stored attr->in_rep.
613f53fe
EC		 4079 * In LAG case, *priv* is the private data of
4080 * uplink which may be not the input vport.
4081 */
4082 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
4083
4084 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
4085 mlx5e_eswitch_uplink_rep(out_dev)))
4086 return 0;
4087
4088 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
4089 termination_table_raw_traffic)) {
4090 NL_SET_ERR_MSG_MOD(extack,
4091 "devices are both uplink, can't offload forwarding");
4092 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
4093 priv->netdev->name, out_dev->name);
4094 return -EOPNOTSUPP;
4095 } else if (out_dev != rep_priv->netdev) {
4096 NL_SET_ERR_MSG_MOD(extack,
4097 "devices are not the same uplink, can't offload forwarding");
4098 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
4099 priv->netdev->name, out_dev->name);
4100 return -EOPNOTSUPP;
4101 }
4102 return 0;
4103}
4104
73867881
PNA		 4105static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
4106 struct flow_action *flow_action,
e98bedf5 4107 struct mlx5e_tc_flow *flow,
14e6b038
EC		 4108 struct netlink_ext_ack *extack,
4109 struct net_device *filter_dev)
03a9d11e 4110{
73867881 4111 struct pedit_headers_action hdrs[2] = {};
bf07aa73 4112 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4113 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 4114 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 4115 const struct ip_tunnel_info *info = NULL;
c620b772 4116 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 4117 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 4118 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 4119 const struct flow_action_entry *act;
c620b772 4120 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 4121 bool encap = false, decap = false;
4122 u32 action = attr->action;
554fe75c 4123 int err, i, if_count = 0;
f828ca6a 4124 bool mpls_push = false;
03a9d11e 4125
73867881 4126 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 4127 return -EINVAL;
4128
53eca1f3
JK		 4129 if (!flow_action_hw_stats_check(flow_action, extack,
4130 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 4131 return -EOPNOTSUPP;
4132
c620b772
AL		 4133 esw_attr = attr->esw_attr;
4134 parse_attr = attr->parse_attr;
4135
73867881
PNA		 4136 flow_action_for_each(i, act, flow_action) {
4137 switch (act->id) {
4138 case FLOW_ACTION_DROP:
1cab1cd7
OG		 4139 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
4140 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 4141 break;
f0288210
EC		 4142 case FLOW_ACTION_TRAP:
4143 if (!flow_offload_has_one_action(flow_action)) {
4144 NL_SET_ERR_MSG_MOD(extack,
4145 "action trap is supported as a sole action only");
4146 return -EOPNOTSUPP;
4147 }
4148 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4149 MLX5_FLOW_CONTEXT_ACTION_COUNT);
4150 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
4151 break;
f828ca6a
EC		 4152 case FLOW_ACTION_MPLS_PUSH:
4153 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
4154 reformat_l2_to_l3_tunnel) ||
4155 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
4156 NL_SET_ERR_MSG_MOD(extack,
4157 "mpls push is supported only for mpls_uc protocol");
4158 return -EOPNOTSUPP;
4159 }
4160 mpls_push = true;
4161 break;
14e6b038
EC		 4162 case FLOW_ACTION_MPLS_POP:
4163 /* we only support mpls pop if it is the first action
4164 * and the filter net device is bareudp. Subsequent
4165 * actions can be pedit and the last can be mirred
4166 * egress redirect.
4167 */
4168 if (i) {
4169 NL_SET_ERR_MSG_MOD(extack,
4170 "mpls pop supported only as first action");
4171 return -EOPNOTSUPP;
4172 }
4173 if (!netif_is_bareudp(filter_dev)) {
4174 NL_SET_ERR_MSG_MOD(extack,
4175 "mpls pop supported only on bareudp devices");
4176 return -EOPNOTSUPP;
4177 }
4178
4179 parse_attr->eth.h_proto = act->mpls_pop.proto;
4180 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
4181 flow_flag_set(flow, L3_TO_L2_DECAP);
4182 break;
73867881
PNA		 4183 case FLOW_ACTION_MANGLE:
4184 case FLOW_ACTION_ADD:
4185 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 4186 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 4187 if (err)
4188 return err;
4189
582234b4
EC		 4190 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
4191 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 4192 esw_attr->split_count = esw_attr->out_count;
582234b4 4193 }
73867881
PNA		 4194 break;
4195 case FLOW_ACTION_CSUM:
1cab1cd7 4196 if (csum_offload_supported(priv, action,
73867881
PNA		 4197 act->csum_flags, extack))
4198 break;
26c02749
OG		 4199
4200 return -EOPNOTSUPP;
73867881
PNA		 4201 case FLOW_ACTION_REDIRECT:
4202 case FLOW_ACTION_MIRRED: {
03a9d11e 4203 struct mlx5e_priv *out_priv;
592d3651 4204 struct net_device *out_dev;
03a9d11e 4205
73867881 4206 out_dev = act->dev;
ef381359
OS		 4207 if (!out_dev) {
4208 /* out_dev is NULL when filters with
4209 * non-existing mirred device are replayed to
4210 * the driver.
4211 */
4212 return -EINVAL;
4213 }
03a9d11e 4214
f828ca6a
EC		 4215 if (mpls_push && !netif_is_bareudp(out_dev)) {
4216 NL_SET_ERR_MSG_MOD(extack,
4217 "mpls is supported only through a bareudp device");
4218 return -EOPNOTSUPP;
4219 }
4220
84179981
PB		 4221 if (ft_flow && out_dev == priv->netdev) {
4222 /* Ignore forward to self rules generated
4223 * by adding both mlx5 devs to the flow table
4224 * block on a normal nft offload setup.
4225 */
4226 return -EOPNOTSUPP;
4227 }
4228
c620b772 4229 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 4230 NL_SET_ERR_MSG_MOD(extack,
4231 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 4232 netdev_warn(priv->netdev,
4233 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 4234 esw_attr->out_count);
592d3651
CM		 4235 return -EOPNOTSUPP;
4236 }
4237
f493f155
EB		 4238 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4239 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 4240 if (encap) {
c620b772 4241 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 4242 out_dev->ifindex;
c620b772
AL		 4243 parse_attr->tun_info[esw_attr->out_count] = dup_tun_info(info);
4244 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 4245 return -ENOMEM;
4246 encap = false;
c620b772 4247 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 4248 MLX5_ESW_DEST_ENCAP;
c620b772 4249 esw_attr->out_count++;
b6a4ac24
VB		 4250 /* attr->dests[].rep is resolved when we
4251 * handle encap
4252 */
4253 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 4254 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4255 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 4256
554fe75c
DL		 4257 if (is_duplicated_output_device(priv->netdev,
4258 out_dev,
4259 ifindexes,
4260 if_count,
4261 extack))
4262 return -EOPNOTSUPP;
4263
4264 ifindexes[if_count] = out_dev->ifindex;
4265 if_count++;
4266
d34eb2fc
OG		 4267 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4268 if (!out_dev)
4269 return -ENODEV;
7ba58ba7 4270
278748a9
EB		 4271 if (is_vlan_dev(out_dev)) {
4272 err = add_vlan_push_action(priv, attr,
4273 &out_dev,
4274 &action);
4275 if (err)
4276 return err;
4277 }
f6dc1264 4278
35a605db
EB		 4279 if (is_vlan_dev(parse_attr->filter_dev)) {
4280 err = add_vlan_pop_action(priv, attr,
4281 &action);
4282 if (err)
4283 return err;
4284 }
278748a9 4285
613f53fe
EC		 4286 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4287 if (err)
4288 return err;
ffec9702 4289
f6dc1264
PB		 4290 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4291 NL_SET_ERR_MSG_MOD(extack,
4292 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4293 return -EOPNOTSUPP;
f6dc1264 4294 }
a0646c88 4295
a54e20b4 4296 out_priv = netdev_priv(out_dev);
1d447a39 4297 rpriv = out_priv->ppriv;
c620b772
AL		 4298 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
4299 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
4300 esw_attr->out_count++;
ef381359
OS		 4301 } else if (parse_attr->filter_dev != priv->netdev) {
4302 /* All mlx5 devices are called to configure
4303 * high level device filters. Therefore, the
4304 * *attempt* to install a filter on invalid
4305 * eswitch should not trigger an explicit error
4306 */
4307 return -EINVAL;
a54e20b4 4308 } else {
e98bedf5
EB		 4309 NL_SET_ERR_MSG_MOD(extack,
4310 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4311 netdev_warn(priv->netdev,
4312 "devices %s %s not on same switch HW, can't offload forwarding\n",
4313 priv->netdev->name,
4314 out_dev->name);
03a9d11e
OG		 4315 return -EINVAL;
4316 }
73867881
PNA		 4317 }
4318 break;
4319 case FLOW_ACTION_TUNNEL_ENCAP:
4320 info = act->tunnel;
a54e20b4
HHZ		 4321 if (info)
4322 encap = true;
4323 else
4324 return -EOPNOTSUPP;
1482bd3d 4325
73867881
PNA		 4326 break;
4327 case FLOW_ACTION_VLAN_PUSH:
4328 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4329 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4330 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4331 /* Replace vlan pop+push with vlan modify */
4332 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4333 err = add_vlan_rewrite_action(priv,
4334 MLX5_FLOW_NAMESPACE_FDB,
4335 act, parse_attr, hdrs,
4336 &action, extack);
4337 } else {
c620b772 4338 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 4339 }
1482bd3d
JL		 4340 if (err)
4341 return err;
4342
c620b772 4343 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 4344 break;
4345 case FLOW_ACTION_VLAN_MANGLE:
4346 err = add_vlan_rewrite_action(priv,
4347 MLX5_FLOW_NAMESPACE_FDB,
4348 act, parse_attr, hdrs,
4349 &action, extack);
4350 if (err)
4351 return err;
4352
c620b772 4353 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 4354 break;
4355 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4356 decap = true;
73867881 4357 break;
2fbbc30d 4358 case FLOW_ACTION_GOTO:
c7569097
AL		 4359 err = validate_goto_chain(priv, flow, act, action,
4360 extack);
2fbbc30d
EC		 4361 if (err)
4362 return err;
bf07aa73 4363
e88afe75 4364 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4365 attr->dest_chain = act->chain_index;
73867881 4366 break;
4c3844d9 4367 case FLOW_ACTION_CT:
aedd133d 4368 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4369 if (err)
4370 return err;
4371
4372 flow_flag_set(flow, CT);
4373 break;
73867881 4374 default:
2cc1cb1d
TZ		 4375 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4376 return -EOPNOTSUPP;
bf07aa73 4377 }
03a9d11e 4378 }
bdd66ac0 4379
0bac1194
EB		 4380 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4381 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4382 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4383 * tag rewrite.
4384 */
4385 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4386 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4387 &action, extack);
4388 if (err)
4389 return err;
4390 }
4391
c500c86b
PNA		 4392 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4393 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4394 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4395 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4396 if (err)
4397 return err;
27c11b6b
EB		 4398 /* in case all pedit actions are skipped, remove the MOD_HDR
4399 * flag. we might have set split_count either by pedit or
4400 * pop/push. if there is no pop/push either, reset it too.
4401 */
6ae4a6a5 4402 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4403 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4404 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4405 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4406 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4407 esw_attr->split_count = 0;
27c11b6b 4408 }
c500c86b
PNA		 4409 }
4410
1cab1cd7 4411 attr->action = action;
73867881 4412 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4413 return -EOPNOTSUPP;
4414
e88afe75 4415 if (attr->dest_chain) {
0a7fcb78
PB		 4416 if (decap) {
4417 /* It can be supported if we'll create a mapping for
4418 * the tunnel device only (without tunnel), and set
4419 * this tunnel id with this decap flow.
4420 *
4421 * On restore (miss), we'll just set this saved tunnel
4422 * device.
4423 */
4424
4425 NL_SET_ERR_MSG(extack,
4426 "Decap with goto isn't supported");
4427 netdev_warn(priv->netdev,
4428 "Decap with goto isn't supported");
4429 return -EOPNOTSUPP;
4430 }
4431
e88afe75 4432 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 4433 NL_SET_ERR_MSG_MOD(extack,
4434 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 4435 return -EOPNOTSUPP;
4436 }
4437 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4438 }
4439
ae2741e2
VB		 4440 if (!(attr->action &
4441 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4442 NL_SET_ERR_MSG_MOD(extack,
4443 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4444 return -EOPNOTSUPP;
4445 }
4446
c620b772 4447 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4448 NL_SET_ERR_MSG_MOD(extack,
4449 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4450 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4451 return -EOPNOTSUPP;
4452 }
4453
31c8eba5 4454 return 0;
03a9d11e
OG		 4455}
4456
226f2ca3 4457static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4458{
226f2ca3 4459 unsigned long __flow_flags = 0;
60bd4af8 4460
226f2ca3
VB		 4461 if (flags & MLX5_TC_FLAG(INGRESS))
4462 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4463 if (flags & MLX5_TC_FLAG(EGRESS))
4464 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4465
226f2ca3
VB		 4466 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4467 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4468 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4469 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4470 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4471 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4472
60bd4af8
OG		 4473 *flow_flags = __flow_flags;
4474}
4475
05866c82
OG		 4476static const struct rhashtable_params tc_ht_params = {
4477 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4478 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4479 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4480 .automatic_shrinking = true,
4481};
4482
226f2ca3
VB		 4483static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4484 unsigned long flags)
05866c82 4485{
655dc3d2
OG		 4486 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4487 struct mlx5e_rep_priv *uplink_rpriv;
4488
226f2ca3 4489 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4490 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4491 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4492 } else /* NIC offload */
655dc3d2 4493 return &priv->fs.tc.ht;
05866c82
OG		 4494}
4495
04de7dda
RD		 4496static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4497{
c620b772
AL		 4498 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4499 struct mlx5_flow_attr *attr = flow->attr;
4500 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4501 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4502 bool act_is_encap = !!(attr->action &
4503 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4504 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4505 MLX5_DEVCOM_ESW_OFFLOADS);
4506
10fbb1cd
RD		 4507 if (!esw_paired)
4508 return false;
4509
c620b772
AL		 4510 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4511 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4512 (is_rep_ingress || act_is_encap))
4513 return true;
4514
4515 return false;
04de7dda
RD		 4516}
4517
c620b772
AL		 4518struct mlx5_flow_attr *
4519mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4520{
4521 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4522 sizeof(struct mlx5_esw_flow_attr) :
4523 sizeof(struct mlx5_nic_flow_attr);
4524 struct mlx5_flow_attr *attr;
4525
4526 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4527}
4528
a88780a9
RD		 4529static int
4530mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4531 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4532 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4533 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4534{
17091853 4535 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4536 struct mlx5_flow_attr *attr;
3bc4b7bf 4537 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4538 int err = -ENOMEM;
4539 int out_index;
e3a2b7ed 4540
c620b772 4541 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4542 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4543 if (!parse_attr || !flow)
4544 goto err_free;
c620b772
AL		 4545
4546 flow->flags = flow_flags;
4547 flow->cookie = f->cookie;
4548 flow->priv = priv;
4549
4550 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4551 if (!attr)
e3a2b7ed 4552 goto err_free;
ff7ea04a 4553
c620b772 4554 flow->attr = attr;
e3a2b7ed 4555
5a7e5bcb
VB		 4556 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4557 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4558 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4559 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4560 refcount_set(&flow->refcnt, 1);
95435ad7 4561 init_completion(&flow->init_done);
e3a2b7ed 4562
a88780a9
RD		 4563 *__flow = flow;
4564 *__parse_attr = parse_attr;
4565
4566 return 0;
4567
4568err_free:
4569 kfree(flow);
4570 kvfree(parse_attr);
4571 return err;
4572}
4573
c7569097
AL		 4574static void
4575mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4576 struct mlx5e_tc_flow_parse_attr *parse_attr,
4577 struct flow_cls_offload *f)
4578{
4579 attr->parse_attr = parse_attr;
4580 attr->chain = f->common.chain_index;
4581 attr->prio = f->common.prio;
4582}
4583
988ab9c7 4584static void
c620b772 4585mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4586 struct mlx5e_priv *priv,
4587 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4588 struct flow_cls_offload *f,
988ab9c7
TZ		 4589 struct mlx5_eswitch_rep *in_rep,
4590 struct mlx5_core_dev *in_mdev)
4591{
4592 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4593 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4594
c7569097 4595 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4596
4597 esw_attr->in_rep = in_rep;
4598 esw_attr->in_mdev = in_mdev;
4599
4600 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4601 MLX5_COUNTER_SOURCE_ESWITCH)
4602 esw_attr->counter_dev = in_mdev;
4603 else
4604 esw_attr->counter_dev = priv->mdev;
4605}
4606
71129676 4607static struct mlx5e_tc_flow *
04de7dda 4608__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4609 struct flow_cls_offload *f,
226f2ca3 4610 unsigned long flow_flags,
04de7dda
RD		 4611 struct net_device *filter_dev,
4612 struct mlx5_eswitch_rep *in_rep,
71129676 4613 struct mlx5_core_dev *in_mdev)
a88780a9 4614{
f9e30088 4615 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4616 struct netlink_ext_ack *extack = f->common.extack;
4617 struct mlx5e_tc_flow_parse_attr *parse_attr;
4618 struct mlx5e_tc_flow *flow;
4619 int attr_size, err;
e3a2b7ed 4620
226f2ca3 4621 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4622 attr_size = sizeof(struct mlx5_esw_flow_attr);
4623 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4624 &parse_attr, &flow);
4625 if (err)
4626 goto out;
988ab9c7 4627
d11afc26 4628 parse_attr->filter_dev = filter_dev;
c620b772 4629 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4630 priv, parse_attr,
4631 f, in_rep, in_mdev);
4632
54c177ca
OS		 4633 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4634 f, filter_dev);
d11afc26
OS		 4635 if (err)
4636 goto err_free;
a88780a9 4637
7e36feeb 4638 /* actions validation depends on parsing the ct matches first */
aedd133d 4639 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4640 &flow->attr->ct_attr, extack);
a88780a9
RD		 4641 if (err)
4642 goto err_free;
4643
7e36feeb 4644 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4645 if (err)
4646 goto err_free;
4647
7040632d 4648 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4649 complete_all(&flow->init_done);
ef06c9ee
RD		 4650 if (err) {
4651 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4652 goto err_free;
4653
b4a23329 4654 add_unready_flow(flow);
ef06c9ee 4655 }
e3a2b7ed 4656
71129676 4657 return flow;
a88780a9
RD		 4658
4659err_free:
e68e28b4 4660 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4661 mlx5e_flow_put(priv, flow);
a88780a9 4662out:
71129676 4663 return ERR_PTR(err);
a88780a9
RD		 4664}
4665
f9e30088 4666static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4667 struct mlx5e_tc_flow *flow,
226f2ca3 4668 unsigned long flow_flags)
04de7dda
RD		 4669{
4670 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4671 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4672 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4673 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4674 struct mlx5e_tc_flow_parse_attr *parse_attr;
4675 struct mlx5e_rep_priv *peer_urpriv;
4676 struct mlx5e_tc_flow *peer_flow;
4677 struct mlx5_core_dev *in_mdev;
4678 int err = 0;
4679
4680 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4681 if (!peer_esw)
4682 return -ENODEV;
4683
4684 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4685 peer_priv = netdev_priv(peer_urpriv->netdev);
4686
4687 /* in_mdev is assigned of which the packet originated from.
4688 * So packets redirected to uplink use the same mdev of the
4689 * original flow and packets redirected from uplink use the
4690 * peer mdev.
4691 */
c620b772 4692 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4693 in_mdev = peer_priv->mdev;
4694 else
4695 in_mdev = priv->mdev;
4696
c620b772 4697 parse_attr = flow->attr->parse_attr;
95dc1902 4698 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4699 parse_attr->filter_dev,
c620b772 4700 attr->in_rep, in_mdev);
71129676
JG		 4701 if (IS_ERR(peer_flow)) {
4702 err = PTR_ERR(peer_flow);
04de7dda 4703 goto out;
71129676 4704 }
04de7dda
RD		 4705
4706 flow->peer_flow = peer_flow;
226f2ca3 4707 flow_flag_set(flow, DUP);
04de7dda
RD		 4708 mutex_lock(&esw->offloads.peer_mutex);
4709 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4710 mutex_unlock(&esw->offloads.peer_mutex);
4711
4712out:
4713 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4714 return err;
4715}
4716
4717static int
4718mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4719 struct flow_cls_offload *f,
226f2ca3 4720 unsigned long flow_flags,
04de7dda
RD		 4721 struct net_device *filter_dev,
4722 struct mlx5e_tc_flow **__flow)
4723{
4724 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4725 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4726 struct mlx5_core_dev *in_mdev = priv->mdev;
4727 struct mlx5e_tc_flow *flow;
4728 int err;
4729
71129676
JG		 4730 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4731 in_mdev);
4732 if (IS_ERR(flow))
4733 return PTR_ERR(flow);
04de7dda
RD		 4734
4735 if (is_peer_flow_needed(flow)) {
95dc1902 4736 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4737 if (err) {
4738 mlx5e_tc_del_fdb_flow(priv, flow);
4739 goto out;
4740 }
4741 }
4742
4743 *__flow = flow;
4744
4745 return 0;
4746
4747out:
4748 return err;
4749}
4750
a88780a9
RD		 4751static int
4752mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4753 struct flow_cls_offload *f,
226f2ca3 4754 unsigned long flow_flags,
d11afc26 4755 struct net_device *filter_dev,
a88780a9
RD		 4756 struct mlx5e_tc_flow **__flow)
4757{
f9e30088 4758 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4759 struct netlink_ext_ack *extack = f->common.extack;
4760 struct mlx5e_tc_flow_parse_attr *parse_attr;
4761 struct mlx5e_tc_flow *flow;
4762 int attr_size, err;
4763
c7569097
AL		 4764 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4765 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4766 return -EOPNOTSUPP;
4767 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4768 return -EOPNOTSUPP;
c7569097 4769 }
bf07aa73 4770
226f2ca3 4771 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4772 attr_size = sizeof(struct mlx5_nic_flow_attr);
4773 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4774 &parse_attr, &flow);
4775 if (err)
4776 goto out;
4777
d11afc26 4778 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4779 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4780
54c177ca
OS		 4781 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4782 f, filter_dev);
d11afc26
OS		 4783 if (err)
4784 goto err_free;
4785
aedd133d
AL		 4786 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4787 &flow->attr->ct_attr, extack);
4788 if (err)
4789 goto err_free;
4790
73867881 4791 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4792 if (err)
4793 goto err_free;
4794
4795 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4796 if (err)
4797 goto err_free;
4798
226f2ca3 4799 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4800 *__flow = flow;
4801
4802 return 0;
e3a2b7ed 4803
e3a2b7ed 4804err_free:
e68e28b4 4805 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4806 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4807out:
4808 return err;
4809}
4810
4811static int
4812mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4813 struct flow_cls_offload *f,
226f2ca3 4814 unsigned long flags,
d11afc26 4815 struct net_device *filter_dev,
a88780a9
RD		 4816 struct mlx5e_tc_flow **flow)
4817{
4818 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4819 unsigned long flow_flags;
a88780a9
RD		 4820 int err;
4821
4822 get_flags(flags, &flow_flags);
4823
bf07aa73
PB		 4824 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4825 return -EOPNOTSUPP;
4826
f6455de0 4827 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4828 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4829 filter_dev, flow);
a88780a9 4830 else
d11afc26
OS		 4831 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4832 filter_dev, flow);
a88780a9
RD		 4833
4834 return err;
4835}
4836
553f9328
VP		 4837static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4838 struct mlx5e_rep_priv *rpriv)
4839{
4840 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4841 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4842 * function is called from NIC mode.
553f9328 4843 */
2fb15e72 4844 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4845}
4846
71d82d2a 4847int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4848 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4849{
4850 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4851 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4852 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4853 struct mlx5e_tc_flow *flow;
4854 int err = 0;
4855
c5d326b2
VB		 4856 rcu_read_lock();
4857 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4858 if (flow) {
553f9328
VP		 4859 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4860 * just return 0.
4861 */
4862 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4863 goto rcu_unlock;
553f9328 4864
a88780a9
RD		 4865 NL_SET_ERR_MSG_MOD(extack,
4866 "flow cookie already exists, ignoring");
4867 netdev_warn_once(priv->netdev,
4868 "flow cookie %lx already exists, ignoring\n",
4869 f->cookie);
0e1c1a2f 4870 err = -EEXIST;
c1aea9e1 4871 goto rcu_unlock;
a88780a9 4872 }
c1aea9e1
VB		 4873rcu_unlock:
4874 rcu_read_unlock();
4875 if (flow)
4876 goto out;
a88780a9 4877
7a978759 4878 trace_mlx5e_configure_flower(f);
d11afc26 4879 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4880 if (err)
4881 goto out;
4882
553f9328
VP		 4883 /* Flow rule offloaded to non-uplink representor sharing tc block,
4884 * set the flow's owner dev.
4885 */
4886 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4887 flow->orig_dev = dev;
4888
c5d326b2 4889 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4890 if (err)
4891 goto err_free;
4892
4893 return 0;
4894
4895err_free:
5a7e5bcb 4896 mlx5e_flow_put(priv, flow);
a88780a9 4897out:
e3a2b7ed
AV		 4898 return err;
4899}
4900
8f8ae895
OG		 4901static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4902{
226f2ca3
VB		 4903 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4904 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4905
226f2ca3
VB		 4906 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4907 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4908}
4909
71d82d2a 4910int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4911 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4912{
d9ee0491 4913 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4914 struct mlx5e_tc_flow *flow;
c5d326b2 4915 int err;
e3a2b7ed 4916
c5d326b2 4917 rcu_read_lock();
ab818362 4918 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4919 if (!flow || !same_flow_direction(flow, flags)) {
4920 err = -EINVAL;
4921 goto errout;
4922 }
e3a2b7ed 4923
c5d326b2
VB		 4924 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4925 * set.
4926 */
4927 if (flow_flag_test_and_set(flow, DELETED)) {
4928 err = -EINVAL;
4929 goto errout;
4930 }
05866c82 4931 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4932 rcu_read_unlock();
e3a2b7ed 4933
7a978759 4934 trace_mlx5e_delete_flower(f);
5a7e5bcb 4935 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4936
4937 return 0;
c5d326b2
VB		 4938
4939errout:
4940 rcu_read_unlock();
4941 return err;
e3a2b7ed
AV		 4942}
4943
71d82d2a 4944int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4945 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4946{
04de7dda 4947 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4948 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4949 struct mlx5_eswitch *peer_esw;
aad7e08d 4950 struct mlx5e_tc_flow *flow;
aad7e08d 4951 struct mlx5_fc *counter;
316d5f72
RD		 4952 u64 lastuse = 0;
4953 u64 packets = 0;
4954 u64 bytes = 0;
5a7e5bcb 4955 int err = 0;
aad7e08d 4956
c5d326b2
VB		 4957 rcu_read_lock();
4958 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4959 tc_ht_params));
4960 rcu_read_unlock();
5a7e5bcb
VB		 4961 if (IS_ERR(flow))
4962 return PTR_ERR(flow);
4963
4964 if (!same_flow_direction(flow, flags)) {
4965 err = -EINVAL;
4966 goto errout;
4967 }
aad7e08d 4968
4c3844d9 4969 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4970 counter = mlx5e_tc_get_counter(flow);
4971 if (!counter)
5a7e5bcb 4972 goto errout;
aad7e08d 4973
316d5f72
RD		 4974 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4975 }
aad7e08d 4976
316d5f72
RD		 4977 /* Under multipath it's possible for one rule to be currently
4978 * un-offloaded while the other rule is offloaded.
4979 */
04de7dda
RD		 4980 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4981 if (!peer_esw)
4982 goto out;
4983
226f2ca3
VB		 4984 if (flow_flag_test(flow, DUP) &&
4985 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4986 u64 bytes2;
4987 u64 packets2;
4988 u64 lastuse2;
4989
4990 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4991 if (!counter)
4992 goto no_peer_counter;
04de7dda
RD		 4993 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4994
4995 bytes += bytes2;
4996 packets += packets2;
4997 lastuse = max_t(u64, lastuse, lastuse2);
4998 }
4999
316d5f72 5000no_peer_counter:
04de7dda 5001 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 5002out:
4b61d3e8 5003 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 5004 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 5005 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 5006errout:
5007 mlx5e_flow_put(priv, flow);
5008 return err;
aad7e08d
AV		 5009}
5010
1fe3e316 5011static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 5012 struct netlink_ext_ack *extack)
5013{
5014 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5015 struct mlx5_eswitch *esw;
1fe3e316 5016 u32 rate_mbps = 0;
fcb64c0f 5017 u16 vport_num;
fcb64c0f
EC		 5018 int err;
5019
e401a184
EC		 5020 vport_num = rpriv->rep->vport;
5021 if (vport_num >= MLX5_VPORT_ECPF) {
5022 NL_SET_ERR_MSG_MOD(extack,
5023 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5024 return -EOPNOTSUPP;
5025 }
5026
fcb64c0f
EC		 5027 esw = priv->mdev->priv.eswitch;
5028 /* rate is given in bytes/sec.
5029 * First convert to bits/sec and then round to the nearest mbit/secs.
5030 * mbit means million bits.
5031 * Moreover, if rate is non zero we choose to configure to a minimum of
5032 * 1 mbit/sec.
5033 */
1fe3e316
PP		 5034 if (rate) {
5035 rate = (rate * BITS_PER_BYTE) + 500000;
5036 rate_mbps = max_t(u32, do_div(rate, 1000000), 1);
5037 }
5038
fcb64c0f
EC		 5039 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
5040 if (err)
5041 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5042
5043 return err;
5044}
5045
5046static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5047 struct flow_action *flow_action,
5048 struct netlink_ext_ack *extack)
5049{
5050 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5051 const struct flow_action_entry *act;
5052 int err;
5053 int i;
5054
5055 if (!flow_action_has_entries(flow_action)) {
5056 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5057 return -EINVAL;
5058 }
5059
5060 if (!flow_offload_has_one_action(flow_action)) {
5061 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5062 return -EOPNOTSUPP;
5063 }
5064
53eca1f3 5065 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 5066 return -EOPNOTSUPP;
5067
fcb64c0f
EC		 5068 flow_action_for_each(i, act, flow_action) {
5069 switch (act->id) {
5070 case FLOW_ACTION_POLICE:
5071 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5072 if (err)
5073 return err;
5074
5075 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
5076 break;
5077 default:
5078 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5079 return -EOPNOTSUPP;
5080 }
5081 }
5082
5083 return 0;
5084}
5085
5086int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5087 struct tc_cls_matchall_offload *ma)
5088{
b5f814cc 5089 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 5090 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 5091
b5f814cc
EC		 5092 if (!mlx5_esw_qos_enabled(esw)) {
5093 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
5094 return -EOPNOTSUPP;
5095 }
5096
7b83355f 5097 if (ma->common.prio != 1) {
fcb64c0f
EC		 5098 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5099 return -EINVAL;
5100 }
5101
5102 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5103}
5104
5105int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5106 struct tc_cls_matchall_offload *ma)
5107{
5108 struct netlink_ext_ack *extack = ma->common.extack;
5109
5110 return apply_police_params(priv, 0, extack);
5111}
5112
5113void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5114 struct tc_cls_matchall_offload *ma)
5115{
5116 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5117 struct rtnl_link_stats64 cur_stats;
5118 u64 dbytes;
5119 u64 dpkts;
5120
5121 cur_stats = priv->stats.vf_vport;
5122 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5123 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5124 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 5125 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 5126 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 5127}
5128
4d8fcf21
AH		 5129static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5130 struct mlx5e_priv *peer_priv)
5131{
5132 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 5133 struct mlx5e_hairpin_entry *hpe, *tmp;
5134 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 5135 u16 peer_vhca_id;
5136 int bkt;
5137
5138 if (!same_hw_devs(priv, peer_priv))
5139 return;
5140
5141 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5142
b32accda 5143 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 5144 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
5145 if (refcount_inc_not_zero(&hpe->refcnt))
5146 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5147 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5148
5149 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5150 wait_for_completion(&hpe->res_ready);
5151 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 5152 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 5153
5154 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 5155 }
5156}
5157
5158static int mlx5e_tc_netdev_event(struct notifier_block *this,
5159 unsigned long event, void *ptr)
5160{
5161 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5162 struct mlx5e_flow_steering *fs;
5163 struct mlx5e_priv *peer_priv;
5164 struct mlx5e_tc_table *tc;
5165 struct mlx5e_priv *priv;
5166
5167 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5168 event != NETDEV_UNREGISTER ||
5169 ndev->reg_state == NETREG_REGISTERED)
5170 return NOTIFY_DONE;
5171
5172 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5173 fs = container_of(tc, struct mlx5e_flow_steering, tc);
5174 priv = container_of(fs, struct mlx5e_priv, fs);
5175 peer_priv = netdev_priv(ndev);
5176 if (priv == peer_priv ||
5177 !(priv->netdev->features & NETIF_F_HW_TC))
5178 return NOTIFY_DONE;
5179
5180 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5181
5182 return NOTIFY_DONE;
5183}
5184
6a064674
AL		 5185static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
5186{
5187 int tc_grp_size, tc_tbl_size;
5188 u32 max_flow_counter;
5189
5190 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
5191 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
5192
5193 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
5194
5195 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
5196 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
5197
5198 return tc_tbl_size;
5199}
5200
655dc3d2 5201int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 5202{
acff797c 5203 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674
AL		 5204 struct mlx5_core_dev *dev = priv->mdev;
5205 struct mlx5_chains_attr attr = {};
4d8fcf21 5206 int err;
e8f887ac 5207
b2fdf3d0 5208 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 5209 mutex_init(&tc->t_lock);
b32accda 5210 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 5211 hash_init(tc->hairpin_tbl);
11c9c548 5212
4d8fcf21
AH		 5213 err = rhashtable_init(&tc->ht, &tc_ht_params);
5214 if (err)
5215 return err;
5216
c7569097
AL		 5217 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
5218 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5219 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5220 attr.max_restore_tag = MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5221 }
6a064674
AL		 5222 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5223 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
5224 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5225 attr.default_ft = priv->fs.vlan.ft.t;
5226
5227 tc->chains = mlx5_chains_create(dev, &attr);
5228 if (IS_ERR(tc->chains)) {
5229 err = PTR_ERR(tc->chains);
5230 goto err_chains;
5231 }
5232
aedd133d
AL		 5233 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
5234 MLX5_FLOW_NAMESPACE_KERNEL);
68ec32da
WH		 5235 if (IS_ERR(tc->ct)) {
5236 err = PTR_ERR(tc->ct);
aedd133d 5237 goto err_ct;
68ec32da 5238 }
aedd133d 5239
4d8fcf21 5240 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 5241 err = register_netdevice_notifier_dev_net(priv->netdev,
5242 &tc->netdevice_nb,
5243 &tc->netdevice_nn);
5244 if (err) {
4d8fcf21
AH		 5245 tc->netdevice_nb.notifier_call = NULL;
5246 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 5247 goto err_reg;
4d8fcf21
AH		 5248 }
5249
6a064674
AL		 5250 return 0;
5251
5252err_reg:
aedd133d
AL		 5253 mlx5_tc_ct_clean(tc->ct);
5254err_ct:
6a064674
AL		 5255 mlx5_chains_destroy(tc->chains);
5256err_chains:
5257 rhashtable_destroy(&tc->ht);
4d8fcf21 5258 return err;
e8f887ac
AV		 5259}
5260
5261static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5262{
5263 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5264 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5265
961e8979 5266 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5267 kfree(flow);
5268}
5269
655dc3d2 5270void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5271{
acff797c 5272 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5273
4d8fcf21 5274 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5275 unregister_netdevice_notifier_dev_net(priv->netdev,
5276 &tc->netdevice_nb,
5277 &tc->netdevice_nn);
4d8fcf21 5278
b2fdf3d0 5279 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 5280 mutex_destroy(&tc->hairpin_tbl_lock);
5281
6a064674 5282 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 5283
acff797c 5284 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 5285 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 5286 tc->t = NULL;
e8f887ac 5287 }
b6fac0b4 5288 mutex_destroy(&tc->t_lock);
6a064674 5289
aedd133d 5290 mlx5_tc_ct_clean(tc->ct);
6a064674 5291 mlx5_chains_destroy(tc->chains);
e8f887ac 5292}
655dc3d2
OG		 5293
5294int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5295{
d7a42ad0 5296 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 5297 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 5298 struct mlx5e_rep_priv *rpriv;
0a7fcb78 5299 struct mapping_ctx *mapping;
aedd133d
AL		 5300 struct mlx5_eswitch *esw;
5301 struct mlx5e_priv *priv;
5302 int err = 0;
0a7fcb78
PB		 5303
5304 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5305 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5306 priv = netdev_priv(rpriv->netdev);
5307 esw = priv->mdev->priv.eswitch;
0a7fcb78 5308
aedd133d
AL		 5309 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5310 esw_chains(esw),
5311 &esw->offloads.mod_hdr,
5312 MLX5_FLOW_NAMESPACE_FDB);
5313 if (IS_ERR(uplink_priv->ct_priv))
4c3844d9
PB		 5314 goto err_ct;
5315
0a7fcb78
PB		 5316 mapping = mapping_create(sizeof(struct tunnel_match_key),
5317 TUNNEL_INFO_BITS_MASK, true);
5318 if (IS_ERR(mapping)) {
5319 err = PTR_ERR(mapping);
5320 goto err_tun_mapping;
5321 }
5322 uplink_priv->tunnel_mapping = mapping;
5323
5324 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
5325 if (IS_ERR(mapping)) {
5326 err = PTR_ERR(mapping);
5327 goto err_enc_opts_mapping;
5328 }
5329 uplink_priv->tunnel_enc_opts_mapping = mapping;
5330
5331 err = rhashtable_init(tc_ht, &tc_ht_params);
5332 if (err)
5333 goto err_ht_init;
5334
5335 return err;
5336
5337err_ht_init:
5338 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5339err_enc_opts_mapping:
5340 mapping_destroy(uplink_priv->tunnel_mapping);
5341err_tun_mapping:
aedd133d 5342 mlx5_tc_ct_clean(uplink_priv->ct_priv);
4c3844d9 5343err_ct:
0a7fcb78
PB		 5344 netdev_warn(priv->netdev,
5345 "Failed to initialize tc (eswitch), err: %d", err);
5346 return err;
655dc3d2
OG		 5347}
5348
5349void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5350{
0a7fcb78
PB		 5351 struct mlx5_rep_uplink_priv *uplink_priv;
5352
655dc3d2 5353 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 5354
5355 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5356
0a7fcb78
PB		 5357 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5358 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5359
aedd133d 5360 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 5361}
01252a27 5362
226f2ca3 5363int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5364{
d9ee0491 5365 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5366
5367 return atomic_read(&tc_ht->nelems);
5368}
04de7dda
RD		 5369
5370void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5371{
5372 struct mlx5e_tc_flow *flow, *tmp;
5373
5374 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5375 __mlx5e_tc_del_fdb_peer_flow(flow);
5376}
b4a23329
RD		 5377
5378void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5379{
5380 struct mlx5_rep_uplink_priv *rpriv =
5381 container_of(work, struct mlx5_rep_uplink_priv,
5382 reoffload_flows_work);
5383 struct mlx5e_tc_flow *flow, *tmp;
5384
ad86755b 5385 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5386 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5387 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5388 unready_flow_del(flow);
b4a23329 5389 }
ad86755b 5390 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5391}
e2394a61
VB		 5392
5393static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5394 struct flow_cls_offload *cls_flower,
5395 unsigned long flags)
5396{
5397 switch (cls_flower->command) {
5398 case FLOW_CLS_REPLACE:
5399 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5400 flags);
5401 case FLOW_CLS_DESTROY:
5402 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5403 flags);
5404 case FLOW_CLS_STATS:
5405 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5406 flags);
5407 default:
5408 return -EOPNOTSUPP;
5409 }
5410}
5411
5412int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5413 void *cb_priv)
5414{
5415 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
5416 struct mlx5e_priv *priv = cb_priv;
5417
5418 switch (type) {
5419 case TC_SETUP_CLSFLOWER:
5420 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5421 default:
5422 return -EOPNOTSUPP;
5423 }
5424}
c7569097
AL		 5425
5426bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5427 struct sk_buff *skb)
5428{
5429#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5430 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5431 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5432 struct mlx5e_tc_table *tc = &priv->fs.tc;
c7569097
AL		 5433 struct tc_skb_ext *tc_skb_ext;
5434 int err;
5435
5436 reg_b = be32_to_cpu(cqe->ft_metadata);
5437
5438 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5439
5440 err = mlx5_get_chain_for_tag(nic_chains(priv), chain_tag, &chain);
5441 if (err) {
5442 netdev_dbg(priv->netdev,
5443 "Couldn't find chain for chain tag: %d, err: %d\n",
5444 chain_tag, err);
5445 return false;
5446 }
5447
5448 if (chain) {
5449 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
5450 if (WARN_ON(!tc_skb_ext))
5451 return false;
5452
5453 tc_skb_ext->chain = chain;
aedd133d
AL		 5454
5455 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
5456 ZONE_RESTORE_MAX;
5457
5458 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5459 zone_restore_id))
5460 return false;
c7569097
AL		 5461 }
5462#endif /* CONFIG_NET_TC_SKB_EXT */
5463
5464 return true;
5465}
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