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ptp: Fix possible memory leak in ptp_clock_register()
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
d79b6df6 42#include <net/tc_act/tc_pedit.h>
26c02749 43#include <net/tc_act/tc_csum.h>
41c2fd94 44#include <net/psample.h>
f6dfb4c3 45#include <net/arp.h>
3616d08b 46#include <net/ipv6_stubs.h>
f828ca6a 47#include <net/bareudp.h>
d34eb2fc 48#include <net/bonding.h>
e8f887ac 49#include "en.h"
f0da4daa 50#include "en/tc/post_act.h"
1d447a39 51#include "en_rep.h"
768c3667 52#include "en/rep/tc.h"
e2394a61 53#include "en/rep/neigh.h"
232c0013 54#include "en_tc.h"
03a9d11e 55#include "eswitch.h"
3f6d08d1 56#include "fs_core.h"
2c81bfd5 57#include "en/port.h"
101f4de9 58#include "en/tc_tun.h"
0a7fcb78 59#include "en/mapping.h"
4c3844d9 60#include "en/tc_ct.h"
b2fdf3d0 61#include "en/mod_hdr.h"
0d9f9647
VB		 62#include "en/tc_priv.h"
63#include "en/tc_tun_encap.h"
0027d70c 64#include "en/tc/sample.h"
04de7dda 65#include "lib/devcom.h"
9272e3df 66#include "lib/geneve.h"
ae430332 67#include "lib/fs_chains.h"
7a978759 68#include "diag/en_tc_tracepoint.h"
1fe3e316 69#include <asm/div64.h>
e8f887ac 70
6a064674 71#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 72#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 73
acff797c 74#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 75#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 76
8f1e0b97
PB		 77struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
78 [CHAIN_TO_REG] = {
79 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
80 .moffset = 0,
ed2fe7ba 81 .mlen = 16,
8f1e0b97 82 },
10742efc
VB		 83 [VPORT_TO_REG] = {
84 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 85 .moffset = 16,
86 .mlen = 16,
10742efc 87 },
0a7fcb78
PB		 88 [TUNNEL_TO_REG] = {
89 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 90 .moffset = 8,
91 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 92 .soffset = MLX5_BYTE_OFF(fte_match_param,
93 misc_parameters_2.metadata_reg_c_1),
94 },
4c3844d9 95 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 96 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 97 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
98 [MARK_TO_REG] = mark_to_reg_ct,
99 [LABELS_TO_REG] = labels_to_reg_ct,
100 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 101 /* For NIC rules we store the restore metadata directly
c7569097
AL		 102 * into reg_b that is passed to SW since we don't
103 * jump between steering domains.
104 */
105 [NIC_CHAIN_TO_REG] = {
106 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
107 .moffset = 0,
ed2fe7ba 108 .mlen = 16,
c7569097 109 },
aedd133d 110 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 111};
112
9ba33339
RD		 113/* To avoid false lock dependency warning set the tc_ht lock
114 * class different than the lock class of the ht being used when deleting
115 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
116 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
117 * it's different than the ht->mutex here.
118 */
119static struct lock_class_key tc_ht_lock_key;
120
0a7fcb78
PB		 121static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
122
123void
124mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
125 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 126 u32 val,
0a7fcb78
PB		 127 u32 mask)
128{
ed2fe7ba 129 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 130 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 131 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 132 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 133 u32 max_mask = GENMASK(match_len - 1, 0);
134 __be32 curr_mask_be, curr_val_be;
135 u32 curr_mask, curr_val;
0a7fcb78
PB		 136
137 fmask = headers_c + soffset;
138 fval = headers_v + soffset;
139
ed2fe7ba
PB		 140 memcpy(&curr_mask_be, fmask, 4);
141 memcpy(&curr_val_be, fval, 4);
142
143 curr_mask = be32_to_cpu(curr_mask_be);
144 curr_val = be32_to_cpu(curr_val_be);
145
146 //move to correct offset
147 WARN_ON(mask > max_mask);
148 mask <<= moffset;
149 val <<= moffset;
150 max_mask <<= moffset;
151
152 //zero val and mask
153 curr_mask &= ~max_mask;
154 curr_val &= ~max_mask;
0a7fcb78 155
ed2fe7ba
PB		 156 //add current to mask
157 curr_mask |= mask;
158 curr_val |= val;
159
160 //back to be32 and write
161 curr_mask_be = cpu_to_be32(curr_mask);
162 curr_val_be = cpu_to_be32(curr_val);
163
164 memcpy(fmask, &curr_mask_be, 4);
165 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 166
167 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
168}
169
7e36feeb
PB		 170void
171mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
172 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 173 u32 *val,
7e36feeb
PB		 174 u32 *mask)
175{
ed2fe7ba 176 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 177 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 178 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 179 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 180 u32 max_mask = GENMASK(match_len - 1, 0);
181 __be32 curr_mask_be, curr_val_be;
182 u32 curr_mask, curr_val;
7e36feeb
PB		 183
184 fmask = headers_c + soffset;
185 fval = headers_v + soffset;
186
ed2fe7ba
PB		 187 memcpy(&curr_mask_be, fmask, 4);
188 memcpy(&curr_val_be, fval, 4);
189
190 curr_mask = be32_to_cpu(curr_mask_be);
191 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 192
ed2fe7ba
PB		 193 *mask = (curr_mask >> moffset) & max_mask;
194 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 195}
196
0a7fcb78 197int
c7b9038d
VB		 198mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
199 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
200 enum mlx5_flow_namespace_type ns,
201 enum mlx5e_tc_attr_to_reg type,
202 u32 data)
0a7fcb78
PB		 203{
204 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
205 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
206 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
207 char *modact;
208 int err;
209
aedd133d 210 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 211 if (err)
212 return err;
213
214 modact = mod_hdr_acts->actions +
215 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
216
217 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 218 if (mlen == 32)
0a7fcb78
PB		 219 mlen = 0;
220
221 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
222 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 223 MLX5_SET(set_action_in, modact, offset, moffset);
224 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 225 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 226 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 227 mod_hdr_acts->num_actions++;
228
c7b9038d 229 return err;
0a7fcb78
PB		 230}
231
aedd133d
AL		 232static struct mlx5_tc_ct_priv *
233get_ct_priv(struct mlx5e_priv *priv)
234{
235 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
236 struct mlx5_rep_uplink_priv *uplink_priv;
237 struct mlx5e_rep_priv *uplink_rpriv;
238
e8711402 239 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 240 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
241 uplink_priv = &uplink_rpriv->uplink_priv;
242
243 return uplink_priv->ct_priv;
244 }
245
246 return priv->fs.tc.ct;
247}
248
f94d6389 249#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
0027d70c 250static struct mlx5e_tc_psample *
f94d6389
CM		 251get_sample_priv(struct mlx5e_priv *priv)
252{
253 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
254 struct mlx5_rep_uplink_priv *uplink_priv;
255 struct mlx5e_rep_priv *uplink_rpriv;
256
257 if (is_mdev_switchdev_mode(priv->mdev)) {
258 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
259 uplink_priv = &uplink_rpriv->uplink_priv;
260
0027d70c 261 return uplink_priv->tc_psample;
f94d6389
CM		 262 }
263
264 return NULL;
265}
266#endif
267
aedd133d
AL		 268struct mlx5_flow_handle *
269mlx5_tc_rule_insert(struct mlx5e_priv *priv,
270 struct mlx5_flow_spec *spec,
271 struct mlx5_flow_attr *attr)
272{
273 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
274
e8711402 275 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 276 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
277
278 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
279}
280
281void
282mlx5_tc_rule_delete(struct mlx5e_priv *priv,
283 struct mlx5_flow_handle *rule,
284 struct mlx5_flow_attr *attr)
285{
286 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
287
e8711402 288 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 289 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
290
291 return;
292 }
293
294 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
295}
296
c7b9038d
VB		 297int
298mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
299 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
300 enum mlx5_flow_namespace_type ns,
301 enum mlx5e_tc_attr_to_reg type,
302 u32 data)
303{
304 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
305
306 return ret < 0 ? ret : 0;
307}
308
309void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
310 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
311 enum mlx5e_tc_attr_to_reg type,
312 int act_id, u32 data)
313{
314 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
315 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
316 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
317 char *modact;
318
319 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
320
321 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 322 if (mlen == 32)
c7b9038d
VB		 323 mlen = 0;
324
325 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
326 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 327 MLX5_SET(set_action_in, modact, offset, moffset);
328 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 329 MLX5_SET(set_action_in, modact, data, data);
330}
331
77ab67b7
OG		 332struct mlx5e_hairpin {
333 struct mlx5_hairpin *pair;
334
335 struct mlx5_core_dev *func_mdev;
3f6d08d1 336 struct mlx5e_priv *func_priv;
77ab67b7 337 u32 tdn;
a6696735 338 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 339
340 int num_channels;
341 struct mlx5e_rqt indir_rqt;
a6696735 342 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 343 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 344};
345
5c65c564
OG		 346struct mlx5e_hairpin_entry {
347 /* a node of a hash table which keeps all the hairpin entries */
348 struct hlist_node hairpin_hlist;
349
73edca73
VB		 350 /* protects flows list */
351 spinlock_t flows_lock;
5c65c564
OG		 352 /* flows sharing the same hairpin */
353 struct list_head flows;
db76ca24
VB		 354 /* hpe's that were not fully initialized when dead peer update event
355 * function traversed them.
356 */
357 struct list_head dead_peer_wait_list;
5c65c564 358
d8822868 359 u16 peer_vhca_id;
106be53b 360 u8 prio;
5c65c564 361 struct mlx5e_hairpin *hp;
e4f9abbd 362 refcount_t refcnt;
db76ca24 363 struct completion res_ready;
5c65c564
OG		 364};
365
5a7e5bcb
VB		 366static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
367 struct mlx5e_tc_flow *flow);
368
0d9f9647 369struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 370{
371 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
372 return ERR_PTR(-EINVAL);
373 return flow;
374}
375
0d9f9647 376void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 377{
378 if (refcount_dec_and_test(&flow->refcnt)) {
379 mlx5e_tc_del_flow(priv, flow);
c5d326b2 380 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 381 }
382}
383
aedd133d 384bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 385{
386 return flow_flag_test(flow, ESWITCH);
387}
388
84179981
PB		 389static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390{
391 return flow_flag_test(flow, FT);
392}
393
0d9f9647 394bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 395{
396 return flow_flag_test(flow, OFFLOADED);
397}
398
b2fdf3d0 399static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 400{
b2fdf3d0
PB		 401 return mlx5e_is_eswitch_flow(flow) ?
402 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 403}
404
dd58edc3 405static struct mod_hdr_tbl *
b2fdf3d0 406get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 407{
408 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
409
b2fdf3d0
PB		 410 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
411 &esw->offloads.mod_hdr :
dd58edc3
VB		 412 &priv->fs.tc.mod_hdr;
413}
414
11c9c548
OG		 415static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
416 struct mlx5e_tc_flow *flow,
417 struct mlx5e_tc_flow_parse_attr *parse_attr)
418{
b2fdf3d0
PB		 419 struct mlx5_modify_hdr *modify_hdr;
420 struct mlx5e_mod_hdr_handle *mh;
11c9c548 421
b2fdf3d0
PB		 422 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
423 get_flow_name_space(flow),
424 &parse_attr->mod_hdr_acts);
425 if (IS_ERR(mh))
426 return PTR_ERR(mh);
11c9c548 427
b2fdf3d0 428 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 429 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 430 flow->mh = mh;
11c9c548
OG		 431
432 return 0;
11c9c548
OG		 433}
434
435static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
436 struct mlx5e_tc_flow *flow)
437{
5a7e5bcb 438 /* flow wasn't fully initialized */
dd58edc3 439 if (!flow->mh)
5a7e5bcb
VB		 440 return;
441
b2fdf3d0
PB		 442 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
443 flow->mh);
dd58edc3 444 flow->mh = NULL;
11c9c548
OG		 445}
446
77ab67b7
OG		 447static
448struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
449{
b1c2f631 450 struct mlx5_core_dev *mdev;
77ab67b7
OG		 451 struct net_device *netdev;
452 struct mlx5e_priv *priv;
453
b1c2f631
DC		 454 netdev = dev_get_by_index(net, ifindex);
455 if (!netdev)
456 return ERR_PTR(-ENODEV);
457
77ab67b7 458 priv = netdev_priv(netdev);
b1c2f631
DC		 459 mdev = priv->mdev;
460 dev_put(netdev);
461
462 /* Mirred tc action holds a refcount on the ifindex net_device (see
463 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
464 * after dev_put(netdev), while we're in the context of adding a tc flow.
465 *
466 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
467 * stored in a hairpin object, which exists until all flows, that refer to it, get
468 * removed.
469 *
470 * On the other hand, after a hairpin object has been created, the peer net_device may
471 * be removed/unbound while there are still some hairpin flows that are using it. This
472 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
473 * NETDEV_UNREGISTER event of the peer net_device.
474 */
475 return mdev;
77ab67b7
OG		 476}
477
478static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
479{
a6696735 480 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 481 int err;
482
a6696735
MM		 483 builder = mlx5e_tir_builder_alloc(false);
484 if (!builder)
485 return -ENOMEM;
486
77ab67b7
OG		 487 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
488 if (err)
a6696735 489 goto out;
77ab67b7 490
a6696735
MM		 491 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
492 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 493 if (err)
494 goto create_tir_err;
495
a6696735
MM		 496out:
497 mlx5e_tir_builder_free(builder);
498 return err;
77ab67b7
OG		 499
500create_tir_err:
501 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 502
503 goto out;
77ab67b7
OG		 504}
505
506static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
507{
a6696735 508 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 509 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
510}
511
3f6d08d1
OG		 512static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
513{
3f6d08d1
OG		 514 struct mlx5e_priv *priv = hp->func_priv;
515 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 516 struct mlx5e_rss_params_indir *indir;
517 int err;
3f6d08d1 518
06e9f13a
MM		 519 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
520 if (!indir)
3f6d08d1
OG		 521 return -ENOMEM;
522
43befe99 523 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 524 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 525 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
526 indir);
3f6d08d1 527
06e9f13a 528 kvfree(indir);
3f6d08d1
OG		 529 return err;
530}
531
532static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
533{
534 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 535 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 536 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 537 struct mlx5e_tir_builder *builder;
538 int err = 0;
539
540 builder = mlx5e_tir_builder_alloc(false);
541 if (!builder)
542 return -ENOMEM;
543
43ec0f41 544 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 545
546 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 547 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 548
65d6b6e5 549 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 550
a6696735
MM		 551 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
552 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
553 false);
43ec0f41 554 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 555
a6696735 556 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 557 if (err) {
558 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
559 goto err_destroy_tirs;
560 }
a6696735
MM		 561
562 mlx5e_tir_builder_clear(builder);
3f6d08d1 563 }
3f6d08d1 564
a6696735
MM		 565out:
566 mlx5e_tir_builder_free(builder);
3f6d08d1 567 return err;
a6696735
MM		 568
569err_destroy_tirs:
570 max_tt = tt;
571 for (tt = 0; tt < max_tt; tt++)
572 mlx5e_tir_destroy(&hp->indir_tir[tt]);
573
574 goto out;
3f6d08d1
OG		 575}
576
577static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
578{
579 int tt;
580
581 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 582 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 583}
584
585static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
586 struct ttc_params *ttc_params)
587{
588 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
589 int tt;
590
591 memset(ttc_params, 0, sizeof(*ttc_params));
592
bc29764e
MG		 593 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
594 MLX5_FLOW_NAMESPACE_KERNEL);
595 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
596 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
597 ttc_params->dests[tt].tir_num =
598 tt == MLX5_TT_ANY ?
599 mlx5e_tir_get_tirn(&hp->direct_tir) :
600 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
601 }
3f6d08d1 602
3f6d08d1
OG		 603 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
604 ft_attr->prio = MLX5E_TC_PRIO;
605}
606
607static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
608{
609 struct mlx5e_priv *priv = hp->func_priv;
610 struct ttc_params ttc_params;
611 int err;
612
613 err = mlx5e_hairpin_create_indirect_rqt(hp);
614 if (err)
615 return err;
616
617 err = mlx5e_hairpin_create_indirect_tirs(hp);
618 if (err)
619 goto err_create_indirect_tirs;
620
621 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 622 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
623 if (IS_ERR(hp->ttc)) {
624 err = PTR_ERR(hp->ttc);
3f6d08d1 625 goto err_create_ttc_table;
f4b45940 626 }
3f6d08d1
OG		 627
628 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 629 hp->num_channels,
630 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 631
632 return 0;
633
634err_create_ttc_table:
635 mlx5e_hairpin_destroy_indirect_tirs(hp);
636err_create_indirect_tirs:
06e9f13a 637 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 638
639 return err;
640}
641
642static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
643{
f4b45940 644 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 645 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 646 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 647}
648
77ab67b7
OG		 649static struct mlx5e_hairpin *
650mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
651 int peer_ifindex)
652{
653 struct mlx5_core_dev *func_mdev, *peer_mdev;
654 struct mlx5e_hairpin *hp;
655 struct mlx5_hairpin *pair;
656 int err;
657
658 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
659 if (!hp)
660 return ERR_PTR(-ENOMEM);
661
662 func_mdev = priv->mdev;
663 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 664 if (IS_ERR(peer_mdev)) {
665 err = PTR_ERR(peer_mdev);
666 goto create_pair_err;
667 }
77ab67b7
OG		 668
669 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
670 if (IS_ERR(pair)) {
671 err = PTR_ERR(pair);
672 goto create_pair_err;
673 }
674 hp->pair = pair;
675 hp->func_mdev = func_mdev;
3f6d08d1
OG		 676 hp->func_priv = priv;
677 hp->num_channels = params->num_channels;
77ab67b7
OG		 678
679 err = mlx5e_hairpin_create_transport(hp);
680 if (err)
681 goto create_transport_err;
682
3f6d08d1
OG		 683 if (hp->num_channels > 1) {
684 err = mlx5e_hairpin_rss_init(hp);
685 if (err)
686 goto rss_init_err;
687 }
688
77ab67b7
OG		 689 return hp;
690
3f6d08d1
OG		 691rss_init_err:
692 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 693create_transport_err:
694 mlx5_core_hairpin_destroy(hp->pair);
695create_pair_err:
696 kfree(hp);
697 return ERR_PTR(err);
698}
699
700static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
701{
3f6d08d1
OG		 702 if (hp->num_channels > 1)
703 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 704 mlx5e_hairpin_destroy_transport(hp);
705 mlx5_core_hairpin_destroy(hp->pair);
706 kvfree(hp);
707}
708
106be53b
OG		 709static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
710{
711 return (peer_vhca_id << 16 | prio);
712}
713
5c65c564 714static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 715 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 716{
717 struct mlx5e_hairpin_entry *hpe;
106be53b 718 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 719
720 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 721 hairpin_hlist, hash_key) {
e4f9abbd
VB		 722 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
723 refcount_inc(&hpe->refcnt);
5c65c564 724 return hpe;
e4f9abbd 725 }
5c65c564
OG		 726 }
727
728 return NULL;
729}
730
e4f9abbd
VB		 731static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
732 struct mlx5e_hairpin_entry *hpe)
733{
734 /* no more hairpin flows for us, release the hairpin pair */
b32accda 735 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 736 return;
b32accda
VB		 737 hash_del(&hpe->hairpin_hlist);
738 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 739
db76ca24
VB		 740 if (!IS_ERR_OR_NULL(hpe->hp)) {
741 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
742 dev_name(hpe->hp->pair->peer_mdev->device));
743
744 mlx5e_hairpin_destroy(hpe->hp);
745 }
e4f9abbd
VB		 746
747 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 748 kfree(hpe);
749}
750
106be53b
OG		 751#define UNKNOWN_MATCH_PRIO 8
752
753static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 754 struct mlx5_flow_spec *spec, u8 *match_prio,
755 struct netlink_ext_ack *extack)
106be53b
OG		 756{
757 void *headers_c, *headers_v;
758 u8 prio_val, prio_mask = 0;
759 bool vlan_present;
760
761#ifdef CONFIG_MLX5_CORE_EN_DCB
762 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 763 NL_SET_ERR_MSG_MOD(extack,
764 "only PCP trust state supported for hairpin");
106be53b
OG		 765 return -EOPNOTSUPP;
766 }
767#endif
768 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
769 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
770
771 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
772 if (vlan_present) {
773 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
774 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
775 }
776
777 if (!vlan_present || !prio_mask) {
778 prio_val = UNKNOWN_MATCH_PRIO;
779 } else if (prio_mask != 0x7) {
e98bedf5
EB		 780 NL_SET_ERR_MSG_MOD(extack,
781 "masked priority match not supported for hairpin");
106be53b
OG		 782 return -EOPNOTSUPP;
783 }
784
785 *match_prio = prio_val;
786 return 0;
787}
788
5c65c564
OG		 789static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
790 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 791 struct mlx5e_tc_flow_parse_attr *parse_attr,
792 struct netlink_ext_ack *extack)
5c65c564 793{
98b66cb1 794 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 795 struct mlx5_hairpin_params params;
d8822868 796 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 797 struct mlx5e_hairpin_entry *hpe;
798 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 799 u64 link_speed64;
800 u32 link_speed;
106be53b 801 u8 match_prio;
d8822868 802 u16 peer_id;
5c65c564
OG		 803 int err;
804
d8822868 805 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 806 if (IS_ERR(peer_mdev)) {
807 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
808 return PTR_ERR(peer_mdev);
809 }
810
d8822868 811 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 812 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 813 return -EOPNOTSUPP;
814 }
815
d8822868 816 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 817 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
818 extack);
106be53b
OG		 819 if (err)
820 return err;
b32accda
VB		 821
822 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 823 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 824 if (hpe) {
825 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
826 wait_for_completion(&hpe->res_ready);
827
828 if (IS_ERR(hpe->hp)) {
829 err = -EREMOTEIO;
830 goto out_err;
831 }
5c65c564 832 goto attach_flow;
db76ca24 833 }
5c65c564
OG		 834
835 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 836 if (!hpe) {
db76ca24
VB		 837 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
838 return -ENOMEM;
b32accda 839 }
5c65c564 840
73edca73 841 spin_lock_init(&hpe->flows_lock);
5c65c564 842 INIT_LIST_HEAD(&hpe->flows);
db76ca24 843 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 844 hpe->peer_vhca_id = peer_id;
106be53b 845 hpe->prio = match_prio;
e4f9abbd 846 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 847 init_completion(&hpe->res_ready);
848
849 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
850 hash_hairpin_info(peer_id, match_prio));
851 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 852
6cdc686a 853 params.log_data_size = 16;
5c65c564
OG		 854 params.log_data_size = min_t(u8, params.log_data_size,
855 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
856 params.log_data_size = max_t(u8, params.log_data_size,
857 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 858
eb9180f7
OG		 859 params.log_num_packets = params.log_data_size -
860 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
861 params.log_num_packets = min_t(u8, params.log_num_packets,
862 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
863
864 params.q_counter = priv->q_counter;
3f6d08d1 865 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 866 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 867 link_speed = max_t(u32, link_speed, 50000);
868 link_speed64 = link_speed;
869 do_div(link_speed64, 50000);
870 params.num_channels = link_speed64;
871
5c65c564 872 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 873 hpe->hp = hp;
874 complete_all(&hpe->res_ready);
5c65c564
OG		 875 if (IS_ERR(hp)) {
876 err = PTR_ERR(hp);
db76ca24 877 goto out_err;
5c65c564
OG		 878 }
879
eb9180f7 880 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 881 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 882 dev_name(hp->pair->peer_mdev->device),
eb9180f7 883 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 884
5c65c564 885attach_flow:
3f6d08d1 886 if (hpe->hp->num_channels > 1) {
226f2ca3 887 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 888 flow->attr->nic_attr->hairpin_ft =
889 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 890 } else {
a6696735 891 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 892 }
b32accda 893
e4f9abbd 894 flow->hpe = hpe;
73edca73 895 spin_lock(&hpe->flows_lock);
5c65c564 896 list_add(&flow->hairpin, &hpe->flows);
73edca73 897 spin_unlock(&hpe->flows_lock);
3f6d08d1 898
5c65c564
OG		 899 return 0;
900
db76ca24
VB		 901out_err:
902 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 903 return err;
904}
905
906static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
907 struct mlx5e_tc_flow *flow)
908{
5a7e5bcb 909 /* flow wasn't fully initialized */
e4f9abbd 910 if (!flow->hpe)
5a7e5bcb
VB		 911 return;
912
73edca73 913 spin_lock(&flow->hpe->flows_lock);
5c65c564 914 list_del(&flow->hairpin);
73edca73
VB		 915 spin_unlock(&flow->hpe->flows_lock);
916
e4f9abbd
VB		 917 mlx5e_hairpin_put(priv, flow->hpe);
918 flow->hpe = NULL;
5c65c564
OG		 919}
920
08247066
AL		 921struct mlx5_flow_handle *
922mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
923 struct mlx5_flow_spec *spec,
c620b772 924 struct mlx5_flow_attr *attr)
e8f887ac 925{
08247066 926 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 927 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 928 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 929 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 930 struct mlx5_flow_destination dest[2] = {};
66958ed9 931 struct mlx5_flow_act flow_act = {
3bc4b7bf 932 .action = attr->action,
bb0ee7dc 933 .flags = FLOW_ACT_NO_APPEND,
66958ed9 934 };
08247066 935 struct mlx5_flow_handle *rule;
c7569097 936 struct mlx5_flow_table *ft;
08247066 937 int dest_ix = 0;
e8f887ac 938
bb0ee7dc 939 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 940 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 941
aedd133d
AL		 942 if (attr->dest_ft) {
943 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
944 dest[dest_ix].ft = attr->dest_ft;
945 dest_ix++;
946 } else if (nic_attr->hairpin_ft) {
08247066 947 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 948 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 949 dest_ix++;
c620b772 950 } else if (nic_attr->hairpin_tirn) {
08247066 951 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 952 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 953 dest_ix++;
3f6d08d1
OG		 954 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 956 if (attr->dest_chain) {
957 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
958 attr->dest_chain, 1,
959 MLX5E_TC_FT_LEVEL);
960 if (IS_ERR(dest[dest_ix].ft))
961 return ERR_CAST(dest[dest_ix].ft);
962 } else {
6783f0a2 963 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 964 }
3f6d08d1 965 dest_ix++;
5c65c564 966 }
aad7e08d 967
c7569097
AL		 968 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
969 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
970 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
971
08247066 972 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 973 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 974 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 975 dest_ix++;
aad7e08d
AV		 976 }
977
08247066 978 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 979 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 980
6a064674
AL		 981 mutex_lock(&tc->t_lock);
982 if (IS_ERR_OR_NULL(tc->t)) {
983 /* Create the root table here if doesn't exist yet */
984 tc->t =
c7569097 985 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 986
987 if (IS_ERR(tc->t)) {
988 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 989 netdev_err(priv->netdev,
990 "Failed to create tc offload table\n");
c7569097
AL		 991 rule = ERR_CAST(priv->fs.tc.t);
992 goto err_ft_get;
e8f887ac 993 }
e8f887ac 994 }
08247066 995 mutex_unlock(&tc->t_lock);
e8f887ac 996
aedd133d
AL		 997 if (attr->chain || attr->prio)
998 ft = mlx5_chains_get_table(nic_chains,
999 attr->chain, attr->prio,
1000 MLX5E_TC_FT_LEVEL);
1001 else
1002 ft = attr->ft;
1003
c7569097
AL		 1004 if (IS_ERR(ft)) {
1005 rule = ERR_CAST(ft);
1006 goto err_ft_get;
1007 }
1008
c620b772 1009 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1010 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1011
c7569097 1012 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1013 &flow_act, dest, dest_ix);
1014 if (IS_ERR(rule))
c7569097 1015 goto err_rule;
08247066
AL		 1016
1017 return rule;
c7569097
AL		 1018
1019err_rule:
aedd133d
AL		 1020 if (attr->chain || attr->prio)
1021 mlx5_chains_put_table(nic_chains,
1022 attr->chain, attr->prio,
1023 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1024err_ft_get:
1025 if (attr->dest_chain)
1026 mlx5_chains_put_table(nic_chains,
1027 attr->dest_chain, 1,
1028 MLX5E_TC_FT_LEVEL);
1029
1030 return ERR_CAST(rule);
08247066
AL		 1031}
1032
1033static int
1034mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1035 struct mlx5e_tc_flow *flow,
1036 struct netlink_ext_ack *extack)
1037{
c6cfe113 1038 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1039 struct mlx5_flow_attr *attr = flow->attr;
08247066 1040 struct mlx5_core_dev *dev = priv->mdev;
97a8d29a 1041 struct mlx5_fc *counter;
08247066
AL		 1042 int err;
1043
c6cfe113
RD		 1044 parse_attr = attr->parse_attr;
1045
08247066
AL		 1046 if (flow_flag_test(flow, HAIRPIN)) {
1047 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1048 if (err)
1049 return err;
1050 }
1051
1052 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1053 counter = mlx5_fc_create(dev, true);
1054 if (IS_ERR(counter))
1055 return PTR_ERR(counter);
1056
1057 attr->counter = counter;
1058 }
1059
1060 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1061 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1062 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1063 if (err)
1064 return err;
1065 }
1066
aedd133d
AL		 1067 if (flow_flag_test(flow, CT))
1068 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1069 attr, &parse_attr->mod_hdr_acts);
1070 else
1071 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1072 attr);
aad7e08d 1073
a2b7189b 1074 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1075}
1076
08247066 1077void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1078 struct mlx5_flow_handle *rule,
1079 struct mlx5_flow_attr *attr)
08247066 1080{
c7569097
AL		 1081 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1082
08247066 1083 mlx5_del_flow_rules(rule);
c7569097 1084
aedd133d
AL		 1085 if (attr->chain || attr->prio)
1086 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1087 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1088
1089 if (attr->dest_chain)
1090 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1091 MLX5E_TC_FT_LEVEL);
08247066
AL		 1092}
1093
d85cdccb
OG		 1094static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1095 struct mlx5e_tc_flow *flow)
1096{
c620b772 1097 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1098 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1099
c7569097
AL		 1100 flow_flag_clear(flow, OFFLOADED);
1101
aedd133d
AL		 1102 if (flow_flag_test(flow, CT))
1103 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1104 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1105 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1106
c7569097
AL		 1107 /* Remove root table if no rules are left to avoid
1108 * extra steering hops.
1109 */
b6fac0b4 1110 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1111 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1112 !IS_ERR_OR_NULL(tc->t)) {
1113 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1114 priv->fs.tc.t = NULL;
1115 }
b6fac0b4 1116 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1117
aedd133d
AL		 1118 kvfree(attr->parse_attr);
1119
513f8f7f 1120 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1121 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1122
aedd133d
AL		 1123 mlx5_fc_destroy(priv->mdev, attr->counter);
1124
226f2ca3 1125 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1126 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1127
1128 kfree(flow->attr);
d85cdccb
OG		 1129}
1130
0d9f9647 1131struct mlx5_flow_handle *
6d2a3ed0
OG		 1132mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1133 struct mlx5e_tc_flow *flow,
1134 struct mlx5_flow_spec *spec,
c620b772 1135 struct mlx5_flow_attr *attr)
6d2a3ed0 1136{
1ef3018f 1137 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1138 struct mlx5_flow_handle *rule;
4c3844d9 1139
89e39467
PB		 1140 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1141 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1142
1ef3018f
PB		 1143 if (flow_flag_test(flow, CT)) {
1144 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1145
69e2916e 1146 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1147 flow, spec, attr,
1ef3018f 1148 mod_hdr_acts);
f94d6389
CM		 1149#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1150 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1151 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1152 mlx5e_tc_get_flow_tun_id(flow));
f94d6389 1153#endif
69e2916e
PB		 1154 } else {
1155 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1156 }
6d2a3ed0 1157
6d2a3ed0
OG		 1158 if (IS_ERR(rule))
1159 return rule;
1160
c620b772 1161 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1162 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1163 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1164 if (flow_flag_test(flow, CT))
1165 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1166 else
1167 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1168 return flow->rule[1];
1169 }
1170 }
1171
6d2a3ed0
OG		 1172 return rule;
1173}
1174
0d9f9647
VB		 1175void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1176 struct mlx5e_tc_flow *flow,
1177 struct mlx5_flow_attr *attr)
6d2a3ed0 1178{
226f2ca3 1179 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1180
89e39467
PB		 1181 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1182 goto offload_rule_0;
1183
4c3844d9 1184 if (flow_flag_test(flow, CT)) {
aedd133d 1185 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1186 return;
1187 }
1188
f94d6389
CM		 1189#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1190 if (flow_flag_test(flow, SAMPLE)) {
0027d70c 1191 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
f94d6389
CM		 1192 return;
1193 }
1194#endif
1195
c620b772 1196 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1197 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1198
89e39467 1199offload_rule_0:
6d2a3ed0
OG		 1200 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1201}
1202
0d9f9647 1203struct mlx5_flow_handle *
5dbe906f
PB		 1204mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1205 struct mlx5e_tc_flow *flow,
178f69b4 1206 struct mlx5_flow_spec *spec)
5dbe906f 1207{
c620b772 1208 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1209 struct mlx5_flow_handle *rule;
1210
c620b772
AL		 1211 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1212 if (!slow_attr)
1213 return ERR_PTR(-ENOMEM);
5dbe906f 1214
c620b772
AL		 1215 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1216 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1217 slow_attr->esw_attr->split_count = 0;
1218 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1219
1220 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1221 if (!IS_ERR(rule))
226f2ca3 1222 flow_flag_set(flow, SLOW);
5dbe906f 1223
c620b772
AL		 1224 kfree(slow_attr);
1225
5dbe906f
PB		 1226 return rule;
1227}
1228
0d9f9647
VB		 1229void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1230 struct mlx5e_tc_flow *flow)
5dbe906f 1231{
c620b772 1232 struct mlx5_flow_attr *slow_attr;
178f69b4 1233
c620b772 1234 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1235 if (!slow_attr) {
1236 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1237 return;
1238 }
c620b772
AL		 1239
1240 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1241 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1242 slow_attr->esw_attr->split_count = 0;
1243 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1244 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1245 flow_flag_clear(flow, SLOW);
c620b772 1246 kfree(slow_attr);
5dbe906f
PB		 1247}
1248
ad86755b
VB		 1249/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1250 * function.
1251 */
1252static void unready_flow_add(struct mlx5e_tc_flow *flow,
1253 struct list_head *unready_flows)
1254{
1255 flow_flag_set(flow, NOT_READY);
1256 list_add_tail(&flow->unready, unready_flows);
1257}
1258
1259/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1260 * function.
1261 */
1262static void unready_flow_del(struct mlx5e_tc_flow *flow)
1263{
1264 list_del(&flow->unready);
1265 flow_flag_clear(flow, NOT_READY);
1266}
1267
b4a23329
RD		 1268static void add_unready_flow(struct mlx5e_tc_flow *flow)
1269{
1270 struct mlx5_rep_uplink_priv *uplink_priv;
1271 struct mlx5e_rep_priv *rpriv;
1272 struct mlx5_eswitch *esw;
1273
1274 esw = flow->priv->mdev->priv.eswitch;
1275 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1276 uplink_priv = &rpriv->uplink_priv;
1277
ad86755b
VB		 1278 mutex_lock(&uplink_priv->unready_flows_lock);
1279 unready_flow_add(flow, &uplink_priv->unready_flows);
1280 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1281}
1282
1283static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1284{
ad86755b
VB		 1285 struct mlx5_rep_uplink_priv *uplink_priv;
1286 struct mlx5e_rep_priv *rpriv;
1287 struct mlx5_eswitch *esw;
1288
1289 esw = flow->priv->mdev->priv.eswitch;
1290 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1291 uplink_priv = &rpriv->uplink_priv;
1292
1293 mutex_lock(&uplink_priv->unready_flows_lock);
1294 unready_flow_del(flow);
1295 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1296}
1297
10742efc
VB		 1298static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1299
a508728a 1300bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1301{
1302 struct mlx5_core_dev *out_mdev, *route_mdev;
1303 struct mlx5e_priv *out_priv, *route_priv;
1304
1305 out_priv = netdev_priv(out_dev);
1306 out_mdev = out_priv->mdev;
1307 route_priv = netdev_priv(route_dev);
1308 route_mdev = route_priv->mdev;
1309
1310 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1311 route_mdev->coredev_type != MLX5_COREDEV_VF)
1312 return false;
1313
1314 return same_hw_devs(out_priv, route_priv);
1315}
1316
a508728a 1317int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1318{
1319 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1320 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1321 struct mlx5_core_dev *route_mdev;
1322 struct mlx5_eswitch *esw;
1323 u16 vhca_id;
1324 int err;
1325
1326 out_priv = netdev_priv(out_dev);
1327 esw = out_priv->mdev->priv.eswitch;
1328 route_priv = netdev_priv(route_dev);
1329 route_mdev = route_priv->mdev;
1330
1331 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1332 if (mlx5_lag_is_active(out_priv->mdev)) {
1333 /* In lag case we may get devices from different eswitch instances.
1334 * If we failed to get vport num, it means, mostly, that we on the wrong
1335 * eswitch.
1336 */
1337 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1338 if (err != -ENOENT)
1339 return err;
1340
1341 devcom = out_priv->mdev->priv.devcom;
1342 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1343 if (!esw)
1344 return -ENODEV;
1345 }
1346
10742efc 1347 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1348 if (devcom)
1349 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1350 return err;
1351}
1352
c7b9038d
VB		 1353int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1354 struct mlx5e_tc_flow_parse_attr *parse_attr,
1355 struct mlx5e_tc_flow *flow)
1356{
1357 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1358 struct mlx5_modify_hdr *mod_hdr;
1359
1360 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1361 get_flow_name_space(flow),
1362 mod_hdr_acts->num_actions,
1363 mod_hdr_acts->actions);
1364 if (IS_ERR(mod_hdr))
1365 return PTR_ERR(mod_hdr);
1366
1367 WARN_ON(flow->attr->modify_hdr);
1368 flow->attr->modify_hdr = mod_hdr;
1369
1370 return 0;
1371}
1372
c83954ab 1373static int
74491de9 1374mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1375 struct mlx5e_tc_flow *flow,
1376 struct netlink_ext_ack *extack)
adb4c123
OG		 1377{
1378 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1379 struct mlx5e_tc_flow_parse_attr *parse_attr;
1380 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1381 bool vf_tun = false, encap_valid = true;
fe7738eb 1382 struct net_device *encap_dev = NULL;
c620b772 1383 struct mlx5_esw_flow_attr *esw_attr;
3c37745e
OG		 1384 struct mlx5e_rep_priv *rpriv;
1385 struct mlx5e_priv *out_priv;
97a8d29a 1386 struct mlx5_fc *counter;
39ac237c 1387 u32 max_prio, max_chain;
0ad060ee 1388 int err = 0;
f493f155 1389 int out_index;
8b32580d 1390
84179981
PB		 1391 /* We check chain range only for tc flows.
1392 * For ft flows, we checked attr->chain was originally 0 and set it to
1393 * FDB_FT_CHAIN which is outside tc range.
1394 * See mlx5e_rep_setup_ft_cb().
1395 */
ae430332 1396 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1397 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1398 NL_SET_ERR_MSG_MOD(extack,
1399 "Requested chain is out of supported range");
8914add2
VB		 1400 err = -EOPNOTSUPP;
1401 goto err_out;
bf07aa73
PB		 1402 }
1403
ae430332 1404 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1405 if (attr->prio > max_prio) {
61644c3d
RD		 1406 NL_SET_ERR_MSG_MOD(extack,
1407 "Requested priority is out of supported range");
8914add2
VB		 1408 err = -EOPNOTSUPP;
1409 goto err_out;
bf07aa73 1410 }
e52c2802 1411
777bb800
VB		 1412 if (flow_flag_test(flow, TUN_RX)) {
1413 err = mlx5e_attach_decap_route(priv, flow);
1414 if (err)
8914add2 1415 goto err_out;
777bb800
VB		 1416 }
1417
14e6b038
EC		 1418 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1419 err = mlx5e_attach_decap(priv, flow, extack);
1420 if (err)
8914add2 1421 goto err_out;
14e6b038
EC		 1422 }
1423
c620b772
AL		 1424 parse_attr = attr->parse_attr;
1425 esw_attr = attr->esw_attr;
1426
f493f155 1427 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1428 struct net_device *out_dev;
8c4dc42b
EB		 1429 int mirred_ifindex;
1430
c620b772 1431 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1432 continue;
1433
7040632d 1434 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1435 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1436 if (!out_dev) {
1437 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1438 err = -ENODEV;
1439 goto err_out;
1440 }
733d4f36 1441 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1442 extack, &encap_dev, &encap_valid);
fe7738eb 1443 dev_put(out_dev);
0ad060ee 1444 if (err)
8914add2 1445 goto err_out;
0ad060ee 1446
8914add2
VB		 1447 if (esw_attr->dests[out_index].flags &
1448 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1449 vf_tun = true;
3c37745e
OG		 1450 out_priv = netdev_priv(encap_dev);
1451 rpriv = out_priv->ppriv;
c620b772
AL		 1452 esw_attr->dests[out_index].rep = rpriv->rep;
1453 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1454 }
1455
7d1a3d08
VB		 1456 if (vf_tun && esw_attr->out_count > 1) {
1457 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1458 err = -EOPNOTSUPP;
1459 goto err_out;
1460 }
1461
8b32580d 1462 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1463 if (err)
8914add2 1464 goto err_out;
adb4c123 1465
d5a3c2b6
RD		 1466 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1467 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1468 if (vf_tun) {
1469 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1470 if (err)
1471 goto err_out;
1472 } else {
1473 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1474 if (err)
1475 goto err_out;
1476 }
d7e75a32
OG		 1477 }
1478
b8aee822 1479 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1480 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1481 if (IS_ERR(counter)) {
1482 err = PTR_ERR(counter);
1483 goto err_out;
1484 }
b8aee822
MB		 1485
1486 attr->counter = counter;
1487 }
1488
0ad060ee
RD		 1489 /* we get here if one of the following takes place:
1490 * (1) there's no error
1491 * (2) there's an encap action and we don't have valid neigh
3c37745e 1492 */
bc1d75fa 1493 if (!encap_valid)
178f69b4 1494 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1495 else
6d2a3ed0 1496 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1497
8914add2
VB		 1498 if (IS_ERR(flow->rule[0])) {
1499 err = PTR_ERR(flow->rule[0]);
1500 goto err_out;
1501 }
1502 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1503
1504 return 0;
8914add2
VB		 1505
1506err_out:
1507 flow_flag_set(flow, FAILED);
1508 return err;
aa0cbbae 1509}
d85cdccb 1510
9272e3df
YK		 1511static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1512{
c620b772 1513 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1514 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1515 spec->match_value,
1516 misc_parameters_3);
1517 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1518 headers_v,
1519 geneve_tlv_option_0_data);
1520
1521 return !!geneve_tlv_opt_0_data;
1522}
1523
d85cdccb
OG		 1524static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1525 struct mlx5e_tc_flow *flow)
1526{
1527 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1528 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1529 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1530 bool vf_tun = false;
f493f155 1531 int out_index;
d85cdccb 1532
777bb800 1533 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1534 mlx5e_put_flow_tunnel_id(flow);
1535
12a240a4 1536 if (flow_flag_test(flow, NOT_READY))
b4a23329 1537 remove_unready_flow(flow);
ef06c9ee 1538
226f2ca3
VB		 1539 if (mlx5e_is_offloaded_flow(flow)) {
1540 if (flow_flag_test(flow, SLOW))
178f69b4 1541 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1542 else
1543 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1544 }
d85cdccb 1545
9272e3df
YK		 1546 if (mlx5_flow_has_geneve_opt(flow))
1547 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1548
513f8f7f 1549 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1550
777bb800
VB		 1551 if (flow->decap_route)
1552 mlx5e_detach_decap_route(priv, flow);
1553
1554 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1555 if (esw_attr->dests[out_index].flags &
1556 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1557 vf_tun = true;
777bb800 1558 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1559 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1560 kfree(attr->parse_attr->tun_info[out_index]);
1561 }
777bb800 1562 }
d7e75a32 1563
aedd133d 1564 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1565
c7b9038d
VB		 1566 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1567 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1568 if (vf_tun && attr->modify_hdr)
1569 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1570 else
1571 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1572 }
bcd6740c 1573 kfree(attr->sample_attr);
8914add2
VB		 1574 kvfree(attr->parse_attr);
1575 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1576
1577 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1578 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1579
1580 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1581 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1582
1583 kfree(flow->attr);
d85cdccb
OG		 1584}
1585
0d9f9647 1586struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1587{
c620b772 1588 return flow->attr->counter;
b8aee822
MB		 1589}
1590
6a06c2f7 1591/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1592void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1593{
1594 struct mlx5e_tc_flow *flow, *tmp;
1595
1596 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1597 mlx5e_flow_put(priv, flow);
1598}
1599
04de7dda
RD		 1600static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1601{
1602 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1603
226f2ca3
VB		 1604 if (!flow_flag_test(flow, ESWITCH) ||
1605 !flow_flag_test(flow, DUP))
04de7dda
RD		 1606 return;
1607
1608 mutex_lock(&esw->offloads.peer_mutex);
1609 list_del(&flow->peer);
1610 mutex_unlock(&esw->offloads.peer_mutex);
1611
226f2ca3 1612 flow_flag_clear(flow, DUP);
04de7dda 1613
eb252c3a
RD		 1614 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1615 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1616 kfree(flow->peer_flow);
1617 }
1618
04de7dda
RD		 1619 flow->peer_flow = NULL;
1620}
1621
1622static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1623{
1624 struct mlx5_core_dev *dev = flow->priv->mdev;
1625 struct mlx5_devcom *devcom = dev->priv.devcom;
1626 struct mlx5_eswitch *peer_esw;
1627
1628 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1629 if (!peer_esw)
1630 return;
1631
1632 __mlx5e_tc_del_fdb_peer_flow(flow);
1633 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1634}
1635
e8f887ac 1636static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1637 struct mlx5e_tc_flow *flow)
e8f887ac 1638{
226f2ca3 1639 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1640 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1641 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1642 } else {
d85cdccb 1643 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1644 }
e8f887ac
AV		 1645}
1646
ee950e5d 1647static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1648{
1649 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1650 struct flow_action *flow_action = &rule->action;
1651 const struct flow_action_entry *act;
1652 int i;
1653
ee950e5d
CM		 1654 if (chain)
1655 return false;
1656
0a7fcb78
PB		 1657 flow_action_for_each(i, act, flow_action) {
1658 switch (act->id) {
1659 case FLOW_ACTION_GOTO:
1660 return true;
ee950e5d
CM		 1661 case FLOW_ACTION_SAMPLE:
1662 return true;
0a7fcb78
PB		 1663 default:
1664 continue;
1665 }
1666 }
1667
1668 return false;
1669}
bbd00f7e 1670
0a7fcb78
PB		 1671static int
1672enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1673 struct flow_dissector_key_enc_opts *opts,
1674 struct netlink_ext_ack *extack,
1675 bool *dont_care)
1676{
1677 struct geneve_opt *opt;
1678 int off = 0;
1679
1680 *dont_care = true;
1681
1682 while (opts->len > off) {
1683 opt = (struct geneve_opt *)&opts->data[off];
1684
1685 if (!(*dont_care) || opt->opt_class || opt->type ||
1686 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1687 *dont_care = false;
1688
c51323ee 1689 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1690 opt->type != U8_MAX) {
0a7fcb78
PB		 1691 NL_SET_ERR_MSG(extack,
1692 "Partial match of tunnel options in chain > 0 isn't supported");
1693 netdev_warn(priv->netdev,
1694 "Partial match of tunnel options in chain > 0 isn't supported");
1695 return -EOPNOTSUPP;
1696 }
1697 }
1698
1699 off += sizeof(struct geneve_opt) + opt->length * 4;
1700 }
1701
1702 return 0;
1703}
1704
1705#define COPY_DISSECTOR(rule, diss_key, dst)\
1706({ \
1707 struct flow_rule *__rule = (rule);\
1708 typeof(dst) __dst = dst;\
1709\
1710 memcpy(__dst,\
1711 skb_flow_dissector_target(__rule->match.dissector,\
1712 diss_key,\
1713 __rule->match.key),\
1714 sizeof(*__dst));\
1715})
1716
1717static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1718 struct mlx5e_tc_flow *flow,
1719 struct flow_cls_offload *f,
1720 struct net_device *filter_dev)
bbd00f7e 1721{
f9e30088 1722 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1723 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1724 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1725 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1726 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1727 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1728 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1729 struct mlx5e_rep_priv *uplink_rpriv;
1730 struct tunnel_match_key tunnel_key;
1731 bool enc_opts_is_dont_care = true;
1732 u32 tun_id, enc_opts_id = 0;
1733 struct mlx5_eswitch *esw;
1734 u32 value, mask;
8f256622 1735 int err;
2e72eb43 1736
0a7fcb78
PB		 1737 esw = priv->mdev->priv.eswitch;
1738 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1739 uplink_priv = &uplink_rpriv->uplink_priv;
1740
1741 memset(&tunnel_key, 0, sizeof(tunnel_key));
1742 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1743 &tunnel_key.enc_control);
1744 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1745 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1746 &tunnel_key.enc_ipv4);
1747 else
1748 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1749 &tunnel_key.enc_ipv6);
1750 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1751 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1752 &tunnel_key.enc_tp);
1753 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1754 &tunnel_key.enc_key_id);
1755 tunnel_key.filter_ifindex = filter_dev->ifindex;
1756
1757 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1758 if (err)
101f4de9 1759 return err;
bbd00f7e 1760
0a7fcb78
PB		 1761 flow_rule_match_enc_opts(rule, &enc_opts_match);
1762 err = enc_opts_is_dont_care_or_full_match(priv,
1763 enc_opts_match.mask,
1764 extack,
1765 &enc_opts_is_dont_care);
1766 if (err)
1767 goto err_enc_opts;
fe1587a7 1768
0a7fcb78 1769 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1770 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1771 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1772 sizeof(*enc_opts_match.key));
1773 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1774 sizeof(*enc_opts_match.mask));
1775
0a7fcb78 1776 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1777 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1778 if (err)
1779 goto err_enc_opts;
1780 }
fe1587a7 1781
0a7fcb78
PB		 1782 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1783 mask = enc_opts_id ? TUNNEL_ID_MASK :
1784 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1785
0a7fcb78
PB		 1786 if (attr->chain) {
1787 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1788 TUNNEL_TO_REG, value, mask);
1789 } else {
1790 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1791 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1792 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1793 TUNNEL_TO_REG, value);
1794 if (err)
1795 goto err_set;
fe1587a7 1796
0a7fcb78 1797 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1798 }
bbd00f7e 1799
0a7fcb78
PB		 1800 flow->tunnel_id = value;
1801 return 0;
bcef735c 1802
0a7fcb78
PB		 1803err_set:
1804 if (enc_opts_id)
1805 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1806 enc_opts_id);
1807err_enc_opts:
1808 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1809 return err;
1810}
bcef735c 1811
0a7fcb78
PB		 1812static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1813{
1814 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1815 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1816 struct mlx5_rep_uplink_priv *uplink_priv;
1817 struct mlx5e_rep_priv *uplink_rpriv;
1818 struct mlx5_eswitch *esw;
bcef735c 1819
0a7fcb78
PB		 1820 esw = flow->priv->mdev->priv.eswitch;
1821 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1822 uplink_priv = &uplink_rpriv->uplink_priv;
1823
1824 if (tun_id)
1825 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1826 if (enc_opts_id)
1827 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1828 enc_opts_id);
1829}
e98bedf5 1830
4c3844d9
PB		 1831u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1832{
1833 return flow->tunnel_id;
1834}
1835
fca53304
EB		 1836void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1837 struct flow_match_basic *match, bool outer,
1838 void *headers_c, void *headers_v)
1839{
1840 bool ip_version_cap;
1841
1842 ip_version_cap = outer ?
1843 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1844 ft_field_support.outer_ip_version) :
1845 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1846 ft_field_support.inner_ip_version);
1847
1848 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1849 (match->key->n_proto == htons(ETH_P_IP) ||
1850 match->key->n_proto == htons(ETH_P_IPV6))) {
1851 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1852 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1853 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1854 } else {
1855 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1856 ntohs(match->mask->n_proto));
1857 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1858 ntohs(match->key->n_proto));
1859 }
4a5d5d73
EB		 1860}
1861
0d9f9647 1862u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1863{
1864 void *headers_v;
1865 u16 ethertype;
1866 u8 ip_version;
1867
1868 if (outer)
1869 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1870 else
1871 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1872
1873 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1874 /* Return ip_version converted from ethertype anyway */
1875 if (!ip_version) {
1876 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1877 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1878 ip_version = 4;
1879 else if (ethertype == ETH_P_IPV6)
1880 ip_version = 6;
1881 }
1882 return ip_version;
1883}
1884
bbd00f7e 1885static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1886 struct mlx5e_tc_flow *flow,
bbd00f7e 1887 struct mlx5_flow_spec *spec,
f9e30088 1888 struct flow_cls_offload *f,
0a7fcb78
PB		 1889 struct net_device *filter_dev,
1890 u8 *match_level,
1891 bool *match_inner)
bbd00f7e 1892{
a508728a 1893 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1894 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1895 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1896 bool needs_mapping, sets_mapping;
8f256622 1897 int err;
2e72eb43 1898
0a7fcb78
PB		 1899 if (!mlx5e_is_eswitch_flow(flow))
1900 return -EOPNOTSUPP;
1901
c620b772 1902 needs_mapping = !!flow->attr->chain;
ee950e5d 1903 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 1904 *match_inner = !needs_mapping;
1905
1906 if ((needs_mapping || sets_mapping) &&
636bb968 1907 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1908 NL_SET_ERR_MSG(extack,
636bb968 1909 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1910 netdev_warn(priv->netdev,
636bb968 1911 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1912 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1913 }
1914
c620b772 1915 if (!flow->attr->chain) {
0a7fcb78
PB		 1916 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1917 match_level);
1918 if (err) {
e98bedf5 1919 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1920 "Failed to parse tunnel attributes");
1921 netdev_warn(priv->netdev,
1922 "Failed to parse tunnel attributes");
1923 return err;
e98bedf5
EB		 1924 }
1925
14e6b038
EC		 1926 /* With mpls over udp we decapsulate using packet reformat
1927 * object
1928 */
1929 if (!netif_is_bareudp(filter_dev))
c620b772 1930 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1931 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1932 if (err)
1933 return err;
1934 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1935 struct mlx5_flow_spec *tmp_spec;
1936
1937 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1938 if (!tmp_spec) {
1939 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1940 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1941 return -ENOMEM;
1942 }
1943 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1944
1945 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1946 if (err) {
1947 kvfree(tmp_spec);
1948 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1949 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1950 return err;
1951 }
1952 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1953 kvfree(tmp_spec);
1954 if (err)
1955 return err;
bcef735c
OG		 1956 }
1957
0a7fcb78
PB		 1958 if (!needs_mapping && !sets_mapping)
1959 return 0;
bbd00f7e 1960
0a7fcb78 1961 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1962}
bbd00f7e 1963
0a7fcb78 1964static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1965{
0a7fcb78
PB		 1966 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1967 inner_headers);
bbd00f7e
HHZ		 1968}
1969
0a7fcb78 1970static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1971{
0a7fcb78
PB		 1972 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1973 inner_headers);
1974}
1975
1976static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1977{
1978 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1979 outer_headers);
1980}
1981
1982static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1983{
1984 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1985 outer_headers);
8377629e
EB		 1986}
1987
1988static void *get_match_headers_value(u32 flags,
1989 struct mlx5_flow_spec *spec)
1990{
1991 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1992 get_match_inner_headers_value(spec) :
1993 get_match_outer_headers_value(spec);
1994}
1995
1996static void *get_match_headers_criteria(u32 flags,
1997 struct mlx5_flow_spec *spec)
1998{
1999 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2000 get_match_inner_headers_criteria(spec) :
2001 get_match_outer_headers_criteria(spec);
8377629e
EB		 2002}
2003
6d65bc64 2004static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2005 struct flow_cls_offload *f)
2006{
2007 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2008 struct netlink_ext_ack *extack = f->common.extack;
2009 struct net_device *ingress_dev;
2010 struct flow_match_meta match;
2011
2012 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2013 return 0;
2014
2015 flow_rule_match_meta(rule, &match);
e3e0f9b2 2016 if (!match.mask->ingress_ifindex)
2017 return 0;
2018
6d65bc64 2019 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2020 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2021 return -EOPNOTSUPP;
6d65bc64 2022 }
2023
2024 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2025 match.key->ingress_ifindex);
2026 if (!ingress_dev) {
2027 NL_SET_ERR_MSG_MOD(extack,
2028 "Can't find the ingress port to match on");
a683012a 2029 return -ENOENT;
6d65bc64 2030 }
2031
2032 if (ingress_dev != filter_dev) {
2033 NL_SET_ERR_MSG_MOD(extack,
2034 "Can't match on the ingress filter port");
a683012a 2035 return -EOPNOTSUPP;
6d65bc64 2036 }
2037
2038 return 0;
2039}
2040
72046a91
EC		 2041static bool skip_key_basic(struct net_device *filter_dev,
2042 struct flow_cls_offload *f)
2043{
2044 /* When doing mpls over udp decap, the user needs to provide
2045 * MPLS_UC as the protocol in order to be able to match on mpls
2046 * label fields. However, the actual ethertype is IP so we want to
2047 * avoid matching on this, otherwise we'll fail the match.
2048 */
2049 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2050 return true;
2051
2052 return false;
2053}
2054
de0af0bf 2055static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2056 struct mlx5e_tc_flow *flow,
de0af0bf 2057 struct mlx5_flow_spec *spec,
f9e30088 2058 struct flow_cls_offload *f,
54c177ca 2059 struct net_device *filter_dev,
93b3586e 2060 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2061{
e98bedf5 2062 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2063 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2064 outer_headers);
2065 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2066 outer_headers);
699e96dd
JL		 2067 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2068 misc_parameters);
2069 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2070 misc_parameters);
a3222a2d
MD		 2071 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2072 misc_parameters_3);
2073 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2074 misc_parameters_3);
f9e30088 2075 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2076 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2077 enum fs_flow_table_type fs_type;
e3a2b7ed
AV		 2078 u16 addr_type = 0;
2079 u8 ip_proto = 0;
93b3586e 2080 u8 *match_level;
6d65bc64 2081 int err;
e3a2b7ed 2082
afe93f71 2083 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2084 match_level = outer_match_level;
de0af0bf 2085
8f256622 2086 if (dissector->used_keys &
3d144578
VB		 2087 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2088 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2089 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2090 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2091 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2092 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2093 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2094 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2095 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2096 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2097 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2098 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2099 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2100 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2101 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2102 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2103 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2104 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2105 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2106 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2107 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2108 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2109 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2110 dissector->used_keys);
e3a2b7ed
AV		 2111 return -EOPNOTSUPP;
2112 }
2113
075973c7 2114 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2115 bool match_inner = false;
bbd00f7e 2116
0a7fcb78
PB		 2117 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2118 outer_match_level, &match_inner);
2119 if (err)
2120 return err;
2121
2122 if (match_inner) {
2123 /* header pointers should point to the inner headers
2124 * if the packet was decapsulated already.
2125 * outer headers are set by parse_tunnel_attr.
2126 */
2127 match_level = inner_match_level;
2128 headers_c = get_match_inner_headers_criteria(spec);
2129 headers_v = get_match_inner_headers_value(spec);
2130 }
bbd00f7e
HHZ		 2131 }
2132
6d65bc64 2133 err = mlx5e_flower_parse_meta(filter_dev, f);
2134 if (err)
2135 return err;
2136
72046a91
EC		 2137 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2138 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2139 struct flow_match_basic match;
2140
2141 flow_rule_match_basic(rule, &match);
fca53304
EB		 2142 mlx5e_tc_set_ethertype(priv->mdev, &match,
2143 match_level == outer_match_level,
2144 headers_c, headers_v);
e3a2b7ed 2145
8f256622 2146 if (match.mask->n_proto)
d708f902 2147 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2148 }
35a605db
EB		 2149 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2150 is_vlan_dev(filter_dev)) {
2151 struct flow_dissector_key_vlan filter_dev_mask;
2152 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2153 struct flow_match_vlan match;
2154
35a605db
EB		 2155 if (is_vlan_dev(filter_dev)) {
2156 match.key = &filter_dev_key;
2157 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2158 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2159 match.key->vlan_priority = 0;
2160 match.mask = &filter_dev_mask;
2161 memset(match.mask, 0xff, sizeof(*match.mask));
2162 match.mask->vlan_priority = 0;
2163 } else {
2164 flow_rule_match_vlan(rule, &match);
2165 }
8f256622
PNA		 2166 if (match.mask->vlan_id ||
2167 match.mask->vlan_priority ||
2168 match.mask->vlan_tpid) {
2169 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2170 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2171 svlan_tag, 1);
2172 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2173 svlan_tag, 1);
2174 } else {
2175 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2176 cvlan_tag, 1);
2177 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2178 cvlan_tag, 1);
2179 }
095b6cfd 2180
8f256622
PNA		 2181 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2182 match.mask->vlan_id);
2183 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2184 match.key->vlan_id);
358d79a4 2185
8f256622
PNA		 2186 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2187 match.mask->vlan_priority);
2188 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2189 match.key->vlan_priority);
54782900 2190
d708f902 2191 *match_level = MLX5_MATCH_L2;
54782900 2192 }
d3a80bb5 2193 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2194 /* cvlan_tag enabled in match criteria and
2195 * disabled in match value means both S & C tags
2196 * don't exist (untagged of both)
2197 */
cee26487 2198 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2199 *match_level = MLX5_MATCH_L2;
54782900
OG		 2200 }
2201
8f256622
PNA		 2202 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2203 struct flow_match_vlan match;
2204
12d5cbf8 2205 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2206 if (match.mask->vlan_id ||
2207 match.mask->vlan_priority ||
2208 match.mask->vlan_tpid) {
afe93f71
RD		 2209 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2210 fs_type)) {
2211 NL_SET_ERR_MSG_MOD(extack,
2212 "Matching on CVLAN is not supported");
2213 return -EOPNOTSUPP;
2214 }
2215
8f256622 2216 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2217 MLX5_SET(fte_match_set_misc, misc_c,
2218 outer_second_svlan_tag, 1);
2219 MLX5_SET(fte_match_set_misc, misc_v,
2220 outer_second_svlan_tag, 1);
2221 } else {
2222 MLX5_SET(fte_match_set_misc, misc_c,
2223 outer_second_cvlan_tag, 1);
2224 MLX5_SET(fte_match_set_misc, misc_v,
2225 outer_second_cvlan_tag, 1);
2226 }
2227
2228 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2229 match.mask->vlan_id);
699e96dd 2230 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2231 match.key->vlan_id);
699e96dd 2232 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2233 match.mask->vlan_priority);
699e96dd 2234 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2235 match.key->vlan_priority);
699e96dd
JL		 2236
2237 *match_level = MLX5_MATCH_L2;
0faddfe6 2238 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2239 }
2240 }
2241
8f256622
PNA		 2242 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2243 struct flow_match_eth_addrs match;
54782900 2244
8f256622 2245 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2246 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2247 dmac_47_16),
8f256622 2248 match.mask->dst);
d3a80bb5
OG		 2249 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2250 dmac_47_16),
8f256622 2251 match.key->dst);
d3a80bb5
OG		 2252
2253 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2254 smac_47_16),
8f256622 2255 match.mask->src);
d3a80bb5
OG		 2256 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2257 smac_47_16),
8f256622 2258 match.key->src);
d3a80bb5 2259
8f256622
PNA		 2260 if (!is_zero_ether_addr(match.mask->src) ||
2261 !is_zero_ether_addr(match.mask->dst))
d708f902 2262 *match_level = MLX5_MATCH_L2;
54782900
OG		 2263 }
2264
8f256622
PNA		 2265 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2266 struct flow_match_control match;
54782900 2267
8f256622
PNA		 2268 flow_rule_match_control(rule, &match);
2269 addr_type = match.key->addr_type;
54782900
OG		 2270
2271 /* the HW doesn't support frag first/later */
8f256622 2272 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2273 return -EOPNOTSUPP;
2274
8f256622 2275 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2276 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2277 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2278 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2279
2280 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2281 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2282 *match_level = MLX5_MATCH_L2;
54782900
OG		 2283 /* *** L2 attributes parsing up to here *** */
2284 else
83621b7d 2285 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2286 }
2287 }
2288
8f256622
PNA		 2289 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2290 struct flow_match_basic match;
2291
2292 flow_rule_match_basic(rule, &match);
2293 ip_proto = match.key->ip_proto;
54782900
OG		 2294
2295 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2296 match.mask->ip_proto);
54782900 2297 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2298 match.key->ip_proto);
54782900 2299
8f256622 2300 if (match.mask->ip_proto)
d708f902 2301 *match_level = MLX5_MATCH_L3;
54782900
OG		 2302 }
2303
e3a2b7ed 2304 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2305 struct flow_match_ipv4_addrs match;
e3a2b7ed 2306
8f256622 2307 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2308 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2309 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2310 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2311 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2312 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2313 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2314 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2315 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2316 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2317 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2318 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2319 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2320
8f256622 2321 if (match.mask->src || match.mask->dst)
d708f902 2322 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2323 }
2324
2325 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2326 struct flow_match_ipv6_addrs match;
e3a2b7ed 2327
8f256622 2328 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2329 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2330 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2331 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2332 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2333 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2334 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2335
2336 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2337 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2338 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2339 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2340 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2341 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2342
8f256622
PNA		 2343 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2344 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2345 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2346 }
2347
8f256622
PNA		 2348 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2349 struct flow_match_ip match;
1f97a526 2350
8f256622
PNA		 2351 flow_rule_match_ip(rule, &match);
2352 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2353 match.mask->tos & 0x3);
2354 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2355 match.key->tos & 0x3);
1f97a526 2356
8f256622
PNA		 2357 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2358 match.mask->tos >> 2);
2359 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2360 match.key->tos >> 2);
1f97a526 2361
8f256622
PNA		 2362 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2363 match.mask->ttl);
2364 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2365 match.key->ttl);
1f97a526 2366
8f256622 2367 if (match.mask->ttl &&
a8ade55f 2368 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2369 ft_field_support.outer_ipv4_ttl)) {
2370 NL_SET_ERR_MSG_MOD(extack,
2371 "Matching on TTL is not supported");
1f97a526 2372 return -EOPNOTSUPP;
e98bedf5 2373 }
a8ade55f 2374
8f256622 2375 if (match.mask->tos || match.mask->ttl)
d708f902 2376 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2377 }
2378
54782900
OG		 2379 /* *** L3 attributes parsing up to here *** */
2380
8f256622
PNA		 2381 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2382 struct flow_match_ports match;
2383
2384 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2385 switch (ip_proto) {
2386 case IPPROTO_TCP:
2387 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2388 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2389 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2390 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2391
2392 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2393 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2394 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2395 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2396 break;
2397
2398 case IPPROTO_UDP:
2399 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2400 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2401 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2402 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2403
2404 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2405 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2406 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2407 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2408 break;
2409 default:
e98bedf5
EB		 2410 NL_SET_ERR_MSG_MOD(extack,
2411 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2412 netdev_err(priv->netdev,
2413 "Only UDP and TCP transport are supported\n");
2414 return -EINVAL;
2415 }
de0af0bf 2416
8f256622 2417 if (match.mask->src || match.mask->dst)
d708f902 2418 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2419 }
2420
8f256622
PNA		 2421 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2422 struct flow_match_tcp match;
e77834ec 2423
8f256622 2424 flow_rule_match_tcp(rule, &match);
e77834ec 2425 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2426 ntohs(match.mask->flags));
e77834ec 2427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2428 ntohs(match.key->flags));
e77834ec 2429
8f256622 2430 if (match.mask->flags)
d708f902 2431 *match_level = MLX5_MATCH_L4;
e77834ec 2432 }
a3222a2d
MD		 2433 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2434 struct flow_match_icmp match;
e77834ec 2435
a3222a2d
MD		 2436 flow_rule_match_icmp(rule, &match);
2437 switch (ip_proto) {
2438 case IPPROTO_ICMP:
2439 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2440 MLX5_FLEX_PROTO_ICMP))
2441 return -EOPNOTSUPP;
2442 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2443 match.mask->type);
2444 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2445 match.key->type);
2446 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2447 match.mask->code);
2448 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2449 match.key->code);
2450 break;
2451 case IPPROTO_ICMPV6:
2452 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2453 MLX5_FLEX_PROTO_ICMPV6))
2454 return -EOPNOTSUPP;
2455 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2456 match.mask->type);
2457 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2458 match.key->type);
2459 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2460 match.mask->code);
2461 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2462 match.key->code);
2463 break;
2464 default:
2465 NL_SET_ERR_MSG_MOD(extack,
2466 "Code and type matching only with ICMP and ICMPv6");
2467 netdev_err(priv->netdev,
2468 "Code and type matching only with ICMP and ICMPv6\n");
2469 return -EINVAL;
2470 }
2471 if (match.mask->code || match.mask->type) {
2472 *match_level = MLX5_MATCH_L4;
2473 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2474 }
2475 }
39c538d6 2476 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2477 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2478 !netif_is_bareudp(filter_dev)) {
2479 NL_SET_ERR_MSG_MOD(extack,
2480 "Matching on MPLS is supported only for MPLS over UDP");
2481 netdev_err(priv->netdev,
2482 "Matching on MPLS is supported only for MPLS over UDP\n");
2483 return -EOPNOTSUPP;
2484 }
2485
e3a2b7ed
AV		 2486 return 0;
2487}
2488
de0af0bf 2489static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2490 struct mlx5e_tc_flow *flow,
de0af0bf 2491 struct mlx5_flow_spec *spec,
f9e30088 2492 struct flow_cls_offload *f,
54c177ca 2493 struct net_device *filter_dev)
de0af0bf 2494{
93b3586e 2495 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2496 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2497 struct mlx5_core_dev *dev = priv->mdev;
2498 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2499 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2500 struct mlx5_eswitch_rep *rep;
226f2ca3 2501 bool is_eswitch_flow;
de0af0bf
RD		 2502 int err;
2503
93b3586e
HN		 2504 inner_match_level = MLX5_MATCH_NONE;
2505 outer_match_level = MLX5_MATCH_NONE;
2506
0a7fcb78
PB		 2507 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2508 &inner_match_level, &outer_match_level);
93b3586e
HN		 2509 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2510 outer_match_level : inner_match_level;
de0af0bf 2511
226f2ca3
VB		 2512 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2513 if (!err && is_eswitch_flow) {
1d447a39 2514 rep = rpriv->rep;
b05af6aa 2515 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2516 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2517 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2518 NL_SET_ERR_MSG_MOD(extack,
2519 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2520 netdev_warn(priv->netdev,
2521 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2522 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2523 return -EOPNOTSUPP;
2524 }
2525 }
2526
c620b772
AL		 2527 flow->attr->inner_match_level = inner_match_level;
2528 flow->attr->outer_match_level = outer_match_level;
2529
38aa51c1 2530
de0af0bf
RD		 2531 return err;
2532}
2533
d79b6df6
OG		 2534struct pedit_headers {
2535 struct ethhdr eth;
0eb69bb9 2536 struct vlan_hdr vlan;
d79b6df6
OG		 2537 struct iphdr ip4;
2538 struct ipv6hdr ip6;
2539 struct tcphdr tcp;
2540 struct udphdr udp;
2541};
2542
c500c86b
PNA		 2543struct pedit_headers_action {
2544 struct pedit_headers vals;
2545 struct pedit_headers masks;
2546 u32 pedits;
2547};
2548
d79b6df6 2549static int pedit_header_offsets[] = {
73867881
PNA		 2550 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2551 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2552 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2553 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2554 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2555};
2556
2557#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2558
2559static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2560 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2561{
2562 u32 *curr_pmask, *curr_pval;
2563
c500c86b
PNA		 2564 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2565 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2566
2567 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2568 goto out_err;
2569
2570 *curr_pmask |= mask;
2571 *curr_pval |= (val & mask);
2572
2573 return 0;
2574
2575out_err:
2576 return -EOPNOTSUPP;
2577}
2578
2579struct mlx5_fields {
2580 u8 field;
88f30bbc
DL		 2581 u8 field_bsize;
2582 u32 field_mask;
d79b6df6 2583 u32 offset;
27c11b6b 2584 u32 match_offset;
d79b6df6
OG		 2585};
2586
88f30bbc
DL		 2587#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2588 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2589 offsetof(struct pedit_headers, field) + (off), \
2590 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2591
2ef86872
EB		 2592/* masked values are the same and there are no rewrites that do not have a
2593 * match.
2594 */
2595#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2596 type matchmaskx = *(type *)(matchmaskp); \
2597 type matchvalx = *(type *)(matchvalp); \
2598 type maskx = *(type *)(maskp); \
2599 type valx = *(type *)(valp); \
2600 \
2601 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2602 matchmaskx)); \
2603})
2604
27c11b6b 2605static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2606 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2607{
2608 bool same = false;
2609
88f30bbc
DL		 2610 switch (bsize) {
2611 case 8:
2ef86872 2612 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2613 break;
88f30bbc 2614 case 16:
2ef86872 2615 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2616 break;
88f30bbc 2617 case 32:
2ef86872 2618 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2619 break;
2620 }
2621
2622 return same;
2623}
a8e4f0c4 2624
d79b6df6 2625static struct mlx5_fields fields[] = {
88f30bbc
DL		 2626 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2627 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2628 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2629 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2630 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2631 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2632
ab9341b5 2633 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2634 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2635 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2636 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2637
2638 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2639 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2640 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2641 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2642 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2643 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2644 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2645 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2646 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2647 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2648 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2649 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2650 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2651 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2652 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2653 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2654 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2655 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2656
88f30bbc
DL		 2657 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2658 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2659 /* in linux iphdr tcp_flags is 8 bits long */
2660 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2661
88f30bbc
DL		 2662 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2663 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2664};
2665
82198d8b
MD		 2666static unsigned long mask_to_le(unsigned long mask, int size)
2667{
2668 __be32 mask_be32;
2669 __be16 mask_be16;
2670
2671 if (size == 32) {
2672 mask_be32 = (__force __be32)(mask);
2673 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2674 } else if (size == 16) {
2675 mask_be32 = (__force __be32)(mask);
2676 mask_be16 = *(__be16 *)&mask_be32;
2677 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2678 }
2679
2680 return mask;
2681}
6ae4a6a5
PB		 2682static int offload_pedit_fields(struct mlx5e_priv *priv,
2683 int namespace,
2684 struct pedit_headers_action *hdrs,
e98bedf5 2685 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2686 u32 *action_flags,
e98bedf5 2687 struct netlink_ext_ack *extack)
d79b6df6
OG		 2688{
2689 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2690 int i, action_size, first, last, next_z;
88f30bbc
DL		 2691 void *headers_c, *headers_v, *action, *vals_p;
2692 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2693 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2694 struct mlx5_fields *f;
82198d8b 2695 unsigned long mask, field_mask;
6ae4a6a5 2696 int err;
88f30bbc
DL		 2697 u8 cmd;
2698
6ae4a6a5 2699 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2700 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2701 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2702
73867881
PNA		 2703 set_masks = &hdrs[0].masks;
2704 add_masks = &hdrs[1].masks;
2705 set_vals = &hdrs[0].vals;
2706 add_vals = &hdrs[1].vals;
d79b6df6 2707
d65dbedf 2708 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2709
2710 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2711 bool skip;
2712
d79b6df6
OG		 2713 f = &fields[i];
2714 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2715 s_mask = 0;
2716 a_mask = 0;
d79b6df6
OG		 2717
2718 s_masks_p = (void *)set_masks + f->offset;
2719 a_masks_p = (void *)add_masks + f->offset;
2720
88f30bbc
DL		 2721 s_mask = *s_masks_p & f->field_mask;
2722 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2723
2724 if (!s_mask && !a_mask) /* nothing to offload here */
2725 continue;
2726
2727 if (s_mask && a_mask) {
e98bedf5
EB		 2728 NL_SET_ERR_MSG_MOD(extack,
2729 "can't set and add to the same HW field");
61b6a6c3
CH		 2730 netdev_warn(priv->netdev,
2731 "mlx5: can't set and add to the same HW field (%x)\n",
2732 f->field);
d79b6df6
OG		 2733 return -EOPNOTSUPP;
2734 }
2735
27c11b6b 2736 skip = false;
d79b6df6 2737 if (s_mask) {
27c11b6b
EB		 2738 void *match_mask = headers_c + f->match_offset;
2739 void *match_val = headers_v + f->match_offset;
2740
d79b6df6
OG		 2741 cmd = MLX5_ACTION_TYPE_SET;
2742 mask = s_mask;
2743 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2744 /* don't rewrite if we have a match on the same value */
2745 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2746 match_mask, f->field_bsize))
27c11b6b 2747 skip = true;
d79b6df6 2748 /* clear to denote we consumed this field */
88f30bbc 2749 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2750 } else {
2751 cmd = MLX5_ACTION_TYPE_ADD;
2752 mask = a_mask;
2753 vals_p = (void *)add_vals + f->offset;
27c11b6b 2754 /* add 0 is no change */
88f30bbc 2755 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2756 skip = true;
d79b6df6 2757 /* clear to denote we consumed this field */
88f30bbc 2758 *a_masks_p &= ~f->field_mask;
d79b6df6 2759 }
27c11b6b
EB		 2760 if (skip)
2761 continue;
d79b6df6 2762
82198d8b 2763 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2764
88f30bbc
DL		 2765 first = find_first_bit(&mask, f->field_bsize);
2766 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2767 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2768 if (first < next_z && next_z < last) {
e98bedf5
EB		 2769 NL_SET_ERR_MSG_MOD(extack,
2770 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2771 netdev_warn(priv->netdev,
2772 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2773 mask);
d79b6df6
OG		 2774 return -EOPNOTSUPP;
2775 }
2776
6ae4a6a5
PB		 2777 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2778 if (err) {
2779 NL_SET_ERR_MSG_MOD(extack,
2780 "too many pedit actions, can't offload");
2781 mlx5_core_warn(priv->mdev,
2782 "mlx5: parsed %d pedit actions, can't do more\n",
2783 mod_acts->num_actions);
2784 return err;
2785 }
2786
2787 action = mod_acts->actions +
2788 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2789 MLX5_SET(set_action_in, action, action_type, cmd);
2790 MLX5_SET(set_action_in, action, field, f->field);
2791
2792 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2793 int start;
2794
82198d8b
MD		 2795 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2796
88f30bbc 2797 /* if field is bit sized it can start not from first bit */
82198d8b 2798 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2799
2800 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2801 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2802 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2803 }
2804
88f30bbc 2805 if (f->field_bsize == 32)
2b64beba 2806 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2807 else if (f->field_bsize == 16)
2b64beba 2808 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2809 else if (f->field_bsize == 8)
2b64beba 2810 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2811
6ae4a6a5 2812 ++mod_acts->num_actions;
d79b6df6
OG		 2813 }
2814
d79b6df6
OG		 2815 return 0;
2816}
2817
2cc1cb1d
TZ		 2818static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2819 int namespace)
2820{
2821 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2822 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2823 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2824 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2825}
2826
6ae4a6a5
PB		 2827int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2828 int namespace,
2829 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2830{
6ae4a6a5
PB		 2831 int action_size, new_num_actions, max_hw_actions;
2832 size_t new_sz, old_sz;
2833 void *ret;
d79b6df6 2834
6ae4a6a5
PB		 2835 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2836 return 0;
d79b6df6 2837
d65dbedf 2838 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2839
6ae4a6a5
PB		 2840 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2841 namespace);
2842 new_num_actions = min(max_hw_actions,
2843 mod_hdr_acts->actions ?
2844 mod_hdr_acts->max_actions * 2 : 1);
2845 if (mod_hdr_acts->max_actions == new_num_actions)
2846 return -ENOSPC;
2847
2848 new_sz = action_size * new_num_actions;
2849 old_sz = mod_hdr_acts->max_actions * action_size;
2850 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2851 if (!ret)
d79b6df6
OG		 2852 return -ENOMEM;
2853
6ae4a6a5
PB		 2854 memset(ret + old_sz, 0, new_sz - old_sz);
2855 mod_hdr_acts->actions = ret;
2856 mod_hdr_acts->max_actions = new_num_actions;
2857
d79b6df6
OG		 2858 return 0;
2859}
2860
6ae4a6a5
PB		 2861void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2862{
2863 kfree(mod_hdr_acts->actions);
2864 mod_hdr_acts->actions = NULL;
2865 mod_hdr_acts->num_actions = 0;
2866 mod_hdr_acts->max_actions = 0;
2867}
2868
d79b6df6
OG		 2869static const struct pedit_headers zero_masks = {};
2870
582234b4
EC		 2871static int
2872parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2873 const struct flow_action_entry *act, int namespace,
2874 struct mlx5e_tc_flow_parse_attr *parse_attr,
2875 struct pedit_headers_action *hdrs,
2876 struct netlink_ext_ack *extack)
d79b6df6 2877{
73867881
PNA		 2878 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2879 int err = -EOPNOTSUPP;
d79b6df6 2880 u32 mask, val, offset;
73867881 2881 u8 htype;
d79b6df6 2882
73867881
PNA		 2883 htype = act->mangle.htype;
2884 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2885
73867881
PNA		 2886 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2887 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2888 goto out_err;
2889 }
d79b6df6 2890
2cc1cb1d
TZ		 2891 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2892 NL_SET_ERR_MSG_MOD(extack,
2893 "The pedit offload action is not supported");
2894 goto out_err;
2895 }
2896
73867881
PNA		 2897 mask = act->mangle.mask;
2898 val = act->mangle.val;
2899 offset = act->mangle.offset;
d79b6df6 2900
73867881
PNA		 2901 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2902 if (err)
2903 goto out_err;
c500c86b 2904
73867881 2905 hdrs[cmd].pedits++;
d79b6df6 2906
c500c86b
PNA		 2907 return 0;
2908out_err:
2909 return err;
2910}
2911
582234b4
EC		 2912static int
2913parse_pedit_to_reformat(struct mlx5e_priv *priv,
2914 const struct flow_action_entry *act,
2915 struct mlx5e_tc_flow_parse_attr *parse_attr,
2916 struct netlink_ext_ack *extack)
2917{
2918 u32 mask, val, offset;
2919 u32 *p;
2920
2921 if (act->id != FLOW_ACTION_MANGLE)
2922 return -EOPNOTSUPP;
2923
2924 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2925 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2926 return -EOPNOTSUPP;
2927 }
2928
2929 mask = ~act->mangle.mask;
2930 val = act->mangle.val;
2931 offset = act->mangle.offset;
2932 p = (u32 *)&parse_attr->eth;
2933 *(p + (offset >> 2)) |= (val & mask);
2934
2935 return 0;
2936}
2937
2938static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2939 const struct flow_action_entry *act, int namespace,
2940 struct mlx5e_tc_flow_parse_attr *parse_attr,
2941 struct pedit_headers_action *hdrs,
2942 struct mlx5e_tc_flow *flow,
2943 struct netlink_ext_ack *extack)
2944{
2945 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2946 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2947
2948 return parse_pedit_to_modify_hdr(priv, act, namespace,
2949 parse_attr, hdrs, extack);
2950}
2951
c500c86b
PNA		 2952static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2953 struct mlx5e_tc_flow_parse_attr *parse_attr,
2954 struct pedit_headers_action *hdrs,
27c11b6b 2955 u32 *action_flags,
c500c86b
PNA		 2956 struct netlink_ext_ack *extack)
2957{
2958 struct pedit_headers *cmd_masks;
2959 int err;
2960 u8 cmd;
2961
6ae4a6a5
PB		 2962 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2963 action_flags, extack);
d79b6df6
OG		 2964 if (err < 0)
2965 goto out_dealloc_parsed_actions;
2966
2967 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2968 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2969 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2970 NL_SET_ERR_MSG_MOD(extack,
2971 "attempt to offload an unsupported field");
b3a433de 2972 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2973 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2974 16, 1, cmd_masks, sizeof(zero_masks), true);
2975 err = -EOPNOTSUPP;
2976 goto out_dealloc_parsed_actions;
2977 }
2978 }
2979
2980 return 0;
2981
2982out_dealloc_parsed_actions:
6ae4a6a5 2983 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2984 return err;
2985}
2986
e98bedf5
EB		 2987static bool csum_offload_supported(struct mlx5e_priv *priv,
2988 u32 action,
2989 u32 update_flags,
2990 struct netlink_ext_ack *extack)
26c02749
OG		 2991{
2992 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2993 TCA_CSUM_UPDATE_FLAG_UDP;
2994
2995 /* The HW recalcs checksums only if re-writing headers */
2996 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2997 NL_SET_ERR_MSG_MOD(extack,
2998 "TC csum action is only offloaded with pedit");
26c02749
OG		 2999 netdev_warn(priv->netdev,
3000 "TC csum action is only offloaded with pedit\n");
3001 return false;
3002 }
3003
3004 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3005 NL_SET_ERR_MSG_MOD(extack,
3006 "can't offload TC csum action for some header/s");
26c02749
OG		 3007 netdev_warn(priv->netdev,
3008 "can't offload TC csum action for some header/s - flags %#x\n",
3009 update_flags);
3010 return false;
3011 }
3012
3013 return true;
3014}
3015
8998576b
DL		 3016struct ip_ttl_word {
3017 __u8 ttl;
3018 __u8 protocol;
3019 __sum16 check;
3020};
3021
3022struct ipv6_hoplimit_word {
3023 __be16 payload_len;
3024 __u8 nexthdr;
3025 __u8 hop_limit;
3026};
3027
4c3844d9
PB		 3028static int is_action_keys_supported(const struct flow_action_entry *act,
3029 bool ct_flow, bool *modify_ip_header,
7e36feeb 3030 bool *modify_tuple,
4c3844d9 3031 struct netlink_ext_ack *extack)
8998576b
DL		 3032{
3033 u32 mask, offset;
3034 u8 htype;
3035
3036 htype = act->mangle.htype;
3037 offset = act->mangle.offset;
3038 mask = ~act->mangle.mask;
3039 /* For IPv4 & IPv6 header check 4 byte word,
3040 * to determine that modified fields
3041 * are NOT ttl & hop_limit only.
3042 */
3043 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3044 struct ip_ttl_word *ttl_word =
3045 (struct ip_ttl_word *)&mask;
3046
3047 if (offset != offsetof(struct iphdr, ttl) ||
3048 ttl_word->protocol ||
3049 ttl_word->check) {
4c3844d9
PB		 3050 *modify_ip_header = true;
3051 }
3052
7e36feeb
PB		 3053 if (offset >= offsetof(struct iphdr, saddr))
3054 *modify_tuple = true;
3055
3056 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3057 NL_SET_ERR_MSG_MOD(extack,
3058 "can't offload re-write of ipv4 address with action ct");
3059 return -EOPNOTSUPP;
8998576b
DL		 3060 }
3061 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3062 struct ipv6_hoplimit_word *hoplimit_word =
3063 (struct ipv6_hoplimit_word *)&mask;
3064
3065 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3066 hoplimit_word->payload_len ||
3067 hoplimit_word->nexthdr) {
4c3844d9
PB		 3068 *modify_ip_header = true;
3069 }
3070
7e36feeb
PB		 3071 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3072 *modify_tuple = true;
3073
3074 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3075 NL_SET_ERR_MSG_MOD(extack,
3076 "can't offload re-write of ipv6 address with action ct");
3077 return -EOPNOTSUPP;
8998576b 3078 }
7e36feeb
PB		 3079 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3080 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3081 *modify_tuple = true;
3082 if (ct_flow) {
3083 NL_SET_ERR_MSG_MOD(extack,
3084 "can't offload re-write of transport header ports with action ct");
3085 return -EOPNOTSUPP;
3086 }
8998576b 3087 }
4c3844d9
PB		 3088
3089 return 0;
8998576b
DL		 3090}
3091
96b5b458
DC		 3092static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3093 bool ct_flow, struct netlink_ext_ack *extack,
3094 struct mlx5e_priv *priv,
3095 struct mlx5_flow_spec *spec)
3096{
3097 if (!modify_tuple || ct_clear)
3098 return true;
3099
3100 if (ct_flow) {
3101 NL_SET_ERR_MSG_MOD(extack,
3102 "can't offload tuple modification with non-clear ct()");
3103 netdev_info(priv->netdev,
3104 "can't offload tuple modification with non-clear ct()");
3105 return false;
3106 }
3107
3108 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3109 * (or after clear action), as otherwise, since the tuple is changed,
3110 * we can't restore ct state
3111 */
3112 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3113 NL_SET_ERR_MSG_MOD(extack,
3114 "can't offload tuple modification with ct matches and no ct(clear) action");
3115 netdev_info(priv->netdev,
3116 "can't offload tuple modification with ct matches and no ct(clear) action");
3117 return false;
3118 }
3119
3120 return true;
3121}
3122
3d486ec4
OS		 3123static bool modify_header_match_supported(struct mlx5e_priv *priv,
3124 struct mlx5_flow_spec *spec,
73867881 3125 struct flow_action *flow_action,
4c3844d9 3126 u32 actions, bool ct_flow,
7e36feeb 3127 bool ct_clear,
e98bedf5 3128 struct netlink_ext_ack *extack)
bdd66ac0 3129{
73867881 3130 const struct flow_action_entry *act;
7e36feeb 3131 bool modify_ip_header, modify_tuple;
fca53304 3132 void *headers_c;
bdd66ac0
OG		 3133 void *headers_v;
3134 u16 ethertype;
8998576b 3135 u8 ip_proto;
4c3844d9 3136 int i, err;
bdd66ac0 3137
fca53304 3138 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3139 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3140 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3141
3142 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3143 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3144 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3145 goto out_ok;
3146
3147 modify_ip_header = false;
7e36feeb 3148 modify_tuple = false;
73867881
PNA		 3149 flow_action_for_each(i, act, flow_action) {
3150 if (act->id != FLOW_ACTION_MANGLE &&
3151 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3152 continue;
3153
4c3844d9 3154 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3155 &modify_ip_header,
3156 &modify_tuple, extack);
4c3844d9
PB		 3157 if (err)
3158 return err;
bdd66ac0
OG		 3159 }
3160
96b5b458
DC		 3161 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3162 priv, spec))
7e36feeb 3163 return false;
7e36feeb 3164
bdd66ac0 3165 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3166 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3167 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3168 NL_SET_ERR_MSG_MOD(extack,
3169 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3170 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3171 ip_proto);
bdd66ac0
OG		 3172 return false;
3173 }
3174
3175out_ok:
3176 return true;
3177}
3178
3179static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3180 struct flow_action *flow_action,
bdd66ac0 3181 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3182 struct mlx5e_tc_flow *flow,
3183 struct netlink_ext_ack *extack)
bdd66ac0 3184{
a7c119bd 3185 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3186 u32 actions;
3187
c620b772
AL		 3188 ct_clear = flow->attr->ct_attr.ct_action &
3189 TCA_CT_ACT_CLEAR;
3190 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3191 actions = flow->attr->action;
3192
4c3844d9 3193 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3194 if (flow->attr->esw_attr->split_count && ct_flow &&
3195 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3196 /* All registers used by ct are cleared when using
3197 * split rules.
3198 */
3199 NL_SET_ERR_MSG_MOD(extack,
3200 "Can't offload mirroring with action ct");
49397b80 3201 return false;
4c3844d9 3202 }
4c3844d9 3203 }
bdd66ac0
OG		 3204
3205 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3206 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3207 flow_action, actions,
7e36feeb
PB		 3208 ct_flow, ct_clear,
3209 extack);
bdd66ac0
OG		 3210
3211 return true;
3212}
3213
32134847
MD		 3214static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3215{
3216 return priv->mdev == peer_priv->mdev;
3217}
3218
5c65c564
OG		 3219static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3220{
3221 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3222 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3223
3224 fmdev = priv->mdev;
3225 pmdev = peer_priv->mdev;
3226
59c9d35e
AH		 3227 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3228 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3229
816f6706 3230 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3231}
3232
bb569657
AL		 3233static bool same_vf_reps(struct mlx5e_priv *priv,
3234 struct net_device *out_dev)
3235{
3236 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3237 priv->netdev == out_dev;
3238}
3239
bdc837ee
EB		 3240static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3241 const struct flow_action_entry *act,
3242 struct mlx5e_tc_flow_parse_attr *parse_attr,
3243 struct pedit_headers_action *hdrs,
3244 u32 *action, struct netlink_ext_ack *extack)
3245{
3246 u16 mask16 = VLAN_VID_MASK;
3247 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3248 const struct flow_action_entry pedit_act = {
3249 .id = FLOW_ACTION_MANGLE,
3250 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3251 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3252 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3253 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3254 };
6fca9d1e 3255 u8 match_prio_mask, match_prio_val;
bf2f3bca 3256 void *headers_c, *headers_v;
bdc837ee
EB		 3257 int err;
3258
bf2f3bca
EB		 3259 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3260 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3261
3262 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3263 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3264 NL_SET_ERR_MSG_MOD(extack,
3265 "VLAN rewrite action must have VLAN protocol match");
3266 return -EOPNOTSUPP;
3267 }
3268
6fca9d1e
EB		 3269 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3270 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3271 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3272 NL_SET_ERR_MSG_MOD(extack,
3273 "Changing VLAN prio is not supported");
bdc837ee
EB		 3274 return -EOPNOTSUPP;
3275 }
3276
582234b4 3277 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3278 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3279
3280 return err;
3281}
3282
0bac1194
EB		 3283static int
3284add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3285 struct mlx5e_tc_flow_parse_attr *parse_attr,
3286 struct pedit_headers_action *hdrs,
3287 u32 *action, struct netlink_ext_ack *extack)
3288{
3289 const struct flow_action_entry prio_tag_act = {
3290 .vlan.vid = 0,
3291 .vlan.prio =
3292 MLX5_GET(fte_match_set_lyr_2_4,
3293 get_match_headers_value(*action,
3294 &parse_attr->spec),
3295 first_prio) &
3296 MLX5_GET(fte_match_set_lyr_2_4,
3297 get_match_headers_criteria(*action,
3298 &parse_attr->spec),
3299 first_prio),
3300 };
3301
3302 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3303 &prio_tag_act, parse_attr, hdrs, action,
3304 extack);
3305}
3306
c7569097
AL		 3307static int validate_goto_chain(struct mlx5e_priv *priv,
3308 struct mlx5e_tc_flow *flow,
3309 const struct flow_action_entry *act,
3310 u32 actions,
3311 struct netlink_ext_ack *extack)
3312{
3313 bool is_esw = mlx5e_is_eswitch_flow(flow);
3314 struct mlx5_flow_attr *attr = flow->attr;
3315 bool ft_flow = mlx5e_is_ft_flow(flow);
3316 u32 dest_chain = act->chain_index;
3317 struct mlx5_fs_chains *chains;
3318 struct mlx5_eswitch *esw;
3319 u32 reformat_and_fwd;
3320 u32 max_chain;
3321
3322 esw = priv->mdev->priv.eswitch;
3323 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3324 max_chain = mlx5_chains_get_chain_range(chains);
3325 reformat_and_fwd = is_esw ?
3326 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3327 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3328
3329 if (ft_flow) {
3330 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3331 return -EOPNOTSUPP;
3332 }
3333
3334 if (!mlx5_chains_backwards_supported(chains) &&
3335 dest_chain <= attr->chain) {
3336 NL_SET_ERR_MSG_MOD(extack,
3337 "Goto lower numbered chain isn't supported");
3338 return -EOPNOTSUPP;
3339 }
3340
3341 if (dest_chain > max_chain) {
3342 NL_SET_ERR_MSG_MOD(extack,
3343 "Requested destination chain is out of supported range");
3344 return -EOPNOTSUPP;
3345 }
3346
3347 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3348 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3349 !reformat_and_fwd) {
3350 NL_SET_ERR_MSG_MOD(extack,
3351 "Goto chain is not allowed if action has reformat or decap");
3352 return -EOPNOTSUPP;
3353 }
3354
3355 return 0;
3356}
3357
73867881
PNA		 3358static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3359 struct flow_action *flow_action,
e98bedf5
EB		 3360 struct mlx5e_tc_flow *flow,
3361 struct netlink_ext_ack *extack)
e3a2b7ed 3362{
c6cfe113 3363 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3364 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3365 struct pedit_headers_action hdrs[2] = {};
3366 const struct flow_action_entry *act;
c620b772 3367 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3368 u32 action = 0;
244cd96a 3369 int err, i;
e3a2b7ed 3370
73867881 3371 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3372 return -EINVAL;
3373
53eca1f3
JK		 3374 if (!flow_action_hw_stats_check(flow_action, extack,
3375 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3376 return -EOPNOTSUPP;
3377
c620b772 3378 nic_attr = attr->nic_attr;
c620b772 3379 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3380 parse_attr = attr->parse_attr;
e3a2b7ed 3381
73867881
PNA		 3382 flow_action_for_each(i, act, flow_action) {
3383 switch (act->id) {
15fc92ec
TZ		 3384 case FLOW_ACTION_ACCEPT:
3385 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3386 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3387 break;
73867881 3388 case FLOW_ACTION_DROP:
950b4df9
RD		 3389 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3390 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3391 break;
3392 case FLOW_ACTION_MANGLE:
3393 case FLOW_ACTION_ADD:
3394 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3395 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3396 if (err)
3397 return err;
3398
c7569097 3399 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3400 break;
bdc837ee
EB		 3401 case FLOW_ACTION_VLAN_MANGLE:
3402 err = add_vlan_rewrite_action(priv,
3403 MLX5_FLOW_NAMESPACE_KERNEL,
3404 act, parse_attr, hdrs,
3405 &action, extack);
3406 if (err)
3407 return err;
3408
3409 break;
73867881 3410 case FLOW_ACTION_CSUM:
1cab1cd7 3411 if (csum_offload_supported(priv, action,
73867881 3412 act->csum_flags,
e98bedf5 3413 extack))
73867881 3414 break;
26c02749
OG		 3415
3416 return -EOPNOTSUPP;
73867881
PNA		 3417 case FLOW_ACTION_REDIRECT: {
3418 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3419
3420 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3421 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3422 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3423 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3424 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3425 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3426 } else {
e98bedf5
EB		 3427 NL_SET_ERR_MSG_MOD(extack,
3428 "device is not on same HW, can't offload");
5c65c564
OG		 3429 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3430 peer_dev->name);
25f150f4 3431 return -EOPNOTSUPP;
5c65c564 3432 }
73867881
PNA		 3433 }
3434 break;
3435 case FLOW_ACTION_MARK: {
3436 u32 mark = act->mark;
e3a2b7ed
AV		 3437
3438 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3439 NL_SET_ERR_MSG_MOD(extack,
3440 "Bad flow mark - only 16 bit is supported");
25f150f4 3441 return -EOPNOTSUPP;
e3a2b7ed
AV		 3442 }
3443
c620b772 3444 nic_attr->flow_tag = mark;
1cab1cd7 3445 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3446 }
3447 break;
c7569097
AL		 3448 case FLOW_ACTION_GOTO:
3449 err = validate_goto_chain(priv, flow, act, action,
3450 extack);
3451 if (err)
3452 return err;
3453
3454 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3455 attr->dest_chain = act->chain_index;
3456 break;
aedd133d
AL		 3457 case FLOW_ACTION_CT:
3458 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3459 if (err)
3460 return err;
3461
3462 flow_flag_set(flow, CT);
3463 break;
73867881 3464 default:
2cc1cb1d
TZ		 3465 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3466 return -EOPNOTSUPP;
e3a2b7ed 3467 }
e3a2b7ed
AV		 3468 }
3469
c500c86b
PNA		 3470 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3471 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3472 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3473 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3474 if (err)
3475 return err;
27c11b6b
EB		 3476 /* in case all pedit actions are skipped, remove the MOD_HDR
3477 * flag.
3478 */
6ae4a6a5 3479 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3480 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3481 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3482 }
c500c86b
PNA		 3483 }
3484
1cab1cd7 3485 attr->action = action;
c7569097
AL		 3486
3487 if (attr->dest_chain) {
3488 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3489 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3490 return -EOPNOTSUPP;
3491 }
3492 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3493 }
3494
3495 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3496 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3497
73867881 3498 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3499 return -EOPNOTSUPP;
3500
e3a2b7ed
AV		 3501 return 0;
3502}
3503
32134847 3504static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3505 struct net_device *peer_netdev)
3506{
3507 struct mlx5e_priv *peer_priv;
3508
3509 peer_priv = netdev_priv(peer_netdev);
3510
3511 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3512 mlx5e_eswitch_vf_rep(priv->netdev) &&
3513 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3514 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3515}
3516
1482bd3d 3517static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3518 const struct flow_action_entry *act,
1482bd3d
JL		 3519 struct mlx5_esw_flow_attr *attr,
3520 u32 *action)
3521{
cc495188
JL		 3522 u8 vlan_idx = attr->total_vlan;
3523
3524 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3525 return -EOPNOTSUPP;
3526
73867881
PNA		 3527 switch (act->id) {
3528 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3529 if (vlan_idx) {
3530 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3531 MLX5_FS_VLAN_DEPTH))
3532 return -EOPNOTSUPP;
3533
3534 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3535 } else {
3536 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3537 }
73867881
PNA		 3538 break;
3539 case FLOW_ACTION_VLAN_PUSH:
3540 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3541 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3542 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3543 if (!attr->vlan_proto[vlan_idx])
3544 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3545
3546 if (vlan_idx) {
3547 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3548 MLX5_FS_VLAN_DEPTH))
3549 return -EOPNOTSUPP;
3550
3551 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3552 } else {
3553 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3554 (act->vlan.proto != htons(ETH_P_8021Q) ||
3555 act->vlan.prio))
cc495188
JL		 3556 return -EOPNOTSUPP;
3557
3558 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3559 }
73867881
PNA		 3560 break;
3561 default:
bdc837ee 3562 return -EINVAL;
1482bd3d
JL		 3563 }
3564
cc495188
JL		 3565 attr->total_vlan = vlan_idx + 1;
3566
1482bd3d
JL		 3567 return 0;
3568}
3569
d34eb2fc
OG		 3570static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3571 struct net_device *out_dev)
3572{
3573 struct net_device *fdb_out_dev = out_dev;
3574 struct net_device *uplink_upper;
3575
3576 rcu_read_lock();
3577 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3578 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3579 uplink_upper == out_dev) {
3580 fdb_out_dev = uplink_dev;
3581 } else if (netif_is_lag_master(out_dev)) {
3582 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3583 if (fdb_out_dev &&
3584 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3585 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3586 fdb_out_dev = NULL;
3587 }
3588 rcu_read_unlock();
3589 return fdb_out_dev;
3590}
3591
278748a9 3592static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3593 struct mlx5_flow_attr *attr,
278748a9
EB		 3594 struct net_device **out_dev,
3595 u32 *action)
3596{
3597 struct net_device *vlan_dev = *out_dev;
3598 struct flow_action_entry vlan_act = {
3599 .id = FLOW_ACTION_VLAN_PUSH,
3600 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3601 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3602 .vlan.prio = 0,
3603 };
3604 int err;
3605
c620b772 3606 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3607 if (err)
3608 return err;
3609
dca59f4a
DC		 3610 rcu_read_lock();
3611 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3612 rcu_read_unlock();
3613 if (!*out_dev)
3614 return -ENODEV;
3615
278748a9
EB		 3616 if (is_vlan_dev(*out_dev))
3617 err = add_vlan_push_action(priv, attr, out_dev, action);
3618
3619 return err;
3620}
3621
35a605db 3622static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3623 struct mlx5_flow_attr *attr,
35a605db
EB		 3624 u32 *action)
3625{
35a605db
EB		 3626 struct flow_action_entry vlan_act = {
3627 .id = FLOW_ACTION_VLAN_POP,
3628 };
70f478ca 3629 int nest_level, err = 0;
35a605db 3630
70f478ca
DL		 3631 nest_level = attr->parse_attr->filter_dev->lower_level -
3632 priv->netdev->lower_level;
35a605db 3633 while (nest_level--) {
c620b772 3634 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3635 if (err)
3636 return err;
3637 }
3638
3639 return err;
3640}
3641
32134847
MD		 3642static bool same_hw_reps(struct mlx5e_priv *priv,
3643 struct net_device *peer_netdev)
3644{
3645 struct mlx5e_priv *peer_priv;
3646
3647 peer_priv = netdev_priv(peer_netdev);
3648
3649 return mlx5e_eswitch_rep(priv->netdev) &&
3650 mlx5e_eswitch_rep(peer_netdev) &&
3651 same_hw_devs(priv, peer_priv);
3652}
3653
3654static bool is_lag_dev(struct mlx5e_priv *priv,
3655 struct net_device *peer_netdev)
3656{
3657 return ((mlx5_lag_is_sriov(priv->mdev) ||
3658 mlx5_lag_is_multipath(priv->mdev)) &&
3659 same_hw_reps(priv, peer_netdev));
3660}
3661
f6dc1264
PB		 3662bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3663 struct net_device *out_dev)
3664{
32134847
MD		 3665 if (is_merged_eswitch_vfs(priv, out_dev))
3666 return true;
3667
3668 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3669 return true;
3670
3671 return mlx5e_eswitch_rep(out_dev) &&
32134847 3672 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3673}
3674
554fe75c
DL		 3675static bool is_duplicated_output_device(struct net_device *dev,
3676 struct net_device *out_dev,
3677 int *ifindexes, int if_count,
3678 struct netlink_ext_ack *extack)
3679{
3680 int i;
3681
3682 for (i = 0; i < if_count; i++) {
3683 if (ifindexes[i] == out_dev->ifindex) {
3684 NL_SET_ERR_MSG_MOD(extack,
3685 "can't duplicate output to same device");
3686 netdev_err(dev, "can't duplicate output to same device: %s\n",
3687 out_dev->name);
3688 return true;
3689 }
3690 }
3691
3692 return false;
3693}
3694
613f53fe
EC		 3695static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3696 struct mlx5e_tc_flow *flow,
3697 struct net_device *out_dev,
3698 struct netlink_ext_ack *extack)
3699{
c620b772 3700 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3701 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3702 struct mlx5e_rep_priv *rep_priv;
3703
3704 /* Forwarding non encapsulated traffic between
3705 * uplink ports is allowed only if
3706 * termination_table_raw_traffic cap is set.
3707 *
c620b772 3708 * Input vport was stored attr->in_rep.
613f53fe
EC		 3709 * In LAG case, *priv* is the private data of
3710 * uplink which may be not the input vport.
3711 */
3712 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3713
3714 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3715 mlx5e_eswitch_uplink_rep(out_dev)))
3716 return 0;
3717
3718 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3719 termination_table_raw_traffic)) {
3720 NL_SET_ERR_MSG_MOD(extack,
3721 "devices are both uplink, can't offload forwarding");
3722 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3723 priv->netdev->name, out_dev->name);
3724 return -EOPNOTSUPP;
3725 } else if (out_dev != rep_priv->netdev) {
3726 NL_SET_ERR_MSG_MOD(extack,
3727 "devices are not the same uplink, can't offload forwarding");
3728 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3729 priv->netdev->name, out_dev->name);
3730 return -EOPNOTSUPP;
3731 }
3732 return 0;
3733}
3734
73867881
PNA		 3735static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3736 struct flow_action *flow_action,
e98bedf5 3737 struct mlx5e_tc_flow *flow,
70f8019e 3738 struct netlink_ext_ack *extack)
03a9d11e 3739{
73867881 3740 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3741 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3742 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3743 struct mlx5e_rep_priv *rpriv = priv->ppriv;
bcd6740c 3744 struct mlx5e_sample_attr sample_attr = {};
73867881 3745 const struct ip_tunnel_info *info = NULL;
c620b772 3746 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3747 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3748 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3749 const struct flow_action_entry *act;
c620b772 3750 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 3751 bool encap = false, decap = false;
3752 u32 action = attr->action;
554fe75c 3753 int err, i, if_count = 0;
f828ca6a 3754 bool mpls_push = false;
03a9d11e 3755
73867881 3756 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3757 return -EINVAL;
3758
53eca1f3
JK		 3759 if (!flow_action_hw_stats_check(flow_action, extack,
3760 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3761 return -EOPNOTSUPP;
3762
c620b772
AL		 3763 esw_attr = attr->esw_attr;
3764 parse_attr = attr->parse_attr;
3765
73867881
PNA		 3766 flow_action_for_each(i, act, flow_action) {
3767 switch (act->id) {
3768 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3769 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3770 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3771 break;
f0288210
EC		 3772 case FLOW_ACTION_TRAP:
3773 if (!flow_offload_has_one_action(flow_action)) {
3774 NL_SET_ERR_MSG_MOD(extack,
3775 "action trap is supported as a sole action only");
3776 return -EOPNOTSUPP;
3777 }
3778 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3779 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3780 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3781 break;
f828ca6a
EC		 3782 case FLOW_ACTION_MPLS_PUSH:
3783 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3784 reformat_l2_to_l3_tunnel) ||
3785 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3786 NL_SET_ERR_MSG_MOD(extack,
3787 "mpls push is supported only for mpls_uc protocol");
3788 return -EOPNOTSUPP;
3789 }
3790 mpls_push = true;
3791 break;
14e6b038
EC		 3792 case FLOW_ACTION_MPLS_POP:
3793 /* we only support mpls pop if it is the first action
3794 * and the filter net device is bareudp. Subsequent
3795 * actions can be pedit and the last can be mirred
3796 * egress redirect.
3797 */
3798 if (i) {
3799 NL_SET_ERR_MSG_MOD(extack,
3800 "mpls pop supported only as first action");
3801 return -EOPNOTSUPP;
3802 }
70f8019e 3803 if (!netif_is_bareudp(parse_attr->filter_dev)) {
14e6b038
EC		 3804 NL_SET_ERR_MSG_MOD(extack,
3805 "mpls pop supported only on bareudp devices");
3806 return -EOPNOTSUPP;
3807 }
3808
3809 parse_attr->eth.h_proto = act->mpls_pop.proto;
3810 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3811 flow_flag_set(flow, L3_TO_L2_DECAP);
3812 break;
73867881
PNA		 3813 case FLOW_ACTION_MANGLE:
3814 case FLOW_ACTION_ADD:
3815 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3816 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3817 if (err)
3818 return err;
3819
582234b4
EC		 3820 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3821 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3822 esw_attr->split_count = esw_attr->out_count;
582234b4 3823 }
73867881
PNA		 3824 break;
3825 case FLOW_ACTION_CSUM:
1cab1cd7 3826 if (csum_offload_supported(priv, action,
73867881
PNA		 3827 act->csum_flags, extack))
3828 break;
26c02749
OG		 3829
3830 return -EOPNOTSUPP;
73867881
PNA		 3831 case FLOW_ACTION_REDIRECT:
3832 case FLOW_ACTION_MIRRED: {
03a9d11e 3833 struct mlx5e_priv *out_priv;
592d3651 3834 struct net_device *out_dev;
03a9d11e 3835
73867881 3836 out_dev = act->dev;
ef381359
OS		 3837 if (!out_dev) {
3838 /* out_dev is NULL when filters with
3839 * non-existing mirred device are replayed to
3840 * the driver.
3841 */
3842 return -EINVAL;
3843 }
03a9d11e 3844
f828ca6a
EC		 3845 if (mpls_push && !netif_is_bareudp(out_dev)) {
3846 NL_SET_ERR_MSG_MOD(extack,
3847 "mpls is supported only through a bareudp device");
3848 return -EOPNOTSUPP;
3849 }
3850
84179981
PB		 3851 if (ft_flow && out_dev == priv->netdev) {
3852 /* Ignore forward to self rules generated
3853 * by adding both mlx5 devs to the flow table
3854 * block on a normal nft offload setup.
3855 */
3856 return -EOPNOTSUPP;
3857 }
3858
c620b772 3859 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3860 NL_SET_ERR_MSG_MOD(extack,
3861 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3862 netdev_warn(priv->netdev,
3863 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3864 esw_attr->out_count);
592d3651
CM		 3865 return -EOPNOTSUPP;
3866 }
3867
f493f155
EB		 3868 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3869 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3870 if (encap) {
c620b772 3871 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3872 out_dev->ifindex;
0d9f9647
VB		 3873 parse_attr->tun_info[esw_attr->out_count] =
3874 mlx5e_dup_tun_info(info);
c620b772 3875 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3876 return -ENOMEM;
3877 encap = false;
c620b772 3878 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3879 MLX5_ESW_DEST_ENCAP;
c620b772 3880 esw_attr->out_count++;
b6a4ac24
VB		 3881 /* attr->dests[].rep is resolved when we
3882 * handle encap
3883 */
3884 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3885 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3886 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3887
554fe75c
DL		 3888 if (is_duplicated_output_device(priv->netdev,
3889 out_dev,
3890 ifindexes,
3891 if_count,
3892 extack))
3893 return -EOPNOTSUPP;
3894
3895 ifindexes[if_count] = out_dev->ifindex;
3896 if_count++;
3897
d34eb2fc
OG		 3898 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3899 if (!out_dev)
3900 return -ENODEV;
7ba58ba7 3901
278748a9
EB		 3902 if (is_vlan_dev(out_dev)) {
3903 err = add_vlan_push_action(priv, attr,
3904 &out_dev,
3905 &action);
3906 if (err)
3907 return err;
3908 }
f6dc1264 3909
35a605db
EB		 3910 if (is_vlan_dev(parse_attr->filter_dev)) {
3911 err = add_vlan_pop_action(priv, attr,
3912 &action);
3913 if (err)
3914 return err;
3915 }
278748a9 3916
613f53fe
EC		 3917 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3918 if (err)
3919 return err;
ffec9702 3920
f6dc1264
PB		 3921 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3922 NL_SET_ERR_MSG_MOD(extack,
3923 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3924 return -EOPNOTSUPP;
f6dc1264 3925 }
a0646c88 3926
bb569657
AL		 3927 if (same_vf_reps(priv, out_dev)) {
3928 NL_SET_ERR_MSG_MOD(extack,
3929 "can't forward from a VF to itself");
3930 return -EOPNOTSUPP;
3931 }
3932
a54e20b4 3933 out_priv = netdev_priv(out_dev);
1d447a39 3934 rpriv = out_priv->ppriv;
c620b772
AL		 3935 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3936 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3937 esw_attr->out_count++;
ef381359
OS		 3938 } else if (parse_attr->filter_dev != priv->netdev) {
3939 /* All mlx5 devices are called to configure
3940 * high level device filters. Therefore, the
3941 * *attempt* to install a filter on invalid
3942 * eswitch should not trigger an explicit error
3943 */
3944 return -EINVAL;
a54e20b4 3945 } else {
e98bedf5
EB		 3946 NL_SET_ERR_MSG_MOD(extack,
3947 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3948 netdev_warn(priv->netdev,
3949 "devices %s %s not on same switch HW, can't offload forwarding\n",
3950 priv->netdev->name,
3951 out_dev->name);
25f150f4 3952 return -EOPNOTSUPP;
03a9d11e 3953 }
73867881
PNA		 3954 }
3955 break;
3956 case FLOW_ACTION_TUNNEL_ENCAP:
3957 info = act->tunnel;
a54e20b4
HHZ		 3958 if (info)
3959 encap = true;
3960 else
3961 return -EOPNOTSUPP;
1482bd3d 3962
73867881
PNA		 3963 break;
3964 case FLOW_ACTION_VLAN_PUSH:
3965 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3966 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3967 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3968 /* Replace vlan pop+push with vlan modify */
3969 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3970 err = add_vlan_rewrite_action(priv,
3971 MLX5_FLOW_NAMESPACE_FDB,
3972 act, parse_attr, hdrs,
3973 &action, extack);
3974 } else {
c620b772 3975 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3976 }
1482bd3d
JL		 3977 if (err)
3978 return err;
3979
c620b772 3980 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3981 break;
3982 case FLOW_ACTION_VLAN_MANGLE:
3983 err = add_vlan_rewrite_action(priv,
3984 MLX5_FLOW_NAMESPACE_FDB,
3985 act, parse_attr, hdrs,
3986 &action, extack);
3987 if (err)
3988 return err;
3989
c620b772 3990 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3991 break;
3992 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3993 decap = true;
73867881 3994 break;
2fbbc30d 3995 case FLOW_ACTION_GOTO:
c7569097
AL		 3996 err = validate_goto_chain(priv, flow, act, action,
3997 extack);
2fbbc30d
EC		 3998 if (err)
3999 return err;
bf07aa73 4000
e88afe75 4001 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4002 attr->dest_chain = act->chain_index;
73867881 4003 break;
4c3844d9 4004 case FLOW_ACTION_CT:
41c2fd94
CM		 4005 if (flow_flag_test(flow, SAMPLE)) {
4006 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4007 return -EOPNOTSUPP;
4008 }
aedd133d 4009 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4010 if (err)
4011 return err;
4012
4013 flow_flag_set(flow, CT);
69e2916e 4014 esw_attr->split_count = esw_attr->out_count;
4c3844d9 4015 break;
41c2fd94
CM		 4016 case FLOW_ACTION_SAMPLE:
4017 if (flow_flag_test(flow, CT)) {
4018 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4019 return -EOPNOTSUPP;
4020 }
bcd6740c
CM		 4021 sample_attr.rate = act->sample.rate;
4022 sample_attr.group_num = act->sample.psample_group->group_num;
41c2fd94 4023 if (act->sample.truncate)
bcd6740c 4024 sample_attr.trunc_size = act->sample.trunc_size;
41c2fd94
CM		 4025 flow_flag_set(flow, SAMPLE);
4026 break;
73867881 4027 default:
2cc1cb1d
TZ		 4028 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4029 return -EOPNOTSUPP;
bf07aa73 4030 }
03a9d11e 4031 }
bdd66ac0 4032
a508728a
VB		 4033 /* always set IP version for indirect table handling */
4034 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4035
0bac1194
EB		 4036 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4037 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4038 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4039 * tag rewrite.
4040 */
4041 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4042 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4043 &action, extack);
4044 if (err)
4045 return err;
4046 }
4047
c500c86b
PNA		 4048 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4049 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4050 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4051 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4052 if (err)
4053 return err;
27c11b6b
EB		 4054 /* in case all pedit actions are skipped, remove the MOD_HDR
4055 * flag. we might have set split_count either by pedit or
4056 * pop/push. if there is no pop/push either, reset it too.
4057 */
6ae4a6a5 4058 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4059 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4060 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4061 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4062 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4063 esw_attr->split_count = 0;
27c11b6b 4064 }
c500c86b
PNA		 4065 }
4066
1cab1cd7 4067 attr->action = action;
73867881 4068 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4069 return -EOPNOTSUPP;
4070
e88afe75 4071 if (attr->dest_chain) {
0a7fcb78
PB		 4072 if (decap) {
4073 /* It can be supported if we'll create a mapping for
4074 * the tunnel device only (without tunnel), and set
4075 * this tunnel id with this decap flow.
4076 *
4077 * On restore (miss), we'll just set this saved tunnel
4078 * device.
4079 */
4080
4081 NL_SET_ERR_MSG(extack,
4082 "Decap with goto isn't supported");
4083 netdev_warn(priv->netdev,
4084 "Decap with goto isn't supported");
4085 return -EOPNOTSUPP;
4086 }
4087
e88afe75
OG		 4088 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4089 }
4090
ae2741e2
VB		 4091 if (!(attr->action &
4092 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4093 NL_SET_ERR_MSG_MOD(extack,
4094 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4095 return -EOPNOTSUPP;
4096 }
4097
c620b772 4098 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4099 NL_SET_ERR_MSG_MOD(extack,
4100 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4101 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4102 return -EOPNOTSUPP;
4103 }
4104
41c2fd94
CM		 4105 /* Allocate sample attribute only when there is a sample action and
4106 * no errors after parsing.
4107 */
4108 if (flow_flag_test(flow, SAMPLE)) {
bcd6740c
CM		 4109 attr->sample_attr = kzalloc(sizeof(*attr->sample_attr), GFP_KERNEL);
4110 if (!attr->sample_attr)
41c2fd94 4111 return -ENOMEM;
bcd6740c 4112 *attr->sample_attr = sample_attr;
41c2fd94
CM		 4113 }
4114
31c8eba5 4115 return 0;
03a9d11e
OG		 4116}
4117
226f2ca3 4118static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4119{
226f2ca3 4120 unsigned long __flow_flags = 0;
60bd4af8 4121
226f2ca3
VB		 4122 if (flags & MLX5_TC_FLAG(INGRESS))
4123 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4124 if (flags & MLX5_TC_FLAG(EGRESS))
4125 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4126
226f2ca3
VB		 4127 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4128 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4129 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4130 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4131 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4132 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4133
60bd4af8
OG		 4134 *flow_flags = __flow_flags;
4135}
4136
05866c82
OG		 4137static const struct rhashtable_params tc_ht_params = {
4138 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4139 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4140 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4141 .automatic_shrinking = true,
4142};
4143
226f2ca3
VB		 4144static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4145 unsigned long flags)
05866c82 4146{
655dc3d2
OG		 4147 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4148 struct mlx5e_rep_priv *uplink_rpriv;
4149
226f2ca3 4150 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4151 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4152 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4153 } else /* NIC offload */
655dc3d2 4154 return &priv->fs.tc.ht;
05866c82
OG		 4155}
4156
04de7dda
RD		 4157static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4158{
c620b772
AL		 4159 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4160 struct mlx5_flow_attr *attr = flow->attr;
4161 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4162 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4163 bool act_is_encap = !!(attr->action &
4164 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4165 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4166 MLX5_DEVCOM_ESW_OFFLOADS);
4167
10fbb1cd
RD		 4168 if (!esw_paired)
4169 return false;
4170
c620b772
AL		 4171 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4172 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4173 (is_rep_ingress || act_is_encap))
4174 return true;
4175
4176 return false;
04de7dda
RD		 4177}
4178
c620b772
AL		 4179struct mlx5_flow_attr *
4180mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4181{
4182 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4183 sizeof(struct mlx5_esw_flow_attr) :
4184 sizeof(struct mlx5_nic_flow_attr);
4185 struct mlx5_flow_attr *attr;
4186
4187 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4188}
4189
a88780a9
RD		 4190static int
4191mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4192 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4193 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4194 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4195{
17091853 4196 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4197 struct mlx5_flow_attr *attr;
3bc4b7bf 4198 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4199 int err = -ENOMEM;
4200 int out_index;
e3a2b7ed 4201
c620b772 4202 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4203 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4204 if (!parse_attr || !flow)
4205 goto err_free;
c620b772
AL		 4206
4207 flow->flags = flow_flags;
4208 flow->cookie = f->cookie;
4209 flow->priv = priv;
4210
4211 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4212 if (!attr)
e3a2b7ed 4213 goto err_free;
ff7ea04a 4214
c620b772 4215 flow->attr = attr;
e3a2b7ed 4216
5a7e5bcb
VB		 4217 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4218 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4219 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4220 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4221 refcount_set(&flow->refcnt, 1);
95435ad7 4222 init_completion(&flow->init_done);
e3a2b7ed 4223
a88780a9
RD		 4224 *__flow = flow;
4225 *__parse_attr = parse_attr;
4226
4227 return 0;
4228
4229err_free:
4230 kfree(flow);
4231 kvfree(parse_attr);
4232 return err;
4233}
4234
c7569097
AL		 4235static void
4236mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4237 struct mlx5e_tc_flow_parse_attr *parse_attr,
4238 struct flow_cls_offload *f)
4239{
4240 attr->parse_attr = parse_attr;
4241 attr->chain = f->common.chain_index;
4242 attr->prio = f->common.prio;
4243}
4244
988ab9c7 4245static void
c620b772 4246mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4247 struct mlx5e_priv *priv,
4248 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4249 struct flow_cls_offload *f,
988ab9c7
TZ		 4250 struct mlx5_eswitch_rep *in_rep,
4251 struct mlx5_core_dev *in_mdev)
4252{
4253 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4254 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4255
c7569097 4256 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4257
4258 esw_attr->in_rep = in_rep;
4259 esw_attr->in_mdev = in_mdev;
4260
4261 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4262 MLX5_COUNTER_SOURCE_ESWITCH)
4263 esw_attr->counter_dev = in_mdev;
4264 else
4265 esw_attr->counter_dev = priv->mdev;
4266}
4267
71129676 4268static struct mlx5e_tc_flow *
04de7dda 4269__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4270 struct flow_cls_offload *f,
226f2ca3 4271 unsigned long flow_flags,
04de7dda
RD		 4272 struct net_device *filter_dev,
4273 struct mlx5_eswitch_rep *in_rep,
71129676 4274 struct mlx5_core_dev *in_mdev)
a88780a9 4275{
f9e30088 4276 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4277 struct netlink_ext_ack *extack = f->common.extack;
4278 struct mlx5e_tc_flow_parse_attr *parse_attr;
4279 struct mlx5e_tc_flow *flow;
4280 int attr_size, err;
e3a2b7ed 4281
226f2ca3 4282 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4283 attr_size = sizeof(struct mlx5_esw_flow_attr);
4284 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4285 &parse_attr, &flow);
4286 if (err)
4287 goto out;
988ab9c7 4288
d11afc26 4289 parse_attr->filter_dev = filter_dev;
c620b772 4290 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4291 priv, parse_attr,
4292 f, in_rep, in_mdev);
4293
54c177ca
OS		 4294 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4295 f, filter_dev);
d11afc26
OS		 4296 if (err)
4297 goto err_free;
a88780a9 4298
7e36feeb 4299 /* actions validation depends on parsing the ct matches first */
aedd133d 4300 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4301 &flow->attr->ct_attr, extack);
a88780a9
RD		 4302 if (err)
4303 goto err_free;
4304
70f8019e 4305 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 4306 if (err)
4307 goto err_free;
4308
7040632d 4309 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4310 complete_all(&flow->init_done);
ef06c9ee
RD		 4311 if (err) {
4312 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4313 goto err_free;
4314
b4a23329 4315 add_unready_flow(flow);
ef06c9ee 4316 }
e3a2b7ed 4317
71129676 4318 return flow;
a88780a9
RD		 4319
4320err_free:
5a7e5bcb 4321 mlx5e_flow_put(priv, flow);
a88780a9 4322out:
71129676 4323 return ERR_PTR(err);
a88780a9
RD		 4324}
4325
f9e30088 4326static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4327 struct mlx5e_tc_flow *flow,
226f2ca3 4328 unsigned long flow_flags)
04de7dda
RD		 4329{
4330 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4331 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4332 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4333 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4334 struct mlx5e_tc_flow_parse_attr *parse_attr;
4335 struct mlx5e_rep_priv *peer_urpriv;
4336 struct mlx5e_tc_flow *peer_flow;
4337 struct mlx5_core_dev *in_mdev;
4338 int err = 0;
4339
4340 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4341 if (!peer_esw)
4342 return -ENODEV;
4343
4344 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4345 peer_priv = netdev_priv(peer_urpriv->netdev);
4346
4347 /* in_mdev is assigned of which the packet originated from.
4348 * So packets redirected to uplink use the same mdev of the
4349 * original flow and packets redirected from uplink use the
4350 * peer mdev.
4351 */
c620b772 4352 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4353 in_mdev = peer_priv->mdev;
4354 else
4355 in_mdev = priv->mdev;
4356
c620b772 4357 parse_attr = flow->attr->parse_attr;
95dc1902 4358 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4359 parse_attr->filter_dev,
c620b772 4360 attr->in_rep, in_mdev);
71129676
JG		 4361 if (IS_ERR(peer_flow)) {
4362 err = PTR_ERR(peer_flow);
04de7dda 4363 goto out;
71129676 4364 }
04de7dda
RD		 4365
4366 flow->peer_flow = peer_flow;
226f2ca3 4367 flow_flag_set(flow, DUP);
04de7dda
RD		 4368 mutex_lock(&esw->offloads.peer_mutex);
4369 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4370 mutex_unlock(&esw->offloads.peer_mutex);
4371
4372out:
4373 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4374 return err;
4375}
4376
4377static int
4378mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4379 struct flow_cls_offload *f,
226f2ca3 4380 unsigned long flow_flags,
04de7dda
RD		 4381 struct net_device *filter_dev,
4382 struct mlx5e_tc_flow **__flow)
4383{
4384 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4385 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4386 struct mlx5_core_dev *in_mdev = priv->mdev;
4387 struct mlx5e_tc_flow *flow;
4388 int err;
4389
71129676
JG		 4390 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4391 in_mdev);
4392 if (IS_ERR(flow))
4393 return PTR_ERR(flow);
04de7dda
RD		 4394
4395 if (is_peer_flow_needed(flow)) {
95dc1902 4396 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4397 if (err) {
4398 mlx5e_tc_del_fdb_flow(priv, flow);
4399 goto out;
4400 }
4401 }
4402
4403 *__flow = flow;
4404
4405 return 0;
4406
4407out:
4408 return err;
4409}
4410
a88780a9
RD		 4411static int
4412mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4413 struct flow_cls_offload *f,
226f2ca3 4414 unsigned long flow_flags,
d11afc26 4415 struct net_device *filter_dev,
a88780a9
RD		 4416 struct mlx5e_tc_flow **__flow)
4417{
f9e30088 4418 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4419 struct netlink_ext_ack *extack = f->common.extack;
4420 struct mlx5e_tc_flow_parse_attr *parse_attr;
4421 struct mlx5e_tc_flow *flow;
4422 int attr_size, err;
4423
c7569097
AL		 4424 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4425 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4426 return -EOPNOTSUPP;
4427 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4428 return -EOPNOTSUPP;
c7569097 4429 }
bf07aa73 4430
226f2ca3 4431 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4432 attr_size = sizeof(struct mlx5_nic_flow_attr);
4433 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4434 &parse_attr, &flow);
4435 if (err)
4436 goto out;
4437
d11afc26 4438 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4439 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4440
54c177ca
OS		 4441 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4442 f, filter_dev);
d11afc26
OS		 4443 if (err)
4444 goto err_free;
4445
aedd133d
AL		 4446 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4447 &flow->attr->ct_attr, extack);
4448 if (err)
4449 goto err_free;
4450
c6cfe113 4451 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4452 if (err)
4453 goto err_free;
4454
c6cfe113 4455 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 4456 if (err)
4457 goto err_free;
4458
226f2ca3 4459 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4460 *__flow = flow;
4461
4462 return 0;
e3a2b7ed 4463
e3a2b7ed 4464err_free:
8914add2 4465 flow_flag_set(flow, FAILED);
e68e28b4 4466 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4467 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4468out:
4469 return err;
4470}
4471
4472static int
4473mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4474 struct flow_cls_offload *f,
226f2ca3 4475 unsigned long flags,
d11afc26 4476 struct net_device *filter_dev,
a88780a9
RD		 4477 struct mlx5e_tc_flow **flow)
4478{
4479 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4480 unsigned long flow_flags;
a88780a9
RD		 4481 int err;
4482
4483 get_flags(flags, &flow_flags);
4484
bf07aa73
PB		 4485 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4486 return -EOPNOTSUPP;
4487
f6455de0 4488 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4489 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4490 filter_dev, flow);
a88780a9 4491 else
d11afc26
OS		 4492 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4493 filter_dev, flow);
a88780a9
RD		 4494
4495 return err;
4496}
4497
553f9328
VP		 4498static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4499 struct mlx5e_rep_priv *rpriv)
4500{
4501 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4502 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4503 * function is called from NIC mode.
553f9328 4504 */
2fb15e72 4505 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4506}
4507
71d82d2a 4508int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4509 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4510{
4511 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4512 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4513 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4514 struct mlx5e_tc_flow *flow;
4515 int err = 0;
4516
7dc84de9
RD		 4517 if (!mlx5_esw_hold(priv->mdev))
4518 return -EAGAIN;
4519
4520 mlx5_esw_get(priv->mdev);
4521
c5d326b2
VB		 4522 rcu_read_lock();
4523 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4524 if (flow) {
553f9328
VP		 4525 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4526 * just return 0.
4527 */
4528 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4529 goto rcu_unlock;
553f9328 4530
a88780a9
RD		 4531 NL_SET_ERR_MSG_MOD(extack,
4532 "flow cookie already exists, ignoring");
4533 netdev_warn_once(priv->netdev,
4534 "flow cookie %lx already exists, ignoring\n",
4535 f->cookie);
0e1c1a2f 4536 err = -EEXIST;
c1aea9e1 4537 goto rcu_unlock;
a88780a9 4538 }
c1aea9e1
VB		 4539rcu_unlock:
4540 rcu_read_unlock();
4541 if (flow)
4542 goto out;
a88780a9 4543
7a978759 4544 trace_mlx5e_configure_flower(f);
d11afc26 4545 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4546 if (err)
4547 goto out;
4548
553f9328
VP		 4549 /* Flow rule offloaded to non-uplink representor sharing tc block,
4550 * set the flow's owner dev.
4551 */
4552 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4553 flow->orig_dev = dev;
4554
c5d326b2 4555 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4556 if (err)
4557 goto err_free;
4558
7dc84de9 4559 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4560 return 0;
4561
4562err_free:
5a7e5bcb 4563 mlx5e_flow_put(priv, flow);
a88780a9 4564out:
7dc84de9
RD		 4565 mlx5_esw_put(priv->mdev);
4566 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4567 return err;
4568}
4569
8f8ae895
OG		 4570static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4571{
226f2ca3
VB		 4572 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4573 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4574
226f2ca3
VB		 4575 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4576 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4577}
4578
71d82d2a 4579int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4580 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4581{
d9ee0491 4582 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4583 struct mlx5e_tc_flow *flow;
c5d326b2 4584 int err;
e3a2b7ed 4585
c5d326b2 4586 rcu_read_lock();
ab818362 4587 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4588 if (!flow || !same_flow_direction(flow, flags)) {
4589 err = -EINVAL;
4590 goto errout;
4591 }
e3a2b7ed 4592
c5d326b2
VB		 4593 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4594 * set.
4595 */
4596 if (flow_flag_test_and_set(flow, DELETED)) {
4597 err = -EINVAL;
4598 goto errout;
4599 }
05866c82 4600 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4601 rcu_read_unlock();
e3a2b7ed 4602
7a978759 4603 trace_mlx5e_delete_flower(f);
5a7e5bcb 4604 mlx5e_flow_put(priv, flow);
e3a2b7ed 4605
7dc84de9 4606 mlx5_esw_put(priv->mdev);
e3a2b7ed 4607 return 0;
c5d326b2
VB		 4608
4609errout:
4610 rcu_read_unlock();
4611 return err;
e3a2b7ed
AV		 4612}
4613
71d82d2a 4614int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4615 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4616{
04de7dda 4617 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4618 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4619 struct mlx5_eswitch *peer_esw;
aad7e08d 4620 struct mlx5e_tc_flow *flow;
aad7e08d 4621 struct mlx5_fc *counter;
316d5f72
RD		 4622 u64 lastuse = 0;
4623 u64 packets = 0;
4624 u64 bytes = 0;
5a7e5bcb 4625 int err = 0;
aad7e08d 4626
c5d326b2
VB		 4627 rcu_read_lock();
4628 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4629 tc_ht_params));
4630 rcu_read_unlock();
5a7e5bcb
VB		 4631 if (IS_ERR(flow))
4632 return PTR_ERR(flow);
4633
4634 if (!same_flow_direction(flow, flags)) {
4635 err = -EINVAL;
4636 goto errout;
4637 }
aad7e08d 4638
4c3844d9 4639 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4640 counter = mlx5e_tc_get_counter(flow);
4641 if (!counter)
5a7e5bcb 4642 goto errout;
aad7e08d 4643
316d5f72
RD		 4644 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4645 }
aad7e08d 4646
316d5f72
RD		 4647 /* Under multipath it's possible for one rule to be currently
4648 * un-offloaded while the other rule is offloaded.
4649 */
04de7dda
RD		 4650 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4651 if (!peer_esw)
4652 goto out;
4653
226f2ca3
VB		 4654 if (flow_flag_test(flow, DUP) &&
4655 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4656 u64 bytes2;
4657 u64 packets2;
4658 u64 lastuse2;
4659
4660 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4661 if (!counter)
4662 goto no_peer_counter;
04de7dda
RD		 4663 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4664
4665 bytes += bytes2;
4666 packets += packets2;
4667 lastuse = max_t(u64, lastuse, lastuse2);
4668 }
4669
316d5f72 4670no_peer_counter:
04de7dda 4671 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4672out:
4b61d3e8 4673 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4674 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4675 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4676errout:
4677 mlx5e_flow_put(priv, flow);
4678 return err;
aad7e08d
AV		 4679}
4680
1fe3e316 4681static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4682 struct netlink_ext_ack *extack)
4683{
4684 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4685 struct mlx5_eswitch *esw;
1fe3e316 4686 u32 rate_mbps = 0;
fcb64c0f 4687 u16 vport_num;
fcb64c0f
EC		 4688 int err;
4689
e401a184
EC		 4690 vport_num = rpriv->rep->vport;
4691 if (vport_num >= MLX5_VPORT_ECPF) {
4692 NL_SET_ERR_MSG_MOD(extack,
4693 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4694 return -EOPNOTSUPP;
4695 }
4696
fcb64c0f
EC		 4697 esw = priv->mdev->priv.eswitch;
4698 /* rate is given in bytes/sec.
4699 * First convert to bits/sec and then round to the nearest mbit/secs.
4700 * mbit means million bits.
4701 * Moreover, if rate is non zero we choose to configure to a minimum of
4702 * 1 mbit/sec.
4703 */
1fe3e316
PP		 4704 if (rate) {
4705 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4706 do_div(rate, 1000000);
4707 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4708 }
4709
2d116e3e 4710 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4711 if (err)
4712 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4713
4714 return err;
4715}
4716
4717static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4718 struct flow_action *flow_action,
4719 struct netlink_ext_ack *extack)
4720{
4721 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4722 const struct flow_action_entry *act;
4723 int err;
4724 int i;
4725
4726 if (!flow_action_has_entries(flow_action)) {
4727 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4728 return -EINVAL;
4729 }
4730
4731 if (!flow_offload_has_one_action(flow_action)) {
4732 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4733 return -EOPNOTSUPP;
4734 }
4735
53eca1f3 4736 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4737 return -EOPNOTSUPP;
4738
fcb64c0f
EC		 4739 flow_action_for_each(i, act, flow_action) {
4740 switch (act->id) {
4741 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4742 if (act->police.rate_pkt_ps) {
4743 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4744 return -EOPNOTSUPP;
4745 }
fcb64c0f
EC		 4746 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4747 if (err)
4748 return err;
4749
4750 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4751 break;
4752 default:
4753 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4754 return -EOPNOTSUPP;
4755 }
4756 }
4757
4758 return 0;
4759}
4760
4761int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4762 struct tc_cls_matchall_offload *ma)
4763{
b5f814cc 4764 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4765 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4766
b5f814cc
EC		 4767 if (!mlx5_esw_qos_enabled(esw)) {
4768 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4769 return -EOPNOTSUPP;
4770 }
4771
7b83355f 4772 if (ma->common.prio != 1) {
fcb64c0f
EC		 4773 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4774 return -EINVAL;
4775 }
4776
4777 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4778}
4779
4780int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4781 struct tc_cls_matchall_offload *ma)
4782{
4783 struct netlink_ext_ack *extack = ma->common.extack;
4784
4785 return apply_police_params(priv, 0, extack);
4786}
4787
4788void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4789 struct tc_cls_matchall_offload *ma)
4790{
4791 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4792 struct rtnl_link_stats64 cur_stats;
4793 u64 dbytes;
4794 u64 dpkts;
4795
4796 cur_stats = priv->stats.vf_vport;
4797 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4798 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4799 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4800 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4801 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4802}
4803
4d8fcf21
AH		 4804static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4805 struct mlx5e_priv *peer_priv)
4806{
4807 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4808 struct mlx5e_hairpin_entry *hpe, *tmp;
4809 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4810 u16 peer_vhca_id;
4811 int bkt;
4812
4813 if (!same_hw_devs(priv, peer_priv))
4814 return;
4815
4816 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4817
b32accda 4818 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4819 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4820 if (refcount_inc_not_zero(&hpe->refcnt))
4821 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4822 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4823
4824 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4825 wait_for_completion(&hpe->res_ready);
4826 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4827 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4828
4829 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4830 }
4831}
4832
4833static int mlx5e_tc_netdev_event(struct notifier_block *this,
4834 unsigned long event, void *ptr)
4835{
4836 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4837 struct mlx5e_flow_steering *fs;
4838 struct mlx5e_priv *peer_priv;
4839 struct mlx5e_tc_table *tc;
4840 struct mlx5e_priv *priv;
4841
4842 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4843 event != NETDEV_UNREGISTER ||
4844 ndev->reg_state == NETREG_REGISTERED)
4845 return NOTIFY_DONE;
4846
4847 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4848 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4849 priv = container_of(fs, struct mlx5e_priv, fs);
4850 peer_priv = netdev_priv(ndev);
4851 if (priv == peer_priv ||
4852 !(priv->netdev->features & NETIF_F_HW_TC))
4853 return NOTIFY_DONE;
4854
4855 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4856
4857 return NOTIFY_DONE;
4858}
4859
6a064674
AL		 4860static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4861{
4862 int tc_grp_size, tc_tbl_size;
4863 u32 max_flow_counter;
4864
4865 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4866 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4867
4868 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4869
4870 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4871 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4872
4873 return tc_tbl_size;
4874}
4875
655dc3d2 4876int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4877{
acff797c 4878 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4879 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4880 struct mapping_ctx *chains_mapping;
6a064674 4881 struct mlx5_chains_attr attr = {};
2198b932 4882 u64 mapping_id;
4d8fcf21 4883 int err;
e8f887ac 4884
b2fdf3d0 4885 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4886 mutex_init(&tc->t_lock);
b32accda 4887 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4888 hash_init(tc->hairpin_tbl);
11c9c548 4889
4d8fcf21
AH		 4890 err = rhashtable_init(&tc->ht, &tc_ht_params);
4891 if (err)
4892 return err;
4893
9ba33339
RD		 4894 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4895
2198b932
RD		 4896 mapping_id = mlx5_query_nic_system_image_guid(dev);
4897
4898 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4899 sizeof(struct mlx5_mapped_obj),
4900 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4901
c9355682
CM		 4902 if (IS_ERR(chains_mapping)) {
4903 err = PTR_ERR(chains_mapping);
4904 goto err_mapping;
4905 }
4906 tc->mapping = chains_mapping;
4907
4908 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4909 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4910 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4911 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4912 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4913 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4914 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4915 attr.mapping = chains_mapping;
6a064674
AL		 4916
4917 tc->chains = mlx5_chains_create(dev, &attr);
4918 if (IS_ERR(tc->chains)) {
4919 err = PTR_ERR(tc->chains);
4920 goto err_chains;
4921 }
4922
f0da4daa 4923 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4924 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4925 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4926
4d8fcf21 4927 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4928 err = register_netdevice_notifier_dev_net(priv->netdev,
4929 &tc->netdevice_nb,
4930 &tc->netdevice_nn);
4931 if (err) {
4d8fcf21
AH		 4932 tc->netdevice_nb.notifier_call = NULL;
4933 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4934 goto err_reg;
4d8fcf21
AH		 4935 }
4936
6a064674
AL		 4937 return 0;
4938
4939err_reg:
aedd133d 4940 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4941 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 4942 mlx5_chains_destroy(tc->chains);
4943err_chains:
c9355682
CM		 4944 mapping_destroy(chains_mapping);
4945err_mapping:
6a064674 4946 rhashtable_destroy(&tc->ht);
4d8fcf21 4947 return err;
e8f887ac
AV		 4948}
4949
4950static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4951{
4952 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4953 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4954
961e8979 4955 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4956 kfree(flow);
4957}
4958
655dc3d2 4959void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4960{
acff797c 4961 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4962
4d8fcf21 4963 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4964 unregister_netdevice_notifier_dev_net(priv->netdev,
4965 &tc->netdevice_nb,
4966 &tc->netdevice_nn);
4d8fcf21 4967
b2fdf3d0 4968 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4969 mutex_destroy(&tc->hairpin_tbl_lock);
4970
6a064674 4971 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4972
acff797c 4973 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4974 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4975 tc->t = NULL;
e8f887ac 4976 }
b6fac0b4 4977 mutex_destroy(&tc->t_lock);
6a064674 4978
aedd133d 4979 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4980 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 4981 mapping_destroy(tc->mapping);
6a064674 4982 mlx5_chains_destroy(tc->chains);
e8f887ac 4983}
655dc3d2
OG		 4984
4985int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4986{
d7a42ad0 4987 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4988 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4989 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4990 struct mapping_ctx *mapping;
aedd133d
AL		 4991 struct mlx5_eswitch *esw;
4992 struct mlx5e_priv *priv;
2198b932 4993 u64 mapping_id;
aedd133d 4994 int err = 0;
0a7fcb78
PB		 4995
4996 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4997 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4998 priv = netdev_priv(rpriv->netdev);
4999 esw = priv->mdev->priv.eswitch;
0a7fcb78 5000
f0da4daa
CM		 5001 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5002 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 5003 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5004 esw_chains(esw),
5005 &esw->offloads.mod_hdr,
f0da4daa
CM		 5006 MLX5_FLOW_NAMESPACE_FDB,
5007 uplink_priv->post_act);
4c3844d9 5008
2a9ab10a 5009#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
2741f223 5010 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a
CM		 5011#endif
5012
2198b932
RD		 5013 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5014
5015 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5016 sizeof(struct tunnel_match_key),
5017 TUNNEL_INFO_BITS_MASK, true);
5018
0a7fcb78
PB		 5019 if (IS_ERR(mapping)) {
5020 err = PTR_ERR(mapping);
5021 goto err_tun_mapping;
5022 }
5023 uplink_priv->tunnel_mapping = mapping;
5024
8e404fef 5025 /* 0xFFF is reserved for stack devices slow path table mark */
2198b932
RD		 5026 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5027 sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 5028 if (IS_ERR(mapping)) {
5029 err = PTR_ERR(mapping);
5030 goto err_enc_opts_mapping;
5031 }
5032 uplink_priv->tunnel_enc_opts_mapping = mapping;
5033
5034 err = rhashtable_init(tc_ht, &tc_ht_params);
5035 if (err)
5036 goto err_ht_init;
5037
9ba33339
RD		 5038 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5039
8914add2 5040 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 5041 if (IS_ERR(uplink_priv->encap)) {
5042 err = PTR_ERR(uplink_priv->encap);
8914add2 5043 goto err_register_fib_notifier;
2b6c3c1e 5044 }
8914add2 5045
2b6c3c1e 5046 return 0;
0a7fcb78 5047
8914add2
VB		 5048err_register_fib_notifier:
5049 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5050err_ht_init:
5051 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5052err_enc_opts_mapping:
5053 mapping_destroy(uplink_priv->tunnel_mapping);
5054err_tun_mapping:
2a9ab10a 5055#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
0027d70c 5056 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
2a9ab10a 5057#endif
aedd133d 5058 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5059 netdev_warn(priv->netdev,
5060 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 5061 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 5062 return err;
655dc3d2
OG		 5063}
5064
5065void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5066{
0a7fcb78
PB		 5067 struct mlx5_rep_uplink_priv *uplink_priv;
5068
0a7fcb78 5069 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5070
8914add2
VB		 5071 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5072 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5073
0a7fcb78
PB		 5074 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5075 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5076
2a9ab10a 5077#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
0027d70c 5078 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
2a9ab10a 5079#endif
aedd133d 5080 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 5081 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 5082}
01252a27 5083
226f2ca3 5084int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5085{
d9ee0491 5086 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5087
5088 return atomic_read(&tc_ht->nelems);
5089}
04de7dda
RD		 5090
5091void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5092{
5093 struct mlx5e_tc_flow *flow, *tmp;
5094
5095 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5096 __mlx5e_tc_del_fdb_peer_flow(flow);
5097}
b4a23329
RD		 5098
5099void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5100{
5101 struct mlx5_rep_uplink_priv *rpriv =
5102 container_of(work, struct mlx5_rep_uplink_priv,
5103 reoffload_flows_work);
5104 struct mlx5e_tc_flow *flow, *tmp;
5105
ad86755b 5106 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5107 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5108 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5109 unready_flow_del(flow);
b4a23329 5110 }
ad86755b 5111 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5112}
e2394a61
VB		 5113
5114static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5115 struct flow_cls_offload *cls_flower,
5116 unsigned long flags)
5117{
5118 switch (cls_flower->command) {
5119 case FLOW_CLS_REPLACE:
5120 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5121 flags);
5122 case FLOW_CLS_DESTROY:
5123 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5124 flags);
5125 case FLOW_CLS_STATS:
5126 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5127 flags);
5128 default:
5129 return -EOPNOTSUPP;
5130 }
5131}
5132
5133int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5134 void *cb_priv)
5135{
ec9457a6 5136 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5137 struct mlx5e_priv *priv = cb_priv;
5138
2ff349c5
RD		 5139 if (!priv->netdev || !netif_device_present(priv->netdev))
5140 return -EOPNOTSUPP;
5141
ec9457a6
RD		 5142 if (mlx5e_is_uplink_rep(priv))
5143 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5144 else
5145 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5146
e2394a61
VB		 5147 switch (type) {
5148 case TC_SETUP_CLSFLOWER:
5149 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5150 default:
5151 return -EOPNOTSUPP;
5152 }
5153}
c7569097
AL		 5154
5155bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5156 struct sk_buff *skb)
5157{
5158#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5159 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5160 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5161 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5162 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5163 struct tc_skb_ext *tc_skb_ext;
5164 int err;
5165
5166 reg_b = be32_to_cpu(cqe->ft_metadata);
5167
5168 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5169
c9355682 5170 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5171 if (err) {
5172 netdev_dbg(priv->netdev,
5173 "Couldn't find chain for chain tag: %d, err: %d\n",
5174 chain_tag, err);
5175 return false;
5176 }
5177
a91d98a0
CM		 5178 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5179 chain = mapped_obj.chain;
9453d45e 5180 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5181 if (WARN_ON(!tc_skb_ext))
5182 return false;
5183
5184 tc_skb_ext->chain = chain;
aedd133d 5185
ed2fe7ba 5186 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5187 ESW_ZONE_ID_MASK;
aedd133d
AL		 5188
5189 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5190 zone_restore_id))
5191 return false;
a91d98a0
CM		 5192 } else {
5193 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5194 return false;
c7569097
AL		 5195 }
5196#endif /* CONFIG_NET_TC_SKB_EXT */
5197
5198 return true;
5199}
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