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net/mlx5: E-Switch, rebuild lag only when needed
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
d79b6df6 42#include <net/tc_act/tc_pedit.h>
26c02749 43#include <net/tc_act/tc_csum.h>
41c2fd94 44#include <net/psample.h>
f6dfb4c3 45#include <net/arp.h>
3616d08b 46#include <net/ipv6_stubs.h>
f828ca6a 47#include <net/bareudp.h>
d34eb2fc 48#include <net/bonding.h>
e8f887ac 49#include "en.h"
f0da4daa 50#include "en/tc/post_act.h"
1d447a39 51#include "en_rep.h"
768c3667 52#include "en/rep/tc.h"
e2394a61 53#include "en/rep/neigh.h"
232c0013 54#include "en_tc.h"
03a9d11e 55#include "eswitch.h"
3f6d08d1 56#include "fs_core.h"
2c81bfd5 57#include "en/port.h"
101f4de9 58#include "en/tc_tun.h"
0a7fcb78 59#include "en/mapping.h"
4c3844d9 60#include "en/tc_ct.h"
b2fdf3d0 61#include "en/mod_hdr.h"
0d9f9647
VB		 62#include "en/tc_priv.h"
63#include "en/tc_tun_encap.h"
0027d70c 64#include "en/tc/sample.h"
04de7dda 65#include "lib/devcom.h"
9272e3df 66#include "lib/geneve.h"
ae430332 67#include "lib/fs_chains.h"
7a978759 68#include "diag/en_tc_tracepoint.h"
1fe3e316 69#include <asm/div64.h>
14fe2471
MD		 70#include "lag.h"
71#include "lag_mp.h"
e8f887ac 72
6a064674 73#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 74#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 75
acff797c 76#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 77#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 78
8f1e0b97
PB		 79struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
80 [CHAIN_TO_REG] = {
81 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
82 .moffset = 0,
ed2fe7ba 83 .mlen = 16,
8f1e0b97 84 },
10742efc
VB		 85 [VPORT_TO_REG] = {
86 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 87 .moffset = 16,
88 .mlen = 16,
10742efc 89 },
0a7fcb78
PB		 90 [TUNNEL_TO_REG] = {
91 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 92 .moffset = 8,
93 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 94 .soffset = MLX5_BYTE_OFF(fte_match_param,
95 misc_parameters_2.metadata_reg_c_1),
96 },
4c3844d9 97 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 98 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 99 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
100 [MARK_TO_REG] = mark_to_reg_ct,
101 [LABELS_TO_REG] = labels_to_reg_ct,
102 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 103 /* For NIC rules we store the restore metadata directly
c7569097
AL		 104 * into reg_b that is passed to SW since we don't
105 * jump between steering domains.
106 */
107 [NIC_CHAIN_TO_REG] = {
108 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
109 .moffset = 0,
ed2fe7ba 110 .mlen = 16,
c7569097 111 },
aedd133d 112 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 113};
114
9ba33339
RD		 115/* To avoid false lock dependency warning set the tc_ht lock
116 * class different than the lock class of the ht being used when deleting
117 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
118 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
119 * it's different than the ht->mutex here.
120 */
121static struct lock_class_key tc_ht_lock_key;
122
0a7fcb78
PB		 123static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
124
125void
126mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
127 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 128 u32 val,
0a7fcb78
PB		 129 u32 mask)
130{
ed2fe7ba 131 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 132 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 133 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 134 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 135 u32 max_mask = GENMASK(match_len - 1, 0);
136 __be32 curr_mask_be, curr_val_be;
137 u32 curr_mask, curr_val;
0a7fcb78
PB		 138
139 fmask = headers_c + soffset;
140 fval = headers_v + soffset;
141
ed2fe7ba
PB		 142 memcpy(&curr_mask_be, fmask, 4);
143 memcpy(&curr_val_be, fval, 4);
144
145 curr_mask = be32_to_cpu(curr_mask_be);
146 curr_val = be32_to_cpu(curr_val_be);
147
148 //move to correct offset
149 WARN_ON(mask > max_mask);
150 mask <<= moffset;
151 val <<= moffset;
152 max_mask <<= moffset;
153
154 //zero val and mask
155 curr_mask &= ~max_mask;
156 curr_val &= ~max_mask;
0a7fcb78 157
ed2fe7ba
PB		 158 //add current to mask
159 curr_mask |= mask;
160 curr_val |= val;
161
162 //back to be32 and write
163 curr_mask_be = cpu_to_be32(curr_mask);
164 curr_val_be = cpu_to_be32(curr_val);
165
166 memcpy(fmask, &curr_mask_be, 4);
167 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 168
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
170}
171
7e36feeb
PB		 172void
173mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
174 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 175 u32 *val,
7e36feeb
PB		 176 u32 *mask)
177{
ed2fe7ba 178 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 179 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 180 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 181 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 182 u32 max_mask = GENMASK(match_len - 1, 0);
183 __be32 curr_mask_be, curr_val_be;
184 u32 curr_mask, curr_val;
7e36feeb
PB		 185
186 fmask = headers_c + soffset;
187 fval = headers_v + soffset;
188
ed2fe7ba
PB		 189 memcpy(&curr_mask_be, fmask, 4);
190 memcpy(&curr_val_be, fval, 4);
191
192 curr_mask = be32_to_cpu(curr_mask_be);
193 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 194
ed2fe7ba
PB		 195 *mask = (curr_mask >> moffset) & max_mask;
196 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 197}
198
0a7fcb78 199int
c7b9038d
VB		 200mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
201 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
202 enum mlx5_flow_namespace_type ns,
203 enum mlx5e_tc_attr_to_reg type,
204 u32 data)
0a7fcb78
PB		 205{
206 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
207 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
208 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
209 char *modact;
210 int err;
211
aedd133d 212 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 213 if (err)
214 return err;
215
216 modact = mod_hdr_acts->actions +
217 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
218
219 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 220 if (mlen == 32)
0a7fcb78
PB		 221 mlen = 0;
222
223 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
224 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 225 MLX5_SET(set_action_in, modact, offset, moffset);
226 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 227 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 228 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 229 mod_hdr_acts->num_actions++;
230
c7b9038d 231 return err;
0a7fcb78
PB		 232}
233
aedd133d
AL		 234static struct mlx5_tc_ct_priv *
235get_ct_priv(struct mlx5e_priv *priv)
236{
237 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
238 struct mlx5_rep_uplink_priv *uplink_priv;
239 struct mlx5e_rep_priv *uplink_rpriv;
240
e8711402 241 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 242 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
243 uplink_priv = &uplink_rpriv->uplink_priv;
244
245 return uplink_priv->ct_priv;
246 }
247
248 return priv->fs.tc.ct;
249}
250
f94d6389 251#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
0027d70c 252static struct mlx5e_tc_psample *
f94d6389
CM		 253get_sample_priv(struct mlx5e_priv *priv)
254{
255 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
256 struct mlx5_rep_uplink_priv *uplink_priv;
257 struct mlx5e_rep_priv *uplink_rpriv;
258
259 if (is_mdev_switchdev_mode(priv->mdev)) {
260 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
261 uplink_priv = &uplink_rpriv->uplink_priv;
262
0027d70c 263 return uplink_priv->tc_psample;
f94d6389
CM		 264 }
265
266 return NULL;
267}
268#endif
269
aedd133d
AL		 270struct mlx5_flow_handle *
271mlx5_tc_rule_insert(struct mlx5e_priv *priv,
272 struct mlx5_flow_spec *spec,
273 struct mlx5_flow_attr *attr)
274{
275 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
276
e8711402 277 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 278 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
279
280 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
281}
282
283void
284mlx5_tc_rule_delete(struct mlx5e_priv *priv,
285 struct mlx5_flow_handle *rule,
286 struct mlx5_flow_attr *attr)
287{
288 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
289
e8711402 290 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 291 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
292
293 return;
294 }
295
296 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
297}
298
c7b9038d
VB		 299int
300mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
301 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
302 enum mlx5_flow_namespace_type ns,
303 enum mlx5e_tc_attr_to_reg type,
304 u32 data)
305{
306 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
307
308 return ret < 0 ? ret : 0;
309}
310
311void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
312 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
313 enum mlx5e_tc_attr_to_reg type,
314 int act_id, u32 data)
315{
316 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
317 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
318 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
319 char *modact;
320
321 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
322
323 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 324 if (mlen == 32)
c7b9038d
VB		 325 mlen = 0;
326
327 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
328 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 329 MLX5_SET(set_action_in, modact, offset, moffset);
330 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 331 MLX5_SET(set_action_in, modact, data, data);
332}
333
77ab67b7
OG		 334struct mlx5e_hairpin {
335 struct mlx5_hairpin *pair;
336
337 struct mlx5_core_dev *func_mdev;
3f6d08d1 338 struct mlx5e_priv *func_priv;
77ab67b7 339 u32 tdn;
a6696735 340 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 341
342 int num_channels;
343 struct mlx5e_rqt indir_rqt;
a6696735 344 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 345 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 346};
347
5c65c564
OG		 348struct mlx5e_hairpin_entry {
349 /* a node of a hash table which keeps all the hairpin entries */
350 struct hlist_node hairpin_hlist;
351
73edca73
VB		 352 /* protects flows list */
353 spinlock_t flows_lock;
5c65c564
OG		 354 /* flows sharing the same hairpin */
355 struct list_head flows;
db76ca24
VB		 356 /* hpe's that were not fully initialized when dead peer update event
357 * function traversed them.
358 */
359 struct list_head dead_peer_wait_list;
5c65c564 360
d8822868 361 u16 peer_vhca_id;
106be53b 362 u8 prio;
5c65c564 363 struct mlx5e_hairpin *hp;
e4f9abbd 364 refcount_t refcnt;
db76ca24 365 struct completion res_ready;
5c65c564
OG		 366};
367
5a7e5bcb
VB		 368static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
369 struct mlx5e_tc_flow *flow);
370
0d9f9647 371struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 372{
373 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
374 return ERR_PTR(-EINVAL);
375 return flow;
376}
377
0d9f9647 378void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 379{
380 if (refcount_dec_and_test(&flow->refcnt)) {
381 mlx5e_tc_del_flow(priv, flow);
c5d326b2 382 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 383 }
384}
385
aedd133d 386bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 387{
388 return flow_flag_test(flow, ESWITCH);
389}
390
84179981
PB		 391static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
392{
393 return flow_flag_test(flow, FT);
394}
395
0d9f9647 396bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 397{
398 return flow_flag_test(flow, OFFLOADED);
399}
400
b2fdf3d0 401static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 402{
b2fdf3d0
PB		 403 return mlx5e_is_eswitch_flow(flow) ?
404 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 405}
406
dd58edc3 407static struct mod_hdr_tbl *
b2fdf3d0 408get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 409{
410 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
411
b2fdf3d0
PB		 412 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
413 &esw->offloads.mod_hdr :
dd58edc3
VB		 414 &priv->fs.tc.mod_hdr;
415}
416
11c9c548
OG		 417static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
418 struct mlx5e_tc_flow *flow,
419 struct mlx5e_tc_flow_parse_attr *parse_attr)
420{
b2fdf3d0
PB		 421 struct mlx5_modify_hdr *modify_hdr;
422 struct mlx5e_mod_hdr_handle *mh;
11c9c548 423
b2fdf3d0
PB		 424 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
425 get_flow_name_space(flow),
426 &parse_attr->mod_hdr_acts);
427 if (IS_ERR(mh))
428 return PTR_ERR(mh);
11c9c548 429
b2fdf3d0 430 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 431 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 432 flow->mh = mh;
11c9c548
OG		 433
434 return 0;
11c9c548
OG		 435}
436
437static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
438 struct mlx5e_tc_flow *flow)
439{
5a7e5bcb 440 /* flow wasn't fully initialized */
dd58edc3 441 if (!flow->mh)
5a7e5bcb
VB		 442 return;
443
b2fdf3d0
PB		 444 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
445 flow->mh);
dd58edc3 446 flow->mh = NULL;
11c9c548
OG		 447}
448
77ab67b7
OG		 449static
450struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
451{
b1c2f631 452 struct mlx5_core_dev *mdev;
77ab67b7
OG		 453 struct net_device *netdev;
454 struct mlx5e_priv *priv;
455
b1c2f631
DC		 456 netdev = dev_get_by_index(net, ifindex);
457 if (!netdev)
458 return ERR_PTR(-ENODEV);
459
77ab67b7 460 priv = netdev_priv(netdev);
b1c2f631
DC		 461 mdev = priv->mdev;
462 dev_put(netdev);
463
464 /* Mirred tc action holds a refcount on the ifindex net_device (see
465 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
466 * after dev_put(netdev), while we're in the context of adding a tc flow.
467 *
468 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
469 * stored in a hairpin object, which exists until all flows, that refer to it, get
470 * removed.
471 *
472 * On the other hand, after a hairpin object has been created, the peer net_device may
473 * be removed/unbound while there are still some hairpin flows that are using it. This
474 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
475 * NETDEV_UNREGISTER event of the peer net_device.
476 */
477 return mdev;
77ab67b7
OG		 478}
479
480static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
481{
a6696735 482 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 483 int err;
484
a6696735
MM		 485 builder = mlx5e_tir_builder_alloc(false);
486 if (!builder)
487 return -ENOMEM;
488
77ab67b7
OG		 489 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
490 if (err)
a6696735 491 goto out;
77ab67b7 492
a6696735
MM		 493 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
494 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 495 if (err)
496 goto create_tir_err;
497
a6696735
MM		 498out:
499 mlx5e_tir_builder_free(builder);
500 return err;
77ab67b7
OG		 501
502create_tir_err:
503 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 504
505 goto out;
77ab67b7
OG		 506}
507
508static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
509{
a6696735 510 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 511 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
512}
513
3f6d08d1
OG		 514static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
515{
3f6d08d1
OG		 516 struct mlx5e_priv *priv = hp->func_priv;
517 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 518 struct mlx5e_rss_params_indir *indir;
519 int err;
3f6d08d1 520
06e9f13a
MM		 521 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
522 if (!indir)
3f6d08d1
OG		 523 return -ENOMEM;
524
43befe99 525 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 526 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 527 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
528 indir);
3f6d08d1 529
06e9f13a 530 kvfree(indir);
3f6d08d1
OG		 531 return err;
532}
533
534static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
535{
536 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 537 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 538 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 539 struct mlx5e_tir_builder *builder;
540 int err = 0;
541
542 builder = mlx5e_tir_builder_alloc(false);
543 if (!builder)
544 return -ENOMEM;
545
43ec0f41 546 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 547
548 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 549 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 550
65d6b6e5 551 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 552
a6696735
MM		 553 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
554 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
555 false);
43ec0f41 556 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 557
a6696735 558 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 559 if (err) {
560 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
561 goto err_destroy_tirs;
562 }
a6696735
MM		 563
564 mlx5e_tir_builder_clear(builder);
3f6d08d1 565 }
3f6d08d1 566
a6696735
MM		 567out:
568 mlx5e_tir_builder_free(builder);
3f6d08d1 569 return err;
a6696735
MM		 570
571err_destroy_tirs:
572 max_tt = tt;
573 for (tt = 0; tt < max_tt; tt++)
574 mlx5e_tir_destroy(&hp->indir_tir[tt]);
575
576 goto out;
3f6d08d1
OG		 577}
578
579static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
580{
581 int tt;
582
583 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 584 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 585}
586
587static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
588 struct ttc_params *ttc_params)
589{
590 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
591 int tt;
592
593 memset(ttc_params, 0, sizeof(*ttc_params));
594
bc29764e
MG		 595 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
596 MLX5_FLOW_NAMESPACE_KERNEL);
597 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
598 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
599 ttc_params->dests[tt].tir_num =
600 tt == MLX5_TT_ANY ?
601 mlx5e_tir_get_tirn(&hp->direct_tir) :
602 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
603 }
3f6d08d1 604
3f6d08d1
OG		 605 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
606 ft_attr->prio = MLX5E_TC_PRIO;
607}
608
609static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
610{
611 struct mlx5e_priv *priv = hp->func_priv;
612 struct ttc_params ttc_params;
613 int err;
614
615 err = mlx5e_hairpin_create_indirect_rqt(hp);
616 if (err)
617 return err;
618
619 err = mlx5e_hairpin_create_indirect_tirs(hp);
620 if (err)
621 goto err_create_indirect_tirs;
622
623 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 624 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
625 if (IS_ERR(hp->ttc)) {
626 err = PTR_ERR(hp->ttc);
3f6d08d1 627 goto err_create_ttc_table;
f4b45940 628 }
3f6d08d1
OG		 629
630 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 631 hp->num_channels,
632 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 633
634 return 0;
635
636err_create_ttc_table:
637 mlx5e_hairpin_destroy_indirect_tirs(hp);
638err_create_indirect_tirs:
06e9f13a 639 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 640
641 return err;
642}
643
644static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
645{
f4b45940 646 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 647 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 648 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 649}
650
77ab67b7
OG		 651static struct mlx5e_hairpin *
652mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
653 int peer_ifindex)
654{
655 struct mlx5_core_dev *func_mdev, *peer_mdev;
656 struct mlx5e_hairpin *hp;
657 struct mlx5_hairpin *pair;
658 int err;
659
660 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
661 if (!hp)
662 return ERR_PTR(-ENOMEM);
663
664 func_mdev = priv->mdev;
665 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 666 if (IS_ERR(peer_mdev)) {
667 err = PTR_ERR(peer_mdev);
668 goto create_pair_err;
669 }
77ab67b7
OG		 670
671 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
672 if (IS_ERR(pair)) {
673 err = PTR_ERR(pair);
674 goto create_pair_err;
675 }
676 hp->pair = pair;
677 hp->func_mdev = func_mdev;
3f6d08d1
OG		 678 hp->func_priv = priv;
679 hp->num_channels = params->num_channels;
77ab67b7
OG		 680
681 err = mlx5e_hairpin_create_transport(hp);
682 if (err)
683 goto create_transport_err;
684
3f6d08d1
OG		 685 if (hp->num_channels > 1) {
686 err = mlx5e_hairpin_rss_init(hp);
687 if (err)
688 goto rss_init_err;
689 }
690
77ab67b7
OG		 691 return hp;
692
3f6d08d1
OG		 693rss_init_err:
694 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 695create_transport_err:
696 mlx5_core_hairpin_destroy(hp->pair);
697create_pair_err:
698 kfree(hp);
699 return ERR_PTR(err);
700}
701
702static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
703{
3f6d08d1
OG		 704 if (hp->num_channels > 1)
705 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 706 mlx5e_hairpin_destroy_transport(hp);
707 mlx5_core_hairpin_destroy(hp->pair);
708 kvfree(hp);
709}
710
106be53b
OG		 711static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
712{
713 return (peer_vhca_id << 16 | prio);
714}
715
5c65c564 716static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 717 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 718{
719 struct mlx5e_hairpin_entry *hpe;
106be53b 720 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 721
722 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 723 hairpin_hlist, hash_key) {
e4f9abbd
VB		 724 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
725 refcount_inc(&hpe->refcnt);
5c65c564 726 return hpe;
e4f9abbd 727 }
5c65c564
OG		 728 }
729
730 return NULL;
731}
732
e4f9abbd
VB		 733static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
734 struct mlx5e_hairpin_entry *hpe)
735{
736 /* no more hairpin flows for us, release the hairpin pair */
b32accda 737 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 738 return;
b32accda
VB		 739 hash_del(&hpe->hairpin_hlist);
740 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 741
db76ca24
VB		 742 if (!IS_ERR_OR_NULL(hpe->hp)) {
743 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
744 dev_name(hpe->hp->pair->peer_mdev->device));
745
746 mlx5e_hairpin_destroy(hpe->hp);
747 }
e4f9abbd
VB		 748
749 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 750 kfree(hpe);
751}
752
106be53b
OG		 753#define UNKNOWN_MATCH_PRIO 8
754
755static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 756 struct mlx5_flow_spec *spec, u8 *match_prio,
757 struct netlink_ext_ack *extack)
106be53b
OG		 758{
759 void *headers_c, *headers_v;
760 u8 prio_val, prio_mask = 0;
761 bool vlan_present;
762
763#ifdef CONFIG_MLX5_CORE_EN_DCB
764 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 765 NL_SET_ERR_MSG_MOD(extack,
766 "only PCP trust state supported for hairpin");
106be53b
OG		 767 return -EOPNOTSUPP;
768 }
769#endif
770 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
771 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
772
773 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
774 if (vlan_present) {
775 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
776 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
777 }
778
779 if (!vlan_present || !prio_mask) {
780 prio_val = UNKNOWN_MATCH_PRIO;
781 } else if (prio_mask != 0x7) {
e98bedf5
EB		 782 NL_SET_ERR_MSG_MOD(extack,
783 "masked priority match not supported for hairpin");
106be53b
OG		 784 return -EOPNOTSUPP;
785 }
786
787 *match_prio = prio_val;
788 return 0;
789}
790
5c65c564
OG		 791static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
792 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 793 struct mlx5e_tc_flow_parse_attr *parse_attr,
794 struct netlink_ext_ack *extack)
5c65c564 795{
98b66cb1 796 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 797 struct mlx5_hairpin_params params;
d8822868 798 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 799 struct mlx5e_hairpin_entry *hpe;
800 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 801 u64 link_speed64;
802 u32 link_speed;
106be53b 803 u8 match_prio;
d8822868 804 u16 peer_id;
5c65c564
OG		 805 int err;
806
d8822868 807 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 808 if (IS_ERR(peer_mdev)) {
809 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
810 return PTR_ERR(peer_mdev);
811 }
812
d8822868 813 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 814 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 815 return -EOPNOTSUPP;
816 }
817
d8822868 818 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 819 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
820 extack);
106be53b
OG		 821 if (err)
822 return err;
b32accda
VB		 823
824 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 825 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 826 if (hpe) {
827 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
828 wait_for_completion(&hpe->res_ready);
829
830 if (IS_ERR(hpe->hp)) {
831 err = -EREMOTEIO;
832 goto out_err;
833 }
5c65c564 834 goto attach_flow;
db76ca24 835 }
5c65c564
OG		 836
837 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 838 if (!hpe) {
db76ca24
VB		 839 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
840 return -ENOMEM;
b32accda 841 }
5c65c564 842
73edca73 843 spin_lock_init(&hpe->flows_lock);
5c65c564 844 INIT_LIST_HEAD(&hpe->flows);
db76ca24 845 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 846 hpe->peer_vhca_id = peer_id;
106be53b 847 hpe->prio = match_prio;
e4f9abbd 848 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 849 init_completion(&hpe->res_ready);
850
851 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
852 hash_hairpin_info(peer_id, match_prio));
853 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 854
6cdc686a 855 params.log_data_size = 16;
5c65c564
OG		 856 params.log_data_size = min_t(u8, params.log_data_size,
857 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
858 params.log_data_size = max_t(u8, params.log_data_size,
859 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 860
eb9180f7
OG		 861 params.log_num_packets = params.log_data_size -
862 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
863 params.log_num_packets = min_t(u8, params.log_num_packets,
864 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
865
866 params.q_counter = priv->q_counter;
3f6d08d1 867 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 868 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 869 link_speed = max_t(u32, link_speed, 50000);
870 link_speed64 = link_speed;
871 do_div(link_speed64, 50000);
872 params.num_channels = link_speed64;
873
5c65c564 874 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 875 hpe->hp = hp;
876 complete_all(&hpe->res_ready);
5c65c564
OG		 877 if (IS_ERR(hp)) {
878 err = PTR_ERR(hp);
db76ca24 879 goto out_err;
5c65c564
OG		 880 }
881
eb9180f7 882 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 883 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 884 dev_name(hp->pair->peer_mdev->device),
eb9180f7 885 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 886
5c65c564 887attach_flow:
3f6d08d1 888 if (hpe->hp->num_channels > 1) {
226f2ca3 889 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 890 flow->attr->nic_attr->hairpin_ft =
891 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 892 } else {
a6696735 893 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 894 }
b32accda 895
e4f9abbd 896 flow->hpe = hpe;
73edca73 897 spin_lock(&hpe->flows_lock);
5c65c564 898 list_add(&flow->hairpin, &hpe->flows);
73edca73 899 spin_unlock(&hpe->flows_lock);
3f6d08d1 900
5c65c564
OG		 901 return 0;
902
db76ca24
VB		 903out_err:
904 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 905 return err;
906}
907
908static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
909 struct mlx5e_tc_flow *flow)
910{
5a7e5bcb 911 /* flow wasn't fully initialized */
e4f9abbd 912 if (!flow->hpe)
5a7e5bcb
VB		 913 return;
914
73edca73 915 spin_lock(&flow->hpe->flows_lock);
5c65c564 916 list_del(&flow->hairpin);
73edca73
VB		 917 spin_unlock(&flow->hpe->flows_lock);
918
e4f9abbd
VB		 919 mlx5e_hairpin_put(priv, flow->hpe);
920 flow->hpe = NULL;
5c65c564
OG		 921}
922
08247066
AL		 923struct mlx5_flow_handle *
924mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
925 struct mlx5_flow_spec *spec,
c620b772 926 struct mlx5_flow_attr *attr)
e8f887ac 927{
08247066 928 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 929 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 930 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 931 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 932 struct mlx5_flow_destination dest[2] = {};
66958ed9 933 struct mlx5_flow_act flow_act = {
3bc4b7bf 934 .action = attr->action,
bb0ee7dc 935 .flags = FLOW_ACT_NO_APPEND,
66958ed9 936 };
08247066 937 struct mlx5_flow_handle *rule;
c7569097 938 struct mlx5_flow_table *ft;
08247066 939 int dest_ix = 0;
e8f887ac 940
bb0ee7dc 941 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 942 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 943
aedd133d
AL		 944 if (attr->dest_ft) {
945 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
946 dest[dest_ix].ft = attr->dest_ft;
947 dest_ix++;
948 } else if (nic_attr->hairpin_ft) {
08247066 949 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 950 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 951 dest_ix++;
c620b772 952 } else if (nic_attr->hairpin_tirn) {
08247066 953 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 954 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 955 dest_ix++;
3f6d08d1
OG		 956 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
957 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 958 if (attr->dest_chain) {
959 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
960 attr->dest_chain, 1,
961 MLX5E_TC_FT_LEVEL);
962 if (IS_ERR(dest[dest_ix].ft))
963 return ERR_CAST(dest[dest_ix].ft);
964 } else {
6783f0a2 965 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 966 }
3f6d08d1 967 dest_ix++;
5c65c564 968 }
aad7e08d 969
c7569097
AL		 970 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
971 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
972 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
973
08247066 974 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 975 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 976 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 977 dest_ix++;
aad7e08d
AV		 978 }
979
08247066 980 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 981 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 982
6a064674
AL		 983 mutex_lock(&tc->t_lock);
984 if (IS_ERR_OR_NULL(tc->t)) {
985 /* Create the root table here if doesn't exist yet */
986 tc->t =
c7569097 987 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 988
989 if (IS_ERR(tc->t)) {
990 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 991 netdev_err(priv->netdev,
992 "Failed to create tc offload table\n");
c7569097
AL		 993 rule = ERR_CAST(priv->fs.tc.t);
994 goto err_ft_get;
e8f887ac 995 }
e8f887ac 996 }
08247066 997 mutex_unlock(&tc->t_lock);
e8f887ac 998
aedd133d
AL		 999 if (attr->chain || attr->prio)
1000 ft = mlx5_chains_get_table(nic_chains,
1001 attr->chain, attr->prio,
1002 MLX5E_TC_FT_LEVEL);
1003 else
1004 ft = attr->ft;
1005
c7569097
AL		 1006 if (IS_ERR(ft)) {
1007 rule = ERR_CAST(ft);
1008 goto err_ft_get;
1009 }
1010
c620b772 1011 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1012 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1013
c7569097 1014 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1015 &flow_act, dest, dest_ix);
1016 if (IS_ERR(rule))
c7569097 1017 goto err_rule;
08247066
AL		 1018
1019 return rule;
c7569097
AL		 1020
1021err_rule:
aedd133d
AL		 1022 if (attr->chain || attr->prio)
1023 mlx5_chains_put_table(nic_chains,
1024 attr->chain, attr->prio,
1025 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1026err_ft_get:
1027 if (attr->dest_chain)
1028 mlx5_chains_put_table(nic_chains,
1029 attr->dest_chain, 1,
1030 MLX5E_TC_FT_LEVEL);
1031
1032 return ERR_CAST(rule);
08247066
AL		 1033}
1034
1035static int
1036mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1037 struct mlx5e_tc_flow *flow,
1038 struct netlink_ext_ack *extack)
1039{
c6cfe113 1040 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1041 struct mlx5_flow_attr *attr = flow->attr;
08247066 1042 struct mlx5_core_dev *dev = priv->mdev;
97a8d29a 1043 struct mlx5_fc *counter;
08247066
AL		 1044 int err;
1045
c6cfe113
RD		 1046 parse_attr = attr->parse_attr;
1047
08247066
AL		 1048 if (flow_flag_test(flow, HAIRPIN)) {
1049 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1050 if (err)
1051 return err;
1052 }
1053
1054 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1055 counter = mlx5_fc_create(dev, true);
1056 if (IS_ERR(counter))
1057 return PTR_ERR(counter);
1058
1059 attr->counter = counter;
1060 }
1061
1062 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1063 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1064 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1065 if (err)
1066 return err;
1067 }
1068
aedd133d
AL		 1069 if (flow_flag_test(flow, CT))
1070 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1071 attr, &parse_attr->mod_hdr_acts);
1072 else
1073 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1074 attr);
aad7e08d 1075
a2b7189b 1076 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1077}
1078
08247066 1079void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1080 struct mlx5_flow_handle *rule,
1081 struct mlx5_flow_attr *attr)
08247066 1082{
c7569097
AL		 1083 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1084
08247066 1085 mlx5_del_flow_rules(rule);
c7569097 1086
aedd133d
AL		 1087 if (attr->chain || attr->prio)
1088 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1089 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1090
1091 if (attr->dest_chain)
1092 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1093 MLX5E_TC_FT_LEVEL);
08247066
AL		 1094}
1095
d85cdccb
OG		 1096static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1097 struct mlx5e_tc_flow *flow)
1098{
c620b772 1099 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1100 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1101
c7569097
AL		 1102 flow_flag_clear(flow, OFFLOADED);
1103
aedd133d
AL		 1104 if (flow_flag_test(flow, CT))
1105 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1106 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1107 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1108
c7569097
AL		 1109 /* Remove root table if no rules are left to avoid
1110 * extra steering hops.
1111 */
b6fac0b4 1112 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1113 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1114 !IS_ERR_OR_NULL(tc->t)) {
1115 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1116 priv->fs.tc.t = NULL;
1117 }
b6fac0b4 1118 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1119
aedd133d
AL		 1120 kvfree(attr->parse_attr);
1121
513f8f7f 1122 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1123 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1124
aedd133d
AL		 1125 mlx5_fc_destroy(priv->mdev, attr->counter);
1126
226f2ca3 1127 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1128 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1129
1130 kfree(flow->attr);
d85cdccb
OG		 1131}
1132
0d9f9647 1133struct mlx5_flow_handle *
6d2a3ed0
OG		 1134mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1135 struct mlx5e_tc_flow *flow,
1136 struct mlx5_flow_spec *spec,
c620b772 1137 struct mlx5_flow_attr *attr)
6d2a3ed0 1138{
1ef3018f 1139 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1140 struct mlx5_flow_handle *rule;
4c3844d9 1141
89e39467
PB		 1142 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1143 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1144
1ef3018f
PB		 1145 if (flow_flag_test(flow, CT)) {
1146 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1147
69e2916e 1148 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1149 flow, spec, attr,
1ef3018f 1150 mod_hdr_acts);
f94d6389
CM		 1151#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1152 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1153 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1154 mlx5e_tc_get_flow_tun_id(flow));
f94d6389 1155#endif
69e2916e
PB		 1156 } else {
1157 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1158 }
6d2a3ed0 1159
6d2a3ed0
OG		 1160 if (IS_ERR(rule))
1161 return rule;
1162
c620b772 1163 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1164 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1165 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1166 if (flow_flag_test(flow, CT))
1167 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1168 else
1169 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1170 return flow->rule[1];
1171 }
1172 }
1173
6d2a3ed0
OG		 1174 return rule;
1175}
1176
0d9f9647
VB		 1177void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1178 struct mlx5e_tc_flow *flow,
1179 struct mlx5_flow_attr *attr)
6d2a3ed0 1180{
226f2ca3 1181 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1182
89e39467
PB		 1183 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1184 goto offload_rule_0;
1185
4c3844d9 1186 if (flow_flag_test(flow, CT)) {
aedd133d 1187 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1188 return;
1189 }
1190
f94d6389
CM		 1191#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1192 if (flow_flag_test(flow, SAMPLE)) {
0027d70c 1193 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
f94d6389
CM		 1194 return;
1195 }
1196#endif
1197
c620b772 1198 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1199 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1200
89e39467 1201offload_rule_0:
6d2a3ed0
OG		 1202 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1203}
1204
0d9f9647 1205struct mlx5_flow_handle *
5dbe906f
PB		 1206mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1207 struct mlx5e_tc_flow *flow,
178f69b4 1208 struct mlx5_flow_spec *spec)
5dbe906f 1209{
c620b772 1210 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1211 struct mlx5_flow_handle *rule;
1212
c620b772
AL		 1213 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1214 if (!slow_attr)
1215 return ERR_PTR(-ENOMEM);
5dbe906f 1216
c620b772
AL		 1217 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1218 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1219 slow_attr->esw_attr->split_count = 0;
1220 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1221
1222 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1223 if (!IS_ERR(rule))
226f2ca3 1224 flow_flag_set(flow, SLOW);
5dbe906f 1225
c620b772
AL		 1226 kfree(slow_attr);
1227
5dbe906f
PB		 1228 return rule;
1229}
1230
0d9f9647
VB		 1231void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1232 struct mlx5e_tc_flow *flow)
5dbe906f 1233{
c620b772 1234 struct mlx5_flow_attr *slow_attr;
178f69b4 1235
c620b772 1236 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1237 if (!slow_attr) {
1238 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1239 return;
1240 }
c620b772
AL		 1241
1242 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1243 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1244 slow_attr->esw_attr->split_count = 0;
1245 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1246 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1247 flow_flag_clear(flow, SLOW);
c620b772 1248 kfree(slow_attr);
5dbe906f
PB		 1249}
1250
ad86755b
VB		 1251/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1252 * function.
1253 */
1254static void unready_flow_add(struct mlx5e_tc_flow *flow,
1255 struct list_head *unready_flows)
1256{
1257 flow_flag_set(flow, NOT_READY);
1258 list_add_tail(&flow->unready, unready_flows);
1259}
1260
1261/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1262 * function.
1263 */
1264static void unready_flow_del(struct mlx5e_tc_flow *flow)
1265{
1266 list_del(&flow->unready);
1267 flow_flag_clear(flow, NOT_READY);
1268}
1269
b4a23329
RD		 1270static void add_unready_flow(struct mlx5e_tc_flow *flow)
1271{
1272 struct mlx5_rep_uplink_priv *uplink_priv;
1273 struct mlx5e_rep_priv *rpriv;
1274 struct mlx5_eswitch *esw;
1275
1276 esw = flow->priv->mdev->priv.eswitch;
1277 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1278 uplink_priv = &rpriv->uplink_priv;
1279
ad86755b
VB		 1280 mutex_lock(&uplink_priv->unready_flows_lock);
1281 unready_flow_add(flow, &uplink_priv->unready_flows);
1282 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1283}
1284
1285static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1286{
ad86755b
VB		 1287 struct mlx5_rep_uplink_priv *uplink_priv;
1288 struct mlx5e_rep_priv *rpriv;
1289 struct mlx5_eswitch *esw;
1290
1291 esw = flow->priv->mdev->priv.eswitch;
1292 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1293 uplink_priv = &rpriv->uplink_priv;
1294
1295 mutex_lock(&uplink_priv->unready_flows_lock);
1296 unready_flow_del(flow);
1297 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1298}
1299
10742efc
VB		 1300static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1301
a508728a 1302bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1303{
1304 struct mlx5_core_dev *out_mdev, *route_mdev;
1305 struct mlx5e_priv *out_priv, *route_priv;
1306
1307 out_priv = netdev_priv(out_dev);
1308 out_mdev = out_priv->mdev;
1309 route_priv = netdev_priv(route_dev);
1310 route_mdev = route_priv->mdev;
1311
1312 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1313 route_mdev->coredev_type != MLX5_COREDEV_VF)
1314 return false;
1315
1316 return same_hw_devs(out_priv, route_priv);
1317}
1318
a508728a 1319int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1320{
1321 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1322 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1323 struct mlx5_core_dev *route_mdev;
1324 struct mlx5_eswitch *esw;
1325 u16 vhca_id;
1326 int err;
1327
1328 out_priv = netdev_priv(out_dev);
1329 esw = out_priv->mdev->priv.eswitch;
1330 route_priv = netdev_priv(route_dev);
1331 route_mdev = route_priv->mdev;
1332
1333 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1334 if (mlx5_lag_is_active(out_priv->mdev)) {
1335 /* In lag case we may get devices from different eswitch instances.
1336 * If we failed to get vport num, it means, mostly, that we on the wrong
1337 * eswitch.
1338 */
1339 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1340 if (err != -ENOENT)
1341 return err;
1342
1343 devcom = out_priv->mdev->priv.devcom;
1344 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1345 if (!esw)
1346 return -ENODEV;
1347 }
1348
10742efc 1349 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1350 if (devcom)
1351 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1352 return err;
1353}
1354
c7b9038d
VB		 1355int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1356 struct mlx5e_tc_flow_parse_attr *parse_attr,
1357 struct mlx5e_tc_flow *flow)
1358{
1359 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1360 struct mlx5_modify_hdr *mod_hdr;
1361
1362 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1363 get_flow_name_space(flow),
1364 mod_hdr_acts->num_actions,
1365 mod_hdr_acts->actions);
1366 if (IS_ERR(mod_hdr))
1367 return PTR_ERR(mod_hdr);
1368
1369 WARN_ON(flow->attr->modify_hdr);
1370 flow->attr->modify_hdr = mod_hdr;
1371
1372 return 0;
1373}
1374
c83954ab 1375static int
74491de9 1376mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1377 struct mlx5e_tc_flow *flow,
1378 struct netlink_ext_ack *extack)
adb4c123
OG		 1379{
1380 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1381 struct mlx5e_tc_flow_parse_attr *parse_attr;
1382 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1383 bool vf_tun = false, encap_valid = true;
fe7738eb 1384 struct net_device *encap_dev = NULL;
c620b772 1385 struct mlx5_esw_flow_attr *esw_attr;
3c37745e
OG		 1386 struct mlx5e_rep_priv *rpriv;
1387 struct mlx5e_priv *out_priv;
97a8d29a 1388 struct mlx5_fc *counter;
39ac237c 1389 u32 max_prio, max_chain;
0ad060ee 1390 int err = 0;
f493f155 1391 int out_index;
8b32580d 1392
84179981
PB		 1393 /* We check chain range only for tc flows.
1394 * For ft flows, we checked attr->chain was originally 0 and set it to
1395 * FDB_FT_CHAIN which is outside tc range.
1396 * See mlx5e_rep_setup_ft_cb().
1397 */
ae430332 1398 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1399 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1400 NL_SET_ERR_MSG_MOD(extack,
1401 "Requested chain is out of supported range");
8914add2
VB		 1402 err = -EOPNOTSUPP;
1403 goto err_out;
bf07aa73
PB		 1404 }
1405
ae430332 1406 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1407 if (attr->prio > max_prio) {
61644c3d
RD		 1408 NL_SET_ERR_MSG_MOD(extack,
1409 "Requested priority is out of supported range");
8914add2
VB		 1410 err = -EOPNOTSUPP;
1411 goto err_out;
bf07aa73 1412 }
e52c2802 1413
777bb800
VB		 1414 if (flow_flag_test(flow, TUN_RX)) {
1415 err = mlx5e_attach_decap_route(priv, flow);
1416 if (err)
8914add2 1417 goto err_out;
777bb800
VB		 1418 }
1419
14e6b038
EC		 1420 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1421 err = mlx5e_attach_decap(priv, flow, extack);
1422 if (err)
8914add2 1423 goto err_out;
14e6b038
EC		 1424 }
1425
c620b772
AL		 1426 parse_attr = attr->parse_attr;
1427 esw_attr = attr->esw_attr;
1428
f493f155 1429 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1430 struct net_device *out_dev;
8c4dc42b
EB		 1431 int mirred_ifindex;
1432
c620b772 1433 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1434 continue;
1435
7040632d 1436 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1437 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1438 if (!out_dev) {
1439 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1440 err = -ENODEV;
1441 goto err_out;
1442 }
733d4f36 1443 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1444 extack, &encap_dev, &encap_valid);
fe7738eb 1445 dev_put(out_dev);
0ad060ee 1446 if (err)
8914add2 1447 goto err_out;
0ad060ee 1448
8914add2
VB		 1449 if (esw_attr->dests[out_index].flags &
1450 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1451 vf_tun = true;
3c37745e
OG		 1452 out_priv = netdev_priv(encap_dev);
1453 rpriv = out_priv->ppriv;
c620b772
AL		 1454 esw_attr->dests[out_index].rep = rpriv->rep;
1455 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1456 }
1457
7d1a3d08
VB		 1458 if (vf_tun && esw_attr->out_count > 1) {
1459 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1460 err = -EOPNOTSUPP;
1461 goto err_out;
1462 }
1463
8b32580d 1464 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1465 if (err)
8914add2 1466 goto err_out;
adb4c123 1467
d5a3c2b6
RD		 1468 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1469 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1470 if (vf_tun) {
1471 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1472 if (err)
1473 goto err_out;
1474 } else {
1475 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1476 if (err)
1477 goto err_out;
1478 }
d7e75a32
OG		 1479 }
1480
b8aee822 1481 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1482 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1483 if (IS_ERR(counter)) {
1484 err = PTR_ERR(counter);
1485 goto err_out;
1486 }
b8aee822
MB		 1487
1488 attr->counter = counter;
1489 }
1490
0ad060ee
RD		 1491 /* we get here if one of the following takes place:
1492 * (1) there's no error
1493 * (2) there's an encap action and we don't have valid neigh
3c37745e 1494 */
bc1d75fa 1495 if (!encap_valid)
178f69b4 1496 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1497 else
6d2a3ed0 1498 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1499
8914add2
VB		 1500 if (IS_ERR(flow->rule[0])) {
1501 err = PTR_ERR(flow->rule[0]);
1502 goto err_out;
1503 }
1504 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1505
1506 return 0;
8914add2
VB		 1507
1508err_out:
1509 flow_flag_set(flow, FAILED);
1510 return err;
aa0cbbae 1511}
d85cdccb 1512
9272e3df
YK		 1513static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1514{
c620b772 1515 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1516 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1517 spec->match_value,
1518 misc_parameters_3);
1519 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1520 headers_v,
1521 geneve_tlv_option_0_data);
1522
1523 return !!geneve_tlv_opt_0_data;
1524}
1525
d85cdccb
OG		 1526static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1527 struct mlx5e_tc_flow *flow)
1528{
1529 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1530 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1531 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1532 bool vf_tun = false;
f493f155 1533 int out_index;
d85cdccb 1534
777bb800 1535 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1536 mlx5e_put_flow_tunnel_id(flow);
1537
12a240a4 1538 if (flow_flag_test(flow, NOT_READY))
b4a23329 1539 remove_unready_flow(flow);
ef06c9ee 1540
226f2ca3
VB		 1541 if (mlx5e_is_offloaded_flow(flow)) {
1542 if (flow_flag_test(flow, SLOW))
178f69b4 1543 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1544 else
1545 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1546 }
909e615d 1547 complete_all(&flow->del_hw_done);
d85cdccb 1548
9272e3df
YK		 1549 if (mlx5_flow_has_geneve_opt(flow))
1550 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1551
513f8f7f 1552 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1553
777bb800
VB		 1554 if (flow->decap_route)
1555 mlx5e_detach_decap_route(priv, flow);
1556
1557 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1558 if (esw_attr->dests[out_index].flags &
1559 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1560 vf_tun = true;
777bb800 1561 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1562 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1563 kfree(attr->parse_attr->tun_info[out_index]);
1564 }
777bb800 1565 }
d7e75a32 1566
aedd133d 1567 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1568
c7b9038d
VB		 1569 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1570 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1571 if (vf_tun && attr->modify_hdr)
1572 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1573 else
1574 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1575 }
bcd6740c 1576 kfree(attr->sample_attr);
8914add2
VB		 1577 kvfree(attr->parse_attr);
1578 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1579
1580 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1581 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1582
1583 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1584 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1585
1586 kfree(flow->attr);
d85cdccb
OG		 1587}
1588
0d9f9647 1589struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1590{
c620b772 1591 return flow->attr->counter;
b8aee822
MB		 1592}
1593
6a06c2f7 1594/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1595void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1596{
1597 struct mlx5e_tc_flow *flow, *tmp;
1598
1599 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1600 mlx5e_flow_put(priv, flow);
1601}
1602
04de7dda
RD		 1603static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1604{
1605 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1606
226f2ca3
VB		 1607 if (!flow_flag_test(flow, ESWITCH) ||
1608 !flow_flag_test(flow, DUP))
04de7dda
RD		 1609 return;
1610
1611 mutex_lock(&esw->offloads.peer_mutex);
1612 list_del(&flow->peer);
1613 mutex_unlock(&esw->offloads.peer_mutex);
1614
226f2ca3 1615 flow_flag_clear(flow, DUP);
04de7dda 1616
eb252c3a
RD		 1617 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1618 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1619 kfree(flow->peer_flow);
1620 }
1621
04de7dda
RD		 1622 flow->peer_flow = NULL;
1623}
1624
1625static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1626{
1627 struct mlx5_core_dev *dev = flow->priv->mdev;
1628 struct mlx5_devcom *devcom = dev->priv.devcom;
1629 struct mlx5_eswitch *peer_esw;
1630
1631 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1632 if (!peer_esw)
1633 return;
1634
1635 __mlx5e_tc_del_fdb_peer_flow(flow);
1636 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1637}
1638
e8f887ac 1639static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1640 struct mlx5e_tc_flow *flow)
e8f887ac 1641{
226f2ca3 1642 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1643 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1644 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1645 } else {
d85cdccb 1646 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1647 }
e8f887ac
AV		 1648}
1649
ee950e5d 1650static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1651{
1652 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1653 struct flow_action *flow_action = &rule->action;
1654 const struct flow_action_entry *act;
1655 int i;
1656
ee950e5d
CM		 1657 if (chain)
1658 return false;
1659
0a7fcb78
PB		 1660 flow_action_for_each(i, act, flow_action) {
1661 switch (act->id) {
1662 case FLOW_ACTION_GOTO:
1663 return true;
ee950e5d
CM		 1664 case FLOW_ACTION_SAMPLE:
1665 return true;
0a7fcb78
PB		 1666 default:
1667 continue;
1668 }
1669 }
1670
1671 return false;
1672}
bbd00f7e 1673
0a7fcb78
PB		 1674static int
1675enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1676 struct flow_dissector_key_enc_opts *opts,
1677 struct netlink_ext_ack *extack,
1678 bool *dont_care)
1679{
1680 struct geneve_opt *opt;
1681 int off = 0;
1682
1683 *dont_care = true;
1684
1685 while (opts->len > off) {
1686 opt = (struct geneve_opt *)&opts->data[off];
1687
1688 if (!(*dont_care) || opt->opt_class || opt->type ||
1689 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1690 *dont_care = false;
1691
c51323ee 1692 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1693 opt->type != U8_MAX) {
0a7fcb78
PB		 1694 NL_SET_ERR_MSG(extack,
1695 "Partial match of tunnel options in chain > 0 isn't supported");
1696 netdev_warn(priv->netdev,
1697 "Partial match of tunnel options in chain > 0 isn't supported");
1698 return -EOPNOTSUPP;
1699 }
1700 }
1701
1702 off += sizeof(struct geneve_opt) + opt->length * 4;
1703 }
1704
1705 return 0;
1706}
1707
1708#define COPY_DISSECTOR(rule, diss_key, dst)\
1709({ \
1710 struct flow_rule *__rule = (rule);\
1711 typeof(dst) __dst = dst;\
1712\
1713 memcpy(__dst,\
1714 skb_flow_dissector_target(__rule->match.dissector,\
1715 diss_key,\
1716 __rule->match.key),\
1717 sizeof(*__dst));\
1718})
1719
1720static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1721 struct mlx5e_tc_flow *flow,
1722 struct flow_cls_offload *f,
1723 struct net_device *filter_dev)
bbd00f7e 1724{
f9e30088 1725 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1726 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1727 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1728 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1729 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1730 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1731 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1732 struct mlx5e_rep_priv *uplink_rpriv;
1733 struct tunnel_match_key tunnel_key;
1734 bool enc_opts_is_dont_care = true;
1735 u32 tun_id, enc_opts_id = 0;
1736 struct mlx5_eswitch *esw;
1737 u32 value, mask;
8f256622 1738 int err;
2e72eb43 1739
0a7fcb78
PB		 1740 esw = priv->mdev->priv.eswitch;
1741 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1742 uplink_priv = &uplink_rpriv->uplink_priv;
1743
1744 memset(&tunnel_key, 0, sizeof(tunnel_key));
1745 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1746 &tunnel_key.enc_control);
1747 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1748 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1749 &tunnel_key.enc_ipv4);
1750 else
1751 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1752 &tunnel_key.enc_ipv6);
1753 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1754 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1755 &tunnel_key.enc_tp);
1756 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1757 &tunnel_key.enc_key_id);
1758 tunnel_key.filter_ifindex = filter_dev->ifindex;
1759
1760 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1761 if (err)
101f4de9 1762 return err;
bbd00f7e 1763
0a7fcb78
PB		 1764 flow_rule_match_enc_opts(rule, &enc_opts_match);
1765 err = enc_opts_is_dont_care_or_full_match(priv,
1766 enc_opts_match.mask,
1767 extack,
1768 &enc_opts_is_dont_care);
1769 if (err)
1770 goto err_enc_opts;
fe1587a7 1771
0a7fcb78 1772 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1773 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1774 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1775 sizeof(*enc_opts_match.key));
1776 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1777 sizeof(*enc_opts_match.mask));
1778
0a7fcb78 1779 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1780 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1781 if (err)
1782 goto err_enc_opts;
1783 }
fe1587a7 1784
0a7fcb78
PB		 1785 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1786 mask = enc_opts_id ? TUNNEL_ID_MASK :
1787 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1788
0a7fcb78
PB		 1789 if (attr->chain) {
1790 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1791 TUNNEL_TO_REG, value, mask);
1792 } else {
1793 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1794 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1795 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1796 TUNNEL_TO_REG, value);
1797 if (err)
1798 goto err_set;
fe1587a7 1799
0a7fcb78 1800 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1801 }
bbd00f7e 1802
0a7fcb78
PB		 1803 flow->tunnel_id = value;
1804 return 0;
bcef735c 1805
0a7fcb78
PB		 1806err_set:
1807 if (enc_opts_id)
1808 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1809 enc_opts_id);
1810err_enc_opts:
1811 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1812 return err;
1813}
bcef735c 1814
0a7fcb78
PB		 1815static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1816{
1817 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1818 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1819 struct mlx5_rep_uplink_priv *uplink_priv;
1820 struct mlx5e_rep_priv *uplink_rpriv;
1821 struct mlx5_eswitch *esw;
bcef735c 1822
0a7fcb78
PB		 1823 esw = flow->priv->mdev->priv.eswitch;
1824 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1825 uplink_priv = &uplink_rpriv->uplink_priv;
1826
1827 if (tun_id)
1828 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1829 if (enc_opts_id)
1830 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1831 enc_opts_id);
1832}
e98bedf5 1833
4c3844d9
PB		 1834u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1835{
1836 return flow->tunnel_id;
1837}
1838
fca53304
EB		 1839void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1840 struct flow_match_basic *match, bool outer,
1841 void *headers_c, void *headers_v)
1842{
1843 bool ip_version_cap;
1844
1845 ip_version_cap = outer ?
1846 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1847 ft_field_support.outer_ip_version) :
1848 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1849 ft_field_support.inner_ip_version);
1850
1851 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1852 (match->key->n_proto == htons(ETH_P_IP) ||
1853 match->key->n_proto == htons(ETH_P_IPV6))) {
1854 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1855 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1856 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1857 } else {
1858 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1859 ntohs(match->mask->n_proto));
1860 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1861 ntohs(match->key->n_proto));
1862 }
4a5d5d73
EB		 1863}
1864
0d9f9647 1865u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1866{
1867 void *headers_v;
1868 u16 ethertype;
1869 u8 ip_version;
1870
1871 if (outer)
1872 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1873 else
1874 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1875
1876 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1877 /* Return ip_version converted from ethertype anyway */
1878 if (!ip_version) {
1879 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1880 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1881 ip_version = 4;
1882 else if (ethertype == ETH_P_IPV6)
1883 ip_version = 6;
1884 }
1885 return ip_version;
1886}
1887
bbd00f7e 1888static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1889 struct mlx5e_tc_flow *flow,
bbd00f7e 1890 struct mlx5_flow_spec *spec,
f9e30088 1891 struct flow_cls_offload *f,
0a7fcb78
PB		 1892 struct net_device *filter_dev,
1893 u8 *match_level,
1894 bool *match_inner)
bbd00f7e 1895{
a508728a 1896 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1897 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1898 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1899 bool needs_mapping, sets_mapping;
8f256622 1900 int err;
2e72eb43 1901
0a7fcb78
PB		 1902 if (!mlx5e_is_eswitch_flow(flow))
1903 return -EOPNOTSUPP;
1904
c620b772 1905 needs_mapping = !!flow->attr->chain;
ee950e5d 1906 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 1907 *match_inner = !needs_mapping;
1908
1909 if ((needs_mapping || sets_mapping) &&
636bb968 1910 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1911 NL_SET_ERR_MSG(extack,
636bb968 1912 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1913 netdev_warn(priv->netdev,
636bb968 1914 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1915 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1916 }
1917
c620b772 1918 if (!flow->attr->chain) {
0a7fcb78
PB		 1919 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1920 match_level);
1921 if (err) {
e98bedf5 1922 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1923 "Failed to parse tunnel attributes");
1924 netdev_warn(priv->netdev,
1925 "Failed to parse tunnel attributes");
1926 return err;
e98bedf5
EB		 1927 }
1928
14e6b038
EC		 1929 /* With mpls over udp we decapsulate using packet reformat
1930 * object
1931 */
1932 if (!netif_is_bareudp(filter_dev))
c620b772 1933 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1934 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1935 if (err)
1936 return err;
1937 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1938 struct mlx5_flow_spec *tmp_spec;
1939
1940 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1941 if (!tmp_spec) {
1942 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1943 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1944 return -ENOMEM;
1945 }
1946 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1947
1948 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1949 if (err) {
1950 kvfree(tmp_spec);
1951 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1952 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1953 return err;
1954 }
1955 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1956 kvfree(tmp_spec);
1957 if (err)
1958 return err;
bcef735c
OG		 1959 }
1960
0a7fcb78
PB		 1961 if (!needs_mapping && !sets_mapping)
1962 return 0;
bbd00f7e 1963
0a7fcb78 1964 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1965}
bbd00f7e 1966
0a7fcb78 1967static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1968{
0a7fcb78
PB		 1969 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1970 inner_headers);
bbd00f7e
HHZ		 1971}
1972
0a7fcb78 1973static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1974{
0a7fcb78
PB		 1975 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1976 inner_headers);
1977}
1978
1979static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1980{
1981 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1982 outer_headers);
1983}
1984
1985static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1986{
1987 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1988 outer_headers);
8377629e
EB		 1989}
1990
1991static void *get_match_headers_value(u32 flags,
1992 struct mlx5_flow_spec *spec)
1993{
1994 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1995 get_match_inner_headers_value(spec) :
1996 get_match_outer_headers_value(spec);
1997}
1998
1999static void *get_match_headers_criteria(u32 flags,
2000 struct mlx5_flow_spec *spec)
2001{
2002 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2003 get_match_inner_headers_criteria(spec) :
2004 get_match_outer_headers_criteria(spec);
8377629e
EB		 2005}
2006
6d65bc64 2007static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2008 struct flow_cls_offload *f)
2009{
2010 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2011 struct netlink_ext_ack *extack = f->common.extack;
2012 struct net_device *ingress_dev;
2013 struct flow_match_meta match;
2014
2015 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2016 return 0;
2017
2018 flow_rule_match_meta(rule, &match);
e3e0f9b2 2019 if (!match.mask->ingress_ifindex)
2020 return 0;
2021
6d65bc64 2022 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2023 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2024 return -EOPNOTSUPP;
6d65bc64 2025 }
2026
2027 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2028 match.key->ingress_ifindex);
2029 if (!ingress_dev) {
2030 NL_SET_ERR_MSG_MOD(extack,
2031 "Can't find the ingress port to match on");
a683012a 2032 return -ENOENT;
6d65bc64 2033 }
2034
2035 if (ingress_dev != filter_dev) {
2036 NL_SET_ERR_MSG_MOD(extack,
2037 "Can't match on the ingress filter port");
a683012a 2038 return -EOPNOTSUPP;
6d65bc64 2039 }
2040
2041 return 0;
2042}
2043
72046a91
EC		 2044static bool skip_key_basic(struct net_device *filter_dev,
2045 struct flow_cls_offload *f)
2046{
2047 /* When doing mpls over udp decap, the user needs to provide
2048 * MPLS_UC as the protocol in order to be able to match on mpls
2049 * label fields. However, the actual ethertype is IP so we want to
2050 * avoid matching on this, otherwise we'll fail the match.
2051 */
2052 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2053 return true;
2054
2055 return false;
2056}
2057
de0af0bf 2058static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2059 struct mlx5e_tc_flow *flow,
de0af0bf 2060 struct mlx5_flow_spec *spec,
f9e30088 2061 struct flow_cls_offload *f,
54c177ca 2062 struct net_device *filter_dev,
93b3586e 2063 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2064{
e98bedf5 2065 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2066 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2067 outer_headers);
2068 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2069 outer_headers);
699e96dd
JL		 2070 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2071 misc_parameters);
2072 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2073 misc_parameters);
a3222a2d
MD		 2074 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2075 misc_parameters_3);
2076 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2077 misc_parameters_3);
f9e30088 2078 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2079 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2080 enum fs_flow_table_type fs_type;
e3a2b7ed
AV		 2081 u16 addr_type = 0;
2082 u8 ip_proto = 0;
93b3586e 2083 u8 *match_level;
6d65bc64 2084 int err;
e3a2b7ed 2085
afe93f71 2086 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2087 match_level = outer_match_level;
de0af0bf 2088
8f256622 2089 if (dissector->used_keys &
3d144578
VB		 2090 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2091 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2092 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2093 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2094 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2095 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2096 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2097 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2098 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2099 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2100 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2101 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2102 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2103 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2104 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2105 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2106 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2107 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2108 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2109 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2110 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2111 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2112 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2113 dissector->used_keys);
e3a2b7ed
AV		 2114 return -EOPNOTSUPP;
2115 }
2116
075973c7 2117 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2118 bool match_inner = false;
bbd00f7e 2119
0a7fcb78
PB		 2120 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2121 outer_match_level, &match_inner);
2122 if (err)
2123 return err;
2124
2125 if (match_inner) {
2126 /* header pointers should point to the inner headers
2127 * if the packet was decapsulated already.
2128 * outer headers are set by parse_tunnel_attr.
2129 */
2130 match_level = inner_match_level;
2131 headers_c = get_match_inner_headers_criteria(spec);
2132 headers_v = get_match_inner_headers_value(spec);
2133 }
bbd00f7e
HHZ		 2134 }
2135
6d65bc64 2136 err = mlx5e_flower_parse_meta(filter_dev, f);
2137 if (err)
2138 return err;
2139
72046a91
EC		 2140 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2141 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2142 struct flow_match_basic match;
2143
2144 flow_rule_match_basic(rule, &match);
fca53304
EB		 2145 mlx5e_tc_set_ethertype(priv->mdev, &match,
2146 match_level == outer_match_level,
2147 headers_c, headers_v);
e3a2b7ed 2148
8f256622 2149 if (match.mask->n_proto)
d708f902 2150 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2151 }
35a605db
EB		 2152 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2153 is_vlan_dev(filter_dev)) {
2154 struct flow_dissector_key_vlan filter_dev_mask;
2155 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2156 struct flow_match_vlan match;
2157
35a605db
EB		 2158 if (is_vlan_dev(filter_dev)) {
2159 match.key = &filter_dev_key;
2160 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2161 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2162 match.key->vlan_priority = 0;
2163 match.mask = &filter_dev_mask;
2164 memset(match.mask, 0xff, sizeof(*match.mask));
2165 match.mask->vlan_priority = 0;
2166 } else {
2167 flow_rule_match_vlan(rule, &match);
2168 }
8f256622
PNA		 2169 if (match.mask->vlan_id ||
2170 match.mask->vlan_priority ||
2171 match.mask->vlan_tpid) {
2172 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2173 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2174 svlan_tag, 1);
2175 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2176 svlan_tag, 1);
2177 } else {
2178 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2179 cvlan_tag, 1);
2180 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2181 cvlan_tag, 1);
2182 }
095b6cfd 2183
8f256622
PNA		 2184 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2185 match.mask->vlan_id);
2186 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2187 match.key->vlan_id);
358d79a4 2188
8f256622
PNA		 2189 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2190 match.mask->vlan_priority);
2191 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2192 match.key->vlan_priority);
54782900 2193
d708f902 2194 *match_level = MLX5_MATCH_L2;
54782900 2195 }
d3a80bb5 2196 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2197 /* cvlan_tag enabled in match criteria and
2198 * disabled in match value means both S & C tags
2199 * don't exist (untagged of both)
2200 */
cee26487 2201 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2202 *match_level = MLX5_MATCH_L2;
54782900
OG		 2203 }
2204
8f256622
PNA		 2205 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2206 struct flow_match_vlan match;
2207
12d5cbf8 2208 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2209 if (match.mask->vlan_id ||
2210 match.mask->vlan_priority ||
2211 match.mask->vlan_tpid) {
afe93f71
RD		 2212 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2213 fs_type)) {
2214 NL_SET_ERR_MSG_MOD(extack,
2215 "Matching on CVLAN is not supported");
2216 return -EOPNOTSUPP;
2217 }
2218
8f256622 2219 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2220 MLX5_SET(fte_match_set_misc, misc_c,
2221 outer_second_svlan_tag, 1);
2222 MLX5_SET(fte_match_set_misc, misc_v,
2223 outer_second_svlan_tag, 1);
2224 } else {
2225 MLX5_SET(fte_match_set_misc, misc_c,
2226 outer_second_cvlan_tag, 1);
2227 MLX5_SET(fte_match_set_misc, misc_v,
2228 outer_second_cvlan_tag, 1);
2229 }
2230
2231 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2232 match.mask->vlan_id);
699e96dd 2233 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2234 match.key->vlan_id);
699e96dd 2235 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2236 match.mask->vlan_priority);
699e96dd 2237 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2238 match.key->vlan_priority);
699e96dd
JL		 2239
2240 *match_level = MLX5_MATCH_L2;
0faddfe6 2241 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2242 }
2243 }
2244
8f256622
PNA		 2245 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2246 struct flow_match_eth_addrs match;
54782900 2247
8f256622 2248 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2249 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2250 dmac_47_16),
8f256622 2251 match.mask->dst);
d3a80bb5
OG		 2252 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2253 dmac_47_16),
8f256622 2254 match.key->dst);
d3a80bb5
OG		 2255
2256 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2257 smac_47_16),
8f256622 2258 match.mask->src);
d3a80bb5
OG		 2259 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2260 smac_47_16),
8f256622 2261 match.key->src);
d3a80bb5 2262
8f256622
PNA		 2263 if (!is_zero_ether_addr(match.mask->src) ||
2264 !is_zero_ether_addr(match.mask->dst))
d708f902 2265 *match_level = MLX5_MATCH_L2;
54782900
OG		 2266 }
2267
8f256622
PNA		 2268 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2269 struct flow_match_control match;
54782900 2270
8f256622
PNA		 2271 flow_rule_match_control(rule, &match);
2272 addr_type = match.key->addr_type;
54782900
OG		 2273
2274 /* the HW doesn't support frag first/later */
8f256622 2275 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2276 return -EOPNOTSUPP;
2277
8f256622 2278 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2279 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2280 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2281 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2282
2283 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2284 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2285 *match_level = MLX5_MATCH_L2;
54782900
OG		 2286 /* *** L2 attributes parsing up to here *** */
2287 else
83621b7d 2288 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2289 }
2290 }
2291
8f256622
PNA		 2292 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2293 struct flow_match_basic match;
2294
2295 flow_rule_match_basic(rule, &match);
2296 ip_proto = match.key->ip_proto;
54782900
OG		 2297
2298 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2299 match.mask->ip_proto);
54782900 2300 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2301 match.key->ip_proto);
54782900 2302
8f256622 2303 if (match.mask->ip_proto)
d708f902 2304 *match_level = MLX5_MATCH_L3;
54782900
OG		 2305 }
2306
e3a2b7ed 2307 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2308 struct flow_match_ipv4_addrs match;
e3a2b7ed 2309
8f256622 2310 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2311 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2312 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2313 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2314 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2315 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2316 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2317 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2318 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2319 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2320 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2321 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2322 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2323
8f256622 2324 if (match.mask->src || match.mask->dst)
d708f902 2325 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2326 }
2327
2328 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2329 struct flow_match_ipv6_addrs match;
e3a2b7ed 2330
8f256622 2331 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2332 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2333 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2334 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2335 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2336 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2337 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2338
2339 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2340 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2341 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2342 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2343 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2344 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2345
8f256622
PNA		 2346 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2347 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2348 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2349 }
2350
8f256622
PNA		 2351 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2352 struct flow_match_ip match;
1f97a526 2353
8f256622
PNA		 2354 flow_rule_match_ip(rule, &match);
2355 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2356 match.mask->tos & 0x3);
2357 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2358 match.key->tos & 0x3);
1f97a526 2359
8f256622
PNA		 2360 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2361 match.mask->tos >> 2);
2362 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2363 match.key->tos >> 2);
1f97a526 2364
8f256622
PNA		 2365 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2366 match.mask->ttl);
2367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2368 match.key->ttl);
1f97a526 2369
8f256622 2370 if (match.mask->ttl &&
a8ade55f 2371 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2372 ft_field_support.outer_ipv4_ttl)) {
2373 NL_SET_ERR_MSG_MOD(extack,
2374 "Matching on TTL is not supported");
1f97a526 2375 return -EOPNOTSUPP;
e98bedf5 2376 }
a8ade55f 2377
8f256622 2378 if (match.mask->tos || match.mask->ttl)
d708f902 2379 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2380 }
2381
54782900
OG		 2382 /* *** L3 attributes parsing up to here *** */
2383
8f256622
PNA		 2384 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2385 struct flow_match_ports match;
2386
2387 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2388 switch (ip_proto) {
2389 case IPPROTO_TCP:
2390 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2391 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2392 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2393 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2394
2395 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2396 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2397 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2398 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2399 break;
2400
2401 case IPPROTO_UDP:
2402 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2403 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2404 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2405 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2406
2407 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2408 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2409 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2410 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2411 break;
2412 default:
e98bedf5
EB		 2413 NL_SET_ERR_MSG_MOD(extack,
2414 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2415 netdev_err(priv->netdev,
2416 "Only UDP and TCP transport are supported\n");
2417 return -EINVAL;
2418 }
de0af0bf 2419
8f256622 2420 if (match.mask->src || match.mask->dst)
d708f902 2421 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2422 }
2423
8f256622
PNA		 2424 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2425 struct flow_match_tcp match;
e77834ec 2426
8f256622 2427 flow_rule_match_tcp(rule, &match);
e77834ec 2428 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2429 ntohs(match.mask->flags));
e77834ec 2430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2431 ntohs(match.key->flags));
e77834ec 2432
8f256622 2433 if (match.mask->flags)
d708f902 2434 *match_level = MLX5_MATCH_L4;
e77834ec 2435 }
a3222a2d
MD		 2436 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2437 struct flow_match_icmp match;
e77834ec 2438
a3222a2d
MD		 2439 flow_rule_match_icmp(rule, &match);
2440 switch (ip_proto) {
2441 case IPPROTO_ICMP:
2442 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2443 MLX5_FLEX_PROTO_ICMP))
2444 return -EOPNOTSUPP;
2445 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2446 match.mask->type);
2447 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2448 match.key->type);
2449 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2450 match.mask->code);
2451 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2452 match.key->code);
2453 break;
2454 case IPPROTO_ICMPV6:
2455 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2456 MLX5_FLEX_PROTO_ICMPV6))
2457 return -EOPNOTSUPP;
2458 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2459 match.mask->type);
2460 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2461 match.key->type);
2462 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2463 match.mask->code);
2464 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2465 match.key->code);
2466 break;
2467 default:
2468 NL_SET_ERR_MSG_MOD(extack,
2469 "Code and type matching only with ICMP and ICMPv6");
2470 netdev_err(priv->netdev,
2471 "Code and type matching only with ICMP and ICMPv6\n");
2472 return -EINVAL;
2473 }
2474 if (match.mask->code || match.mask->type) {
2475 *match_level = MLX5_MATCH_L4;
2476 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2477 }
2478 }
39c538d6 2479 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2480 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2481 !netif_is_bareudp(filter_dev)) {
2482 NL_SET_ERR_MSG_MOD(extack,
2483 "Matching on MPLS is supported only for MPLS over UDP");
2484 netdev_err(priv->netdev,
2485 "Matching on MPLS is supported only for MPLS over UDP\n");
2486 return -EOPNOTSUPP;
2487 }
2488
e3a2b7ed
AV		 2489 return 0;
2490}
2491
de0af0bf 2492static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2493 struct mlx5e_tc_flow *flow,
de0af0bf 2494 struct mlx5_flow_spec *spec,
f9e30088 2495 struct flow_cls_offload *f,
54c177ca 2496 struct net_device *filter_dev)
de0af0bf 2497{
93b3586e 2498 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2499 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2500 struct mlx5_core_dev *dev = priv->mdev;
2501 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2502 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2503 struct mlx5_eswitch_rep *rep;
226f2ca3 2504 bool is_eswitch_flow;
de0af0bf
RD		 2505 int err;
2506
93b3586e
HN		 2507 inner_match_level = MLX5_MATCH_NONE;
2508 outer_match_level = MLX5_MATCH_NONE;
2509
0a7fcb78
PB		 2510 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2511 &inner_match_level, &outer_match_level);
93b3586e
HN		 2512 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2513 outer_match_level : inner_match_level;
de0af0bf 2514
226f2ca3
VB		 2515 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2516 if (!err && is_eswitch_flow) {
1d447a39 2517 rep = rpriv->rep;
b05af6aa 2518 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2519 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2520 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2521 NL_SET_ERR_MSG_MOD(extack,
2522 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2523 netdev_warn(priv->netdev,
2524 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2525 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2526 return -EOPNOTSUPP;
2527 }
2528 }
2529
c620b772
AL		 2530 flow->attr->inner_match_level = inner_match_level;
2531 flow->attr->outer_match_level = outer_match_level;
2532
38aa51c1 2533
de0af0bf
RD		 2534 return err;
2535}
2536
d79b6df6
OG		 2537struct pedit_headers {
2538 struct ethhdr eth;
0eb69bb9 2539 struct vlan_hdr vlan;
d79b6df6
OG		 2540 struct iphdr ip4;
2541 struct ipv6hdr ip6;
2542 struct tcphdr tcp;
2543 struct udphdr udp;
2544};
2545
c500c86b
PNA		 2546struct pedit_headers_action {
2547 struct pedit_headers vals;
2548 struct pedit_headers masks;
2549 u32 pedits;
2550};
2551
d79b6df6 2552static int pedit_header_offsets[] = {
73867881
PNA		 2553 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2554 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2555 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2556 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2557 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2558};
2559
2560#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2561
2562static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2563 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2564{
2565 u32 *curr_pmask, *curr_pval;
2566
c500c86b
PNA		 2567 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2568 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2569
2570 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2571 goto out_err;
2572
2573 *curr_pmask |= mask;
2574 *curr_pval |= (val & mask);
2575
2576 return 0;
2577
2578out_err:
2579 return -EOPNOTSUPP;
2580}
2581
2582struct mlx5_fields {
2583 u8 field;
88f30bbc
DL		 2584 u8 field_bsize;
2585 u32 field_mask;
d79b6df6 2586 u32 offset;
27c11b6b 2587 u32 match_offset;
d79b6df6
OG		 2588};
2589
88f30bbc
DL		 2590#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2591 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2592 offsetof(struct pedit_headers, field) + (off), \
2593 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2594
2ef86872
EB		 2595/* masked values are the same and there are no rewrites that do not have a
2596 * match.
2597 */
2598#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2599 type matchmaskx = *(type *)(matchmaskp); \
2600 type matchvalx = *(type *)(matchvalp); \
2601 type maskx = *(type *)(maskp); \
2602 type valx = *(type *)(valp); \
2603 \
2604 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2605 matchmaskx)); \
2606})
2607
27c11b6b 2608static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2609 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2610{
2611 bool same = false;
2612
88f30bbc
DL		 2613 switch (bsize) {
2614 case 8:
2ef86872 2615 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2616 break;
88f30bbc 2617 case 16:
2ef86872 2618 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2619 break;
88f30bbc 2620 case 32:
2ef86872 2621 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2622 break;
2623 }
2624
2625 return same;
2626}
a8e4f0c4 2627
d79b6df6 2628static struct mlx5_fields fields[] = {
88f30bbc
DL		 2629 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2630 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2631 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2632 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2633 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2634 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2635
ab9341b5 2636 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2637 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2638 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2639 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2640
2641 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2642 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2643 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2644 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2645 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2646 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2647 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2648 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2649 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2650 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2651 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2652 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2653 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2654 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2655 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2656 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2657 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2658 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2659
88f30bbc
DL		 2660 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2661 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2662 /* in linux iphdr tcp_flags is 8 bits long */
2663 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2664
88f30bbc
DL		 2665 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2666 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2667};
2668
82198d8b
MD		 2669static unsigned long mask_to_le(unsigned long mask, int size)
2670{
2671 __be32 mask_be32;
2672 __be16 mask_be16;
2673
2674 if (size == 32) {
2675 mask_be32 = (__force __be32)(mask);
2676 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2677 } else if (size == 16) {
2678 mask_be32 = (__force __be32)(mask);
2679 mask_be16 = *(__be16 *)&mask_be32;
2680 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2681 }
2682
2683 return mask;
2684}
6ae4a6a5
PB		 2685static int offload_pedit_fields(struct mlx5e_priv *priv,
2686 int namespace,
2687 struct pedit_headers_action *hdrs,
e98bedf5 2688 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2689 u32 *action_flags,
e98bedf5 2690 struct netlink_ext_ack *extack)
d79b6df6
OG		 2691{
2692 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2693 int i, action_size, first, last, next_z;
88f30bbc
DL		 2694 void *headers_c, *headers_v, *action, *vals_p;
2695 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2696 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2697 struct mlx5_fields *f;
82198d8b 2698 unsigned long mask, field_mask;
6ae4a6a5 2699 int err;
88f30bbc
DL		 2700 u8 cmd;
2701
6ae4a6a5 2702 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2703 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2704 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2705
73867881
PNA		 2706 set_masks = &hdrs[0].masks;
2707 add_masks = &hdrs[1].masks;
2708 set_vals = &hdrs[0].vals;
2709 add_vals = &hdrs[1].vals;
d79b6df6 2710
d65dbedf 2711 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2712
2713 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2714 bool skip;
2715
d79b6df6
OG		 2716 f = &fields[i];
2717 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2718 s_mask = 0;
2719 a_mask = 0;
d79b6df6
OG		 2720
2721 s_masks_p = (void *)set_masks + f->offset;
2722 a_masks_p = (void *)add_masks + f->offset;
2723
88f30bbc
DL		 2724 s_mask = *s_masks_p & f->field_mask;
2725 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2726
2727 if (!s_mask && !a_mask) /* nothing to offload here */
2728 continue;
2729
2730 if (s_mask && a_mask) {
e98bedf5
EB		 2731 NL_SET_ERR_MSG_MOD(extack,
2732 "can't set and add to the same HW field");
61b6a6c3
CH		 2733 netdev_warn(priv->netdev,
2734 "mlx5: can't set and add to the same HW field (%x)\n",
2735 f->field);
d79b6df6
OG		 2736 return -EOPNOTSUPP;
2737 }
2738
27c11b6b 2739 skip = false;
d79b6df6 2740 if (s_mask) {
27c11b6b
EB		 2741 void *match_mask = headers_c + f->match_offset;
2742 void *match_val = headers_v + f->match_offset;
2743
d79b6df6
OG		 2744 cmd = MLX5_ACTION_TYPE_SET;
2745 mask = s_mask;
2746 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2747 /* don't rewrite if we have a match on the same value */
2748 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2749 match_mask, f->field_bsize))
27c11b6b 2750 skip = true;
d79b6df6 2751 /* clear to denote we consumed this field */
88f30bbc 2752 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2753 } else {
2754 cmd = MLX5_ACTION_TYPE_ADD;
2755 mask = a_mask;
2756 vals_p = (void *)add_vals + f->offset;
27c11b6b 2757 /* add 0 is no change */
88f30bbc 2758 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2759 skip = true;
d79b6df6 2760 /* clear to denote we consumed this field */
88f30bbc 2761 *a_masks_p &= ~f->field_mask;
d79b6df6 2762 }
27c11b6b
EB		 2763 if (skip)
2764 continue;
d79b6df6 2765
82198d8b 2766 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2767
88f30bbc
DL		 2768 first = find_first_bit(&mask, f->field_bsize);
2769 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2770 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2771 if (first < next_z && next_z < last) {
e98bedf5
EB		 2772 NL_SET_ERR_MSG_MOD(extack,
2773 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2774 netdev_warn(priv->netdev,
2775 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2776 mask);
d79b6df6
OG		 2777 return -EOPNOTSUPP;
2778 }
2779
6ae4a6a5
PB		 2780 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2781 if (err) {
2782 NL_SET_ERR_MSG_MOD(extack,
2783 "too many pedit actions, can't offload");
2784 mlx5_core_warn(priv->mdev,
2785 "mlx5: parsed %d pedit actions, can't do more\n",
2786 mod_acts->num_actions);
2787 return err;
2788 }
2789
2790 action = mod_acts->actions +
2791 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2792 MLX5_SET(set_action_in, action, action_type, cmd);
2793 MLX5_SET(set_action_in, action, field, f->field);
2794
2795 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2796 int start;
2797
82198d8b
MD		 2798 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2799
88f30bbc 2800 /* if field is bit sized it can start not from first bit */
82198d8b 2801 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2802
2803 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2804 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2805 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2806 }
2807
88f30bbc 2808 if (f->field_bsize == 32)
2b64beba 2809 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2810 else if (f->field_bsize == 16)
2b64beba 2811 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2812 else if (f->field_bsize == 8)
2b64beba 2813 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2814
6ae4a6a5 2815 ++mod_acts->num_actions;
d79b6df6
OG		 2816 }
2817
d79b6df6
OG		 2818 return 0;
2819}
2820
2cc1cb1d
TZ		 2821static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2822 int namespace)
2823{
2824 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2825 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2826 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2827 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2828}
2829
6ae4a6a5
PB		 2830int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2831 int namespace,
2832 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2833{
6ae4a6a5
PB		 2834 int action_size, new_num_actions, max_hw_actions;
2835 size_t new_sz, old_sz;
2836 void *ret;
d79b6df6 2837
6ae4a6a5
PB		 2838 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2839 return 0;
d79b6df6 2840
d65dbedf 2841 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2842
6ae4a6a5
PB		 2843 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2844 namespace);
2845 new_num_actions = min(max_hw_actions,
2846 mod_hdr_acts->actions ?
2847 mod_hdr_acts->max_actions * 2 : 1);
2848 if (mod_hdr_acts->max_actions == new_num_actions)
2849 return -ENOSPC;
2850
2851 new_sz = action_size * new_num_actions;
2852 old_sz = mod_hdr_acts->max_actions * action_size;
2853 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2854 if (!ret)
d79b6df6
OG		 2855 return -ENOMEM;
2856
6ae4a6a5
PB		 2857 memset(ret + old_sz, 0, new_sz - old_sz);
2858 mod_hdr_acts->actions = ret;
2859 mod_hdr_acts->max_actions = new_num_actions;
2860
d79b6df6
OG		 2861 return 0;
2862}
2863
6ae4a6a5
PB		 2864void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2865{
2866 kfree(mod_hdr_acts->actions);
2867 mod_hdr_acts->actions = NULL;
2868 mod_hdr_acts->num_actions = 0;
2869 mod_hdr_acts->max_actions = 0;
2870}
2871
d79b6df6
OG		 2872static const struct pedit_headers zero_masks = {};
2873
582234b4
EC		 2874static int
2875parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2876 const struct flow_action_entry *act, int namespace,
2877 struct mlx5e_tc_flow_parse_attr *parse_attr,
2878 struct pedit_headers_action *hdrs,
2879 struct netlink_ext_ack *extack)
d79b6df6 2880{
73867881
PNA		 2881 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2882 int err = -EOPNOTSUPP;
d79b6df6 2883 u32 mask, val, offset;
73867881 2884 u8 htype;
d79b6df6 2885
73867881
PNA		 2886 htype = act->mangle.htype;
2887 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2888
73867881
PNA		 2889 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2890 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2891 goto out_err;
2892 }
d79b6df6 2893
2cc1cb1d
TZ		 2894 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2895 NL_SET_ERR_MSG_MOD(extack,
2896 "The pedit offload action is not supported");
2897 goto out_err;
2898 }
2899
73867881
PNA		 2900 mask = act->mangle.mask;
2901 val = act->mangle.val;
2902 offset = act->mangle.offset;
d79b6df6 2903
73867881
PNA		 2904 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2905 if (err)
2906 goto out_err;
c500c86b 2907
73867881 2908 hdrs[cmd].pedits++;
d79b6df6 2909
c500c86b
PNA		 2910 return 0;
2911out_err:
2912 return err;
2913}
2914
582234b4
EC		 2915static int
2916parse_pedit_to_reformat(struct mlx5e_priv *priv,
2917 const struct flow_action_entry *act,
2918 struct mlx5e_tc_flow_parse_attr *parse_attr,
2919 struct netlink_ext_ack *extack)
2920{
2921 u32 mask, val, offset;
2922 u32 *p;
2923
2924 if (act->id != FLOW_ACTION_MANGLE)
2925 return -EOPNOTSUPP;
2926
2927 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2928 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2929 return -EOPNOTSUPP;
2930 }
2931
2932 mask = ~act->mangle.mask;
2933 val = act->mangle.val;
2934 offset = act->mangle.offset;
2935 p = (u32 *)&parse_attr->eth;
2936 *(p + (offset >> 2)) |= (val & mask);
2937
2938 return 0;
2939}
2940
2941static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2942 const struct flow_action_entry *act, int namespace,
2943 struct mlx5e_tc_flow_parse_attr *parse_attr,
2944 struct pedit_headers_action *hdrs,
2945 struct mlx5e_tc_flow *flow,
2946 struct netlink_ext_ack *extack)
2947{
2948 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2949 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2950
2951 return parse_pedit_to_modify_hdr(priv, act, namespace,
2952 parse_attr, hdrs, extack);
2953}
2954
c500c86b
PNA		 2955static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2956 struct mlx5e_tc_flow_parse_attr *parse_attr,
2957 struct pedit_headers_action *hdrs,
27c11b6b 2958 u32 *action_flags,
c500c86b
PNA		 2959 struct netlink_ext_ack *extack)
2960{
2961 struct pedit_headers *cmd_masks;
2962 int err;
2963 u8 cmd;
2964
6ae4a6a5
PB		 2965 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2966 action_flags, extack);
d79b6df6
OG		 2967 if (err < 0)
2968 goto out_dealloc_parsed_actions;
2969
2970 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2971 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2972 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2973 NL_SET_ERR_MSG_MOD(extack,
2974 "attempt to offload an unsupported field");
b3a433de 2975 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2976 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2977 16, 1, cmd_masks, sizeof(zero_masks), true);
2978 err = -EOPNOTSUPP;
2979 goto out_dealloc_parsed_actions;
2980 }
2981 }
2982
2983 return 0;
2984
2985out_dealloc_parsed_actions:
6ae4a6a5 2986 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2987 return err;
2988}
2989
e98bedf5
EB		 2990static bool csum_offload_supported(struct mlx5e_priv *priv,
2991 u32 action,
2992 u32 update_flags,
2993 struct netlink_ext_ack *extack)
26c02749
OG		 2994{
2995 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2996 TCA_CSUM_UPDATE_FLAG_UDP;
2997
2998 /* The HW recalcs checksums only if re-writing headers */
2999 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3000 NL_SET_ERR_MSG_MOD(extack,
3001 "TC csum action is only offloaded with pedit");
26c02749
OG		 3002 netdev_warn(priv->netdev,
3003 "TC csum action is only offloaded with pedit\n");
3004 return false;
3005 }
3006
3007 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3008 NL_SET_ERR_MSG_MOD(extack,
3009 "can't offload TC csum action for some header/s");
26c02749
OG		 3010 netdev_warn(priv->netdev,
3011 "can't offload TC csum action for some header/s - flags %#x\n",
3012 update_flags);
3013 return false;
3014 }
3015
3016 return true;
3017}
3018
8998576b
DL		 3019struct ip_ttl_word {
3020 __u8 ttl;
3021 __u8 protocol;
3022 __sum16 check;
3023};
3024
3025struct ipv6_hoplimit_word {
3026 __be16 payload_len;
3027 __u8 nexthdr;
3028 __u8 hop_limit;
3029};
3030
4c3844d9
PB		 3031static int is_action_keys_supported(const struct flow_action_entry *act,
3032 bool ct_flow, bool *modify_ip_header,
7e36feeb 3033 bool *modify_tuple,
4c3844d9 3034 struct netlink_ext_ack *extack)
8998576b
DL		 3035{
3036 u32 mask, offset;
3037 u8 htype;
3038
3039 htype = act->mangle.htype;
3040 offset = act->mangle.offset;
3041 mask = ~act->mangle.mask;
3042 /* For IPv4 & IPv6 header check 4 byte word,
3043 * to determine that modified fields
3044 * are NOT ttl & hop_limit only.
3045 */
3046 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3047 struct ip_ttl_word *ttl_word =
3048 (struct ip_ttl_word *)&mask;
3049
3050 if (offset != offsetof(struct iphdr, ttl) ||
3051 ttl_word->protocol ||
3052 ttl_word->check) {
4c3844d9
PB		 3053 *modify_ip_header = true;
3054 }
3055
7e36feeb
PB		 3056 if (offset >= offsetof(struct iphdr, saddr))
3057 *modify_tuple = true;
3058
3059 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3060 NL_SET_ERR_MSG_MOD(extack,
3061 "can't offload re-write of ipv4 address with action ct");
3062 return -EOPNOTSUPP;
8998576b
DL		 3063 }
3064 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3065 struct ipv6_hoplimit_word *hoplimit_word =
3066 (struct ipv6_hoplimit_word *)&mask;
3067
3068 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3069 hoplimit_word->payload_len ||
3070 hoplimit_word->nexthdr) {
4c3844d9
PB		 3071 *modify_ip_header = true;
3072 }
3073
7e36feeb
PB		 3074 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3075 *modify_tuple = true;
3076
3077 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3078 NL_SET_ERR_MSG_MOD(extack,
3079 "can't offload re-write of ipv6 address with action ct");
3080 return -EOPNOTSUPP;
8998576b 3081 }
7e36feeb
PB		 3082 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3083 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3084 *modify_tuple = true;
3085 if (ct_flow) {
3086 NL_SET_ERR_MSG_MOD(extack,
3087 "can't offload re-write of transport header ports with action ct");
3088 return -EOPNOTSUPP;
3089 }
8998576b 3090 }
4c3844d9
PB		 3091
3092 return 0;
8998576b
DL		 3093}
3094
96b5b458
DC		 3095static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3096 bool ct_flow, struct netlink_ext_ack *extack,
3097 struct mlx5e_priv *priv,
3098 struct mlx5_flow_spec *spec)
3099{
3100 if (!modify_tuple || ct_clear)
3101 return true;
3102
3103 if (ct_flow) {
3104 NL_SET_ERR_MSG_MOD(extack,
3105 "can't offload tuple modification with non-clear ct()");
3106 netdev_info(priv->netdev,
3107 "can't offload tuple modification with non-clear ct()");
3108 return false;
3109 }
3110
3111 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3112 * (or after clear action), as otherwise, since the tuple is changed,
3113 * we can't restore ct state
3114 */
3115 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3116 NL_SET_ERR_MSG_MOD(extack,
3117 "can't offload tuple modification with ct matches and no ct(clear) action");
3118 netdev_info(priv->netdev,
3119 "can't offload tuple modification with ct matches and no ct(clear) action");
3120 return false;
3121 }
3122
3123 return true;
3124}
3125
3d486ec4
OS		 3126static bool modify_header_match_supported(struct mlx5e_priv *priv,
3127 struct mlx5_flow_spec *spec,
73867881 3128 struct flow_action *flow_action,
4c3844d9 3129 u32 actions, bool ct_flow,
7e36feeb 3130 bool ct_clear,
e98bedf5 3131 struct netlink_ext_ack *extack)
bdd66ac0 3132{
73867881 3133 const struct flow_action_entry *act;
7e36feeb 3134 bool modify_ip_header, modify_tuple;
fca53304 3135 void *headers_c;
bdd66ac0
OG		 3136 void *headers_v;
3137 u16 ethertype;
8998576b 3138 u8 ip_proto;
4c3844d9 3139 int i, err;
bdd66ac0 3140
fca53304 3141 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3142 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3143 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3144
3145 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3146 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3147 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3148 goto out_ok;
3149
3150 modify_ip_header = false;
7e36feeb 3151 modify_tuple = false;
73867881
PNA		 3152 flow_action_for_each(i, act, flow_action) {
3153 if (act->id != FLOW_ACTION_MANGLE &&
3154 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3155 continue;
3156
4c3844d9 3157 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3158 &modify_ip_header,
3159 &modify_tuple, extack);
4c3844d9
PB		 3160 if (err)
3161 return err;
bdd66ac0
OG		 3162 }
3163
96b5b458
DC		 3164 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3165 priv, spec))
7e36feeb 3166 return false;
7e36feeb 3167
bdd66ac0 3168 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3169 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3170 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3171 NL_SET_ERR_MSG_MOD(extack,
3172 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3173 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3174 ip_proto);
bdd66ac0
OG		 3175 return false;
3176 }
3177
3178out_ok:
3179 return true;
3180}
3181
3182static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3183 struct flow_action *flow_action,
bdd66ac0 3184 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3185 struct mlx5e_tc_flow *flow,
3186 struct netlink_ext_ack *extack)
bdd66ac0 3187{
a7c119bd 3188 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3189 u32 actions;
3190
c620b772
AL		 3191 ct_clear = flow->attr->ct_attr.ct_action &
3192 TCA_CT_ACT_CLEAR;
3193 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3194 actions = flow->attr->action;
3195
4c3844d9 3196 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3197 if (flow->attr->esw_attr->split_count && ct_flow &&
3198 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3199 /* All registers used by ct are cleared when using
3200 * split rules.
3201 */
3202 NL_SET_ERR_MSG_MOD(extack,
3203 "Can't offload mirroring with action ct");
49397b80 3204 return false;
4c3844d9 3205 }
4c3844d9 3206 }
bdd66ac0
OG		 3207
3208 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3209 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3210 flow_action, actions,
7e36feeb
PB		 3211 ct_flow, ct_clear,
3212 extack);
bdd66ac0
OG		 3213
3214 return true;
3215}
3216
32134847
MD		 3217static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3218{
3219 return priv->mdev == peer_priv->mdev;
3220}
3221
5c65c564
OG		 3222static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3223{
3224 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3225 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3226
3227 fmdev = priv->mdev;
3228 pmdev = peer_priv->mdev;
3229
59c9d35e
AH		 3230 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3231 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3232
816f6706 3233 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3234}
3235
bb569657
AL		 3236static bool same_vf_reps(struct mlx5e_priv *priv,
3237 struct net_device *out_dev)
3238{
3239 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3240 priv->netdev == out_dev;
3241}
3242
bdc837ee
EB		 3243static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3244 const struct flow_action_entry *act,
3245 struct mlx5e_tc_flow_parse_attr *parse_attr,
3246 struct pedit_headers_action *hdrs,
3247 u32 *action, struct netlink_ext_ack *extack)
3248{
3249 u16 mask16 = VLAN_VID_MASK;
3250 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3251 const struct flow_action_entry pedit_act = {
3252 .id = FLOW_ACTION_MANGLE,
3253 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3254 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3255 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3256 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3257 };
6fca9d1e 3258 u8 match_prio_mask, match_prio_val;
bf2f3bca 3259 void *headers_c, *headers_v;
bdc837ee
EB		 3260 int err;
3261
bf2f3bca
EB		 3262 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3263 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3264
3265 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3266 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3267 NL_SET_ERR_MSG_MOD(extack,
3268 "VLAN rewrite action must have VLAN protocol match");
3269 return -EOPNOTSUPP;
3270 }
3271
6fca9d1e
EB		 3272 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3273 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3274 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3275 NL_SET_ERR_MSG_MOD(extack,
3276 "Changing VLAN prio is not supported");
bdc837ee
EB		 3277 return -EOPNOTSUPP;
3278 }
3279
582234b4 3280 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3281 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3282
3283 return err;
3284}
3285
0bac1194
EB		 3286static int
3287add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3288 struct mlx5e_tc_flow_parse_attr *parse_attr,
3289 struct pedit_headers_action *hdrs,
3290 u32 *action, struct netlink_ext_ack *extack)
3291{
3292 const struct flow_action_entry prio_tag_act = {
3293 .vlan.vid = 0,
3294 .vlan.prio =
3295 MLX5_GET(fte_match_set_lyr_2_4,
3296 get_match_headers_value(*action,
3297 &parse_attr->spec),
3298 first_prio) &
3299 MLX5_GET(fte_match_set_lyr_2_4,
3300 get_match_headers_criteria(*action,
3301 &parse_attr->spec),
3302 first_prio),
3303 };
3304
3305 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3306 &prio_tag_act, parse_attr, hdrs, action,
3307 extack);
3308}
3309
c7569097
AL		 3310static int validate_goto_chain(struct mlx5e_priv *priv,
3311 struct mlx5e_tc_flow *flow,
3312 const struct flow_action_entry *act,
3313 u32 actions,
3314 struct netlink_ext_ack *extack)
3315{
3316 bool is_esw = mlx5e_is_eswitch_flow(flow);
3317 struct mlx5_flow_attr *attr = flow->attr;
3318 bool ft_flow = mlx5e_is_ft_flow(flow);
3319 u32 dest_chain = act->chain_index;
3320 struct mlx5_fs_chains *chains;
3321 struct mlx5_eswitch *esw;
3322 u32 reformat_and_fwd;
3323 u32 max_chain;
3324
3325 esw = priv->mdev->priv.eswitch;
3326 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3327 max_chain = mlx5_chains_get_chain_range(chains);
3328 reformat_and_fwd = is_esw ?
3329 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3330 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3331
3332 if (ft_flow) {
3333 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3334 return -EOPNOTSUPP;
3335 }
3336
3337 if (!mlx5_chains_backwards_supported(chains) &&
3338 dest_chain <= attr->chain) {
3339 NL_SET_ERR_MSG_MOD(extack,
3340 "Goto lower numbered chain isn't supported");
3341 return -EOPNOTSUPP;
3342 }
3343
3344 if (dest_chain > max_chain) {
3345 NL_SET_ERR_MSG_MOD(extack,
3346 "Requested destination chain is out of supported range");
3347 return -EOPNOTSUPP;
3348 }
3349
3350 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3351 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3352 !reformat_and_fwd) {
3353 NL_SET_ERR_MSG_MOD(extack,
3354 "Goto chain is not allowed if action has reformat or decap");
3355 return -EOPNOTSUPP;
3356 }
3357
3358 return 0;
3359}
3360
73867881
PNA		 3361static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3362 struct flow_action *flow_action,
e98bedf5
EB		 3363 struct mlx5e_tc_flow *flow,
3364 struct netlink_ext_ack *extack)
e3a2b7ed 3365{
c6cfe113 3366 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3367 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3368 struct pedit_headers_action hdrs[2] = {};
3369 const struct flow_action_entry *act;
c620b772 3370 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3371 u32 action = 0;
244cd96a 3372 int err, i;
e3a2b7ed 3373
73867881 3374 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3375 return -EINVAL;
3376
53eca1f3
JK		 3377 if (!flow_action_hw_stats_check(flow_action, extack,
3378 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3379 return -EOPNOTSUPP;
3380
c620b772 3381 nic_attr = attr->nic_attr;
c620b772 3382 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3383 parse_attr = attr->parse_attr;
e3a2b7ed 3384
73867881
PNA		 3385 flow_action_for_each(i, act, flow_action) {
3386 switch (act->id) {
15fc92ec
TZ		 3387 case FLOW_ACTION_ACCEPT:
3388 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3389 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3390 break;
73867881 3391 case FLOW_ACTION_DROP:
950b4df9
RD		 3392 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3393 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3394 break;
3395 case FLOW_ACTION_MANGLE:
3396 case FLOW_ACTION_ADD:
3397 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3398 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3399 if (err)
3400 return err;
3401
c7569097 3402 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3403 break;
bdc837ee
EB		 3404 case FLOW_ACTION_VLAN_MANGLE:
3405 err = add_vlan_rewrite_action(priv,
3406 MLX5_FLOW_NAMESPACE_KERNEL,
3407 act, parse_attr, hdrs,
3408 &action, extack);
3409 if (err)
3410 return err;
3411
3412 break;
73867881 3413 case FLOW_ACTION_CSUM:
1cab1cd7 3414 if (csum_offload_supported(priv, action,
73867881 3415 act->csum_flags,
e98bedf5 3416 extack))
73867881 3417 break;
26c02749
OG		 3418
3419 return -EOPNOTSUPP;
73867881
PNA		 3420 case FLOW_ACTION_REDIRECT: {
3421 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3422
3423 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3424 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3425 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3426 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3427 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3428 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3429 } else {
e98bedf5
EB		 3430 NL_SET_ERR_MSG_MOD(extack,
3431 "device is not on same HW, can't offload");
5c65c564
OG		 3432 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3433 peer_dev->name);
25f150f4 3434 return -EOPNOTSUPP;
5c65c564 3435 }
73867881
PNA		 3436 }
3437 break;
3438 case FLOW_ACTION_MARK: {
3439 u32 mark = act->mark;
e3a2b7ed
AV		 3440
3441 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3442 NL_SET_ERR_MSG_MOD(extack,
3443 "Bad flow mark - only 16 bit is supported");
25f150f4 3444 return -EOPNOTSUPP;
e3a2b7ed
AV		 3445 }
3446
c620b772 3447 nic_attr->flow_tag = mark;
1cab1cd7 3448 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3449 }
3450 break;
c7569097
AL		 3451 case FLOW_ACTION_GOTO:
3452 err = validate_goto_chain(priv, flow, act, action,
3453 extack);
3454 if (err)
3455 return err;
3456
3457 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3458 attr->dest_chain = act->chain_index;
3459 break;
aedd133d
AL		 3460 case FLOW_ACTION_CT:
3461 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3462 if (err)
3463 return err;
3464
3465 flow_flag_set(flow, CT);
3466 break;
73867881 3467 default:
2cc1cb1d
TZ		 3468 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3469 return -EOPNOTSUPP;
e3a2b7ed 3470 }
e3a2b7ed
AV		 3471 }
3472
c500c86b
PNA		 3473 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3474 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3475 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3476 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3477 if (err)
3478 return err;
27c11b6b
EB		 3479 /* in case all pedit actions are skipped, remove the MOD_HDR
3480 * flag.
3481 */
6ae4a6a5 3482 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3483 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3484 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3485 }
c500c86b
PNA		 3486 }
3487
1cab1cd7 3488 attr->action = action;
c7569097
AL		 3489
3490 if (attr->dest_chain) {
3491 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3492 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3493 return -EOPNOTSUPP;
3494 }
3495 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3496 }
3497
3498 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3499 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3500
73867881 3501 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3502 return -EOPNOTSUPP;
3503
e3a2b7ed
AV		 3504 return 0;
3505}
3506
32134847 3507static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3508 struct net_device *peer_netdev)
3509{
3510 struct mlx5e_priv *peer_priv;
3511
3512 peer_priv = netdev_priv(peer_netdev);
3513
3514 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3515 mlx5e_eswitch_vf_rep(priv->netdev) &&
3516 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3517 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3518}
3519
1482bd3d 3520static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3521 const struct flow_action_entry *act,
1482bd3d
JL		 3522 struct mlx5_esw_flow_attr *attr,
3523 u32 *action)
3524{
cc495188
JL		 3525 u8 vlan_idx = attr->total_vlan;
3526
3527 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3528 return -EOPNOTSUPP;
3529
73867881
PNA		 3530 switch (act->id) {
3531 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3532 if (vlan_idx) {
3533 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3534 MLX5_FS_VLAN_DEPTH))
3535 return -EOPNOTSUPP;
3536
3537 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3538 } else {
3539 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3540 }
73867881
PNA		 3541 break;
3542 case FLOW_ACTION_VLAN_PUSH:
3543 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3544 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3545 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3546 if (!attr->vlan_proto[vlan_idx])
3547 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3548
3549 if (vlan_idx) {
3550 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3551 MLX5_FS_VLAN_DEPTH))
3552 return -EOPNOTSUPP;
3553
3554 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3555 } else {
3556 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3557 (act->vlan.proto != htons(ETH_P_8021Q) ||
3558 act->vlan.prio))
cc495188
JL		 3559 return -EOPNOTSUPP;
3560
3561 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3562 }
73867881
PNA		 3563 break;
3564 default:
bdc837ee 3565 return -EINVAL;
1482bd3d
JL		 3566 }
3567
cc495188
JL		 3568 attr->total_vlan = vlan_idx + 1;
3569
1482bd3d
JL		 3570 return 0;
3571}
3572
d34eb2fc
OG		 3573static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3574 struct net_device *out_dev)
3575{
3576 struct net_device *fdb_out_dev = out_dev;
3577 struct net_device *uplink_upper;
3578
3579 rcu_read_lock();
3580 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3581 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3582 uplink_upper == out_dev) {
3583 fdb_out_dev = uplink_dev;
3584 } else if (netif_is_lag_master(out_dev)) {
3585 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3586 if (fdb_out_dev &&
3587 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3588 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3589 fdb_out_dev = NULL;
3590 }
3591 rcu_read_unlock();
3592 return fdb_out_dev;
3593}
3594
278748a9 3595static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3596 struct mlx5_flow_attr *attr,
278748a9
EB		 3597 struct net_device **out_dev,
3598 u32 *action)
3599{
3600 struct net_device *vlan_dev = *out_dev;
3601 struct flow_action_entry vlan_act = {
3602 .id = FLOW_ACTION_VLAN_PUSH,
3603 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3604 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3605 .vlan.prio = 0,
3606 };
3607 int err;
3608
c620b772 3609 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3610 if (err)
3611 return err;
3612
dca59f4a
DC		 3613 rcu_read_lock();
3614 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3615 rcu_read_unlock();
3616 if (!*out_dev)
3617 return -ENODEV;
3618
278748a9
EB		 3619 if (is_vlan_dev(*out_dev))
3620 err = add_vlan_push_action(priv, attr, out_dev, action);
3621
3622 return err;
3623}
3624
35a605db 3625static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3626 struct mlx5_flow_attr *attr,
35a605db
EB		 3627 u32 *action)
3628{
35a605db
EB		 3629 struct flow_action_entry vlan_act = {
3630 .id = FLOW_ACTION_VLAN_POP,
3631 };
70f478ca 3632 int nest_level, err = 0;
35a605db 3633
70f478ca
DL		 3634 nest_level = attr->parse_attr->filter_dev->lower_level -
3635 priv->netdev->lower_level;
35a605db 3636 while (nest_level--) {
c620b772 3637 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3638 if (err)
3639 return err;
3640 }
3641
3642 return err;
3643}
3644
32134847
MD		 3645static bool same_hw_reps(struct mlx5e_priv *priv,
3646 struct net_device *peer_netdev)
3647{
3648 struct mlx5e_priv *peer_priv;
3649
3650 peer_priv = netdev_priv(peer_netdev);
3651
3652 return mlx5e_eswitch_rep(priv->netdev) &&
3653 mlx5e_eswitch_rep(peer_netdev) &&
3654 same_hw_devs(priv, peer_priv);
3655}
3656
3657static bool is_lag_dev(struct mlx5e_priv *priv,
3658 struct net_device *peer_netdev)
3659{
3660 return ((mlx5_lag_is_sriov(priv->mdev) ||
3661 mlx5_lag_is_multipath(priv->mdev)) &&
3662 same_hw_reps(priv, peer_netdev));
3663}
3664
f6dc1264
PB		 3665bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3666 struct net_device *out_dev)
3667{
32134847
MD		 3668 if (is_merged_eswitch_vfs(priv, out_dev))
3669 return true;
3670
3671 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3672 return true;
3673
3674 return mlx5e_eswitch_rep(out_dev) &&
32134847 3675 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3676}
3677
554fe75c
DL		 3678static bool is_duplicated_output_device(struct net_device *dev,
3679 struct net_device *out_dev,
3680 int *ifindexes, int if_count,
3681 struct netlink_ext_ack *extack)
3682{
3683 int i;
3684
3685 for (i = 0; i < if_count; i++) {
3686 if (ifindexes[i] == out_dev->ifindex) {
3687 NL_SET_ERR_MSG_MOD(extack,
3688 "can't duplicate output to same device");
3689 netdev_err(dev, "can't duplicate output to same device: %s\n",
3690 out_dev->name);
3691 return true;
3692 }
3693 }
3694
3695 return false;
3696}
3697
613f53fe
EC		 3698static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3699 struct mlx5e_tc_flow *flow,
3700 struct net_device *out_dev,
3701 struct netlink_ext_ack *extack)
3702{
c620b772 3703 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3704 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3705 struct mlx5e_rep_priv *rep_priv;
3706
3707 /* Forwarding non encapsulated traffic between
3708 * uplink ports is allowed only if
3709 * termination_table_raw_traffic cap is set.
3710 *
c620b772 3711 * Input vport was stored attr->in_rep.
613f53fe
EC		 3712 * In LAG case, *priv* is the private data of
3713 * uplink which may be not the input vport.
3714 */
3715 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3716
3717 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3718 mlx5e_eswitch_uplink_rep(out_dev)))
3719 return 0;
3720
3721 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3722 termination_table_raw_traffic)) {
3723 NL_SET_ERR_MSG_MOD(extack,
3724 "devices are both uplink, can't offload forwarding");
3725 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3726 priv->netdev->name, out_dev->name);
3727 return -EOPNOTSUPP;
3728 } else if (out_dev != rep_priv->netdev) {
3729 NL_SET_ERR_MSG_MOD(extack,
3730 "devices are not the same uplink, can't offload forwarding");
3731 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3732 priv->netdev->name, out_dev->name);
3733 return -EOPNOTSUPP;
3734 }
3735 return 0;
3736}
3737
73867881
PNA		 3738static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3739 struct flow_action *flow_action,
e98bedf5 3740 struct mlx5e_tc_flow *flow,
70f8019e 3741 struct netlink_ext_ack *extack)
03a9d11e 3742{
73867881 3743 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3744 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3745 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3746 struct mlx5e_rep_priv *rpriv = priv->ppriv;
bcd6740c 3747 struct mlx5e_sample_attr sample_attr = {};
73867881 3748 const struct ip_tunnel_info *info = NULL;
c620b772 3749 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3750 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3751 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3752 const struct flow_action_entry *act;
c620b772 3753 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 3754 bool encap = false, decap = false;
3755 u32 action = attr->action;
554fe75c 3756 int err, i, if_count = 0;
f828ca6a 3757 bool mpls_push = false;
03a9d11e 3758
73867881 3759 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3760 return -EINVAL;
3761
53eca1f3
JK		 3762 if (!flow_action_hw_stats_check(flow_action, extack,
3763 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3764 return -EOPNOTSUPP;
3765
c620b772
AL		 3766 esw_attr = attr->esw_attr;
3767 parse_attr = attr->parse_attr;
3768
73867881
PNA		 3769 flow_action_for_each(i, act, flow_action) {
3770 switch (act->id) {
3771 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3772 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3773 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3774 break;
f0288210
EC		 3775 case FLOW_ACTION_TRAP:
3776 if (!flow_offload_has_one_action(flow_action)) {
3777 NL_SET_ERR_MSG_MOD(extack,
3778 "action trap is supported as a sole action only");
3779 return -EOPNOTSUPP;
3780 }
3781 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3782 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3783 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3784 break;
f828ca6a
EC		 3785 case FLOW_ACTION_MPLS_PUSH:
3786 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3787 reformat_l2_to_l3_tunnel) ||
3788 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3789 NL_SET_ERR_MSG_MOD(extack,
3790 "mpls push is supported only for mpls_uc protocol");
3791 return -EOPNOTSUPP;
3792 }
3793 mpls_push = true;
3794 break;
14e6b038
EC		 3795 case FLOW_ACTION_MPLS_POP:
3796 /* we only support mpls pop if it is the first action
3797 * and the filter net device is bareudp. Subsequent
3798 * actions can be pedit and the last can be mirred
3799 * egress redirect.
3800 */
3801 if (i) {
3802 NL_SET_ERR_MSG_MOD(extack,
3803 "mpls pop supported only as first action");
3804 return -EOPNOTSUPP;
3805 }
70f8019e 3806 if (!netif_is_bareudp(parse_attr->filter_dev)) {
14e6b038
EC		 3807 NL_SET_ERR_MSG_MOD(extack,
3808 "mpls pop supported only on bareudp devices");
3809 return -EOPNOTSUPP;
3810 }
3811
3812 parse_attr->eth.h_proto = act->mpls_pop.proto;
3813 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3814 flow_flag_set(flow, L3_TO_L2_DECAP);
3815 break;
73867881
PNA		 3816 case FLOW_ACTION_MANGLE:
3817 case FLOW_ACTION_ADD:
3818 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3819 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3820 if (err)
3821 return err;
3822
582234b4
EC		 3823 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3824 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3825 esw_attr->split_count = esw_attr->out_count;
582234b4 3826 }
73867881
PNA		 3827 break;
3828 case FLOW_ACTION_CSUM:
1cab1cd7 3829 if (csum_offload_supported(priv, action,
73867881
PNA		 3830 act->csum_flags, extack))
3831 break;
26c02749
OG		 3832
3833 return -EOPNOTSUPP;
73867881
PNA		 3834 case FLOW_ACTION_REDIRECT:
3835 case FLOW_ACTION_MIRRED: {
03a9d11e 3836 struct mlx5e_priv *out_priv;
592d3651 3837 struct net_device *out_dev;
03a9d11e 3838
73867881 3839 out_dev = act->dev;
ef381359
OS		 3840 if (!out_dev) {
3841 /* out_dev is NULL when filters with
3842 * non-existing mirred device are replayed to
3843 * the driver.
3844 */
3845 return -EINVAL;
3846 }
03a9d11e 3847
f828ca6a
EC		 3848 if (mpls_push && !netif_is_bareudp(out_dev)) {
3849 NL_SET_ERR_MSG_MOD(extack,
3850 "mpls is supported only through a bareudp device");
3851 return -EOPNOTSUPP;
3852 }
3853
84179981
PB		 3854 if (ft_flow && out_dev == priv->netdev) {
3855 /* Ignore forward to self rules generated
3856 * by adding both mlx5 devs to the flow table
3857 * block on a normal nft offload setup.
3858 */
3859 return -EOPNOTSUPP;
3860 }
3861
c620b772 3862 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3863 NL_SET_ERR_MSG_MOD(extack,
3864 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3865 netdev_warn(priv->netdev,
3866 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3867 esw_attr->out_count);
592d3651
CM		 3868 return -EOPNOTSUPP;
3869 }
3870
f493f155
EB		 3871 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3872 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3873 if (encap) {
c620b772 3874 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3875 out_dev->ifindex;
0d9f9647
VB		 3876 parse_attr->tun_info[esw_attr->out_count] =
3877 mlx5e_dup_tun_info(info);
c620b772 3878 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3879 return -ENOMEM;
3880 encap = false;
c620b772 3881 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3882 MLX5_ESW_DEST_ENCAP;
c620b772 3883 esw_attr->out_count++;
b6a4ac24
VB		 3884 /* attr->dests[].rep is resolved when we
3885 * handle encap
3886 */
3887 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3888 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3889 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3890
554fe75c
DL		 3891 if (is_duplicated_output_device(priv->netdev,
3892 out_dev,
3893 ifindexes,
3894 if_count,
3895 extack))
3896 return -EOPNOTSUPP;
3897
3898 ifindexes[if_count] = out_dev->ifindex;
3899 if_count++;
3900
d34eb2fc
OG		 3901 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3902 if (!out_dev)
3903 return -ENODEV;
7ba58ba7 3904
278748a9
EB		 3905 if (is_vlan_dev(out_dev)) {
3906 err = add_vlan_push_action(priv, attr,
3907 &out_dev,
3908 &action);
3909 if (err)
3910 return err;
3911 }
f6dc1264 3912
35a605db
EB		 3913 if (is_vlan_dev(parse_attr->filter_dev)) {
3914 err = add_vlan_pop_action(priv, attr,
3915 &action);
3916 if (err)
3917 return err;
3918 }
278748a9 3919
613f53fe
EC		 3920 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3921 if (err)
3922 return err;
ffec9702 3923
f6dc1264
PB		 3924 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3925 NL_SET_ERR_MSG_MOD(extack,
3926 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3927 return -EOPNOTSUPP;
f6dc1264 3928 }
a0646c88 3929
bb569657
AL		 3930 if (same_vf_reps(priv, out_dev)) {
3931 NL_SET_ERR_MSG_MOD(extack,
3932 "can't forward from a VF to itself");
3933 return -EOPNOTSUPP;
3934 }
3935
a54e20b4 3936 out_priv = netdev_priv(out_dev);
1d447a39 3937 rpriv = out_priv->ppriv;
c620b772
AL		 3938 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3939 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3940 esw_attr->out_count++;
ef381359
OS		 3941 } else if (parse_attr->filter_dev != priv->netdev) {
3942 /* All mlx5 devices are called to configure
3943 * high level device filters. Therefore, the
3944 * *attempt* to install a filter on invalid
3945 * eswitch should not trigger an explicit error
3946 */
3947 return -EINVAL;
a54e20b4 3948 } else {
e98bedf5
EB		 3949 NL_SET_ERR_MSG_MOD(extack,
3950 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3951 netdev_warn(priv->netdev,
3952 "devices %s %s not on same switch HW, can't offload forwarding\n",
3953 priv->netdev->name,
3954 out_dev->name);
25f150f4 3955 return -EOPNOTSUPP;
03a9d11e 3956 }
73867881
PNA		 3957 }
3958 break;
3959 case FLOW_ACTION_TUNNEL_ENCAP:
3960 info = act->tunnel;
a54e20b4
HHZ		 3961 if (info)
3962 encap = true;
3963 else
3964 return -EOPNOTSUPP;
1482bd3d 3965
73867881
PNA		 3966 break;
3967 case FLOW_ACTION_VLAN_PUSH:
3968 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3969 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3970 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3971 /* Replace vlan pop+push with vlan modify */
3972 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3973 err = add_vlan_rewrite_action(priv,
3974 MLX5_FLOW_NAMESPACE_FDB,
3975 act, parse_attr, hdrs,
3976 &action, extack);
3977 } else {
c620b772 3978 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3979 }
1482bd3d
JL		 3980 if (err)
3981 return err;
3982
c620b772 3983 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3984 break;
3985 case FLOW_ACTION_VLAN_MANGLE:
3986 err = add_vlan_rewrite_action(priv,
3987 MLX5_FLOW_NAMESPACE_FDB,
3988 act, parse_attr, hdrs,
3989 &action, extack);
3990 if (err)
3991 return err;
3992
c620b772 3993 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3994 break;
3995 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3996 decap = true;
73867881 3997 break;
2fbbc30d 3998 case FLOW_ACTION_GOTO:
c7569097
AL		 3999 err = validate_goto_chain(priv, flow, act, action,
4000 extack);
2fbbc30d
EC		 4001 if (err)
4002 return err;
bf07aa73 4003
e88afe75 4004 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4005 attr->dest_chain = act->chain_index;
73867881 4006 break;
4c3844d9 4007 case FLOW_ACTION_CT:
41c2fd94
CM		 4008 if (flow_flag_test(flow, SAMPLE)) {
4009 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4010 return -EOPNOTSUPP;
4011 }
aedd133d 4012 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4013 if (err)
4014 return err;
4015
4016 flow_flag_set(flow, CT);
69e2916e 4017 esw_attr->split_count = esw_attr->out_count;
4c3844d9 4018 break;
41c2fd94
CM		 4019 case FLOW_ACTION_SAMPLE:
4020 if (flow_flag_test(flow, CT)) {
4021 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4022 return -EOPNOTSUPP;
4023 }
bcd6740c
CM		 4024 sample_attr.rate = act->sample.rate;
4025 sample_attr.group_num = act->sample.psample_group->group_num;
41c2fd94 4026 if (act->sample.truncate)
bcd6740c 4027 sample_attr.trunc_size = act->sample.trunc_size;
41c2fd94
CM		 4028 flow_flag_set(flow, SAMPLE);
4029 break;
73867881 4030 default:
2cc1cb1d
TZ		 4031 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4032 return -EOPNOTSUPP;
bf07aa73 4033 }
03a9d11e 4034 }
bdd66ac0 4035
a508728a
VB		 4036 /* always set IP version for indirect table handling */
4037 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4038
0bac1194
EB		 4039 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4040 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4041 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4042 * tag rewrite.
4043 */
4044 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4045 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4046 &action, extack);
4047 if (err)
4048 return err;
4049 }
4050
c500c86b
PNA		 4051 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4052 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4053 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4054 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4055 if (err)
4056 return err;
27c11b6b
EB		 4057 /* in case all pedit actions are skipped, remove the MOD_HDR
4058 * flag. we might have set split_count either by pedit or
4059 * pop/push. if there is no pop/push either, reset it too.
4060 */
6ae4a6a5 4061 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4062 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4063 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4064 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4065 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4066 esw_attr->split_count = 0;
27c11b6b 4067 }
c500c86b
PNA		 4068 }
4069
1cab1cd7 4070 attr->action = action;
73867881 4071 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4072 return -EOPNOTSUPP;
4073
e88afe75 4074 if (attr->dest_chain) {
0a7fcb78
PB		 4075 if (decap) {
4076 /* It can be supported if we'll create a mapping for
4077 * the tunnel device only (without tunnel), and set
4078 * this tunnel id with this decap flow.
4079 *
4080 * On restore (miss), we'll just set this saved tunnel
4081 * device.
4082 */
4083
4084 NL_SET_ERR_MSG(extack,
4085 "Decap with goto isn't supported");
4086 netdev_warn(priv->netdev,
4087 "Decap with goto isn't supported");
4088 return -EOPNOTSUPP;
4089 }
4090
e88afe75
OG		 4091 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4092 }
4093
ae2741e2
VB		 4094 if (!(attr->action &
4095 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4096 NL_SET_ERR_MSG_MOD(extack,
4097 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4098 return -EOPNOTSUPP;
4099 }
4100
c620b772 4101 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4102 NL_SET_ERR_MSG_MOD(extack,
4103 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4104 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4105 return -EOPNOTSUPP;
4106 }
4107
41c2fd94
CM		 4108 /* Allocate sample attribute only when there is a sample action and
4109 * no errors after parsing.
4110 */
4111 if (flow_flag_test(flow, SAMPLE)) {
bcd6740c
CM		 4112 attr->sample_attr = kzalloc(sizeof(*attr->sample_attr), GFP_KERNEL);
4113 if (!attr->sample_attr)
41c2fd94 4114 return -ENOMEM;
bcd6740c 4115 *attr->sample_attr = sample_attr;
41c2fd94
CM		 4116 }
4117
31c8eba5 4118 return 0;
03a9d11e
OG		 4119}
4120
226f2ca3 4121static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4122{
226f2ca3 4123 unsigned long __flow_flags = 0;
60bd4af8 4124
226f2ca3
VB		 4125 if (flags & MLX5_TC_FLAG(INGRESS))
4126 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4127 if (flags & MLX5_TC_FLAG(EGRESS))
4128 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4129
226f2ca3
VB		 4130 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4131 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4132 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4133 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4134 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4135 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4136
60bd4af8
OG		 4137 *flow_flags = __flow_flags;
4138}
4139
05866c82
OG		 4140static const struct rhashtable_params tc_ht_params = {
4141 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4142 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4143 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4144 .automatic_shrinking = true,
4145};
4146
226f2ca3
VB		 4147static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4148 unsigned long flags)
05866c82 4149{
655dc3d2
OG		 4150 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4151 struct mlx5e_rep_priv *uplink_rpriv;
4152
226f2ca3 4153 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4154 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4155 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4156 } else /* NIC offload */
655dc3d2 4157 return &priv->fs.tc.ht;
05866c82
OG		 4158}
4159
04de7dda
RD		 4160static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4161{
c620b772
AL		 4162 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4163 struct mlx5_flow_attr *attr = flow->attr;
4164 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4165 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4166 bool act_is_encap = !!(attr->action &
4167 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4168 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4169 MLX5_DEVCOM_ESW_OFFLOADS);
4170
10fbb1cd
RD		 4171 if (!esw_paired)
4172 return false;
4173
c620b772
AL		 4174 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4175 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4176 (is_rep_ingress || act_is_encap))
4177 return true;
4178
4179 return false;
04de7dda
RD		 4180}
4181
c620b772
AL		 4182struct mlx5_flow_attr *
4183mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4184{
4185 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4186 sizeof(struct mlx5_esw_flow_attr) :
4187 sizeof(struct mlx5_nic_flow_attr);
4188 struct mlx5_flow_attr *attr;
4189
4190 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4191}
4192
a88780a9
RD		 4193static int
4194mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4195 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4196 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4197 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4198{
17091853 4199 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4200 struct mlx5_flow_attr *attr;
3bc4b7bf 4201 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4202 int err = -ENOMEM;
4203 int out_index;
e3a2b7ed 4204
c620b772 4205 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4206 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4207 if (!parse_attr || !flow)
4208 goto err_free;
c620b772
AL		 4209
4210 flow->flags = flow_flags;
4211 flow->cookie = f->cookie;
4212 flow->priv = priv;
4213
4214 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4215 if (!attr)
e3a2b7ed 4216 goto err_free;
ff7ea04a 4217
c620b772 4218 flow->attr = attr;
e3a2b7ed 4219
5a7e5bcb
VB		 4220 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4221 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4222 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4223 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4224 refcount_set(&flow->refcnt, 1);
95435ad7 4225 init_completion(&flow->init_done);
909e615d 4226 init_completion(&flow->del_hw_done);
e3a2b7ed 4227
a88780a9
RD		 4228 *__flow = flow;
4229 *__parse_attr = parse_attr;
4230
4231 return 0;
4232
4233err_free:
4234 kfree(flow);
4235 kvfree(parse_attr);
4236 return err;
4237}
4238
c7569097
AL		 4239static void
4240mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4241 struct mlx5e_tc_flow_parse_attr *parse_attr,
4242 struct flow_cls_offload *f)
4243{
4244 attr->parse_attr = parse_attr;
4245 attr->chain = f->common.chain_index;
4246 attr->prio = f->common.prio;
4247}
4248
988ab9c7 4249static void
c620b772 4250mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4251 struct mlx5e_priv *priv,
4252 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4253 struct flow_cls_offload *f,
988ab9c7
TZ		 4254 struct mlx5_eswitch_rep *in_rep,
4255 struct mlx5_core_dev *in_mdev)
4256{
4257 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4258 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4259
c7569097 4260 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4261
4262 esw_attr->in_rep = in_rep;
4263 esw_attr->in_mdev = in_mdev;
4264
4265 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4266 MLX5_COUNTER_SOURCE_ESWITCH)
4267 esw_attr->counter_dev = in_mdev;
4268 else
4269 esw_attr->counter_dev = priv->mdev;
4270}
4271
71129676 4272static struct mlx5e_tc_flow *
04de7dda 4273__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4274 struct flow_cls_offload *f,
226f2ca3 4275 unsigned long flow_flags,
04de7dda
RD		 4276 struct net_device *filter_dev,
4277 struct mlx5_eswitch_rep *in_rep,
71129676 4278 struct mlx5_core_dev *in_mdev)
a88780a9 4279{
f9e30088 4280 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4281 struct netlink_ext_ack *extack = f->common.extack;
4282 struct mlx5e_tc_flow_parse_attr *parse_attr;
4283 struct mlx5e_tc_flow *flow;
4284 int attr_size, err;
e3a2b7ed 4285
226f2ca3 4286 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4287 attr_size = sizeof(struct mlx5_esw_flow_attr);
4288 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4289 &parse_attr, &flow);
4290 if (err)
4291 goto out;
988ab9c7 4292
d11afc26 4293 parse_attr->filter_dev = filter_dev;
c620b772 4294 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4295 priv, parse_attr,
4296 f, in_rep, in_mdev);
4297
54c177ca
OS		 4298 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4299 f, filter_dev);
d11afc26
OS		 4300 if (err)
4301 goto err_free;
a88780a9 4302
7e36feeb 4303 /* actions validation depends on parsing the ct matches first */
aedd133d 4304 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4305 &flow->attr->ct_attr, extack);
a88780a9
RD		 4306 if (err)
4307 goto err_free;
4308
70f8019e 4309 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 4310 if (err)
4311 goto err_free;
4312
7040632d 4313 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4314 complete_all(&flow->init_done);
ef06c9ee
RD		 4315 if (err) {
4316 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4317 goto err_free;
4318
b4a23329 4319 add_unready_flow(flow);
ef06c9ee 4320 }
e3a2b7ed 4321
71129676 4322 return flow;
a88780a9
RD		 4323
4324err_free:
5a7e5bcb 4325 mlx5e_flow_put(priv, flow);
a88780a9 4326out:
71129676 4327 return ERR_PTR(err);
a88780a9
RD		 4328}
4329
f9e30088 4330static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4331 struct mlx5e_tc_flow *flow,
226f2ca3 4332 unsigned long flow_flags)
04de7dda
RD		 4333{
4334 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4335 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4336 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4337 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4338 struct mlx5e_tc_flow_parse_attr *parse_attr;
4339 struct mlx5e_rep_priv *peer_urpriv;
4340 struct mlx5e_tc_flow *peer_flow;
4341 struct mlx5_core_dev *in_mdev;
4342 int err = 0;
4343
4344 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4345 if (!peer_esw)
4346 return -ENODEV;
4347
4348 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4349 peer_priv = netdev_priv(peer_urpriv->netdev);
4350
4351 /* in_mdev is assigned of which the packet originated from.
4352 * So packets redirected to uplink use the same mdev of the
4353 * original flow and packets redirected from uplink use the
4354 * peer mdev.
4355 */
c620b772 4356 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4357 in_mdev = peer_priv->mdev;
4358 else
4359 in_mdev = priv->mdev;
4360
c620b772 4361 parse_attr = flow->attr->parse_attr;
95dc1902 4362 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4363 parse_attr->filter_dev,
c620b772 4364 attr->in_rep, in_mdev);
71129676
JG		 4365 if (IS_ERR(peer_flow)) {
4366 err = PTR_ERR(peer_flow);
04de7dda 4367 goto out;
71129676 4368 }
04de7dda
RD		 4369
4370 flow->peer_flow = peer_flow;
226f2ca3 4371 flow_flag_set(flow, DUP);
04de7dda
RD		 4372 mutex_lock(&esw->offloads.peer_mutex);
4373 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4374 mutex_unlock(&esw->offloads.peer_mutex);
4375
4376out:
4377 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4378 return err;
4379}
4380
4381static int
4382mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4383 struct flow_cls_offload *f,
226f2ca3 4384 unsigned long flow_flags,
04de7dda
RD		 4385 struct net_device *filter_dev,
4386 struct mlx5e_tc_flow **__flow)
4387{
4388 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4389 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4390 struct mlx5_core_dev *in_mdev = priv->mdev;
4391 struct mlx5e_tc_flow *flow;
4392 int err;
4393
71129676
JG		 4394 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4395 in_mdev);
4396 if (IS_ERR(flow))
4397 return PTR_ERR(flow);
04de7dda
RD		 4398
4399 if (is_peer_flow_needed(flow)) {
95dc1902 4400 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4401 if (err) {
4402 mlx5e_tc_del_fdb_flow(priv, flow);
4403 goto out;
4404 }
4405 }
4406
4407 *__flow = flow;
4408
4409 return 0;
4410
4411out:
4412 return err;
4413}
4414
a88780a9
RD		 4415static int
4416mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4417 struct flow_cls_offload *f,
226f2ca3 4418 unsigned long flow_flags,
d11afc26 4419 struct net_device *filter_dev,
a88780a9
RD		 4420 struct mlx5e_tc_flow **__flow)
4421{
f9e30088 4422 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4423 struct netlink_ext_ack *extack = f->common.extack;
4424 struct mlx5e_tc_flow_parse_attr *parse_attr;
4425 struct mlx5e_tc_flow *flow;
4426 int attr_size, err;
4427
c7569097
AL		 4428 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4429 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4430 return -EOPNOTSUPP;
4431 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4432 return -EOPNOTSUPP;
c7569097 4433 }
bf07aa73 4434
226f2ca3 4435 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4436 attr_size = sizeof(struct mlx5_nic_flow_attr);
4437 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4438 &parse_attr, &flow);
4439 if (err)
4440 goto out;
4441
d11afc26 4442 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4443 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4444
54c177ca
OS		 4445 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4446 f, filter_dev);
d11afc26
OS		 4447 if (err)
4448 goto err_free;
4449
aedd133d
AL		 4450 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4451 &flow->attr->ct_attr, extack);
4452 if (err)
4453 goto err_free;
4454
c6cfe113 4455 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4456 if (err)
4457 goto err_free;
4458
c6cfe113 4459 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 4460 if (err)
4461 goto err_free;
4462
226f2ca3 4463 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4464 *__flow = flow;
4465
4466 return 0;
e3a2b7ed 4467
e3a2b7ed 4468err_free:
8914add2 4469 flow_flag_set(flow, FAILED);
e68e28b4 4470 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4471 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4472out:
4473 return err;
4474}
4475
4476static int
4477mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4478 struct flow_cls_offload *f,
226f2ca3 4479 unsigned long flags,
d11afc26 4480 struct net_device *filter_dev,
a88780a9
RD		 4481 struct mlx5e_tc_flow **flow)
4482{
4483 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4484 unsigned long flow_flags;
a88780a9
RD		 4485 int err;
4486
4487 get_flags(flags, &flow_flags);
4488
bf07aa73
PB		 4489 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4490 return -EOPNOTSUPP;
4491
f6455de0 4492 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4493 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4494 filter_dev, flow);
a88780a9 4495 else
d11afc26
OS		 4496 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4497 filter_dev, flow);
a88780a9
RD		 4498
4499 return err;
4500}
4501
553f9328
VP		 4502static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4503 struct mlx5e_rep_priv *rpriv)
4504{
4505 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4506 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4507 * function is called from NIC mode.
553f9328 4508 */
2fb15e72 4509 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4510}
4511
71d82d2a 4512int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4513 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4514{
4515 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4516 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4517 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4518 struct mlx5e_tc_flow *flow;
4519 int err = 0;
4520
7dc84de9
RD		 4521 if (!mlx5_esw_hold(priv->mdev))
4522 return -EAGAIN;
4523
4524 mlx5_esw_get(priv->mdev);
4525
c5d326b2
VB		 4526 rcu_read_lock();
4527 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4528 if (flow) {
553f9328
VP		 4529 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4530 * just return 0.
4531 */
4532 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4533 goto rcu_unlock;
553f9328 4534
a88780a9
RD		 4535 NL_SET_ERR_MSG_MOD(extack,
4536 "flow cookie already exists, ignoring");
4537 netdev_warn_once(priv->netdev,
4538 "flow cookie %lx already exists, ignoring\n",
4539 f->cookie);
0e1c1a2f 4540 err = -EEXIST;
c1aea9e1 4541 goto rcu_unlock;
a88780a9 4542 }
c1aea9e1
VB		 4543rcu_unlock:
4544 rcu_read_unlock();
4545 if (flow)
4546 goto out;
a88780a9 4547
7a978759 4548 trace_mlx5e_configure_flower(f);
d11afc26 4549 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4550 if (err)
4551 goto out;
4552
553f9328
VP		 4553 /* Flow rule offloaded to non-uplink representor sharing tc block,
4554 * set the flow's owner dev.
4555 */
4556 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4557 flow->orig_dev = dev;
4558
c5d326b2 4559 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4560 if (err)
4561 goto err_free;
4562
7dc84de9 4563 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4564 return 0;
4565
4566err_free:
5a7e5bcb 4567 mlx5e_flow_put(priv, flow);
a88780a9 4568out:
7dc84de9
RD		 4569 mlx5_esw_put(priv->mdev);
4570 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4571 return err;
4572}
4573
8f8ae895
OG		 4574static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4575{
226f2ca3
VB		 4576 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4577 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4578
226f2ca3
VB		 4579 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4580 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4581}
4582
71d82d2a 4583int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4584 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4585{
d9ee0491 4586 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4587 struct mlx5e_tc_flow *flow;
c5d326b2 4588 int err;
e3a2b7ed 4589
c5d326b2 4590 rcu_read_lock();
ab818362 4591 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4592 if (!flow || !same_flow_direction(flow, flags)) {
4593 err = -EINVAL;
4594 goto errout;
4595 }
e3a2b7ed 4596
c5d326b2
VB		 4597 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4598 * set.
4599 */
4600 if (flow_flag_test_and_set(flow, DELETED)) {
4601 err = -EINVAL;
4602 goto errout;
4603 }
05866c82 4604 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4605 rcu_read_unlock();
e3a2b7ed 4606
7a978759 4607 trace_mlx5e_delete_flower(f);
5a7e5bcb 4608 mlx5e_flow_put(priv, flow);
e3a2b7ed 4609
7dc84de9 4610 mlx5_esw_put(priv->mdev);
e3a2b7ed 4611 return 0;
c5d326b2
VB		 4612
4613errout:
4614 rcu_read_unlock();
4615 return err;
e3a2b7ed
AV		 4616}
4617
71d82d2a 4618int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4619 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4620{
04de7dda 4621 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4622 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4623 struct mlx5_eswitch *peer_esw;
aad7e08d 4624 struct mlx5e_tc_flow *flow;
aad7e08d 4625 struct mlx5_fc *counter;
316d5f72
RD		 4626 u64 lastuse = 0;
4627 u64 packets = 0;
4628 u64 bytes = 0;
5a7e5bcb 4629 int err = 0;
aad7e08d 4630
c5d326b2
VB		 4631 rcu_read_lock();
4632 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4633 tc_ht_params));
4634 rcu_read_unlock();
5a7e5bcb
VB		 4635 if (IS_ERR(flow))
4636 return PTR_ERR(flow);
4637
4638 if (!same_flow_direction(flow, flags)) {
4639 err = -EINVAL;
4640 goto errout;
4641 }
aad7e08d 4642
4c3844d9 4643 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4644 counter = mlx5e_tc_get_counter(flow);
4645 if (!counter)
5a7e5bcb 4646 goto errout;
aad7e08d 4647
316d5f72
RD		 4648 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4649 }
aad7e08d 4650
316d5f72
RD		 4651 /* Under multipath it's possible for one rule to be currently
4652 * un-offloaded while the other rule is offloaded.
4653 */
04de7dda
RD		 4654 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4655 if (!peer_esw)
4656 goto out;
4657
226f2ca3
VB		 4658 if (flow_flag_test(flow, DUP) &&
4659 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4660 u64 bytes2;
4661 u64 packets2;
4662 u64 lastuse2;
4663
4664 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4665 if (!counter)
4666 goto no_peer_counter;
04de7dda
RD		 4667 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4668
4669 bytes += bytes2;
4670 packets += packets2;
4671 lastuse = max_t(u64, lastuse, lastuse2);
4672 }
4673
316d5f72 4674no_peer_counter:
04de7dda 4675 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4676out:
4b61d3e8 4677 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4678 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4679 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4680errout:
4681 mlx5e_flow_put(priv, flow);
4682 return err;
aad7e08d
AV		 4683}
4684
1fe3e316 4685static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4686 struct netlink_ext_ack *extack)
4687{
4688 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4689 struct mlx5_eswitch *esw;
1fe3e316 4690 u32 rate_mbps = 0;
fcb64c0f 4691 u16 vport_num;
fcb64c0f
EC		 4692 int err;
4693
e401a184
EC		 4694 vport_num = rpriv->rep->vport;
4695 if (vport_num >= MLX5_VPORT_ECPF) {
4696 NL_SET_ERR_MSG_MOD(extack,
4697 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4698 return -EOPNOTSUPP;
4699 }
4700
fcb64c0f
EC		 4701 esw = priv->mdev->priv.eswitch;
4702 /* rate is given in bytes/sec.
4703 * First convert to bits/sec and then round to the nearest mbit/secs.
4704 * mbit means million bits.
4705 * Moreover, if rate is non zero we choose to configure to a minimum of
4706 * 1 mbit/sec.
4707 */
1fe3e316
PP		 4708 if (rate) {
4709 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4710 do_div(rate, 1000000);
4711 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4712 }
4713
2d116e3e 4714 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4715 if (err)
4716 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4717
4718 return err;
4719}
4720
4721static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4722 struct flow_action *flow_action,
4723 struct netlink_ext_ack *extack)
4724{
4725 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4726 const struct flow_action_entry *act;
4727 int err;
4728 int i;
4729
4730 if (!flow_action_has_entries(flow_action)) {
4731 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4732 return -EINVAL;
4733 }
4734
4735 if (!flow_offload_has_one_action(flow_action)) {
4736 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4737 return -EOPNOTSUPP;
4738 }
4739
53eca1f3 4740 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4741 return -EOPNOTSUPP;
4742
fcb64c0f
EC		 4743 flow_action_for_each(i, act, flow_action) {
4744 switch (act->id) {
4745 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4746 if (act->police.rate_pkt_ps) {
4747 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4748 return -EOPNOTSUPP;
4749 }
fcb64c0f
EC		 4750 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4751 if (err)
4752 return err;
4753
4754 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4755 break;
4756 default:
4757 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4758 return -EOPNOTSUPP;
4759 }
4760 }
4761
4762 return 0;
4763}
4764
4765int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4766 struct tc_cls_matchall_offload *ma)
4767{
b5f814cc 4768 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4769 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4770
b5f814cc
EC		 4771 if (!mlx5_esw_qos_enabled(esw)) {
4772 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4773 return -EOPNOTSUPP;
4774 }
4775
7b83355f 4776 if (ma->common.prio != 1) {
fcb64c0f
EC		 4777 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4778 return -EINVAL;
4779 }
4780
4781 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4782}
4783
4784int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4785 struct tc_cls_matchall_offload *ma)
4786{
4787 struct netlink_ext_ack *extack = ma->common.extack;
4788
4789 return apply_police_params(priv, 0, extack);
4790}
4791
4792void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4793 struct tc_cls_matchall_offload *ma)
4794{
4795 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4796 struct rtnl_link_stats64 cur_stats;
4797 u64 dbytes;
4798 u64 dpkts;
4799
4800 cur_stats = priv->stats.vf_vport;
4801 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4802 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4803 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4804 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4805 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4806}
4807
4d8fcf21
AH		 4808static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4809 struct mlx5e_priv *peer_priv)
4810{
4811 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4812 struct mlx5e_hairpin_entry *hpe, *tmp;
4813 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4814 u16 peer_vhca_id;
4815 int bkt;
4816
4817 if (!same_hw_devs(priv, peer_priv))
4818 return;
4819
4820 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4821
b32accda 4822 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4823 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4824 if (refcount_inc_not_zero(&hpe->refcnt))
4825 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4826 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4827
4828 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4829 wait_for_completion(&hpe->res_ready);
4830 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4831 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4832
4833 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4834 }
4835}
4836
4837static int mlx5e_tc_netdev_event(struct notifier_block *this,
4838 unsigned long event, void *ptr)
4839{
4840 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4841 struct mlx5e_flow_steering *fs;
4842 struct mlx5e_priv *peer_priv;
4843 struct mlx5e_tc_table *tc;
4844 struct mlx5e_priv *priv;
4845
4846 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4847 event != NETDEV_UNREGISTER ||
4848 ndev->reg_state == NETREG_REGISTERED)
4849 return NOTIFY_DONE;
4850
4851 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4852 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4853 priv = container_of(fs, struct mlx5e_priv, fs);
4854 peer_priv = netdev_priv(ndev);
4855 if (priv == peer_priv ||
4856 !(priv->netdev->features & NETIF_F_HW_TC))
4857 return NOTIFY_DONE;
4858
4859 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4860
4861 return NOTIFY_DONE;
4862}
4863
6a064674
AL		 4864static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4865{
4866 int tc_grp_size, tc_tbl_size;
4867 u32 max_flow_counter;
4868
4869 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4870 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4871
4872 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4873
4874 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4875 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4876
4877 return tc_tbl_size;
4878}
4879
655dc3d2 4880int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4881{
acff797c 4882 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4883 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4884 struct mapping_ctx *chains_mapping;
6a064674 4885 struct mlx5_chains_attr attr = {};
2198b932 4886 u64 mapping_id;
4d8fcf21 4887 int err;
e8f887ac 4888
b2fdf3d0 4889 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4890 mutex_init(&tc->t_lock);
b32accda 4891 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4892 hash_init(tc->hairpin_tbl);
11c9c548 4893
4d8fcf21
AH		 4894 err = rhashtable_init(&tc->ht, &tc_ht_params);
4895 if (err)
4896 return err;
4897
9ba33339
RD		 4898 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4899
2198b932
RD		 4900 mapping_id = mlx5_query_nic_system_image_guid(dev);
4901
4902 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4903 sizeof(struct mlx5_mapped_obj),
4904 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4905
c9355682
CM		 4906 if (IS_ERR(chains_mapping)) {
4907 err = PTR_ERR(chains_mapping);
4908 goto err_mapping;
4909 }
4910 tc->mapping = chains_mapping;
4911
4912 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4913 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4914 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4915 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4916 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4917 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4918 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4919 attr.mapping = chains_mapping;
6a064674
AL		 4920
4921 tc->chains = mlx5_chains_create(dev, &attr);
4922 if (IS_ERR(tc->chains)) {
4923 err = PTR_ERR(tc->chains);
4924 goto err_chains;
4925 }
4926
f0da4daa 4927 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4928 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4929 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4930
4d8fcf21 4931 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4932 err = register_netdevice_notifier_dev_net(priv->netdev,
4933 &tc->netdevice_nb,
4934 &tc->netdevice_nn);
4935 if (err) {
4d8fcf21
AH		 4936 tc->netdevice_nb.notifier_call = NULL;
4937 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4938 goto err_reg;
4d8fcf21
AH		 4939 }
4940
6a064674
AL		 4941 return 0;
4942
4943err_reg:
aedd133d 4944 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4945 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 4946 mlx5_chains_destroy(tc->chains);
4947err_chains:
c9355682
CM		 4948 mapping_destroy(chains_mapping);
4949err_mapping:
6a064674 4950 rhashtable_destroy(&tc->ht);
4d8fcf21 4951 return err;
e8f887ac
AV		 4952}
4953
4954static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4955{
4956 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4957 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4958
961e8979 4959 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4960 kfree(flow);
4961}
4962
655dc3d2 4963void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4964{
acff797c 4965 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4966
4d8fcf21 4967 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4968 unregister_netdevice_notifier_dev_net(priv->netdev,
4969 &tc->netdevice_nb,
4970 &tc->netdevice_nn);
4d8fcf21 4971
b2fdf3d0 4972 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4973 mutex_destroy(&tc->hairpin_tbl_lock);
4974
6a064674 4975 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4976
acff797c 4977 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4978 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4979 tc->t = NULL;
e8f887ac 4980 }
b6fac0b4 4981 mutex_destroy(&tc->t_lock);
6a064674 4982
aedd133d 4983 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4984 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 4985 mapping_destroy(tc->mapping);
6a064674 4986 mlx5_chains_destroy(tc->chains);
e8f887ac 4987}
655dc3d2
OG		 4988
4989int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4990{
d7a42ad0 4991 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4992 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4993 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4994 struct mapping_ctx *mapping;
aedd133d
AL		 4995 struct mlx5_eswitch *esw;
4996 struct mlx5e_priv *priv;
2198b932 4997 u64 mapping_id;
aedd133d 4998 int err = 0;
0a7fcb78
PB		 4999
5000 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5001 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5002 priv = netdev_priv(rpriv->netdev);
5003 esw = priv->mdev->priv.eswitch;
0a7fcb78 5004
f0da4daa
CM		 5005 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5006 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 5007 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5008 esw_chains(esw),
5009 &esw->offloads.mod_hdr,
f0da4daa
CM		 5010 MLX5_FLOW_NAMESPACE_FDB,
5011 uplink_priv->post_act);
4c3844d9 5012
2a9ab10a 5013#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
2741f223 5014 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a
CM		 5015#endif
5016
2198b932
RD		 5017 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5018
5019 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5020 sizeof(struct tunnel_match_key),
5021 TUNNEL_INFO_BITS_MASK, true);
5022
0a7fcb78
PB		 5023 if (IS_ERR(mapping)) {
5024 err = PTR_ERR(mapping);
5025 goto err_tun_mapping;
5026 }
5027 uplink_priv->tunnel_mapping = mapping;
5028
8e404fef 5029 /* 0xFFF is reserved for stack devices slow path table mark */
2198b932
RD		 5030 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5031 sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 5032 if (IS_ERR(mapping)) {
5033 err = PTR_ERR(mapping);
5034 goto err_enc_opts_mapping;
5035 }
5036 uplink_priv->tunnel_enc_opts_mapping = mapping;
5037
5038 err = rhashtable_init(tc_ht, &tc_ht_params);
5039 if (err)
5040 goto err_ht_init;
5041
9ba33339
RD		 5042 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5043
8914add2 5044 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 5045 if (IS_ERR(uplink_priv->encap)) {
5046 err = PTR_ERR(uplink_priv->encap);
8914add2 5047 goto err_register_fib_notifier;
2b6c3c1e 5048 }
8914add2 5049
2b6c3c1e 5050 return 0;
0a7fcb78 5051
8914add2
VB		 5052err_register_fib_notifier:
5053 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5054err_ht_init:
5055 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5056err_enc_opts_mapping:
5057 mapping_destroy(uplink_priv->tunnel_mapping);
5058err_tun_mapping:
2a9ab10a 5059#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
0027d70c 5060 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
2a9ab10a 5061#endif
aedd133d 5062 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5063 netdev_warn(priv->netdev,
5064 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 5065 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 5066 return err;
655dc3d2
OG		 5067}
5068
5069void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5070{
0a7fcb78
PB		 5071 struct mlx5_rep_uplink_priv *uplink_priv;
5072
0a7fcb78 5073 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5074
8914add2
VB		 5075 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5076 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5077
0a7fcb78
PB		 5078 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5079 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5080
2a9ab10a 5081#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
0027d70c 5082 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
2a9ab10a 5083#endif
aedd133d 5084 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 5085 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 5086}
01252a27 5087
226f2ca3 5088int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5089{
d9ee0491 5090 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5091
5092 return atomic_read(&tc_ht->nelems);
5093}
04de7dda
RD		 5094
5095void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5096{
5097 struct mlx5e_tc_flow *flow, *tmp;
5098
5099 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5100 __mlx5e_tc_del_fdb_peer_flow(flow);
5101}
b4a23329
RD		 5102
5103void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5104{
5105 struct mlx5_rep_uplink_priv *rpriv =
5106 container_of(work, struct mlx5_rep_uplink_priv,
5107 reoffload_flows_work);
5108 struct mlx5e_tc_flow *flow, *tmp;
5109
ad86755b 5110 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5111 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5112 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5113 unready_flow_del(flow);
b4a23329 5114 }
ad86755b 5115 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5116}
e2394a61
VB		 5117
5118static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5119 struct flow_cls_offload *cls_flower,
5120 unsigned long flags)
5121{
5122 switch (cls_flower->command) {
5123 case FLOW_CLS_REPLACE:
5124 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5125 flags);
5126 case FLOW_CLS_DESTROY:
5127 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5128 flags);
5129 case FLOW_CLS_STATS:
5130 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5131 flags);
5132 default:
5133 return -EOPNOTSUPP;
5134 }
5135}
5136
5137int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5138 void *cb_priv)
5139{
ec9457a6 5140 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5141 struct mlx5e_priv *priv = cb_priv;
5142
2ff349c5
RD		 5143 if (!priv->netdev || !netif_device_present(priv->netdev))
5144 return -EOPNOTSUPP;
5145
ec9457a6
RD		 5146 if (mlx5e_is_uplink_rep(priv))
5147 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5148 else
5149 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5150
e2394a61
VB		 5151 switch (type) {
5152 case TC_SETUP_CLSFLOWER:
5153 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5154 default:
5155 return -EOPNOTSUPP;
5156 }
5157}
c7569097
AL		 5158
5159bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5160 struct sk_buff *skb)
5161{
5162#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5163 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5164 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5165 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5166 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5167 struct tc_skb_ext *tc_skb_ext;
5168 int err;
5169
5170 reg_b = be32_to_cpu(cqe->ft_metadata);
5171
5172 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5173
c9355682 5174 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5175 if (err) {
5176 netdev_dbg(priv->netdev,
5177 "Couldn't find chain for chain tag: %d, err: %d\n",
5178 chain_tag, err);
5179 return false;
5180 }
5181
a91d98a0
CM		 5182 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5183 chain = mapped_obj.chain;
9453d45e 5184 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5185 if (WARN_ON(!tc_skb_ext))
5186 return false;
5187
5188 tc_skb_ext->chain = chain;
aedd133d 5189
ed2fe7ba 5190 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5191 ESW_ZONE_ID_MASK;
aedd133d
AL		 5192
5193 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5194 zone_restore_id))
5195 return false;
a91d98a0
CM		 5196 } else {
5197 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5198 return false;
c7569097
AL		 5199 }
5200#endif /* CONFIG_NET_TC_SKB_EXT */
5201
5202 return true;
5203}
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