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net/mlx5e: Refactor reg_c1 usage
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
3f6d08d1 60#include "fs_core.h"
2c81bfd5 61#include "en/port.h"
101f4de9 62#include "en/tc_tun.h"
0a7fcb78 63#include "en/mapping.h"
4c3844d9 64#include "en/tc_ct.h"
b2fdf3d0 65#include "en/mod_hdr.h"
04de7dda 66#include "lib/devcom.h"
9272e3df 67#include "lib/geneve.h"
ae430332 68#include "lib/fs_chains.h"
7a978759 69#include "diag/en_tc_tracepoint.h"
1fe3e316 70#include <asm/div64.h>
e8f887ac 71
6a064674 72#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 73#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
226f2ca3 74#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 75
65ba8fb7 76enum {
226f2ca3
VB		 77 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
78 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
79 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 80 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 81 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
82 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
83 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
84 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
85 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
86 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
87 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 88 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 89 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
14e6b038 90 MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8,
65ba8fb7
OG		 91};
92
e4ad91f2
CM		 93#define MLX5E_TC_MAX_SPLITS 1
94
79baaec7
EB		 95/* Helper struct for accessing a struct containing list_head array.
96 * Containing struct
97 * |- Helper array
98 * [0] Helper item 0
99 * |- list_head item 0
100 * |- index (0)
101 * [1] Helper item 1
102 * |- list_head item 1
103 * |- index (1)
104 * To access the containing struct from one of the list_head items:
105 * 1. Get the helper item from the list_head item using
106 * helper item =
107 * container_of(list_head item, helper struct type, list_head field)
108 * 2. Get the contining struct from the helper item and its index in the array:
109 * containing struct =
110 * container_of(helper item, containing struct type, helper field[index])
111 */
112struct encap_flow_item {
948993f2 113 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 114 struct list_head list;
115 int index;
116};
117
e8f887ac
AV		 118struct mlx5e_tc_flow {
119 struct rhash_head node;
655dc3d2 120 struct mlx5e_priv *priv;
e8f887ac 121 u64 cookie;
226f2ca3 122 unsigned long flags;
e4ad91f2 123 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
14e6b038
EC		 124
125 /* flows sharing the same reformat object - currently mpls decap */
126 struct list_head l3_to_l2_reformat;
127 struct mlx5e_decap_entry *decap_reformat;
128
79baaec7
EB		 129 /* Flow can be associated with multiple encap IDs.
130 * The number of encaps is bounded by the number of supported
131 * destinations.
132 */
133 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 134 struct mlx5e_tc_flow *peer_flow;
b2fdf3d0 135 struct mlx5e_mod_hdr_handle *mh; /* attached mod header instance */
e4f9abbd 136 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 137 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 138 struct list_head peer; /* flows with peer flow */
b4a23329 139 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
553f9328 140 struct net_device *orig_dev; /* netdev adding flow first */
2a1f1768 141 int tmp_efi_index;
6a06c2f7 142 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 143 refcount_t refcnt;
c5d326b2 144 struct rcu_head rcu_head;
95435ad7 145 struct completion init_done;
0a7fcb78 146 int tunnel_id; /* the mapped tunnel id of this flow */
c620b772 147 struct mlx5_flow_attr *attr;
e8f887ac
AV		 148};
149
17091853 150struct mlx5e_tc_flow_parse_attr {
1f6da306 151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 152 struct net_device *filter_dev;
17091853 153 struct mlx5_flow_spec spec;
6ae4a6a5 154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
14e6b038 156 struct ethhdr eth;
17091853
OG		 157};
158
acff797c 159#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 160#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 161
8f1e0b97
PB		 162struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
163 [CHAIN_TO_REG] = {
164 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
165 .moffset = 0,
166 .mlen = 2,
167 },
10742efc
VB		 168 [VPORT_TO_REG] = {
169 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
170 .moffset = 2,
171 .mlen = 2,
172 },
0a7fcb78
PB		 173 [TUNNEL_TO_REG] = {
174 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521 175 .moffset = 1,
48d216e5 176 .mlen = ((ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS) / 8),
0a7fcb78
PB		 177 .soffset = MLX5_BYTE_OFF(fte_match_param,
178 misc_parameters_2.metadata_reg_c_1),
179 },
4c3844d9 180 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 181 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 182 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
183 [MARK_TO_REG] = mark_to_reg_ct,
184 [LABELS_TO_REG] = labels_to_reg_ct,
185 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 186 /* For NIC rules we store the retore metadata directly
187 * into reg_b that is passed to SW since we don't
188 * jump between steering domains.
189 */
190 [NIC_CHAIN_TO_REG] = {
191 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
192 .moffset = 0,
193 .mlen = 2,
194 },
aedd133d 195 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 196};
197
9ba33339
RD		 198/* To avoid false lock dependency warning set the tc_ht lock
199 * class different than the lock class of the ht being used when deleting
200 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
201 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
202 * it's different than the ht->mutex here.
203 */
204static struct lock_class_key tc_ht_lock_key;
205
0a7fcb78
PB		 206static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
207
208void
209mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
210 enum mlx5e_tc_attr_to_reg type,
211 u32 data,
212 u32 mask)
213{
214 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
215 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
216 void *headers_c = spec->match_criteria;
217 void *headers_v = spec->match_value;
218 void *fmask, *fval;
219
220 fmask = headers_c + soffset;
221 fval = headers_v + soffset;
222
58ff18e1
SM		 223 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
224 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 225
226 memcpy(fmask, &mask, match_len);
227 memcpy(fval, &data, match_len);
228
229 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
230}
231
7e36feeb
PB		 232void
233mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
234 enum mlx5e_tc_attr_to_reg type,
235 u32 *data,
236 u32 *mask)
237{
238 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
239 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
240 void *headers_c = spec->match_criteria;
241 void *headers_v = spec->match_value;
242 void *fmask, *fval;
243
244 fmask = headers_c + soffset;
245 fval = headers_v + soffset;
246
247 memcpy(mask, fmask, match_len);
248 memcpy(data, fval, match_len);
249
250 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
251 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
252}
253
0a7fcb78
PB		 254int
255mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
256 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
aedd133d 257 enum mlx5_flow_namespace_type ns,
0a7fcb78
PB		 258 enum mlx5e_tc_attr_to_reg type,
259 u32 data)
260{
261 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
262 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
263 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
264 char *modact;
265 int err;
266
aedd133d 267 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 268 if (err)
269 return err;
270
271 modact = mod_hdr_acts->actions +
272 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
273
274 /* Firmware has 5bit length field and 0 means 32bits */
275 if (mlen == 4)
276 mlen = 0;
277
278 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
279 MLX5_SET(set_action_in, modact, field, mfield);
280 MLX5_SET(set_action_in, modact, offset, moffset * 8);
281 MLX5_SET(set_action_in, modact, length, mlen * 8);
282 MLX5_SET(set_action_in, modact, data, data);
283 mod_hdr_acts->num_actions++;
284
285 return 0;
286}
287
aedd133d
AL		 288static struct mlx5_tc_ct_priv *
289get_ct_priv(struct mlx5e_priv *priv)
290{
291 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
292 struct mlx5_rep_uplink_priv *uplink_priv;
293 struct mlx5e_rep_priv *uplink_rpriv;
294
e8711402 295 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 296 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
297 uplink_priv = &uplink_rpriv->uplink_priv;
298
299 return uplink_priv->ct_priv;
300 }
301
302 return priv->fs.tc.ct;
303}
304
305struct mlx5_flow_handle *
306mlx5_tc_rule_insert(struct mlx5e_priv *priv,
307 struct mlx5_flow_spec *spec,
308 struct mlx5_flow_attr *attr)
309{
310 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
311
e8711402 312 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 313 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
314
315 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
316}
317
318void
319mlx5_tc_rule_delete(struct mlx5e_priv *priv,
320 struct mlx5_flow_handle *rule,
321 struct mlx5_flow_attr *attr)
322{
323 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
324
e8711402 325 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 326 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
327
328 return;
329 }
330
331 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
332}
333
77ab67b7
OG		 334struct mlx5e_hairpin {
335 struct mlx5_hairpin *pair;
336
337 struct mlx5_core_dev *func_mdev;
3f6d08d1 338 struct mlx5e_priv *func_priv;
77ab67b7
OG		 339 u32 tdn;
340 u32 tirn;
3f6d08d1
OG		 341
342 int num_channels;
343 struct mlx5e_rqt indir_rqt;
344 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
345 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 346};
347
5c65c564
OG		 348struct mlx5e_hairpin_entry {
349 /* a node of a hash table which keeps all the hairpin entries */
350 struct hlist_node hairpin_hlist;
351
73edca73
VB		 352 /* protects flows list */
353 spinlock_t flows_lock;
5c65c564
OG		 354 /* flows sharing the same hairpin */
355 struct list_head flows;
db76ca24
VB		 356 /* hpe's that were not fully initialized when dead peer update event
357 * function traversed them.
358 */
359 struct list_head dead_peer_wait_list;
5c65c564 360
d8822868 361 u16 peer_vhca_id;
106be53b 362 u8 prio;
5c65c564 363 struct mlx5e_hairpin *hp;
e4f9abbd 364 refcount_t refcnt;
db76ca24 365 struct completion res_ready;
5c65c564
OG		 366};
367
5a7e5bcb
VB		 368static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
369 struct mlx5e_tc_flow *flow);
370
371static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
372{
373 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
374 return ERR_PTR(-EINVAL);
375 return flow;
376}
377
378static void mlx5e_flow_put(struct mlx5e_priv *priv,
379 struct mlx5e_tc_flow *flow)
380{
381 if (refcount_dec_and_test(&flow->refcnt)) {
382 mlx5e_tc_del_flow(priv, flow);
c5d326b2 383 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 384 }
385}
386
226f2ca3
VB		 387static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
388{
389 /* Complete all memory stores before setting bit. */
390 smp_mb__before_atomic();
391 set_bit(flag, &flow->flags);
392}
393
394#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
395
c5d326b2
VB		 396static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
397 unsigned long flag)
398{
399 /* test_and_set_bit() provides all necessary barriers */
400 return test_and_set_bit(flag, &flow->flags);
401}
402
403#define flow_flag_test_and_set(flow, flag) \
404 __flow_flag_test_and_set(flow, \
405 MLX5E_TC_FLOW_FLAG_##flag)
406
226f2ca3
VB		 407static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
408{
409 /* Complete all memory stores before clearing bit. */
410 smp_mb__before_atomic();
411 clear_bit(flag, &flow->flags);
412}
413
414#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
415 MLX5E_TC_FLOW_FLAG_##flag)
416
417static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
418{
419 bool ret = test_bit(flag, &flow->flags);
420
421 /* Read fields of flow structure only after checking flags. */
422 smp_mb__after_atomic();
423 return ret;
424}
425
426#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
427 MLX5E_TC_FLOW_FLAG_##flag)
428
aedd133d 429bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 430{
431 return flow_flag_test(flow, ESWITCH);
432}
433
84179981
PB		 434static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
435{
436 return flow_flag_test(flow, FT);
437}
438
226f2ca3
VB		 439static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
440{
441 return flow_flag_test(flow, OFFLOADED);
442}
443
b2fdf3d0 444static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 445{
b2fdf3d0
PB		 446 return mlx5e_is_eswitch_flow(flow) ?
447 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 448}
449
dd58edc3 450static struct mod_hdr_tbl *
b2fdf3d0 451get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 452{
453 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
454
b2fdf3d0
PB		 455 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
456 &esw->offloads.mod_hdr :
dd58edc3
VB		 457 &priv->fs.tc.mod_hdr;
458}
459
11c9c548
OG		 460static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
461 struct mlx5e_tc_flow *flow,
462 struct mlx5e_tc_flow_parse_attr *parse_attr)
463{
b2fdf3d0
PB		 464 struct mlx5_modify_hdr *modify_hdr;
465 struct mlx5e_mod_hdr_handle *mh;
11c9c548 466
b2fdf3d0
PB		 467 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
468 get_flow_name_space(flow),
469 &parse_attr->mod_hdr_acts);
470 if (IS_ERR(mh))
471 return PTR_ERR(mh);
11c9c548 472
b2fdf3d0 473 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 474 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 475 flow->mh = mh;
11c9c548
OG		 476
477 return 0;
11c9c548
OG		 478}
479
480static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
481 struct mlx5e_tc_flow *flow)
482{
5a7e5bcb 483 /* flow wasn't fully initialized */
dd58edc3 484 if (!flow->mh)
5a7e5bcb
VB		 485 return;
486
b2fdf3d0
PB		 487 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
488 flow->mh);
dd58edc3 489 flow->mh = NULL;
11c9c548
OG		 490}
491
77ab67b7
OG		 492static
493struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
494{
495 struct net_device *netdev;
496 struct mlx5e_priv *priv;
497
498 netdev = __dev_get_by_index(net, ifindex);
499 priv = netdev_priv(netdev);
500 return priv->mdev;
501}
502
503static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
504{
e0b4b472 505 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 506 void *tirc;
507 int err;
508
509 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
510 if (err)
511 goto alloc_tdn_err;
512
513 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
514
515 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 516 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 517 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
518
e0b4b472 519 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 520 if (err)
521 goto create_tir_err;
522
523 return 0;
524
525create_tir_err:
526 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
527alloc_tdn_err:
528 return err;
529}
530
531static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
532{
533 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
534 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
535}
536
3f6d08d1
OG		 537static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
538{
539 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
540 struct mlx5e_priv *priv = hp->func_priv;
541 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
542
543 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
544 hp->num_channels);
545
546 for (i = 0; i < sz; i++) {
547 ix = i;
bbeb53b8 548 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 549 ix = mlx5e_bits_invert(i, ilog2(sz));
550 ix = indirection_rqt[ix];
551 rqn = hp->pair->rqn[ix];
552 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
553 }
554}
555
556static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
557{
558 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
559 struct mlx5e_priv *priv = hp->func_priv;
560 struct mlx5_core_dev *mdev = priv->mdev;
561 void *rqtc;
562 u32 *in;
563
564 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
565 in = kvzalloc(inlen, GFP_KERNEL);
566 if (!in)
567 return -ENOMEM;
568
569 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
570
571 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
572 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
573
574 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
575
576 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
577 if (!err)
578 hp->indir_rqt.enabled = true;
579
580 kvfree(in);
581 return err;
582}
583
584static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
585{
586 struct mlx5e_priv *priv = hp->func_priv;
587 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
588 int tt, i, err;
589 void *tirc;
590
591 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 592 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
593
3f6d08d1
OG		 594 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
595 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
596
597 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
598 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
599 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 600 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
601
3f6d08d1 602 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 603 &hp->indir_tirn[tt]);
3f6d08d1
OG		 604 if (err) {
605 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
606 goto err_destroy_tirs;
607 }
608 }
609 return 0;
610
611err_destroy_tirs:
612 for (i = 0; i < tt; i++)
613 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
614 return err;
615}
616
617static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
618{
619 int tt;
620
621 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
622 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
623}
624
625static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
626 struct ttc_params *ttc_params)
627{
628 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
629 int tt;
630
631 memset(ttc_params, 0, sizeof(*ttc_params));
632
633 ttc_params->any_tt_tirn = hp->tirn;
634
635 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
636 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
637
6412bb39 638 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 639 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
640 ft_attr->prio = MLX5E_TC_PRIO;
641}
642
643static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
644{
645 struct mlx5e_priv *priv = hp->func_priv;
646 struct ttc_params ttc_params;
647 int err;
648
649 err = mlx5e_hairpin_create_indirect_rqt(hp);
650 if (err)
651 return err;
652
653 err = mlx5e_hairpin_create_indirect_tirs(hp);
654 if (err)
655 goto err_create_indirect_tirs;
656
657 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
658 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
659 if (err)
660 goto err_create_ttc_table;
661
662 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
663 hp->num_channels, hp->ttc.ft.t->id);
664
665 return 0;
666
667err_create_ttc_table:
668 mlx5e_hairpin_destroy_indirect_tirs(hp);
669err_create_indirect_tirs:
670 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
671
672 return err;
673}
674
675static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
676{
677 struct mlx5e_priv *priv = hp->func_priv;
678
679 mlx5e_destroy_ttc_table(priv, &hp->ttc);
680 mlx5e_hairpin_destroy_indirect_tirs(hp);
681 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
682}
683
77ab67b7
OG		 684static struct mlx5e_hairpin *
685mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
686 int peer_ifindex)
687{
688 struct mlx5_core_dev *func_mdev, *peer_mdev;
689 struct mlx5e_hairpin *hp;
690 struct mlx5_hairpin *pair;
691 int err;
692
693 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
694 if (!hp)
695 return ERR_PTR(-ENOMEM);
696
697 func_mdev = priv->mdev;
698 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
699
700 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
701 if (IS_ERR(pair)) {
702 err = PTR_ERR(pair);
703 goto create_pair_err;
704 }
705 hp->pair = pair;
706 hp->func_mdev = func_mdev;
3f6d08d1
OG		 707 hp->func_priv = priv;
708 hp->num_channels = params->num_channels;
77ab67b7
OG		 709
710 err = mlx5e_hairpin_create_transport(hp);
711 if (err)
712 goto create_transport_err;
713
3f6d08d1
OG		 714 if (hp->num_channels > 1) {
715 err = mlx5e_hairpin_rss_init(hp);
716 if (err)
717 goto rss_init_err;
718 }
719
77ab67b7
OG		 720 return hp;
721
3f6d08d1
OG		 722rss_init_err:
723 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 724create_transport_err:
725 mlx5_core_hairpin_destroy(hp->pair);
726create_pair_err:
727 kfree(hp);
728 return ERR_PTR(err);
729}
730
731static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
732{
3f6d08d1
OG		 733 if (hp->num_channels > 1)
734 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 735 mlx5e_hairpin_destroy_transport(hp);
736 mlx5_core_hairpin_destroy(hp->pair);
737 kvfree(hp);
738}
739
106be53b
OG		 740static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
741{
742 return (peer_vhca_id << 16 | prio);
743}
744
5c65c564 745static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 746 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 747{
748 struct mlx5e_hairpin_entry *hpe;
106be53b 749 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 750
751 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 752 hairpin_hlist, hash_key) {
e4f9abbd
VB		 753 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
754 refcount_inc(&hpe->refcnt);
5c65c564 755 return hpe;
e4f9abbd 756 }
5c65c564
OG		 757 }
758
759 return NULL;
760}
761
e4f9abbd
VB		 762static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
763 struct mlx5e_hairpin_entry *hpe)
764{
765 /* no more hairpin flows for us, release the hairpin pair */
b32accda 766 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 767 return;
b32accda
VB		 768 hash_del(&hpe->hairpin_hlist);
769 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 770
db76ca24
VB		 771 if (!IS_ERR_OR_NULL(hpe->hp)) {
772 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
773 dev_name(hpe->hp->pair->peer_mdev->device));
774
775 mlx5e_hairpin_destroy(hpe->hp);
776 }
e4f9abbd
VB		 777
778 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 779 kfree(hpe);
780}
781
106be53b
OG		 782#define UNKNOWN_MATCH_PRIO 8
783
784static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 785 struct mlx5_flow_spec *spec, u8 *match_prio,
786 struct netlink_ext_ack *extack)
106be53b
OG		 787{
788 void *headers_c, *headers_v;
789 u8 prio_val, prio_mask = 0;
790 bool vlan_present;
791
792#ifdef CONFIG_MLX5_CORE_EN_DCB
793 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 794 NL_SET_ERR_MSG_MOD(extack,
795 "only PCP trust state supported for hairpin");
106be53b
OG		 796 return -EOPNOTSUPP;
797 }
798#endif
799 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
800 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
801
802 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
803 if (vlan_present) {
804 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
805 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
806 }
807
808 if (!vlan_present || !prio_mask) {
809 prio_val = UNKNOWN_MATCH_PRIO;
810 } else if (prio_mask != 0x7) {
e98bedf5
EB		 811 NL_SET_ERR_MSG_MOD(extack,
812 "masked priority match not supported for hairpin");
106be53b
OG		 813 return -EOPNOTSUPP;
814 }
815
816 *match_prio = prio_val;
817 return 0;
818}
819
5c65c564
OG		 820static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
821 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 822 struct mlx5e_tc_flow_parse_attr *parse_attr,
823 struct netlink_ext_ack *extack)
5c65c564 824{
98b66cb1 825 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 826 struct mlx5_hairpin_params params;
d8822868 827 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 828 struct mlx5e_hairpin_entry *hpe;
829 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 830 u64 link_speed64;
831 u32 link_speed;
106be53b 832 u8 match_prio;
d8822868 833 u16 peer_id;
5c65c564
OG		 834 int err;
835
d8822868
OG		 836 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
837 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 838 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 839 return -EOPNOTSUPP;
840 }
841
d8822868 842 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 843 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
844 extack);
106be53b
OG		 845 if (err)
846 return err;
b32accda
VB		 847
848 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 849 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 850 if (hpe) {
851 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
852 wait_for_completion(&hpe->res_ready);
853
854 if (IS_ERR(hpe->hp)) {
855 err = -EREMOTEIO;
856 goto out_err;
857 }
5c65c564 858 goto attach_flow;
db76ca24 859 }
5c65c564
OG		 860
861 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 862 if (!hpe) {
db76ca24
VB		 863 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
864 return -ENOMEM;
b32accda 865 }
5c65c564 866
73edca73 867 spin_lock_init(&hpe->flows_lock);
5c65c564 868 INIT_LIST_HEAD(&hpe->flows);
db76ca24 869 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 870 hpe->peer_vhca_id = peer_id;
106be53b 871 hpe->prio = match_prio;
e4f9abbd 872 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 873 init_completion(&hpe->res_ready);
874
875 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
876 hash_hairpin_info(peer_id, match_prio));
877 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 878
879 params.log_data_size = 15;
880 params.log_data_size = min_t(u8, params.log_data_size,
881 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
882 params.log_data_size = max_t(u8, params.log_data_size,
883 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 884
eb9180f7
OG		 885 params.log_num_packets = params.log_data_size -
886 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
887 params.log_num_packets = min_t(u8, params.log_num_packets,
888 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
889
890 params.q_counter = priv->q_counter;
3f6d08d1 891 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 892 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 893 link_speed = max_t(u32, link_speed, 50000);
894 link_speed64 = link_speed;
895 do_div(link_speed64, 50000);
896 params.num_channels = link_speed64;
897
5c65c564 898 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 899 hpe->hp = hp;
900 complete_all(&hpe->res_ready);
5c65c564
OG		 901 if (IS_ERR(hp)) {
902 err = PTR_ERR(hp);
db76ca24 903 goto out_err;
5c65c564
OG		 904 }
905
eb9180f7 906 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 907 hp->tirn, hp->pair->rqn[0],
908 dev_name(hp->pair->peer_mdev->device),
eb9180f7 909 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 910
5c65c564 911attach_flow:
3f6d08d1 912 if (hpe->hp->num_channels > 1) {
226f2ca3 913 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 914 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 915 } else {
c620b772 916 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 917 }
b32accda 918
e4f9abbd 919 flow->hpe = hpe;
73edca73 920 spin_lock(&hpe->flows_lock);
5c65c564 921 list_add(&flow->hairpin, &hpe->flows);
73edca73 922 spin_unlock(&hpe->flows_lock);
3f6d08d1 923
5c65c564
OG		 924 return 0;
925
db76ca24
VB		 926out_err:
927 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 928 return err;
929}
930
931static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
932 struct mlx5e_tc_flow *flow)
933{
5a7e5bcb 934 /* flow wasn't fully initialized */
e4f9abbd 935 if (!flow->hpe)
5a7e5bcb
VB		 936 return;
937
73edca73 938 spin_lock(&flow->hpe->flows_lock);
5c65c564 939 list_del(&flow->hairpin);
73edca73
VB		 940 spin_unlock(&flow->hpe->flows_lock);
941
e4f9abbd
VB		 942 mlx5e_hairpin_put(priv, flow->hpe);
943 flow->hpe = NULL;
5c65c564
OG		 944}
945
08247066
AL		 946struct mlx5_flow_handle *
947mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
948 struct mlx5_flow_spec *spec,
c620b772 949 struct mlx5_flow_attr *attr)
e8f887ac 950{
08247066 951 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 952 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 953 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 954 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 955 struct mlx5_flow_destination dest[2] = {};
66958ed9 956 struct mlx5_flow_act flow_act = {
3bc4b7bf 957 .action = attr->action,
bb0ee7dc 958 .flags = FLOW_ACT_NO_APPEND,
66958ed9 959 };
08247066 960 struct mlx5_flow_handle *rule;
c7569097 961 struct mlx5_flow_table *ft;
08247066 962 int dest_ix = 0;
e8f887ac 963
bb0ee7dc 964 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 965 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 966
aedd133d
AL		 967 if (attr->dest_ft) {
968 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
969 dest[dest_ix].ft = attr->dest_ft;
970 dest_ix++;
971 } else if (nic_attr->hairpin_ft) {
08247066 972 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 973 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 974 dest_ix++;
c620b772 975 } else if (nic_attr->hairpin_tirn) {
08247066 976 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 977 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 978 dest_ix++;
3f6d08d1
OG		 979 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
980 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 981 if (attr->dest_chain) {
982 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
983 attr->dest_chain, 1,
984 MLX5E_TC_FT_LEVEL);
985 if (IS_ERR(dest[dest_ix].ft))
986 return ERR_CAST(dest[dest_ix].ft);
987 } else {
988 dest[dest_ix].ft = priv->fs.vlan.ft.t;
989 }
3f6d08d1 990 dest_ix++;
5c65c564 991 }
aad7e08d 992
c7569097
AL		 993 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
994 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
995 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
996
08247066 997 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 998 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 999 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 1000 dest_ix++;
aad7e08d
AV		 1001 }
1002
08247066 1003 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 1004 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 1005
6a064674
AL		 1006 mutex_lock(&tc->t_lock);
1007 if (IS_ERR_OR_NULL(tc->t)) {
1008 /* Create the root table here if doesn't exist yet */
1009 tc->t =
c7569097 1010 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 1011
1012 if (IS_ERR(tc->t)) {
1013 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 1014 netdev_err(priv->netdev,
1015 "Failed to create tc offload table\n");
c7569097
AL		 1016 rule = ERR_CAST(priv->fs.tc.t);
1017 goto err_ft_get;
e8f887ac 1018 }
e8f887ac 1019 }
08247066 1020 mutex_unlock(&tc->t_lock);
e8f887ac 1021
aedd133d
AL		 1022 if (attr->chain || attr->prio)
1023 ft = mlx5_chains_get_table(nic_chains,
1024 attr->chain, attr->prio,
1025 MLX5E_TC_FT_LEVEL);
1026 else
1027 ft = attr->ft;
1028
c7569097
AL		 1029 if (IS_ERR(ft)) {
1030 rule = ERR_CAST(ft);
1031 goto err_ft_get;
1032 }
1033
c620b772 1034 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1035 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1036
c7569097 1037 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1038 &flow_act, dest, dest_ix);
1039 if (IS_ERR(rule))
c7569097 1040 goto err_rule;
08247066
AL		 1041
1042 return rule;
c7569097
AL		 1043
1044err_rule:
aedd133d
AL		 1045 if (attr->chain || attr->prio)
1046 mlx5_chains_put_table(nic_chains,
1047 attr->chain, attr->prio,
1048 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1049err_ft_get:
1050 if (attr->dest_chain)
1051 mlx5_chains_put_table(nic_chains,
1052 attr->dest_chain, 1,
1053 MLX5E_TC_FT_LEVEL);
1054
1055 return ERR_CAST(rule);
08247066
AL		 1056}
1057
1058static int
1059mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1060 struct mlx5e_tc_flow_parse_attr *parse_attr,
1061 struct mlx5e_tc_flow *flow,
1062 struct netlink_ext_ack *extack)
1063{
c620b772 1064 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1065 struct mlx5_core_dev *dev = priv->mdev;
1066 struct mlx5_fc *counter = NULL;
1067 int err;
1068
1069 if (flow_flag_test(flow, HAIRPIN)) {
1070 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1071 if (err)
1072 return err;
1073 }
1074
1075 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1076 counter = mlx5_fc_create(dev, true);
1077 if (IS_ERR(counter))
1078 return PTR_ERR(counter);
1079
1080 attr->counter = counter;
1081 }
1082
1083 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1084 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1085 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1086 if (err)
1087 return err;
1088 }
1089
aedd133d
AL		 1090 if (flow_flag_test(flow, CT))
1091 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1092 attr, &parse_attr->mod_hdr_acts);
1093 else
1094 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1095 attr);
aad7e08d 1096
a2b7189b 1097 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1098}
1099
08247066 1100void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1101 struct mlx5_flow_handle *rule,
1102 struct mlx5_flow_attr *attr)
08247066 1103{
c7569097
AL		 1104 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1105
08247066 1106 mlx5_del_flow_rules(rule);
c7569097 1107
aedd133d
AL		 1108 if (attr->chain || attr->prio)
1109 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1110 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1111
1112 if (attr->dest_chain)
1113 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1114 MLX5E_TC_FT_LEVEL);
08247066
AL		 1115}
1116
d85cdccb
OG		 1117static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1118 struct mlx5e_tc_flow *flow)
1119{
c620b772 1120 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1121 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1122
c7569097
AL		 1123 flow_flag_clear(flow, OFFLOADED);
1124
aedd133d
AL		 1125 if (flow_flag_test(flow, CT))
1126 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1127 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1128 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1129
c7569097
AL		 1130 /* Remove root table if no rules are left to avoid
1131 * extra steering hops.
1132 */
b6fac0b4 1133 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1134 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1135 !IS_ERR_OR_NULL(tc->t)) {
1136 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1137 priv->fs.tc.t = NULL;
1138 }
b6fac0b4 1139 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1140
aedd133d
AL		 1141 kvfree(attr->parse_attr);
1142
513f8f7f 1143 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1144 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1145
aedd133d
AL		 1146 mlx5_fc_destroy(priv->mdev, attr->counter);
1147
226f2ca3 1148 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1149 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1150
1151 kfree(flow->attr);
d85cdccb
OG		 1152}
1153
aa0cbbae 1154static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1155 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1156
3c37745e 1157static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1158 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1159 struct net_device *mirred_dev,
1160 int out_index,
8c4dc42b 1161 struct netlink_ext_ack *extack,
0ad060ee
RD		 1162 struct net_device **encap_dev,
1163 bool *encap_valid);
14e6b038
EC		 1164static int mlx5e_attach_decap(struct mlx5e_priv *priv,
1165 struct mlx5e_tc_flow *flow,
1166 struct netlink_ext_ack *extack);
1167static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1168 struct mlx5e_tc_flow *flow);
3c37745e 1169
6d2a3ed0
OG		 1170static struct mlx5_flow_handle *
1171mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1172 struct mlx5e_tc_flow *flow,
1173 struct mlx5_flow_spec *spec,
c620b772 1174 struct mlx5_flow_attr *attr)
6d2a3ed0 1175{
1ef3018f 1176 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1177 struct mlx5_flow_handle *rule;
4c3844d9 1178
89e39467
PB		 1179 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1180 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1181
1ef3018f
PB		 1182 if (flow_flag_test(flow, CT)) {
1183 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1184
aedd133d
AL		 1185 return mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
1186 flow, spec, attr,
1ef3018f
PB		 1187 mod_hdr_acts);
1188 }
6d2a3ed0
OG		 1189
1190 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1191 if (IS_ERR(rule))
1192 return rule;
1193
c620b772 1194 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1195 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1196 if (IS_ERR(flow->rule[1])) {
1197 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1198 return flow->rule[1];
1199 }
1200 }
1201
6d2a3ed0
OG		 1202 return rule;
1203}
1204
1205static void
1206mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1207 struct mlx5e_tc_flow *flow,
c620b772 1208 struct mlx5_flow_attr *attr)
6d2a3ed0 1209{
226f2ca3 1210 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1211
89e39467
PB		 1212 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1213 goto offload_rule_0;
1214
4c3844d9 1215 if (flow_flag_test(flow, CT)) {
aedd133d 1216 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1217 return;
1218 }
1219
c620b772 1220 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1221 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1222
89e39467 1223offload_rule_0:
6d2a3ed0
OG		 1224 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1225}
1226
5dbe906f
PB		 1227static struct mlx5_flow_handle *
1228mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1229 struct mlx5e_tc_flow *flow,
178f69b4 1230 struct mlx5_flow_spec *spec)
5dbe906f 1231{
c620b772 1232 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1233 struct mlx5_flow_handle *rule;
1234
c620b772
AL		 1235 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1236 if (!slow_attr)
1237 return ERR_PTR(-ENOMEM);
5dbe906f 1238
c620b772
AL		 1239 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1240 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1241 slow_attr->esw_attr->split_count = 0;
1242 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1243
1244 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1245 if (!IS_ERR(rule))
226f2ca3 1246 flow_flag_set(flow, SLOW);
5dbe906f 1247
c620b772
AL		 1248 kfree(slow_attr);
1249
5dbe906f
PB		 1250 return rule;
1251}
1252
1253static void
1254mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1255 struct mlx5e_tc_flow *flow)
5dbe906f 1256{
c620b772 1257 struct mlx5_flow_attr *slow_attr;
178f69b4 1258
c620b772 1259 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1260 if (!slow_attr) {
1261 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1262 return;
1263 }
c620b772
AL		 1264
1265 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1266 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1267 slow_attr->esw_attr->split_count = 0;
1268 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1269 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1270 flow_flag_clear(flow, SLOW);
c620b772 1271 kfree(slow_attr);
5dbe906f
PB		 1272}
1273
ad86755b
VB		 1274/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1275 * function.
1276 */
1277static void unready_flow_add(struct mlx5e_tc_flow *flow,
1278 struct list_head *unready_flows)
1279{
1280 flow_flag_set(flow, NOT_READY);
1281 list_add_tail(&flow->unready, unready_flows);
1282}
1283
1284/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1285 * function.
1286 */
1287static void unready_flow_del(struct mlx5e_tc_flow *flow)
1288{
1289 list_del(&flow->unready);
1290 flow_flag_clear(flow, NOT_READY);
1291}
1292
b4a23329
RD		 1293static void add_unready_flow(struct mlx5e_tc_flow *flow)
1294{
1295 struct mlx5_rep_uplink_priv *uplink_priv;
1296 struct mlx5e_rep_priv *rpriv;
1297 struct mlx5_eswitch *esw;
1298
1299 esw = flow->priv->mdev->priv.eswitch;
1300 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1301 uplink_priv = &rpriv->uplink_priv;
1302
ad86755b
VB		 1303 mutex_lock(&uplink_priv->unready_flows_lock);
1304 unready_flow_add(flow, &uplink_priv->unready_flows);
1305 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1306}
1307
1308static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1309{
ad86755b
VB		 1310 struct mlx5_rep_uplink_priv *uplink_priv;
1311 struct mlx5e_rep_priv *rpriv;
1312 struct mlx5_eswitch *esw;
1313
1314 esw = flow->priv->mdev->priv.eswitch;
1315 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1316 uplink_priv = &rpriv->uplink_priv;
1317
1318 mutex_lock(&uplink_priv->unready_flows_lock);
1319 unready_flow_del(flow);
1320 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1321}
1322
10742efc
VB		 1323static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1324
a508728a 1325bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1326{
1327 struct mlx5_core_dev *out_mdev, *route_mdev;
1328 struct mlx5e_priv *out_priv, *route_priv;
1329
1330 out_priv = netdev_priv(out_dev);
1331 out_mdev = out_priv->mdev;
1332 route_priv = netdev_priv(route_dev);
1333 route_mdev = route_priv->mdev;
1334
1335 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1336 route_mdev->coredev_type != MLX5_COREDEV_VF)
1337 return false;
1338
1339 return same_hw_devs(out_priv, route_priv);
1340}
1341
a508728a 1342int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1343{
1344 struct mlx5e_priv *out_priv, *route_priv;
1345 struct mlx5_core_dev *route_mdev;
1346 struct mlx5_eswitch *esw;
1347 u16 vhca_id;
1348 int err;
1349
1350 out_priv = netdev_priv(out_dev);
1351 esw = out_priv->mdev->priv.eswitch;
1352 route_priv = netdev_priv(route_dev);
1353 route_mdev = route_priv->mdev;
1354
1355 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1356 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1357 return err;
1358}
1359
c83954ab 1360static int
74491de9 1361mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1362 struct mlx5e_tc_flow *flow,
1363 struct netlink_ext_ack *extack)
adb4c123
OG		 1364{
1365 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1366 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1367 struct mlx5e_tc_flow_parse_attr *parse_attr;
1368 struct mlx5_flow_attr *attr = flow->attr;
1369 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1370 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1371 struct mlx5e_rep_priv *rpriv;
1372 struct mlx5e_priv *out_priv;
0ad060ee 1373 bool encap_valid = true;
39ac237c 1374 u32 max_prio, max_chain;
0ad060ee 1375 int err = 0;
f493f155 1376 int out_index;
8b32580d 1377
84179981
PB		 1378 /* We check chain range only for tc flows.
1379 * For ft flows, we checked attr->chain was originally 0 and set it to
1380 * FDB_FT_CHAIN which is outside tc range.
1381 * See mlx5e_rep_setup_ft_cb().
1382 */
ae430332 1383 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1384 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1385 NL_SET_ERR_MSG_MOD(extack,
1386 "Requested chain is out of supported range");
5a7e5bcb 1387 return -EOPNOTSUPP;
bf07aa73
PB		 1388 }
1389
ae430332 1390 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1391 if (attr->prio > max_prio) {
61644c3d
RD		 1392 NL_SET_ERR_MSG_MOD(extack,
1393 "Requested priority is out of supported range");
5a7e5bcb 1394 return -EOPNOTSUPP;
bf07aa73 1395 }
e52c2802 1396
14e6b038
EC		 1397 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1398 err = mlx5e_attach_decap(priv, flow, extack);
1399 if (err)
1400 return err;
1401 }
1402
c620b772
AL		 1403 parse_attr = attr->parse_attr;
1404 esw_attr = attr->esw_attr;
1405
f493f155 1406 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1407 int mirred_ifindex;
1408
c620b772 1409 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1410 continue;
1411
7040632d 1412 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1413 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1414 mirred_ifindex);
733d4f36 1415 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1416 extack, &encap_dev, &encap_valid);
1417 if (err)
5a7e5bcb 1418 return err;
0ad060ee 1419
3c37745e
OG		 1420 out_priv = netdev_priv(encap_dev);
1421 rpriv = out_priv->ppriv;
c620b772
AL		 1422 esw_attr->dests[out_index].rep = rpriv->rep;
1423 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1424 }
1425
8b32580d 1426 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1427 if (err)
5a7e5bcb 1428 return err;
adb4c123 1429
d5a3c2b6
RD		 1430 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1431 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1a9527bb 1432 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1433 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1434 if (err)
5a7e5bcb 1435 return err;
d7e75a32
OG		 1436 }
1437
b8aee822 1438 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1439 counter = mlx5_fc_create(esw_attr->counter_dev, true);
5a7e5bcb
VB		 1440 if (IS_ERR(counter))
1441 return PTR_ERR(counter);
b8aee822
MB		 1442
1443 attr->counter = counter;
1444 }
1445
0ad060ee
RD		 1446 /* we get here if one of the following takes place:
1447 * (1) there's no error
1448 * (2) there's an encap action and we don't have valid neigh
3c37745e 1449 */
bc1d75fa 1450 if (!encap_valid)
178f69b4 1451 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1452 else
6d2a3ed0 1453 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1454
5a7e5bcb
VB		 1455 if (IS_ERR(flow->rule[0]))
1456 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1457 else
1458 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1459
1460 return 0;
aa0cbbae 1461}
d85cdccb 1462
9272e3df
YK		 1463static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1464{
c620b772 1465 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1466 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1467 spec->match_value,
1468 misc_parameters_3);
1469 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1470 headers_v,
1471 geneve_tlv_option_0_data);
1472
1473 return !!geneve_tlv_opt_0_data;
1474}
1475
d85cdccb
OG		 1476static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1477 struct mlx5e_tc_flow *flow)
1478{
1479 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1480 struct mlx5_flow_attr *attr = flow->attr;
f493f155 1481 int out_index;
d85cdccb 1482
0a7fcb78
PB		 1483 mlx5e_put_flow_tunnel_id(flow);
1484
12a240a4 1485 if (flow_flag_test(flow, NOT_READY))
b4a23329 1486 remove_unready_flow(flow);
ef06c9ee 1487
226f2ca3
VB		 1488 if (mlx5e_is_offloaded_flow(flow)) {
1489 if (flow_flag_test(flow, SLOW))
178f69b4 1490 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1491 else
1492 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1493 }
d85cdccb 1494
9272e3df
YK		 1495 if (mlx5_flow_has_geneve_opt(flow))
1496 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1497
513f8f7f 1498 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1499
f493f155 1500 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
c620b772 1501 if (attr->esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1502 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1503 kfree(attr->parse_attr->tun_info[out_index]);
1504 }
f493f155 1505 kvfree(attr->parse_attr);
a508728a 1506 kvfree(attr->esw_attr->rx_tun_attr);
d7e75a32 1507
aedd133d 1508 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1509
513f8f7f 1510 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1511 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1512
1513 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
c620b772 1514 mlx5_fc_destroy(attr->esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1515
1516 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1517 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1518
1519 kfree(flow->attr);
d85cdccb
OG		 1520}
1521
232c0013 1522void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1523 struct mlx5e_encap_entry *e,
1524 struct list_head *flow_list)
232c0013 1525{
3c37745e 1526 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1527 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0 1528 struct mlx5_flow_handle *rule;
c620b772 1529 struct mlx5_flow_attr *attr;
6d2a3ed0 1530 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1531 struct mlx5e_tc_flow *flow;
1532 int err;
1533
2b688ea5
MG		 1534 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1535 e->reformat_type,
1536 e->encap_size, e->encap_header,
1537 MLX5_FLOW_NAMESPACE_FDB);
1538 if (IS_ERR(e->pkt_reformat)) {
1539 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1540 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1541 return;
1542 }
1543 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1544 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1545
2a1f1768 1546 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1547 bool all_flow_encaps_valid = true;
1548 int i;
1549
95435ad7
VB		 1550 if (!mlx5e_is_offloaded_flow(flow))
1551 continue;
c620b772
AL		 1552 attr = flow->attr;
1553 esw_attr = attr->esw_attr;
1554 spec = &attr->parse_attr->spec;
6d2a3ed0 1555
2b688ea5 1556 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1557 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1558 /* Flow can be associated with multiple encap entries.
1559 * Before offloading the flow verify that all of them have
1560 * a valid neighbour.
1561 */
1562 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1563 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1564 continue;
1565 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1566 all_flow_encaps_valid = false;
1567 break;
1568 }
1569 }
1570 /* Do not offload flows with unresolved neighbors */
1571 if (!all_flow_encaps_valid)
2a1f1768 1572 continue;
5dbe906f 1573 /* update from slow path rule to encap rule */
c620b772 1574 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, attr);
6d2a3ed0
OG		 1575 if (IS_ERR(rule)) {
1576 err = PTR_ERR(rule);
232c0013
HHZ		 1577 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1578 err);
2a1f1768 1579 continue;
232c0013 1580 }
5dbe906f 1581
178f69b4 1582 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1583 flow->rule[0] = rule;
226f2ca3
VB		 1584 /* was unset when slow path rule removed */
1585 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1586 }
1587}
1588
1589void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1590 struct mlx5e_encap_entry *e,
1591 struct list_head *flow_list)
232c0013 1592{
3c37745e 1593 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1594 struct mlx5_esw_flow_attr *esw_attr;
5dbe906f 1595 struct mlx5_flow_handle *rule;
c620b772 1596 struct mlx5_flow_attr *attr;
5dbe906f 1597 struct mlx5_flow_spec *spec;
232c0013 1598 struct mlx5e_tc_flow *flow;
5dbe906f 1599 int err;
232c0013 1600
2a1f1768 1601 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1602 if (!mlx5e_is_offloaded_flow(flow))
1603 continue;
c620b772
AL		 1604 attr = flow->attr;
1605 esw_attr = attr->esw_attr;
1606 spec = &attr->parse_attr->spec;
5dbe906f
PB		 1607
1608 /* update from encap rule to slow path rule */
178f69b4 1609 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1610 /* mark the flow's encap dest as non-valid */
c620b772 1611 esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1612
1613 if (IS_ERR(rule)) {
1614 err = PTR_ERR(rule);
1615 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1616 err);
2a1f1768 1617 continue;
5dbe906f
PB		 1618 }
1619
c620b772 1620 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
5dbe906f 1621 flow->rule[0] = rule;
226f2ca3
VB		 1622 /* was unset when fast path rule removed */
1623 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1624 }
1625
61c806da
OG		 1626 /* we know that the encap is valid */
1627 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1628 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1629}
1630
b8aee822
MB		 1631static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1632{
c620b772 1633 return flow->attr->counter;
b8aee822
MB		 1634}
1635
2a1f1768
VB		 1636/* Takes reference to all flows attached to encap and adds the flows to
1637 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1638 */
1639void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1640{
1641 struct encap_flow_item *efi;
1642 struct mlx5e_tc_flow *flow;
1643
1644 list_for_each_entry(efi, &e->flows, list) {
1645 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1646 if (IS_ERR(mlx5e_flow_get(flow)))
1647 continue;
95435ad7 1648 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1649
1650 flow->tmp_efi_index = efi->index;
1651 list_add(&flow->tmp_list, flow_list);
1652 }
1653}
1654
6a06c2f7 1655/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1656void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1657{
1658 struct mlx5e_tc_flow *flow, *tmp;
1659
1660 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1661 mlx5e_flow_put(priv, flow);
1662}
1663
ac0d9176
VB		 1664static struct mlx5e_encap_entry *
1665mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1666 struct mlx5e_encap_entry *e)
1667{
1668 struct mlx5e_encap_entry *next = NULL;
1669
1670retry:
1671 rcu_read_lock();
1672
1673 /* find encap with non-zero reference counter value */
1674 for (next = e ?
1675 list_next_or_null_rcu(&nhe->encap_list,
1676 &e->encap_list,
1677 struct mlx5e_encap_entry,
1678 encap_list) :
1679 list_first_or_null_rcu(&nhe->encap_list,
1680 struct mlx5e_encap_entry,
1681 encap_list);
1682 next;
1683 next = list_next_or_null_rcu(&nhe->encap_list,
1684 &next->encap_list,
1685 struct mlx5e_encap_entry,
1686 encap_list))
1687 if (mlx5e_encap_take(next))
1688 break;
1689
1690 rcu_read_unlock();
1691
1692 /* release starting encap */
1693 if (e)
1694 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1695 if (!next)
1696 return next;
1697
1698 /* wait for encap to be fully initialized */
1699 wait_for_completion(&next->res_ready);
1700 /* continue searching if encap entry is not in valid state after completion */
1701 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1702 e = next;
1703 goto retry;
1704 }
1705
1706 return next;
1707}
1708
f6dfb4c3
HHZ		 1709void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1710{
1711 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1712 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1713 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1714 struct mlx5_fc *counter;
1715 struct neigh_table *tbl;
1716 bool neigh_used = false;
1717 struct neighbour *n;
90bb7692 1718 u64 lastuse;
f6dfb4c3
HHZ		 1719
1720 if (m_neigh->family == AF_INET)
1721 tbl = &arp_tbl;
1722#if IS_ENABLED(CONFIG_IPV6)
1723 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1724 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1725#endif
1726 else
1727 return;
1728
ac0d9176
VB		 1729 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1730 * next one.
1731 */
1732 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1733 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1734 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1735 struct mlx5_eswitch *esw;
1736 LIST_HEAD(flow_list);
948993f2 1737
6a06c2f7
VB		 1738 esw = priv->mdev->priv.eswitch;
1739 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1740 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1741 flow = container_of(efi, struct mlx5e_tc_flow,
1742 encaps[efi->index]);
5a7e5bcb
VB		 1743 if (IS_ERR(mlx5e_flow_get(flow)))
1744 continue;
6a06c2f7 1745 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1746
226f2ca3 1747 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1748 counter = mlx5e_tc_get_counter(flow);
90bb7692 1749 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1750 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1751 neigh_used = true;
1752 break;
1753 }
1754 }
1755 }
6a06c2f7 1756 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1757
6a06c2f7 1758 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1759 if (neigh_used) {
1760 /* release current encap before breaking the loop */
6a06c2f7 1761 mlx5e_encap_put(priv, e);
e36d4810 1762 break;
ac0d9176 1763 }
f6dfb4c3
HHZ		 1764 }
1765
c786fe59
VB		 1766 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1767
f6dfb4c3
HHZ		 1768 if (neigh_used) {
1769 nhe->reported_lastuse = jiffies;
1770
1771 /* find the relevant neigh according to the cached device and
1772 * dst ip pair
1773 */
1774 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1775 if (!n)
f6dfb4c3 1776 return;
f6dfb4c3
HHZ		 1777
1778 neigh_event_send(n, NULL);
1779 neigh_release(n);
1780 }
1781}
1782
61086f39 1783static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1784{
948993f2 1785 WARN_ON(!list_empty(&e->flows));
948993f2 1786
3c140dd5
VB		 1787 if (e->compl_result > 0) {
1788 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1789
1790 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1791 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1792 }
948993f2 1793
2a4b6526 1794 kfree(e->tun_info);
948993f2 1795 kfree(e->encap_header);
ac0d9176 1796 kfree_rcu(e, rcu);
948993f2
VB		 1797}
1798
14e6b038
EC		 1799static void mlx5e_decap_dealloc(struct mlx5e_priv *priv,
1800 struct mlx5e_decap_entry *d)
1801{
1802 WARN_ON(!list_empty(&d->flows));
1803
1804 if (!d->compl_result)
1805 mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat);
1806
1807 kfree_rcu(d, rcu);
1808}
1809
61086f39
VB		 1810void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1811{
1812 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1813
1814 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1815 return;
1816 hash_del_rcu(&e->encap_hlist);
1817 mutex_unlock(&esw->offloads.encap_tbl_lock);
1818
1819 mlx5e_encap_dealloc(priv, e);
1820}
1821
14e6b038
EC		 1822static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d)
1823{
1824 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1825
1826 if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock))
1827 return;
1828 hash_del_rcu(&d->hlist);
1829 mutex_unlock(&esw->offloads.decap_tbl_lock);
1830
1831 mlx5e_decap_dealloc(priv, d);
1832}
1833
d85cdccb 1834static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1835 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1836{
61086f39
VB		 1837 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1838 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1839
5a7e5bcb 1840 /* flow wasn't fully initialized */
61086f39 1841 if (!e)
5a7e5bcb
VB		 1842 return;
1843
61086f39 1844 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1845 list_del(&flow->encaps[out_index].list);
948993f2 1846 flow->encaps[out_index].e = NULL;
61086f39
VB		 1847 if (!refcount_dec_and_test(&e->refcnt)) {
1848 mutex_unlock(&esw->offloads.encap_tbl_lock);
1849 return;
1850 }
1851 hash_del_rcu(&e->encap_hlist);
1852 mutex_unlock(&esw->offloads.encap_tbl_lock);
1853
1854 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1855}
1856
14e6b038
EC		 1857static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1858 struct mlx5e_tc_flow *flow)
1859{
1860 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1861 struct mlx5e_decap_entry *d = flow->decap_reformat;
1862
1863 if (!d)
1864 return;
1865
1866 mutex_lock(&esw->offloads.decap_tbl_lock);
1867 list_del(&flow->l3_to_l2_reformat);
1868 flow->decap_reformat = NULL;
1869
1870 if (!refcount_dec_and_test(&d->refcnt)) {
1871 mutex_unlock(&esw->offloads.decap_tbl_lock);
1872 return;
1873 }
1874 hash_del_rcu(&d->hlist);
1875 mutex_unlock(&esw->offloads.decap_tbl_lock);
1876
1877 mlx5e_decap_dealloc(priv, d);
1878}
1879
04de7dda
RD		 1880static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1881{
1882 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1883
226f2ca3
VB		 1884 if (!flow_flag_test(flow, ESWITCH) ||
1885 !flow_flag_test(flow, DUP))
04de7dda
RD		 1886 return;
1887
1888 mutex_lock(&esw->offloads.peer_mutex);
1889 list_del(&flow->peer);
1890 mutex_unlock(&esw->offloads.peer_mutex);
1891
226f2ca3 1892 flow_flag_clear(flow, DUP);
04de7dda 1893
eb252c3a
RD		 1894 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1895 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1896 kfree(flow->peer_flow);
1897 }
1898
04de7dda
RD		 1899 flow->peer_flow = NULL;
1900}
1901
1902static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1903{
1904 struct mlx5_core_dev *dev = flow->priv->mdev;
1905 struct mlx5_devcom *devcom = dev->priv.devcom;
1906 struct mlx5_eswitch *peer_esw;
1907
1908 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1909 if (!peer_esw)
1910 return;
1911
1912 __mlx5e_tc_del_fdb_peer_flow(flow);
1913 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1914}
1915
e8f887ac 1916static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1917 struct mlx5e_tc_flow *flow)
e8f887ac 1918{
226f2ca3 1919 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1920 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1921 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1922 } else {
d85cdccb 1923 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1924 }
e8f887ac
AV		 1925}
1926
0a7fcb78
PB		 1927static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1928{
1929 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1930 struct flow_action *flow_action = &rule->action;
1931 const struct flow_action_entry *act;
1932 int i;
1933
1934 flow_action_for_each(i, act, flow_action) {
1935 switch (act->id) {
1936 case FLOW_ACTION_GOTO:
1937 return true;
1938 default:
1939 continue;
1940 }
1941 }
1942
1943 return false;
1944}
bbd00f7e 1945
0a7fcb78
PB		 1946static int
1947enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1948 struct flow_dissector_key_enc_opts *opts,
1949 struct netlink_ext_ack *extack,
1950 bool *dont_care)
1951{
1952 struct geneve_opt *opt;
1953 int off = 0;
1954
1955 *dont_care = true;
1956
1957 while (opts->len > off) {
1958 opt = (struct geneve_opt *)&opts->data[off];
1959
1960 if (!(*dont_care) || opt->opt_class || opt->type ||
1961 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1962 *dont_care = false;
1963
c51323ee 1964 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1965 opt->type != U8_MAX) {
0a7fcb78
PB		 1966 NL_SET_ERR_MSG(extack,
1967 "Partial match of tunnel options in chain > 0 isn't supported");
1968 netdev_warn(priv->netdev,
1969 "Partial match of tunnel options in chain > 0 isn't supported");
1970 return -EOPNOTSUPP;
1971 }
1972 }
1973
1974 off += sizeof(struct geneve_opt) + opt->length * 4;
1975 }
1976
1977 return 0;
1978}
1979
1980#define COPY_DISSECTOR(rule, diss_key, dst)\
1981({ \
1982 struct flow_rule *__rule = (rule);\
1983 typeof(dst) __dst = dst;\
1984\
1985 memcpy(__dst,\
1986 skb_flow_dissector_target(__rule->match.dissector,\
1987 diss_key,\
1988 __rule->match.key),\
1989 sizeof(*__dst));\
1990})
1991
1992static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1993 struct mlx5e_tc_flow *flow,
1994 struct flow_cls_offload *f,
1995 struct net_device *filter_dev)
bbd00f7e 1996{
f9e30088 1997 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1998 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1999 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2000 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 2001 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 2002 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 2003 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 2004 struct mlx5e_rep_priv *uplink_rpriv;
2005 struct tunnel_match_key tunnel_key;
2006 bool enc_opts_is_dont_care = true;
2007 u32 tun_id, enc_opts_id = 0;
2008 struct mlx5_eswitch *esw;
2009 u32 value, mask;
8f256622 2010 int err;
2e72eb43 2011
0a7fcb78
PB		 2012 esw = priv->mdev->priv.eswitch;
2013 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2014 uplink_priv = &uplink_rpriv->uplink_priv;
2015
2016 memset(&tunnel_key, 0, sizeof(tunnel_key));
2017 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2018 &tunnel_key.enc_control);
2019 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2020 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2021 &tunnel_key.enc_ipv4);
2022 else
2023 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2024 &tunnel_key.enc_ipv6);
2025 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2026 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2027 &tunnel_key.enc_tp);
2028 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2029 &tunnel_key.enc_key_id);
2030 tunnel_key.filter_ifindex = filter_dev->ifindex;
2031
2032 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2033 if (err)
101f4de9 2034 return err;
bbd00f7e 2035
0a7fcb78
PB		 2036 flow_rule_match_enc_opts(rule, &enc_opts_match);
2037 err = enc_opts_is_dont_care_or_full_match(priv,
2038 enc_opts_match.mask,
2039 extack,
2040 &enc_opts_is_dont_care);
2041 if (err)
2042 goto err_enc_opts;
fe1587a7 2043
0a7fcb78 2044 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 2045 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2046 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2047 sizeof(*enc_opts_match.key));
2048 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2049 sizeof(*enc_opts_match.mask));
2050
0a7fcb78 2051 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 2052 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 2053 if (err)
2054 goto err_enc_opts;
2055 }
fe1587a7 2056
0a7fcb78
PB		 2057 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2058 mask = enc_opts_id ? TUNNEL_ID_MASK :
2059 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 2060
0a7fcb78
PB		 2061 if (attr->chain) {
2062 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2063 TUNNEL_TO_REG, value, mask);
2064 } else {
2065 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2066 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 2067 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 2068 TUNNEL_TO_REG, value);
2069 if (err)
2070 goto err_set;
fe1587a7 2071
0a7fcb78 2072 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 2073 }
bbd00f7e 2074
0a7fcb78
PB		 2075 flow->tunnel_id = value;
2076 return 0;
bcef735c 2077
0a7fcb78
PB		 2078err_set:
2079 if (enc_opts_id)
2080 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2081 enc_opts_id);
2082err_enc_opts:
2083 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2084 return err;
2085}
bcef735c 2086
0a7fcb78
PB		 2087static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2088{
2089 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
2090 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
2091 struct mlx5_rep_uplink_priv *uplink_priv;
2092 struct mlx5e_rep_priv *uplink_rpriv;
2093 struct mlx5_eswitch *esw;
bcef735c 2094
0a7fcb78
PB		 2095 esw = flow->priv->mdev->priv.eswitch;
2096 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2097 uplink_priv = &uplink_rpriv->uplink_priv;
2098
2099 if (tun_id)
2100 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2101 if (enc_opts_id)
2102 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2103 enc_opts_id);
2104}
e98bedf5 2105
4c3844d9
PB		 2106u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
2107{
2108 return flow->tunnel_id;
2109}
2110
fca53304
EB		 2111void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2112 struct flow_match_basic *match, bool outer,
2113 void *headers_c, void *headers_v)
2114{
2115 bool ip_version_cap;
2116
2117 ip_version_cap = outer ?
2118 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2119 ft_field_support.outer_ip_version) :
2120 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2121 ft_field_support.inner_ip_version);
2122
2123 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2124 (match->key->n_proto == htons(ETH_P_IP) ||
2125 match->key->n_proto == htons(ETH_P_IPV6))) {
2126 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2127 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2128 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2129 } else {
2130 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2131 ntohs(match->mask->n_proto));
2132 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2133 ntohs(match->key->n_proto));
2134 }
4a5d5d73
EB		 2135}
2136
a508728a
VB		 2137static u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2138{
2139 void *headers_v;
2140 u16 ethertype;
2141 u8 ip_version;
2142
2143 if (outer)
2144 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2145 else
2146 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2147
2148 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2149 /* Return ip_version converted from ethertype anyway */
2150 if (!ip_version) {
2151 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2152 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2153 ip_version = 4;
2154 else if (ethertype == ETH_P_IPV6)
2155 ip_version = 6;
2156 }
2157 return ip_version;
2158}
2159
2160static int mlx5e_tc_set_attr_rx_tun(struct mlx5e_tc_flow *flow,
2161 struct mlx5_flow_spec *spec)
2162{
2163 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
2164 struct mlx5_rx_tun_attr *tun_attr;
2165 void *daddr, *saddr;
2166 u8 ip_version;
2167
2168 tun_attr = kvzalloc(sizeof(*tun_attr), GFP_KERNEL);
2169 if (!tun_attr)
2170 return -ENOMEM;
2171
2172 esw_attr->rx_tun_attr = tun_attr;
2173 ip_version = mlx5e_tc_get_ip_version(spec, true);
2174
2175 if (ip_version == 4) {
2176 daddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2177 outer_headers.dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
2178 saddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2179 outer_headers.src_ipv4_src_ipv6.ipv4_layout.ipv4);
2180 tun_attr->dst_ip.v4 = *(__be32 *)daddr;
2181 tun_attr->src_ip.v4 = *(__be32 *)saddr;
2182 }
2183#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
2184 else if (ip_version == 6) {
2185 int ipv6_size = MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6);
2186
2187 daddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2188 outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
2189 saddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2190 outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6);
2191 memcpy(&tun_attr->dst_ip.v6, daddr, ipv6_size);
2192 memcpy(&tun_attr->src_ip.v6, saddr, ipv6_size);
2193 }
2194#endif
2195 return 0;
2196}
2197
bbd00f7e 2198static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2199 struct mlx5e_tc_flow *flow,
bbd00f7e 2200 struct mlx5_flow_spec *spec,
f9e30088 2201 struct flow_cls_offload *f,
0a7fcb78
PB		 2202 struct net_device *filter_dev,
2203 u8 *match_level,
2204 bool *match_inner)
bbd00f7e 2205{
a508728a 2206 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 2207 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2208 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2209 bool needs_mapping, sets_mapping;
8f256622 2210 int err;
2e72eb43 2211
0a7fcb78
PB		 2212 if (!mlx5e_is_eswitch_flow(flow))
2213 return -EOPNOTSUPP;
2214
c620b772
AL		 2215 needs_mapping = !!flow->attr->chain;
2216 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 2217 *match_inner = !needs_mapping;
2218
2219 if ((needs_mapping || sets_mapping) &&
636bb968 2220 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 2221 NL_SET_ERR_MSG(extack,
636bb968 2222 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2223 netdev_warn(priv->netdev,
636bb968 2224 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2225 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2226 }
2227
c620b772 2228 if (!flow->attr->chain) {
0a7fcb78
PB		 2229 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2230 match_level);
2231 if (err) {
e98bedf5 2232 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2233 "Failed to parse tunnel attributes");
2234 netdev_warn(priv->netdev,
2235 "Failed to parse tunnel attributes");
2236 return err;
e98bedf5
EB		 2237 }
2238
14e6b038
EC		 2239 /* With mpls over udp we decapsulate using packet reformat
2240 * object
2241 */
2242 if (!netif_is_bareudp(filter_dev))
c620b772 2243 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 2244 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2245 if (err)
2246 return err;
2247 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
2248 struct mlx5_flow_spec *tmp_spec;
2249
2250 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2251 if (!tmp_spec) {
2252 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
2253 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
2254 return -ENOMEM;
2255 }
2256 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2257
2258 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2259 if (err) {
2260 kvfree(tmp_spec);
2261 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2262 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2263 return err;
2264 }
2265 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2266 kvfree(tmp_spec);
2267 if (err)
2268 return err;
bcef735c
OG		 2269 }
2270
0a7fcb78
PB		 2271 if (!needs_mapping && !sets_mapping)
2272 return 0;
bbd00f7e 2273
0a7fcb78 2274 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2275}
bbd00f7e 2276
0a7fcb78 2277static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2278{
0a7fcb78
PB		 2279 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2280 inner_headers);
bbd00f7e
HHZ		 2281}
2282
0a7fcb78 2283static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2284{
0a7fcb78
PB		 2285 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2286 inner_headers);
2287}
2288
2289static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2290{
2291 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2292 outer_headers);
2293}
2294
2295static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2296{
2297 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2298 outer_headers);
8377629e
EB		 2299}
2300
2301static void *get_match_headers_value(u32 flags,
2302 struct mlx5_flow_spec *spec)
2303{
2304 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2305 get_match_inner_headers_value(spec) :
2306 get_match_outer_headers_value(spec);
2307}
2308
2309static void *get_match_headers_criteria(u32 flags,
2310 struct mlx5_flow_spec *spec)
2311{
2312 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2313 get_match_inner_headers_criteria(spec) :
2314 get_match_outer_headers_criteria(spec);
8377629e
EB		 2315}
2316
6d65bc64 2317static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2318 struct flow_cls_offload *f)
2319{
2320 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2321 struct netlink_ext_ack *extack = f->common.extack;
2322 struct net_device *ingress_dev;
2323 struct flow_match_meta match;
2324
2325 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2326 return 0;
2327
2328 flow_rule_match_meta(rule, &match);
2329 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2330 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2331 return -EOPNOTSUPP;
6d65bc64 2332 }
2333
2334 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2335 match.key->ingress_ifindex);
2336 if (!ingress_dev) {
2337 NL_SET_ERR_MSG_MOD(extack,
2338 "Can't find the ingress port to match on");
a683012a 2339 return -ENOENT;
6d65bc64 2340 }
2341
2342 if (ingress_dev != filter_dev) {
2343 NL_SET_ERR_MSG_MOD(extack,
2344 "Can't match on the ingress filter port");
a683012a 2345 return -EOPNOTSUPP;
6d65bc64 2346 }
2347
2348 return 0;
2349}
2350
72046a91
EC		 2351static bool skip_key_basic(struct net_device *filter_dev,
2352 struct flow_cls_offload *f)
2353{
2354 /* When doing mpls over udp decap, the user needs to provide
2355 * MPLS_UC as the protocol in order to be able to match on mpls
2356 * label fields. However, the actual ethertype is IP so we want to
2357 * avoid matching on this, otherwise we'll fail the match.
2358 */
2359 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2360 return true;
2361
2362 return false;
2363}
2364
de0af0bf 2365static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2366 struct mlx5e_tc_flow *flow,
de0af0bf 2367 struct mlx5_flow_spec *spec,
f9e30088 2368 struct flow_cls_offload *f,
54c177ca 2369 struct net_device *filter_dev,
93b3586e 2370 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2371{
e98bedf5 2372 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2373 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2374 outer_headers);
2375 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2376 outer_headers);
699e96dd
JL		 2377 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2378 misc_parameters);
2379 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2380 misc_parameters);
f9e30088 2381 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2382 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2383 u16 addr_type = 0;
2384 u8 ip_proto = 0;
93b3586e 2385 u8 *match_level;
6d65bc64 2386 int err;
e3a2b7ed 2387
93b3586e 2388 match_level = outer_match_level;
de0af0bf 2389
8f256622 2390 if (dissector->used_keys &
3d144578
VB		 2391 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2392 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2393 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2394 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2395 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2396 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2397 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2398 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2399 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2400 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2401 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2402 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2403 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2404 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2405 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2406 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2407 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2408 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91
EC		 2409 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2410 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2411 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2412 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2413 dissector->used_keys);
e3a2b7ed
AV		 2414 return -EOPNOTSUPP;
2415 }
2416
075973c7 2417 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2418 bool match_inner = false;
bbd00f7e 2419
0a7fcb78
PB		 2420 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2421 outer_match_level, &match_inner);
2422 if (err)
2423 return err;
2424
2425 if (match_inner) {
2426 /* header pointers should point to the inner headers
2427 * if the packet was decapsulated already.
2428 * outer headers are set by parse_tunnel_attr.
2429 */
2430 match_level = inner_match_level;
2431 headers_c = get_match_inner_headers_criteria(spec);
2432 headers_v = get_match_inner_headers_value(spec);
2433 }
bbd00f7e
HHZ		 2434 }
2435
6d65bc64 2436 err = mlx5e_flower_parse_meta(filter_dev, f);
2437 if (err)
2438 return err;
2439
72046a91
EC		 2440 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2441 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2442 struct flow_match_basic match;
2443
2444 flow_rule_match_basic(rule, &match);
fca53304
EB		 2445 mlx5e_tc_set_ethertype(priv->mdev, &match,
2446 match_level == outer_match_level,
2447 headers_c, headers_v);
e3a2b7ed 2448
8f256622 2449 if (match.mask->n_proto)
d708f902 2450 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2451 }
35a605db
EB		 2452 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2453 is_vlan_dev(filter_dev)) {
2454 struct flow_dissector_key_vlan filter_dev_mask;
2455 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2456 struct flow_match_vlan match;
2457
35a605db
EB		 2458 if (is_vlan_dev(filter_dev)) {
2459 match.key = &filter_dev_key;
2460 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2461 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2462 match.key->vlan_priority = 0;
2463 match.mask = &filter_dev_mask;
2464 memset(match.mask, 0xff, sizeof(*match.mask));
2465 match.mask->vlan_priority = 0;
2466 } else {
2467 flow_rule_match_vlan(rule, &match);
2468 }
8f256622
PNA		 2469 if (match.mask->vlan_id ||
2470 match.mask->vlan_priority ||
2471 match.mask->vlan_tpid) {
2472 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2473 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2474 svlan_tag, 1);
2475 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2476 svlan_tag, 1);
2477 } else {
2478 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2479 cvlan_tag, 1);
2480 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2481 cvlan_tag, 1);
2482 }
095b6cfd 2483
8f256622
PNA		 2484 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2485 match.mask->vlan_id);
2486 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2487 match.key->vlan_id);
358d79a4 2488
8f256622
PNA		 2489 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2490 match.mask->vlan_priority);
2491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2492 match.key->vlan_priority);
54782900 2493
d708f902 2494 *match_level = MLX5_MATCH_L2;
54782900 2495 }
d3a80bb5 2496 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2497 /* cvlan_tag enabled in match criteria and
2498 * disabled in match value means both S & C tags
2499 * don't exist (untagged of both)
2500 */
cee26487 2501 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2502 *match_level = MLX5_MATCH_L2;
54782900
OG		 2503 }
2504
8f256622
PNA		 2505 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2506 struct flow_match_vlan match;
2507
12d5cbf8 2508 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2509 if (match.mask->vlan_id ||
2510 match.mask->vlan_priority ||
2511 match.mask->vlan_tpid) {
2512 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2513 MLX5_SET(fte_match_set_misc, misc_c,
2514 outer_second_svlan_tag, 1);
2515 MLX5_SET(fte_match_set_misc, misc_v,
2516 outer_second_svlan_tag, 1);
2517 } else {
2518 MLX5_SET(fte_match_set_misc, misc_c,
2519 outer_second_cvlan_tag, 1);
2520 MLX5_SET(fte_match_set_misc, misc_v,
2521 outer_second_cvlan_tag, 1);
2522 }
2523
2524 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2525 match.mask->vlan_id);
699e96dd 2526 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2527 match.key->vlan_id);
699e96dd 2528 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2529 match.mask->vlan_priority);
699e96dd 2530 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2531 match.key->vlan_priority);
699e96dd
JL		 2532
2533 *match_level = MLX5_MATCH_L2;
0faddfe6 2534 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2535 }
2536 }
2537
8f256622
PNA		 2538 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2539 struct flow_match_eth_addrs match;
54782900 2540
8f256622 2541 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2542 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2543 dmac_47_16),
8f256622 2544 match.mask->dst);
d3a80bb5
OG		 2545 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2546 dmac_47_16),
8f256622 2547 match.key->dst);
d3a80bb5
OG		 2548
2549 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2550 smac_47_16),
8f256622 2551 match.mask->src);
d3a80bb5
OG		 2552 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2553 smac_47_16),
8f256622 2554 match.key->src);
d3a80bb5 2555
8f256622
PNA		 2556 if (!is_zero_ether_addr(match.mask->src) ||
2557 !is_zero_ether_addr(match.mask->dst))
d708f902 2558 *match_level = MLX5_MATCH_L2;
54782900
OG		 2559 }
2560
8f256622
PNA		 2561 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2562 struct flow_match_control match;
54782900 2563
8f256622
PNA		 2564 flow_rule_match_control(rule, &match);
2565 addr_type = match.key->addr_type;
54782900
OG		 2566
2567 /* the HW doesn't support frag first/later */
8f256622 2568 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2569 return -EOPNOTSUPP;
2570
8f256622 2571 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2572 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2573 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2574 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2575
2576 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2577 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2578 *match_level = MLX5_MATCH_L2;
54782900
OG		 2579 /* *** L2 attributes parsing up to here *** */
2580 else
83621b7d 2581 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2582 }
2583 }
2584
8f256622
PNA		 2585 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2586 struct flow_match_basic match;
2587
2588 flow_rule_match_basic(rule, &match);
2589 ip_proto = match.key->ip_proto;
54782900
OG		 2590
2591 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2592 match.mask->ip_proto);
54782900 2593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2594 match.key->ip_proto);
54782900 2595
8f256622 2596 if (match.mask->ip_proto)
d708f902 2597 *match_level = MLX5_MATCH_L3;
54782900
OG		 2598 }
2599
e3a2b7ed 2600 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2601 struct flow_match_ipv4_addrs match;
e3a2b7ed 2602
8f256622 2603 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2604 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2605 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2606 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2607 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2608 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2609 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2610 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2611 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2612 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2613 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2614 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2615 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2616
8f256622 2617 if (match.mask->src || match.mask->dst)
d708f902 2618 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2619 }
2620
2621 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2622 struct flow_match_ipv6_addrs match;
e3a2b7ed 2623
8f256622 2624 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2626 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2627 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2628 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2629 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2630 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2631
2632 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2633 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2634 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2635 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2636 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2637 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2638
8f256622
PNA		 2639 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2640 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2641 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2642 }
2643
8f256622
PNA		 2644 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2645 struct flow_match_ip match;
1f97a526 2646
8f256622
PNA		 2647 flow_rule_match_ip(rule, &match);
2648 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2649 match.mask->tos & 0x3);
2650 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2651 match.key->tos & 0x3);
1f97a526 2652
8f256622
PNA		 2653 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2654 match.mask->tos >> 2);
2655 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2656 match.key->tos >> 2);
1f97a526 2657
8f256622
PNA		 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2659 match.mask->ttl);
2660 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2661 match.key->ttl);
1f97a526 2662
8f256622 2663 if (match.mask->ttl &&
a8ade55f 2664 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2665 ft_field_support.outer_ipv4_ttl)) {
2666 NL_SET_ERR_MSG_MOD(extack,
2667 "Matching on TTL is not supported");
1f97a526 2668 return -EOPNOTSUPP;
e98bedf5 2669 }
a8ade55f 2670
8f256622 2671 if (match.mask->tos || match.mask->ttl)
d708f902 2672 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2673 }
2674
54782900
OG		 2675 /* *** L3 attributes parsing up to here *** */
2676
8f256622
PNA		 2677 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2678 struct flow_match_ports match;
2679
2680 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2681 switch (ip_proto) {
2682 case IPPROTO_TCP:
2683 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2684 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2685 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2686 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2687
2688 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2689 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2690 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2691 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2692 break;
2693
2694 case IPPROTO_UDP:
2695 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2696 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2697 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2698 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2699
2700 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2701 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2702 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2703 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2704 break;
2705 default:
e98bedf5
EB		 2706 NL_SET_ERR_MSG_MOD(extack,
2707 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2708 netdev_err(priv->netdev,
2709 "Only UDP and TCP transport are supported\n");
2710 return -EINVAL;
2711 }
de0af0bf 2712
8f256622 2713 if (match.mask->src || match.mask->dst)
d708f902 2714 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2715 }
2716
8f256622
PNA		 2717 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2718 struct flow_match_tcp match;
e77834ec 2719
8f256622 2720 flow_rule_match_tcp(rule, &match);
e77834ec 2721 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2722 ntohs(match.mask->flags));
e77834ec 2723 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2724 ntohs(match.key->flags));
e77834ec 2725
8f256622 2726 if (match.mask->flags)
d708f902 2727 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2728 }
2729
e3a2b7ed
AV		 2730 return 0;
2731}
2732
de0af0bf 2733static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2734 struct mlx5e_tc_flow *flow,
de0af0bf 2735 struct mlx5_flow_spec *spec,
f9e30088 2736 struct flow_cls_offload *f,
54c177ca 2737 struct net_device *filter_dev)
de0af0bf 2738{
93b3586e 2739 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2740 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2741 struct mlx5_core_dev *dev = priv->mdev;
2742 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2743 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2744 struct mlx5_eswitch_rep *rep;
226f2ca3 2745 bool is_eswitch_flow;
de0af0bf
RD		 2746 int err;
2747
93b3586e
HN		 2748 inner_match_level = MLX5_MATCH_NONE;
2749 outer_match_level = MLX5_MATCH_NONE;
2750
0a7fcb78
PB		 2751 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2752 &inner_match_level, &outer_match_level);
93b3586e
HN		 2753 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2754 outer_match_level : inner_match_level;
de0af0bf 2755
226f2ca3
VB		 2756 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2757 if (!err && is_eswitch_flow) {
1d447a39 2758 rep = rpriv->rep;
b05af6aa 2759 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2760 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2761 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2762 NL_SET_ERR_MSG_MOD(extack,
2763 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2764 netdev_warn(priv->netdev,
2765 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2766 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2767 return -EOPNOTSUPP;
2768 }
2769 }
2770
c620b772
AL		 2771 flow->attr->inner_match_level = inner_match_level;
2772 flow->attr->outer_match_level = outer_match_level;
2773
38aa51c1 2774
de0af0bf
RD		 2775 return err;
2776}
2777
d79b6df6
OG		 2778struct pedit_headers {
2779 struct ethhdr eth;
0eb69bb9 2780 struct vlan_hdr vlan;
d79b6df6
OG		 2781 struct iphdr ip4;
2782 struct ipv6hdr ip6;
2783 struct tcphdr tcp;
2784 struct udphdr udp;
2785};
2786
c500c86b
PNA		 2787struct pedit_headers_action {
2788 struct pedit_headers vals;
2789 struct pedit_headers masks;
2790 u32 pedits;
2791};
2792
d79b6df6 2793static int pedit_header_offsets[] = {
73867881
PNA		 2794 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2795 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2796 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2797 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2798 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2799};
2800
2801#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2802
2803static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2804 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2805{
2806 u32 *curr_pmask, *curr_pval;
2807
c500c86b
PNA		 2808 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2809 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2810
2811 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2812 goto out_err;
2813
2814 *curr_pmask |= mask;
2815 *curr_pval |= (val & mask);
2816
2817 return 0;
2818
2819out_err:
2820 return -EOPNOTSUPP;
2821}
2822
2823struct mlx5_fields {
2824 u8 field;
88f30bbc
DL		 2825 u8 field_bsize;
2826 u32 field_mask;
d79b6df6 2827 u32 offset;
27c11b6b 2828 u32 match_offset;
d79b6df6
OG		 2829};
2830
88f30bbc
DL		 2831#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2832 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2833 offsetof(struct pedit_headers, field) + (off), \
2834 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2835
2ef86872
EB		 2836/* masked values are the same and there are no rewrites that do not have a
2837 * match.
2838 */
2839#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2840 type matchmaskx = *(type *)(matchmaskp); \
2841 type matchvalx = *(type *)(matchvalp); \
2842 type maskx = *(type *)(maskp); \
2843 type valx = *(type *)(valp); \
2844 \
2845 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2846 matchmaskx)); \
2847})
2848
27c11b6b 2849static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2850 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2851{
2852 bool same = false;
2853
88f30bbc
DL		 2854 switch (bsize) {
2855 case 8:
2ef86872 2856 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2857 break;
88f30bbc 2858 case 16:
2ef86872 2859 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2860 break;
88f30bbc 2861 case 32:
2ef86872 2862 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2863 break;
2864 }
2865
2866 return same;
2867}
a8e4f0c4 2868
d79b6df6 2869static struct mlx5_fields fields[] = {
88f30bbc
DL		 2870 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2871 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2872 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2873 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2874 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2875 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2876
ab9341b5 2877 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2878 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2879 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2880 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2881
2882 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2883 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2884 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2885 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2886 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2887 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2888 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2889 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2890 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2891 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2892 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2893 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2894 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2895 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2896 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2897 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2898 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2899 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2900
88f30bbc
DL		 2901 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2902 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2903 /* in linux iphdr tcp_flags is 8 bits long */
2904 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2905
88f30bbc
DL		 2906 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2907 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2908};
2909
82198d8b
MD		 2910static unsigned long mask_to_le(unsigned long mask, int size)
2911{
2912 __be32 mask_be32;
2913 __be16 mask_be16;
2914
2915 if (size == 32) {
2916 mask_be32 = (__force __be32)(mask);
2917 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2918 } else if (size == 16) {
2919 mask_be32 = (__force __be32)(mask);
2920 mask_be16 = *(__be16 *)&mask_be32;
2921 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2922 }
2923
2924 return mask;
2925}
6ae4a6a5
PB		 2926static int offload_pedit_fields(struct mlx5e_priv *priv,
2927 int namespace,
2928 struct pedit_headers_action *hdrs,
e98bedf5 2929 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2930 u32 *action_flags,
e98bedf5 2931 struct netlink_ext_ack *extack)
d79b6df6
OG		 2932{
2933 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2934 int i, action_size, first, last, next_z;
88f30bbc
DL		 2935 void *headers_c, *headers_v, *action, *vals_p;
2936 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2937 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2938 struct mlx5_fields *f;
82198d8b 2939 unsigned long mask, field_mask;
6ae4a6a5 2940 int err;
88f30bbc
DL		 2941 u8 cmd;
2942
6ae4a6a5 2943 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2944 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2945 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2946
73867881
PNA		 2947 set_masks = &hdrs[0].masks;
2948 add_masks = &hdrs[1].masks;
2949 set_vals = &hdrs[0].vals;
2950 add_vals = &hdrs[1].vals;
d79b6df6 2951
d65dbedf 2952 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2953
2954 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2955 bool skip;
2956
d79b6df6
OG		 2957 f = &fields[i];
2958 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2959 s_mask = 0;
2960 a_mask = 0;
d79b6df6
OG		 2961
2962 s_masks_p = (void *)set_masks + f->offset;
2963 a_masks_p = (void *)add_masks + f->offset;
2964
88f30bbc
DL		 2965 s_mask = *s_masks_p & f->field_mask;
2966 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2967
2968 if (!s_mask && !a_mask) /* nothing to offload here */
2969 continue;
2970
2971 if (s_mask && a_mask) {
e98bedf5
EB		 2972 NL_SET_ERR_MSG_MOD(extack,
2973 "can't set and add to the same HW field");
d79b6df6
OG		 2974 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2975 return -EOPNOTSUPP;
2976 }
2977
27c11b6b 2978 skip = false;
d79b6df6 2979 if (s_mask) {
27c11b6b
EB		 2980 void *match_mask = headers_c + f->match_offset;
2981 void *match_val = headers_v + f->match_offset;
2982
d79b6df6
OG		 2983 cmd = MLX5_ACTION_TYPE_SET;
2984 mask = s_mask;
2985 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2986 /* don't rewrite if we have a match on the same value */
2987 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2988 match_mask, f->field_bsize))
27c11b6b 2989 skip = true;
d79b6df6 2990 /* clear to denote we consumed this field */
88f30bbc 2991 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2992 } else {
2993 cmd = MLX5_ACTION_TYPE_ADD;
2994 mask = a_mask;
2995 vals_p = (void *)add_vals + f->offset;
27c11b6b 2996 /* add 0 is no change */
88f30bbc 2997 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2998 skip = true;
d79b6df6 2999 /* clear to denote we consumed this field */
88f30bbc 3000 *a_masks_p &= ~f->field_mask;
d79b6df6 3001 }
27c11b6b
EB		 3002 if (skip)
3003 continue;
d79b6df6 3004
82198d8b 3005 mask = mask_to_le(mask, f->field_bsize);
2b64beba 3006
88f30bbc
DL		 3007 first = find_first_bit(&mask, f->field_bsize);
3008 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3009 last = find_last_bit(&mask, f->field_bsize);
2b64beba 3010 if (first < next_z && next_z < last) {
e98bedf5
EB		 3011 NL_SET_ERR_MSG_MOD(extack,
3012 "rewrite of few sub-fields isn't supported");
2b64beba 3013 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 3014 mask);
3015 return -EOPNOTSUPP;
3016 }
3017
6ae4a6a5
PB		 3018 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
3019 if (err) {
3020 NL_SET_ERR_MSG_MOD(extack,
3021 "too many pedit actions, can't offload");
3022 mlx5_core_warn(priv->mdev,
3023 "mlx5: parsed %d pedit actions, can't do more\n",
3024 mod_acts->num_actions);
3025 return err;
3026 }
3027
3028 action = mod_acts->actions +
3029 (mod_acts->num_actions * action_size);
d79b6df6
OG		 3030 MLX5_SET(set_action_in, action, action_type, cmd);
3031 MLX5_SET(set_action_in, action, field, f->field);
3032
3033 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 3034 int start;
3035
82198d8b
MD		 3036 field_mask = mask_to_le(f->field_mask, f->field_bsize);
3037
88f30bbc 3038 /* if field is bit sized it can start not from first bit */
82198d8b 3039 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 3040
3041 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 3042 /* length is num of bits to be written, zero means length of 32 */
2b64beba 3043 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 3044 }
3045
88f30bbc 3046 if (f->field_bsize == 32)
2b64beba 3047 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 3048 else if (f->field_bsize == 16)
2b64beba 3049 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 3050 else if (f->field_bsize == 8)
2b64beba 3051 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 3052
6ae4a6a5 3053 ++mod_acts->num_actions;
d79b6df6
OG		 3054 }
3055
d79b6df6
OG		 3056 return 0;
3057}
3058
2cc1cb1d
TZ		 3059static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
3060 int namespace)
3061{
3062 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
3063 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
3064 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
3065 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
3066}
3067
6ae4a6a5
PB		 3068int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
3069 int namespace,
3070 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 3071{
6ae4a6a5
PB		 3072 int action_size, new_num_actions, max_hw_actions;
3073 size_t new_sz, old_sz;
3074 void *ret;
d79b6df6 3075
6ae4a6a5
PB		 3076 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
3077 return 0;
d79b6df6 3078
d65dbedf 3079 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 3080
6ae4a6a5
PB		 3081 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
3082 namespace);
3083 new_num_actions = min(max_hw_actions,
3084 mod_hdr_acts->actions ?
3085 mod_hdr_acts->max_actions * 2 : 1);
3086 if (mod_hdr_acts->max_actions == new_num_actions)
3087 return -ENOSPC;
3088
3089 new_sz = action_size * new_num_actions;
3090 old_sz = mod_hdr_acts->max_actions * action_size;
3091 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
3092 if (!ret)
d79b6df6
OG		 3093 return -ENOMEM;
3094
6ae4a6a5
PB		 3095 memset(ret + old_sz, 0, new_sz - old_sz);
3096 mod_hdr_acts->actions = ret;
3097 mod_hdr_acts->max_actions = new_num_actions;
3098
d79b6df6
OG		 3099 return 0;
3100}
3101
6ae4a6a5
PB		 3102void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
3103{
3104 kfree(mod_hdr_acts->actions);
3105 mod_hdr_acts->actions = NULL;
3106 mod_hdr_acts->num_actions = 0;
3107 mod_hdr_acts->max_actions = 0;
3108}
3109
d79b6df6
OG		 3110static const struct pedit_headers zero_masks = {};
3111
582234b4
EC		 3112static int
3113parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
3114 const struct flow_action_entry *act, int namespace,
3115 struct mlx5e_tc_flow_parse_attr *parse_attr,
3116 struct pedit_headers_action *hdrs,
3117 struct netlink_ext_ack *extack)
d79b6df6 3118{
73867881
PNA		 3119 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
3120 int err = -EOPNOTSUPP;
d79b6df6 3121 u32 mask, val, offset;
73867881 3122 u8 htype;
d79b6df6 3123
73867881
PNA		 3124 htype = act->mangle.htype;
3125 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 3126
73867881
PNA		 3127 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
3128 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
3129 goto out_err;
3130 }
d79b6df6 3131
2cc1cb1d
TZ		 3132 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
3133 NL_SET_ERR_MSG_MOD(extack,
3134 "The pedit offload action is not supported");
3135 goto out_err;
3136 }
3137
73867881
PNA		 3138 mask = act->mangle.mask;
3139 val = act->mangle.val;
3140 offset = act->mangle.offset;
d79b6df6 3141
73867881
PNA		 3142 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
3143 if (err)
3144 goto out_err;
c500c86b 3145
73867881 3146 hdrs[cmd].pedits++;
d79b6df6 3147
c500c86b
PNA		 3148 return 0;
3149out_err:
3150 return err;
3151}
3152
582234b4
EC		 3153static int
3154parse_pedit_to_reformat(struct mlx5e_priv *priv,
3155 const struct flow_action_entry *act,
3156 struct mlx5e_tc_flow_parse_attr *parse_attr,
3157 struct netlink_ext_ack *extack)
3158{
3159 u32 mask, val, offset;
3160 u32 *p;
3161
3162 if (act->id != FLOW_ACTION_MANGLE)
3163 return -EOPNOTSUPP;
3164
3165 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
3166 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
3167 return -EOPNOTSUPP;
3168 }
3169
3170 mask = ~act->mangle.mask;
3171 val = act->mangle.val;
3172 offset = act->mangle.offset;
3173 p = (u32 *)&parse_attr->eth;
3174 *(p + (offset >> 2)) |= (val & mask);
3175
3176 return 0;
3177}
3178
3179static int parse_tc_pedit_action(struct mlx5e_priv *priv,
3180 const struct flow_action_entry *act, int namespace,
3181 struct mlx5e_tc_flow_parse_attr *parse_attr,
3182 struct pedit_headers_action *hdrs,
3183 struct mlx5e_tc_flow *flow,
3184 struct netlink_ext_ack *extack)
3185{
3186 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
3187 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
3188
3189 return parse_pedit_to_modify_hdr(priv, act, namespace,
3190 parse_attr, hdrs, extack);
3191}
3192
c500c86b
PNA		 3193static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3194 struct mlx5e_tc_flow_parse_attr *parse_attr,
3195 struct pedit_headers_action *hdrs,
27c11b6b 3196 u32 *action_flags,
c500c86b
PNA		 3197 struct netlink_ext_ack *extack)
3198{
3199 struct pedit_headers *cmd_masks;
3200 int err;
3201 u8 cmd;
3202
6ae4a6a5
PB		 3203 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
3204 action_flags, extack);
d79b6df6
OG		 3205 if (err < 0)
3206 goto out_dealloc_parsed_actions;
3207
3208 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 3209 cmd_masks = &hdrs[cmd].masks;
d79b6df6 3210 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 3211 NL_SET_ERR_MSG_MOD(extack,
3212 "attempt to offload an unsupported field");
b3a433de 3213 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3214 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3215 16, 1, cmd_masks, sizeof(zero_masks), true);
3216 err = -EOPNOTSUPP;
3217 goto out_dealloc_parsed_actions;
3218 }
3219 }
3220
3221 return 0;
3222
3223out_dealloc_parsed_actions:
6ae4a6a5 3224 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3225 return err;
3226}
3227
e98bedf5
EB		 3228static bool csum_offload_supported(struct mlx5e_priv *priv,
3229 u32 action,
3230 u32 update_flags,
3231 struct netlink_ext_ack *extack)
26c02749
OG		 3232{
3233 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3234 TCA_CSUM_UPDATE_FLAG_UDP;
3235
3236 /* The HW recalcs checksums only if re-writing headers */
3237 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3238 NL_SET_ERR_MSG_MOD(extack,
3239 "TC csum action is only offloaded with pedit");
26c02749
OG		 3240 netdev_warn(priv->netdev,
3241 "TC csum action is only offloaded with pedit\n");
3242 return false;
3243 }
3244
3245 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3246 NL_SET_ERR_MSG_MOD(extack,
3247 "can't offload TC csum action for some header/s");
26c02749
OG		 3248 netdev_warn(priv->netdev,
3249 "can't offload TC csum action for some header/s - flags %#x\n",
3250 update_flags);
3251 return false;
3252 }
3253
3254 return true;
3255}
3256
8998576b
DL		 3257struct ip_ttl_word {
3258 __u8 ttl;
3259 __u8 protocol;
3260 __sum16 check;
3261};
3262
3263struct ipv6_hoplimit_word {
3264 __be16 payload_len;
3265 __u8 nexthdr;
3266 __u8 hop_limit;
3267};
3268
4c3844d9
PB		 3269static int is_action_keys_supported(const struct flow_action_entry *act,
3270 bool ct_flow, bool *modify_ip_header,
7e36feeb 3271 bool *modify_tuple,
4c3844d9 3272 struct netlink_ext_ack *extack)
8998576b
DL		 3273{
3274 u32 mask, offset;
3275 u8 htype;
3276
3277 htype = act->mangle.htype;
3278 offset = act->mangle.offset;
3279 mask = ~act->mangle.mask;
3280 /* For IPv4 & IPv6 header check 4 byte word,
3281 * to determine that modified fields
3282 * are NOT ttl & hop_limit only.
3283 */
3284 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3285 struct ip_ttl_word *ttl_word =
3286 (struct ip_ttl_word *)&mask;
3287
3288 if (offset != offsetof(struct iphdr, ttl) ||
3289 ttl_word->protocol ||
3290 ttl_word->check) {
4c3844d9
PB		 3291 *modify_ip_header = true;
3292 }
3293
7e36feeb
PB		 3294 if (offset >= offsetof(struct iphdr, saddr))
3295 *modify_tuple = true;
3296
3297 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3298 NL_SET_ERR_MSG_MOD(extack,
3299 "can't offload re-write of ipv4 address with action ct");
3300 return -EOPNOTSUPP;
8998576b
DL		 3301 }
3302 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3303 struct ipv6_hoplimit_word *hoplimit_word =
3304 (struct ipv6_hoplimit_word *)&mask;
3305
3306 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3307 hoplimit_word->payload_len ||
3308 hoplimit_word->nexthdr) {
4c3844d9
PB		 3309 *modify_ip_header = true;
3310 }
3311
7e36feeb
PB		 3312 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3313 *modify_tuple = true;
3314
3315 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3316 NL_SET_ERR_MSG_MOD(extack,
3317 "can't offload re-write of ipv6 address with action ct");
3318 return -EOPNOTSUPP;
8998576b 3319 }
7e36feeb
PB		 3320 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3321 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3322 *modify_tuple = true;
3323 if (ct_flow) {
3324 NL_SET_ERR_MSG_MOD(extack,
3325 "can't offload re-write of transport header ports with action ct");
3326 return -EOPNOTSUPP;
3327 }
8998576b 3328 }
4c3844d9
PB		 3329
3330 return 0;
8998576b
DL		 3331}
3332
3d486ec4
OS		 3333static bool modify_header_match_supported(struct mlx5e_priv *priv,
3334 struct mlx5_flow_spec *spec,
73867881 3335 struct flow_action *flow_action,
4c3844d9 3336 u32 actions, bool ct_flow,
7e36feeb 3337 bool ct_clear,
e98bedf5 3338 struct netlink_ext_ack *extack)
bdd66ac0 3339{
73867881 3340 const struct flow_action_entry *act;
7e36feeb 3341 bool modify_ip_header, modify_tuple;
fca53304 3342 void *headers_c;
bdd66ac0
OG		 3343 void *headers_v;
3344 u16 ethertype;
8998576b 3345 u8 ip_proto;
4c3844d9 3346 int i, err;
bdd66ac0 3347
fca53304 3348 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3349 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3350 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3351
3352 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3353 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3354 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3355 goto out_ok;
3356
3357 modify_ip_header = false;
7e36feeb 3358 modify_tuple = false;
73867881
PNA		 3359 flow_action_for_each(i, act, flow_action) {
3360 if (act->id != FLOW_ACTION_MANGLE &&
3361 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3362 continue;
3363
4c3844d9 3364 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3365 &modify_ip_header,
3366 &modify_tuple, extack);
4c3844d9
PB		 3367 if (err)
3368 return err;
bdd66ac0
OG		 3369 }
3370
7e36feeb
PB		 3371 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3372 * (or after clear action), as otherwise, since the tuple is changed,
3373 * we can't restore ct state
3374 */
3375 if (!ct_clear && modify_tuple &&
89fbdbae 3376 mlx5_tc_ct_add_no_trk_match(spec)) {
7e36feeb
PB		 3377 NL_SET_ERR_MSG_MOD(extack,
3378 "can't offload tuple modify header with ct matches");
3379 netdev_info(priv->netdev,
3380 "can't offload tuple modify header with ct matches");
3381 return false;
3382 }
3383
bdd66ac0 3384 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3385 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3386 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3387 NL_SET_ERR_MSG_MOD(extack,
3388 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3389 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3390 ip_proto);
bdd66ac0
OG		 3391 return false;
3392 }
3393
3394out_ok:
3395 return true;
3396}
3397
3398static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3399 struct flow_action *flow_action,
bdd66ac0 3400 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3401 struct mlx5e_tc_flow *flow,
3402 struct netlink_ext_ack *extack)
bdd66ac0 3403{
a7c119bd 3404 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3405 u32 actions;
3406
c620b772
AL		 3407 ct_clear = flow->attr->ct_attr.ct_action &
3408 TCA_CT_ACT_CLEAR;
3409 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3410 actions = flow->attr->action;
3411
4c3844d9 3412 if (mlx5e_is_eswitch_flow(flow)) {
c620b772 3413 if (flow->attr->esw_attr->split_count && ct_flow) {
4c3844d9
PB		 3414 /* All registers used by ct are cleared when using
3415 * split rules.
3416 */
3417 NL_SET_ERR_MSG_MOD(extack,
3418 "Can't offload mirroring with action ct");
49397b80 3419 return false;
4c3844d9 3420 }
4c3844d9 3421 }
bdd66ac0
OG		 3422
3423 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3424 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3425 flow_action, actions,
7e36feeb
PB		 3426 ct_flow, ct_clear,
3427 extack);
bdd66ac0
OG		 3428
3429 return true;
3430}
3431
32134847
MD		 3432static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3433{
3434 return priv->mdev == peer_priv->mdev;
3435}
3436
5c65c564
OG		 3437static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3438{
3439 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3440 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3441
3442 fmdev = priv->mdev;
3443 pmdev = peer_priv->mdev;
3444
59c9d35e
AH		 3445 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3446 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3447
816f6706 3448 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3449}
3450
bdc837ee
EB		 3451static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3452 const struct flow_action_entry *act,
3453 struct mlx5e_tc_flow_parse_attr *parse_attr,
3454 struct pedit_headers_action *hdrs,
3455 u32 *action, struct netlink_ext_ack *extack)
3456{
3457 u16 mask16 = VLAN_VID_MASK;
3458 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3459 const struct flow_action_entry pedit_act = {
3460 .id = FLOW_ACTION_MANGLE,
3461 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3462 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3463 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3464 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3465 };
6fca9d1e 3466 u8 match_prio_mask, match_prio_val;
bf2f3bca 3467 void *headers_c, *headers_v;
bdc837ee
EB		 3468 int err;
3469
bf2f3bca
EB		 3470 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3471 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3472
3473 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3474 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3475 NL_SET_ERR_MSG_MOD(extack,
3476 "VLAN rewrite action must have VLAN protocol match");
3477 return -EOPNOTSUPP;
3478 }
3479
6fca9d1e
EB		 3480 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3481 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3482 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3483 NL_SET_ERR_MSG_MOD(extack,
3484 "Changing VLAN prio is not supported");
bdc837ee
EB		 3485 return -EOPNOTSUPP;
3486 }
3487
582234b4 3488 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3489 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3490
3491 return err;
3492}
3493
0bac1194
EB		 3494static int
3495add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3496 struct mlx5e_tc_flow_parse_attr *parse_attr,
3497 struct pedit_headers_action *hdrs,
3498 u32 *action, struct netlink_ext_ack *extack)
3499{
3500 const struct flow_action_entry prio_tag_act = {
3501 .vlan.vid = 0,
3502 .vlan.prio =
3503 MLX5_GET(fte_match_set_lyr_2_4,
3504 get_match_headers_value(*action,
3505 &parse_attr->spec),
3506 first_prio) &
3507 MLX5_GET(fte_match_set_lyr_2_4,
3508 get_match_headers_criteria(*action,
3509 &parse_attr->spec),
3510 first_prio),
3511 };
3512
3513 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3514 &prio_tag_act, parse_attr, hdrs, action,
3515 extack);
3516}
3517
c7569097
AL		 3518static int validate_goto_chain(struct mlx5e_priv *priv,
3519 struct mlx5e_tc_flow *flow,
3520 const struct flow_action_entry *act,
3521 u32 actions,
3522 struct netlink_ext_ack *extack)
3523{
3524 bool is_esw = mlx5e_is_eswitch_flow(flow);
3525 struct mlx5_flow_attr *attr = flow->attr;
3526 bool ft_flow = mlx5e_is_ft_flow(flow);
3527 u32 dest_chain = act->chain_index;
3528 struct mlx5_fs_chains *chains;
3529 struct mlx5_eswitch *esw;
3530 u32 reformat_and_fwd;
3531 u32 max_chain;
3532
3533 esw = priv->mdev->priv.eswitch;
3534 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3535 max_chain = mlx5_chains_get_chain_range(chains);
3536 reformat_and_fwd = is_esw ?
3537 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3538 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3539
3540 if (ft_flow) {
3541 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3542 return -EOPNOTSUPP;
3543 }
3544
3545 if (!mlx5_chains_backwards_supported(chains) &&
3546 dest_chain <= attr->chain) {
3547 NL_SET_ERR_MSG_MOD(extack,
3548 "Goto lower numbered chain isn't supported");
3549 return -EOPNOTSUPP;
3550 }
3551
3552 if (dest_chain > max_chain) {
3553 NL_SET_ERR_MSG_MOD(extack,
3554 "Requested destination chain is out of supported range");
3555 return -EOPNOTSUPP;
3556 }
3557
3558 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3559 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3560 !reformat_and_fwd) {
3561 NL_SET_ERR_MSG_MOD(extack,
3562 "Goto chain is not allowed if action has reformat or decap");
3563 return -EOPNOTSUPP;
3564 }
3565
3566 return 0;
3567}
3568
73867881
PNA		 3569static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3570 struct flow_action *flow_action,
aa0cbbae 3571 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3572 struct mlx5e_tc_flow *flow,
3573 struct netlink_ext_ack *extack)
e3a2b7ed 3574{
c620b772 3575 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3576 struct pedit_headers_action hdrs[2] = {};
3577 const struct flow_action_entry *act;
c620b772 3578 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3579 u32 action = 0;
244cd96a 3580 int err, i;
e3a2b7ed 3581
73867881 3582 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3583 return -EINVAL;
3584
53eca1f3
JK		 3585 if (!flow_action_hw_stats_check(flow_action, extack,
3586 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3587 return -EOPNOTSUPP;
3588
c620b772
AL		 3589 nic_attr = attr->nic_attr;
3590
3591 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3592
73867881
PNA		 3593 flow_action_for_each(i, act, flow_action) {
3594 switch (act->id) {
15fc92ec
TZ		 3595 case FLOW_ACTION_ACCEPT:
3596 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3597 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3598 break;
73867881 3599 case FLOW_ACTION_DROP:
1cab1cd7 3600 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3601 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3602 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3603 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3604 break;
3605 case FLOW_ACTION_MANGLE:
3606 case FLOW_ACTION_ADD:
3607 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3608 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3609 if (err)
3610 return err;
3611
c7569097 3612 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3613 break;
bdc837ee
EB		 3614 case FLOW_ACTION_VLAN_MANGLE:
3615 err = add_vlan_rewrite_action(priv,
3616 MLX5_FLOW_NAMESPACE_KERNEL,
3617 act, parse_attr, hdrs,
3618 &action, extack);
3619 if (err)
3620 return err;
3621
3622 break;
73867881 3623 case FLOW_ACTION_CSUM:
1cab1cd7 3624 if (csum_offload_supported(priv, action,
73867881 3625 act->csum_flags,
e98bedf5 3626 extack))
73867881 3627 break;
26c02749
OG		 3628
3629 return -EOPNOTSUPP;
73867881
PNA		 3630 case FLOW_ACTION_REDIRECT: {
3631 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3632
3633 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3634 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3635 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3636 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3637 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3638 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3639 } else {
e98bedf5
EB		 3640 NL_SET_ERR_MSG_MOD(extack,
3641 "device is not on same HW, can't offload");
5c65c564
OG		 3642 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3643 peer_dev->name);
3644 return -EINVAL;
3645 }
73867881
PNA		 3646 }
3647 break;
3648 case FLOW_ACTION_MARK: {
3649 u32 mark = act->mark;
e3a2b7ed
AV		 3650
3651 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3652 NL_SET_ERR_MSG_MOD(extack,
3653 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3654 return -EINVAL;
3655 }
3656
c620b772 3657 nic_attr->flow_tag = mark;
1cab1cd7 3658 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3659 }
3660 break;
c7569097
AL		 3661 case FLOW_ACTION_GOTO:
3662 err = validate_goto_chain(priv, flow, act, action,
3663 extack);
3664 if (err)
3665 return err;
3666
3667 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3668 attr->dest_chain = act->chain_index;
3669 break;
aedd133d
AL		 3670 case FLOW_ACTION_CT:
3671 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3672 if (err)
3673 return err;
3674
3675 flow_flag_set(flow, CT);
3676 break;
73867881 3677 default:
2cc1cb1d
TZ		 3678 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3679 return -EOPNOTSUPP;
e3a2b7ed 3680 }
e3a2b7ed
AV		 3681 }
3682
c500c86b
PNA		 3683 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3684 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3685 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3686 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3687 if (err)
3688 return err;
27c11b6b
EB		 3689 /* in case all pedit actions are skipped, remove the MOD_HDR
3690 * flag.
3691 */
6ae4a6a5 3692 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3693 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3694 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3695 }
c500c86b
PNA		 3696 }
3697
1cab1cd7 3698 attr->action = action;
c7569097
AL		 3699
3700 if (attr->dest_chain) {
3701 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3702 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3703 return -EOPNOTSUPP;
3704 }
3705 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3706 }
3707
3708 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3709 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3710
73867881 3711 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3712 return -EOPNOTSUPP;
3713
e3a2b7ed
AV		 3714 return 0;
3715}
3716
7f1a546e 3717struct encap_key {
1f6da306 3718 const struct ip_tunnel_key *ip_tun_key;
d386939a 3719 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3720};
3721
3722static inline int cmp_encap_info(struct encap_key *a,
3723 struct encap_key *b)
a54e20b4 3724{
7f1a546e 3725 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3726 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3727}
3728
14e6b038
EC		 3729static inline int cmp_decap_info(struct mlx5e_decap_key *a,
3730 struct mlx5e_decap_key *b)
3731{
3732 return memcmp(&a->key, &b->key, sizeof(b->key));
3733}
3734
7f1a546e 3735static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3736{
7f1a546e 3737 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3738 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3739}
3740
14e6b038
EC		 3741static inline int hash_decap_info(struct mlx5e_decap_key *key)
3742{
3743 return jhash(&key->key, sizeof(key->key), 0);
3744}
a54e20b4 3745
32134847 3746static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3747 struct net_device *peer_netdev)
3748{
3749 struct mlx5e_priv *peer_priv;
3750
3751 peer_priv = netdev_priv(peer_netdev);
3752
3753 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3754 mlx5e_eswitch_vf_rep(priv->netdev) &&
3755 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3756 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3757}
3758
948993f2
VB		 3759bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3760{
3761 return refcount_inc_not_zero(&e->refcnt);
3762}
3763
14e6b038
EC		 3764static bool mlx5e_decap_take(struct mlx5e_decap_entry *e)
3765{
3766 return refcount_inc_not_zero(&e->refcnt);
3767}
3768
948993f2
VB		 3769static struct mlx5e_encap_entry *
3770mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3771 uintptr_t hash_key)
3772{
3773 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3774 struct mlx5e_encap_entry *e;
3775 struct encap_key e_key;
3776
3777 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3778 encap_hlist, hash_key) {
3779 e_key.ip_tun_key = &e->tun_info->key;
3780 e_key.tc_tunnel = e->tunnel;
3781 if (!cmp_encap_info(&e_key, key) &&
3782 mlx5e_encap_take(e))
3783 return e;
3784 }
3785
3786 return NULL;
3787}
3788
14e6b038
EC		 3789static struct mlx5e_decap_entry *
3790mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key,
3791 uintptr_t hash_key)
3792{
3793 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3794 struct mlx5e_decap_key r_key;
3795 struct mlx5e_decap_entry *e;
3796
3797 hash_for_each_possible_rcu(esw->offloads.decap_tbl, e,
3798 hlist, hash_key) {
3799 r_key = e->key;
3800 if (!cmp_decap_info(&r_key, key) &&
3801 mlx5e_decap_take(e))
3802 return e;
3803 }
3804 return NULL;
3805}
3806
2a4b6526
VB		 3807static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3808{
3809 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3810
3811 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3812}
3813
554fe75c
DL		 3814static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3815 struct mlx5e_tc_flow *flow,
3816 int out_index,
3817 struct mlx5e_encap_entry *e,
3818 struct netlink_ext_ack *extack)
3819{
3820 int i;
3821
3822 for (i = 0; i < out_index; i++) {
3823 if (flow->encaps[i].e != e)
3824 continue;
3825 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3826 netdev_err(priv->netdev, "can't duplicate encap action\n");
3827 return true;
3828 }
3829
3830 return false;
3831}
3832
10742efc
VB		 3833static int mlx5e_set_vf_tunnel(struct mlx5_eswitch *esw,
3834 struct mlx5_flow_attr *attr,
3835 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
3836 struct net_device *out_dev,
3837 int route_dev_ifindex,
3838 int out_index)
3839{
3840 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
3841 struct net_device *route_dev;
3842 u16 vport_num;
3843 int err = 0;
3844 u32 data;
3845
3846 route_dev = dev_get_by_index(dev_net(out_dev), route_dev_ifindex);
3847
3848 if (!route_dev || route_dev->netdev_ops != &mlx5e_netdev_ops ||
3849 !mlx5e_tc_is_vf_tunnel(out_dev, route_dev))
3850 goto out;
3851
3852 err = mlx5e_tc_query_route_vport(out_dev, route_dev, &vport_num);
3853 if (err)
3854 goto out;
3855
3856 attr->dest_chain = 0;
3857 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3858 esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
3859 data = mlx5_eswitch_get_vport_metadata_for_set(esw_attr->in_mdev->priv.eswitch,
3860 vport_num);
3861 err = mlx5e_tc_match_to_reg_set(esw->dev, mod_hdr_acts,
3862 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG, data);
3863 if (err)
3864 goto out;
3865
3866out:
3867 if (route_dev)
3868 dev_put(route_dev);
3869 return err;
3870}
3871
a54e20b4 3872static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3873 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3874 struct net_device *mirred_dev,
3875 int out_index,
8c4dc42b 3876 struct netlink_ext_ack *extack,
0ad060ee
RD		 3877 struct net_device **encap_dev,
3878 bool *encap_valid)
a54e20b4
HHZ		 3879{
3880 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
733d4f36 3881 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3882 struct mlx5_flow_attr *attr = flow->attr;
1f6da306 3883 const struct ip_tunnel_info *tun_info;
948993f2 3884 struct encap_key key;
c1ae1152 3885 struct mlx5e_encap_entry *e;
733d4f36 3886 unsigned short family;
a54e20b4 3887 uintptr_t hash_key;
54c177ca 3888 int err = 0;
a54e20b4 3889
733d4f36 3890 parse_attr = attr->parse_attr;
1f6da306 3891 tun_info = parse_attr->tun_info[out_index];
733d4f36 3892 family = ip_tunnel_info_af(tun_info);
7f1a546e 3893 key.ip_tun_key = &tun_info->key;
d386939a 3894 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3895 if (!key.tc_tunnel) {
3896 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3897 return -EOPNOTSUPP;
3898 }
733d4f36 3899
7f1a546e 3900 hash_key = hash_encap_info(&key);
a54e20b4 3901
61086f39 3902 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3903 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3904
b2812089 3905 /* must verify if encap is valid or not */
d589e785 3906 if (e) {
554fe75c
DL		 3907 /* Check that entry was not already attached to this flow */
3908 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3909 err = -EOPNOTSUPP;
3910 goto out_err;
3911 }
3912
d589e785
VB		 3913 mutex_unlock(&esw->offloads.encap_tbl_lock);
3914 wait_for_completion(&e->res_ready);
3915
3916 /* Protect against concurrent neigh update. */
3917 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3918 if (e->compl_result < 0) {
d589e785
VB		 3919 err = -EREMOTEIO;
3920 goto out_err;
3921 }
45247bf2 3922 goto attach_flow;
d589e785 3923 }
a54e20b4
HHZ		 3924
3925 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3926 if (!e) {
3927 err = -ENOMEM;
3928 goto out_err;
3929 }
a54e20b4 3930
948993f2 3931 refcount_set(&e->refcnt, 1);
d589e785
VB		 3932 init_completion(&e->res_ready);
3933
2a4b6526
VB		 3934 tun_info = dup_tun_info(tun_info);
3935 if (!tun_info) {
3936 err = -ENOMEM;
3937 goto out_err_init;
3938 }
1f6da306 3939 e->tun_info = tun_info;
101f4de9 3940 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3941 if (err)
3942 goto out_err_init;
54c177ca 3943
a54e20b4 3944 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3945 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3946 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3947
ce99f6b9 3948 if (family == AF_INET)
101f4de9 3949 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3950 else if (family == AF_INET6)
101f4de9 3951 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3952
d589e785
VB		 3953 /* Protect against concurrent neigh update. */
3954 mutex_lock(&esw->offloads.encap_tbl_lock);
3955 complete_all(&e->res_ready);
3956 if (err) {
3957 e->compl_result = err;
a54e20b4 3958 goto out_err;
d589e785 3959 }
3c140dd5 3960 e->compl_result = 1;
a54e20b4 3961
45247bf2 3962attach_flow:
10742efc
VB		 3963 err = mlx5e_set_vf_tunnel(esw, attr, &parse_attr->mod_hdr_acts, e->out_dev,
3964 e->route_dev_ifindex, out_index);
3965 if (err)
3966 goto out_err;
3967
948993f2 3968 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3969 list_add(&flow->encaps[out_index].list, &e->flows);
3970 flow->encaps[out_index].index = out_index;
45247bf2 3971 *encap_dev = e->out_dev;
8c4dc42b 3972 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
c620b772
AL		 3973 attr->esw_attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3974 attr->esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3975 *encap_valid = true;
8c4dc42b 3976 } else {
0ad060ee 3977 *encap_valid = false;
8c4dc42b 3978 }
61086f39 3979 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3980
232c0013 3981 return err;
a54e20b4
HHZ		 3982
3983out_err:
61086f39 3984 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3985 if (e)
3986 mlx5e_encap_put(priv, e);
a54e20b4 3987 return err;
2a4b6526
VB		 3988
3989out_err_init:
3990 mutex_unlock(&esw->offloads.encap_tbl_lock);
3991 kfree(tun_info);
3992 kfree(e);
3993 return err;
a54e20b4
HHZ		 3994}
3995
14e6b038
EC		 3996static int mlx5e_attach_decap(struct mlx5e_priv *priv,
3997 struct mlx5e_tc_flow *flow,
3998 struct netlink_ext_ack *extack)
3999{
4000 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4001 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
14e6b038
EC		 4002 struct mlx5e_tc_flow_parse_attr *parse_attr;
4003 struct mlx5e_decap_entry *d;
4004 struct mlx5e_decap_key key;
4005 uintptr_t hash_key;
28619046 4006 int err = 0;
14e6b038 4007
c620b772 4008 parse_attr = flow->attr->parse_attr;
14e6b038
EC		 4009 if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {
4010 NL_SET_ERR_MSG_MOD(extack,
4011 "encap header larger than max supported");
4012 return -EOPNOTSUPP;
4013 }
4014
4015 key.key = parse_attr->eth;
4016 hash_key = hash_decap_info(&key);
4017 mutex_lock(&esw->offloads.decap_tbl_lock);
4018 d = mlx5e_decap_get(priv, &key, hash_key);
4019 if (d) {
4020 mutex_unlock(&esw->offloads.decap_tbl_lock);
4021 wait_for_completion(&d->res_ready);
4022 mutex_lock(&esw->offloads.decap_tbl_lock);
4023 if (d->compl_result) {
4024 err = -EREMOTEIO;
4025 goto out_free;
4026 }
4027 goto found;
4028 }
4029
4030 d = kzalloc(sizeof(*d), GFP_KERNEL);
4031 if (!d) {
4032 err = -ENOMEM;
4033 goto out_err;
4034 }
4035
4036 d->key = key;
4037 refcount_set(&d->refcnt, 1);
4038 init_completion(&d->res_ready);
4039 INIT_LIST_HEAD(&d->flows);
4040 hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key);
4041 mutex_unlock(&esw->offloads.decap_tbl_lock);
4042
4043 d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
4044 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2,
4045 sizeof(parse_attr->eth),
4046 &parse_attr->eth,
4047 MLX5_FLOW_NAMESPACE_FDB);
4048 if (IS_ERR(d->pkt_reformat)) {
4049 err = PTR_ERR(d->pkt_reformat);
4050 d->compl_result = err;
4051 }
4052 mutex_lock(&esw->offloads.decap_tbl_lock);
4053 complete_all(&d->res_ready);
4054 if (err)
4055 goto out_free;
4056
4057found:
4058 flow->decap_reformat = d;
4059 attr->decap_pkt_reformat = d->pkt_reformat;
4060 list_add(&flow->l3_to_l2_reformat, &d->flows);
4061 mutex_unlock(&esw->offloads.decap_tbl_lock);
4062 return 0;
4063
4064out_free:
4065 mutex_unlock(&esw->offloads.decap_tbl_lock);
4066 mlx5e_decap_put(priv, d);
4067 return err;
4068
4069out_err:
4070 mutex_unlock(&esw->offloads.decap_tbl_lock);
4071 return err;
4072}
4073
1482bd3d 4074static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 4075 const struct flow_action_entry *act,
1482bd3d
JL		 4076 struct mlx5_esw_flow_attr *attr,
4077 u32 *action)
4078{
cc495188
JL		 4079 u8 vlan_idx = attr->total_vlan;
4080
4081 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
4082 return -EOPNOTSUPP;
4083
73867881
PNA		 4084 switch (act->id) {
4085 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 4086 if (vlan_idx) {
4087 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
4088 MLX5_FS_VLAN_DEPTH))
4089 return -EOPNOTSUPP;
4090
4091 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
4092 } else {
4093 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4094 }
73867881
PNA		 4095 break;
4096 case FLOW_ACTION_VLAN_PUSH:
4097 attr->vlan_vid[vlan_idx] = act->vlan.vid;
4098 attr->vlan_prio[vlan_idx] = act->vlan.prio;
4099 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 4100 if (!attr->vlan_proto[vlan_idx])
4101 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
4102
4103 if (vlan_idx) {
4104 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
4105 MLX5_FS_VLAN_DEPTH))
4106 return -EOPNOTSUPP;
4107
4108 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
4109 } else {
4110 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 4111 (act->vlan.proto != htons(ETH_P_8021Q) ||
4112 act->vlan.prio))
cc495188
JL		 4113 return -EOPNOTSUPP;
4114
4115 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 4116 }
73867881
PNA		 4117 break;
4118 default:
bdc837ee 4119 return -EINVAL;
1482bd3d
JL		 4120 }
4121
cc495188
JL		 4122 attr->total_vlan = vlan_idx + 1;
4123
1482bd3d
JL		 4124 return 0;
4125}
4126
d34eb2fc
OG		 4127static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
4128 struct net_device *out_dev)
4129{
4130 struct net_device *fdb_out_dev = out_dev;
4131 struct net_device *uplink_upper;
4132
4133 rcu_read_lock();
4134 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
4135 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
4136 uplink_upper == out_dev) {
4137 fdb_out_dev = uplink_dev;
4138 } else if (netif_is_lag_master(out_dev)) {
4139 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
4140 if (fdb_out_dev &&
4141 (!mlx5e_eswitch_rep(fdb_out_dev) ||
4142 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
4143 fdb_out_dev = NULL;
4144 }
4145 rcu_read_unlock();
4146 return fdb_out_dev;
4147}
4148
278748a9 4149static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 4150 struct mlx5_flow_attr *attr,
278748a9
EB		 4151 struct net_device **out_dev,
4152 u32 *action)
4153{
4154 struct net_device *vlan_dev = *out_dev;
4155 struct flow_action_entry vlan_act = {
4156 .id = FLOW_ACTION_VLAN_PUSH,
4157 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
4158 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
4159 .vlan.prio = 0,
4160 };
4161 int err;
4162
c620b772 4163 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 4164 if (err)
4165 return err;
4166
4167 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
4168 dev_get_iflink(vlan_dev));
4169 if (is_vlan_dev(*out_dev))
4170 err = add_vlan_push_action(priv, attr, out_dev, action);
4171
4172 return err;
4173}
4174
35a605db 4175static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 4176 struct mlx5_flow_attr *attr,
35a605db
EB		 4177 u32 *action)
4178{
35a605db
EB		 4179 struct flow_action_entry vlan_act = {
4180 .id = FLOW_ACTION_VLAN_POP,
4181 };
70f478ca 4182 int nest_level, err = 0;
35a605db 4183
70f478ca
DL		 4184 nest_level = attr->parse_attr->filter_dev->lower_level -
4185 priv->netdev->lower_level;
35a605db 4186 while (nest_level--) {
c620b772 4187 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 4188 if (err)
4189 return err;
4190 }
4191
4192 return err;
4193}
4194
32134847
MD		 4195static bool same_hw_reps(struct mlx5e_priv *priv,
4196 struct net_device *peer_netdev)
4197{
4198 struct mlx5e_priv *peer_priv;
4199
4200 peer_priv = netdev_priv(peer_netdev);
4201
4202 return mlx5e_eswitch_rep(priv->netdev) &&
4203 mlx5e_eswitch_rep(peer_netdev) &&
4204 same_hw_devs(priv, peer_priv);
4205}
4206
4207static bool is_lag_dev(struct mlx5e_priv *priv,
4208 struct net_device *peer_netdev)
4209{
4210 return ((mlx5_lag_is_sriov(priv->mdev) ||
4211 mlx5_lag_is_multipath(priv->mdev)) &&
4212 same_hw_reps(priv, peer_netdev));
4213}
4214
f6dc1264
PB		 4215bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4216 struct net_device *out_dev)
4217{
32134847
MD		 4218 if (is_merged_eswitch_vfs(priv, out_dev))
4219 return true;
4220
4221 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 4222 return true;
4223
4224 return mlx5e_eswitch_rep(out_dev) &&
32134847 4225 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 4226}
4227
554fe75c
DL		 4228static bool is_duplicated_output_device(struct net_device *dev,
4229 struct net_device *out_dev,
4230 int *ifindexes, int if_count,
4231 struct netlink_ext_ack *extack)
4232{
4233 int i;
4234
4235 for (i = 0; i < if_count; i++) {
4236 if (ifindexes[i] == out_dev->ifindex) {
4237 NL_SET_ERR_MSG_MOD(extack,
4238 "can't duplicate output to same device");
4239 netdev_err(dev, "can't duplicate output to same device: %s\n",
4240 out_dev->name);
4241 return true;
4242 }
4243 }
4244
4245 return false;
4246}
4247
613f53fe
EC		 4248static int verify_uplink_forwarding(struct mlx5e_priv *priv,
4249 struct mlx5e_tc_flow *flow,
4250 struct net_device *out_dev,
4251 struct netlink_ext_ack *extack)
4252{
c620b772 4253 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 4254 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 4255 struct mlx5e_rep_priv *rep_priv;
4256
4257 /* Forwarding non encapsulated traffic between
4258 * uplink ports is allowed only if
4259 * termination_table_raw_traffic cap is set.
4260 *
c620b772 4261 * Input vport was stored attr->in_rep.
613f53fe
EC		 4262 * In LAG case, *priv* is the private data of
4263 * uplink which may be not the input vport.
4264 */
4265 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
4266
4267 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
4268 mlx5e_eswitch_uplink_rep(out_dev)))
4269 return 0;
4270
4271 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
4272 termination_table_raw_traffic)) {
4273 NL_SET_ERR_MSG_MOD(extack,
4274 "devices are both uplink, can't offload forwarding");
4275 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
4276 priv->netdev->name, out_dev->name);
4277 return -EOPNOTSUPP;
4278 } else if (out_dev != rep_priv->netdev) {
4279 NL_SET_ERR_MSG_MOD(extack,
4280 "devices are not the same uplink, can't offload forwarding");
4281 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
4282 priv->netdev->name, out_dev->name);
4283 return -EOPNOTSUPP;
4284 }
4285 return 0;
4286}
4287
73867881
PNA		 4288static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
4289 struct flow_action *flow_action,
e98bedf5 4290 struct mlx5e_tc_flow *flow,
14e6b038
EC		 4291 struct netlink_ext_ack *extack,
4292 struct net_device *filter_dev)
03a9d11e 4293{
73867881 4294 struct pedit_headers_action hdrs[2] = {};
bf07aa73 4295 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4296 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 4297 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 4298 const struct ip_tunnel_info *info = NULL;
c620b772 4299 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 4300 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 4301 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 4302 const struct flow_action_entry *act;
c620b772 4303 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 4304 bool encap = false, decap = false;
4305 u32 action = attr->action;
554fe75c 4306 int err, i, if_count = 0;
f828ca6a 4307 bool mpls_push = false;
03a9d11e 4308
73867881 4309 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 4310 return -EINVAL;
4311
53eca1f3
JK		 4312 if (!flow_action_hw_stats_check(flow_action, extack,
4313 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 4314 return -EOPNOTSUPP;
4315
c620b772
AL		 4316 esw_attr = attr->esw_attr;
4317 parse_attr = attr->parse_attr;
4318
73867881
PNA		 4319 flow_action_for_each(i, act, flow_action) {
4320 switch (act->id) {
4321 case FLOW_ACTION_DROP:
1cab1cd7
OG		 4322 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
4323 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 4324 break;
f0288210
EC		 4325 case FLOW_ACTION_TRAP:
4326 if (!flow_offload_has_one_action(flow_action)) {
4327 NL_SET_ERR_MSG_MOD(extack,
4328 "action trap is supported as a sole action only");
4329 return -EOPNOTSUPP;
4330 }
4331 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4332 MLX5_FLOW_CONTEXT_ACTION_COUNT);
4333 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
4334 break;
f828ca6a
EC		 4335 case FLOW_ACTION_MPLS_PUSH:
4336 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
4337 reformat_l2_to_l3_tunnel) ||
4338 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
4339 NL_SET_ERR_MSG_MOD(extack,
4340 "mpls push is supported only for mpls_uc protocol");
4341 return -EOPNOTSUPP;
4342 }
4343 mpls_push = true;
4344 break;
14e6b038
EC		 4345 case FLOW_ACTION_MPLS_POP:
4346 /* we only support mpls pop if it is the first action
4347 * and the filter net device is bareudp. Subsequent
4348 * actions can be pedit and the last can be mirred
4349 * egress redirect.
4350 */
4351 if (i) {
4352 NL_SET_ERR_MSG_MOD(extack,
4353 "mpls pop supported only as first action");
4354 return -EOPNOTSUPP;
4355 }
4356 if (!netif_is_bareudp(filter_dev)) {
4357 NL_SET_ERR_MSG_MOD(extack,
4358 "mpls pop supported only on bareudp devices");
4359 return -EOPNOTSUPP;
4360 }
4361
4362 parse_attr->eth.h_proto = act->mpls_pop.proto;
4363 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
4364 flow_flag_set(flow, L3_TO_L2_DECAP);
4365 break;
73867881
PNA		 4366 case FLOW_ACTION_MANGLE:
4367 case FLOW_ACTION_ADD:
4368 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 4369 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 4370 if (err)
4371 return err;
4372
582234b4
EC		 4373 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
4374 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 4375 esw_attr->split_count = esw_attr->out_count;
582234b4 4376 }
73867881
PNA		 4377 break;
4378 case FLOW_ACTION_CSUM:
1cab1cd7 4379 if (csum_offload_supported(priv, action,
73867881
PNA		 4380 act->csum_flags, extack))
4381 break;
26c02749
OG		 4382
4383 return -EOPNOTSUPP;
73867881
PNA		 4384 case FLOW_ACTION_REDIRECT:
4385 case FLOW_ACTION_MIRRED: {
03a9d11e 4386 struct mlx5e_priv *out_priv;
592d3651 4387 struct net_device *out_dev;
03a9d11e 4388
73867881 4389 out_dev = act->dev;
ef381359
OS		 4390 if (!out_dev) {
4391 /* out_dev is NULL when filters with
4392 * non-existing mirred device are replayed to
4393 * the driver.
4394 */
4395 return -EINVAL;
4396 }
03a9d11e 4397
f828ca6a
EC		 4398 if (mpls_push && !netif_is_bareudp(out_dev)) {
4399 NL_SET_ERR_MSG_MOD(extack,
4400 "mpls is supported only through a bareudp device");
4401 return -EOPNOTSUPP;
4402 }
4403
84179981
PB		 4404 if (ft_flow && out_dev == priv->netdev) {
4405 /* Ignore forward to self rules generated
4406 * by adding both mlx5 devs to the flow table
4407 * block on a normal nft offload setup.
4408 */
4409 return -EOPNOTSUPP;
4410 }
4411
c620b772 4412 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 4413 NL_SET_ERR_MSG_MOD(extack,
4414 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 4415 netdev_warn(priv->netdev,
4416 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 4417 esw_attr->out_count);
592d3651
CM		 4418 return -EOPNOTSUPP;
4419 }
4420
f493f155
EB		 4421 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4422 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 4423 if (encap) {
c620b772 4424 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 4425 out_dev->ifindex;
c620b772
AL		 4426 parse_attr->tun_info[esw_attr->out_count] = dup_tun_info(info);
4427 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 4428 return -ENOMEM;
4429 encap = false;
c620b772 4430 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 4431 MLX5_ESW_DEST_ENCAP;
c620b772 4432 esw_attr->out_count++;
b6a4ac24
VB		 4433 /* attr->dests[].rep is resolved when we
4434 * handle encap
4435 */
4436 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 4437 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4438 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 4439
554fe75c
DL		 4440 if (is_duplicated_output_device(priv->netdev,
4441 out_dev,
4442 ifindexes,
4443 if_count,
4444 extack))
4445 return -EOPNOTSUPP;
4446
4447 ifindexes[if_count] = out_dev->ifindex;
4448 if_count++;
4449
d34eb2fc
OG		 4450 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4451 if (!out_dev)
4452 return -ENODEV;
7ba58ba7 4453
278748a9
EB		 4454 if (is_vlan_dev(out_dev)) {
4455 err = add_vlan_push_action(priv, attr,
4456 &out_dev,
4457 &action);
4458 if (err)
4459 return err;
4460 }
f6dc1264 4461
35a605db
EB		 4462 if (is_vlan_dev(parse_attr->filter_dev)) {
4463 err = add_vlan_pop_action(priv, attr,
4464 &action);
4465 if (err)
4466 return err;
4467 }
278748a9 4468
613f53fe
EC		 4469 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4470 if (err)
4471 return err;
ffec9702 4472
f6dc1264
PB		 4473 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4474 NL_SET_ERR_MSG_MOD(extack,
4475 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4476 return -EOPNOTSUPP;
f6dc1264 4477 }
a0646c88 4478
a54e20b4 4479 out_priv = netdev_priv(out_dev);
1d447a39 4480 rpriv = out_priv->ppriv;
c620b772
AL		 4481 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
4482 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
4483 esw_attr->out_count++;
ef381359
OS		 4484 } else if (parse_attr->filter_dev != priv->netdev) {
4485 /* All mlx5 devices are called to configure
4486 * high level device filters. Therefore, the
4487 * *attempt* to install a filter on invalid
4488 * eswitch should not trigger an explicit error
4489 */
4490 return -EINVAL;
a54e20b4 4491 } else {
e98bedf5
EB		 4492 NL_SET_ERR_MSG_MOD(extack,
4493 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4494 netdev_warn(priv->netdev,
4495 "devices %s %s not on same switch HW, can't offload forwarding\n",
4496 priv->netdev->name,
4497 out_dev->name);
03a9d11e
OG		 4498 return -EINVAL;
4499 }
73867881
PNA		 4500 }
4501 break;
4502 case FLOW_ACTION_TUNNEL_ENCAP:
4503 info = act->tunnel;
a54e20b4
HHZ		 4504 if (info)
4505 encap = true;
4506 else
4507 return -EOPNOTSUPP;
1482bd3d 4508
73867881
PNA		 4509 break;
4510 case FLOW_ACTION_VLAN_PUSH:
4511 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4512 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4513 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4514 /* Replace vlan pop+push with vlan modify */
4515 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4516 err = add_vlan_rewrite_action(priv,
4517 MLX5_FLOW_NAMESPACE_FDB,
4518 act, parse_attr, hdrs,
4519 &action, extack);
4520 } else {
c620b772 4521 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 4522 }
1482bd3d
JL		 4523 if (err)
4524 return err;
4525
c620b772 4526 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 4527 break;
4528 case FLOW_ACTION_VLAN_MANGLE:
4529 err = add_vlan_rewrite_action(priv,
4530 MLX5_FLOW_NAMESPACE_FDB,
4531 act, parse_attr, hdrs,
4532 &action, extack);
4533 if (err)
4534 return err;
4535
c620b772 4536 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 4537 break;
4538 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4539 decap = true;
73867881 4540 break;
2fbbc30d 4541 case FLOW_ACTION_GOTO:
c7569097
AL		 4542 err = validate_goto_chain(priv, flow, act, action,
4543 extack);
2fbbc30d
EC		 4544 if (err)
4545 return err;
bf07aa73 4546
e88afe75 4547 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4548 attr->dest_chain = act->chain_index;
73867881 4549 break;
4c3844d9 4550 case FLOW_ACTION_CT:
aedd133d 4551 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4552 if (err)
4553 return err;
4554
4555 flow_flag_set(flow, CT);
4556 break;
73867881 4557 default:
2cc1cb1d
TZ		 4558 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4559 return -EOPNOTSUPP;
bf07aa73 4560 }
03a9d11e 4561 }
bdd66ac0 4562
a508728a
VB		 4563 if (decap && esw_attr->rx_tun_attr) {
4564 err = mlx5e_tc_tun_route_lookup(priv, &parse_attr->spec, attr);
4565 if (err)
4566 return err;
4567 }
4568
4569 /* always set IP version for indirect table handling */
4570 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4571
0bac1194
EB		 4572 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4573 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4574 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4575 * tag rewrite.
4576 */
4577 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4578 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4579 &action, extack);
4580 if (err)
4581 return err;
4582 }
4583
c500c86b
PNA		 4584 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4585 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4586 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4587 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4588 if (err)
4589 return err;
27c11b6b
EB		 4590 /* in case all pedit actions are skipped, remove the MOD_HDR
4591 * flag. we might have set split_count either by pedit or
4592 * pop/push. if there is no pop/push either, reset it too.
4593 */
6ae4a6a5 4594 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4595 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4596 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4597 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4598 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4599 esw_attr->split_count = 0;
27c11b6b 4600 }
c500c86b
PNA		 4601 }
4602
1cab1cd7 4603 attr->action = action;
73867881 4604 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4605 return -EOPNOTSUPP;
4606
e88afe75 4607 if (attr->dest_chain) {
0a7fcb78
PB		 4608 if (decap) {
4609 /* It can be supported if we'll create a mapping for
4610 * the tunnel device only (without tunnel), and set
4611 * this tunnel id with this decap flow.
4612 *
4613 * On restore (miss), we'll just set this saved tunnel
4614 * device.
4615 */
4616
4617 NL_SET_ERR_MSG(extack,
4618 "Decap with goto isn't supported");
4619 netdev_warn(priv->netdev,
4620 "Decap with goto isn't supported");
4621 return -EOPNOTSUPP;
4622 }
4623
e88afe75 4624 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 4625 NL_SET_ERR_MSG_MOD(extack,
4626 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 4627 return -EOPNOTSUPP;
4628 }
4629 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4630 }
4631
ae2741e2
VB		 4632 if (!(attr->action &
4633 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4634 NL_SET_ERR_MSG_MOD(extack,
4635 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4636 return -EOPNOTSUPP;
4637 }
4638
c620b772 4639 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4640 NL_SET_ERR_MSG_MOD(extack,
4641 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4642 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4643 return -EOPNOTSUPP;
4644 }
4645
31c8eba5 4646 return 0;
03a9d11e
OG		 4647}
4648
226f2ca3 4649static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4650{
226f2ca3 4651 unsigned long __flow_flags = 0;
60bd4af8 4652
226f2ca3
VB		 4653 if (flags & MLX5_TC_FLAG(INGRESS))
4654 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4655 if (flags & MLX5_TC_FLAG(EGRESS))
4656 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4657
226f2ca3
VB		 4658 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4659 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4660 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4661 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4662 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4663 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4664
60bd4af8
OG		 4665 *flow_flags = __flow_flags;
4666}
4667
05866c82
OG		 4668static const struct rhashtable_params tc_ht_params = {
4669 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4670 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4671 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4672 .automatic_shrinking = true,
4673};
4674
226f2ca3
VB		 4675static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4676 unsigned long flags)
05866c82 4677{
655dc3d2
OG		 4678 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4679 struct mlx5e_rep_priv *uplink_rpriv;
4680
226f2ca3 4681 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4682 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4683 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4684 } else /* NIC offload */
655dc3d2 4685 return &priv->fs.tc.ht;
05866c82
OG		 4686}
4687
04de7dda
RD		 4688static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4689{
c620b772
AL		 4690 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4691 struct mlx5_flow_attr *attr = flow->attr;
4692 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4693 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4694 bool act_is_encap = !!(attr->action &
4695 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4696 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4697 MLX5_DEVCOM_ESW_OFFLOADS);
4698
10fbb1cd
RD		 4699 if (!esw_paired)
4700 return false;
4701
c620b772
AL		 4702 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4703 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4704 (is_rep_ingress || act_is_encap))
4705 return true;
4706
4707 return false;
04de7dda
RD		 4708}
4709
c620b772
AL		 4710struct mlx5_flow_attr *
4711mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4712{
4713 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4714 sizeof(struct mlx5_esw_flow_attr) :
4715 sizeof(struct mlx5_nic_flow_attr);
4716 struct mlx5_flow_attr *attr;
4717
4718 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4719}
4720
a88780a9
RD		 4721static int
4722mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4723 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4724 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4725 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4726{
17091853 4727 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4728 struct mlx5_flow_attr *attr;
3bc4b7bf 4729 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4730 int err = -ENOMEM;
4731 int out_index;
e3a2b7ed 4732
c620b772 4733 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4734 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4735 if (!parse_attr || !flow)
4736 goto err_free;
c620b772
AL		 4737
4738 flow->flags = flow_flags;
4739 flow->cookie = f->cookie;
4740 flow->priv = priv;
4741
4742 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4743 if (!attr)
e3a2b7ed 4744 goto err_free;
ff7ea04a 4745
c620b772 4746 flow->attr = attr;
e3a2b7ed 4747
5a7e5bcb
VB		 4748 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4749 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4750 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4751 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4752 refcount_set(&flow->refcnt, 1);
95435ad7 4753 init_completion(&flow->init_done);
e3a2b7ed 4754
a88780a9
RD		 4755 *__flow = flow;
4756 *__parse_attr = parse_attr;
4757
4758 return 0;
4759
4760err_free:
4761 kfree(flow);
4762 kvfree(parse_attr);
4763 return err;
4764}
4765
c7569097
AL		 4766static void
4767mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4768 struct mlx5e_tc_flow_parse_attr *parse_attr,
4769 struct flow_cls_offload *f)
4770{
4771 attr->parse_attr = parse_attr;
4772 attr->chain = f->common.chain_index;
4773 attr->prio = f->common.prio;
4774}
4775
988ab9c7 4776static void
c620b772 4777mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4778 struct mlx5e_priv *priv,
4779 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4780 struct flow_cls_offload *f,
988ab9c7
TZ		 4781 struct mlx5_eswitch_rep *in_rep,
4782 struct mlx5_core_dev *in_mdev)
4783{
4784 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4785 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4786
c7569097 4787 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4788
4789 esw_attr->in_rep = in_rep;
4790 esw_attr->in_mdev = in_mdev;
4791
4792 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4793 MLX5_COUNTER_SOURCE_ESWITCH)
4794 esw_attr->counter_dev = in_mdev;
4795 else
4796 esw_attr->counter_dev = priv->mdev;
4797}
4798
71129676 4799static struct mlx5e_tc_flow *
04de7dda 4800__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4801 struct flow_cls_offload *f,
226f2ca3 4802 unsigned long flow_flags,
04de7dda
RD		 4803 struct net_device *filter_dev,
4804 struct mlx5_eswitch_rep *in_rep,
71129676 4805 struct mlx5_core_dev *in_mdev)
a88780a9 4806{
f9e30088 4807 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4808 struct netlink_ext_ack *extack = f->common.extack;
4809 struct mlx5e_tc_flow_parse_attr *parse_attr;
4810 struct mlx5e_tc_flow *flow;
4811 int attr_size, err;
e3a2b7ed 4812
226f2ca3 4813 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4814 attr_size = sizeof(struct mlx5_esw_flow_attr);
4815 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4816 &parse_attr, &flow);
4817 if (err)
4818 goto out;
988ab9c7 4819
d11afc26 4820 parse_attr->filter_dev = filter_dev;
c620b772 4821 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4822 priv, parse_attr,
4823 f, in_rep, in_mdev);
4824
54c177ca
OS		 4825 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4826 f, filter_dev);
d11afc26
OS		 4827 if (err)
4828 goto err_free;
a88780a9 4829
7e36feeb 4830 /* actions validation depends on parsing the ct matches first */
aedd133d 4831 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4832 &flow->attr->ct_attr, extack);
a88780a9
RD		 4833 if (err)
4834 goto err_free;
4835
7e36feeb 4836 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4837 if (err)
4838 goto err_free;
4839
7040632d 4840 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4841 complete_all(&flow->init_done);
ef06c9ee
RD		 4842 if (err) {
4843 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4844 goto err_free;
4845
b4a23329 4846 add_unready_flow(flow);
ef06c9ee 4847 }
e3a2b7ed 4848
71129676 4849 return flow;
a88780a9
RD		 4850
4851err_free:
e68e28b4 4852 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4853 mlx5e_flow_put(priv, flow);
a88780a9 4854out:
71129676 4855 return ERR_PTR(err);
a88780a9
RD		 4856}
4857
f9e30088 4858static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4859 struct mlx5e_tc_flow *flow,
226f2ca3 4860 unsigned long flow_flags)
04de7dda
RD		 4861{
4862 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4863 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4864 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4865 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4866 struct mlx5e_tc_flow_parse_attr *parse_attr;
4867 struct mlx5e_rep_priv *peer_urpriv;
4868 struct mlx5e_tc_flow *peer_flow;
4869 struct mlx5_core_dev *in_mdev;
4870 int err = 0;
4871
4872 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4873 if (!peer_esw)
4874 return -ENODEV;
4875
4876 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4877 peer_priv = netdev_priv(peer_urpriv->netdev);
4878
4879 /* in_mdev is assigned of which the packet originated from.
4880 * So packets redirected to uplink use the same mdev of the
4881 * original flow and packets redirected from uplink use the
4882 * peer mdev.
4883 */
c620b772 4884 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4885 in_mdev = peer_priv->mdev;
4886 else
4887 in_mdev = priv->mdev;
4888
c620b772 4889 parse_attr = flow->attr->parse_attr;
95dc1902 4890 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4891 parse_attr->filter_dev,
c620b772 4892 attr->in_rep, in_mdev);
71129676
JG		 4893 if (IS_ERR(peer_flow)) {
4894 err = PTR_ERR(peer_flow);
04de7dda 4895 goto out;
71129676 4896 }
04de7dda
RD		 4897
4898 flow->peer_flow = peer_flow;
226f2ca3 4899 flow_flag_set(flow, DUP);
04de7dda
RD		 4900 mutex_lock(&esw->offloads.peer_mutex);
4901 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4902 mutex_unlock(&esw->offloads.peer_mutex);
4903
4904out:
4905 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4906 return err;
4907}
4908
4909static int
4910mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4911 struct flow_cls_offload *f,
226f2ca3 4912 unsigned long flow_flags,
04de7dda
RD		 4913 struct net_device *filter_dev,
4914 struct mlx5e_tc_flow **__flow)
4915{
4916 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4917 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4918 struct mlx5_core_dev *in_mdev = priv->mdev;
4919 struct mlx5e_tc_flow *flow;
4920 int err;
4921
71129676
JG		 4922 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4923 in_mdev);
4924 if (IS_ERR(flow))
4925 return PTR_ERR(flow);
04de7dda
RD		 4926
4927 if (is_peer_flow_needed(flow)) {
95dc1902 4928 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4929 if (err) {
4930 mlx5e_tc_del_fdb_flow(priv, flow);
4931 goto out;
4932 }
4933 }
4934
4935 *__flow = flow;
4936
4937 return 0;
4938
4939out:
4940 return err;
4941}
4942
a88780a9
RD		 4943static int
4944mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4945 struct flow_cls_offload *f,
226f2ca3 4946 unsigned long flow_flags,
d11afc26 4947 struct net_device *filter_dev,
a88780a9
RD		 4948 struct mlx5e_tc_flow **__flow)
4949{
f9e30088 4950 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4951 struct netlink_ext_ack *extack = f->common.extack;
4952 struct mlx5e_tc_flow_parse_attr *parse_attr;
4953 struct mlx5e_tc_flow *flow;
4954 int attr_size, err;
4955
c7569097
AL		 4956 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4957 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4958 return -EOPNOTSUPP;
4959 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4960 return -EOPNOTSUPP;
c7569097 4961 }
bf07aa73 4962
226f2ca3 4963 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4964 attr_size = sizeof(struct mlx5_nic_flow_attr);
4965 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4966 &parse_attr, &flow);
4967 if (err)
4968 goto out;
4969
d11afc26 4970 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4971 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4972
54c177ca
OS		 4973 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4974 f, filter_dev);
d11afc26
OS		 4975 if (err)
4976 goto err_free;
4977
aedd133d
AL		 4978 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4979 &flow->attr->ct_attr, extack);
4980 if (err)
4981 goto err_free;
4982
73867881 4983 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4984 if (err)
4985 goto err_free;
4986
4987 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4988 if (err)
4989 goto err_free;
4990
226f2ca3 4991 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4992 *__flow = flow;
4993
4994 return 0;
e3a2b7ed 4995
e3a2b7ed 4996err_free:
e68e28b4 4997 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4998 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4999out:
5000 return err;
5001}
5002
5003static int
5004mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 5005 struct flow_cls_offload *f,
226f2ca3 5006 unsigned long flags,
d11afc26 5007 struct net_device *filter_dev,
a88780a9
RD		 5008 struct mlx5e_tc_flow **flow)
5009{
5010 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 5011 unsigned long flow_flags;
a88780a9
RD		 5012 int err;
5013
5014 get_flags(flags, &flow_flags);
5015
bf07aa73
PB		 5016 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
5017 return -EOPNOTSUPP;
5018
f6455de0 5019 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 5020 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
5021 filter_dev, flow);
a88780a9 5022 else
d11afc26
OS		 5023 err = mlx5e_add_nic_flow(priv, f, flow_flags,
5024 filter_dev, flow);
a88780a9
RD		 5025
5026 return err;
5027}
5028
553f9328
VP		 5029static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
5030 struct mlx5e_rep_priv *rpriv)
5031{
5032 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 5033 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
5034 * function is called from NIC mode.
553f9328 5035 */
2fb15e72 5036 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 5037}
5038
71d82d2a 5039int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 5040 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 5041{
5042 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 5043 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 5044 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 5045 struct mlx5e_tc_flow *flow;
5046 int err = 0;
5047
c5d326b2
VB		 5048 rcu_read_lock();
5049 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 5050 if (flow) {
553f9328
VP		 5051 /* Same flow rule offloaded to non-uplink representor sharing tc block,
5052 * just return 0.
5053 */
5054 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 5055 goto rcu_unlock;
553f9328 5056
a88780a9
RD		 5057 NL_SET_ERR_MSG_MOD(extack,
5058 "flow cookie already exists, ignoring");
5059 netdev_warn_once(priv->netdev,
5060 "flow cookie %lx already exists, ignoring\n",
5061 f->cookie);
0e1c1a2f 5062 err = -EEXIST;
c1aea9e1 5063 goto rcu_unlock;
a88780a9 5064 }
c1aea9e1
VB		 5065rcu_unlock:
5066 rcu_read_unlock();
5067 if (flow)
5068 goto out;
a88780a9 5069
7a978759 5070 trace_mlx5e_configure_flower(f);
d11afc26 5071 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 5072 if (err)
5073 goto out;
5074
553f9328
VP		 5075 /* Flow rule offloaded to non-uplink representor sharing tc block,
5076 * set the flow's owner dev.
5077 */
5078 if (is_flow_rule_duplicate_allowed(dev, rpriv))
5079 flow->orig_dev = dev;
5080
c5d326b2 5081 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 5082 if (err)
5083 goto err_free;
5084
5085 return 0;
5086
5087err_free:
5a7e5bcb 5088 mlx5e_flow_put(priv, flow);
a88780a9 5089out:
e3a2b7ed
AV		 5090 return err;
5091}
5092
8f8ae895
OG		 5093static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
5094{
226f2ca3
VB		 5095 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
5096 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 5097
226f2ca3
VB		 5098 return flow_flag_test(flow, INGRESS) == dir_ingress &&
5099 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 5100}
5101
71d82d2a 5102int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 5103 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 5104{
d9ee0491 5105 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 5106 struct mlx5e_tc_flow *flow;
c5d326b2 5107 int err;
e3a2b7ed 5108
c5d326b2 5109 rcu_read_lock();
ab818362 5110 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 5111 if (!flow || !same_flow_direction(flow, flags)) {
5112 err = -EINVAL;
5113 goto errout;
5114 }
e3a2b7ed 5115
c5d326b2
VB		 5116 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
5117 * set.
5118 */
5119 if (flow_flag_test_and_set(flow, DELETED)) {
5120 err = -EINVAL;
5121 goto errout;
5122 }
05866c82 5123 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 5124 rcu_read_unlock();
e3a2b7ed 5125
7a978759 5126 trace_mlx5e_delete_flower(f);
5a7e5bcb 5127 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 5128
5129 return 0;
c5d326b2
VB		 5130
5131errout:
5132 rcu_read_unlock();
5133 return err;
e3a2b7ed
AV		 5134}
5135
71d82d2a 5136int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 5137 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 5138{
04de7dda 5139 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 5140 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 5141 struct mlx5_eswitch *peer_esw;
aad7e08d 5142 struct mlx5e_tc_flow *flow;
aad7e08d 5143 struct mlx5_fc *counter;
316d5f72
RD		 5144 u64 lastuse = 0;
5145 u64 packets = 0;
5146 u64 bytes = 0;
5a7e5bcb 5147 int err = 0;
aad7e08d 5148
c5d326b2
VB		 5149 rcu_read_lock();
5150 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
5151 tc_ht_params));
5152 rcu_read_unlock();
5a7e5bcb
VB		 5153 if (IS_ERR(flow))
5154 return PTR_ERR(flow);
5155
5156 if (!same_flow_direction(flow, flags)) {
5157 err = -EINVAL;
5158 goto errout;
5159 }
aad7e08d 5160
4c3844d9 5161 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 5162 counter = mlx5e_tc_get_counter(flow);
5163 if (!counter)
5a7e5bcb 5164 goto errout;
aad7e08d 5165
316d5f72
RD		 5166 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
5167 }
aad7e08d 5168
316d5f72
RD		 5169 /* Under multipath it's possible for one rule to be currently
5170 * un-offloaded while the other rule is offloaded.
5171 */
04de7dda
RD		 5172 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
5173 if (!peer_esw)
5174 goto out;
5175
226f2ca3
VB		 5176 if (flow_flag_test(flow, DUP) &&
5177 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 5178 u64 bytes2;
5179 u64 packets2;
5180 u64 lastuse2;
5181
5182 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 5183 if (!counter)
5184 goto no_peer_counter;
04de7dda
RD		 5185 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
5186
5187 bytes += bytes2;
5188 packets += packets2;
5189 lastuse = max_t(u64, lastuse, lastuse2);
5190 }
5191
316d5f72 5192no_peer_counter:
04de7dda 5193 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 5194out:
4b61d3e8 5195 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 5196 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 5197 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 5198errout:
5199 mlx5e_flow_put(priv, flow);
5200 return err;
aad7e08d
AV		 5201}
5202
1fe3e316 5203static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 5204 struct netlink_ext_ack *extack)
5205{
5206 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5207 struct mlx5_eswitch *esw;
1fe3e316 5208 u32 rate_mbps = 0;
fcb64c0f 5209 u16 vport_num;
fcb64c0f
EC		 5210 int err;
5211
e401a184
EC		 5212 vport_num = rpriv->rep->vport;
5213 if (vport_num >= MLX5_VPORT_ECPF) {
5214 NL_SET_ERR_MSG_MOD(extack,
5215 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5216 return -EOPNOTSUPP;
5217 }
5218
fcb64c0f
EC		 5219 esw = priv->mdev->priv.eswitch;
5220 /* rate is given in bytes/sec.
5221 * First convert to bits/sec and then round to the nearest mbit/secs.
5222 * mbit means million bits.
5223 * Moreover, if rate is non zero we choose to configure to a minimum of
5224 * 1 mbit/sec.
5225 */
1fe3e316
PP		 5226 if (rate) {
5227 rate = (rate * BITS_PER_BYTE) + 500000;
5228 rate_mbps = max_t(u32, do_div(rate, 1000000), 1);
5229 }
5230
fcb64c0f
EC		 5231 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
5232 if (err)
5233 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5234
5235 return err;
5236}
5237
5238static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5239 struct flow_action *flow_action,
5240 struct netlink_ext_ack *extack)
5241{
5242 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5243 const struct flow_action_entry *act;
5244 int err;
5245 int i;
5246
5247 if (!flow_action_has_entries(flow_action)) {
5248 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5249 return -EINVAL;
5250 }
5251
5252 if (!flow_offload_has_one_action(flow_action)) {
5253 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5254 return -EOPNOTSUPP;
5255 }
5256
53eca1f3 5257 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 5258 return -EOPNOTSUPP;
5259
fcb64c0f
EC		 5260 flow_action_for_each(i, act, flow_action) {
5261 switch (act->id) {
5262 case FLOW_ACTION_POLICE:
5263 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5264 if (err)
5265 return err;
5266
5267 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
5268 break;
5269 default:
5270 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5271 return -EOPNOTSUPP;
5272 }
5273 }
5274
5275 return 0;
5276}
5277
5278int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5279 struct tc_cls_matchall_offload *ma)
5280{
b5f814cc 5281 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 5282 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 5283
b5f814cc
EC		 5284 if (!mlx5_esw_qos_enabled(esw)) {
5285 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
5286 return -EOPNOTSUPP;
5287 }
5288
7b83355f 5289 if (ma->common.prio != 1) {
fcb64c0f
EC		 5290 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5291 return -EINVAL;
5292 }
5293
5294 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5295}
5296
5297int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5298 struct tc_cls_matchall_offload *ma)
5299{
5300 struct netlink_ext_ack *extack = ma->common.extack;
5301
5302 return apply_police_params(priv, 0, extack);
5303}
5304
5305void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5306 struct tc_cls_matchall_offload *ma)
5307{
5308 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5309 struct rtnl_link_stats64 cur_stats;
5310 u64 dbytes;
5311 u64 dpkts;
5312
5313 cur_stats = priv->stats.vf_vport;
5314 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5315 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5316 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 5317 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 5318 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 5319}
5320
4d8fcf21
AH		 5321static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5322 struct mlx5e_priv *peer_priv)
5323{
5324 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 5325 struct mlx5e_hairpin_entry *hpe, *tmp;
5326 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 5327 u16 peer_vhca_id;
5328 int bkt;
5329
5330 if (!same_hw_devs(priv, peer_priv))
5331 return;
5332
5333 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5334
b32accda 5335 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 5336 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
5337 if (refcount_inc_not_zero(&hpe->refcnt))
5338 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5339 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5340
5341 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5342 wait_for_completion(&hpe->res_ready);
5343 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 5344 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 5345
5346 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 5347 }
5348}
5349
5350static int mlx5e_tc_netdev_event(struct notifier_block *this,
5351 unsigned long event, void *ptr)
5352{
5353 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5354 struct mlx5e_flow_steering *fs;
5355 struct mlx5e_priv *peer_priv;
5356 struct mlx5e_tc_table *tc;
5357 struct mlx5e_priv *priv;
5358
5359 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5360 event != NETDEV_UNREGISTER ||
5361 ndev->reg_state == NETREG_REGISTERED)
5362 return NOTIFY_DONE;
5363
5364 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5365 fs = container_of(tc, struct mlx5e_flow_steering, tc);
5366 priv = container_of(fs, struct mlx5e_priv, fs);
5367 peer_priv = netdev_priv(ndev);
5368 if (priv == peer_priv ||
5369 !(priv->netdev->features & NETIF_F_HW_TC))
5370 return NOTIFY_DONE;
5371
5372 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5373
5374 return NOTIFY_DONE;
5375}
5376
6a064674
AL		 5377static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
5378{
5379 int tc_grp_size, tc_tbl_size;
5380 u32 max_flow_counter;
5381
5382 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
5383 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
5384
5385 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
5386
5387 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
5388 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
5389
5390 return tc_tbl_size;
5391}
5392
655dc3d2 5393int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 5394{
acff797c 5395 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674
AL		 5396 struct mlx5_core_dev *dev = priv->mdev;
5397 struct mlx5_chains_attr attr = {};
4d8fcf21 5398 int err;
e8f887ac 5399
b2fdf3d0 5400 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 5401 mutex_init(&tc->t_lock);
b32accda 5402 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 5403 hash_init(tc->hairpin_tbl);
11c9c548 5404
4d8fcf21
AH		 5405 err = rhashtable_init(&tc->ht, &tc_ht_params);
5406 if (err)
5407 return err;
5408
9ba33339
RD		 5409 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5410
c7569097
AL		 5411 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
5412 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5413 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5414 attr.max_restore_tag = MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5415 }
6a064674
AL		 5416 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5417 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
5418 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5419 attr.default_ft = priv->fs.vlan.ft.t;
5420
5421 tc->chains = mlx5_chains_create(dev, &attr);
5422 if (IS_ERR(tc->chains)) {
5423 err = PTR_ERR(tc->chains);
5424 goto err_chains;
5425 }
5426
aedd133d
AL		 5427 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
5428 MLX5_FLOW_NAMESPACE_KERNEL);
68ec32da
WH		 5429 if (IS_ERR(tc->ct)) {
5430 err = PTR_ERR(tc->ct);
aedd133d 5431 goto err_ct;
68ec32da 5432 }
aedd133d 5433
4d8fcf21 5434 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 5435 err = register_netdevice_notifier_dev_net(priv->netdev,
5436 &tc->netdevice_nb,
5437 &tc->netdevice_nn);
5438 if (err) {
4d8fcf21
AH		 5439 tc->netdevice_nb.notifier_call = NULL;
5440 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 5441 goto err_reg;
4d8fcf21
AH		 5442 }
5443
6a064674
AL		 5444 return 0;
5445
5446err_reg:
aedd133d
AL		 5447 mlx5_tc_ct_clean(tc->ct);
5448err_ct:
6a064674
AL		 5449 mlx5_chains_destroy(tc->chains);
5450err_chains:
5451 rhashtable_destroy(&tc->ht);
4d8fcf21 5452 return err;
e8f887ac
AV		 5453}
5454
5455static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5456{
5457 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5458 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5459
961e8979 5460 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5461 kfree(flow);
5462}
5463
655dc3d2 5464void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5465{
acff797c 5466 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5467
4d8fcf21 5468 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5469 unregister_netdevice_notifier_dev_net(priv->netdev,
5470 &tc->netdevice_nb,
5471 &tc->netdevice_nn);
4d8fcf21 5472
b2fdf3d0 5473 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 5474 mutex_destroy(&tc->hairpin_tbl_lock);
5475
6a064674 5476 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 5477
acff797c 5478 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 5479 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 5480 tc->t = NULL;
e8f887ac 5481 }
b6fac0b4 5482 mutex_destroy(&tc->t_lock);
6a064674 5483
aedd133d 5484 mlx5_tc_ct_clean(tc->ct);
6a064674 5485 mlx5_chains_destroy(tc->chains);
e8f887ac 5486}
655dc3d2
OG		 5487
5488int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5489{
d7a42ad0 5490 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 5491 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 5492 struct mlx5e_rep_priv *rpriv;
0a7fcb78 5493 struct mapping_ctx *mapping;
aedd133d
AL		 5494 struct mlx5_eswitch *esw;
5495 struct mlx5e_priv *priv;
5496 int err = 0;
0a7fcb78
PB		 5497
5498 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5499 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5500 priv = netdev_priv(rpriv->netdev);
5501 esw = priv->mdev->priv.eswitch;
0a7fcb78 5502
aedd133d
AL		 5503 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5504 esw_chains(esw),
5505 &esw->offloads.mod_hdr,
5506 MLX5_FLOW_NAMESPACE_FDB);
5507 if (IS_ERR(uplink_priv->ct_priv))
4c3844d9
PB		 5508 goto err_ct;
5509
0a7fcb78
PB		 5510 mapping = mapping_create(sizeof(struct tunnel_match_key),
5511 TUNNEL_INFO_BITS_MASK, true);
5512 if (IS_ERR(mapping)) {
5513 err = PTR_ERR(mapping);
5514 goto err_tun_mapping;
5515 }
5516 uplink_priv->tunnel_mapping = mapping;
5517
5518 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
5519 if (IS_ERR(mapping)) {
5520 err = PTR_ERR(mapping);
5521 goto err_enc_opts_mapping;
5522 }
5523 uplink_priv->tunnel_enc_opts_mapping = mapping;
5524
5525 err = rhashtable_init(tc_ht, &tc_ht_params);
5526 if (err)
5527 goto err_ht_init;
5528
9ba33339
RD		 5529 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5530
0a7fcb78
PB		 5531 return err;
5532
5533err_ht_init:
5534 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5535err_enc_opts_mapping:
5536 mapping_destroy(uplink_priv->tunnel_mapping);
5537err_tun_mapping:
aedd133d 5538 mlx5_tc_ct_clean(uplink_priv->ct_priv);
4c3844d9 5539err_ct:
0a7fcb78
PB		 5540 netdev_warn(priv->netdev,
5541 "Failed to initialize tc (eswitch), err: %d", err);
5542 return err;
655dc3d2
OG		 5543}
5544
5545void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5546{
0a7fcb78
PB		 5547 struct mlx5_rep_uplink_priv *uplink_priv;
5548
655dc3d2 5549 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 5550
5551 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5552
0a7fcb78
PB		 5553 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5554 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5555
aedd133d 5556 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 5557}
01252a27 5558
226f2ca3 5559int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5560{
d9ee0491 5561 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5562
5563 return atomic_read(&tc_ht->nelems);
5564}
04de7dda
RD		 5565
5566void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5567{
5568 struct mlx5e_tc_flow *flow, *tmp;
5569
5570 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5571 __mlx5e_tc_del_fdb_peer_flow(flow);
5572}
b4a23329
RD		 5573
5574void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5575{
5576 struct mlx5_rep_uplink_priv *rpriv =
5577 container_of(work, struct mlx5_rep_uplink_priv,
5578 reoffload_flows_work);
5579 struct mlx5e_tc_flow *flow, *tmp;
5580
ad86755b 5581 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5582 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5583 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5584 unready_flow_del(flow);
b4a23329 5585 }
ad86755b 5586 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5587}
e2394a61
VB		 5588
5589static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5590 struct flow_cls_offload *cls_flower,
5591 unsigned long flags)
5592{
5593 switch (cls_flower->command) {
5594 case FLOW_CLS_REPLACE:
5595 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5596 flags);
5597 case FLOW_CLS_DESTROY:
5598 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5599 flags);
5600 case FLOW_CLS_STATS:
5601 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5602 flags);
5603 default:
5604 return -EOPNOTSUPP;
5605 }
5606}
5607
5608int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5609 void *cb_priv)
5610{
5611 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
5612 struct mlx5e_priv *priv = cb_priv;
5613
5614 switch (type) {
5615 case TC_SETUP_CLSFLOWER:
5616 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5617 default:
5618 return -EOPNOTSUPP;
5619 }
5620}
c7569097
AL		 5621
5622bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5623 struct sk_buff *skb)
5624{
5625#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5626 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5627 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5628 struct mlx5e_tc_table *tc = &priv->fs.tc;
c7569097
AL		 5629 struct tc_skb_ext *tc_skb_ext;
5630 int err;
5631
5632 reg_b = be32_to_cpu(cqe->ft_metadata);
5633
5634 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5635
5636 err = mlx5_get_chain_for_tag(nic_chains(priv), chain_tag, &chain);
5637 if (err) {
5638 netdev_dbg(priv->netdev,
5639 "Couldn't find chain for chain tag: %d, err: %d\n",
5640 chain_tag, err);
5641 return false;
5642 }
5643
5644 if (chain) {
5645 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
5646 if (WARN_ON(!tc_skb_ext))
5647 return false;
5648
5649 tc_skb_ext->chain = chain;
aedd133d
AL		 5650
5651 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5652 ESW_ZONE_ID_MASK;
aedd133d
AL		 5653
5654 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5655 zone_restore_id))
5656 return false;
c7569097
AL		 5657 }
5658#endif /* CONFIG_NET_TC_SKB_EXT */
5659
5660 return true;
5661}
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