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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
f6dfb4c3 47#include <net/arp.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
3f6d08d1 52#include "fs_core.h"
2c81bfd5 53#include "en/port.h"
101f4de9 54#include "en/tc_tun.h"
04de7dda 55#include "lib/devcom.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
72 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
73 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
5dbe906f 77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 5),
04de7dda 78 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 6),
65ba8fb7
OG		 79};
80
e4ad91f2
CM		 81#define MLX5E_TC_MAX_SPLITS 1
82
79baaec7
EB		 83/* Helper struct for accessing a struct containing list_head array.
84 * Containing struct
85 * |- Helper array
86 * [0] Helper item 0
87 * |- list_head item 0
88 * |- index (0)
89 * [1] Helper item 1
90 * |- list_head item 1
91 * |- index (1)
92 * To access the containing struct from one of the list_head items:
93 * 1. Get the helper item from the list_head item using
94 * helper item =
95 * container_of(list_head item, helper struct type, list_head field)
96 * 2. Get the contining struct from the helper item and its index in the array:
97 * containing struct =
98 * container_of(helper item, containing struct type, helper field[index])
99 */
100struct encap_flow_item {
101 struct list_head list;
102 int index;
103};
104
e8f887ac
AV		 105struct mlx5e_tc_flow {
106 struct rhash_head node;
655dc3d2 107 struct mlx5e_priv *priv;
e8f887ac 108 u64 cookie;
5dbe906f 109 u16 flags;
e4ad91f2 110 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 111 /* Flow can be associated with multiple encap IDs.
112 * The number of encaps is bounded by the number of supported
113 * destinations.
114 */
115 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 116 struct mlx5e_tc_flow *peer_flow;
11c9c548 117 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 118 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 119 struct list_head peer; /* flows with peer flow */
3bc4b7bf
OG		 120 union {
121 struct mlx5_esw_flow_attr esw_attr[0];
122 struct mlx5_nic_flow_attr nic_attr[0];
123 };
e8f887ac
AV		 124};
125
17091853 126struct mlx5e_tc_flow_parse_attr {
98b66cb1 127 struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 128 struct net_device *filter_dev;
17091853 129 struct mlx5_flow_spec spec;
d79b6df6
OG		 130 int num_mod_hdr_actions;
131 void *mod_hdr_actions;
98b66cb1 132 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 133};
134
acff797c 135#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 136#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 137
77ab67b7
OG		 138struct mlx5e_hairpin {
139 struct mlx5_hairpin *pair;
140
141 struct mlx5_core_dev *func_mdev;
3f6d08d1 142 struct mlx5e_priv *func_priv;
77ab67b7
OG		 143 u32 tdn;
144 u32 tirn;
3f6d08d1
OG		 145
146 int num_channels;
147 struct mlx5e_rqt indir_rqt;
148 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
149 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 150};
151
5c65c564
OG		 152struct mlx5e_hairpin_entry {
153 /* a node of a hash table which keeps all the hairpin entries */
154 struct hlist_node hairpin_hlist;
155
156 /* flows sharing the same hairpin */
157 struct list_head flows;
158
d8822868 159 u16 peer_vhca_id;
106be53b 160 u8 prio;
5c65c564
OG		 161 struct mlx5e_hairpin *hp;
162};
163
11c9c548
OG		 164struct mod_hdr_key {
165 int num_actions;
166 void *actions;
167};
168
169struct mlx5e_mod_hdr_entry {
170 /* a node of a hash table which keeps all the mod_hdr entries */
171 struct hlist_node mod_hdr_hlist;
172
173 /* flows sharing the same mod_hdr entry */
174 struct list_head flows;
175
176 struct mod_hdr_key key;
177
178 u32 mod_hdr_id;
179};
180
181#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
182
183static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
184{
185 return jhash(key->actions,
186 key->num_actions * MLX5_MH_ACT_SZ, 0);
187}
188
189static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
190 struct mod_hdr_key *b)
191{
192 if (a->num_actions != b->num_actions)
193 return 1;
194
195 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
196}
197
198static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
199 struct mlx5e_tc_flow *flow,
200 struct mlx5e_tc_flow_parse_attr *parse_attr)
201{
202 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
203 int num_actions, actions_size, namespace, err;
204 struct mlx5e_mod_hdr_entry *mh;
205 struct mod_hdr_key key;
206 bool found = false;
207 u32 hash_key;
208
209 num_actions = parse_attr->num_mod_hdr_actions;
210 actions_size = MLX5_MH_ACT_SZ * num_actions;
211
212 key.actions = parse_attr->mod_hdr_actions;
213 key.num_actions = num_actions;
214
215 hash_key = hash_mod_hdr_info(&key);
216
217 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
218 namespace = MLX5_FLOW_NAMESPACE_FDB;
219 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
220 mod_hdr_hlist, hash_key) {
221 if (!cmp_mod_hdr_info(&mh->key, &key)) {
222 found = true;
223 break;
224 }
225 }
226 } else {
227 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
228 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
229 mod_hdr_hlist, hash_key) {
230 if (!cmp_mod_hdr_info(&mh->key, &key)) {
231 found = true;
232 break;
233 }
234 }
235 }
236
237 if (found)
238 goto attach_flow;
239
240 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
241 if (!mh)
242 return -ENOMEM;
243
244 mh->key.actions = (void *)mh + sizeof(*mh);
245 memcpy(mh->key.actions, key.actions, actions_size);
246 mh->key.num_actions = num_actions;
247 INIT_LIST_HEAD(&mh->flows);
248
249 err = mlx5_modify_header_alloc(priv->mdev, namespace,
250 mh->key.num_actions,
251 mh->key.actions,
252 &mh->mod_hdr_id);
253 if (err)
254 goto out_err;
255
256 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
257 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
258 else
259 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
260
261attach_flow:
262 list_add(&flow->mod_hdr, &mh->flows);
263 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
264 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
265 else
266 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
267
268 return 0;
269
270out_err:
271 kfree(mh);
272 return err;
273}
274
275static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
276 struct mlx5e_tc_flow *flow)
277{
278 struct list_head *next = flow->mod_hdr.next;
279
280 list_del(&flow->mod_hdr);
281
282 if (list_empty(next)) {
283 struct mlx5e_mod_hdr_entry *mh;
284
285 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
286
287 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
288 hash_del(&mh->mod_hdr_hlist);
289 kfree(mh);
290 }
291}
292
77ab67b7
OG		 293static
294struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
295{
296 struct net_device *netdev;
297 struct mlx5e_priv *priv;
298
299 netdev = __dev_get_by_index(net, ifindex);
300 priv = netdev_priv(netdev);
301 return priv->mdev;
302}
303
304static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
305{
306 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
307 void *tirc;
308 int err;
309
310 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
311 if (err)
312 goto alloc_tdn_err;
313
314 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
315
316 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 317 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 318 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
319
320 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
321 if (err)
322 goto create_tir_err;
323
324 return 0;
325
326create_tir_err:
327 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
328alloc_tdn_err:
329 return err;
330}
331
332static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
333{
334 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
335 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
336}
337
3f6d08d1
OG		 338static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
339{
340 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
341 struct mlx5e_priv *priv = hp->func_priv;
342 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
343
344 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
345 hp->num_channels);
346
347 for (i = 0; i < sz; i++) {
348 ix = i;
bbeb53b8 349 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 350 ix = mlx5e_bits_invert(i, ilog2(sz));
351 ix = indirection_rqt[ix];
352 rqn = hp->pair->rqn[ix];
353 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
354 }
355}
356
357static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
358{
359 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
360 struct mlx5e_priv *priv = hp->func_priv;
361 struct mlx5_core_dev *mdev = priv->mdev;
362 void *rqtc;
363 u32 *in;
364
365 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
366 in = kvzalloc(inlen, GFP_KERNEL);
367 if (!in)
368 return -ENOMEM;
369
370 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
371
372 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
373 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
374
375 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
376
377 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
378 if (!err)
379 hp->indir_rqt.enabled = true;
380
381 kvfree(in);
382 return err;
383}
384
385static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
386{
387 struct mlx5e_priv *priv = hp->func_priv;
388 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
389 int tt, i, err;
390 void *tirc;
391
392 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 393 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
394
3f6d08d1
OG		 395 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
396 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
397
398 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
399 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
400 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 401 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
402
3f6d08d1
OG		 403 err = mlx5_core_create_tir(hp->func_mdev, in,
404 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
405 if (err) {
406 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
407 goto err_destroy_tirs;
408 }
409 }
410 return 0;
411
412err_destroy_tirs:
413 for (i = 0; i < tt; i++)
414 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
415 return err;
416}
417
418static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
419{
420 int tt;
421
422 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
423 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
424}
425
426static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
427 struct ttc_params *ttc_params)
428{
429 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
430 int tt;
431
432 memset(ttc_params, 0, sizeof(*ttc_params));
433
434 ttc_params->any_tt_tirn = hp->tirn;
435
436 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
437 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
438
439 ft_attr->max_fte = MLX5E_NUM_TT;
440 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
441 ft_attr->prio = MLX5E_TC_PRIO;
442}
443
444static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
445{
446 struct mlx5e_priv *priv = hp->func_priv;
447 struct ttc_params ttc_params;
448 int err;
449
450 err = mlx5e_hairpin_create_indirect_rqt(hp);
451 if (err)
452 return err;
453
454 err = mlx5e_hairpin_create_indirect_tirs(hp);
455 if (err)
456 goto err_create_indirect_tirs;
457
458 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
459 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
460 if (err)
461 goto err_create_ttc_table;
462
463 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
464 hp->num_channels, hp->ttc.ft.t->id);
465
466 return 0;
467
468err_create_ttc_table:
469 mlx5e_hairpin_destroy_indirect_tirs(hp);
470err_create_indirect_tirs:
471 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
472
473 return err;
474}
475
476static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
477{
478 struct mlx5e_priv *priv = hp->func_priv;
479
480 mlx5e_destroy_ttc_table(priv, &hp->ttc);
481 mlx5e_hairpin_destroy_indirect_tirs(hp);
482 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
483}
484
77ab67b7
OG		 485static struct mlx5e_hairpin *
486mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
487 int peer_ifindex)
488{
489 struct mlx5_core_dev *func_mdev, *peer_mdev;
490 struct mlx5e_hairpin *hp;
491 struct mlx5_hairpin *pair;
492 int err;
493
494 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
495 if (!hp)
496 return ERR_PTR(-ENOMEM);
497
498 func_mdev = priv->mdev;
499 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
500
501 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
502 if (IS_ERR(pair)) {
503 err = PTR_ERR(pair);
504 goto create_pair_err;
505 }
506 hp->pair = pair;
507 hp->func_mdev = func_mdev;
3f6d08d1
OG		 508 hp->func_priv = priv;
509 hp->num_channels = params->num_channels;
77ab67b7
OG		 510
511 err = mlx5e_hairpin_create_transport(hp);
512 if (err)
513 goto create_transport_err;
514
3f6d08d1
OG		 515 if (hp->num_channels > 1) {
516 err = mlx5e_hairpin_rss_init(hp);
517 if (err)
518 goto rss_init_err;
519 }
520
77ab67b7
OG		 521 return hp;
522
3f6d08d1
OG		 523rss_init_err:
524 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 525create_transport_err:
526 mlx5_core_hairpin_destroy(hp->pair);
527create_pair_err:
528 kfree(hp);
529 return ERR_PTR(err);
530}
531
532static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
533{
3f6d08d1
OG		 534 if (hp->num_channels > 1)
535 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 536 mlx5e_hairpin_destroy_transport(hp);
537 mlx5_core_hairpin_destroy(hp->pair);
538 kvfree(hp);
539}
540
106be53b
OG		 541static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
542{
543 return (peer_vhca_id << 16 | prio);
544}
545
5c65c564 546static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 547 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 548{
549 struct mlx5e_hairpin_entry *hpe;
106be53b 550 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 551
552 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 553 hairpin_hlist, hash_key) {
554 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 555 return hpe;
556 }
557
558 return NULL;
559}
560
106be53b
OG		 561#define UNKNOWN_MATCH_PRIO 8
562
563static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 564 struct mlx5_flow_spec *spec, u8 *match_prio,
565 struct netlink_ext_ack *extack)
106be53b
OG		 566{
567 void *headers_c, *headers_v;
568 u8 prio_val, prio_mask = 0;
569 bool vlan_present;
570
571#ifdef CONFIG_MLX5_CORE_EN_DCB
572 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 573 NL_SET_ERR_MSG_MOD(extack,
574 "only PCP trust state supported for hairpin");
106be53b
OG		 575 return -EOPNOTSUPP;
576 }
577#endif
578 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
579 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
580
581 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
582 if (vlan_present) {
583 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
584 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
585 }
586
587 if (!vlan_present || !prio_mask) {
588 prio_val = UNKNOWN_MATCH_PRIO;
589 } else if (prio_mask != 0x7) {
e98bedf5
EB		 590 NL_SET_ERR_MSG_MOD(extack,
591 "masked priority match not supported for hairpin");
106be53b
OG		 592 return -EOPNOTSUPP;
593 }
594
595 *match_prio = prio_val;
596 return 0;
597}
598
5c65c564
OG		 599static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
600 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 601 struct mlx5e_tc_flow_parse_attr *parse_attr,
602 struct netlink_ext_ack *extack)
5c65c564 603{
98b66cb1 604 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 605 struct mlx5_hairpin_params params;
d8822868 606 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 607 struct mlx5e_hairpin_entry *hpe;
608 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 609 u64 link_speed64;
610 u32 link_speed;
106be53b 611 u8 match_prio;
d8822868 612 u16 peer_id;
5c65c564
OG		 613 int err;
614
d8822868
OG		 615 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
616 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 617 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 618 return -EOPNOTSUPP;
619 }
620
d8822868 621 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 622 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
623 extack);
106be53b
OG		 624 if (err)
625 return err;
626 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 627 if (hpe)
628 goto attach_flow;
629
630 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
631 if (!hpe)
632 return -ENOMEM;
633
634 INIT_LIST_HEAD(&hpe->flows);
d8822868 635 hpe->peer_vhca_id = peer_id;
106be53b 636 hpe->prio = match_prio;
5c65c564
OG		 637
638 params.log_data_size = 15;
639 params.log_data_size = min_t(u8, params.log_data_size,
640 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
641 params.log_data_size = max_t(u8, params.log_data_size,
642 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 643
eb9180f7
OG		 644 params.log_num_packets = params.log_data_size -
645 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
646 params.log_num_packets = min_t(u8, params.log_num_packets,
647 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
648
649 params.q_counter = priv->q_counter;
3f6d08d1 650 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 651 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 652 link_speed = max_t(u32, link_speed, 50000);
653 link_speed64 = link_speed;
654 do_div(link_speed64, 50000);
655 params.num_channels = link_speed64;
656
5c65c564
OG		 657 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
658 if (IS_ERR(hp)) {
659 err = PTR_ERR(hp);
660 goto create_hairpin_err;
661 }
662
eb9180f7 663 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 664 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 665 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 666
667 hpe->hp = hp;
106be53b
OG		 668 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
669 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 670
671attach_flow:
3f6d08d1
OG		 672 if (hpe->hp->num_channels > 1) {
673 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
674 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
675 } else {
676 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
677 }
5c65c564 678 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 679
5c65c564
OG		 680 return 0;
681
682create_hairpin_err:
683 kfree(hpe);
684 return err;
685}
686
687static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
688 struct mlx5e_tc_flow *flow)
689{
690 struct list_head *next = flow->hairpin.next;
691
692 list_del(&flow->hairpin);
693
694 /* no more hairpin flows for us, release the hairpin pair */
695 if (list_empty(next)) {
696 struct mlx5e_hairpin_entry *hpe;
697
698 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
699
700 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
701 hpe->hp->pair->peer_mdev->priv.name);
702
703 mlx5e_hairpin_destroy(hpe->hp);
704 hash_del(&hpe->hairpin_hlist);
705 kfree(hpe);
706 }
707}
708
c83954ab 709static int
74491de9 710mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 711 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 712 struct mlx5e_tc_flow *flow,
713 struct netlink_ext_ack *extack)
e8f887ac 714{
aa0cbbae 715 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 716 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 717 struct mlx5_flow_destination dest[2] = {};
66958ed9 718 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 719 .action = attr->action,
720 .flow_tag = attr->flow_tag,
60786f09 721 .reformat_id = 0,
42f7ad67 722 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 723 };
aad7e08d 724 struct mlx5_fc *counter = NULL;
e8f887ac 725 bool table_created = false;
5c65c564 726 int err, dest_ix = 0;
e8f887ac 727
3f6d08d1 728 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 729 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 730 if (err) {
3f6d08d1
OG		 731 goto err_add_hairpin_flow;
732 }
733 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
734 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
735 dest[dest_ix].ft = attr->hairpin_ft;
736 } else {
5c65c564
OG		 737 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
738 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 739 }
740 dest_ix++;
3f6d08d1
OG		 741 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
742 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
743 dest[dest_ix].ft = priv->fs.vlan.ft.t;
744 dest_ix++;
5c65c564 745 }
aad7e08d 746
5c65c564
OG		 747 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
748 counter = mlx5_fc_create(dev, true);
749 if (IS_ERR(counter)) {
c83954ab 750 err = PTR_ERR(counter);
5c65c564
OG		 751 goto err_fc_create;
752 }
753 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 754 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 755 dest_ix++;
b8aee822 756 attr->counter = counter;
aad7e08d
AV		 757 }
758
2f4fe4ca 759 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 760 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 761 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 762 kfree(parse_attr->mod_hdr_actions);
c83954ab 763 if (err)
2f4fe4ca 764 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 765 }
766
acff797c 767 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 768 int tc_grp_size, tc_tbl_size;
769 u32 max_flow_counter;
770
771 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
772 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
773
774 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
775
776 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
777 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
778
acff797c
MG		 779 priv->fs.tc.t =
780 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
781 MLX5E_TC_PRIO,
21b9c144 782 tc_tbl_size,
acff797c 783 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 784 MLX5E_TC_FT_LEVEL, 0);
acff797c 785 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 786 NL_SET_ERR_MSG_MOD(extack,
787 "Failed to create tc offload table\n");
e8f887ac
AV		 788 netdev_err(priv->netdev,
789 "Failed to create tc offload table\n");
c83954ab 790 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 791 goto err_create_ft;
e8f887ac
AV		 792 }
793
794 table_created = true;
795 }
796
38aa51c1
OG		 797 if (attr->match_level != MLX5_MATCH_NONE)
798 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
799
c83954ab
RL		 800 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
801 &flow_act, dest, dest_ix);
aad7e08d 802
c83954ab
RL		 803 if (IS_ERR(flow->rule[0])) {
804 err = PTR_ERR(flow->rule[0]);
aad7e08d 805 goto err_add_rule;
c83954ab 806 }
aad7e08d 807
c83954ab 808 return 0;
e8f887ac 809
aad7e08d
AV		 810err_add_rule:
811 if (table_created) {
acff797c
MG		 812 mlx5_destroy_flow_table(priv->fs.tc.t);
813 priv->fs.tc.t = NULL;
e8f887ac 814 }
aad7e08d 815err_create_ft:
2f4fe4ca 816 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 817 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 818err_create_mod_hdr_id:
aad7e08d 819 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 820err_fc_create:
821 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
822 mlx5e_hairpin_flow_del(priv, flow);
823err_add_hairpin_flow:
c83954ab 824 return err;
e8f887ac
AV		 825}
826
d85cdccb
OG		 827static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
828 struct mlx5e_tc_flow *flow)
829{
513f8f7f 830 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 831 struct mlx5_fc *counter = NULL;
832
b8aee822 833 counter = attr->counter;
e4ad91f2 834 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 835 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 836
b3a433de 837 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 838 mlx5_destroy_flow_table(priv->fs.tc.t);
839 priv->fs.tc.t = NULL;
840 }
2f4fe4ca 841
513f8f7f 842 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 843 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 844
845 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
846 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 847}
848
aa0cbbae 849static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 850 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 851
3c37745e
OG		 852static int mlx5e_attach_encap(struct mlx5e_priv *priv,
853 struct ip_tunnel_info *tun_info,
854 struct net_device *mirred_dev,
855 struct net_device **encap_dev,
e98bedf5 856 struct mlx5e_tc_flow *flow,
8c4dc42b
EB		 857 struct netlink_ext_ack *extack,
858 int out_index);
3c37745e 859
6d2a3ed0
OG		 860static struct mlx5_flow_handle *
861mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
862 struct mlx5e_tc_flow *flow,
863 struct mlx5_flow_spec *spec,
864 struct mlx5_esw_flow_attr *attr)
865{
866 struct mlx5_flow_handle *rule;
867
868 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
869 if (IS_ERR(rule))
870 return rule;
871
e85e02ba 872 if (attr->split_count) {
6d2a3ed0
OG		 873 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
874 if (IS_ERR(flow->rule[1])) {
875 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
876 return flow->rule[1];
877 }
878 }
879
880 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
881 return rule;
882}
883
884static void
885mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
886 struct mlx5e_tc_flow *flow,
887 struct mlx5_esw_flow_attr *attr)
888{
889 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
890
e85e02ba 891 if (attr->split_count)
6d2a3ed0
OG		 892 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
893
894 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
895}
896
5dbe906f
PB		 897static struct mlx5_flow_handle *
898mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
899 struct mlx5e_tc_flow *flow,
900 struct mlx5_flow_spec *spec,
901 struct mlx5_esw_flow_attr *slow_attr)
902{
903 struct mlx5_flow_handle *rule;
904
905 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
906 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
e85e02ba 907 slow_attr->split_count = 0,
5dbe906f
PB		 908 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN,
909
910 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
911 if (!IS_ERR(rule))
912 flow->flags |= MLX5E_TC_FLOW_SLOW;
913
914 return rule;
915}
916
917static void
918mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
919 struct mlx5e_tc_flow *flow,
920 struct mlx5_esw_flow_attr *slow_attr)
921{
922 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
923 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
924 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
925}
926
c83954ab 927static int
74491de9 928mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 929 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 930 struct mlx5e_tc_flow *flow,
931 struct netlink_ext_ack *extack)
adb4c123
OG		 932{
933 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 934 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 935 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
bf07aa73 936 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 937 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 938 struct mlx5_fc *counter = NULL;
3c37745e
OG		 939 struct mlx5e_rep_priv *rpriv;
940 struct mlx5e_priv *out_priv;
c83954ab 941 int err = 0, encap_err = 0;
f493f155 942 int out_index;
8b32580d 943
bf07aa73
PB		 944 /* if prios are not supported, keep the old behaviour of using same prio
945 * for all offloaded rules.
946 */
947 if (!mlx5_eswitch_prios_supported(esw))
948 attr->prio = 1;
949
950 if (attr->chain > max_chain) {
951 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
952 err = -EOPNOTSUPP;
953 goto err_max_prio_chain;
954 }
955
956 if (attr->prio > max_prio) {
957 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
958 err = -EOPNOTSUPP;
959 goto err_max_prio_chain;
960 }
e52c2802 961
f493f155 962 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 963 int mirred_ifindex;
964
f493f155
EB		 965 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
966 continue;
967
8c4dc42b 968 mirred_ifindex = attr->parse_attr->mirred_ifindex[out_index];
3c37745e 969 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b
EB		 970 mirred_ifindex);
971 err = mlx5e_attach_encap(priv,
972 &parse_attr->tun_info[out_index],
973 out_dev, &encap_dev, flow,
974 extack, out_index);
975 if (err && err != -EAGAIN)
c83954ab 976 goto err_attach_encap;
8c4dc42b
EB		 977 if (err == -EAGAIN)
978 encap_err = err;
3c37745e
OG		 979 out_priv = netdev_priv(encap_dev);
980 rpriv = out_priv->ppriv;
1cc26d74
EB		 981 attr->dests[out_index].rep = rpriv->rep;
982 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 983 }
984
8b32580d 985 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 986 if (err)
aa0cbbae 987 goto err_add_vlan;
adb4c123 988
d7e75a32 989 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 990 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 991 kfree(parse_attr->mod_hdr_actions);
c83954ab 992 if (err)
d7e75a32 993 goto err_mod_hdr;
d7e75a32
OG		 994 }
995
b8aee822 996 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 997 counter = mlx5_fc_create(attr->counter_dev, true);
b8aee822 998 if (IS_ERR(counter)) {
c83954ab 999 err = PTR_ERR(counter);
b8aee822
MB		 1000 goto err_create_counter;
1001 }
1002
1003 attr->counter = counter;
1004 }
1005
c83954ab 1006 /* we get here if (1) there's no error or when
3c37745e
OG		 1007 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
1008 */
5dbe906f
PB		 1009 if (encap_err == -EAGAIN) {
1010 /* continue with goto slow path rule instead */
1011 struct mlx5_esw_flow_attr slow_attr;
1012
1013 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1014 } else {
6d2a3ed0 1015 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1016 }
c83954ab 1017
5dbe906f
PB		 1018 if (IS_ERR(flow->rule[0])) {
1019 err = PTR_ERR(flow->rule[0]);
1020 goto err_add_rule;
1021 }
1022
1023 return 0;
aa0cbbae
OG		 1024
1025err_add_rule:
f9392795 1026 mlx5_fc_destroy(attr->counter_dev, counter);
b8aee822 1027err_create_counter:
513f8f7f 1028 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1029 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 1030err_mod_hdr:
aa0cbbae
OG		 1031 mlx5_eswitch_del_vlan_action(esw, attr);
1032err_add_vlan:
f493f155 1033 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1034 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1035 mlx5e_detach_encap(priv, flow, out_index);
3c37745e 1036err_attach_encap:
bf07aa73 1037err_max_prio_chain:
c83954ab 1038 return err;
aa0cbbae 1039}
d85cdccb
OG		 1040
1041static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1042 struct mlx5e_tc_flow *flow)
1043{
1044 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1045 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1046 struct mlx5_esw_flow_attr slow_attr;
f493f155 1047 int out_index;
d85cdccb 1048
5dbe906f
PB		 1049 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1050 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1051 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1052 else
1053 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1054 }
d85cdccb 1055
513f8f7f 1056 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1057
f493f155 1058 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1059 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1060 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1061 kvfree(attr->parse_attr);
d7e75a32 1062
513f8f7f 1063 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1064 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1065
1066 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1067 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1068}
1069
232c0013
HHZ		 1070void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1071 struct mlx5e_encap_entry *e)
1072{
3c37745e 1073 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1074 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1075 struct mlx5_flow_handle *rule;
1076 struct mlx5_flow_spec *spec;
79baaec7 1077 struct encap_flow_item *efi;
232c0013
HHZ		 1078 struct mlx5e_tc_flow *flow;
1079 int err;
1080
54c177ca
OS		 1081 err = mlx5_packet_reformat_alloc(priv->mdev,
1082 e->reformat_type,
60786f09 1083 e->encap_size, e->encap_header,
31ca3648 1084 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1085 &e->encap_id);
232c0013
HHZ		 1086 if (err) {
1087 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1088 err);
1089 return;
1090 }
1091 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1092 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1093
79baaec7 1094 list_for_each_entry(efi, &e->flows, list) {
8c4dc42b
EB		 1095 bool all_flow_encaps_valid = true;
1096 int i;
1097
79baaec7 1098 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
3c37745e 1099 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1100 spec = &esw_attr->parse_attr->spec;
1101
8c4dc42b
EB		 1102 esw_attr->dests[efi->index].encap_id = e->encap_id;
1103 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1104 /* Flow can be associated with multiple encap entries.
1105 * Before offloading the flow verify that all of them have
1106 * a valid neighbour.
1107 */
1108 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1109 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1110 continue;
1111 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1112 all_flow_encaps_valid = false;
1113 break;
1114 }
1115 }
1116 /* Do not offload flows with unresolved neighbors */
1117 if (!all_flow_encaps_valid)
1118 continue;
5dbe906f 1119 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1120 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1121 if (IS_ERR(rule)) {
1122 err = PTR_ERR(rule);
232c0013
HHZ		 1123 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1124 err);
1125 continue;
1126 }
5dbe906f
PB		 1127
1128 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1129 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1130 flow->rule[0] = rule;
232c0013
HHZ		 1131 }
1132}
1133
1134void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1135 struct mlx5e_encap_entry *e)
1136{
3c37745e 1137 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1138 struct mlx5_esw_flow_attr slow_attr;
1139 struct mlx5_flow_handle *rule;
1140 struct mlx5_flow_spec *spec;
79baaec7 1141 struct encap_flow_item *efi;
232c0013 1142 struct mlx5e_tc_flow *flow;
5dbe906f 1143 int err;
232c0013 1144
79baaec7
EB		 1145 list_for_each_entry(efi, &e->flows, list) {
1146 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5dbe906f
PB		 1147 spec = &flow->esw_attr->parse_attr->spec;
1148
1149 /* update from encap rule to slow path rule */
1150 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1151 /* mark the flow's encap dest as non-valid */
1152 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1153
1154 if (IS_ERR(rule)) {
1155 err = PTR_ERR(rule);
1156 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1157 err);
1158 continue;
1159 }
1160
1161 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1162 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1163 flow->rule[0] = rule;
232c0013
HHZ		 1164 }
1165
1166 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
1167 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
60786f09 1168 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1169 }
1170}
1171
b8aee822
MB		 1172static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1173{
1174 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1175 return flow->esw_attr->counter;
1176 else
1177 return flow->nic_attr->counter;
1178}
1179
f6dfb4c3
HHZ		 1180void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1181{
1182 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1183 u64 bytes, packets, lastuse = 0;
1184 struct mlx5e_tc_flow *flow;
1185 struct mlx5e_encap_entry *e;
1186 struct mlx5_fc *counter;
1187 struct neigh_table *tbl;
1188 bool neigh_used = false;
1189 struct neighbour *n;
1190
1191 if (m_neigh->family == AF_INET)
1192 tbl = &arp_tbl;
1193#if IS_ENABLED(CONFIG_IPV6)
1194 else if (m_neigh->family == AF_INET6)
423c9db2 1195 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1196#endif
1197 else
1198 return;
1199
1200 list_for_each_entry(e, &nhe->encap_list, encap_list) {
79baaec7 1201 struct encap_flow_item *efi;
f6dfb4c3
HHZ		 1202 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1203 continue;
79baaec7
EB		 1204 list_for_each_entry(efi, &e->flows, list) {
1205 flow = container_of(efi, struct mlx5e_tc_flow,
1206 encaps[efi->index]);
f6dfb4c3 1207 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1208 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1209 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1210 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1211 neigh_used = true;
1212 break;
1213 }
1214 }
1215 }
e36d4810
RD		 1216 if (neigh_used)
1217 break;
f6dfb4c3
HHZ		 1218 }
1219
1220 if (neigh_used) {
1221 nhe->reported_lastuse = jiffies;
1222
1223 /* find the relevant neigh according to the cached device and
1224 * dst ip pair
1225 */
1226 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1227 if (!n)
f6dfb4c3 1228 return;
f6dfb4c3
HHZ		 1229
1230 neigh_event_send(n, NULL);
1231 neigh_release(n);
1232 }
1233}
1234
d85cdccb 1235static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1236 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1237{
8c4dc42b 1238 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1239
8c4dc42b 1240 list_del(&flow->encaps[out_index].list);
5067b602 1241 if (list_empty(next)) {
c1ae1152 1242 struct mlx5e_encap_entry *e;
5067b602 1243
c1ae1152 1244 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1245 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1246
1247 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1248 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1249
cdc5a7f3 1250 hash_del_rcu(&e->encap_hlist);
232c0013 1251 kfree(e->encap_header);
5067b602
RD		 1252 kfree(e);
1253 }
1254}
1255
04de7dda
RD		 1256static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1257{
1258 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1259
1260 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1261 !(flow->flags & MLX5E_TC_FLOW_DUP))
1262 return;
1263
1264 mutex_lock(&esw->offloads.peer_mutex);
1265 list_del(&flow->peer);
1266 mutex_unlock(&esw->offloads.peer_mutex);
1267
1268 flow->flags &= ~MLX5E_TC_FLOW_DUP;
1269
1270 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1271 kvfree(flow->peer_flow);
1272 flow->peer_flow = NULL;
1273}
1274
1275static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1276{
1277 struct mlx5_core_dev *dev = flow->priv->mdev;
1278 struct mlx5_devcom *devcom = dev->priv.devcom;
1279 struct mlx5_eswitch *peer_esw;
1280
1281 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1282 if (!peer_esw)
1283 return;
1284
1285 __mlx5e_tc_del_fdb_peer_flow(flow);
1286 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1287}
1288
e8f887ac 1289static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1290 struct mlx5e_tc_flow *flow)
e8f887ac 1291{
04de7dda
RD		 1292 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1293 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1294 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1295 } else {
d85cdccb 1296 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1297 }
e8f887ac
AV		 1298}
1299
bbd00f7e
HHZ		 1300
1301static int parse_tunnel_attr(struct mlx5e_priv *priv,
1302 struct mlx5_flow_spec *spec,
54c177ca
OS		 1303 struct tc_cls_flower_offload *f,
1304 struct net_device *filter_dev)
bbd00f7e 1305{
e98bedf5 1306 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1307 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1308 outer_headers);
1309 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1310 outer_headers);
1311
2e72eb43
OG		 1312 struct flow_dissector_key_control *enc_control =
1313 skb_flow_dissector_target(f->dissector,
1314 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1315 f->key);
54c177ca 1316 int err = 0;
2e72eb43 1317
101f4de9
OS		 1318 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1319 headers_c, headers_v);
54c177ca
OS		 1320 if (err) {
1321 NL_SET_ERR_MSG_MOD(extack,
1322 "failed to parse tunnel attributes");
101f4de9 1323 return err;
bbd00f7e
HHZ		 1324 }
1325
2e72eb43 1326 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1327 struct flow_dissector_key_ipv4_addrs *key =
1328 skb_flow_dissector_target(f->dissector,
1329 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1330 f->key);
1331 struct flow_dissector_key_ipv4_addrs *mask =
1332 skb_flow_dissector_target(f->dissector,
1333 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1334 f->mask);
1335 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1336 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1337 ntohl(mask->src));
1338 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1339 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1340 ntohl(key->src));
1341
1342 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1343 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1344 ntohl(mask->dst));
1345 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1346 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1347 ntohl(key->dst));
bbd00f7e 1348
2e72eb43
OG		 1349 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1350 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1351 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1352 struct flow_dissector_key_ipv6_addrs *key =
1353 skb_flow_dissector_target(f->dissector,
1354 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1355 f->key);
1356 struct flow_dissector_key_ipv6_addrs *mask =
1357 skb_flow_dissector_target(f->dissector,
1358 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1359 f->mask);
1360
1361 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1362 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1363 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1364 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1365 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1366 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1367
1368 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1369 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1370 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1371 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1372 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1373 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1374
1375 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1376 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1377 }
bbd00f7e 1378
bcef735c
OG		 1379 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1380 struct flow_dissector_key_ip *key =
1381 skb_flow_dissector_target(f->dissector,
1382 FLOW_DISSECTOR_KEY_ENC_IP,
1383 f->key);
1384 struct flow_dissector_key_ip *mask =
1385 skb_flow_dissector_target(f->dissector,
1386 FLOW_DISSECTOR_KEY_ENC_IP,
1387 f->mask);
1388
1389 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1390 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1391
1392 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1393 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1394
1395 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1396 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
e98bedf5
EB		 1397
1398 if (mask->ttl &&
1399 !MLX5_CAP_ESW_FLOWTABLE_FDB
1400 (priv->mdev,
1401 ft_field_support.outer_ipv4_ttl)) {
1402 NL_SET_ERR_MSG_MOD(extack,
1403 "Matching on TTL is not supported");
1404 return -EOPNOTSUPP;
1405 }
1406
bcef735c
OG		 1407 }
1408
bbd00f7e
HHZ		 1409 /* Enforce DMAC when offloading incoming tunneled flows.
1410 * Flow counters require a match on the DMAC.
1411 */
1412 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1413 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1414 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1415 dmac_47_16), priv->netdev->dev_addr);
1416
1417 /* let software handle IP fragments */
1418 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1419 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1420
1421 return 0;
1422}
1423
de0af0bf
RD		 1424static int __parse_cls_flower(struct mlx5e_priv *priv,
1425 struct mlx5_flow_spec *spec,
1426 struct tc_cls_flower_offload *f,
54c177ca 1427 struct net_device *filter_dev,
d708f902 1428 u8 *match_level)
e3a2b7ed 1429{
e98bedf5 1430 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1431 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1432 outer_headers);
1433 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1434 outer_headers);
699e96dd
JL		 1435 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1436 misc_parameters);
1437 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1438 misc_parameters);
e3a2b7ed
AV		 1439 u16 addr_type = 0;
1440 u8 ip_proto = 0;
1441
d708f902 1442 *match_level = MLX5_MATCH_NONE;
de0af0bf 1443
e3a2b7ed
AV		 1444 if (f->dissector->used_keys &
1445 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1446 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1447 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1448 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1449 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1450 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1451 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1452 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1453 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1454 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1455 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1456 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1457 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1458 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1459 BIT(FLOW_DISSECTOR_KEY_IP) |
1460 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1461 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed
AV		 1462 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1463 f->dissector->used_keys);
1464 return -EOPNOTSUPP;
1465 }
1466
bbd00f7e
HHZ		 1467 if ((dissector_uses_key(f->dissector,
1468 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1469 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1470 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1471 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1472 struct flow_dissector_key_control *key =
1473 skb_flow_dissector_target(f->dissector,
1474 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1475 f->key);
1476 switch (key->addr_type) {
1477 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1478 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
54c177ca 1479 if (parse_tunnel_attr(priv, spec, f, filter_dev))
bbd00f7e
HHZ		 1480 return -EOPNOTSUPP;
1481 break;
1482 default:
1483 return -EOPNOTSUPP;
1484 }
1485
1486 /* In decap flow, header pointers should point to the inner
1487 * headers, outer header were already set by parse_tunnel_attr
1488 */
1489 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1490 inner_headers);
1491 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1492 inner_headers);
1493 }
1494
d3a80bb5
OG		 1495 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1496 struct flow_dissector_key_basic *key =
e3a2b7ed 1497 skb_flow_dissector_target(f->dissector,
d3a80bb5 1498 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1499 f->key);
d3a80bb5 1500 struct flow_dissector_key_basic *mask =
e3a2b7ed 1501 skb_flow_dissector_target(f->dissector,
d3a80bb5 1502 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1503 f->mask);
d3a80bb5
OG		 1504 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1505 ntohs(mask->n_proto));
1506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1507 ntohs(key->n_proto));
e3a2b7ed 1508
d3a80bb5 1509 if (mask->n_proto)
d708f902 1510 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1511 }
1512
095b6cfd
OG		 1513 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1514 struct flow_dissector_key_vlan *key =
1515 skb_flow_dissector_target(f->dissector,
1516 FLOW_DISSECTOR_KEY_VLAN,
1517 f->key);
1518 struct flow_dissector_key_vlan *mask =
1519 skb_flow_dissector_target(f->dissector,
1520 FLOW_DISSECTOR_KEY_VLAN,
1521 f->mask);
699e96dd
JL		 1522 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1523 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1524 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1525 svlan_tag, 1);
1526 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1527 svlan_tag, 1);
1528 } else {
1529 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1530 cvlan_tag, 1);
1531 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1532 cvlan_tag, 1);
1533 }
095b6cfd
OG		 1534
1535 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1537
1538 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1540
d708f902 1541 *match_level = MLX5_MATCH_L2;
54782900 1542 }
d3a80bb5 1543 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1544 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1545 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1546 *match_level = MLX5_MATCH_L2;
54782900
OG		 1547 }
1548
699e96dd
JL		 1549 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1550 struct flow_dissector_key_vlan *key =
1551 skb_flow_dissector_target(f->dissector,
1552 FLOW_DISSECTOR_KEY_CVLAN,
1553 f->key);
1554 struct flow_dissector_key_vlan *mask =
1555 skb_flow_dissector_target(f->dissector,
1556 FLOW_DISSECTOR_KEY_CVLAN,
1557 f->mask);
1558 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1559 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1560 MLX5_SET(fte_match_set_misc, misc_c,
1561 outer_second_svlan_tag, 1);
1562 MLX5_SET(fte_match_set_misc, misc_v,
1563 outer_second_svlan_tag, 1);
1564 } else {
1565 MLX5_SET(fte_match_set_misc, misc_c,
1566 outer_second_cvlan_tag, 1);
1567 MLX5_SET(fte_match_set_misc, misc_v,
1568 outer_second_cvlan_tag, 1);
1569 }
1570
1571 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1572 mask->vlan_id);
1573 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1574 key->vlan_id);
1575 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1576 mask->vlan_priority);
1577 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1578 key->vlan_priority);
1579
1580 *match_level = MLX5_MATCH_L2;
1581 }
1582 }
1583
d3a80bb5
OG		 1584 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1585 struct flow_dissector_key_eth_addrs *key =
54782900 1586 skb_flow_dissector_target(f->dissector,
d3a80bb5 1587 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1588 f->key);
d3a80bb5 1589 struct flow_dissector_key_eth_addrs *mask =
54782900 1590 skb_flow_dissector_target(f->dissector,
d3a80bb5 1591 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1592 f->mask);
54782900 1593
d3a80bb5
OG		 1594 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1595 dmac_47_16),
1596 mask->dst);
1597 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1598 dmac_47_16),
1599 key->dst);
1600
1601 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1602 smac_47_16),
1603 mask->src);
1604 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1605 smac_47_16),
1606 key->src);
1607
1608 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1609 *match_level = MLX5_MATCH_L2;
54782900
OG		 1610 }
1611
1612 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1613 struct flow_dissector_key_control *key =
1614 skb_flow_dissector_target(f->dissector,
1615 FLOW_DISSECTOR_KEY_CONTROL,
1616 f->key);
1617
1618 struct flow_dissector_key_control *mask =
1619 skb_flow_dissector_target(f->dissector,
1620 FLOW_DISSECTOR_KEY_CONTROL,
1621 f->mask);
1622 addr_type = key->addr_type;
1623
1624 /* the HW doesn't support frag first/later */
1625 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1626 return -EOPNOTSUPP;
1627
1628 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1629 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1630 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1631 key->flags & FLOW_DIS_IS_FRAGMENT);
1632
1633 /* the HW doesn't need L3 inline to match on frag=no */
1634 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1635 *match_level = MLX5_MATCH_L2;
54782900
OG		 1636 /* *** L2 attributes parsing up to here *** */
1637 else
83621b7d 1638 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1639 }
1640 }
1641
54782900
OG		 1642 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1643 struct flow_dissector_key_basic *key =
1644 skb_flow_dissector_target(f->dissector,
1645 FLOW_DISSECTOR_KEY_BASIC,
1646 f->key);
1647 struct flow_dissector_key_basic *mask =
1648 skb_flow_dissector_target(f->dissector,
1649 FLOW_DISSECTOR_KEY_BASIC,
1650 f->mask);
1651 ip_proto = key->ip_proto;
1652
1653 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1654 mask->ip_proto);
1655 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1656 key->ip_proto);
1657
1658 if (mask->ip_proto)
d708f902 1659 *match_level = MLX5_MATCH_L3;
54782900
OG		 1660 }
1661
e3a2b7ed
AV		 1662 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1663 struct flow_dissector_key_ipv4_addrs *key =
1664 skb_flow_dissector_target(f->dissector,
1665 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1666 f->key);
1667 struct flow_dissector_key_ipv4_addrs *mask =
1668 skb_flow_dissector_target(f->dissector,
1669 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1670 f->mask);
1671
1672 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1673 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1674 &mask->src, sizeof(mask->src));
1675 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1676 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1677 &key->src, sizeof(key->src));
1678 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1679 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1680 &mask->dst, sizeof(mask->dst));
1681 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1682 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1683 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1684
1685 if (mask->src || mask->dst)
d708f902 1686 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1687 }
1688
1689 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1690 struct flow_dissector_key_ipv6_addrs *key =
1691 skb_flow_dissector_target(f->dissector,
1692 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1693 f->key);
1694 struct flow_dissector_key_ipv6_addrs *mask =
1695 skb_flow_dissector_target(f->dissector,
1696 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1697 f->mask);
1698
1699 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1700 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1701 &mask->src, sizeof(mask->src));
1702 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1703 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1704 &key->src, sizeof(key->src));
1705
1706 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1707 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1708 &mask->dst, sizeof(mask->dst));
1709 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1710 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1711 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1712
1713 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1714 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1715 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1716 }
1717
1f97a526
OG		 1718 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1719 struct flow_dissector_key_ip *key =
1720 skb_flow_dissector_target(f->dissector,
1721 FLOW_DISSECTOR_KEY_IP,
1722 f->key);
1723 struct flow_dissector_key_ip *mask =
1724 skb_flow_dissector_target(f->dissector,
1725 FLOW_DISSECTOR_KEY_IP,
1726 f->mask);
1727
1728 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1729 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1730
1731 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1733
a8ade55f
OG		 1734 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1735 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1736
a8ade55f
OG		 1737 if (mask->ttl &&
1738 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1739 ft_field_support.outer_ipv4_ttl)) {
1740 NL_SET_ERR_MSG_MOD(extack,
1741 "Matching on TTL is not supported");
1f97a526 1742 return -EOPNOTSUPP;
e98bedf5 1743 }
a8ade55f
OG		 1744
1745 if (mask->tos || mask->ttl)
d708f902 1746 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1747 }
1748
54782900
OG		 1749 /* *** L3 attributes parsing up to here *** */
1750
e3a2b7ed
AV		 1751 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1752 struct flow_dissector_key_ports *key =
1753 skb_flow_dissector_target(f->dissector,
1754 FLOW_DISSECTOR_KEY_PORTS,
1755 f->key);
1756 struct flow_dissector_key_ports *mask =
1757 skb_flow_dissector_target(f->dissector,
1758 FLOW_DISSECTOR_KEY_PORTS,
1759 f->mask);
1760 switch (ip_proto) {
1761 case IPPROTO_TCP:
1762 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1763 tcp_sport, ntohs(mask->src));
1764 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1765 tcp_sport, ntohs(key->src));
1766
1767 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1768 tcp_dport, ntohs(mask->dst));
1769 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1770 tcp_dport, ntohs(key->dst));
1771 break;
1772
1773 case IPPROTO_UDP:
1774 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1775 udp_sport, ntohs(mask->src));
1776 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1777 udp_sport, ntohs(key->src));
1778
1779 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1780 udp_dport, ntohs(mask->dst));
1781 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1782 udp_dport, ntohs(key->dst));
1783 break;
1784 default:
e98bedf5
EB		 1785 NL_SET_ERR_MSG_MOD(extack,
1786 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1787 netdev_err(priv->netdev,
1788 "Only UDP and TCP transport are supported\n");
1789 return -EINVAL;
1790 }
de0af0bf
RD		 1791
1792 if (mask->src || mask->dst)
d708f902 1793 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1794 }
1795
e77834ec
OG		 1796 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1797 struct flow_dissector_key_tcp *key =
1798 skb_flow_dissector_target(f->dissector,
1799 FLOW_DISSECTOR_KEY_TCP,
1800 f->key);
1801 struct flow_dissector_key_tcp *mask =
1802 skb_flow_dissector_target(f->dissector,
1803 FLOW_DISSECTOR_KEY_TCP,
1804 f->mask);
1805
1806 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1807 ntohs(mask->flags));
1808 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1809 ntohs(key->flags));
1810
1811 if (mask->flags)
d708f902 1812 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1813 }
1814
e3a2b7ed
AV		 1815 return 0;
1816}
1817
de0af0bf 1818static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1819 struct mlx5e_tc_flow *flow,
de0af0bf 1820 struct mlx5_flow_spec *spec,
54c177ca
OS		 1821 struct tc_cls_flower_offload *f,
1822 struct net_device *filter_dev)
de0af0bf 1823{
e98bedf5 1824 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1825 struct mlx5_core_dev *dev = priv->mdev;
1826 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1827 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1828 struct mlx5_eswitch_rep *rep;
d708f902 1829 u8 match_level;
de0af0bf
RD		 1830 int err;
1831
54c177ca 1832 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level);
de0af0bf 1833
1d447a39
SM		 1834 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1835 rep = rpriv->rep;
1836 if (rep->vport != FDB_UPLINK_VPORT &&
1837 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1838 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1839 NL_SET_ERR_MSG_MOD(extack,
1840 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1841 netdev_warn(priv->netdev,
1842 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1843 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1844 return -EOPNOTSUPP;
1845 }
1846 }
1847
38aa51c1
OG		 1848 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1849 flow->esw_attr->match_level = match_level;
1850 else
1851 flow->nic_attr->match_level = match_level;
1852
de0af0bf
RD		 1853 return err;
1854}
1855
d79b6df6
OG		 1856struct pedit_headers {
1857 struct ethhdr eth;
1858 struct iphdr ip4;
1859 struct ipv6hdr ip6;
1860 struct tcphdr tcp;
1861 struct udphdr udp;
1862};
1863
1864static int pedit_header_offsets[] = {
1865 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1866 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1867 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1868 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1869 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1870};
1871
1872#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1873
1874static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1875 struct pedit_headers *masks,
1876 struct pedit_headers *vals)
1877{
1878 u32 *curr_pmask, *curr_pval;
1879
1880 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1881 goto out_err;
1882
1883 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1884 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1885
1886 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1887 goto out_err;
1888
1889 *curr_pmask |= mask;
1890 *curr_pval |= (val & mask);
1891
1892 return 0;
1893
1894out_err:
1895 return -EOPNOTSUPP;
1896}
1897
1898struct mlx5_fields {
1899 u8 field;
1900 u8 size;
1901 u32 offset;
1902};
1903
a8e4f0c4
OG		 1904#define OFFLOAD(fw_field, size, field, off) \
1905 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1906
d79b6df6 1907static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1908 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1909 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1910 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1911 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1912 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1913
1914 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1915 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1916 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1917
1918 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1919 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1920 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1921 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1922 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1923 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1924 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1925 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1926 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1927
1928 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1929 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1930 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1931
1932 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1933 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1934};
1935
1936/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1937 * max from the SW pedit action. On success, it says how many HW actions were
1938 * actually parsed.
1939 */
1940static int offload_pedit_fields(struct pedit_headers *masks,
1941 struct pedit_headers *vals,
e98bedf5
EB		 1942 struct mlx5e_tc_flow_parse_attr *parse_attr,
1943 struct netlink_ext_ack *extack)
d79b6df6
OG		 1944{
1945 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1946 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1947 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1948 struct mlx5_fields *f;
1949 u8 cmd, field_bsize;
e3ca4e05 1950 u32 s_mask, a_mask;
d79b6df6 1951 unsigned long mask;
2b64beba
OG		 1952 __be32 mask_be32;
1953 __be16 mask_be16;
d79b6df6
OG		 1954 void *action;
1955
1956 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1957 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1958 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1959 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1960
1961 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1962 action = parse_attr->mod_hdr_actions;
1963 max_actions = parse_attr->num_mod_hdr_actions;
1964 nactions = 0;
1965
1966 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1967 f = &fields[i];
1968 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1969 s_mask = 0;
1970 a_mask = 0;
d79b6df6
OG		 1971
1972 s_masks_p = (void *)set_masks + f->offset;
1973 a_masks_p = (void *)add_masks + f->offset;
1974
1975 memcpy(&s_mask, s_masks_p, f->size);
1976 memcpy(&a_mask, a_masks_p, f->size);
1977
1978 if (!s_mask && !a_mask) /* nothing to offload here */
1979 continue;
1980
1981 if (s_mask && a_mask) {
e98bedf5
EB		 1982 NL_SET_ERR_MSG_MOD(extack,
1983 "can't set and add to the same HW field");
d79b6df6
OG		 1984 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1985 return -EOPNOTSUPP;
1986 }
1987
1988 if (nactions == max_actions) {
e98bedf5
EB		 1989 NL_SET_ERR_MSG_MOD(extack,
1990 "too many pedit actions, can't offload");
d79b6df6
OG		 1991 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1992 return -EOPNOTSUPP;
1993 }
1994
1995 if (s_mask) {
1996 cmd = MLX5_ACTION_TYPE_SET;
1997 mask = s_mask;
1998 vals_p = (void *)set_vals + f->offset;
1999 /* clear to denote we consumed this field */
2000 memset(s_masks_p, 0, f->size);
2001 } else {
2002 cmd = MLX5_ACTION_TYPE_ADD;
2003 mask = a_mask;
2004 vals_p = (void *)add_vals + f->offset;
2005 /* clear to denote we consumed this field */
2006 memset(a_masks_p, 0, f->size);
2007 }
2008
d79b6df6 2009 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2010
2b64beba
OG		 2011 if (field_bsize == 32) {
2012 mask_be32 = *(__be32 *)&mask;
2013 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2014 } else if (field_bsize == 16) {
2015 mask_be16 = *(__be16 *)&mask;
2016 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2017 }
2018
d79b6df6 2019 first = find_first_bit(&mask, field_bsize);
2b64beba 2020 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2021 last = find_last_bit(&mask, field_bsize);
2b64beba 2022 if (first < next_z && next_z < last) {
e98bedf5
EB		 2023 NL_SET_ERR_MSG_MOD(extack,
2024 "rewrite of few sub-fields isn't supported");
2b64beba 2025 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2026 mask);
2027 return -EOPNOTSUPP;
2028 }
2029
2030 MLX5_SET(set_action_in, action, action_type, cmd);
2031 MLX5_SET(set_action_in, action, field, f->field);
2032
2033 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2034 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2035 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2036 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2037 }
2038
2039 if (field_bsize == 32)
2b64beba 2040 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2041 else if (field_bsize == 16)
2b64beba 2042 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2043 else if (field_bsize == 8)
2b64beba 2044 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2045
2046 action += action_size;
2047 nactions++;
2048 }
2049
2050 parse_attr->num_mod_hdr_actions = nactions;
2051 return 0;
2052}
2053
2054static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2055 const struct tc_action *a, int namespace,
2056 struct mlx5e_tc_flow_parse_attr *parse_attr)
2057{
2058 int nkeys, action_size, max_actions;
2059
2060 nkeys = tcf_pedit_nkeys(a);
2061 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2062
2063 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2064 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2065 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2066 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2067
2068 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2069 max_actions = min(max_actions, nkeys * 16);
2070
2071 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2072 if (!parse_attr->mod_hdr_actions)
2073 return -ENOMEM;
2074
2075 parse_attr->num_mod_hdr_actions = max_actions;
2076 return 0;
2077}
2078
2079static const struct pedit_headers zero_masks = {};
2080
2081static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2082 const struct tc_action *a, int namespace,
e98bedf5
EB		 2083 struct mlx5e_tc_flow_parse_attr *parse_attr,
2084 struct netlink_ext_ack *extack)
d79b6df6
OG		 2085{
2086 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
2087 int nkeys, i, err = -EOPNOTSUPP;
2088 u32 mask, val, offset;
2089 u8 cmd, htype;
2090
2091 nkeys = tcf_pedit_nkeys(a);
2092
2093 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2094 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2095
2096 for (i = 0; i < nkeys; i++) {
2097 htype = tcf_pedit_htype(a, i);
2098 cmd = tcf_pedit_cmd(a, i);
2099 err = -EOPNOTSUPP; /* can't be all optimistic */
2100
2101 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
e98bedf5
EB		 2102 NL_SET_ERR_MSG_MOD(extack,
2103 "legacy pedit isn't offloaded");
d79b6df6
OG		 2104 goto out_err;
2105 }
2106
2107 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
e98bedf5 2108 NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
d79b6df6
OG		 2109 goto out_err;
2110 }
2111
2112 mask = tcf_pedit_mask(a, i);
2113 val = tcf_pedit_val(a, i);
2114 offset = tcf_pedit_offset(a, i);
2115
2116 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
2117 if (err)
2118 goto out_err;
2119 }
2120
2121 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
2122 if (err)
2123 goto out_err;
2124
e98bedf5 2125 err = offload_pedit_fields(masks, vals, parse_attr, extack);
d79b6df6
OG		 2126 if (err < 0)
2127 goto out_dealloc_parsed_actions;
2128
2129 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2130 cmd_masks = &masks[cmd];
2131 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2132 NL_SET_ERR_MSG_MOD(extack,
2133 "attempt to offload an unsupported field");
b3a433de 2134 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2135 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2136 16, 1, cmd_masks, sizeof(zero_masks), true);
2137 err = -EOPNOTSUPP;
2138 goto out_dealloc_parsed_actions;
2139 }
2140 }
2141
2142 return 0;
2143
2144out_dealloc_parsed_actions:
2145 kfree(parse_attr->mod_hdr_actions);
2146out_err:
2147 return err;
2148}
2149
e98bedf5
EB		 2150static bool csum_offload_supported(struct mlx5e_priv *priv,
2151 u32 action,
2152 u32 update_flags,
2153 struct netlink_ext_ack *extack)
26c02749
OG		 2154{
2155 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2156 TCA_CSUM_UPDATE_FLAG_UDP;
2157
2158 /* The HW recalcs checksums only if re-writing headers */
2159 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2160 NL_SET_ERR_MSG_MOD(extack,
2161 "TC csum action is only offloaded with pedit");
26c02749
OG		 2162 netdev_warn(priv->netdev,
2163 "TC csum action is only offloaded with pedit\n");
2164 return false;
2165 }
2166
2167 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2168 NL_SET_ERR_MSG_MOD(extack,
2169 "can't offload TC csum action for some header/s");
26c02749
OG		 2170 netdev_warn(priv->netdev,
2171 "can't offload TC csum action for some header/s - flags %#x\n",
2172 update_flags);
2173 return false;
2174 }
2175
2176 return true;
2177}
2178
bdd66ac0 2179static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
e98bedf5
EB		 2180 struct tcf_exts *exts,
2181 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2182{
2183 const struct tc_action *a;
2184 bool modify_ip_header;
2185 LIST_HEAD(actions);
2186 u8 htype, ip_proto;
2187 void *headers_v;
2188 u16 ethertype;
2189 int nkeys, i;
2190
2191 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2192 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2193
2194 /* for non-IP we only re-write MACs, so we're okay */
2195 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2196 goto out_ok;
2197
2198 modify_ip_header = false;
244cd96a
CW		 2199 tcf_exts_for_each_action(i, a, exts) {
2200 int k;
2201
bdd66ac0
OG		 2202 if (!is_tcf_pedit(a))
2203 continue;
2204
2205 nkeys = tcf_pedit_nkeys(a);
244cd96a
CW		 2206 for (k = 0; k < nkeys; k++) {
2207 htype = tcf_pedit_htype(a, k);
bdd66ac0
OG		 2208 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2209 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2210 modify_ip_header = true;
2211 break;
2212 }
2213 }
2214 }
2215
2216 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2217 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2218 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2219 NL_SET_ERR_MSG_MOD(extack,
2220 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2221 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2222 return false;
2223 }
2224
2225out_ok:
2226 return true;
2227}
2228
2229static bool actions_match_supported(struct mlx5e_priv *priv,
2230 struct tcf_exts *exts,
2231 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2232 struct mlx5e_tc_flow *flow,
2233 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2234{
2235 u32 actions;
2236
2237 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2238 actions = flow->esw_attr->action;
2239 else
2240 actions = flow->nic_attr->action;
2241
7e29392e
RD		 2242 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2243 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2244 return false;
2245
bdd66ac0 2246 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
e98bedf5
EB		 2247 return modify_header_match_supported(&parse_attr->spec, exts,
2248 extack);
bdd66ac0
OG		 2249
2250 return true;
2251}
2252
5c65c564
OG		 2253static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2254{
2255 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2256 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2257
2258 fmdev = priv->mdev;
2259 pmdev = peer_priv->mdev;
2260
59c9d35e
AH		 2261 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2262 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2263
816f6706 2264 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2265}
2266
5c40348c 2267static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae 2268 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2269 struct mlx5e_tc_flow *flow,
2270 struct netlink_ext_ack *extack)
e3a2b7ed 2271{
aa0cbbae 2272 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 2273 const struct tc_action *a;
22dc13c8 2274 LIST_HEAD(actions);
1cab1cd7 2275 u32 action = 0;
244cd96a 2276 int err, i;
e3a2b7ed 2277
3bcc0cec 2278 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 2279 return -EINVAL;
2280
3bc4b7bf 2281 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2282
244cd96a 2283 tcf_exts_for_each_action(i, a, exts) {
e3a2b7ed 2284 if (is_tcf_gact_shot(a)) {
1cab1cd7 2285 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2286 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2287 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2288 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2289 continue;
2290 }
2291
2f4fe4ca
OG		 2292 if (is_tcf_pedit(a)) {
2293 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
e98bedf5 2294 parse_attr, extack);
2f4fe4ca
OG		 2295 if (err)
2296 return err;
2297
1cab1cd7
OG		 2298 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2299 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2300 continue;
2301 }
2302
26c02749 2303 if (is_tcf_csum(a)) {
1cab1cd7 2304 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2305 tcf_csum_update_flags(a),
2306 extack))
26c02749
OG		 2307 continue;
2308
2309 return -EOPNOTSUPP;
2310 }
2311
5c65c564
OG		 2312 if (is_tcf_mirred_egress_redirect(a)) {
2313 struct net_device *peer_dev = tcf_mirred_dev(a);
2314
2315 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2316 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2317 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
5c65c564 2318 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2319 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2320 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2321 } else {
e98bedf5
EB		 2322 NL_SET_ERR_MSG_MOD(extack,
2323 "device is not on same HW, can't offload");
5c65c564
OG		 2324 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2325 peer_dev->name);
2326 return -EINVAL;
2327 }
2328 continue;
2329 }
2330
e3a2b7ed
AV		 2331 if (is_tcf_skbedit_mark(a)) {
2332 u32 mark = tcf_skbedit_mark(a);
2333
2334 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2335 NL_SET_ERR_MSG_MOD(extack,
2336 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2337 return -EINVAL;
2338 }
2339
3bc4b7bf 2340 attr->flow_tag = mark;
1cab1cd7 2341 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2342 continue;
2343 }
2344
2345 return -EINVAL;
2346 }
2347
1cab1cd7 2348 attr->action = action;
e98bedf5 2349 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2350 return -EOPNOTSUPP;
2351
e3a2b7ed
AV		 2352 return 0;
2353}
2354
76f7444d
OG		 2355static inline int cmp_encap_info(struct ip_tunnel_key *a,
2356 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2357{
2358 return memcmp(a, b, sizeof(*a));
2359}
2360
76f7444d 2361static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2362{
76f7444d 2363 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2364}
2365
a54e20b4 2366
b1d90e6b
RL		 2367static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2368 struct net_device *peer_netdev)
2369{
2370 struct mlx5e_priv *peer_priv;
2371
2372 peer_priv = netdev_priv(peer_netdev);
2373
2374 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2375 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2376 same_hw_devs(priv, peer_priv) &&
2377 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2378 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2379}
2380
32f3671f 2381
f5bc2c5d 2382
a54e20b4
HHZ		 2383static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2384 struct ip_tunnel_info *tun_info,
2385 struct net_device *mirred_dev,
45247bf2 2386 struct net_device **encap_dev,
e98bedf5 2387 struct mlx5e_tc_flow *flow,
8c4dc42b
EB		 2388 struct netlink_ext_ack *extack,
2389 int out_index)
a54e20b4
HHZ		 2390{
2391 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2392 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2393 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2394 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2395 struct mlx5e_encap_entry *e;
a54e20b4
HHZ		 2396 uintptr_t hash_key;
2397 bool found = false;
54c177ca 2398 int err = 0;
a54e20b4 2399
76f7444d 2400 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2401
2402 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2403 encap_hlist, hash_key) {
76f7444d 2404 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2405 found = true;
2406 break;
2407 }
2408 }
2409
b2812089 2410 /* must verify if encap is valid or not */
45247bf2
OG		 2411 if (found)
2412 goto attach_flow;
a54e20b4
HHZ		 2413
2414 e = kzalloc(sizeof(*e), GFP_KERNEL);
2415 if (!e)
2416 return -ENOMEM;
2417
76f7444d 2418 e->tun_info = *tun_info;
101f4de9 2419 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2420 if (err)
2421 goto out_err;
2422
a54e20b4
HHZ		 2423 INIT_LIST_HEAD(&e->flows);
2424
ce99f6b9 2425 if (family == AF_INET)
101f4de9 2426 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2427 else if (family == AF_INET6)
101f4de9 2428 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2429
232c0013 2430 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2431 goto out_err;
2432
a54e20b4
HHZ		 2433 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2434
45247bf2 2435attach_flow:
8c4dc42b
EB		 2436 list_add(&flow->encaps[out_index].list, &e->flows);
2437 flow->encaps[out_index].index = out_index;
45247bf2 2438 *encap_dev = e->out_dev;
8c4dc42b
EB		 2439 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2440 attr->dests[out_index].encap_id = e->encap_id;
2441 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
2442 } else {
b2812089 2443 err = -EAGAIN;
8c4dc42b 2444 }
45247bf2 2445
232c0013 2446 return err;
a54e20b4
HHZ		 2447
2448out_err:
2449 kfree(e);
2450 return err;
2451}
2452
1482bd3d
JL		 2453static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2454 const struct tc_action *a,
2455 struct mlx5_esw_flow_attr *attr,
2456 u32 *action)
2457{
cc495188
JL		 2458 u8 vlan_idx = attr->total_vlan;
2459
2460 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2461 return -EOPNOTSUPP;
2462
1482bd3d 2463 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
cc495188
JL		 2464 if (vlan_idx) {
2465 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2466 MLX5_FS_VLAN_DEPTH))
2467 return -EOPNOTSUPP;
2468
2469 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2470 } else {
2471 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2472 }
1482bd3d 2473 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
cc495188
JL		 2474 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2475 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2476 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2477 if (!attr->vlan_proto[vlan_idx])
2478 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2479
2480 if (vlan_idx) {
2481 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2482 MLX5_FS_VLAN_DEPTH))
2483 return -EOPNOTSUPP;
2484
2485 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2486 } else {
2487 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2488 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2489 tcf_vlan_push_prio(a)))
2490 return -EOPNOTSUPP;
2491
2492 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d
JL		 2493 }
2494 } else { /* action is TCA_VLAN_ACT_MODIFY */
2495 return -EOPNOTSUPP;
2496 }
2497
cc495188
JL		 2498 attr->total_vlan = vlan_idx + 1;
2499
1482bd3d
JL		 2500 return 0;
2501}
2502
03a9d11e 2503static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2504 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2505 struct mlx5e_tc_flow *flow,
2506 struct netlink_ext_ack *extack)
03a9d11e 2507{
bf07aa73 2508 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2509 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2510 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2511 struct ip_tunnel_info *info = NULL;
03a9d11e 2512 const struct tc_action *a;
22dc13c8 2513 LIST_HEAD(actions);
a54e20b4 2514 bool encap = false;
1cab1cd7 2515 u32 action = 0;
244cd96a 2516 int err, i;
03a9d11e 2517
3bcc0cec 2518 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2519 return -EINVAL;
2520
1d447a39 2521 attr->in_rep = rpriv->rep;
10ff5359 2522 attr->in_mdev = priv->mdev;
03a9d11e 2523
244cd96a 2524 tcf_exts_for_each_action(i, a, exts) {
03a9d11e 2525 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2526 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2527 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2528 continue;
2529 }
2530
d7e75a32
OG		 2531 if (is_tcf_pedit(a)) {
2532 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
e98bedf5 2533 parse_attr, extack);
d7e75a32
OG		 2534 if (err)
2535 return err;
2536
1cab1cd7 2537 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2538 attr->split_count = attr->out_count;
d7e75a32
OG		 2539 continue;
2540 }
2541
26c02749 2542 if (is_tcf_csum(a)) {
1cab1cd7 2543 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2544 tcf_csum_update_flags(a),
2545 extack))
26c02749
OG		 2546 continue;
2547
2548 return -EOPNOTSUPP;
2549 }
2550
592d3651 2551 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2552 struct mlx5e_priv *out_priv;
592d3651 2553 struct net_device *out_dev;
03a9d11e 2554
9f8a739e 2555 out_dev = tcf_mirred_dev(a);
ef381359
OS		 2556 if (!out_dev) {
2557 /* out_dev is NULL when filters with
2558 * non-existing mirred device are replayed to
2559 * the driver.
2560 */
2561 return -EINVAL;
2562 }
03a9d11e 2563
592d3651 2564 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2565 NL_SET_ERR_MSG_MOD(extack,
2566 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2567 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2568 attr->out_count);
2569 return -EOPNOTSUPP;
2570 }
2571
f493f155
EB		 2572 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2573 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2574 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2575 out_dev) ||
2576 is_merged_eswitch_dev(priv, out_dev)) {
a54e20b4 2577 out_priv = netdev_priv(out_dev);
1d447a39 2578 rpriv = out_priv->ppriv;
df65a573
EB		 2579 attr->dests[attr->out_count].rep = rpriv->rep;
2580 attr->dests[attr->out_count].mdev = out_priv->mdev;
2581 attr->out_count++;
a54e20b4 2582 } else if (encap) {
8c4dc42b
EB		 2583 parse_attr->mirred_ifindex[attr->out_count] =
2584 out_dev->ifindex;
2585 parse_attr->tun_info[attr->out_count] = *info;
2586 encap = false;
3c37745e 2587 attr->parse_attr = parse_attr;
f493f155
EB		 2588 attr->dests[attr->out_count].flags |=
2589 MLX5_ESW_DEST_ENCAP;
1cc26d74 2590 attr->out_count++;
df65a573
EB		 2591 /* attr->dests[].rep is resolved when we
2592 * handle encap
2593 */
ef381359
OS		 2594 } else if (parse_attr->filter_dev != priv->netdev) {
2595 /* All mlx5 devices are called to configure
2596 * high level device filters. Therefore, the
2597 * *attempt* to install a filter on invalid
2598 * eswitch should not trigger an explicit error
2599 */
2600 return -EINVAL;
a54e20b4 2601 } else {
e98bedf5
EB		 2602 NL_SET_ERR_MSG_MOD(extack,
2603 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2604 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2605 priv->netdev->name, out_dev->name);
2606 return -EINVAL;
2607 }
a54e20b4
HHZ		 2608 continue;
2609 }
03a9d11e 2610
a54e20b4
HHZ		 2611 if (is_tcf_tunnel_set(a)) {
2612 info = tcf_tunnel_info(a);
2613 if (info)
2614 encap = true;
2615 else
2616 return -EOPNOTSUPP;
03a9d11e
OG		 2617 continue;
2618 }
2619
8b32580d 2620 if (is_tcf_vlan(a)) {
1482bd3d
JL		 2621 err = parse_tc_vlan_action(priv, a, attr, &action);
2622
2623 if (err)
2624 return err;
2625
e85e02ba 2626 attr->split_count = attr->out_count;
8b32580d
OG		 2627 continue;
2628 }
2629
bbd00f7e 2630 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2631 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2632 continue;
2633 }
2634
bf07aa73
PB		 2635 if (is_tcf_gact_goto_chain(a)) {
2636 u32 dest_chain = tcf_gact_goto_chain_index(a);
2637 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2638
2639 if (dest_chain <= attr->chain) {
2640 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2641 return -EOPNOTSUPP;
2642 }
2643 if (dest_chain > max_chain) {
2644 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2645 return -EOPNOTSUPP;
2646 }
2647 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2648 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2649 attr->dest_chain = dest_chain;
2650
2651 continue;
2652 }
2653
03a9d11e
OG		 2654 return -EINVAL;
2655 }
bdd66ac0 2656
1cab1cd7 2657 attr->action = action;
e98bedf5 2658 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2659 return -EOPNOTSUPP;
2660
e85e02ba 2661 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2662 NL_SET_ERR_MSG_MOD(extack,
2663 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2664 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2665 return -EOPNOTSUPP;
2666 }
2667
31c8eba5 2668 return 0;
03a9d11e
OG		 2669}
2670
5dbe906f 2671static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2672{
5dbe906f 2673 u16 __flow_flags = 0;
60bd4af8
OG		 2674
2675 if (flags & MLX5E_TC_INGRESS)
2676 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2677 if (flags & MLX5E_TC_EGRESS)
2678 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2679
2680 *flow_flags = __flow_flags;
2681}
2682
05866c82
OG		 2683static const struct rhashtable_params tc_ht_params = {
2684 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2685 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2686 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2687 .automatic_shrinking = true,
2688};
2689
2690static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
2691{
655dc3d2
OG		 2692 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2693 struct mlx5e_rep_priv *uplink_rpriv;
2694
2695 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
2696 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 2697 return &uplink_rpriv->uplink_priv.tc_ht;
655dc3d2
OG		 2698 } else
2699 return &priv->fs.tc.ht;
05866c82
OG		 2700}
2701
04de7dda
RD		 2702static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
2703{
2704 return false;
2705}
2706
a88780a9
RD		 2707static int
2708mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 2709 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 2710 struct mlx5e_tc_flow_parse_attr **__parse_attr,
2711 struct mlx5e_tc_flow **__flow)
e3a2b7ed 2712{
17091853 2713 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 2714 struct mlx5e_tc_flow *flow;
a88780a9 2715 int err;
e3a2b7ed 2716
65ba8fb7 2717 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2718 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2719 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2720 err = -ENOMEM;
2721 goto err_free;
2722 }
2723
2724 flow->cookie = f->cookie;
65ba8fb7 2725 flow->flags = flow_flags;
655dc3d2 2726 flow->priv = priv;
e3a2b7ed 2727
a88780a9
RD		 2728 *__flow = flow;
2729 *__parse_attr = parse_attr;
2730
2731 return 0;
2732
2733err_free:
2734 kfree(flow);
2735 kvfree(parse_attr);
2736 return err;
2737}
2738
2739static int
04de7dda
RD		 2740__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2741 struct tc_cls_flower_offload *f,
2742 u16 flow_flags,
2743 struct net_device *filter_dev,
2744 struct mlx5_eswitch_rep *in_rep,
2745 struct mlx5_core_dev *in_mdev,
2746 struct mlx5e_tc_flow **__flow)
a88780a9
RD		 2747{
2748 struct netlink_ext_ack *extack = f->common.extack;
f9392795 2749 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a88780a9
RD		 2750 struct mlx5e_tc_flow_parse_attr *parse_attr;
2751 struct mlx5e_tc_flow *flow;
2752 int attr_size, err;
e3a2b7ed 2753
a88780a9
RD		 2754 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2755 attr_size = sizeof(struct mlx5_esw_flow_attr);
2756 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2757 &parse_attr, &flow);
2758 if (err)
2759 goto out;
d11afc26
OS		 2760 parse_attr->filter_dev = filter_dev;
2761 flow->esw_attr->parse_attr = parse_attr;
54c177ca
OS		 2762 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2763 f, filter_dev);
d11afc26
OS		 2764 if (err)
2765 goto err_free;
a88780a9 2766
bf07aa73
PB		 2767 flow->esw_attr->chain = f->common.chain_index;
2768 flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
a88780a9
RD		 2769 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow, extack);
2770 if (err)
2771 goto err_free;
2772
04de7dda
RD		 2773 flow->esw_attr->in_rep = in_rep;
2774 flow->esw_attr->in_mdev = in_mdev;
f9392795
SK		 2775
2776 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
2777 MLX5_COUNTER_SOURCE_ESWITCH)
2778 flow->esw_attr->counter_dev = in_mdev;
2779 else
2780 flow->esw_attr->counter_dev = priv->mdev;
2781
a88780a9 2782 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
5dbe906f 2783 if (err)
c83954ab 2784 goto err_free;
e3a2b7ed 2785
a88780a9 2786 *__flow = flow;
5c40348c 2787
a88780a9
RD		 2788 return 0;
2789
2790err_free:
2791 kfree(flow);
2792 kvfree(parse_attr);
2793out:
232c0013 2794 return err;
a88780a9
RD		 2795}
2796
04de7dda
RD		 2797static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
2798 struct mlx5e_tc_flow *flow)
2799{
2800 struct mlx5e_priv *priv = flow->priv, *peer_priv;
2801 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
2802 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
2803 struct mlx5e_tc_flow_parse_attr *parse_attr;
2804 struct mlx5e_rep_priv *peer_urpriv;
2805 struct mlx5e_tc_flow *peer_flow;
2806 struct mlx5_core_dev *in_mdev;
2807 int err = 0;
2808
2809 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2810 if (!peer_esw)
2811 return -ENODEV;
2812
2813 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
2814 peer_priv = netdev_priv(peer_urpriv->netdev);
2815
2816 /* in_mdev is assigned of which the packet originated from.
2817 * So packets redirected to uplink use the same mdev of the
2818 * original flow and packets redirected from uplink use the
2819 * peer mdev.
2820 */
2821 if (flow->esw_attr->in_rep->vport == FDB_UPLINK_VPORT)
2822 in_mdev = peer_priv->mdev;
2823 else
2824 in_mdev = priv->mdev;
2825
2826 parse_attr = flow->esw_attr->parse_attr;
2827 err = __mlx5e_add_fdb_flow(peer_priv, f, flow->flags,
2828 parse_attr->filter_dev,
2829 flow->esw_attr->in_rep, in_mdev, &peer_flow);
2830 if (err)
2831 goto out;
2832
2833 flow->peer_flow = peer_flow;
2834 flow->flags |= MLX5E_TC_FLOW_DUP;
2835 mutex_lock(&esw->offloads.peer_mutex);
2836 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
2837 mutex_unlock(&esw->offloads.peer_mutex);
2838
2839out:
2840 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2841 return err;
2842}
2843
2844static int
2845mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2846 struct tc_cls_flower_offload *f,
2847 u16 flow_flags,
2848 struct net_device *filter_dev,
2849 struct mlx5e_tc_flow **__flow)
2850{
2851 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2852 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
2853 struct mlx5_core_dev *in_mdev = priv->mdev;
2854 struct mlx5e_tc_flow *flow;
2855 int err;
2856
2857 err = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
2858 in_mdev, &flow);
2859 if (err)
2860 goto out;
2861
2862 if (is_peer_flow_needed(flow)) {
2863 err = mlx5e_tc_add_fdb_peer_flow(f, flow);
2864 if (err) {
2865 mlx5e_tc_del_fdb_flow(priv, flow);
2866 goto out;
2867 }
2868 }
2869
2870 *__flow = flow;
2871
2872 return 0;
2873
2874out:
2875 return err;
2876}
2877
a88780a9
RD		 2878static int
2879mlx5e_add_nic_flow(struct mlx5e_priv *priv,
2880 struct tc_cls_flower_offload *f,
5dbe906f 2881 u16 flow_flags,
d11afc26 2882 struct net_device *filter_dev,
a88780a9
RD		 2883 struct mlx5e_tc_flow **__flow)
2884{
2885 struct netlink_ext_ack *extack = f->common.extack;
2886 struct mlx5e_tc_flow_parse_attr *parse_attr;
2887 struct mlx5e_tc_flow *flow;
2888 int attr_size, err;
2889
bf07aa73
PB		 2890 /* multi-chain not supported for NIC rules */
2891 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
2892 return -EOPNOTSUPP;
2893
a88780a9
RD		 2894 flow_flags |= MLX5E_TC_FLOW_NIC;
2895 attr_size = sizeof(struct mlx5_nic_flow_attr);
2896 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2897 &parse_attr, &flow);
2898 if (err)
2899 goto out;
2900
d11afc26 2901 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 2902 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2903 f, filter_dev);
d11afc26
OS		 2904 if (err)
2905 goto err_free;
2906
a88780a9
RD		 2907 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow, extack);
2908 if (err)
2909 goto err_free;
2910
2911 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
2912 if (err)
2913 goto err_free;
2914
2915 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2916 kvfree(parse_attr);
2917 *__flow = flow;
2918
2919 return 0;
e3a2b7ed 2920
e3a2b7ed 2921err_free:
a88780a9 2922 kfree(flow);
17091853 2923 kvfree(parse_attr);
a88780a9
RD		 2924out:
2925 return err;
2926}
2927
2928static int
2929mlx5e_tc_add_flow(struct mlx5e_priv *priv,
2930 struct tc_cls_flower_offload *f,
2931 int flags,
d11afc26 2932 struct net_device *filter_dev,
a88780a9
RD		 2933 struct mlx5e_tc_flow **flow)
2934{
2935 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 2936 u16 flow_flags;
a88780a9
RD		 2937 int err;
2938
2939 get_flags(flags, &flow_flags);
2940
bf07aa73
PB		 2941 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
2942 return -EOPNOTSUPP;
2943
a88780a9 2944 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 2945 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
2946 filter_dev, flow);
a88780a9 2947 else
d11afc26
OS		 2948 err = mlx5e_add_nic_flow(priv, f, flow_flags,
2949 filter_dev, flow);
a88780a9
RD		 2950
2951 return err;
2952}
2953
71d82d2a 2954int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 2955 struct tc_cls_flower_offload *f, int flags)
2956{
2957 struct netlink_ext_ack *extack = f->common.extack;
2958 struct rhashtable *tc_ht = get_tc_ht(priv);
2959 struct mlx5e_tc_flow *flow;
2960 int err = 0;
2961
2962 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2963 if (flow) {
2964 NL_SET_ERR_MSG_MOD(extack,
2965 "flow cookie already exists, ignoring");
2966 netdev_warn_once(priv->netdev,
2967 "flow cookie %lx already exists, ignoring\n",
2968 f->cookie);
2969 goto out;
2970 }
2971
d11afc26 2972 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 2973 if (err)
2974 goto out;
2975
2976 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
2977 if (err)
2978 goto err_free;
2979
2980 return 0;
2981
2982err_free:
2983 mlx5e_tc_del_flow(priv, flow);
232c0013 2984 kfree(flow);
a88780a9 2985out:
e3a2b7ed
AV		 2986 return err;
2987}
2988
8f8ae895
OG		 2989#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2990#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2991
2992static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2993{
2994 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2995 return true;
2996
2997 return false;
2998}
2999
71d82d2a 3000int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3001 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3002{
05866c82 3003 struct rhashtable *tc_ht = get_tc_ht(priv);
e3a2b7ed 3004 struct mlx5e_tc_flow *flow;
e3a2b7ed 3005
05866c82 3006 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3007 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3008 return -EINVAL;
3009
05866c82 3010 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3011
961e8979 3012 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3013
3014 kfree(flow);
3015
3016 return 0;
3017}
3018
71d82d2a 3019int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3020 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3021{
04de7dda 3022 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
05866c82 3023 struct rhashtable *tc_ht = get_tc_ht(priv);
04de7dda 3024 struct mlx5_eswitch *peer_esw;
aad7e08d 3025 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 3026 struct mlx5_fc *counter;
3027 u64 bytes;
3028 u64 packets;
3029 u64 lastuse;
3030
05866c82 3031 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3032 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3033 return -EINVAL;
3034
0b67a38f
HHZ		 3035 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3036 return 0;
3037
b8aee822 3038 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 3039 if (!counter)
3040 return 0;
3041
3042 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3043
04de7dda
RD		 3044 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3045 if (!peer_esw)
3046 goto out;
3047
3048 if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3049 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3050 u64 bytes2;
3051 u64 packets2;
3052 u64 lastuse2;
3053
3054 counter = mlx5e_tc_get_counter(flow->peer_flow);
3055 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3056
3057 bytes += bytes2;
3058 packets += packets2;
3059 lastuse = max_t(u64, lastuse, lastuse2);
3060 }
3061
3062 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3063
3064out:
d897a638 3065 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 3066
aad7e08d
AV		 3067 return 0;
3068}
3069
4d8fcf21
AH		 3070static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3071 struct mlx5e_priv *peer_priv)
3072{
3073 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3074 struct mlx5e_hairpin_entry *hpe;
3075 u16 peer_vhca_id;
3076 int bkt;
3077
3078 if (!same_hw_devs(priv, peer_priv))
3079 return;
3080
3081 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3082
3083 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3084 if (hpe->peer_vhca_id == peer_vhca_id)
3085 hpe->hp->pair->peer_gone = true;
3086 }
3087}
3088
3089static int mlx5e_tc_netdev_event(struct notifier_block *this,
3090 unsigned long event, void *ptr)
3091{
3092 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3093 struct mlx5e_flow_steering *fs;
3094 struct mlx5e_priv *peer_priv;
3095 struct mlx5e_tc_table *tc;
3096 struct mlx5e_priv *priv;
3097
3098 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3099 event != NETDEV_UNREGISTER ||
3100 ndev->reg_state == NETREG_REGISTERED)
3101 return NOTIFY_DONE;
3102
3103 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3104 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3105 priv = container_of(fs, struct mlx5e_priv, fs);
3106 peer_priv = netdev_priv(ndev);
3107 if (priv == peer_priv ||
3108 !(priv->netdev->features & NETIF_F_HW_TC))
3109 return NOTIFY_DONE;
3110
3111 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3112
3113 return NOTIFY_DONE;
3114}
3115
655dc3d2 3116int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3117{
acff797c 3118 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3119 int err;
e8f887ac 3120
11c9c548 3121 hash_init(tc->mod_hdr_tbl);
5c65c564 3122 hash_init(tc->hairpin_tbl);
11c9c548 3123
4d8fcf21
AH		 3124 err = rhashtable_init(&tc->ht, &tc_ht_params);
3125 if (err)
3126 return err;
3127
3128 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3129 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3130 tc->netdevice_nb.notifier_call = NULL;
3131 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3132 }
3133
3134 return err;
e8f887ac
AV		 3135}
3136
3137static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3138{
3139 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3140 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3141
961e8979 3142 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3143 kfree(flow);
3144}
3145
655dc3d2 3146void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3147{
acff797c 3148 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3149
4d8fcf21
AH		 3150 if (tc->netdevice_nb.notifier_call)
3151 unregister_netdevice_notifier(&tc->netdevice_nb);
3152
655dc3d2 3153 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 3154
acff797c
MG		 3155 if (!IS_ERR_OR_NULL(tc->t)) {
3156 mlx5_destroy_flow_table(tc->t);
3157 tc->t = NULL;
e8f887ac
AV		 3158 }
3159}
655dc3d2
OG		 3160
3161int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3162{
3163 return rhashtable_init(tc_ht, &tc_ht_params);
3164}
3165
3166void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3167{
3168 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3169}
01252a27
OG		 3170
3171int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
3172{
3173 struct rhashtable *tc_ht = get_tc_ht(priv);
3174
3175 return atomic_read(&tc_ht->nelems);
3176}
04de7dda
RD		 3177
3178void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3179{
3180 struct mlx5e_tc_flow *flow, *tmp;
3181
3182 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3183 __mlx5e_tc_del_fdb_peer_flow(flow);
3184}
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