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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
03a9d11e 42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
f6dfb4c3 47#include <net/arp.h>
3616d08b 48#include <net/ipv6_stubs.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
3f6d08d1 53#include "fs_core.h"
2c81bfd5 54#include "en/port.h"
101f4de9 55#include "en/tc_tun.h"
04de7dda 56#include "lib/devcom.h"
9272e3df 57#include "lib/geneve.h"
e8f887ac 58
3bc4b7bf
OG		 59struct mlx5_nic_flow_attr {
60 u32 action;
61 u32 flow_tag;
2f4fe4ca 62 u32 mod_hdr_id;
5c65c564 63 u32 hairpin_tirn;
38aa51c1 64 u8 match_level;
3f6d08d1 65 struct mlx5_flow_table *hairpin_ft;
b8aee822 66 struct mlx5_fc *counter;
3bc4b7bf
OG		 67};
68
226f2ca3 69#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 70
65ba8fb7 71enum {
226f2ca3
VB		 72 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
73 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
74 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
75 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
76 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
77 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
78 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
79 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
80 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
81 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 82 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
65ba8fb7
OG		 83};
84
e4ad91f2
CM		 85#define MLX5E_TC_MAX_SPLITS 1
86
79baaec7
EB		 87/* Helper struct for accessing a struct containing list_head array.
88 * Containing struct
89 * |- Helper array
90 * [0] Helper item 0
91 * |- list_head item 0
92 * |- index (0)
93 * [1] Helper item 1
94 * |- list_head item 1
95 * |- index (1)
96 * To access the containing struct from one of the list_head items:
97 * 1. Get the helper item from the list_head item using
98 * helper item =
99 * container_of(list_head item, helper struct type, list_head field)
100 * 2. Get the contining struct from the helper item and its index in the array:
101 * containing struct =
102 * container_of(helper item, containing struct type, helper field[index])
103 */
104struct encap_flow_item {
105 struct list_head list;
106 int index;
107};
108
e8f887ac
AV		 109struct mlx5e_tc_flow {
110 struct rhash_head node;
655dc3d2 111 struct mlx5e_priv *priv;
e8f887ac 112 u64 cookie;
226f2ca3 113 unsigned long flags;
e4ad91f2 114 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 115 /* Flow can be associated with multiple encap IDs.
116 * The number of encaps is bounded by the number of supported
117 * destinations.
118 */
119 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 120 struct mlx5e_tc_flow *peer_flow;
11c9c548 121 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 122 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 123 struct list_head peer; /* flows with peer flow */
b4a23329 124 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
5a7e5bcb 125 refcount_t refcnt;
c5d326b2 126 struct rcu_head rcu_head;
3bc4b7bf
OG		 127 union {
128 struct mlx5_esw_flow_attr esw_attr[0];
129 struct mlx5_nic_flow_attr nic_attr[0];
130 };
e8f887ac
AV		 131};
132
17091853 133struct mlx5e_tc_flow_parse_attr {
1f6da306 134 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 135 struct net_device *filter_dev;
17091853 136 struct mlx5_flow_spec spec;
d79b6df6 137 int num_mod_hdr_actions;
218d05ce 138 int max_mod_hdr_actions;
d79b6df6 139 void *mod_hdr_actions;
98b66cb1 140 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 141};
142
acff797c 143#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 144#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 145
77ab67b7
OG		 146struct mlx5e_hairpin {
147 struct mlx5_hairpin *pair;
148
149 struct mlx5_core_dev *func_mdev;
3f6d08d1 150 struct mlx5e_priv *func_priv;
77ab67b7
OG		 151 u32 tdn;
152 u32 tirn;
3f6d08d1
OG		 153
154 int num_channels;
155 struct mlx5e_rqt indir_rqt;
156 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
157 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 158};
159
5c65c564
OG		 160struct mlx5e_hairpin_entry {
161 /* a node of a hash table which keeps all the hairpin entries */
162 struct hlist_node hairpin_hlist;
163
164 /* flows sharing the same hairpin */
165 struct list_head flows;
166
d8822868 167 u16 peer_vhca_id;
106be53b 168 u8 prio;
5c65c564
OG		 169 struct mlx5e_hairpin *hp;
170};
171
11c9c548
OG		 172struct mod_hdr_key {
173 int num_actions;
174 void *actions;
175};
176
177struct mlx5e_mod_hdr_entry {
178 /* a node of a hash table which keeps all the mod_hdr entries */
179 struct hlist_node mod_hdr_hlist;
180
181 /* flows sharing the same mod_hdr entry */
182 struct list_head flows;
183
184 struct mod_hdr_key key;
185
186 u32 mod_hdr_id;
187};
188
189#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
190
5a7e5bcb
VB		 191static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
192 struct mlx5e_tc_flow *flow);
193
194static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
195{
196 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
197 return ERR_PTR(-EINVAL);
198 return flow;
199}
200
201static void mlx5e_flow_put(struct mlx5e_priv *priv,
202 struct mlx5e_tc_flow *flow)
203{
204 if (refcount_dec_and_test(&flow->refcnt)) {
205 mlx5e_tc_del_flow(priv, flow);
c5d326b2 206 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 207 }
208}
209
226f2ca3
VB		 210static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
211{
212 /* Complete all memory stores before setting bit. */
213 smp_mb__before_atomic();
214 set_bit(flag, &flow->flags);
215}
216
217#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
218
c5d326b2
VB		 219static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
220 unsigned long flag)
221{
222 /* test_and_set_bit() provides all necessary barriers */
223 return test_and_set_bit(flag, &flow->flags);
224}
225
226#define flow_flag_test_and_set(flow, flag) \
227 __flow_flag_test_and_set(flow, \
228 MLX5E_TC_FLOW_FLAG_##flag)
229
226f2ca3
VB		 230static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
231{
232 /* Complete all memory stores before clearing bit. */
233 smp_mb__before_atomic();
234 clear_bit(flag, &flow->flags);
235}
236
237#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
238 MLX5E_TC_FLOW_FLAG_##flag)
239
240static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
241{
242 bool ret = test_bit(flag, &flow->flags);
243
244 /* Read fields of flow structure only after checking flags. */
245 smp_mb__after_atomic();
246 return ret;
247}
248
249#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
250 MLX5E_TC_FLOW_FLAG_##flag)
251
252static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
253{
254 return flow_flag_test(flow, ESWITCH);
255}
256
257static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
258{
259 return flow_flag_test(flow, OFFLOADED);
260}
261
11c9c548
OG		 262static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
263{
264 return jhash(key->actions,
265 key->num_actions * MLX5_MH_ACT_SZ, 0);
266}
267
268static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
269 struct mod_hdr_key *b)
270{
271 if (a->num_actions != b->num_actions)
272 return 1;
273
274 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
275}
276
277static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
278 struct mlx5e_tc_flow *flow,
279 struct mlx5e_tc_flow_parse_attr *parse_attr)
280{
281 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
282 int num_actions, actions_size, namespace, err;
226f2ca3 283 bool found = false, is_eswitch_flow;
11c9c548
OG		 284 struct mlx5e_mod_hdr_entry *mh;
285 struct mod_hdr_key key;
11c9c548
OG		 286 u32 hash_key;
287
288 num_actions = parse_attr->num_mod_hdr_actions;
289 actions_size = MLX5_MH_ACT_SZ * num_actions;
290
291 key.actions = parse_attr->mod_hdr_actions;
292 key.num_actions = num_actions;
293
294 hash_key = hash_mod_hdr_info(&key);
295
226f2ca3
VB		 296 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
297 if (is_eswitch_flow) {
11c9c548
OG		 298 namespace = MLX5_FLOW_NAMESPACE_FDB;
299 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
300 mod_hdr_hlist, hash_key) {
301 if (!cmp_mod_hdr_info(&mh->key, &key)) {
302 found = true;
303 break;
304 }
305 }
306 } else {
307 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
308 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
309 mod_hdr_hlist, hash_key) {
310 if (!cmp_mod_hdr_info(&mh->key, &key)) {
311 found = true;
312 break;
313 }
314 }
315 }
316
317 if (found)
318 goto attach_flow;
319
320 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
321 if (!mh)
322 return -ENOMEM;
323
324 mh->key.actions = (void *)mh + sizeof(*mh);
325 memcpy(mh->key.actions, key.actions, actions_size);
326 mh->key.num_actions = num_actions;
327 INIT_LIST_HEAD(&mh->flows);
328
329 err = mlx5_modify_header_alloc(priv->mdev, namespace,
330 mh->key.num_actions,
331 mh->key.actions,
332 &mh->mod_hdr_id);
333 if (err)
334 goto out_err;
335
226f2ca3 336 if (is_eswitch_flow)
11c9c548
OG		 337 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
338 else
339 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
340
341attach_flow:
342 list_add(&flow->mod_hdr, &mh->flows);
226f2ca3 343 if (is_eswitch_flow)
11c9c548
OG		 344 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
345 else
346 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
347
348 return 0;
349
350out_err:
351 kfree(mh);
352 return err;
353}
354
355static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
356 struct mlx5e_tc_flow *flow)
357{
358 struct list_head *next = flow->mod_hdr.next;
359
5a7e5bcb
VB		 360 /* flow wasn't fully initialized */
361 if (list_empty(&flow->mod_hdr))
362 return;
363
11c9c548
OG		 364 list_del(&flow->mod_hdr);
365
366 if (list_empty(next)) {
367 struct mlx5e_mod_hdr_entry *mh;
368
369 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
370
371 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
372 hash_del(&mh->mod_hdr_hlist);
373 kfree(mh);
374 }
375}
376
77ab67b7
OG		 377static
378struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
379{
380 struct net_device *netdev;
381 struct mlx5e_priv *priv;
382
383 netdev = __dev_get_by_index(net, ifindex);
384 priv = netdev_priv(netdev);
385 return priv->mdev;
386}
387
388static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
389{
390 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
391 void *tirc;
392 int err;
393
394 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
395 if (err)
396 goto alloc_tdn_err;
397
398 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
399
400 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 401 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 402 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
403
404 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
405 if (err)
406 goto create_tir_err;
407
408 return 0;
409
410create_tir_err:
411 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
412alloc_tdn_err:
413 return err;
414}
415
416static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
417{
418 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
419 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
420}
421
3f6d08d1
OG		 422static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
423{
424 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
425 struct mlx5e_priv *priv = hp->func_priv;
426 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
427
428 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
429 hp->num_channels);
430
431 for (i = 0; i < sz; i++) {
432 ix = i;
bbeb53b8 433 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 434 ix = mlx5e_bits_invert(i, ilog2(sz));
435 ix = indirection_rqt[ix];
436 rqn = hp->pair->rqn[ix];
437 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
438 }
439}
440
441static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
442{
443 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
444 struct mlx5e_priv *priv = hp->func_priv;
445 struct mlx5_core_dev *mdev = priv->mdev;
446 void *rqtc;
447 u32 *in;
448
449 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
450 in = kvzalloc(inlen, GFP_KERNEL);
451 if (!in)
452 return -ENOMEM;
453
454 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
455
456 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
457 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
458
459 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
460
461 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
462 if (!err)
463 hp->indir_rqt.enabled = true;
464
465 kvfree(in);
466 return err;
467}
468
469static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
470{
471 struct mlx5e_priv *priv = hp->func_priv;
472 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
473 int tt, i, err;
474 void *tirc;
475
476 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 477 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
478
3f6d08d1
OG		 479 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
480 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
481
482 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
483 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
484 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 485 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
486
3f6d08d1
OG		 487 err = mlx5_core_create_tir(hp->func_mdev, in,
488 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
489 if (err) {
490 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
491 goto err_destroy_tirs;
492 }
493 }
494 return 0;
495
496err_destroy_tirs:
497 for (i = 0; i < tt; i++)
498 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
499 return err;
500}
501
502static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
503{
504 int tt;
505
506 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
507 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
508}
509
510static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
511 struct ttc_params *ttc_params)
512{
513 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
514 int tt;
515
516 memset(ttc_params, 0, sizeof(*ttc_params));
517
518 ttc_params->any_tt_tirn = hp->tirn;
519
520 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
521 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
522
523 ft_attr->max_fte = MLX5E_NUM_TT;
524 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
525 ft_attr->prio = MLX5E_TC_PRIO;
526}
527
528static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
529{
530 struct mlx5e_priv *priv = hp->func_priv;
531 struct ttc_params ttc_params;
532 int err;
533
534 err = mlx5e_hairpin_create_indirect_rqt(hp);
535 if (err)
536 return err;
537
538 err = mlx5e_hairpin_create_indirect_tirs(hp);
539 if (err)
540 goto err_create_indirect_tirs;
541
542 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
543 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
544 if (err)
545 goto err_create_ttc_table;
546
547 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
548 hp->num_channels, hp->ttc.ft.t->id);
549
550 return 0;
551
552err_create_ttc_table:
553 mlx5e_hairpin_destroy_indirect_tirs(hp);
554err_create_indirect_tirs:
555 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
556
557 return err;
558}
559
560static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
561{
562 struct mlx5e_priv *priv = hp->func_priv;
563
564 mlx5e_destroy_ttc_table(priv, &hp->ttc);
565 mlx5e_hairpin_destroy_indirect_tirs(hp);
566 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
567}
568
77ab67b7
OG		 569static struct mlx5e_hairpin *
570mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
571 int peer_ifindex)
572{
573 struct mlx5_core_dev *func_mdev, *peer_mdev;
574 struct mlx5e_hairpin *hp;
575 struct mlx5_hairpin *pair;
576 int err;
577
578 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
579 if (!hp)
580 return ERR_PTR(-ENOMEM);
581
582 func_mdev = priv->mdev;
583 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
584
585 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
586 if (IS_ERR(pair)) {
587 err = PTR_ERR(pair);
588 goto create_pair_err;
589 }
590 hp->pair = pair;
591 hp->func_mdev = func_mdev;
3f6d08d1
OG		 592 hp->func_priv = priv;
593 hp->num_channels = params->num_channels;
77ab67b7
OG		 594
595 err = mlx5e_hairpin_create_transport(hp);
596 if (err)
597 goto create_transport_err;
598
3f6d08d1
OG		 599 if (hp->num_channels > 1) {
600 err = mlx5e_hairpin_rss_init(hp);
601 if (err)
602 goto rss_init_err;
603 }
604
77ab67b7
OG		 605 return hp;
606
3f6d08d1
OG		 607rss_init_err:
608 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 609create_transport_err:
610 mlx5_core_hairpin_destroy(hp->pair);
611create_pair_err:
612 kfree(hp);
613 return ERR_PTR(err);
614}
615
616static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
617{
3f6d08d1
OG		 618 if (hp->num_channels > 1)
619 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 620 mlx5e_hairpin_destroy_transport(hp);
621 mlx5_core_hairpin_destroy(hp->pair);
622 kvfree(hp);
623}
624
106be53b
OG		 625static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
626{
627 return (peer_vhca_id << 16 | prio);
628}
629
5c65c564 630static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 631 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 632{
633 struct mlx5e_hairpin_entry *hpe;
106be53b 634 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 635
636 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 637 hairpin_hlist, hash_key) {
638 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 639 return hpe;
640 }
641
642 return NULL;
643}
644
106be53b
OG		 645#define UNKNOWN_MATCH_PRIO 8
646
647static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 648 struct mlx5_flow_spec *spec, u8 *match_prio,
649 struct netlink_ext_ack *extack)
106be53b
OG		 650{
651 void *headers_c, *headers_v;
652 u8 prio_val, prio_mask = 0;
653 bool vlan_present;
654
655#ifdef CONFIG_MLX5_CORE_EN_DCB
656 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 657 NL_SET_ERR_MSG_MOD(extack,
658 "only PCP trust state supported for hairpin");
106be53b
OG		 659 return -EOPNOTSUPP;
660 }
661#endif
662 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
663 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
664
665 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
666 if (vlan_present) {
667 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
668 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
669 }
670
671 if (!vlan_present || !prio_mask) {
672 prio_val = UNKNOWN_MATCH_PRIO;
673 } else if (prio_mask != 0x7) {
e98bedf5
EB		 674 NL_SET_ERR_MSG_MOD(extack,
675 "masked priority match not supported for hairpin");
106be53b
OG		 676 return -EOPNOTSUPP;
677 }
678
679 *match_prio = prio_val;
680 return 0;
681}
682
5c65c564
OG		 683static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
684 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 685 struct mlx5e_tc_flow_parse_attr *parse_attr,
686 struct netlink_ext_ack *extack)
5c65c564 687{
98b66cb1 688 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 689 struct mlx5_hairpin_params params;
d8822868 690 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 691 struct mlx5e_hairpin_entry *hpe;
692 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 693 u64 link_speed64;
694 u32 link_speed;
106be53b 695 u8 match_prio;
d8822868 696 u16 peer_id;
5c65c564
OG		 697 int err;
698
d8822868
OG		 699 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
700 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 701 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 702 return -EOPNOTSUPP;
703 }
704
d8822868 705 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 706 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
707 extack);
106be53b
OG		 708 if (err)
709 return err;
710 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 711 if (hpe)
712 goto attach_flow;
713
714 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
715 if (!hpe)
716 return -ENOMEM;
717
718 INIT_LIST_HEAD(&hpe->flows);
d8822868 719 hpe->peer_vhca_id = peer_id;
106be53b 720 hpe->prio = match_prio;
5c65c564
OG		 721
722 params.log_data_size = 15;
723 params.log_data_size = min_t(u8, params.log_data_size,
724 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
725 params.log_data_size = max_t(u8, params.log_data_size,
726 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 727
eb9180f7
OG		 728 params.log_num_packets = params.log_data_size -
729 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
730 params.log_num_packets = min_t(u8, params.log_num_packets,
731 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
732
733 params.q_counter = priv->q_counter;
3f6d08d1 734 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 735 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 736 link_speed = max_t(u32, link_speed, 50000);
737 link_speed64 = link_speed;
738 do_div(link_speed64, 50000);
739 params.num_channels = link_speed64;
740
5c65c564
OG		 741 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
742 if (IS_ERR(hp)) {
743 err = PTR_ERR(hp);
744 goto create_hairpin_err;
745 }
746
eb9180f7 747 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 748 hp->tirn, hp->pair->rqn[0],
749 dev_name(hp->pair->peer_mdev->device),
eb9180f7 750 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 751
752 hpe->hp = hp;
106be53b
OG		 753 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
754 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 755
756attach_flow:
3f6d08d1 757 if (hpe->hp->num_channels > 1) {
226f2ca3 758 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 759 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
760 } else {
761 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
762 }
5c65c564 763 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 764
5c65c564
OG		 765 return 0;
766
767create_hairpin_err:
768 kfree(hpe);
769 return err;
770}
771
772static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
773 struct mlx5e_tc_flow *flow)
774{
775 struct list_head *next = flow->hairpin.next;
776
5a7e5bcb
VB		 777 /* flow wasn't fully initialized */
778 if (list_empty(&flow->hairpin))
779 return;
780
5c65c564
OG		 781 list_del(&flow->hairpin);
782
783 /* no more hairpin flows for us, release the hairpin pair */
784 if (list_empty(next)) {
785 struct mlx5e_hairpin_entry *hpe;
786
787 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
788
789 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
27b942fb 790 dev_name(hpe->hp->pair->peer_mdev->device));
5c65c564
OG		 791
792 mlx5e_hairpin_destroy(hpe->hp);
793 hash_del(&hpe->hairpin_hlist);
794 kfree(hpe);
795 }
796}
797
c83954ab 798static int
74491de9 799mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 800 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 801 struct mlx5e_tc_flow *flow,
802 struct netlink_ext_ack *extack)
e8f887ac 803{
bb0ee7dc 804 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 805 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 806 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 807 struct mlx5_flow_destination dest[2] = {};
66958ed9 808 struct mlx5_flow_act flow_act = {
3bc4b7bf 809 .action = attr->action,
60786f09 810 .reformat_id = 0,
bb0ee7dc 811 .flags = FLOW_ACT_NO_APPEND,
66958ed9 812 };
aad7e08d 813 struct mlx5_fc *counter = NULL;
5c65c564 814 int err, dest_ix = 0;
e8f887ac 815
bb0ee7dc
JL		 816 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
817 flow_context->flow_tag = attr->flow_tag;
818
226f2ca3 819 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 820 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 821 if (err)
822 return err;
823
226f2ca3 824 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 825 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
826 dest[dest_ix].ft = attr->hairpin_ft;
827 } else {
5c65c564
OG		 828 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
829 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 830 }
831 dest_ix++;
3f6d08d1
OG		 832 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
833 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
834 dest[dest_ix].ft = priv->fs.vlan.ft.t;
835 dest_ix++;
5c65c564 836 }
aad7e08d 837
5c65c564
OG		 838 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
839 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 840 if (IS_ERR(counter))
841 return PTR_ERR(counter);
842
5c65c564 843 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 844 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 845 dest_ix++;
b8aee822 846 attr->counter = counter;
aad7e08d
AV		 847 }
848
2f4fe4ca 849 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 850 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 851 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 852 kfree(parse_attr->mod_hdr_actions);
c83954ab 853 if (err)
5a7e5bcb 854 return err;
2f4fe4ca
OG		 855 }
856
b6fac0b4 857 mutex_lock(&priv->fs.tc.t_lock);
acff797c 858 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 859 int tc_grp_size, tc_tbl_size;
860 u32 max_flow_counter;
861
862 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
863 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
864
865 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
866
867 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
868 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
869
acff797c
MG		 870 priv->fs.tc.t =
871 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
872 MLX5E_TC_PRIO,
21b9c144 873 tc_tbl_size,
acff797c 874 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 875 MLX5E_TC_FT_LEVEL, 0);
acff797c 876 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 877 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 878 NL_SET_ERR_MSG_MOD(extack,
879 "Failed to create tc offload table\n");
e8f887ac
AV		 880 netdev_err(priv->netdev,
881 "Failed to create tc offload table\n");
5a7e5bcb 882 return PTR_ERR(priv->fs.tc.t);
e8f887ac 883 }
e8f887ac
AV		 884 }
885
38aa51c1 886 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 887 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 888
c83954ab
RL		 889 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
890 &flow_act, dest, dest_ix);
b6fac0b4 891 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 892
5a7e5bcb
VB		 893 if (IS_ERR(flow->rule[0]))
894 return PTR_ERR(flow->rule[0]);
aad7e08d 895
c83954ab 896 return 0;
e8f887ac
AV		 897}
898
d85cdccb
OG		 899static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
900 struct mlx5e_tc_flow *flow)
901{
513f8f7f 902 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 903 struct mlx5_fc *counter = NULL;
904
b8aee822 905 counter = attr->counter;
5a7e5bcb
VB		 906 if (!IS_ERR_OR_NULL(flow->rule[0]))
907 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 908 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 909
b6fac0b4 910 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 911 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 912 mlx5_destroy_flow_table(priv->fs.tc.t);
913 priv->fs.tc.t = NULL;
914 }
b6fac0b4 915 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 916
513f8f7f 917 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 918 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 919
226f2ca3 920 if (flow_flag_test(flow, HAIRPIN))
5c65c564 921 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 922}
923
aa0cbbae 924static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 925 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 926
3c37745e 927static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 928 struct mlx5e_tc_flow *flow,
733d4f36
RD		 929 struct net_device *mirred_dev,
930 int out_index,
8c4dc42b 931 struct netlink_ext_ack *extack,
0ad060ee
RD		 932 struct net_device **encap_dev,
933 bool *encap_valid);
3c37745e 934
6d2a3ed0
OG		 935static struct mlx5_flow_handle *
936mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
937 struct mlx5e_tc_flow *flow,
938 struct mlx5_flow_spec *spec,
939 struct mlx5_esw_flow_attr *attr)
940{
941 struct mlx5_flow_handle *rule;
942
943 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
944 if (IS_ERR(rule))
945 return rule;
946
e85e02ba 947 if (attr->split_count) {
6d2a3ed0
OG		 948 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
949 if (IS_ERR(flow->rule[1])) {
950 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
951 return flow->rule[1];
952 }
953 }
954
6d2a3ed0
OG		 955 return rule;
956}
957
958static void
959mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
960 struct mlx5e_tc_flow *flow,
961 struct mlx5_esw_flow_attr *attr)
962{
226f2ca3 963 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 964
e85e02ba 965 if (attr->split_count)
6d2a3ed0
OG		 966 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
967
968 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
969}
970
5dbe906f
PB		 971static struct mlx5_flow_handle *
972mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
973 struct mlx5e_tc_flow *flow,
974 struct mlx5_flow_spec *spec,
975 struct mlx5_esw_flow_attr *slow_attr)
976{
977 struct mlx5_flow_handle *rule;
978
979 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 980 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 981 slow_attr->split_count = 0;
154e62ab 982 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 983
984 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
985 if (!IS_ERR(rule))
226f2ca3 986 flow_flag_set(flow, SLOW);
5dbe906f
PB		 987
988 return rule;
989}
990
991static void
992mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
993 struct mlx5e_tc_flow *flow,
994 struct mlx5_esw_flow_attr *slow_attr)
995{
996 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 997 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 998 slow_attr->split_count = 0;
154e62ab 999 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f 1000 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1001 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1002}
1003
ad86755b
VB		 1004/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1005 * function.
1006 */
1007static void unready_flow_add(struct mlx5e_tc_flow *flow,
1008 struct list_head *unready_flows)
1009{
1010 flow_flag_set(flow, NOT_READY);
1011 list_add_tail(&flow->unready, unready_flows);
1012}
1013
1014/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1015 * function.
1016 */
1017static void unready_flow_del(struct mlx5e_tc_flow *flow)
1018{
1019 list_del(&flow->unready);
1020 flow_flag_clear(flow, NOT_READY);
1021}
1022
b4a23329
RD		 1023static void add_unready_flow(struct mlx5e_tc_flow *flow)
1024{
1025 struct mlx5_rep_uplink_priv *uplink_priv;
1026 struct mlx5e_rep_priv *rpriv;
1027 struct mlx5_eswitch *esw;
1028
1029 esw = flow->priv->mdev->priv.eswitch;
1030 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1031 uplink_priv = &rpriv->uplink_priv;
1032
ad86755b
VB		 1033 mutex_lock(&uplink_priv->unready_flows_lock);
1034 unready_flow_add(flow, &uplink_priv->unready_flows);
1035 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1036}
1037
1038static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1039{
ad86755b
VB		 1040 struct mlx5_rep_uplink_priv *uplink_priv;
1041 struct mlx5e_rep_priv *rpriv;
1042 struct mlx5_eswitch *esw;
1043
1044 esw = flow->priv->mdev->priv.eswitch;
1045 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1046 uplink_priv = &rpriv->uplink_priv;
1047
1048 mutex_lock(&uplink_priv->unready_flows_lock);
1049 unready_flow_del(flow);
1050 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1051}
1052
c83954ab 1053static int
74491de9 1054mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1055 struct mlx5e_tc_flow *flow,
1056 struct netlink_ext_ack *extack)
adb4c123
OG		 1057{
1058 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 1059 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 1060 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1061 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 1062 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 1063 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1064 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1065 struct mlx5e_rep_priv *rpriv;
1066 struct mlx5e_priv *out_priv;
0ad060ee
RD		 1067 bool encap_valid = true;
1068 int err = 0;
f493f155 1069 int out_index;
8b32580d 1070
d14f6f2a
OG		 1071 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1072 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1073 return -EOPNOTSUPP;
1074 }
bf07aa73
PB		 1075
1076 if (attr->chain > max_chain) {
1077 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
5a7e5bcb 1078 return -EOPNOTSUPP;
bf07aa73
PB		 1079 }
1080
1081 if (attr->prio > max_prio) {
1082 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
5a7e5bcb 1083 return -EOPNOTSUPP;
bf07aa73 1084 }
e52c2802 1085
f493f155 1086 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1087 int mirred_ifindex;
1088
f493f155
EB		 1089 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1090 continue;
1091
7040632d 1092 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1093 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1094 mirred_ifindex);
733d4f36 1095 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1096 extack, &encap_dev, &encap_valid);
1097 if (err)
5a7e5bcb 1098 return err;
0ad060ee 1099
3c37745e
OG		 1100 out_priv = netdev_priv(encap_dev);
1101 rpriv = out_priv->ppriv;
1cc26d74
EB		 1102 attr->dests[out_index].rep = rpriv->rep;
1103 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1104 }
1105
8b32580d 1106 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1107 if (err)
5a7e5bcb 1108 return err;
adb4c123 1109
d7e75a32 1110 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1111 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1112 kfree(parse_attr->mod_hdr_actions);
c83954ab 1113 if (err)
5a7e5bcb 1114 return err;
d7e75a32
OG		 1115 }
1116
b8aee822 1117 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1118 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1119 if (IS_ERR(counter))
1120 return PTR_ERR(counter);
b8aee822
MB		 1121
1122 attr->counter = counter;
1123 }
1124
0ad060ee
RD		 1125 /* we get here if one of the following takes place:
1126 * (1) there's no error
1127 * (2) there's an encap action and we don't have valid neigh
3c37745e 1128 */
0ad060ee 1129 if (!encap_valid) {
5dbe906f
PB		 1130 /* continue with goto slow path rule instead */
1131 struct mlx5_esw_flow_attr slow_attr;
1132
1133 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1134 } else {
6d2a3ed0 1135 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1136 }
c83954ab 1137
5a7e5bcb
VB		 1138 if (IS_ERR(flow->rule[0]))
1139 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1140 else
1141 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1142
1143 return 0;
aa0cbbae 1144}
d85cdccb 1145
9272e3df
YK		 1146static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1147{
1148 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1149 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1150 spec->match_value,
1151 misc_parameters_3);
1152 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1153 headers_v,
1154 geneve_tlv_option_0_data);
1155
1156 return !!geneve_tlv_opt_0_data;
1157}
1158
d85cdccb
OG		 1159static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1160 struct mlx5e_tc_flow *flow)
1161{
1162 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1163 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1164 struct mlx5_esw_flow_attr slow_attr;
f493f155 1165 int out_index;
d85cdccb 1166
226f2ca3 1167 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1168 remove_unready_flow(flow);
ef06c9ee
RD		 1169 kvfree(attr->parse_attr);
1170 return;
1171 }
1172
226f2ca3
VB		 1173 if (mlx5e_is_offloaded_flow(flow)) {
1174 if (flow_flag_test(flow, SLOW))
5dbe906f
PB		 1175 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1176 else
1177 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1178 }
d85cdccb 1179
9272e3df
YK		 1180 if (mlx5_flow_has_geneve_opt(flow))
1181 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1182
513f8f7f 1183 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1184
f493f155 1185 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1186 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1187 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1188 kvfree(attr->parse_attr);
d7e75a32 1189
513f8f7f 1190 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1191 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1192
1193 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1194 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1195}
1196
232c0013
HHZ		 1197void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1198 struct mlx5e_encap_entry *e)
1199{
3c37745e 1200 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1201 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
5a7e5bcb 1202 struct encap_flow_item *efi, *tmp;
6d2a3ed0
OG		 1203 struct mlx5_flow_handle *rule;
1204 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1205 struct mlx5e_tc_flow *flow;
1206 int err;
1207
54c177ca
OS		 1208 err = mlx5_packet_reformat_alloc(priv->mdev,
1209 e->reformat_type,
60786f09 1210 e->encap_size, e->encap_header,
31ca3648 1211 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1212 &e->encap_id);
232c0013
HHZ		 1213 if (err) {
1214 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1215 err);
1216 return;
1217 }
1218 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1219 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1220
5a7e5bcb 1221 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
8c4dc42b
EB		 1222 bool all_flow_encaps_valid = true;
1223 int i;
1224
79baaec7 1225 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5a7e5bcb
VB		 1226 if (IS_ERR(mlx5e_flow_get(flow)))
1227 continue;
1228
3c37745e 1229 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1230 spec = &esw_attr->parse_attr->spec;
1231
8c4dc42b
EB		 1232 esw_attr->dests[efi->index].encap_id = e->encap_id;
1233 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1234 /* Flow can be associated with multiple encap entries.
1235 * Before offloading the flow verify that all of them have
1236 * a valid neighbour.
1237 */
1238 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1239 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1240 continue;
1241 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1242 all_flow_encaps_valid = false;
1243 break;
1244 }
1245 }
1246 /* Do not offload flows with unresolved neighbors */
1247 if (!all_flow_encaps_valid)
5a7e5bcb 1248 goto loop_cont;
5dbe906f 1249 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1250 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1251 if (IS_ERR(rule)) {
1252 err = PTR_ERR(rule);
232c0013
HHZ		 1253 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1254 err);
5a7e5bcb 1255 goto loop_cont;
232c0013 1256 }
5dbe906f
PB		 1257
1258 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
6d2a3ed0 1259 flow->rule[0] = rule;
226f2ca3
VB		 1260 /* was unset when slow path rule removed */
1261 flow_flag_set(flow, OFFLOADED);
5a7e5bcb
VB		 1262
1263loop_cont:
1264 mlx5e_flow_put(priv, flow);
232c0013
HHZ		 1265 }
1266}
1267
1268void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1269 struct mlx5e_encap_entry *e)
1270{
3c37745e 1271 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1272 struct mlx5_esw_flow_attr slow_attr;
5a7e5bcb 1273 struct encap_flow_item *efi, *tmp;
5dbe906f
PB		 1274 struct mlx5_flow_handle *rule;
1275 struct mlx5_flow_spec *spec;
232c0013 1276 struct mlx5e_tc_flow *flow;
5dbe906f 1277 int err;
232c0013 1278
5a7e5bcb 1279 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7 1280 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5a7e5bcb
VB		 1281 if (IS_ERR(mlx5e_flow_get(flow)))
1282 continue;
1283
5dbe906f
PB		 1284 spec = &flow->esw_attr->parse_attr->spec;
1285
1286 /* update from encap rule to slow path rule */
1287 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1288 /* mark the flow's encap dest as non-valid */
1289 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1290
1291 if (IS_ERR(rule)) {
1292 err = PTR_ERR(rule);
1293 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1294 err);
5a7e5bcb 1295 goto loop_cont;
5dbe906f
PB		 1296 }
1297
1298 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1299 flow->rule[0] = rule;
226f2ca3
VB		 1300 /* was unset when fast path rule removed */
1301 flow_flag_set(flow, OFFLOADED);
5a7e5bcb
VB		 1302
1303loop_cont:
1304 mlx5e_flow_put(priv, flow);
232c0013
HHZ		 1305 }
1306
61c806da
OG		 1307 /* we know that the encap is valid */
1308 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1309 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1310}
1311
b8aee822
MB		 1312static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1313{
226f2ca3 1314 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1315 return flow->esw_attr->counter;
1316 else
1317 return flow->nic_attr->counter;
1318}
1319
f6dfb4c3
HHZ		 1320void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1321{
1322 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1323 u64 bytes, packets, lastuse = 0;
1324 struct mlx5e_tc_flow *flow;
1325 struct mlx5e_encap_entry *e;
1326 struct mlx5_fc *counter;
1327 struct neigh_table *tbl;
1328 bool neigh_used = false;
1329 struct neighbour *n;
1330
1331 if (m_neigh->family == AF_INET)
1332 tbl = &arp_tbl;
1333#if IS_ENABLED(CONFIG_IPV6)
1334 else if (m_neigh->family == AF_INET6)
423c9db2 1335 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1336#endif
1337 else
1338 return;
1339
1340 list_for_each_entry(e, &nhe->encap_list, encap_list) {
5a7e5bcb 1341 struct encap_flow_item *efi, *tmp;
f6dfb4c3
HHZ		 1342 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1343 continue;
5a7e5bcb 1344 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1345 flow = container_of(efi, struct mlx5e_tc_flow,
1346 encaps[efi->index]);
5a7e5bcb
VB		 1347 if (IS_ERR(mlx5e_flow_get(flow)))
1348 continue;
1349
226f2ca3 1350 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1351 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1352 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1353 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
5a7e5bcb 1354 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
f6dfb4c3
HHZ		 1355 neigh_used = true;
1356 break;
1357 }
1358 }
5a7e5bcb
VB		 1359
1360 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
f6dfb4c3 1361 }
e36d4810
RD		 1362 if (neigh_used)
1363 break;
f6dfb4c3
HHZ		 1364 }
1365
1366 if (neigh_used) {
1367 nhe->reported_lastuse = jiffies;
1368
1369 /* find the relevant neigh according to the cached device and
1370 * dst ip pair
1371 */
1372 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1373 if (!n)
f6dfb4c3 1374 return;
f6dfb4c3
HHZ		 1375
1376 neigh_event_send(n, NULL);
1377 neigh_release(n);
1378 }
1379}
1380
d85cdccb 1381static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1382 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1383{
8c4dc42b 1384 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1385
5a7e5bcb
VB		 1386 /* flow wasn't fully initialized */
1387 if (list_empty(&flow->encaps[out_index].list))
1388 return;
1389
8c4dc42b 1390 list_del(&flow->encaps[out_index].list);
5067b602 1391 if (list_empty(next)) {
c1ae1152 1392 struct mlx5e_encap_entry *e;
5067b602 1393
c1ae1152 1394 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1395 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1396
1397 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1398 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1399
cdc5a7f3 1400 hash_del_rcu(&e->encap_hlist);
232c0013 1401 kfree(e->encap_header);
5067b602
RD		 1402 kfree(e);
1403 }
1404}
1405
04de7dda
RD		 1406static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1407{
1408 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1409
226f2ca3
VB		 1410 if (!flow_flag_test(flow, ESWITCH) ||
1411 !flow_flag_test(flow, DUP))
04de7dda
RD		 1412 return;
1413
1414 mutex_lock(&esw->offloads.peer_mutex);
1415 list_del(&flow->peer);
1416 mutex_unlock(&esw->offloads.peer_mutex);
1417
226f2ca3 1418 flow_flag_clear(flow, DUP);
04de7dda
RD		 1419
1420 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1421 kvfree(flow->peer_flow);
1422 flow->peer_flow = NULL;
1423}
1424
1425static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1426{
1427 struct mlx5_core_dev *dev = flow->priv->mdev;
1428 struct mlx5_devcom *devcom = dev->priv.devcom;
1429 struct mlx5_eswitch *peer_esw;
1430
1431 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1432 if (!peer_esw)
1433 return;
1434
1435 __mlx5e_tc_del_fdb_peer_flow(flow);
1436 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1437}
1438
e8f887ac 1439static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1440 struct mlx5e_tc_flow *flow)
e8f887ac 1441{
226f2ca3 1442 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1443 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1444 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1445 } else {
d85cdccb 1446 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1447 }
e8f887ac
AV		 1448}
1449
bbd00f7e
HHZ		 1450
1451static int parse_tunnel_attr(struct mlx5e_priv *priv,
1452 struct mlx5_flow_spec *spec,
f9e30088 1453 struct flow_cls_offload *f,
6363651d 1454 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1455{
e98bedf5 1456 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1457 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1458 outer_headers);
1459 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1460 outer_headers);
f9e30088 1461 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1462 int err;
2e72eb43 1463
101f4de9 1464 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1465 headers_c, headers_v, match_level);
54c177ca
OS		 1466 if (err) {
1467 NL_SET_ERR_MSG_MOD(extack,
1468 "failed to parse tunnel attributes");
101f4de9 1469 return err;
bbd00f7e
HHZ		 1470 }
1471
d1bda7ee 1472 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
8f256622
PNA		 1473 struct flow_match_ipv4_addrs match;
1474
1475 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1476 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1477 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1478 ntohl(match.mask->src));
bbd00f7e
HHZ		 1479 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1480 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1481 ntohl(match.key->src));
bbd00f7e
HHZ		 1482
1483 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1484 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1485 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1486 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1487 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1488 ntohl(match.key->dst));
bbd00f7e 1489
2e72eb43
OG		 1490 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
d1bda7ee 1492 } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
8f256622 1493 struct flow_match_ipv6_addrs match;
19f44401 1494
8f256622 1495 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1496 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1497 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1498 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1499 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1500 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1501 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1502
1503 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1504 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1505 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1506 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1507 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1508 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1509
1510 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1512 }
bbd00f7e 1513
8f256622
PNA		 1514 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1515 struct flow_match_ip match;
bcef735c 1516
8f256622
PNA		 1517 flow_rule_match_enc_ip(rule, &match);
1518 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1519 match.mask->tos & 0x3);
1520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1521 match.key->tos & 0x3);
bcef735c 1522
8f256622
PNA		 1523 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1524 match.mask->tos >> 2);
1525 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1526 match.key->tos >> 2);
bcef735c 1527
8f256622
PNA		 1528 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1529 match.mask->ttl);
1530 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1531 match.key->ttl);
e98bedf5 1532
8f256622 1533 if (match.mask->ttl &&
e98bedf5
EB		 1534 !MLX5_CAP_ESW_FLOWTABLE_FDB
1535 (priv->mdev,
1536 ft_field_support.outer_ipv4_ttl)) {
1537 NL_SET_ERR_MSG_MOD(extack,
1538 "Matching on TTL is not supported");
1539 return -EOPNOTSUPP;
1540 }
1541
bcef735c
OG		 1542 }
1543
bbd00f7e
HHZ		 1544 /* Enforce DMAC when offloading incoming tunneled flows.
1545 * Flow counters require a match on the DMAC.
1546 */
1547 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1548 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1549 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1550 dmac_47_16), priv->netdev->dev_addr);
1551
1552 /* let software handle IP fragments */
1553 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1554 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1555
1556 return 0;
1557}
1558
8377629e
EB		 1559static void *get_match_headers_criteria(u32 flags,
1560 struct mlx5_flow_spec *spec)
1561{
1562 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1563 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1564 inner_headers) :
1565 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1566 outer_headers);
1567}
1568
1569static void *get_match_headers_value(u32 flags,
1570 struct mlx5_flow_spec *spec)
1571{
1572 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1573 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1574 inner_headers) :
1575 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1576 outer_headers);
1577}
1578
de0af0bf
RD		 1579static int __parse_cls_flower(struct mlx5e_priv *priv,
1580 struct mlx5_flow_spec *spec,
f9e30088 1581 struct flow_cls_offload *f,
54c177ca 1582 struct net_device *filter_dev,
6363651d 1583 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1584{
e98bedf5 1585 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1586 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1587 outer_headers);
1588 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1589 outer_headers);
699e96dd
JL		 1590 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1591 misc_parameters);
1592 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1593 misc_parameters);
f9e30088 1594 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1595 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1596 u16 addr_type = 0;
1597 u8 ip_proto = 0;
1598
d708f902 1599 *match_level = MLX5_MATCH_NONE;
de0af0bf 1600
8f256622 1601 if (dissector->used_keys &
3d144578
VB		 1602 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1603 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1604 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1605 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1606 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1607 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1608 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1609 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1610 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1611 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1612 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1613 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1614 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1615 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1616 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1617 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1618 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1619 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1620 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1621 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1622 dissector->used_keys);
e3a2b7ed
AV		 1623 return -EOPNOTSUPP;
1624 }
1625
075973c7 1626 if (mlx5e_get_tc_tun(filter_dev)) {
d1bda7ee 1627 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e 1628 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1629
1630 /* In decap flow, header pointers should point to the inner
1631 * headers, outer header were already set by parse_tunnel_attr
1632 */
8377629e
EB		 1633 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1634 spec);
1635 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1636 spec);
bbd00f7e
HHZ		 1637 }
1638
8f256622
PNA		 1639 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1640 struct flow_match_basic match;
1641
1642 flow_rule_match_basic(rule, &match);
d3a80bb5 1643 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1644 ntohs(match.mask->n_proto));
d3a80bb5 1645 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1646 ntohs(match.key->n_proto));
e3a2b7ed 1647
8f256622 1648 if (match.mask->n_proto)
d708f902 1649 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1650 }
35a605db
EB		 1651 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1652 is_vlan_dev(filter_dev)) {
1653 struct flow_dissector_key_vlan filter_dev_mask;
1654 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1655 struct flow_match_vlan match;
1656
35a605db
EB		 1657 if (is_vlan_dev(filter_dev)) {
1658 match.key = &filter_dev_key;
1659 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1660 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1661 match.key->vlan_priority = 0;
1662 match.mask = &filter_dev_mask;
1663 memset(match.mask, 0xff, sizeof(*match.mask));
1664 match.mask->vlan_priority = 0;
1665 } else {
1666 flow_rule_match_vlan(rule, &match);
1667 }
8f256622
PNA		 1668 if (match.mask->vlan_id ||
1669 match.mask->vlan_priority ||
1670 match.mask->vlan_tpid) {
1671 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1672 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1673 svlan_tag, 1);
1674 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1675 svlan_tag, 1);
1676 } else {
1677 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1678 cvlan_tag, 1);
1679 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1680 cvlan_tag, 1);
1681 }
095b6cfd 1682
8f256622
PNA		 1683 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1684 match.mask->vlan_id);
1685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1686 match.key->vlan_id);
358d79a4 1687
8f256622
PNA		 1688 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1689 match.mask->vlan_priority);
1690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1691 match.key->vlan_priority);
54782900 1692
d708f902 1693 *match_level = MLX5_MATCH_L2;
54782900 1694 }
d3a80bb5 1695 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1696 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1697 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1698 *match_level = MLX5_MATCH_L2;
54782900
OG		 1699 }
1700
8f256622
PNA		 1701 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1702 struct flow_match_vlan match;
1703
12d5cbf8 1704 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1705 if (match.mask->vlan_id ||
1706 match.mask->vlan_priority ||
1707 match.mask->vlan_tpid) {
1708 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1709 MLX5_SET(fte_match_set_misc, misc_c,
1710 outer_second_svlan_tag, 1);
1711 MLX5_SET(fte_match_set_misc, misc_v,
1712 outer_second_svlan_tag, 1);
1713 } else {
1714 MLX5_SET(fte_match_set_misc, misc_c,
1715 outer_second_cvlan_tag, 1);
1716 MLX5_SET(fte_match_set_misc, misc_v,
1717 outer_second_cvlan_tag, 1);
1718 }
1719
1720 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1721 match.mask->vlan_id);
699e96dd 1722 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1723 match.key->vlan_id);
699e96dd 1724 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1725 match.mask->vlan_priority);
699e96dd 1726 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1727 match.key->vlan_priority);
699e96dd
JL		 1728
1729 *match_level = MLX5_MATCH_L2;
1730 }
1731 }
1732
8f256622
PNA		 1733 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1734 struct flow_match_eth_addrs match;
54782900 1735
8f256622 1736 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1737 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1738 dmac_47_16),
8f256622 1739 match.mask->dst);
d3a80bb5
OG		 1740 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1741 dmac_47_16),
8f256622 1742 match.key->dst);
d3a80bb5
OG		 1743
1744 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1745 smac_47_16),
8f256622 1746 match.mask->src);
d3a80bb5
OG		 1747 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1748 smac_47_16),
8f256622 1749 match.key->src);
d3a80bb5 1750
8f256622
PNA		 1751 if (!is_zero_ether_addr(match.mask->src) ||
1752 !is_zero_ether_addr(match.mask->dst))
d708f902 1753 *match_level = MLX5_MATCH_L2;
54782900
OG		 1754 }
1755
8f256622
PNA		 1756 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1757 struct flow_match_control match;
54782900 1758
8f256622
PNA		 1759 flow_rule_match_control(rule, &match);
1760 addr_type = match.key->addr_type;
54782900
OG		 1761
1762 /* the HW doesn't support frag first/later */
8f256622 1763 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1764 return -EOPNOTSUPP;
1765
8f256622 1766 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1767 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1768 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1769 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1770
1771 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1772 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1773 *match_level = MLX5_MATCH_L2;
54782900
OG		 1774 /* *** L2 attributes parsing up to here *** */
1775 else
83621b7d 1776 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1777 }
1778 }
1779
8f256622
PNA		 1780 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1781 struct flow_match_basic match;
1782
1783 flow_rule_match_basic(rule, &match);
1784 ip_proto = match.key->ip_proto;
54782900
OG		 1785
1786 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1787 match.mask->ip_proto);
54782900 1788 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1789 match.key->ip_proto);
54782900 1790
8f256622 1791 if (match.mask->ip_proto)
d708f902 1792 *match_level = MLX5_MATCH_L3;
54782900
OG		 1793 }
1794
e3a2b7ed 1795 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1796 struct flow_match_ipv4_addrs match;
e3a2b7ed 1797
8f256622 1798 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1799 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1800 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1801 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1802 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1803 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1804 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1805 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1806 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1807 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1808 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1809 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1810 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1811
8f256622 1812 if (match.mask->src || match.mask->dst)
d708f902 1813 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1814 }
1815
1816 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1817 struct flow_match_ipv6_addrs match;
e3a2b7ed 1818
8f256622 1819 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1820 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1821 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1822 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1823 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1824 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1825 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1826
1827 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1828 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1829 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1830 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1831 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1832 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1833
8f256622
PNA		 1834 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1835 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1836 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1837 }
1838
8f256622
PNA		 1839 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1840 struct flow_match_ip match;
1f97a526 1841
8f256622
PNA		 1842 flow_rule_match_ip(rule, &match);
1843 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1844 match.mask->tos & 0x3);
1845 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1846 match.key->tos & 0x3);
1f97a526 1847
8f256622
PNA		 1848 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1849 match.mask->tos >> 2);
1850 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1851 match.key->tos >> 2);
1f97a526 1852
8f256622
PNA		 1853 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1854 match.mask->ttl);
1855 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1856 match.key->ttl);
1f97a526 1857
8f256622 1858 if (match.mask->ttl &&
a8ade55f 1859 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1860 ft_field_support.outer_ipv4_ttl)) {
1861 NL_SET_ERR_MSG_MOD(extack,
1862 "Matching on TTL is not supported");
1f97a526 1863 return -EOPNOTSUPP;
e98bedf5 1864 }
a8ade55f 1865
8f256622 1866 if (match.mask->tos || match.mask->ttl)
d708f902 1867 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1868 }
1869
54782900
OG		 1870 /* *** L3 attributes parsing up to here *** */
1871
8f256622
PNA		 1872 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1873 struct flow_match_ports match;
1874
1875 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1876 switch (ip_proto) {
1877 case IPPROTO_TCP:
1878 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1879 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1880 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1881 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1882
1883 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1884 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1885 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1886 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1887 break;
1888
1889 case IPPROTO_UDP:
1890 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1891 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1892 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1893 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1894
1895 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1896 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1897 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1898 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1899 break;
1900 default:
e98bedf5
EB		 1901 NL_SET_ERR_MSG_MOD(extack,
1902 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1903 netdev_err(priv->netdev,
1904 "Only UDP and TCP transport are supported\n");
1905 return -EINVAL;
1906 }
de0af0bf 1907
8f256622 1908 if (match.mask->src || match.mask->dst)
d708f902 1909 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1910 }
1911
8f256622
PNA		 1912 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1913 struct flow_match_tcp match;
e77834ec 1914
8f256622 1915 flow_rule_match_tcp(rule, &match);
e77834ec 1916 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1917 ntohs(match.mask->flags));
e77834ec 1918 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1919 ntohs(match.key->flags));
e77834ec 1920
8f256622 1921 if (match.mask->flags)
d708f902 1922 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1923 }
1924
e3a2b7ed
AV		 1925 return 0;
1926}
1927
de0af0bf 1928static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1929 struct mlx5e_tc_flow *flow,
de0af0bf 1930 struct mlx5_flow_spec *spec,
f9e30088 1931 struct flow_cls_offload *f,
54c177ca 1932 struct net_device *filter_dev)
de0af0bf 1933{
e98bedf5 1934 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1935 struct mlx5_core_dev *dev = priv->mdev;
1936 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1937 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1938 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1939 struct mlx5_eswitch_rep *rep;
226f2ca3 1940 bool is_eswitch_flow;
de0af0bf
RD		 1941 int err;
1942
6363651d 1943 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 1944
226f2ca3
VB		 1945 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
1946 if (!err && is_eswitch_flow) {
1d447a39 1947 rep = rpriv->rep;
b05af6aa 1948 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 1949 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1950 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1951 NL_SET_ERR_MSG_MOD(extack,
1952 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1953 netdev_warn(priv->netdev,
1954 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1955 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1956 return -EOPNOTSUPP;
1957 }
1958 }
1959
226f2ca3 1960 if (is_eswitch_flow) {
38aa51c1 1961 flow->esw_attr->match_level = match_level;
6363651d
OG		 1962 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1963 } else {
38aa51c1 1964 flow->nic_attr->match_level = match_level;
6363651d 1965 }
38aa51c1 1966
de0af0bf
RD		 1967 return err;
1968}
1969
d79b6df6
OG		 1970struct pedit_headers {
1971 struct ethhdr eth;
0eb69bb9 1972 struct vlan_hdr vlan;
d79b6df6
OG		 1973 struct iphdr ip4;
1974 struct ipv6hdr ip6;
1975 struct tcphdr tcp;
1976 struct udphdr udp;
1977};
1978
c500c86b
PNA		 1979struct pedit_headers_action {
1980 struct pedit_headers vals;
1981 struct pedit_headers masks;
1982 u32 pedits;
1983};
1984
d79b6df6 1985static int pedit_header_offsets[] = {
73867881
PNA		 1986 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1987 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1988 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1989 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1990 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 1991};
1992
1993#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1994
1995static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 1996 struct pedit_headers_action *hdrs)
d79b6df6
OG		 1997{
1998 u32 *curr_pmask, *curr_pval;
1999
c500c86b
PNA		 2000 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2001 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2002
2003 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2004 goto out_err;
2005
2006 *curr_pmask |= mask;
2007 *curr_pval |= (val & mask);
2008
2009 return 0;
2010
2011out_err:
2012 return -EOPNOTSUPP;
2013}
2014
2015struct mlx5_fields {
2016 u8 field;
2017 u8 size;
2018 u32 offset;
27c11b6b 2019 u32 match_offset;
d79b6df6
OG		 2020};
2021
27c11b6b
EB		 2022#define OFFLOAD(fw_field, size, field, off, match_field) \
2023 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2024 offsetof(struct pedit_headers, field) + (off), \
2025 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2026
2ef86872
EB		 2027/* masked values are the same and there are no rewrites that do not have a
2028 * match.
2029 */
2030#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2031 type matchmaskx = *(type *)(matchmaskp); \
2032 type matchvalx = *(type *)(matchvalp); \
2033 type maskx = *(type *)(maskp); \
2034 type valx = *(type *)(valp); \
2035 \
2036 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2037 matchmaskx)); \
2038})
2039
27c11b6b
EB		 2040static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2041 void *matchmaskp, int size)
2042{
2043 bool same = false;
2044
2045 switch (size) {
2046 case sizeof(u8):
2ef86872 2047 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2048 break;
2049 case sizeof(u16):
2ef86872 2050 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2051 break;
2052 case sizeof(u32):
2ef86872 2053 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2054 break;
2055 }
2056
2057 return same;
2058}
a8e4f0c4 2059
d79b6df6 2060static struct mlx5_fields fields[] = {
27c11b6b
EB		 2061 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2062 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
2063 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2064 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
2065 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
2066 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
2067
2068 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
2069 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2070 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2071
2072 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2073 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2074 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
2075 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2076 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
2077 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2078 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
2079 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2080 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2081 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2082 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
2083 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2084 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
2085 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2086 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
2087 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2088 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2089
2090 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
2091 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
2092 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2093
2094 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2095 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
d79b6df6
OG		 2096};
2097
218d05ce
TZ		 2098/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2099 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2100 * says how many HW actions were actually parsed.
d79b6df6 2101 */
c500c86b 2102static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2103 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2104 u32 *action_flags,
e98bedf5 2105 struct netlink_ext_ack *extack)
d79b6df6
OG		 2106{
2107 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
27c11b6b
EB		 2108 void *headers_c = get_match_headers_criteria(*action_flags,
2109 &parse_attr->spec);
2110 void *headers_v = get_match_headers_value(*action_flags,
2111 &parse_attr->spec);
2b64beba 2112 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 2113 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 2114 struct mlx5_fields *f;
2115 u8 cmd, field_bsize;
e3ca4e05 2116 u32 s_mask, a_mask;
d79b6df6 2117 unsigned long mask;
2b64beba
OG		 2118 __be32 mask_be32;
2119 __be16 mask_be16;
d79b6df6
OG		 2120 void *action;
2121
73867881
PNA		 2122 set_masks = &hdrs[0].masks;
2123 add_masks = &hdrs[1].masks;
2124 set_vals = &hdrs[0].vals;
2125 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2126
2127 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2128 action = parse_attr->mod_hdr_actions +
2129 parse_attr->num_mod_hdr_actions * action_size;
2130
2131 max_actions = parse_attr->max_mod_hdr_actions;
2132 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2133
2134 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2135 bool skip;
2136
d79b6df6
OG		 2137 f = &fields[i];
2138 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2139 s_mask = 0;
2140 a_mask = 0;
d79b6df6
OG		 2141
2142 s_masks_p = (void *)set_masks + f->offset;
2143 a_masks_p = (void *)add_masks + f->offset;
2144
2145 memcpy(&s_mask, s_masks_p, f->size);
2146 memcpy(&a_mask, a_masks_p, f->size);
2147
2148 if (!s_mask && !a_mask) /* nothing to offload here */
2149 continue;
2150
2151 if (s_mask && a_mask) {
e98bedf5
EB		 2152 NL_SET_ERR_MSG_MOD(extack,
2153 "can't set and add to the same HW field");
d79b6df6
OG		 2154 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2155 return -EOPNOTSUPP;
2156 }
2157
2158 if (nactions == max_actions) {
e98bedf5
EB		 2159 NL_SET_ERR_MSG_MOD(extack,
2160 "too many pedit actions, can't offload");
d79b6df6
OG		 2161 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2162 return -EOPNOTSUPP;
2163 }
2164
27c11b6b 2165 skip = false;
d79b6df6 2166 if (s_mask) {
27c11b6b
EB		 2167 void *match_mask = headers_c + f->match_offset;
2168 void *match_val = headers_v + f->match_offset;
2169
d79b6df6
OG		 2170 cmd = MLX5_ACTION_TYPE_SET;
2171 mask = s_mask;
2172 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2173 /* don't rewrite if we have a match on the same value */
2174 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2175 match_mask, f->size))
2176 skip = true;
d79b6df6
OG		 2177 /* clear to denote we consumed this field */
2178 memset(s_masks_p, 0, f->size);
2179 } else {
27c11b6b
EB		 2180 u32 zero = 0;
2181
d79b6df6
OG		 2182 cmd = MLX5_ACTION_TYPE_ADD;
2183 mask = a_mask;
2184 vals_p = (void *)add_vals + f->offset;
27c11b6b
EB		 2185 /* add 0 is no change */
2186 if (!memcmp(vals_p, &zero, f->size))
2187 skip = true;
d79b6df6
OG		 2188 /* clear to denote we consumed this field */
2189 memset(a_masks_p, 0, f->size);
2190 }
27c11b6b
EB		 2191 if (skip)
2192 continue;
d79b6df6 2193
d79b6df6 2194 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2195
2b64beba
OG		 2196 if (field_bsize == 32) {
2197 mask_be32 = *(__be32 *)&mask;
2198 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2199 } else if (field_bsize == 16) {
2200 mask_be16 = *(__be16 *)&mask;
2201 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2202 }
2203
d79b6df6 2204 first = find_first_bit(&mask, field_bsize);
2b64beba 2205 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2206 last = find_last_bit(&mask, field_bsize);
2b64beba 2207 if (first < next_z && next_z < last) {
e98bedf5
EB		 2208 NL_SET_ERR_MSG_MOD(extack,
2209 "rewrite of few sub-fields isn't supported");
2b64beba 2210 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2211 mask);
2212 return -EOPNOTSUPP;
2213 }
2214
2215 MLX5_SET(set_action_in, action, action_type, cmd);
2216 MLX5_SET(set_action_in, action, field, f->field);
2217
2218 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2219 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2220 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2221 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2222 }
2223
2224 if (field_bsize == 32)
2b64beba 2225 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2226 else if (field_bsize == 16)
2b64beba 2227 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2228 else if (field_bsize == 8)
2b64beba 2229 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2230
2231 action += action_size;
2232 nactions++;
2233 }
2234
2235 parse_attr->num_mod_hdr_actions = nactions;
2236 return 0;
2237}
2238
2cc1cb1d
TZ		 2239static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2240 int namespace)
2241{
2242 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2243 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2244 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2245 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2246}
2247
d79b6df6 2248static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2249 struct pedit_headers_action *hdrs,
2250 int namespace,
d79b6df6
OG		 2251 struct mlx5e_tc_flow_parse_attr *parse_attr)
2252{
2253 int nkeys, action_size, max_actions;
2254
c500c86b
PNA		 2255 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2256 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2257 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2258
2cc1cb1d 2259 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2260 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2261 max_actions = min(max_actions, nkeys * 16);
2262
2263 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2264 if (!parse_attr->mod_hdr_actions)
2265 return -ENOMEM;
2266
218d05ce 2267 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2268 return 0;
2269}
2270
2271static const struct pedit_headers zero_masks = {};
2272
2273static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2274 const struct flow_action_entry *act, int namespace,
e98bedf5 2275 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2276 struct pedit_headers_action *hdrs,
e98bedf5 2277 struct netlink_ext_ack *extack)
d79b6df6 2278{
73867881
PNA		 2279 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2280 int err = -EOPNOTSUPP;
d79b6df6 2281 u32 mask, val, offset;
73867881 2282 u8 htype;
d79b6df6 2283
73867881
PNA		 2284 htype = act->mangle.htype;
2285 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2286
73867881
PNA		 2287 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2288 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2289 goto out_err;
2290 }
d79b6df6 2291
2cc1cb1d
TZ		 2292 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2293 NL_SET_ERR_MSG_MOD(extack,
2294 "The pedit offload action is not supported");
2295 goto out_err;
2296 }
2297
73867881
PNA		 2298 mask = act->mangle.mask;
2299 val = act->mangle.val;
2300 offset = act->mangle.offset;
d79b6df6 2301
73867881
PNA		 2302 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2303 if (err)
2304 goto out_err;
c500c86b 2305
73867881 2306 hdrs[cmd].pedits++;
d79b6df6 2307
c500c86b
PNA		 2308 return 0;
2309out_err:
2310 return err;
2311}
2312
2313static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2314 struct mlx5e_tc_flow_parse_attr *parse_attr,
2315 struct pedit_headers_action *hdrs,
27c11b6b 2316 u32 *action_flags,
c500c86b
PNA		 2317 struct netlink_ext_ack *extack)
2318{
2319 struct pedit_headers *cmd_masks;
2320 int err;
2321 u8 cmd;
2322
218d05ce 2323 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2324 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2325 if (err)
2326 goto out_err;
2327 }
d79b6df6 2328
27c11b6b 2329 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2330 if (err < 0)
2331 goto out_dealloc_parsed_actions;
2332
2333 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2334 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2335 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2336 NL_SET_ERR_MSG_MOD(extack,
2337 "attempt to offload an unsupported field");
b3a433de 2338 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2339 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2340 16, 1, cmd_masks, sizeof(zero_masks), true);
2341 err = -EOPNOTSUPP;
2342 goto out_dealloc_parsed_actions;
2343 }
2344 }
2345
2346 return 0;
2347
2348out_dealloc_parsed_actions:
2349 kfree(parse_attr->mod_hdr_actions);
2350out_err:
2351 return err;
2352}
2353
e98bedf5
EB		 2354static bool csum_offload_supported(struct mlx5e_priv *priv,
2355 u32 action,
2356 u32 update_flags,
2357 struct netlink_ext_ack *extack)
26c02749
OG		 2358{
2359 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2360 TCA_CSUM_UPDATE_FLAG_UDP;
2361
2362 /* The HW recalcs checksums only if re-writing headers */
2363 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2364 NL_SET_ERR_MSG_MOD(extack,
2365 "TC csum action is only offloaded with pedit");
26c02749
OG		 2366 netdev_warn(priv->netdev,
2367 "TC csum action is only offloaded with pedit\n");
2368 return false;
2369 }
2370
2371 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2372 NL_SET_ERR_MSG_MOD(extack,
2373 "can't offload TC csum action for some header/s");
26c02749
OG		 2374 netdev_warn(priv->netdev,
2375 "can't offload TC csum action for some header/s - flags %#x\n",
2376 update_flags);
2377 return false;
2378 }
2379
2380 return true;
2381}
2382
8998576b
DL		 2383struct ip_ttl_word {
2384 __u8 ttl;
2385 __u8 protocol;
2386 __sum16 check;
2387};
2388
2389struct ipv6_hoplimit_word {
2390 __be16 payload_len;
2391 __u8 nexthdr;
2392 __u8 hop_limit;
2393};
2394
2395static bool is_action_keys_supported(const struct flow_action_entry *act)
2396{
2397 u32 mask, offset;
2398 u8 htype;
2399
2400 htype = act->mangle.htype;
2401 offset = act->mangle.offset;
2402 mask = ~act->mangle.mask;
2403 /* For IPv4 & IPv6 header check 4 byte word,
2404 * to determine that modified fields
2405 * are NOT ttl & hop_limit only.
2406 */
2407 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2408 struct ip_ttl_word *ttl_word =
2409 (struct ip_ttl_word *)&mask;
2410
2411 if (offset != offsetof(struct iphdr, ttl) ||
2412 ttl_word->protocol ||
2413 ttl_word->check) {
2414 return true;
2415 }
2416 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2417 struct ipv6_hoplimit_word *hoplimit_word =
2418 (struct ipv6_hoplimit_word *)&mask;
2419
2420 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2421 hoplimit_word->payload_len ||
2422 hoplimit_word->nexthdr) {
2423 return true;
2424 }
2425 }
2426 return false;
2427}
2428
bdd66ac0 2429static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2430 struct flow_action *flow_action,
1651925d 2431 u32 actions,
e98bedf5 2432 struct netlink_ext_ack *extack)
bdd66ac0 2433{
73867881 2434 const struct flow_action_entry *act;
bdd66ac0 2435 bool modify_ip_header;
bdd66ac0
OG		 2436 void *headers_v;
2437 u16 ethertype;
8998576b 2438 u8 ip_proto;
73867881 2439 int i;
bdd66ac0 2440
8377629e 2441 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2442 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2443
2444 /* for non-IP we only re-write MACs, so we're okay */
2445 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2446 goto out_ok;
2447
2448 modify_ip_header = false;
73867881
PNA		 2449 flow_action_for_each(i, act, flow_action) {
2450 if (act->id != FLOW_ACTION_MANGLE &&
2451 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2452 continue;
2453
8998576b 2454 if (is_action_keys_supported(act)) {
73867881
PNA		 2455 modify_ip_header = true;
2456 break;
bdd66ac0
OG		 2457 }
2458 }
2459
2460 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2461 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2462 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2463 NL_SET_ERR_MSG_MOD(extack,
2464 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2465 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2466 return false;
2467 }
2468
2469out_ok:
2470 return true;
2471}
2472
2473static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2474 struct flow_action *flow_action,
bdd66ac0 2475 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2476 struct mlx5e_tc_flow *flow,
2477 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2478{
2479 u32 actions;
2480
226f2ca3 2481 if (mlx5e_is_eswitch_flow(flow))
bdd66ac0
OG		 2482 actions = flow->esw_attr->action;
2483 else
2484 actions = flow->nic_attr->action;
2485
226f2ca3 2486 if (flow_flag_test(flow, EGRESS) &&
35a605db
EB		 2487 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2488 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)))
7e29392e
RD		 2489 return false;
2490
bdd66ac0 2491 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2492 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2493 flow_action, actions,
e98bedf5 2494 extack);
bdd66ac0
OG		 2495
2496 return true;
2497}
2498
5c65c564
OG		 2499static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2500{
2501 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2502 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2503
2504 fmdev = priv->mdev;
2505 pmdev = peer_priv->mdev;
2506
59c9d35e
AH		 2507 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2508 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2509
816f6706 2510 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2511}
2512
bdc837ee
EB		 2513static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2514 const struct flow_action_entry *act,
2515 struct mlx5e_tc_flow_parse_attr *parse_attr,
2516 struct pedit_headers_action *hdrs,
2517 u32 *action, struct netlink_ext_ack *extack)
2518{
2519 u16 mask16 = VLAN_VID_MASK;
2520 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2521 const struct flow_action_entry pedit_act = {
2522 .id = FLOW_ACTION_MANGLE,
2523 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2524 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2525 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2526 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2527 };
6fca9d1e 2528 u8 match_prio_mask, match_prio_val;
bf2f3bca 2529 void *headers_c, *headers_v;
bdc837ee
EB		 2530 int err;
2531
bf2f3bca
EB		 2532 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2533 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2534
2535 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2536 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2537 NL_SET_ERR_MSG_MOD(extack,
2538 "VLAN rewrite action must have VLAN protocol match");
2539 return -EOPNOTSUPP;
2540 }
2541
6fca9d1e
EB		 2542 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2543 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2544 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2545 NL_SET_ERR_MSG_MOD(extack,
2546 "Changing VLAN prio is not supported");
bdc837ee
EB		 2547 return -EOPNOTSUPP;
2548 }
2549
2550 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2551 hdrs, NULL);
2552 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2553
2554 return err;
2555}
2556
0bac1194
EB		 2557static int
2558add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2559 struct mlx5e_tc_flow_parse_attr *parse_attr,
2560 struct pedit_headers_action *hdrs,
2561 u32 *action, struct netlink_ext_ack *extack)
2562{
2563 const struct flow_action_entry prio_tag_act = {
2564 .vlan.vid = 0,
2565 .vlan.prio =
2566 MLX5_GET(fte_match_set_lyr_2_4,
2567 get_match_headers_value(*action,
2568 &parse_attr->spec),
2569 first_prio) &
2570 MLX5_GET(fte_match_set_lyr_2_4,
2571 get_match_headers_criteria(*action,
2572 &parse_attr->spec),
2573 first_prio),
2574 };
2575
2576 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2577 &prio_tag_act, parse_attr, hdrs, action,
2578 extack);
2579}
2580
73867881
PNA		 2581static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2582 struct flow_action *flow_action,
aa0cbbae 2583 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2584 struct mlx5e_tc_flow *flow,
2585 struct netlink_ext_ack *extack)
e3a2b7ed 2586{
aa0cbbae 2587 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2588 struct pedit_headers_action hdrs[2] = {};
2589 const struct flow_action_entry *act;
1cab1cd7 2590 u32 action = 0;
244cd96a 2591 int err, i;
e3a2b7ed 2592
73867881 2593 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2594 return -EINVAL;
2595
3bc4b7bf 2596 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2597
73867881
PNA		 2598 flow_action_for_each(i, act, flow_action) {
2599 switch (act->id) {
2600 case FLOW_ACTION_DROP:
1cab1cd7 2601 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2602 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2603 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2604 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2605 break;
2606 case FLOW_ACTION_MANGLE:
2607 case FLOW_ACTION_ADD:
2608 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2609 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2610 if (err)
2611 return err;
2612
1cab1cd7
OG		 2613 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2614 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2615 break;
bdc837ee
EB		 2616 case FLOW_ACTION_VLAN_MANGLE:
2617 err = add_vlan_rewrite_action(priv,
2618 MLX5_FLOW_NAMESPACE_KERNEL,
2619 act, parse_attr, hdrs,
2620 &action, extack);
2621 if (err)
2622 return err;
2623
2624 break;
73867881 2625 case FLOW_ACTION_CSUM:
1cab1cd7 2626 if (csum_offload_supported(priv, action,
73867881 2627 act->csum_flags,
e98bedf5 2628 extack))
73867881 2629 break;
26c02749
OG		 2630
2631 return -EOPNOTSUPP;
73867881
PNA		 2632 case FLOW_ACTION_REDIRECT: {
2633 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2634
2635 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2636 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2637 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 2638 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 2639 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2640 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2641 } else {
e98bedf5
EB		 2642 NL_SET_ERR_MSG_MOD(extack,
2643 "device is not on same HW, can't offload");
5c65c564
OG		 2644 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2645 peer_dev->name);
2646 return -EINVAL;
2647 }
73867881
PNA		 2648 }
2649 break;
2650 case FLOW_ACTION_MARK: {
2651 u32 mark = act->mark;
e3a2b7ed
AV		 2652
2653 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2654 NL_SET_ERR_MSG_MOD(extack,
2655 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2656 return -EINVAL;
2657 }
2658
3bc4b7bf 2659 attr->flow_tag = mark;
1cab1cd7 2660 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2661 }
2662 break;
2663 default:
2cc1cb1d
TZ		 2664 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2665 return -EOPNOTSUPP;
e3a2b7ed 2666 }
e3a2b7ed
AV		 2667 }
2668
c500c86b
PNA		 2669 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2670 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2671 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2672 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2673 if (err)
2674 return err;
27c11b6b
EB		 2675 /* in case all pedit actions are skipped, remove the MOD_HDR
2676 * flag.
2677 */
e7739a60 2678 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2679 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2680 kfree(parse_attr->mod_hdr_actions);
2681 }
c500c86b
PNA		 2682 }
2683
1cab1cd7 2684 attr->action = action;
73867881 2685 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2686 return -EOPNOTSUPP;
2687
e3a2b7ed
AV		 2688 return 0;
2689}
2690
7f1a546e 2691struct encap_key {
1f6da306 2692 const struct ip_tunnel_key *ip_tun_key;
d386939a 2693 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2694};
2695
2696static inline int cmp_encap_info(struct encap_key *a,
2697 struct encap_key *b)
a54e20b4 2698{
7f1a546e 2699 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2700 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2701}
2702
7f1a546e 2703static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2704{
7f1a546e 2705 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2706 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 2707}
2708
a54e20b4 2709
b1d90e6b
RL		 2710static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2711 struct net_device *peer_netdev)
2712{
2713 struct mlx5e_priv *peer_priv;
2714
2715 peer_priv = netdev_priv(peer_netdev);
2716
2717 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2718 mlx5e_eswitch_rep(priv->netdev) &&
2719 mlx5e_eswitch_rep(peer_netdev) &&
2720 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2721}
2722
32f3671f 2723
f5bc2c5d 2724
a54e20b4 2725static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 2726 struct mlx5e_tc_flow *flow,
733d4f36
RD		 2727 struct net_device *mirred_dev,
2728 int out_index,
8c4dc42b 2729 struct netlink_ext_ack *extack,
0ad060ee
RD		 2730 struct net_device **encap_dev,
2731 bool *encap_valid)
a54e20b4
HHZ		 2732{
2733 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 2734 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 2735 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 2736 const struct ip_tunnel_info *tun_info;
7f1a546e 2737 struct encap_key key, e_key;
c1ae1152 2738 struct mlx5e_encap_entry *e;
733d4f36 2739 unsigned short family;
a54e20b4
HHZ		 2740 uintptr_t hash_key;
2741 bool found = false;
54c177ca 2742 int err = 0;
a54e20b4 2743
733d4f36 2744 parse_attr = attr->parse_attr;
1f6da306 2745 tun_info = parse_attr->tun_info[out_index];
733d4f36 2746 family = ip_tunnel_info_af(tun_info);
7f1a546e 2747 key.ip_tun_key = &tun_info->key;
d386939a 2748 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 2749 if (!key.tc_tunnel) {
2750 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
2751 return -EOPNOTSUPP;
2752 }
733d4f36 2753
7f1a546e 2754 hash_key = hash_encap_info(&key);
a54e20b4
HHZ		 2755
2756 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2757 encap_hlist, hash_key) {
1f6da306 2758 e_key.ip_tun_key = &e->tun_info->key;
d386939a 2759 e_key.tc_tunnel = e->tunnel;
7f1a546e 2760 if (!cmp_encap_info(&e_key, &key)) {
a54e20b4
HHZ		 2761 found = true;
2762 break;
2763 }
2764 }
2765
b2812089 2766 /* must verify if encap is valid or not */
45247bf2
OG		 2767 if (found)
2768 goto attach_flow;
a54e20b4
HHZ		 2769
2770 e = kzalloc(sizeof(*e), GFP_KERNEL);
2771 if (!e)
2772 return -ENOMEM;
2773
1f6da306 2774 e->tun_info = tun_info;
101f4de9 2775 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2776 if (err)
2777 goto out_err;
2778
a54e20b4
HHZ		 2779 INIT_LIST_HEAD(&e->flows);
2780
ce99f6b9 2781 if (family == AF_INET)
101f4de9 2782 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2783 else if (family == AF_INET6)
101f4de9 2784 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2785
0ad060ee 2786 if (err)
a54e20b4
HHZ		 2787 goto out_err;
2788
a54e20b4
HHZ		 2789 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2790
45247bf2 2791attach_flow:
8c4dc42b
EB		 2792 list_add(&flow->encaps[out_index].list, &e->flows);
2793 flow->encaps[out_index].index = out_index;
45247bf2 2794 *encap_dev = e->out_dev;
8c4dc42b
EB		 2795 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2796 attr->dests[out_index].encap_id = e->encap_id;
2797 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 2798 *encap_valid = true;
8c4dc42b 2799 } else {
0ad060ee 2800 *encap_valid = false;
8c4dc42b 2801 }
45247bf2 2802
232c0013 2803 return err;
a54e20b4
HHZ		 2804
2805out_err:
2806 kfree(e);
2807 return err;
2808}
2809
1482bd3d 2810static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2811 const struct flow_action_entry *act,
1482bd3d
JL		 2812 struct mlx5_esw_flow_attr *attr,
2813 u32 *action)
2814{
cc495188
JL		 2815 u8 vlan_idx = attr->total_vlan;
2816
2817 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2818 return -EOPNOTSUPP;
2819
73867881
PNA		 2820 switch (act->id) {
2821 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2822 if (vlan_idx) {
2823 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2824 MLX5_FS_VLAN_DEPTH))
2825 return -EOPNOTSUPP;
2826
2827 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2828 } else {
2829 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2830 }
73867881
PNA		 2831 break;
2832 case FLOW_ACTION_VLAN_PUSH:
2833 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2834 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2835 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2836 if (!attr->vlan_proto[vlan_idx])
2837 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2838
2839 if (vlan_idx) {
2840 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2841 MLX5_FS_VLAN_DEPTH))
2842 return -EOPNOTSUPP;
2843
2844 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2845 } else {
2846 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2847 (act->vlan.proto != htons(ETH_P_8021Q) ||
2848 act->vlan.prio))
cc495188
JL		 2849 return -EOPNOTSUPP;
2850
2851 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2852 }
73867881
PNA		 2853 break;
2854 default:
bdc837ee 2855 return -EINVAL;
1482bd3d
JL		 2856 }
2857
cc495188
JL		 2858 attr->total_vlan = vlan_idx + 1;
2859
1482bd3d
JL		 2860 return 0;
2861}
2862
278748a9
EB		 2863static int add_vlan_push_action(struct mlx5e_priv *priv,
2864 struct mlx5_esw_flow_attr *attr,
2865 struct net_device **out_dev,
2866 u32 *action)
2867{
2868 struct net_device *vlan_dev = *out_dev;
2869 struct flow_action_entry vlan_act = {
2870 .id = FLOW_ACTION_VLAN_PUSH,
2871 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
2872 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
2873 .vlan.prio = 0,
2874 };
2875 int err;
2876
2877 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2878 if (err)
2879 return err;
2880
2881 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
2882 dev_get_iflink(vlan_dev));
2883 if (is_vlan_dev(*out_dev))
2884 err = add_vlan_push_action(priv, attr, out_dev, action);
2885
2886 return err;
2887}
2888
35a605db
EB		 2889static int add_vlan_pop_action(struct mlx5e_priv *priv,
2890 struct mlx5_esw_flow_attr *attr,
2891 u32 *action)
2892{
2893 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
2894 struct flow_action_entry vlan_act = {
2895 .id = FLOW_ACTION_VLAN_POP,
2896 };
2897 int err = 0;
2898
2899 while (nest_level--) {
2900 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2901 if (err)
2902 return err;
2903 }
2904
2905 return err;
2906}
2907
f6dc1264
PB		 2908bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
2909 struct net_device *out_dev)
2910{
2911 if (is_merged_eswitch_dev(priv, out_dev))
2912 return true;
2913
2914 return mlx5e_eswitch_rep(out_dev) &&
2915 same_hw_devs(priv, netdev_priv(out_dev));
2916}
2917
73867881
PNA		 2918static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2919 struct flow_action *flow_action,
e98bedf5
EB		 2920 struct mlx5e_tc_flow *flow,
2921 struct netlink_ext_ack *extack)
03a9d11e 2922{
73867881 2923 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2924 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2925 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 2926 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 2927 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2928 const struct ip_tunnel_info *info = NULL;
2929 const struct flow_action_entry *act;
a54e20b4 2930 bool encap = false;
1cab1cd7 2931 u32 action = 0;
244cd96a 2932 int err, i;
03a9d11e 2933
73867881 2934 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2935 return -EINVAL;
2936
73867881
PNA		 2937 flow_action_for_each(i, act, flow_action) {
2938 switch (act->id) {
2939 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2940 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2941 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2942 break;
2943 case FLOW_ACTION_MANGLE:
2944 case FLOW_ACTION_ADD:
2945 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 2946 parse_attr, hdrs, extack);
d7e75a32
OG		 2947 if (err)
2948 return err;
2949
1cab1cd7 2950 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2951 attr->split_count = attr->out_count;
73867881
PNA		 2952 break;
2953 case FLOW_ACTION_CSUM:
1cab1cd7 2954 if (csum_offload_supported(priv, action,
73867881
PNA		 2955 act->csum_flags, extack))
2956 break;
26c02749
OG		 2957
2958 return -EOPNOTSUPP;
73867881
PNA		 2959 case FLOW_ACTION_REDIRECT:
2960 case FLOW_ACTION_MIRRED: {
03a9d11e 2961 struct mlx5e_priv *out_priv;
592d3651 2962 struct net_device *out_dev;
03a9d11e 2963
73867881 2964 out_dev = act->dev;
ef381359
OS		 2965 if (!out_dev) {
2966 /* out_dev is NULL when filters with
2967 * non-existing mirred device are replayed to
2968 * the driver.
2969 */
2970 return -EINVAL;
2971 }
03a9d11e 2972
592d3651 2973 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2974 NL_SET_ERR_MSG_MOD(extack,
2975 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2976 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2977 attr->out_count);
2978 return -EOPNOTSUPP;
2979 }
2980
f493f155
EB		 2981 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2982 MLX5_FLOW_CONTEXT_ACTION_COUNT;
f6dc1264 2983 if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 2984 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2985 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 2986 struct net_device *uplink_upper;
7ba58ba7 2987
fa833bd5
VB		 2988 rcu_read_lock();
2989 uplink_upper =
2990 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 2991 if (uplink_upper &&
2992 netif_is_lag_master(uplink_upper) &&
2993 uplink_upper == out_dev)
2994 out_dev = uplink_dev;
fa833bd5 2995 rcu_read_unlock();
7ba58ba7 2996
278748a9
EB		 2997 if (is_vlan_dev(out_dev)) {
2998 err = add_vlan_push_action(priv, attr,
2999 &out_dev,
3000 &action);
3001 if (err)
3002 return err;
3003 }
f6dc1264 3004
35a605db
EB		 3005 if (is_vlan_dev(parse_attr->filter_dev)) {
3006 err = add_vlan_pop_action(priv, attr,
3007 &action);
3008 if (err)
3009 return err;
3010 }
278748a9 3011
f6dc1264
PB		 3012 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3013 NL_SET_ERR_MSG_MOD(extack,
3014 "devices are not on same switch HW, can't offload forwarding");
3015 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3016 priv->netdev->name, out_dev->name);
a0646c88 3017 return -EOPNOTSUPP;
f6dc1264 3018 }
a0646c88 3019
a54e20b4 3020 out_priv = netdev_priv(out_dev);
1d447a39 3021 rpriv = out_priv->ppriv;
df65a573
EB		 3022 attr->dests[attr->out_count].rep = rpriv->rep;
3023 attr->dests[attr->out_count].mdev = out_priv->mdev;
3024 attr->out_count++;
a54e20b4 3025 } else if (encap) {
8c4dc42b
EB		 3026 parse_attr->mirred_ifindex[attr->out_count] =
3027 out_dev->ifindex;
1f6da306 3028 parse_attr->tun_info[attr->out_count] = info;
8c4dc42b 3029 encap = false;
f493f155
EB		 3030 attr->dests[attr->out_count].flags |=
3031 MLX5_ESW_DEST_ENCAP;
1cc26d74 3032 attr->out_count++;
df65a573
EB		 3033 /* attr->dests[].rep is resolved when we
3034 * handle encap
3035 */
ef381359
OS		 3036 } else if (parse_attr->filter_dev != priv->netdev) {
3037 /* All mlx5 devices are called to configure
3038 * high level device filters. Therefore, the
3039 * *attempt* to install a filter on invalid
3040 * eswitch should not trigger an explicit error
3041 */
3042 return -EINVAL;
a54e20b4 3043 } else {
e98bedf5
EB		 3044 NL_SET_ERR_MSG_MOD(extack,
3045 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 3046 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3047 priv->netdev->name, out_dev->name);
3048 return -EINVAL;
3049 }
73867881
PNA		 3050 }
3051 break;
3052 case FLOW_ACTION_TUNNEL_ENCAP:
3053 info = act->tunnel;
a54e20b4
HHZ		 3054 if (info)
3055 encap = true;
3056 else
3057 return -EOPNOTSUPP;
1482bd3d 3058
73867881
PNA		 3059 break;
3060 case FLOW_ACTION_VLAN_PUSH:
3061 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3062 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3063 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3064 /* Replace vlan pop+push with vlan modify */
3065 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3066 err = add_vlan_rewrite_action(priv,
3067 MLX5_FLOW_NAMESPACE_FDB,
3068 act, parse_attr, hdrs,
3069 &action, extack);
3070 } else {
3071 err = parse_tc_vlan_action(priv, act, attr, &action);
3072 }
1482bd3d
JL		 3073 if (err)
3074 return err;
3075
bdc837ee
EB		 3076 attr->split_count = attr->out_count;
3077 break;
3078 case FLOW_ACTION_VLAN_MANGLE:
3079 err = add_vlan_rewrite_action(priv,
3080 MLX5_FLOW_NAMESPACE_FDB,
3081 act, parse_attr, hdrs,
3082 &action, extack);
3083 if (err)
3084 return err;
3085
e85e02ba 3086 attr->split_count = attr->out_count;
73867881
PNA		 3087 break;
3088 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 3089 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 3090 break;
3091 case FLOW_ACTION_GOTO: {
3092 u32 dest_chain = act->chain_index;
bf07aa73
PB		 3093 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3094
3095 if (dest_chain <= attr->chain) {
3096 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3097 return -EOPNOTSUPP;
3098 }
3099 if (dest_chain > max_chain) {
3100 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3101 return -EOPNOTSUPP;
3102 }
e88afe75 3103 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 3104 attr->dest_chain = dest_chain;
73867881
PNA		 3105 break;
3106 }
3107 default:
2cc1cb1d
TZ		 3108 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3109 return -EOPNOTSUPP;
bf07aa73 3110 }
03a9d11e 3111 }
bdd66ac0 3112
0bac1194
EB		 3113 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3114 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3115 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3116 * tag rewrite.
3117 */
3118 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3119 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3120 &action, extack);
3121 if (err)
3122 return err;
3123 }
3124
c500c86b
PNA		 3125 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3126 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3127 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3128 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3129 if (err)
3130 return err;
27c11b6b
EB		 3131 /* in case all pedit actions are skipped, remove the MOD_HDR
3132 * flag. we might have set split_count either by pedit or
3133 * pop/push. if there is no pop/push either, reset it too.
3134 */
3135 if (parse_attr->num_mod_hdr_actions == 0) {
3136 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3137 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3138 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3139 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3140 attr->split_count = 0;
3141 }
c500c86b
PNA		 3142 }
3143
1cab1cd7 3144 attr->action = action;
73867881 3145 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3146 return -EOPNOTSUPP;
3147
e88afe75
OG		 3148 if (attr->dest_chain) {
3149 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3150 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3151 return -EOPNOTSUPP;
3152 }
3153 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3154 }
3155
e85e02ba 3156 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3157 NL_SET_ERR_MSG_MOD(extack,
3158 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3159 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3160 return -EOPNOTSUPP;
3161 }
3162
31c8eba5 3163 return 0;
03a9d11e
OG		 3164}
3165
226f2ca3 3166static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3167{
226f2ca3 3168 unsigned long __flow_flags = 0;
60bd4af8 3169
226f2ca3
VB		 3170 if (flags & MLX5_TC_FLAG(INGRESS))
3171 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3172 if (flags & MLX5_TC_FLAG(EGRESS))
3173 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3174
226f2ca3
VB		 3175 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3176 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3177 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3178 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
d9ee0491 3179
60bd4af8
OG		 3180 *flow_flags = __flow_flags;
3181}
3182
05866c82
OG		 3183static const struct rhashtable_params tc_ht_params = {
3184 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3185 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3186 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3187 .automatic_shrinking = true,
3188};
3189
226f2ca3
VB		 3190static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3191 unsigned long flags)
05866c82 3192{
655dc3d2
OG		 3193 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3194 struct mlx5e_rep_priv *uplink_rpriv;
3195
226f2ca3 3196 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3197 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3198 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3199 } else /* NIC offload */
655dc3d2 3200 return &priv->fs.tc.ht;
05866c82
OG		 3201}
3202
04de7dda
RD		 3203static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3204{
1418ddd9 3205 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3206 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3207 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3208 bool act_is_encap = !!(attr->action &
3209 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3210 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3211 MLX5_DEVCOM_ESW_OFFLOADS);
3212
10fbb1cd
RD		 3213 if (!esw_paired)
3214 return false;
3215
3216 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3217 mlx5_lag_is_multipath(attr->in_mdev)) &&
3218 (is_rep_ingress || act_is_encap))
3219 return true;
3220
3221 return false;
04de7dda
RD		 3222}
3223
a88780a9
RD		 3224static int
3225mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3226 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3227 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3228 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3229{
17091853 3230 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3231 struct mlx5e_tc_flow *flow;
5a7e5bcb 3232 int out_index, err;
e3a2b7ed 3233
65ba8fb7 3234 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3235 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3236 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3237 err = -ENOMEM;
3238 goto err_free;
3239 }
3240
3241 flow->cookie = f->cookie;
65ba8fb7 3242 flow->flags = flow_flags;
655dc3d2 3243 flow->priv = priv;
5a7e5bcb
VB		 3244 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3245 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3246 INIT_LIST_HEAD(&flow->mod_hdr);
3247 INIT_LIST_HEAD(&flow->hairpin);
3248 refcount_set(&flow->refcnt, 1);
e3a2b7ed 3249
a88780a9
RD		 3250 *__flow = flow;
3251 *__parse_attr = parse_attr;
3252
3253 return 0;
3254
3255err_free:
3256 kfree(flow);
3257 kvfree(parse_attr);
3258 return err;
3259}
3260
988ab9c7
TZ		 3261static void
3262mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3263 struct mlx5e_priv *priv,
3264 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3265 struct flow_cls_offload *f,
988ab9c7
TZ		 3266 struct mlx5_eswitch_rep *in_rep,
3267 struct mlx5_core_dev *in_mdev)
3268{
3269 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3270
3271 esw_attr->parse_attr = parse_attr;
3272 esw_attr->chain = f->common.chain_index;
3273 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
3274
3275 esw_attr->in_rep = in_rep;
3276 esw_attr->in_mdev = in_mdev;
3277
3278 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3279 MLX5_COUNTER_SOURCE_ESWITCH)
3280 esw_attr->counter_dev = in_mdev;
3281 else
3282 esw_attr->counter_dev = priv->mdev;
3283}
3284
71129676 3285static struct mlx5e_tc_flow *
04de7dda 3286__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3287 struct flow_cls_offload *f,
226f2ca3 3288 unsigned long flow_flags,
04de7dda
RD		 3289 struct net_device *filter_dev,
3290 struct mlx5_eswitch_rep *in_rep,
71129676 3291 struct mlx5_core_dev *in_mdev)
a88780a9 3292{
f9e30088 3293 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3294 struct netlink_ext_ack *extack = f->common.extack;
3295 struct mlx5e_tc_flow_parse_attr *parse_attr;
3296 struct mlx5e_tc_flow *flow;
3297 int attr_size, err;
e3a2b7ed 3298
226f2ca3 3299 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3300 attr_size = sizeof(struct mlx5_esw_flow_attr);
3301 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3302 &parse_attr, &flow);
3303 if (err)
3304 goto out;
988ab9c7 3305
d11afc26 3306 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3307 mlx5e_flow_esw_attr_init(flow->esw_attr,
3308 priv, parse_attr,
3309 f, in_rep, in_mdev);
3310
54c177ca
OS		 3311 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3312 f, filter_dev);
d11afc26
OS		 3313 if (err)
3314 goto err_free;
a88780a9 3315
6f9af8ff 3316 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3317 if (err)
3318 goto err_free;
3319
7040632d 3320 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
ef06c9ee
RD		 3321 if (err) {
3322 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3323 goto err_free;
3324
b4a23329 3325 add_unready_flow(flow);
ef06c9ee 3326 }
e3a2b7ed 3327
71129676 3328 return flow;
a88780a9
RD		 3329
3330err_free:
5a7e5bcb 3331 mlx5e_flow_put(priv, flow);
a88780a9 3332out:
71129676 3333 return ERR_PTR(err);
a88780a9
RD		 3334}
3335
f9e30088 3336static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3337 struct mlx5e_tc_flow *flow,
226f2ca3 3338 unsigned long flow_flags)
04de7dda
RD		 3339{
3340 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3341 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3342 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3343 struct mlx5e_tc_flow_parse_attr *parse_attr;
3344 struct mlx5e_rep_priv *peer_urpriv;
3345 struct mlx5e_tc_flow *peer_flow;
3346 struct mlx5_core_dev *in_mdev;
3347 int err = 0;
3348
3349 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3350 if (!peer_esw)
3351 return -ENODEV;
3352
3353 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3354 peer_priv = netdev_priv(peer_urpriv->netdev);
3355
3356 /* in_mdev is assigned of which the packet originated from.
3357 * So packets redirected to uplink use the same mdev of the
3358 * original flow and packets redirected from uplink use the
3359 * peer mdev.
3360 */
b05af6aa 3361 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3362 in_mdev = peer_priv->mdev;
3363 else
3364 in_mdev = priv->mdev;
3365
3366 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3367 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3368 parse_attr->filter_dev,
3369 flow->esw_attr->in_rep, in_mdev);
3370 if (IS_ERR(peer_flow)) {
3371 err = PTR_ERR(peer_flow);
04de7dda 3372 goto out;
71129676 3373 }
04de7dda
RD		 3374
3375 flow->peer_flow = peer_flow;
226f2ca3 3376 flow_flag_set(flow, DUP);
04de7dda
RD		 3377 mutex_lock(&esw->offloads.peer_mutex);
3378 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3379 mutex_unlock(&esw->offloads.peer_mutex);
3380
3381out:
3382 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3383 return err;
3384}
3385
3386static int
3387mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3388 struct flow_cls_offload *f,
226f2ca3 3389 unsigned long flow_flags,
04de7dda
RD		 3390 struct net_device *filter_dev,
3391 struct mlx5e_tc_flow **__flow)
3392{
3393 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3394 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3395 struct mlx5_core_dev *in_mdev = priv->mdev;
3396 struct mlx5e_tc_flow *flow;
3397 int err;
3398
71129676
JG		 3399 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3400 in_mdev);
3401 if (IS_ERR(flow))
3402 return PTR_ERR(flow);
04de7dda
RD		 3403
3404 if (is_peer_flow_needed(flow)) {
95dc1902 3405 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3406 if (err) {
3407 mlx5e_tc_del_fdb_flow(priv, flow);
3408 goto out;
3409 }
3410 }
3411
3412 *__flow = flow;
3413
3414 return 0;
3415
3416out:
3417 return err;
3418}
3419
a88780a9
RD		 3420static int
3421mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3422 struct flow_cls_offload *f,
226f2ca3 3423 unsigned long flow_flags,
d11afc26 3424 struct net_device *filter_dev,
a88780a9
RD		 3425 struct mlx5e_tc_flow **__flow)
3426{
f9e30088 3427 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3428 struct netlink_ext_ack *extack = f->common.extack;
3429 struct mlx5e_tc_flow_parse_attr *parse_attr;
3430 struct mlx5e_tc_flow *flow;
3431 int attr_size, err;
3432
bf07aa73
PB		 3433 /* multi-chain not supported for NIC rules */
3434 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3435 return -EOPNOTSUPP;
3436
226f2ca3 3437 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3438 attr_size = sizeof(struct mlx5_nic_flow_attr);
3439 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3440 &parse_attr, &flow);
3441 if (err)
3442 goto out;
3443
d11afc26 3444 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3445 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3446 f, filter_dev);
d11afc26
OS		 3447 if (err)
3448 goto err_free;
3449
73867881 3450 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3451 if (err)
3452 goto err_free;
3453
3454 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3455 if (err)
3456 goto err_free;
3457
226f2ca3 3458 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3459 kvfree(parse_attr);
3460 *__flow = flow;
3461
3462 return 0;
e3a2b7ed 3463
e3a2b7ed 3464err_free:
5a7e5bcb 3465 mlx5e_flow_put(priv, flow);
17091853 3466 kvfree(parse_attr);
a88780a9
RD		 3467out:
3468 return err;
3469}
3470
3471static int
3472mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3473 struct flow_cls_offload *f,
226f2ca3 3474 unsigned long flags,
d11afc26 3475 struct net_device *filter_dev,
a88780a9
RD		 3476 struct mlx5e_tc_flow **flow)
3477{
3478 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3479 unsigned long flow_flags;
a88780a9
RD		 3480 int err;
3481
3482 get_flags(flags, &flow_flags);
3483
bf07aa73
PB		 3484 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3485 return -EOPNOTSUPP;
3486
f6455de0 3487 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3488 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3489 filter_dev, flow);
a88780a9 3490 else
d11afc26
OS		 3491 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3492 filter_dev, flow);
a88780a9
RD		 3493
3494 return err;
3495}
3496
71d82d2a 3497int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3498 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3499{
3500 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3501 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3502 struct mlx5e_tc_flow *flow;
3503 int err = 0;
3504
c5d326b2
VB		 3505 rcu_read_lock();
3506 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3507 rcu_read_unlock();
a88780a9
RD		 3508 if (flow) {
3509 NL_SET_ERR_MSG_MOD(extack,
3510 "flow cookie already exists, ignoring");
3511 netdev_warn_once(priv->netdev,
3512 "flow cookie %lx already exists, ignoring\n",
3513 f->cookie);
0e1c1a2f 3514 err = -EEXIST;
a88780a9
RD		 3515 goto out;
3516 }
3517
d11afc26 3518 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3519 if (err)
3520 goto out;
3521
c5d326b2 3522 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3523 if (err)
3524 goto err_free;
3525
3526 return 0;
3527
3528err_free:
5a7e5bcb 3529 mlx5e_flow_put(priv, flow);
a88780a9 3530out:
e3a2b7ed
AV		 3531 return err;
3532}
3533
8f8ae895
OG		 3534static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3535{
226f2ca3
VB		 3536 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3537 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 3538
226f2ca3
VB		 3539 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3540 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 3541}
3542
71d82d2a 3543int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3544 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 3545{
d9ee0491 3546 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3547 struct mlx5e_tc_flow *flow;
c5d326b2 3548 int err;
e3a2b7ed 3549
c5d326b2 3550 rcu_read_lock();
05866c82 3551 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 3552 if (!flow || !same_flow_direction(flow, flags)) {
3553 err = -EINVAL;
3554 goto errout;
3555 }
e3a2b7ed 3556
c5d326b2
VB		 3557 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3558 * set.
3559 */
3560 if (flow_flag_test_and_set(flow, DELETED)) {
3561 err = -EINVAL;
3562 goto errout;
3563 }
05866c82 3564 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 3565 rcu_read_unlock();
e3a2b7ed 3566
5a7e5bcb 3567 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 3568
3569 return 0;
c5d326b2
VB		 3570
3571errout:
3572 rcu_read_unlock();
3573 return err;
e3a2b7ed
AV		 3574}
3575
71d82d2a 3576int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3577 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 3578{
04de7dda 3579 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3580 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3581 struct mlx5_eswitch *peer_esw;
aad7e08d 3582 struct mlx5e_tc_flow *flow;
aad7e08d 3583 struct mlx5_fc *counter;
316d5f72
RD		 3584 u64 lastuse = 0;
3585 u64 packets = 0;
3586 u64 bytes = 0;
5a7e5bcb 3587 int err = 0;
aad7e08d 3588
c5d326b2
VB		 3589 rcu_read_lock();
3590 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3591 tc_ht_params));
3592 rcu_read_unlock();
5a7e5bcb
VB		 3593 if (IS_ERR(flow))
3594 return PTR_ERR(flow);
3595
3596 if (!same_flow_direction(flow, flags)) {
3597 err = -EINVAL;
3598 goto errout;
3599 }
aad7e08d 3600
226f2ca3 3601 if (mlx5e_is_offloaded_flow(flow)) {
316d5f72
RD		 3602 counter = mlx5e_tc_get_counter(flow);
3603 if (!counter)
5a7e5bcb 3604 goto errout;
aad7e08d 3605
316d5f72
RD		 3606 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3607 }
aad7e08d 3608
316d5f72
RD		 3609 /* Under multipath it's possible for one rule to be currently
3610 * un-offloaded while the other rule is offloaded.
3611 */
04de7dda
RD		 3612 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3613 if (!peer_esw)
3614 goto out;
3615
226f2ca3
VB		 3616 if (flow_flag_test(flow, DUP) &&
3617 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 3618 u64 bytes2;
3619 u64 packets2;
3620 u64 lastuse2;
3621
3622 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3623 if (!counter)
3624 goto no_peer_counter;
04de7dda
RD		 3625 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3626
3627 bytes += bytes2;
3628 packets += packets2;
3629 lastuse = max_t(u64, lastuse, lastuse2);
3630 }
3631
316d5f72 3632no_peer_counter:
04de7dda 3633 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3634out:
3b1903ef 3635 flow_stats_update(&f->stats, bytes, packets, lastuse);
5a7e5bcb
VB		 3636errout:
3637 mlx5e_flow_put(priv, flow);
3638 return err;
aad7e08d
AV		 3639}
3640
4d8fcf21
AH		 3641static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3642 struct mlx5e_priv *peer_priv)
3643{
3644 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3645 struct mlx5e_hairpin_entry *hpe;
3646 u16 peer_vhca_id;
3647 int bkt;
3648
3649 if (!same_hw_devs(priv, peer_priv))
3650 return;
3651
3652 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3653
3654 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3655 if (hpe->peer_vhca_id == peer_vhca_id)
3656 hpe->hp->pair->peer_gone = true;
3657 }
3658}
3659
3660static int mlx5e_tc_netdev_event(struct notifier_block *this,
3661 unsigned long event, void *ptr)
3662{
3663 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3664 struct mlx5e_flow_steering *fs;
3665 struct mlx5e_priv *peer_priv;
3666 struct mlx5e_tc_table *tc;
3667 struct mlx5e_priv *priv;
3668
3669 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3670 event != NETDEV_UNREGISTER ||
3671 ndev->reg_state == NETREG_REGISTERED)
3672 return NOTIFY_DONE;
3673
3674 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3675 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3676 priv = container_of(fs, struct mlx5e_priv, fs);
3677 peer_priv = netdev_priv(ndev);
3678 if (priv == peer_priv ||
3679 !(priv->netdev->features & NETIF_F_HW_TC))
3680 return NOTIFY_DONE;
3681
3682 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3683
3684 return NOTIFY_DONE;
3685}
3686
655dc3d2 3687int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3688{
acff797c 3689 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3690 int err;
e8f887ac 3691
b6fac0b4 3692 mutex_init(&tc->t_lock);
11c9c548 3693 hash_init(tc->mod_hdr_tbl);
5c65c564 3694 hash_init(tc->hairpin_tbl);
11c9c548 3695
4d8fcf21
AH		 3696 err = rhashtable_init(&tc->ht, &tc_ht_params);
3697 if (err)
3698 return err;
3699
3700 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3701 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3702 tc->netdevice_nb.notifier_call = NULL;
3703 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3704 }
3705
3706 return err;
e8f887ac
AV		 3707}
3708
3709static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3710{
3711 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3712 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3713
961e8979 3714 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3715 kfree(flow);
3716}
3717
655dc3d2 3718void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3719{
acff797c 3720 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3721
4d8fcf21
AH		 3722 if (tc->netdevice_nb.notifier_call)
3723 unregister_netdevice_notifier(&tc->netdevice_nb);
3724
d9ee0491 3725 rhashtable_destroy(&tc->ht);
e8f887ac 3726
acff797c
MG		 3727 if (!IS_ERR_OR_NULL(tc->t)) {
3728 mlx5_destroy_flow_table(tc->t);
3729 tc->t = NULL;
e8f887ac 3730 }
b6fac0b4 3731 mutex_destroy(&tc->t_lock);
e8f887ac 3732}
655dc3d2
OG		 3733
3734int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3735{
3736 return rhashtable_init(tc_ht, &tc_ht_params);
3737}
3738
3739void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3740{
3741 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3742}
01252a27 3743
226f2ca3 3744int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 3745{
d9ee0491 3746 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3747
3748 return atomic_read(&tc_ht->nelems);
3749}
04de7dda
RD		 3750
3751void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3752{
3753 struct mlx5e_tc_flow *flow, *tmp;
3754
3755 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3756 __mlx5e_tc_del_fdb_peer_flow(flow);
3757}
b4a23329
RD		 3758
3759void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
3760{
3761 struct mlx5_rep_uplink_priv *rpriv =
3762 container_of(work, struct mlx5_rep_uplink_priv,
3763 reoffload_flows_work);
3764 struct mlx5e_tc_flow *flow, *tmp;
3765
ad86755b 3766 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 3767 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
3768 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 3769 unready_flow_del(flow);
b4a23329 3770 }
ad86755b 3771 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 3772}
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