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net/mlx5e: Enable adding peer miss rules only if merged eswitch is supported
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
49964352 60#include "esw/chains.h"
3f6d08d1 61#include "fs_core.h"
2c81bfd5 62#include "en/port.h"
101f4de9 63#include "en/tc_tun.h"
0a7fcb78 64#include "en/mapping.h"
4c3844d9 65#include "en/tc_ct.h"
b2fdf3d0 66#include "en/mod_hdr.h"
04de7dda 67#include "lib/devcom.h"
9272e3df 68#include "lib/geneve.h"
7a978759 69#include "diag/en_tc_tracepoint.h"
e8f887ac 70
d65dbedf 71#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
0a7fcb78 72
3bc4b7bf
OG		 73struct mlx5_nic_flow_attr {
74 u32 action;
75 u32 flow_tag;
2b688ea5 76 struct mlx5_modify_hdr *modify_hdr;
5c65c564 77 u32 hairpin_tirn;
38aa51c1 78 u8 match_level;
3f6d08d1 79 struct mlx5_flow_table *hairpin_ft;
b8aee822 80 struct mlx5_fc *counter;
3bc4b7bf
OG		 81};
82
226f2ca3 83#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 84
65ba8fb7 85enum {
226f2ca3
VB		 86 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
87 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
88 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 89 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 90 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
91 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
92 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
93 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
94 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
95 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
96 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 97 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 98 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
14e6b038 99 MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8,
65ba8fb7
OG		 100};
101
e4ad91f2
CM		 102#define MLX5E_TC_MAX_SPLITS 1
103
79baaec7
EB		 104/* Helper struct for accessing a struct containing list_head array.
105 * Containing struct
106 * |- Helper array
107 * [0] Helper item 0
108 * |- list_head item 0
109 * |- index (0)
110 * [1] Helper item 1
111 * |- list_head item 1
112 * |- index (1)
113 * To access the containing struct from one of the list_head items:
114 * 1. Get the helper item from the list_head item using
115 * helper item =
116 * container_of(list_head item, helper struct type, list_head field)
117 * 2. Get the contining struct from the helper item and its index in the array:
118 * containing struct =
119 * container_of(helper item, containing struct type, helper field[index])
120 */
121struct encap_flow_item {
948993f2 122 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 123 struct list_head list;
124 int index;
125};
126
e8f887ac
AV		 127struct mlx5e_tc_flow {
128 struct rhash_head node;
655dc3d2 129 struct mlx5e_priv *priv;
e8f887ac 130 u64 cookie;
226f2ca3 131 unsigned long flags;
e4ad91f2 132 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
14e6b038
EC		 133
134 /* flows sharing the same reformat object - currently mpls decap */
135 struct list_head l3_to_l2_reformat;
136 struct mlx5e_decap_entry *decap_reformat;
137
79baaec7
EB		 138 /* Flow can be associated with multiple encap IDs.
139 * The number of encaps is bounded by the number of supported
140 * destinations.
141 */
142 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 143 struct mlx5e_tc_flow *peer_flow;
b2fdf3d0 144 struct mlx5e_mod_hdr_handle *mh; /* attached mod header instance */
e4f9abbd 145 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 146 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 147 struct list_head peer; /* flows with peer flow */
b4a23329 148 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
553f9328 149 struct net_device *orig_dev; /* netdev adding flow first */
2a1f1768 150 int tmp_efi_index;
6a06c2f7 151 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 152 refcount_t refcnt;
c5d326b2 153 struct rcu_head rcu_head;
95435ad7 154 struct completion init_done;
0a7fcb78
PB		 155 int tunnel_id; /* the mapped tunnel id of this flow */
156
3bc4b7bf
OG		 157 union {
158 struct mlx5_esw_flow_attr esw_attr[0];
159 struct mlx5_nic_flow_attr nic_attr[0];
160 };
e8f887ac
AV		 161};
162
17091853 163struct mlx5e_tc_flow_parse_attr {
1f6da306 164 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 165 struct net_device *filter_dev;
17091853 166 struct mlx5_flow_spec spec;
6ae4a6a5 167 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 168 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
14e6b038 169 struct ethhdr eth;
17091853
OG		 170};
171
acff797c 172#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 173#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 174
8f1e0b97
PB		 175struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
176 [CHAIN_TO_REG] = {
177 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
178 .moffset = 0,
179 .mlen = 2,
180 },
0a7fcb78
PB		 181 [TUNNEL_TO_REG] = {
182 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521
PB		 183 .moffset = 1,
184 .mlen = 3,
0a7fcb78
PB		 185 .soffset = MLX5_BYTE_OFF(fte_match_param,
186 misc_parameters_2.metadata_reg_c_1),
187 },
4c3844d9 188 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 189 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 190 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
191 [MARK_TO_REG] = mark_to_reg_ct,
192 [LABELS_TO_REG] = labels_to_reg_ct,
193 [FTEID_TO_REG] = fteid_to_reg_ct,
8f1e0b97
PB		 194};
195
0a7fcb78
PB		 196static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
197
198void
199mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
200 enum mlx5e_tc_attr_to_reg type,
201 u32 data,
202 u32 mask)
203{
204 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
205 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
206 void *headers_c = spec->match_criteria;
207 void *headers_v = spec->match_value;
208 void *fmask, *fval;
209
210 fmask = headers_c + soffset;
211 fval = headers_v + soffset;
212
58ff18e1
SM		 213 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
214 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 215
216 memcpy(fmask, &mask, match_len);
217 memcpy(fval, &data, match_len);
218
219 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
220}
221
7e36feeb
PB		 222void
223mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
224 enum mlx5e_tc_attr_to_reg type,
225 u32 *data,
226 u32 *mask)
227{
228 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
229 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
230 void *headers_c = spec->match_criteria;
231 void *headers_v = spec->match_value;
232 void *fmask, *fval;
233
234 fmask = headers_c + soffset;
235 fval = headers_v + soffset;
236
237 memcpy(mask, fmask, match_len);
238 memcpy(data, fval, match_len);
239
240 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
241 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
242}
243
0a7fcb78
PB		 244int
245mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
246 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
247 enum mlx5e_tc_attr_to_reg type,
248 u32 data)
249{
250 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
251 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
252 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
253 char *modact;
254 int err;
255
256 err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB,
257 mod_hdr_acts);
258 if (err)
259 return err;
260
261 modact = mod_hdr_acts->actions +
262 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
263
264 /* Firmware has 5bit length field and 0 means 32bits */
265 if (mlen == 4)
266 mlen = 0;
267
268 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
269 MLX5_SET(set_action_in, modact, field, mfield);
270 MLX5_SET(set_action_in, modact, offset, moffset * 8);
271 MLX5_SET(set_action_in, modact, length, mlen * 8);
272 MLX5_SET(set_action_in, modact, data, data);
273 mod_hdr_acts->num_actions++;
274
275 return 0;
276}
277
77ab67b7
OG		 278struct mlx5e_hairpin {
279 struct mlx5_hairpin *pair;
280
281 struct mlx5_core_dev *func_mdev;
3f6d08d1 282 struct mlx5e_priv *func_priv;
77ab67b7
OG		 283 u32 tdn;
284 u32 tirn;
3f6d08d1
OG		 285
286 int num_channels;
287 struct mlx5e_rqt indir_rqt;
288 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
289 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 290};
291
5c65c564
OG		 292struct mlx5e_hairpin_entry {
293 /* a node of a hash table which keeps all the hairpin entries */
294 struct hlist_node hairpin_hlist;
295
73edca73
VB		 296 /* protects flows list */
297 spinlock_t flows_lock;
5c65c564
OG		 298 /* flows sharing the same hairpin */
299 struct list_head flows;
db76ca24
VB		 300 /* hpe's that were not fully initialized when dead peer update event
301 * function traversed them.
302 */
303 struct list_head dead_peer_wait_list;
5c65c564 304
d8822868 305 u16 peer_vhca_id;
106be53b 306 u8 prio;
5c65c564 307 struct mlx5e_hairpin *hp;
e4f9abbd 308 refcount_t refcnt;
db76ca24 309 struct completion res_ready;
5c65c564
OG		 310};
311
5a7e5bcb
VB		 312static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
313 struct mlx5e_tc_flow *flow);
314
315static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
316{
317 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
318 return ERR_PTR(-EINVAL);
319 return flow;
320}
321
322static void mlx5e_flow_put(struct mlx5e_priv *priv,
323 struct mlx5e_tc_flow *flow)
324{
325 if (refcount_dec_and_test(&flow->refcnt)) {
326 mlx5e_tc_del_flow(priv, flow);
c5d326b2 327 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 328 }
329}
330
226f2ca3
VB		 331static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
332{
333 /* Complete all memory stores before setting bit. */
334 smp_mb__before_atomic();
335 set_bit(flag, &flow->flags);
336}
337
338#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
339
c5d326b2
VB		 340static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
341 unsigned long flag)
342{
343 /* test_and_set_bit() provides all necessary barriers */
344 return test_and_set_bit(flag, &flow->flags);
345}
346
347#define flow_flag_test_and_set(flow, flag) \
348 __flow_flag_test_and_set(flow, \
349 MLX5E_TC_FLOW_FLAG_##flag)
350
226f2ca3
VB		 351static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
352{
353 /* Complete all memory stores before clearing bit. */
354 smp_mb__before_atomic();
355 clear_bit(flag, &flow->flags);
356}
357
358#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
359 MLX5E_TC_FLOW_FLAG_##flag)
360
361static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
362{
363 bool ret = test_bit(flag, &flow->flags);
364
365 /* Read fields of flow structure only after checking flags. */
366 smp_mb__after_atomic();
367 return ret;
368}
369
370#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
371 MLX5E_TC_FLOW_FLAG_##flag)
372
373static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
374{
375 return flow_flag_test(flow, ESWITCH);
376}
377
84179981
PB		 378static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
379{
380 return flow_flag_test(flow, FT);
381}
382
226f2ca3
VB		 383static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
384{
385 return flow_flag_test(flow, OFFLOADED);
386}
387
b2fdf3d0 388static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 389{
b2fdf3d0
PB		 390 return mlx5e_is_eswitch_flow(flow) ?
391 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 392}
393
dd58edc3 394static struct mod_hdr_tbl *
b2fdf3d0 395get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 396{
397 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
398
b2fdf3d0
PB		 399 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
400 &esw->offloads.mod_hdr :
dd58edc3
VB		 401 &priv->fs.tc.mod_hdr;
402}
403
11c9c548
OG		 404static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
405 struct mlx5e_tc_flow *flow,
406 struct mlx5e_tc_flow_parse_attr *parse_attr)
407{
b2fdf3d0
PB		 408 struct mlx5_modify_hdr *modify_hdr;
409 struct mlx5e_mod_hdr_handle *mh;
11c9c548 410
b2fdf3d0
PB		 411 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
412 get_flow_name_space(flow),
413 &parse_attr->mod_hdr_acts);
414 if (IS_ERR(mh))
415 return PTR_ERR(mh);
11c9c548 416
b2fdf3d0 417 modify_hdr = mlx5e_mod_hdr_get(mh);
d2faae25 418 if (mlx5e_is_eswitch_flow(flow))
b2fdf3d0 419 flow->esw_attr->modify_hdr = modify_hdr;
11c9c548 420 else
b2fdf3d0
PB		 421 flow->nic_attr->modify_hdr = modify_hdr;
422 flow->mh = mh;
11c9c548
OG		 423
424 return 0;
11c9c548
OG		 425}
426
427static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
428 struct mlx5e_tc_flow *flow)
429{
5a7e5bcb 430 /* flow wasn't fully initialized */
dd58edc3 431 if (!flow->mh)
5a7e5bcb
VB		 432 return;
433
b2fdf3d0
PB		 434 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
435 flow->mh);
dd58edc3 436 flow->mh = NULL;
11c9c548
OG		 437}
438
77ab67b7
OG		 439static
440struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
441{
442 struct net_device *netdev;
443 struct mlx5e_priv *priv;
444
445 netdev = __dev_get_by_index(net, ifindex);
446 priv = netdev_priv(netdev);
447 return priv->mdev;
448}
449
450static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
451{
e0b4b472 452 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 453 void *tirc;
454 int err;
455
456 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
457 if (err)
458 goto alloc_tdn_err;
459
460 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
461
462 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 463 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 464 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
465
e0b4b472 466 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 467 if (err)
468 goto create_tir_err;
469
470 return 0;
471
472create_tir_err:
473 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
474alloc_tdn_err:
475 return err;
476}
477
478static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
479{
480 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
481 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
482}
483
3f6d08d1
OG		 484static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
485{
486 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
487 struct mlx5e_priv *priv = hp->func_priv;
488 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
489
490 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
491 hp->num_channels);
492
493 for (i = 0; i < sz; i++) {
494 ix = i;
bbeb53b8 495 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 496 ix = mlx5e_bits_invert(i, ilog2(sz));
497 ix = indirection_rqt[ix];
498 rqn = hp->pair->rqn[ix];
499 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
500 }
501}
502
503static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
504{
505 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
506 struct mlx5e_priv *priv = hp->func_priv;
507 struct mlx5_core_dev *mdev = priv->mdev;
508 void *rqtc;
509 u32 *in;
510
511 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
512 in = kvzalloc(inlen, GFP_KERNEL);
513 if (!in)
514 return -ENOMEM;
515
516 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
517
518 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
519 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
520
521 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
522
523 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
524 if (!err)
525 hp->indir_rqt.enabled = true;
526
527 kvfree(in);
528 return err;
529}
530
531static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
532{
533 struct mlx5e_priv *priv = hp->func_priv;
534 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
535 int tt, i, err;
536 void *tirc;
537
538 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 539 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
540
3f6d08d1
OG		 541 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
542 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
543
544 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
545 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
546 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 547 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
548
3f6d08d1 549 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 550 &hp->indir_tirn[tt]);
3f6d08d1
OG		 551 if (err) {
552 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
553 goto err_destroy_tirs;
554 }
555 }
556 return 0;
557
558err_destroy_tirs:
559 for (i = 0; i < tt; i++)
560 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
561 return err;
562}
563
564static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
565{
566 int tt;
567
568 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
569 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
570}
571
572static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
573 struct ttc_params *ttc_params)
574{
575 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
576 int tt;
577
578 memset(ttc_params, 0, sizeof(*ttc_params));
579
580 ttc_params->any_tt_tirn = hp->tirn;
581
582 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
583 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
584
6412bb39 585 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 586 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
587 ft_attr->prio = MLX5E_TC_PRIO;
588}
589
590static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
591{
592 struct mlx5e_priv *priv = hp->func_priv;
593 struct ttc_params ttc_params;
594 int err;
595
596 err = mlx5e_hairpin_create_indirect_rqt(hp);
597 if (err)
598 return err;
599
600 err = mlx5e_hairpin_create_indirect_tirs(hp);
601 if (err)
602 goto err_create_indirect_tirs;
603
604 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
605 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
606 if (err)
607 goto err_create_ttc_table;
608
609 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
610 hp->num_channels, hp->ttc.ft.t->id);
611
612 return 0;
613
614err_create_ttc_table:
615 mlx5e_hairpin_destroy_indirect_tirs(hp);
616err_create_indirect_tirs:
617 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
618
619 return err;
620}
621
622static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
623{
624 struct mlx5e_priv *priv = hp->func_priv;
625
626 mlx5e_destroy_ttc_table(priv, &hp->ttc);
627 mlx5e_hairpin_destroy_indirect_tirs(hp);
628 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
629}
630
77ab67b7
OG		 631static struct mlx5e_hairpin *
632mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
633 int peer_ifindex)
634{
635 struct mlx5_core_dev *func_mdev, *peer_mdev;
636 struct mlx5e_hairpin *hp;
637 struct mlx5_hairpin *pair;
638 int err;
639
640 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
641 if (!hp)
642 return ERR_PTR(-ENOMEM);
643
644 func_mdev = priv->mdev;
645 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
646
647 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
648 if (IS_ERR(pair)) {
649 err = PTR_ERR(pair);
650 goto create_pair_err;
651 }
652 hp->pair = pair;
653 hp->func_mdev = func_mdev;
3f6d08d1
OG		 654 hp->func_priv = priv;
655 hp->num_channels = params->num_channels;
77ab67b7
OG		 656
657 err = mlx5e_hairpin_create_transport(hp);
658 if (err)
659 goto create_transport_err;
660
3f6d08d1
OG		 661 if (hp->num_channels > 1) {
662 err = mlx5e_hairpin_rss_init(hp);
663 if (err)
664 goto rss_init_err;
665 }
666
77ab67b7
OG		 667 return hp;
668
3f6d08d1
OG		 669rss_init_err:
670 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 671create_transport_err:
672 mlx5_core_hairpin_destroy(hp->pair);
673create_pair_err:
674 kfree(hp);
675 return ERR_PTR(err);
676}
677
678static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
679{
3f6d08d1
OG		 680 if (hp->num_channels > 1)
681 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 682 mlx5e_hairpin_destroy_transport(hp);
683 mlx5_core_hairpin_destroy(hp->pair);
684 kvfree(hp);
685}
686
106be53b
OG		 687static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
688{
689 return (peer_vhca_id << 16 | prio);
690}
691
5c65c564 692static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 693 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 694{
695 struct mlx5e_hairpin_entry *hpe;
106be53b 696 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 697
698 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 699 hairpin_hlist, hash_key) {
e4f9abbd
VB		 700 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
701 refcount_inc(&hpe->refcnt);
5c65c564 702 return hpe;
e4f9abbd 703 }
5c65c564
OG		 704 }
705
706 return NULL;
707}
708
e4f9abbd
VB		 709static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
710 struct mlx5e_hairpin_entry *hpe)
711{
712 /* no more hairpin flows for us, release the hairpin pair */
b32accda 713 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 714 return;
b32accda
VB		 715 hash_del(&hpe->hairpin_hlist);
716 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 717
db76ca24
VB		 718 if (!IS_ERR_OR_NULL(hpe->hp)) {
719 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
720 dev_name(hpe->hp->pair->peer_mdev->device));
721
722 mlx5e_hairpin_destroy(hpe->hp);
723 }
e4f9abbd
VB		 724
725 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 726 kfree(hpe);
727}
728
106be53b
OG		 729#define UNKNOWN_MATCH_PRIO 8
730
731static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 732 struct mlx5_flow_spec *spec, u8 *match_prio,
733 struct netlink_ext_ack *extack)
106be53b
OG		 734{
735 void *headers_c, *headers_v;
736 u8 prio_val, prio_mask = 0;
737 bool vlan_present;
738
739#ifdef CONFIG_MLX5_CORE_EN_DCB
740 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 741 NL_SET_ERR_MSG_MOD(extack,
742 "only PCP trust state supported for hairpin");
106be53b
OG		 743 return -EOPNOTSUPP;
744 }
745#endif
746 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
747 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
748
749 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
750 if (vlan_present) {
751 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
752 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
753 }
754
755 if (!vlan_present || !prio_mask) {
756 prio_val = UNKNOWN_MATCH_PRIO;
757 } else if (prio_mask != 0x7) {
e98bedf5
EB		 758 NL_SET_ERR_MSG_MOD(extack,
759 "masked priority match not supported for hairpin");
106be53b
OG		 760 return -EOPNOTSUPP;
761 }
762
763 *match_prio = prio_val;
764 return 0;
765}
766
5c65c564
OG		 767static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
768 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 769 struct mlx5e_tc_flow_parse_attr *parse_attr,
770 struct netlink_ext_ack *extack)
5c65c564 771{
98b66cb1 772 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 773 struct mlx5_hairpin_params params;
d8822868 774 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 775 struct mlx5e_hairpin_entry *hpe;
776 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 777 u64 link_speed64;
778 u32 link_speed;
106be53b 779 u8 match_prio;
d8822868 780 u16 peer_id;
5c65c564
OG		 781 int err;
782
d8822868
OG		 783 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
784 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 785 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 786 return -EOPNOTSUPP;
787 }
788
d8822868 789 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 790 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
791 extack);
106be53b
OG		 792 if (err)
793 return err;
b32accda
VB		 794
795 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 796 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 797 if (hpe) {
798 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
799 wait_for_completion(&hpe->res_ready);
800
801 if (IS_ERR(hpe->hp)) {
802 err = -EREMOTEIO;
803 goto out_err;
804 }
5c65c564 805 goto attach_flow;
db76ca24 806 }
5c65c564
OG		 807
808 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 809 if (!hpe) {
db76ca24
VB		 810 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
811 return -ENOMEM;
b32accda 812 }
5c65c564 813
73edca73 814 spin_lock_init(&hpe->flows_lock);
5c65c564 815 INIT_LIST_HEAD(&hpe->flows);
db76ca24 816 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 817 hpe->peer_vhca_id = peer_id;
106be53b 818 hpe->prio = match_prio;
e4f9abbd 819 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 820 init_completion(&hpe->res_ready);
821
822 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
823 hash_hairpin_info(peer_id, match_prio));
824 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 825
826 params.log_data_size = 15;
827 params.log_data_size = min_t(u8, params.log_data_size,
828 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
829 params.log_data_size = max_t(u8, params.log_data_size,
830 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 831
eb9180f7
OG		 832 params.log_num_packets = params.log_data_size -
833 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
834 params.log_num_packets = min_t(u8, params.log_num_packets,
835 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
836
837 params.q_counter = priv->q_counter;
3f6d08d1 838 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 839 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 840 link_speed = max_t(u32, link_speed, 50000);
841 link_speed64 = link_speed;
842 do_div(link_speed64, 50000);
843 params.num_channels = link_speed64;
844
5c65c564 845 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 846 hpe->hp = hp;
847 complete_all(&hpe->res_ready);
5c65c564
OG		 848 if (IS_ERR(hp)) {
849 err = PTR_ERR(hp);
db76ca24 850 goto out_err;
5c65c564
OG		 851 }
852
eb9180f7 853 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 854 hp->tirn, hp->pair->rqn[0],
855 dev_name(hp->pair->peer_mdev->device),
eb9180f7 856 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 857
5c65c564 858attach_flow:
3f6d08d1 859 if (hpe->hp->num_channels > 1) {
226f2ca3 860 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 861 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
862 } else {
863 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
864 }
b32accda 865
e4f9abbd 866 flow->hpe = hpe;
73edca73 867 spin_lock(&hpe->flows_lock);
5c65c564 868 list_add(&flow->hairpin, &hpe->flows);
73edca73 869 spin_unlock(&hpe->flows_lock);
3f6d08d1 870
5c65c564
OG		 871 return 0;
872
db76ca24
VB		 873out_err:
874 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 875 return err;
876}
877
878static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
879 struct mlx5e_tc_flow *flow)
880{
5a7e5bcb 881 /* flow wasn't fully initialized */
e4f9abbd 882 if (!flow->hpe)
5a7e5bcb
VB		 883 return;
884
73edca73 885 spin_lock(&flow->hpe->flows_lock);
5c65c564 886 list_del(&flow->hairpin);
73edca73
VB		 887 spin_unlock(&flow->hpe->flows_lock);
888
e4f9abbd
VB		 889 mlx5e_hairpin_put(priv, flow->hpe);
890 flow->hpe = NULL;
5c65c564
OG		 891}
892
c83954ab 893static int
74491de9 894mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 895 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 896 struct mlx5e_tc_flow *flow,
897 struct netlink_ext_ack *extack)
e8f887ac 898{
bb0ee7dc 899 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 900 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 901 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 902 struct mlx5_flow_destination dest[2] = {};
66958ed9 903 struct mlx5_flow_act flow_act = {
3bc4b7bf 904 .action = attr->action,
bb0ee7dc 905 .flags = FLOW_ACT_NO_APPEND,
66958ed9 906 };
aad7e08d 907 struct mlx5_fc *counter = NULL;
5c65c564 908 int err, dest_ix = 0;
e8f887ac 909
bb0ee7dc
JL		 910 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
911 flow_context->flow_tag = attr->flow_tag;
912
226f2ca3 913 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 914 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 915 if (err)
916 return err;
917
226f2ca3 918 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 919 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
920 dest[dest_ix].ft = attr->hairpin_ft;
921 } else {
5c65c564
OG		 922 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
923 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 924 }
925 dest_ix++;
3f6d08d1
OG		 926 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
927 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
928 dest[dest_ix].ft = priv->fs.vlan.ft.t;
929 dest_ix++;
5c65c564 930 }
aad7e08d 931
5c65c564
OG		 932 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
933 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 934 if (IS_ERR(counter))
935 return PTR_ERR(counter);
936
5c65c564 937 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 938 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 939 dest_ix++;
b8aee822 940 attr->counter = counter;
aad7e08d
AV		 941 }
942
2f4fe4ca 943 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 944 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 945 flow_act.modify_hdr = attr->modify_hdr;
6ae4a6a5 946 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 947 if (err)
5a7e5bcb 948 return err;
2f4fe4ca
OG		 949 }
950
b6fac0b4 951 mutex_lock(&priv->fs.tc.t_lock);
acff797c 952 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
61dc7b01
PB		 953 struct mlx5_flow_table_attr ft_attr = {};
954 int tc_grp_size, tc_tbl_size, tc_num_grps;
21b9c144
OG		 955 u32 max_flow_counter;
956
957 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
958 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
959
960 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
961
962 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
963 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
61dc7b01 964 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
21b9c144 965
61dc7b01
PB		 966 ft_attr.prio = MLX5E_TC_PRIO;
967 ft_attr.max_fte = tc_tbl_size;
968 ft_attr.level = MLX5E_TC_FT_LEVEL;
969 ft_attr.autogroup.max_num_groups = tc_num_grps;
acff797c
MG		 970 priv->fs.tc.t =
971 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
61dc7b01 972 &ft_attr);
acff797c 973 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 974 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5 975 NL_SET_ERR_MSG_MOD(extack,
c75a33c8 976 "Failed to create tc offload table");
e8f887ac
AV		 977 netdev_err(priv->netdev,
978 "Failed to create tc offload table\n");
5a7e5bcb 979 return PTR_ERR(priv->fs.tc.t);
e8f887ac 980 }
e8f887ac
AV		 981 }
982
38aa51c1 983 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 984 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 985
c83954ab
RL		 986 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
987 &flow_act, dest, dest_ix);
b6fac0b4 988 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 989
a2b7189b 990 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 991}
992
d85cdccb
OG		 993static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
994 struct mlx5e_tc_flow *flow)
995{
513f8f7f 996 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 997 struct mlx5_fc *counter = NULL;
998
b8aee822 999 counter = attr->counter;
5a7e5bcb
VB		 1000 if (!IS_ERR_OR_NULL(flow->rule[0]))
1001 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1002 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1003
b6fac0b4 1004 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1005 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1006 mlx5_destroy_flow_table(priv->fs.tc.t);
1007 priv->fs.tc.t = NULL;
1008 }
b6fac0b4 1009 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1010
513f8f7f 1011 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1012 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1013
226f2ca3 1014 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1015 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1016}
1017
aa0cbbae 1018static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1019 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1020
3c37745e 1021static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1022 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1023 struct net_device *mirred_dev,
1024 int out_index,
8c4dc42b 1025 struct netlink_ext_ack *extack,
0ad060ee
RD		 1026 struct net_device **encap_dev,
1027 bool *encap_valid);
14e6b038
EC		 1028static int mlx5e_attach_decap(struct mlx5e_priv *priv,
1029 struct mlx5e_tc_flow *flow,
1030 struct netlink_ext_ack *extack);
1031static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1032 struct mlx5e_tc_flow *flow);
3c37745e 1033
6d2a3ed0
OG		 1034static struct mlx5_flow_handle *
1035mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1036 struct mlx5e_tc_flow *flow,
1037 struct mlx5_flow_spec *spec,
1038 struct mlx5_esw_flow_attr *attr)
1039{
1ef3018f 1040 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1041 struct mlx5_flow_handle *rule;
4c3844d9 1042
1ef3018f
PB		 1043 if (flow_flag_test(flow, CT)) {
1044 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1045
1046 return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr,
1047 mod_hdr_acts);
1048 }
6d2a3ed0
OG		 1049
1050 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1051 if (IS_ERR(rule))
1052 return rule;
1053
e85e02ba 1054 if (attr->split_count) {
6d2a3ed0
OG		 1055 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1056 if (IS_ERR(flow->rule[1])) {
1057 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1058 return flow->rule[1];
1059 }
1060 }
1061
6d2a3ed0
OG		 1062 return rule;
1063}
1064
1065static void
1066mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1067 struct mlx5e_tc_flow *flow,
4c3844d9 1068 struct mlx5_esw_flow_attr *attr)
6d2a3ed0 1069{
226f2ca3 1070 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1071
4c3844d9
PB		 1072 if (flow_flag_test(flow, CT)) {
1073 mlx5_tc_ct_delete_flow(flow->priv, flow, attr);
1074 return;
1075 }
1076
e85e02ba 1077 if (attr->split_count)
6d2a3ed0
OG		 1078 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1079
1080 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1081}
1082
5dbe906f
PB		 1083static struct mlx5_flow_handle *
1084mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1085 struct mlx5e_tc_flow *flow,
178f69b4 1086 struct mlx5_flow_spec *spec)
5dbe906f 1087{
178f69b4 1088 struct mlx5_esw_flow_attr slow_attr;
5dbe906f
PB		 1089 struct mlx5_flow_handle *rule;
1090
178f69b4
EC		 1091 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1092 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1093 slow_attr.split_count = 0;
1094 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f 1095
178f69b4 1096 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
5dbe906f 1097 if (!IS_ERR(rule))
226f2ca3 1098 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1099
1100 return rule;
1101}
1102
1103static void
1104mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1105 struct mlx5e_tc_flow *flow)
5dbe906f 1106{
178f69b4
EC		 1107 struct mlx5_esw_flow_attr slow_attr;
1108
1109 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1110 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1111 slow_attr.split_count = 0;
1112 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1113 mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
226f2ca3 1114 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1115}
1116
ad86755b
VB		 1117/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1118 * function.
1119 */
1120static void unready_flow_add(struct mlx5e_tc_flow *flow,
1121 struct list_head *unready_flows)
1122{
1123 flow_flag_set(flow, NOT_READY);
1124 list_add_tail(&flow->unready, unready_flows);
1125}
1126
1127/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1128 * function.
1129 */
1130static void unready_flow_del(struct mlx5e_tc_flow *flow)
1131{
1132 list_del(&flow->unready);
1133 flow_flag_clear(flow, NOT_READY);
1134}
1135
b4a23329
RD		 1136static void add_unready_flow(struct mlx5e_tc_flow *flow)
1137{
1138 struct mlx5_rep_uplink_priv *uplink_priv;
1139 struct mlx5e_rep_priv *rpriv;
1140 struct mlx5_eswitch *esw;
1141
1142 esw = flow->priv->mdev->priv.eswitch;
1143 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1144 uplink_priv = &rpriv->uplink_priv;
1145
ad86755b
VB		 1146 mutex_lock(&uplink_priv->unready_flows_lock);
1147 unready_flow_add(flow, &uplink_priv->unready_flows);
1148 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1149}
1150
1151static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1152{
ad86755b
VB		 1153 struct mlx5_rep_uplink_priv *uplink_priv;
1154 struct mlx5e_rep_priv *rpriv;
1155 struct mlx5_eswitch *esw;
1156
1157 esw = flow->priv->mdev->priv.eswitch;
1158 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1159 uplink_priv = &rpriv->uplink_priv;
1160
1161 mutex_lock(&uplink_priv->unready_flows_lock);
1162 unready_flow_del(flow);
1163 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1164}
1165
c83954ab 1166static int
74491de9 1167mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1168 struct mlx5e_tc_flow *flow,
1169 struct netlink_ext_ack *extack)
adb4c123
OG		 1170{
1171 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 1172 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1173 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3c37745e 1174 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1175 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1176 struct mlx5e_rep_priv *rpriv;
1177 struct mlx5e_priv *out_priv;
0ad060ee 1178 bool encap_valid = true;
39ac237c 1179 u32 max_prio, max_chain;
0ad060ee 1180 int err = 0;
f493f155 1181 int out_index;
8b32580d 1182
39ac237c 1183 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
61644c3d
RD		 1184 NL_SET_ERR_MSG_MOD(extack,
1185 "E-switch priorities unsupported, upgrade FW");
d14f6f2a
OG		 1186 return -EOPNOTSUPP;
1187 }
bf07aa73 1188
84179981
PB		 1189 /* We check chain range only for tc flows.
1190 * For ft flows, we checked attr->chain was originally 0 and set it to
1191 * FDB_FT_CHAIN which is outside tc range.
1192 * See mlx5e_rep_setup_ft_cb().
1193 */
39ac237c 1194 max_chain = mlx5_esw_chains_get_chain_range(esw);
84179981 1195 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1196 NL_SET_ERR_MSG_MOD(extack,
1197 "Requested chain is out of supported range");
5a7e5bcb 1198 return -EOPNOTSUPP;
bf07aa73
PB		 1199 }
1200
39ac237c 1201 max_prio = mlx5_esw_chains_get_prio_range(esw);
bf07aa73 1202 if (attr->prio > max_prio) {
61644c3d
RD		 1203 NL_SET_ERR_MSG_MOD(extack,
1204 "Requested priority is out of supported range");
5a7e5bcb 1205 return -EOPNOTSUPP;
bf07aa73 1206 }
e52c2802 1207
14e6b038
EC		 1208 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1209 err = mlx5e_attach_decap(priv, flow, extack);
1210 if (err)
1211 return err;
1212 }
1213
f493f155 1214 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1215 int mirred_ifindex;
1216
f493f155
EB		 1217 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1218 continue;
1219
7040632d 1220 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1221 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1222 mirred_ifindex);
733d4f36 1223 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1224 extack, &encap_dev, &encap_valid);
1225 if (err)
5a7e5bcb 1226 return err;
0ad060ee 1227
3c37745e
OG		 1228 out_priv = netdev_priv(encap_dev);
1229 rpriv = out_priv->ppriv;
1cc26d74
EB		 1230 attr->dests[out_index].rep = rpriv->rep;
1231 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1232 }
1233
8b32580d 1234 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1235 if (err)
5a7e5bcb 1236 return err;
adb4c123 1237
d5a3c2b6
RD		 1238 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1239 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1a9527bb 1240 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1241 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1242 if (err)
5a7e5bcb 1243 return err;
d7e75a32
OG		 1244 }
1245
b8aee822 1246 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1247 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1248 if (IS_ERR(counter))
1249 return PTR_ERR(counter);
b8aee822
MB		 1250
1251 attr->counter = counter;
1252 }
1253
0ad060ee
RD		 1254 /* we get here if one of the following takes place:
1255 * (1) there's no error
1256 * (2) there's an encap action and we don't have valid neigh
3c37745e 1257 */
bc1d75fa 1258 if (!encap_valid)
178f69b4 1259 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1260 else
6d2a3ed0 1261 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1262
5a7e5bcb
VB		 1263 if (IS_ERR(flow->rule[0]))
1264 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1265 else
1266 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1267
1268 return 0;
aa0cbbae 1269}
d85cdccb 1270
9272e3df
YK		 1271static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1272{
1273 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1274 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1275 spec->match_value,
1276 misc_parameters_3);
1277 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1278 headers_v,
1279 geneve_tlv_option_0_data);
1280
1281 return !!geneve_tlv_opt_0_data;
1282}
1283
d85cdccb
OG		 1284static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1285 struct mlx5e_tc_flow *flow)
1286{
1287 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1288 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
f493f155 1289 int out_index;
d85cdccb 1290
0a7fcb78
PB		 1291 mlx5e_put_flow_tunnel_id(flow);
1292
12a240a4 1293 if (flow_flag_test(flow, NOT_READY))
b4a23329 1294 remove_unready_flow(flow);
ef06c9ee 1295
226f2ca3
VB		 1296 if (mlx5e_is_offloaded_flow(flow)) {
1297 if (flow_flag_test(flow, SLOW))
178f69b4 1298 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1299 else
1300 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1301 }
d85cdccb 1302
9272e3df
YK		 1303 if (mlx5_flow_has_geneve_opt(flow))
1304 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1305
513f8f7f 1306 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1307
f493f155 1308 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1309 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1310 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1311 kfree(attr->parse_attr->tun_info[out_index]);
1312 }
f493f155 1313 kvfree(attr->parse_attr);
d7e75a32 1314
4c8594ad
RD		 1315 mlx5_tc_ct_match_del(priv, &flow->esw_attr->ct_attr);
1316
513f8f7f 1317 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1318 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1319
1320 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1321 mlx5_fc_destroy(attr->counter_dev, attr->counter);
14e6b038
EC		 1322
1323 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1324 mlx5e_detach_decap(priv, flow);
d85cdccb
OG		 1325}
1326
232c0013 1327void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1328 struct mlx5e_encap_entry *e,
1329 struct list_head *flow_list)
232c0013 1330{
3c37745e 1331 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1332 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0
OG		 1333 struct mlx5_flow_handle *rule;
1334 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1335 struct mlx5e_tc_flow *flow;
1336 int err;
1337
2b688ea5
MG		 1338 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1339 e->reformat_type,
1340 e->encap_size, e->encap_header,
1341 MLX5_FLOW_NAMESPACE_FDB);
1342 if (IS_ERR(e->pkt_reformat)) {
1343 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1344 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1345 return;
1346 }
1347 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1348 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1349
2a1f1768 1350 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1351 bool all_flow_encaps_valid = true;
1352 int i;
1353
95435ad7
VB		 1354 if (!mlx5e_is_offloaded_flow(flow))
1355 continue;
3c37745e 1356 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1357 spec = &esw_attr->parse_attr->spec;
1358
2b688ea5 1359 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1360 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1361 /* Flow can be associated with multiple encap entries.
1362 * Before offloading the flow verify that all of them have
1363 * a valid neighbour.
1364 */
1365 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1366 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1367 continue;
1368 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1369 all_flow_encaps_valid = false;
1370 break;
1371 }
1372 }
1373 /* Do not offload flows with unresolved neighbors */
1374 if (!all_flow_encaps_valid)
2a1f1768 1375 continue;
5dbe906f 1376 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1377 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1378 if (IS_ERR(rule)) {
1379 err = PTR_ERR(rule);
232c0013
HHZ		 1380 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1381 err);
2a1f1768 1382 continue;
232c0013 1383 }
5dbe906f 1384
178f69b4 1385 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1386 flow->rule[0] = rule;
226f2ca3
VB		 1387 /* was unset when slow path rule removed */
1388 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1389 }
1390}
1391
1392void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1393 struct mlx5e_encap_entry *e,
1394 struct list_head *flow_list)
232c0013 1395{
3c37745e 1396 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1397 struct mlx5_flow_handle *rule;
1398 struct mlx5_flow_spec *spec;
232c0013 1399 struct mlx5e_tc_flow *flow;
5dbe906f 1400 int err;
232c0013 1401
2a1f1768 1402 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1403 if (!mlx5e_is_offloaded_flow(flow))
1404 continue;
5dbe906f
PB		 1405 spec = &flow->esw_attr->parse_attr->spec;
1406
1407 /* update from encap rule to slow path rule */
178f69b4 1408 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1409 /* mark the flow's encap dest as non-valid */
2a1f1768 1410 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1411
1412 if (IS_ERR(rule)) {
1413 err = PTR_ERR(rule);
1414 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1415 err);
2a1f1768 1416 continue;
5dbe906f
PB		 1417 }
1418
1419 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1420 flow->rule[0] = rule;
226f2ca3
VB		 1421 /* was unset when fast path rule removed */
1422 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1423 }
1424
61c806da
OG		 1425 /* we know that the encap is valid */
1426 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1427 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1428}
1429
b8aee822
MB		 1430static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1431{
226f2ca3 1432 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1433 return flow->esw_attr->counter;
1434 else
1435 return flow->nic_attr->counter;
1436}
1437
2a1f1768
VB		 1438/* Takes reference to all flows attached to encap and adds the flows to
1439 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1440 */
1441void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1442{
1443 struct encap_flow_item *efi;
1444 struct mlx5e_tc_flow *flow;
1445
1446 list_for_each_entry(efi, &e->flows, list) {
1447 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1448 if (IS_ERR(mlx5e_flow_get(flow)))
1449 continue;
95435ad7 1450 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1451
1452 flow->tmp_efi_index = efi->index;
1453 list_add(&flow->tmp_list, flow_list);
1454 }
1455}
1456
6a06c2f7 1457/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1458void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1459{
1460 struct mlx5e_tc_flow *flow, *tmp;
1461
1462 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1463 mlx5e_flow_put(priv, flow);
1464}
1465
ac0d9176
VB		 1466static struct mlx5e_encap_entry *
1467mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1468 struct mlx5e_encap_entry *e)
1469{
1470 struct mlx5e_encap_entry *next = NULL;
1471
1472retry:
1473 rcu_read_lock();
1474
1475 /* find encap with non-zero reference counter value */
1476 for (next = e ?
1477 list_next_or_null_rcu(&nhe->encap_list,
1478 &e->encap_list,
1479 struct mlx5e_encap_entry,
1480 encap_list) :
1481 list_first_or_null_rcu(&nhe->encap_list,
1482 struct mlx5e_encap_entry,
1483 encap_list);
1484 next;
1485 next = list_next_or_null_rcu(&nhe->encap_list,
1486 &next->encap_list,
1487 struct mlx5e_encap_entry,
1488 encap_list))
1489 if (mlx5e_encap_take(next))
1490 break;
1491
1492 rcu_read_unlock();
1493
1494 /* release starting encap */
1495 if (e)
1496 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1497 if (!next)
1498 return next;
1499
1500 /* wait for encap to be fully initialized */
1501 wait_for_completion(&next->res_ready);
1502 /* continue searching if encap entry is not in valid state after completion */
1503 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1504 e = next;
1505 goto retry;
1506 }
1507
1508 return next;
1509}
1510
f6dfb4c3
HHZ		 1511void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1512{
1513 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1514 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1515 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1516 struct mlx5_fc *counter;
1517 struct neigh_table *tbl;
1518 bool neigh_used = false;
1519 struct neighbour *n;
90bb7692 1520 u64 lastuse;
f6dfb4c3
HHZ		 1521
1522 if (m_neigh->family == AF_INET)
1523 tbl = &arp_tbl;
1524#if IS_ENABLED(CONFIG_IPV6)
1525 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1526 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1527#endif
1528 else
1529 return;
1530
ac0d9176
VB		 1531 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1532 * next one.
1533 */
1534 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1535 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1536 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1537 struct mlx5_eswitch *esw;
1538 LIST_HEAD(flow_list);
948993f2 1539
6a06c2f7
VB		 1540 esw = priv->mdev->priv.eswitch;
1541 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1542 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1543 flow = container_of(efi, struct mlx5e_tc_flow,
1544 encaps[efi->index]);
5a7e5bcb
VB		 1545 if (IS_ERR(mlx5e_flow_get(flow)))
1546 continue;
6a06c2f7 1547 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1548
226f2ca3 1549 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1550 counter = mlx5e_tc_get_counter(flow);
90bb7692 1551 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1552 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1553 neigh_used = true;
1554 break;
1555 }
1556 }
1557 }
6a06c2f7 1558 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1559
6a06c2f7 1560 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1561 if (neigh_used) {
1562 /* release current encap before breaking the loop */
6a06c2f7 1563 mlx5e_encap_put(priv, e);
e36d4810 1564 break;
ac0d9176 1565 }
f6dfb4c3
HHZ		 1566 }
1567
c786fe59
VB		 1568 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1569
f6dfb4c3
HHZ		 1570 if (neigh_used) {
1571 nhe->reported_lastuse = jiffies;
1572
1573 /* find the relevant neigh according to the cached device and
1574 * dst ip pair
1575 */
1576 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1577 if (!n)
f6dfb4c3 1578 return;
f6dfb4c3
HHZ		 1579
1580 neigh_event_send(n, NULL);
1581 neigh_release(n);
1582 }
1583}
1584
61086f39 1585static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1586{
948993f2 1587 WARN_ON(!list_empty(&e->flows));
948993f2 1588
3c140dd5
VB		 1589 if (e->compl_result > 0) {
1590 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1591
1592 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1593 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1594 }
948993f2 1595
2a4b6526 1596 kfree(e->tun_info);
948993f2 1597 kfree(e->encap_header);
ac0d9176 1598 kfree_rcu(e, rcu);
948993f2
VB		 1599}
1600
14e6b038
EC		 1601static void mlx5e_decap_dealloc(struct mlx5e_priv *priv,
1602 struct mlx5e_decap_entry *d)
1603{
1604 WARN_ON(!list_empty(&d->flows));
1605
1606 if (!d->compl_result)
1607 mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat);
1608
1609 kfree_rcu(d, rcu);
1610}
1611
61086f39
VB		 1612void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1613{
1614 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1615
1616 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1617 return;
1618 hash_del_rcu(&e->encap_hlist);
1619 mutex_unlock(&esw->offloads.encap_tbl_lock);
1620
1621 mlx5e_encap_dealloc(priv, e);
1622}
1623
14e6b038
EC		 1624static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d)
1625{
1626 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1627
1628 if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock))
1629 return;
1630 hash_del_rcu(&d->hlist);
1631 mutex_unlock(&esw->offloads.decap_tbl_lock);
1632
1633 mlx5e_decap_dealloc(priv, d);
1634}
1635
d85cdccb 1636static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1637 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1638{
61086f39
VB		 1639 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1640 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1641
5a7e5bcb 1642 /* flow wasn't fully initialized */
61086f39 1643 if (!e)
5a7e5bcb
VB		 1644 return;
1645
61086f39 1646 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1647 list_del(&flow->encaps[out_index].list);
948993f2 1648 flow->encaps[out_index].e = NULL;
61086f39
VB		 1649 if (!refcount_dec_and_test(&e->refcnt)) {
1650 mutex_unlock(&esw->offloads.encap_tbl_lock);
1651 return;
1652 }
1653 hash_del_rcu(&e->encap_hlist);
1654 mutex_unlock(&esw->offloads.encap_tbl_lock);
1655
1656 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1657}
1658
14e6b038
EC		 1659static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1660 struct mlx5e_tc_flow *flow)
1661{
1662 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1663 struct mlx5e_decap_entry *d = flow->decap_reformat;
1664
1665 if (!d)
1666 return;
1667
1668 mutex_lock(&esw->offloads.decap_tbl_lock);
1669 list_del(&flow->l3_to_l2_reformat);
1670 flow->decap_reformat = NULL;
1671
1672 if (!refcount_dec_and_test(&d->refcnt)) {
1673 mutex_unlock(&esw->offloads.decap_tbl_lock);
1674 return;
1675 }
1676 hash_del_rcu(&d->hlist);
1677 mutex_unlock(&esw->offloads.decap_tbl_lock);
1678
1679 mlx5e_decap_dealloc(priv, d);
1680}
1681
04de7dda
RD		 1682static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1683{
1684 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1685
226f2ca3
VB		 1686 if (!flow_flag_test(flow, ESWITCH) ||
1687 !flow_flag_test(flow, DUP))
04de7dda
RD		 1688 return;
1689
1690 mutex_lock(&esw->offloads.peer_mutex);
1691 list_del(&flow->peer);
1692 mutex_unlock(&esw->offloads.peer_mutex);
1693
226f2ca3 1694 flow_flag_clear(flow, DUP);
04de7dda 1695
eb252c3a
RD		 1696 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1697 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1698 kfree(flow->peer_flow);
1699 }
1700
04de7dda
RD		 1701 flow->peer_flow = NULL;
1702}
1703
1704static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1705{
1706 struct mlx5_core_dev *dev = flow->priv->mdev;
1707 struct mlx5_devcom *devcom = dev->priv.devcom;
1708 struct mlx5_eswitch *peer_esw;
1709
1710 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1711 if (!peer_esw)
1712 return;
1713
1714 __mlx5e_tc_del_fdb_peer_flow(flow);
1715 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1716}
1717
e8f887ac 1718static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1719 struct mlx5e_tc_flow *flow)
e8f887ac 1720{
226f2ca3 1721 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1722 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1723 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1724 } else {
d85cdccb 1725 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1726 }
e8f887ac
AV		 1727}
1728
0a7fcb78
PB		 1729static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1730{
1731 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1732 struct flow_action *flow_action = &rule->action;
1733 const struct flow_action_entry *act;
1734 int i;
1735
1736 flow_action_for_each(i, act, flow_action) {
1737 switch (act->id) {
1738 case FLOW_ACTION_GOTO:
1739 return true;
1740 default:
1741 continue;
1742 }
1743 }
1744
1745 return false;
1746}
bbd00f7e 1747
0a7fcb78
PB		 1748static int
1749enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1750 struct flow_dissector_key_enc_opts *opts,
1751 struct netlink_ext_ack *extack,
1752 bool *dont_care)
1753{
1754 struct geneve_opt *opt;
1755 int off = 0;
1756
1757 *dont_care = true;
1758
1759 while (opts->len > off) {
1760 opt = (struct geneve_opt *)&opts->data[off];
1761
1762 if (!(*dont_care) || opt->opt_class || opt->type ||
1763 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1764 *dont_care = false;
1765
c51323ee 1766 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1767 opt->type != U8_MAX) {
0a7fcb78
PB		 1768 NL_SET_ERR_MSG(extack,
1769 "Partial match of tunnel options in chain > 0 isn't supported");
1770 netdev_warn(priv->netdev,
1771 "Partial match of tunnel options in chain > 0 isn't supported");
1772 return -EOPNOTSUPP;
1773 }
1774 }
1775
1776 off += sizeof(struct geneve_opt) + opt->length * 4;
1777 }
1778
1779 return 0;
1780}
1781
1782#define COPY_DISSECTOR(rule, diss_key, dst)\
1783({ \
1784 struct flow_rule *__rule = (rule);\
1785 typeof(dst) __dst = dst;\
1786\
1787 memcpy(__dst,\
1788 skb_flow_dissector_target(__rule->match.dissector,\
1789 diss_key,\
1790 __rule->match.key),\
1791 sizeof(*__dst));\
1792})
1793
1794static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1795 struct mlx5e_tc_flow *flow,
1796 struct flow_cls_offload *f,
1797 struct net_device *filter_dev)
bbd00f7e 1798{
f9e30088 1799 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78
PB		 1800 struct netlink_ext_ack *extack = f->common.extack;
1801 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1802 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1803 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1804 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78
PB		 1805 struct mlx5_rep_uplink_priv *uplink_priv;
1806 struct mlx5e_rep_priv *uplink_rpriv;
1807 struct tunnel_match_key tunnel_key;
1808 bool enc_opts_is_dont_care = true;
1809 u32 tun_id, enc_opts_id = 0;
1810 struct mlx5_eswitch *esw;
1811 u32 value, mask;
8f256622 1812 int err;
2e72eb43 1813
0a7fcb78
PB		 1814 esw = priv->mdev->priv.eswitch;
1815 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1816 uplink_priv = &uplink_rpriv->uplink_priv;
1817
1818 memset(&tunnel_key, 0, sizeof(tunnel_key));
1819 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1820 &tunnel_key.enc_control);
1821 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1822 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1823 &tunnel_key.enc_ipv4);
1824 else
1825 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1826 &tunnel_key.enc_ipv6);
1827 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1828 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1829 &tunnel_key.enc_tp);
1830 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1831 &tunnel_key.enc_key_id);
1832 tunnel_key.filter_ifindex = filter_dev->ifindex;
1833
1834 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1835 if (err)
101f4de9 1836 return err;
bbd00f7e 1837
0a7fcb78
PB		 1838 flow_rule_match_enc_opts(rule, &enc_opts_match);
1839 err = enc_opts_is_dont_care_or_full_match(priv,
1840 enc_opts_match.mask,
1841 extack,
1842 &enc_opts_is_dont_care);
1843 if (err)
1844 goto err_enc_opts;
fe1587a7 1845
0a7fcb78 1846 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1847 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1848 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1849 sizeof(*enc_opts_match.key));
1850 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1851 sizeof(*enc_opts_match.mask));
1852
0a7fcb78 1853 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1854 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1855 if (err)
1856 goto err_enc_opts;
1857 }
fe1587a7 1858
0a7fcb78
PB		 1859 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1860 mask = enc_opts_id ? TUNNEL_ID_MASK :
1861 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1862
0a7fcb78
PB		 1863 if (attr->chain) {
1864 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1865 TUNNEL_TO_REG, value, mask);
1866 } else {
1867 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1868 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1869 mod_hdr_acts,
1870 TUNNEL_TO_REG, value);
1871 if (err)
1872 goto err_set;
fe1587a7 1873
0a7fcb78 1874 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1875 }
bbd00f7e 1876
0a7fcb78
PB		 1877 flow->tunnel_id = value;
1878 return 0;
bcef735c 1879
0a7fcb78
PB		 1880err_set:
1881 if (enc_opts_id)
1882 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1883 enc_opts_id);
1884err_enc_opts:
1885 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1886 return err;
1887}
bcef735c 1888
0a7fcb78
PB		 1889static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1890{
1891 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1892 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1893 struct mlx5_rep_uplink_priv *uplink_priv;
1894 struct mlx5e_rep_priv *uplink_rpriv;
1895 struct mlx5_eswitch *esw;
bcef735c 1896
0a7fcb78
PB		 1897 esw = flow->priv->mdev->priv.eswitch;
1898 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1899 uplink_priv = &uplink_rpriv->uplink_priv;
1900
1901 if (tun_id)
1902 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1903 if (enc_opts_id)
1904 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1905 enc_opts_id);
1906}
e98bedf5 1907
4c3844d9
PB		 1908u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1909{
1910 return flow->tunnel_id;
1911}
1912
fca53304
EB		 1913void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1914 struct flow_match_basic *match, bool outer,
1915 void *headers_c, void *headers_v)
1916{
1917 bool ip_version_cap;
1918
1919 ip_version_cap = outer ?
1920 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1921 ft_field_support.outer_ip_version) :
1922 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1923 ft_field_support.inner_ip_version);
1924
1925 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1926 (match->key->n_proto == htons(ETH_P_IP) ||
1927 match->key->n_proto == htons(ETH_P_IPV6))) {
1928 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1929 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1930 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1931 } else {
1932 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1933 ntohs(match->mask->n_proto));
1934 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1935 ntohs(match->key->n_proto));
1936 }
4a5d5d73
EB		 1937}
1938
bbd00f7e 1939static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1940 struct mlx5e_tc_flow *flow,
bbd00f7e 1941 struct mlx5_flow_spec *spec,
f9e30088 1942 struct flow_cls_offload *f,
0a7fcb78
PB		 1943 struct net_device *filter_dev,
1944 u8 *match_level,
1945 bool *match_inner)
bbd00f7e 1946{
0a7fcb78 1947 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1948 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1949 bool needs_mapping, sets_mapping;
8f256622 1950 int err;
2e72eb43 1951
0a7fcb78
PB		 1952 if (!mlx5e_is_eswitch_flow(flow))
1953 return -EOPNOTSUPP;
1954
1955 needs_mapping = !!flow->esw_attr->chain;
1956 sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f);
1957 *match_inner = !needs_mapping;
1958
1959 if ((needs_mapping || sets_mapping) &&
636bb968 1960 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1961 NL_SET_ERR_MSG(extack,
636bb968 1962 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1963 netdev_warn(priv->netdev,
636bb968 1964 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1965 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1966 }
1967
0a7fcb78
PB		 1968 if (!flow->esw_attr->chain) {
1969 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1970 match_level);
1971 if (err) {
e98bedf5 1972 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1973 "Failed to parse tunnel attributes");
1974 netdev_warn(priv->netdev,
1975 "Failed to parse tunnel attributes");
1976 return err;
e98bedf5
EB		 1977 }
1978
14e6b038
EC		 1979 /* With mpls over udp we decapsulate using packet reformat
1980 * object
1981 */
1982 if (!netif_is_bareudp(filter_dev))
1983 flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 1984 }
1985
0a7fcb78
PB		 1986 if (!needs_mapping && !sets_mapping)
1987 return 0;
bbd00f7e 1988
0a7fcb78 1989 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1990}
bbd00f7e 1991
0a7fcb78 1992static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1993{
0a7fcb78
PB		 1994 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1995 inner_headers);
bbd00f7e
HHZ		 1996}
1997
0a7fcb78 1998static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1999{
0a7fcb78
PB		 2000 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2001 inner_headers);
2002}
2003
2004static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2005{
2006 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2007 outer_headers);
2008}
2009
2010static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2011{
2012 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2013 outer_headers);
8377629e
EB		 2014}
2015
2016static void *get_match_headers_value(u32 flags,
2017 struct mlx5_flow_spec *spec)
2018{
2019 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2020 get_match_inner_headers_value(spec) :
2021 get_match_outer_headers_value(spec);
2022}
2023
2024static void *get_match_headers_criteria(u32 flags,
2025 struct mlx5_flow_spec *spec)
2026{
2027 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2028 get_match_inner_headers_criteria(spec) :
2029 get_match_outer_headers_criteria(spec);
8377629e
EB		 2030}
2031
6d65bc64 2032static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2033 struct flow_cls_offload *f)
2034{
2035 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2036 struct netlink_ext_ack *extack = f->common.extack;
2037 struct net_device *ingress_dev;
2038 struct flow_match_meta match;
2039
2040 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2041 return 0;
2042
2043 flow_rule_match_meta(rule, &match);
2044 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2045 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2046 return -EOPNOTSUPP;
6d65bc64 2047 }
2048
2049 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2050 match.key->ingress_ifindex);
2051 if (!ingress_dev) {
2052 NL_SET_ERR_MSG_MOD(extack,
2053 "Can't find the ingress port to match on");
a683012a 2054 return -ENOENT;
6d65bc64 2055 }
2056
2057 if (ingress_dev != filter_dev) {
2058 NL_SET_ERR_MSG_MOD(extack,
2059 "Can't match on the ingress filter port");
a683012a 2060 return -EOPNOTSUPP;
6d65bc64 2061 }
2062
2063 return 0;
2064}
2065
72046a91
EC		 2066static bool skip_key_basic(struct net_device *filter_dev,
2067 struct flow_cls_offload *f)
2068{
2069 /* When doing mpls over udp decap, the user needs to provide
2070 * MPLS_UC as the protocol in order to be able to match on mpls
2071 * label fields. However, the actual ethertype is IP so we want to
2072 * avoid matching on this, otherwise we'll fail the match.
2073 */
2074 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2075 return true;
2076
2077 return false;
2078}
2079
de0af0bf 2080static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2081 struct mlx5e_tc_flow *flow,
de0af0bf 2082 struct mlx5_flow_spec *spec,
f9e30088 2083 struct flow_cls_offload *f,
54c177ca 2084 struct net_device *filter_dev,
93b3586e 2085 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2086{
e98bedf5 2087 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2088 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2089 outer_headers);
2090 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2091 outer_headers);
699e96dd
JL		 2092 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2093 misc_parameters);
2094 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2095 misc_parameters);
f9e30088 2096 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2097 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2098 u16 addr_type = 0;
2099 u8 ip_proto = 0;
93b3586e 2100 u8 *match_level;
6d65bc64 2101 int err;
e3a2b7ed 2102
93b3586e 2103 match_level = outer_match_level;
de0af0bf 2104
8f256622 2105 if (dissector->used_keys &
3d144578
VB		 2106 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2107 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2108 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2109 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2110 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2111 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2112 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2113 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2114 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2115 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2116 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2117 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2118 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2119 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2120 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2121 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2122 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2123 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91
EC		 2124 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2125 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2126 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 2127 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 2128 dissector->used_keys);
e3a2b7ed
AV		 2129 return -EOPNOTSUPP;
2130 }
2131
075973c7 2132 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2133 bool match_inner = false;
bbd00f7e 2134
0a7fcb78
PB		 2135 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2136 outer_match_level, &match_inner);
2137 if (err)
2138 return err;
2139
2140 if (match_inner) {
2141 /* header pointers should point to the inner headers
2142 * if the packet was decapsulated already.
2143 * outer headers are set by parse_tunnel_attr.
2144 */
2145 match_level = inner_match_level;
2146 headers_c = get_match_inner_headers_criteria(spec);
2147 headers_v = get_match_inner_headers_value(spec);
2148 }
bbd00f7e
HHZ		 2149 }
2150
6d65bc64 2151 err = mlx5e_flower_parse_meta(filter_dev, f);
2152 if (err)
2153 return err;
2154
72046a91
EC		 2155 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2156 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2157 struct flow_match_basic match;
2158
2159 flow_rule_match_basic(rule, &match);
fca53304
EB		 2160 mlx5e_tc_set_ethertype(priv->mdev, &match,
2161 match_level == outer_match_level,
2162 headers_c, headers_v);
e3a2b7ed 2163
8f256622 2164 if (match.mask->n_proto)
d708f902 2165 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2166 }
35a605db
EB		 2167 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2168 is_vlan_dev(filter_dev)) {
2169 struct flow_dissector_key_vlan filter_dev_mask;
2170 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2171 struct flow_match_vlan match;
2172
35a605db
EB		 2173 if (is_vlan_dev(filter_dev)) {
2174 match.key = &filter_dev_key;
2175 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2176 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2177 match.key->vlan_priority = 0;
2178 match.mask = &filter_dev_mask;
2179 memset(match.mask, 0xff, sizeof(*match.mask));
2180 match.mask->vlan_priority = 0;
2181 } else {
2182 flow_rule_match_vlan(rule, &match);
2183 }
8f256622
PNA		 2184 if (match.mask->vlan_id ||
2185 match.mask->vlan_priority ||
2186 match.mask->vlan_tpid) {
2187 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2188 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2189 svlan_tag, 1);
2190 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2191 svlan_tag, 1);
2192 } else {
2193 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2194 cvlan_tag, 1);
2195 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2196 cvlan_tag, 1);
2197 }
095b6cfd 2198
8f256622
PNA		 2199 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2200 match.mask->vlan_id);
2201 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2202 match.key->vlan_id);
358d79a4 2203
8f256622
PNA		 2204 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2205 match.mask->vlan_priority);
2206 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2207 match.key->vlan_priority);
54782900 2208
d708f902 2209 *match_level = MLX5_MATCH_L2;
54782900 2210 }
d3a80bb5 2211 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2212 /* cvlan_tag enabled in match criteria and
2213 * disabled in match value means both S & C tags
2214 * don't exist (untagged of both)
2215 */
cee26487 2216 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2217 *match_level = MLX5_MATCH_L2;
54782900
OG		 2218 }
2219
8f256622
PNA		 2220 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2221 struct flow_match_vlan match;
2222
12d5cbf8 2223 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2224 if (match.mask->vlan_id ||
2225 match.mask->vlan_priority ||
2226 match.mask->vlan_tpid) {
2227 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2228 MLX5_SET(fte_match_set_misc, misc_c,
2229 outer_second_svlan_tag, 1);
2230 MLX5_SET(fte_match_set_misc, misc_v,
2231 outer_second_svlan_tag, 1);
2232 } else {
2233 MLX5_SET(fte_match_set_misc, misc_c,
2234 outer_second_cvlan_tag, 1);
2235 MLX5_SET(fte_match_set_misc, misc_v,
2236 outer_second_cvlan_tag, 1);
2237 }
2238
2239 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2240 match.mask->vlan_id);
699e96dd 2241 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2242 match.key->vlan_id);
699e96dd 2243 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2244 match.mask->vlan_priority);
699e96dd 2245 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2246 match.key->vlan_priority);
699e96dd
JL		 2247
2248 *match_level = MLX5_MATCH_L2;
0faddfe6 2249 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2250 }
2251 }
2252
8f256622
PNA		 2253 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2254 struct flow_match_eth_addrs match;
54782900 2255
8f256622 2256 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2257 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2258 dmac_47_16),
8f256622 2259 match.mask->dst);
d3a80bb5
OG		 2260 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2261 dmac_47_16),
8f256622 2262 match.key->dst);
d3a80bb5
OG		 2263
2264 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2265 smac_47_16),
8f256622 2266 match.mask->src);
d3a80bb5
OG		 2267 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2268 smac_47_16),
8f256622 2269 match.key->src);
d3a80bb5 2270
8f256622
PNA		 2271 if (!is_zero_ether_addr(match.mask->src) ||
2272 !is_zero_ether_addr(match.mask->dst))
d708f902 2273 *match_level = MLX5_MATCH_L2;
54782900
OG		 2274 }
2275
8f256622
PNA		 2276 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2277 struct flow_match_control match;
54782900 2278
8f256622
PNA		 2279 flow_rule_match_control(rule, &match);
2280 addr_type = match.key->addr_type;
54782900
OG		 2281
2282 /* the HW doesn't support frag first/later */
8f256622 2283 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2284 return -EOPNOTSUPP;
2285
8f256622 2286 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2287 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2288 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2289 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2290
2291 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2292 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2293 *match_level = MLX5_MATCH_L2;
54782900
OG		 2294 /* *** L2 attributes parsing up to here *** */
2295 else
83621b7d 2296 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2297 }
2298 }
2299
8f256622
PNA		 2300 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2301 struct flow_match_basic match;
2302
2303 flow_rule_match_basic(rule, &match);
2304 ip_proto = match.key->ip_proto;
54782900
OG		 2305
2306 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2307 match.mask->ip_proto);
54782900 2308 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2309 match.key->ip_proto);
54782900 2310
8f256622 2311 if (match.mask->ip_proto)
d708f902 2312 *match_level = MLX5_MATCH_L3;
54782900
OG		 2313 }
2314
e3a2b7ed 2315 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2316 struct flow_match_ipv4_addrs match;
e3a2b7ed 2317
8f256622 2318 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2319 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2320 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2321 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2322 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2323 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2324 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2325 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2326 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2327 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2328 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2329 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2330 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2331
8f256622 2332 if (match.mask->src || match.mask->dst)
d708f902 2333 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2334 }
2335
2336 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2337 struct flow_match_ipv6_addrs match;
e3a2b7ed 2338
8f256622 2339 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2340 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2341 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2342 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2343 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2344 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2345 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2346
2347 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2348 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2349 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2350 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2351 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2352 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2353
8f256622
PNA		 2354 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2355 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2356 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2357 }
2358
8f256622
PNA		 2359 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2360 struct flow_match_ip match;
1f97a526 2361
8f256622
PNA		 2362 flow_rule_match_ip(rule, &match);
2363 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2364 match.mask->tos & 0x3);
2365 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2366 match.key->tos & 0x3);
1f97a526 2367
8f256622
PNA		 2368 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2369 match.mask->tos >> 2);
2370 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2371 match.key->tos >> 2);
1f97a526 2372
8f256622
PNA		 2373 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2374 match.mask->ttl);
2375 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2376 match.key->ttl);
1f97a526 2377
8f256622 2378 if (match.mask->ttl &&
a8ade55f 2379 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2380 ft_field_support.outer_ipv4_ttl)) {
2381 NL_SET_ERR_MSG_MOD(extack,
2382 "Matching on TTL is not supported");
1f97a526 2383 return -EOPNOTSUPP;
e98bedf5 2384 }
a8ade55f 2385
8f256622 2386 if (match.mask->tos || match.mask->ttl)
d708f902 2387 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2388 }
2389
54782900
OG		 2390 /* *** L3 attributes parsing up to here *** */
2391
8f256622
PNA		 2392 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2393 struct flow_match_ports match;
2394
2395 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2396 switch (ip_proto) {
2397 case IPPROTO_TCP:
2398 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2399 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2400 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2401 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2402
2403 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2404 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2405 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2406 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2407 break;
2408
2409 case IPPROTO_UDP:
2410 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2411 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2412 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2413 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2414
2415 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2416 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2417 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2418 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2419 break;
2420 default:
e98bedf5
EB		 2421 NL_SET_ERR_MSG_MOD(extack,
2422 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2423 netdev_err(priv->netdev,
2424 "Only UDP and TCP transport are supported\n");
2425 return -EINVAL;
2426 }
de0af0bf 2427
8f256622 2428 if (match.mask->src || match.mask->dst)
d708f902 2429 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2430 }
2431
8f256622
PNA		 2432 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2433 struct flow_match_tcp match;
e77834ec 2434
8f256622 2435 flow_rule_match_tcp(rule, &match);
e77834ec 2436 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2437 ntohs(match.mask->flags));
e77834ec 2438 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2439 ntohs(match.key->flags));
e77834ec 2440
8f256622 2441 if (match.mask->flags)
d708f902 2442 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2443 }
2444
e3a2b7ed
AV		 2445 return 0;
2446}
2447
de0af0bf 2448static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2449 struct mlx5e_tc_flow *flow,
de0af0bf 2450 struct mlx5_flow_spec *spec,
f9e30088 2451 struct flow_cls_offload *f,
54c177ca 2452 struct net_device *filter_dev)
de0af0bf 2453{
93b3586e 2454 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2455 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2456 struct mlx5_core_dev *dev = priv->mdev;
2457 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2458 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2459 struct mlx5_eswitch_rep *rep;
226f2ca3 2460 bool is_eswitch_flow;
de0af0bf
RD		 2461 int err;
2462
93b3586e
HN		 2463 inner_match_level = MLX5_MATCH_NONE;
2464 outer_match_level = MLX5_MATCH_NONE;
2465
0a7fcb78
PB		 2466 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2467 &inner_match_level, &outer_match_level);
93b3586e
HN		 2468 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2469 outer_match_level : inner_match_level;
de0af0bf 2470
226f2ca3
VB		 2471 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2472 if (!err && is_eswitch_flow) {
1d447a39 2473 rep = rpriv->rep;
b05af6aa 2474 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2475 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2476 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2477 NL_SET_ERR_MSG_MOD(extack,
2478 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2479 netdev_warn(priv->netdev,
2480 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2481 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2482 return -EOPNOTSUPP;
2483 }
2484 }
2485
226f2ca3 2486 if (is_eswitch_flow) {
93b3586e
HN		 2487 flow->esw_attr->inner_match_level = inner_match_level;
2488 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2489 } else {
93b3586e 2490 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2491 }
38aa51c1 2492
de0af0bf
RD		 2493 return err;
2494}
2495
d79b6df6
OG		 2496struct pedit_headers {
2497 struct ethhdr eth;
0eb69bb9 2498 struct vlan_hdr vlan;
d79b6df6
OG		 2499 struct iphdr ip4;
2500 struct ipv6hdr ip6;
2501 struct tcphdr tcp;
2502 struct udphdr udp;
2503};
2504
c500c86b
PNA		 2505struct pedit_headers_action {
2506 struct pedit_headers vals;
2507 struct pedit_headers masks;
2508 u32 pedits;
2509};
2510
d79b6df6 2511static int pedit_header_offsets[] = {
73867881
PNA		 2512 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2513 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2514 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2515 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2516 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2517};
2518
2519#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2520
2521static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2522 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2523{
2524 u32 *curr_pmask, *curr_pval;
2525
c500c86b
PNA		 2526 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2527 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2528
2529 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2530 goto out_err;
2531
2532 *curr_pmask |= mask;
2533 *curr_pval |= (val & mask);
2534
2535 return 0;
2536
2537out_err:
2538 return -EOPNOTSUPP;
2539}
2540
2541struct mlx5_fields {
2542 u8 field;
88f30bbc
DL		 2543 u8 field_bsize;
2544 u32 field_mask;
d79b6df6 2545 u32 offset;
27c11b6b 2546 u32 match_offset;
d79b6df6
OG		 2547};
2548
88f30bbc
DL		 2549#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2550 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2551 offsetof(struct pedit_headers, field) + (off), \
2552 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2553
2ef86872
EB		 2554/* masked values are the same and there are no rewrites that do not have a
2555 * match.
2556 */
2557#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2558 type matchmaskx = *(type *)(matchmaskp); \
2559 type matchvalx = *(type *)(matchvalp); \
2560 type maskx = *(type *)(maskp); \
2561 type valx = *(type *)(valp); \
2562 \
2563 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2564 matchmaskx)); \
2565})
2566
27c11b6b 2567static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2568 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2569{
2570 bool same = false;
2571
88f30bbc
DL		 2572 switch (bsize) {
2573 case 8:
2ef86872 2574 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2575 break;
88f30bbc 2576 case 16:
2ef86872 2577 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2578 break;
88f30bbc 2579 case 32:
2ef86872 2580 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2581 break;
2582 }
2583
2584 return same;
2585}
a8e4f0c4 2586
d79b6df6 2587static struct mlx5_fields fields[] = {
88f30bbc
DL		 2588 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2589 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2590 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2591 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2592 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2593 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2594
ab9341b5 2595 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2596 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2597 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2598 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2599
2600 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2601 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2602 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2603 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2604 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2605 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2606 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2607 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2608 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2609 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2610 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2611 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2612 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2613 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2614 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2615 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2616 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
27c11b6b 2617
88f30bbc
DL		 2618 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2619 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2620 /* in linux iphdr tcp_flags is 8 bits long */
2621 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2622
88f30bbc
DL		 2623 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2624 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2625};
2626
6ae4a6a5
PB		 2627static int offload_pedit_fields(struct mlx5e_priv *priv,
2628 int namespace,
2629 struct pedit_headers_action *hdrs,
e98bedf5 2630 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2631 u32 *action_flags,
e98bedf5 2632 struct netlink_ext_ack *extack)
d79b6df6
OG		 2633{
2634 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2635 int i, action_size, first, last, next_z;
88f30bbc
DL		 2636 void *headers_c, *headers_v, *action, *vals_p;
2637 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2638 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2639 struct mlx5_fields *f;
d79b6df6 2640 unsigned long mask;
2b64beba
OG		 2641 __be32 mask_be32;
2642 __be16 mask_be16;
6ae4a6a5 2643 int err;
88f30bbc
DL		 2644 u8 cmd;
2645
6ae4a6a5 2646 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2647 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2648 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2649
73867881
PNA		 2650 set_masks = &hdrs[0].masks;
2651 add_masks = &hdrs[1].masks;
2652 set_vals = &hdrs[0].vals;
2653 add_vals = &hdrs[1].vals;
d79b6df6 2654
d65dbedf 2655 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2656
2657 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2658 bool skip;
2659
d79b6df6
OG		 2660 f = &fields[i];
2661 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2662 s_mask = 0;
2663 a_mask = 0;
d79b6df6
OG		 2664
2665 s_masks_p = (void *)set_masks + f->offset;
2666 a_masks_p = (void *)add_masks + f->offset;
2667
88f30bbc
DL		 2668 s_mask = *s_masks_p & f->field_mask;
2669 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2670
2671 if (!s_mask && !a_mask) /* nothing to offload here */
2672 continue;
2673
2674 if (s_mask && a_mask) {
e98bedf5
EB		 2675 NL_SET_ERR_MSG_MOD(extack,
2676 "can't set and add to the same HW field");
d79b6df6
OG		 2677 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2678 return -EOPNOTSUPP;
2679 }
2680
27c11b6b 2681 skip = false;
d79b6df6 2682 if (s_mask) {
27c11b6b
EB		 2683 void *match_mask = headers_c + f->match_offset;
2684 void *match_val = headers_v + f->match_offset;
2685
d79b6df6
OG		 2686 cmd = MLX5_ACTION_TYPE_SET;
2687 mask = s_mask;
2688 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2689 /* don't rewrite if we have a match on the same value */
2690 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2691 match_mask, f->field_bsize))
27c11b6b 2692 skip = true;
d79b6df6 2693 /* clear to denote we consumed this field */
88f30bbc 2694 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2695 } else {
2696 cmd = MLX5_ACTION_TYPE_ADD;
2697 mask = a_mask;
2698 vals_p = (void *)add_vals + f->offset;
27c11b6b 2699 /* add 0 is no change */
88f30bbc 2700 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2701 skip = true;
d79b6df6 2702 /* clear to denote we consumed this field */
88f30bbc 2703 *a_masks_p &= ~f->field_mask;
d79b6df6 2704 }
27c11b6b
EB		 2705 if (skip)
2706 continue;
d79b6df6 2707
88f30bbc 2708 if (f->field_bsize == 32) {
58ff18e1 2709 mask_be32 = (__force __be32)(mask);
2b64beba 2710 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
88f30bbc 2711 } else if (f->field_bsize == 16) {
58ff18e1 2712 mask_be32 = (__force __be32)(mask);
404402ab 2713 mask_be16 = *(__be16 *)&mask_be32;
2b64beba
OG		 2714 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2715 }
2716
88f30bbc
DL		 2717 first = find_first_bit(&mask, f->field_bsize);
2718 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2719 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2720 if (first < next_z && next_z < last) {
e98bedf5
EB		 2721 NL_SET_ERR_MSG_MOD(extack,
2722 "rewrite of few sub-fields isn't supported");
2b64beba 2723 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2724 mask);
2725 return -EOPNOTSUPP;
2726 }
2727
6ae4a6a5
PB		 2728 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2729 if (err) {
2730 NL_SET_ERR_MSG_MOD(extack,
2731 "too many pedit actions, can't offload");
2732 mlx5_core_warn(priv->mdev,
2733 "mlx5: parsed %d pedit actions, can't do more\n",
2734 mod_acts->num_actions);
2735 return err;
2736 }
2737
2738 action = mod_acts->actions +
2739 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2740 MLX5_SET(set_action_in, action, action_type, cmd);
2741 MLX5_SET(set_action_in, action, field, f->field);
2742
2743 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2744 int start;
2745
2746 /* if field is bit sized it can start not from first bit */
2747 start = find_first_bit((unsigned long *)&f->field_mask,
2748 f->field_bsize);
2749
2750 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2751 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2752 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2753 }
2754
88f30bbc 2755 if (f->field_bsize == 32)
2b64beba 2756 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2757 else if (f->field_bsize == 16)
2b64beba 2758 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2759 else if (f->field_bsize == 8)
2b64beba 2760 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2761
6ae4a6a5 2762 ++mod_acts->num_actions;
d79b6df6
OG		 2763 }
2764
d79b6df6
OG		 2765 return 0;
2766}
2767
2cc1cb1d
TZ		 2768static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2769 int namespace)
2770{
2771 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2772 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2773 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2774 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2775}
2776
6ae4a6a5
PB		 2777int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2778 int namespace,
2779 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2780{
6ae4a6a5
PB		 2781 int action_size, new_num_actions, max_hw_actions;
2782 size_t new_sz, old_sz;
2783 void *ret;
d79b6df6 2784
6ae4a6a5
PB		 2785 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2786 return 0;
d79b6df6 2787
d65dbedf 2788 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2789
6ae4a6a5
PB		 2790 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2791 namespace);
2792 new_num_actions = min(max_hw_actions,
2793 mod_hdr_acts->actions ?
2794 mod_hdr_acts->max_actions * 2 : 1);
2795 if (mod_hdr_acts->max_actions == new_num_actions)
2796 return -ENOSPC;
2797
2798 new_sz = action_size * new_num_actions;
2799 old_sz = mod_hdr_acts->max_actions * action_size;
2800 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2801 if (!ret)
d79b6df6
OG		 2802 return -ENOMEM;
2803
6ae4a6a5
PB		 2804 memset(ret + old_sz, 0, new_sz - old_sz);
2805 mod_hdr_acts->actions = ret;
2806 mod_hdr_acts->max_actions = new_num_actions;
2807
d79b6df6
OG		 2808 return 0;
2809}
2810
6ae4a6a5
PB		 2811void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2812{
2813 kfree(mod_hdr_acts->actions);
2814 mod_hdr_acts->actions = NULL;
2815 mod_hdr_acts->num_actions = 0;
2816 mod_hdr_acts->max_actions = 0;
2817}
2818
d79b6df6
OG		 2819static const struct pedit_headers zero_masks = {};
2820
582234b4
EC		 2821static int
2822parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2823 const struct flow_action_entry *act, int namespace,
2824 struct mlx5e_tc_flow_parse_attr *parse_attr,
2825 struct pedit_headers_action *hdrs,
2826 struct netlink_ext_ack *extack)
d79b6df6 2827{
73867881
PNA		 2828 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2829 int err = -EOPNOTSUPP;
d79b6df6 2830 u32 mask, val, offset;
73867881 2831 u8 htype;
d79b6df6 2832
73867881
PNA		 2833 htype = act->mangle.htype;
2834 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2835
73867881
PNA		 2836 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2837 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2838 goto out_err;
2839 }
d79b6df6 2840
2cc1cb1d
TZ		 2841 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2842 NL_SET_ERR_MSG_MOD(extack,
2843 "The pedit offload action is not supported");
2844 goto out_err;
2845 }
2846
73867881
PNA		 2847 mask = act->mangle.mask;
2848 val = act->mangle.val;
2849 offset = act->mangle.offset;
d79b6df6 2850
73867881
PNA		 2851 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2852 if (err)
2853 goto out_err;
c500c86b 2854
73867881 2855 hdrs[cmd].pedits++;
d79b6df6 2856
c500c86b
PNA		 2857 return 0;
2858out_err:
2859 return err;
2860}
2861
582234b4
EC		 2862static int
2863parse_pedit_to_reformat(struct mlx5e_priv *priv,
2864 const struct flow_action_entry *act,
2865 struct mlx5e_tc_flow_parse_attr *parse_attr,
2866 struct netlink_ext_ack *extack)
2867{
2868 u32 mask, val, offset;
2869 u32 *p;
2870
2871 if (act->id != FLOW_ACTION_MANGLE)
2872 return -EOPNOTSUPP;
2873
2874 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2875 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2876 return -EOPNOTSUPP;
2877 }
2878
2879 mask = ~act->mangle.mask;
2880 val = act->mangle.val;
2881 offset = act->mangle.offset;
2882 p = (u32 *)&parse_attr->eth;
2883 *(p + (offset >> 2)) |= (val & mask);
2884
2885 return 0;
2886}
2887
2888static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2889 const struct flow_action_entry *act, int namespace,
2890 struct mlx5e_tc_flow_parse_attr *parse_attr,
2891 struct pedit_headers_action *hdrs,
2892 struct mlx5e_tc_flow *flow,
2893 struct netlink_ext_ack *extack)
2894{
2895 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2896 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2897
2898 return parse_pedit_to_modify_hdr(priv, act, namespace,
2899 parse_attr, hdrs, extack);
2900}
2901
c500c86b
PNA		 2902static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2903 struct mlx5e_tc_flow_parse_attr *parse_attr,
2904 struct pedit_headers_action *hdrs,
27c11b6b 2905 u32 *action_flags,
c500c86b
PNA		 2906 struct netlink_ext_ack *extack)
2907{
2908 struct pedit_headers *cmd_masks;
2909 int err;
2910 u8 cmd;
2911
6ae4a6a5
PB		 2912 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2913 action_flags, extack);
d79b6df6
OG		 2914 if (err < 0)
2915 goto out_dealloc_parsed_actions;
2916
2917 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2918 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2919 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2920 NL_SET_ERR_MSG_MOD(extack,
2921 "attempt to offload an unsupported field");
b3a433de 2922 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2923 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2924 16, 1, cmd_masks, sizeof(zero_masks), true);
2925 err = -EOPNOTSUPP;
2926 goto out_dealloc_parsed_actions;
2927 }
2928 }
2929
2930 return 0;
2931
2932out_dealloc_parsed_actions:
6ae4a6a5 2933 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2934 return err;
2935}
2936
e98bedf5
EB		 2937static bool csum_offload_supported(struct mlx5e_priv *priv,
2938 u32 action,
2939 u32 update_flags,
2940 struct netlink_ext_ack *extack)
26c02749
OG		 2941{
2942 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2943 TCA_CSUM_UPDATE_FLAG_UDP;
2944
2945 /* The HW recalcs checksums only if re-writing headers */
2946 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2947 NL_SET_ERR_MSG_MOD(extack,
2948 "TC csum action is only offloaded with pedit");
26c02749
OG		 2949 netdev_warn(priv->netdev,
2950 "TC csum action is only offloaded with pedit\n");
2951 return false;
2952 }
2953
2954 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2955 NL_SET_ERR_MSG_MOD(extack,
2956 "can't offload TC csum action for some header/s");
26c02749
OG		 2957 netdev_warn(priv->netdev,
2958 "can't offload TC csum action for some header/s - flags %#x\n",
2959 update_flags);
2960 return false;
2961 }
2962
2963 return true;
2964}
2965
8998576b
DL		 2966struct ip_ttl_word {
2967 __u8 ttl;
2968 __u8 protocol;
2969 __sum16 check;
2970};
2971
2972struct ipv6_hoplimit_word {
2973 __be16 payload_len;
2974 __u8 nexthdr;
2975 __u8 hop_limit;
2976};
2977
4c3844d9
PB		 2978static int is_action_keys_supported(const struct flow_action_entry *act,
2979 bool ct_flow, bool *modify_ip_header,
7e36feeb 2980 bool *modify_tuple,
4c3844d9 2981 struct netlink_ext_ack *extack)
8998576b
DL		 2982{
2983 u32 mask, offset;
2984 u8 htype;
2985
2986 htype = act->mangle.htype;
2987 offset = act->mangle.offset;
2988 mask = ~act->mangle.mask;
2989 /* For IPv4 & IPv6 header check 4 byte word,
2990 * to determine that modified fields
2991 * are NOT ttl & hop_limit only.
2992 */
2993 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2994 struct ip_ttl_word *ttl_word =
2995 (struct ip_ttl_word *)&mask;
2996
2997 if (offset != offsetof(struct iphdr, ttl) ||
2998 ttl_word->protocol ||
2999 ttl_word->check) {
4c3844d9
PB		 3000 *modify_ip_header = true;
3001 }
3002
7e36feeb
PB		 3003 if (offset >= offsetof(struct iphdr, saddr))
3004 *modify_tuple = true;
3005
3006 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3007 NL_SET_ERR_MSG_MOD(extack,
3008 "can't offload re-write of ipv4 address with action ct");
3009 return -EOPNOTSUPP;
8998576b
DL		 3010 }
3011 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3012 struct ipv6_hoplimit_word *hoplimit_word =
3013 (struct ipv6_hoplimit_word *)&mask;
3014
3015 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3016 hoplimit_word->payload_len ||
3017 hoplimit_word->nexthdr) {
4c3844d9
PB		 3018 *modify_ip_header = true;
3019 }
3020
7e36feeb
PB		 3021 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3022 *modify_tuple = true;
3023
3024 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3025 NL_SET_ERR_MSG_MOD(extack,
3026 "can't offload re-write of ipv6 address with action ct");
3027 return -EOPNOTSUPP;
8998576b 3028 }
7e36feeb
PB		 3029 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3030 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3031 *modify_tuple = true;
3032 if (ct_flow) {
3033 NL_SET_ERR_MSG_MOD(extack,
3034 "can't offload re-write of transport header ports with action ct");
3035 return -EOPNOTSUPP;
3036 }
8998576b 3037 }
4c3844d9
PB		 3038
3039 return 0;
8998576b
DL		 3040}
3041
3d486ec4
OS		 3042static bool modify_header_match_supported(struct mlx5e_priv *priv,
3043 struct mlx5_flow_spec *spec,
73867881 3044 struct flow_action *flow_action,
4c3844d9 3045 u32 actions, bool ct_flow,
7e36feeb 3046 bool ct_clear,
e98bedf5 3047 struct netlink_ext_ack *extack)
bdd66ac0 3048{
73867881 3049 const struct flow_action_entry *act;
7e36feeb 3050 bool modify_ip_header, modify_tuple;
fca53304 3051 void *headers_c;
bdd66ac0
OG		 3052 void *headers_v;
3053 u16 ethertype;
8998576b 3054 u8 ip_proto;
4c3844d9 3055 int i, err;
bdd66ac0 3056
fca53304 3057 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3058 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3059 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3060
3061 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3062 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3063 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3064 goto out_ok;
3065
3066 modify_ip_header = false;
7e36feeb 3067 modify_tuple = false;
73867881
PNA		 3068 flow_action_for_each(i, act, flow_action) {
3069 if (act->id != FLOW_ACTION_MANGLE &&
3070 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3071 continue;
3072
4c3844d9 3073 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3074 &modify_ip_header,
3075 &modify_tuple, extack);
4c3844d9
PB		 3076 if (err)
3077 return err;
bdd66ac0
OG		 3078 }
3079
7e36feeb
PB		 3080 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3081 * (or after clear action), as otherwise, since the tuple is changed,
3082 * we can't restore ct state
3083 */
3084 if (!ct_clear && modify_tuple &&
3085 mlx5_tc_ct_add_no_trk_match(priv, spec)) {
3086 NL_SET_ERR_MSG_MOD(extack,
3087 "can't offload tuple modify header with ct matches");
3088 netdev_info(priv->netdev,
3089 "can't offload tuple modify header with ct matches");
3090 return false;
3091 }
3092
bdd66ac0 3093 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3094 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3095 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3096 NL_SET_ERR_MSG_MOD(extack,
3097 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3098 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3099 ip_proto);
bdd66ac0
OG		 3100 return false;
3101 }
3102
3103out_ok:
3104 return true;
3105}
3106
3107static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3108 struct flow_action *flow_action,
bdd66ac0 3109 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3110 struct mlx5e_tc_flow *flow,
3111 struct netlink_ext_ack *extack)
bdd66ac0 3112{
a7c119bd 3113 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3114 u32 actions;
3115
4c3844d9 3116 if (mlx5e_is_eswitch_flow(flow)) {
bdd66ac0 3117 actions = flow->esw_attr->action;
a7c119bd
PB		 3118 ct_clear = flow->esw_attr->ct_attr.ct_action &
3119 TCA_CT_ACT_CLEAR;
3120 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
4c3844d9
PB		 3121 if (flow->esw_attr->split_count && ct_flow) {
3122 /* All registers used by ct are cleared when using
3123 * split rules.
3124 */
3125 NL_SET_ERR_MSG_MOD(extack,
3126 "Can't offload mirroring with action ct");
49397b80 3127 return false;
4c3844d9
PB		 3128 }
3129 } else {
bdd66ac0 3130 actions = flow->nic_attr->action;
4c3844d9 3131 }
bdd66ac0
OG		 3132
3133 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3134 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3135 flow_action, actions,
7e36feeb
PB		 3136 ct_flow, ct_clear,
3137 extack);
bdd66ac0
OG		 3138
3139 return true;
3140}
3141
32134847
MD		 3142static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3143{
3144 return priv->mdev == peer_priv->mdev;
3145}
3146
5c65c564
OG		 3147static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3148{
3149 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3150 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3151
3152 fmdev = priv->mdev;
3153 pmdev = peer_priv->mdev;
3154
59c9d35e
AH		 3155 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3156 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3157
816f6706 3158 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3159}
3160
bdc837ee
EB		 3161static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3162 const struct flow_action_entry *act,
3163 struct mlx5e_tc_flow_parse_attr *parse_attr,
3164 struct pedit_headers_action *hdrs,
3165 u32 *action, struct netlink_ext_ack *extack)
3166{
3167 u16 mask16 = VLAN_VID_MASK;
3168 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3169 const struct flow_action_entry pedit_act = {
3170 .id = FLOW_ACTION_MANGLE,
3171 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3172 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3173 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3174 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3175 };
6fca9d1e 3176 u8 match_prio_mask, match_prio_val;
bf2f3bca 3177 void *headers_c, *headers_v;
bdc837ee
EB		 3178 int err;
3179
bf2f3bca
EB		 3180 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3181 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3182
3183 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3184 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3185 NL_SET_ERR_MSG_MOD(extack,
3186 "VLAN rewrite action must have VLAN protocol match");
3187 return -EOPNOTSUPP;
3188 }
3189
6fca9d1e
EB		 3190 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3191 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3192 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3193 NL_SET_ERR_MSG_MOD(extack,
3194 "Changing VLAN prio is not supported");
bdc837ee
EB		 3195 return -EOPNOTSUPP;
3196 }
3197
582234b4 3198 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3199 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3200
3201 return err;
3202}
3203
0bac1194
EB		 3204static int
3205add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3206 struct mlx5e_tc_flow_parse_attr *parse_attr,
3207 struct pedit_headers_action *hdrs,
3208 u32 *action, struct netlink_ext_ack *extack)
3209{
3210 const struct flow_action_entry prio_tag_act = {
3211 .vlan.vid = 0,
3212 .vlan.prio =
3213 MLX5_GET(fte_match_set_lyr_2_4,
3214 get_match_headers_value(*action,
3215 &parse_attr->spec),
3216 first_prio) &
3217 MLX5_GET(fte_match_set_lyr_2_4,
3218 get_match_headers_criteria(*action,
3219 &parse_attr->spec),
3220 first_prio),
3221 };
3222
3223 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3224 &prio_tag_act, parse_attr, hdrs, action,
3225 extack);
3226}
3227
73867881
PNA		 3228static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3229 struct flow_action *flow_action,
aa0cbbae 3230 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3231 struct mlx5e_tc_flow *flow,
3232 struct netlink_ext_ack *extack)
e3a2b7ed 3233{
aa0cbbae 3234 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 3235 struct pedit_headers_action hdrs[2] = {};
3236 const struct flow_action_entry *act;
1cab1cd7 3237 u32 action = 0;
244cd96a 3238 int err, i;
e3a2b7ed 3239
73867881 3240 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3241 return -EINVAL;
3242
53eca1f3
JK		 3243 if (!flow_action_hw_stats_check(flow_action, extack,
3244 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3245 return -EOPNOTSUPP;
3246
3bc4b7bf 3247 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3248
73867881
PNA		 3249 flow_action_for_each(i, act, flow_action) {
3250 switch (act->id) {
15fc92ec
TZ		 3251 case FLOW_ACTION_ACCEPT:
3252 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3253 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3254 break;
73867881 3255 case FLOW_ACTION_DROP:
1cab1cd7 3256 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3257 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3258 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3259 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3260 break;
3261 case FLOW_ACTION_MANGLE:
3262 case FLOW_ACTION_ADD:
3263 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3264 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3265 if (err)
3266 return err;
3267
1cab1cd7
OG		 3268 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
3269 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 3270 break;
bdc837ee
EB		 3271 case FLOW_ACTION_VLAN_MANGLE:
3272 err = add_vlan_rewrite_action(priv,
3273 MLX5_FLOW_NAMESPACE_KERNEL,
3274 act, parse_attr, hdrs,
3275 &action, extack);
3276 if (err)
3277 return err;
3278
3279 break;
73867881 3280 case FLOW_ACTION_CSUM:
1cab1cd7 3281 if (csum_offload_supported(priv, action,
73867881 3282 act->csum_flags,
e98bedf5 3283 extack))
73867881 3284 break;
26c02749
OG		 3285
3286 return -EOPNOTSUPP;
73867881
PNA		 3287 case FLOW_ACTION_REDIRECT: {
3288 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3289
3290 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3291 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3292 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3293 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3294 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3295 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3296 } else {
e98bedf5
EB		 3297 NL_SET_ERR_MSG_MOD(extack,
3298 "device is not on same HW, can't offload");
5c65c564
OG		 3299 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3300 peer_dev->name);
3301 return -EINVAL;
3302 }
73867881
PNA		 3303 }
3304 break;
3305 case FLOW_ACTION_MARK: {
3306 u32 mark = act->mark;
e3a2b7ed
AV		 3307
3308 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3309 NL_SET_ERR_MSG_MOD(extack,
3310 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3311 return -EINVAL;
3312 }
3313
3bc4b7bf 3314 attr->flow_tag = mark;
1cab1cd7 3315 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3316 }
3317 break;
3318 default:
2cc1cb1d
TZ		 3319 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3320 return -EOPNOTSUPP;
e3a2b7ed 3321 }
e3a2b7ed
AV		 3322 }
3323
c500c86b
PNA		 3324 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3325 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3326 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3327 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3328 if (err)
3329 return err;
27c11b6b
EB		 3330 /* in case all pedit actions are skipped, remove the MOD_HDR
3331 * flag.
3332 */
6ae4a6a5 3333 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3334 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3335 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3336 }
c500c86b
PNA		 3337 }
3338
1cab1cd7 3339 attr->action = action;
73867881 3340 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3341 return -EOPNOTSUPP;
3342
e3a2b7ed
AV		 3343 return 0;
3344}
3345
7f1a546e 3346struct encap_key {
1f6da306 3347 const struct ip_tunnel_key *ip_tun_key;
d386939a 3348 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3349};
3350
3351static inline int cmp_encap_info(struct encap_key *a,
3352 struct encap_key *b)
a54e20b4 3353{
7f1a546e 3354 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3355 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3356}
3357
14e6b038
EC		 3358static inline int cmp_decap_info(struct mlx5e_decap_key *a,
3359 struct mlx5e_decap_key *b)
3360{
3361 return memcmp(&a->key, &b->key, sizeof(b->key));
3362}
3363
7f1a546e 3364static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3365{
7f1a546e 3366 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3367 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3368}
3369
14e6b038
EC		 3370static inline int hash_decap_info(struct mlx5e_decap_key *key)
3371{
3372 return jhash(&key->key, sizeof(key->key), 0);
3373}
a54e20b4 3374
32134847 3375static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3376 struct net_device *peer_netdev)
3377{
3378 struct mlx5e_priv *peer_priv;
3379
3380 peer_priv = netdev_priv(peer_netdev);
3381
3382 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3383 mlx5e_eswitch_vf_rep(priv->netdev) &&
3384 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3385 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3386}
3387
948993f2
VB		 3388bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3389{
3390 return refcount_inc_not_zero(&e->refcnt);
3391}
3392
14e6b038
EC		 3393static bool mlx5e_decap_take(struct mlx5e_decap_entry *e)
3394{
3395 return refcount_inc_not_zero(&e->refcnt);
3396}
3397
948993f2
VB		 3398static struct mlx5e_encap_entry *
3399mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3400 uintptr_t hash_key)
3401{
3402 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3403 struct mlx5e_encap_entry *e;
3404 struct encap_key e_key;
3405
3406 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3407 encap_hlist, hash_key) {
3408 e_key.ip_tun_key = &e->tun_info->key;
3409 e_key.tc_tunnel = e->tunnel;
3410 if (!cmp_encap_info(&e_key, key) &&
3411 mlx5e_encap_take(e))
3412 return e;
3413 }
3414
3415 return NULL;
3416}
3417
14e6b038
EC		 3418static struct mlx5e_decap_entry *
3419mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key,
3420 uintptr_t hash_key)
3421{
3422 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3423 struct mlx5e_decap_key r_key;
3424 struct mlx5e_decap_entry *e;
3425
3426 hash_for_each_possible_rcu(esw->offloads.decap_tbl, e,
3427 hlist, hash_key) {
3428 r_key = e->key;
3429 if (!cmp_decap_info(&r_key, key) &&
3430 mlx5e_decap_take(e))
3431 return e;
3432 }
3433 return NULL;
3434}
3435
2a4b6526
VB		 3436static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3437{
3438 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3439
3440 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3441}
3442
554fe75c
DL		 3443static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3444 struct mlx5e_tc_flow *flow,
3445 int out_index,
3446 struct mlx5e_encap_entry *e,
3447 struct netlink_ext_ack *extack)
3448{
3449 int i;
3450
3451 for (i = 0; i < out_index; i++) {
3452 if (flow->encaps[i].e != e)
3453 continue;
3454 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3455 netdev_err(priv->netdev, "can't duplicate encap action\n");
3456 return true;
3457 }
3458
3459 return false;
3460}
3461
a54e20b4 3462static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3463 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3464 struct net_device *mirred_dev,
3465 int out_index,
8c4dc42b 3466 struct netlink_ext_ack *extack,
0ad060ee
RD		 3467 struct net_device **encap_dev,
3468 bool *encap_valid)
a54e20b4
HHZ		 3469{
3470 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3471 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3472 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3473 const struct ip_tunnel_info *tun_info;
948993f2 3474 struct encap_key key;
c1ae1152 3475 struct mlx5e_encap_entry *e;
733d4f36 3476 unsigned short family;
a54e20b4 3477 uintptr_t hash_key;
54c177ca 3478 int err = 0;
a54e20b4 3479
733d4f36 3480 parse_attr = attr->parse_attr;
1f6da306 3481 tun_info = parse_attr->tun_info[out_index];
733d4f36 3482 family = ip_tunnel_info_af(tun_info);
7f1a546e 3483 key.ip_tun_key = &tun_info->key;
d386939a 3484 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3485 if (!key.tc_tunnel) {
3486 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3487 return -EOPNOTSUPP;
3488 }
733d4f36 3489
7f1a546e 3490 hash_key = hash_encap_info(&key);
a54e20b4 3491
61086f39 3492 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3493 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3494
b2812089 3495 /* must verify if encap is valid or not */
d589e785 3496 if (e) {
554fe75c
DL		 3497 /* Check that entry was not already attached to this flow */
3498 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3499 err = -EOPNOTSUPP;
3500 goto out_err;
3501 }
3502
d589e785
VB		 3503 mutex_unlock(&esw->offloads.encap_tbl_lock);
3504 wait_for_completion(&e->res_ready);
3505
3506 /* Protect against concurrent neigh update. */
3507 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3508 if (e->compl_result < 0) {
d589e785
VB		 3509 err = -EREMOTEIO;
3510 goto out_err;
3511 }
45247bf2 3512 goto attach_flow;
d589e785 3513 }
a54e20b4
HHZ		 3514
3515 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3516 if (!e) {
3517 err = -ENOMEM;
3518 goto out_err;
3519 }
a54e20b4 3520
948993f2 3521 refcount_set(&e->refcnt, 1);
d589e785
VB		 3522 init_completion(&e->res_ready);
3523
2a4b6526
VB		 3524 tun_info = dup_tun_info(tun_info);
3525 if (!tun_info) {
3526 err = -ENOMEM;
3527 goto out_err_init;
3528 }
1f6da306 3529 e->tun_info = tun_info;
101f4de9 3530 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3531 if (err)
3532 goto out_err_init;
54c177ca 3533
a54e20b4 3534 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3535 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3536 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3537
ce99f6b9 3538 if (family == AF_INET)
101f4de9 3539 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3540 else if (family == AF_INET6)
101f4de9 3541 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3542
d589e785
VB		 3543 /* Protect against concurrent neigh update. */
3544 mutex_lock(&esw->offloads.encap_tbl_lock);
3545 complete_all(&e->res_ready);
3546 if (err) {
3547 e->compl_result = err;
a54e20b4 3548 goto out_err;
d589e785 3549 }
3c140dd5 3550 e->compl_result = 1;
a54e20b4 3551
45247bf2 3552attach_flow:
948993f2 3553 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3554 list_add(&flow->encaps[out_index].list, &e->flows);
3555 flow->encaps[out_index].index = out_index;
45247bf2 3556 *encap_dev = e->out_dev;
8c4dc42b 3557 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3558 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3559 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3560 *encap_valid = true;
8c4dc42b 3561 } else {
0ad060ee 3562 *encap_valid = false;
8c4dc42b 3563 }
61086f39 3564 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3565
232c0013 3566 return err;
a54e20b4
HHZ		 3567
3568out_err:
61086f39 3569 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3570 if (e)
3571 mlx5e_encap_put(priv, e);
a54e20b4 3572 return err;
2a4b6526
VB		 3573
3574out_err_init:
3575 mutex_unlock(&esw->offloads.encap_tbl_lock);
3576 kfree(tun_info);
3577 kfree(e);
3578 return err;
a54e20b4
HHZ		 3579}
3580
14e6b038
EC		 3581static int mlx5e_attach_decap(struct mlx5e_priv *priv,
3582 struct mlx5e_tc_flow *flow,
3583 struct netlink_ext_ack *extack)
3584{
3585 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3586 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3587 struct mlx5e_tc_flow_parse_attr *parse_attr;
3588 struct mlx5e_decap_entry *d;
3589 struct mlx5e_decap_key key;
3590 uintptr_t hash_key;
28619046 3591 int err = 0;
14e6b038
EC		 3592
3593 parse_attr = attr->parse_attr;
3594 if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {
3595 NL_SET_ERR_MSG_MOD(extack,
3596 "encap header larger than max supported");
3597 return -EOPNOTSUPP;
3598 }
3599
3600 key.key = parse_attr->eth;
3601 hash_key = hash_decap_info(&key);
3602 mutex_lock(&esw->offloads.decap_tbl_lock);
3603 d = mlx5e_decap_get(priv, &key, hash_key);
3604 if (d) {
3605 mutex_unlock(&esw->offloads.decap_tbl_lock);
3606 wait_for_completion(&d->res_ready);
3607 mutex_lock(&esw->offloads.decap_tbl_lock);
3608 if (d->compl_result) {
3609 err = -EREMOTEIO;
3610 goto out_free;
3611 }
3612 goto found;
3613 }
3614
3615 d = kzalloc(sizeof(*d), GFP_KERNEL);
3616 if (!d) {
3617 err = -ENOMEM;
3618 goto out_err;
3619 }
3620
3621 d->key = key;
3622 refcount_set(&d->refcnt, 1);
3623 init_completion(&d->res_ready);
3624 INIT_LIST_HEAD(&d->flows);
3625 hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key);
3626 mutex_unlock(&esw->offloads.decap_tbl_lock);
3627
3628 d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
3629 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2,
3630 sizeof(parse_attr->eth),
3631 &parse_attr->eth,
3632 MLX5_FLOW_NAMESPACE_FDB);
3633 if (IS_ERR(d->pkt_reformat)) {
3634 err = PTR_ERR(d->pkt_reformat);
3635 d->compl_result = err;
3636 }
3637 mutex_lock(&esw->offloads.decap_tbl_lock);
3638 complete_all(&d->res_ready);
3639 if (err)
3640 goto out_free;
3641
3642found:
3643 flow->decap_reformat = d;
3644 attr->decap_pkt_reformat = d->pkt_reformat;
3645 list_add(&flow->l3_to_l2_reformat, &d->flows);
3646 mutex_unlock(&esw->offloads.decap_tbl_lock);
3647 return 0;
3648
3649out_free:
3650 mutex_unlock(&esw->offloads.decap_tbl_lock);
3651 mlx5e_decap_put(priv, d);
3652 return err;
3653
3654out_err:
3655 mutex_unlock(&esw->offloads.decap_tbl_lock);
3656 return err;
3657}
3658
1482bd3d 3659static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3660 const struct flow_action_entry *act,
1482bd3d
JL		 3661 struct mlx5_esw_flow_attr *attr,
3662 u32 *action)
3663{
cc495188
JL		 3664 u8 vlan_idx = attr->total_vlan;
3665
3666 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3667 return -EOPNOTSUPP;
3668
73867881
PNA		 3669 switch (act->id) {
3670 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3671 if (vlan_idx) {
3672 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3673 MLX5_FS_VLAN_DEPTH))
3674 return -EOPNOTSUPP;
3675
3676 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3677 } else {
3678 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3679 }
73867881
PNA		 3680 break;
3681 case FLOW_ACTION_VLAN_PUSH:
3682 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3683 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3684 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3685 if (!attr->vlan_proto[vlan_idx])
3686 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3687
3688 if (vlan_idx) {
3689 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3690 MLX5_FS_VLAN_DEPTH))
3691 return -EOPNOTSUPP;
3692
3693 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3694 } else {
3695 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3696 (act->vlan.proto != htons(ETH_P_8021Q) ||
3697 act->vlan.prio))
cc495188
JL		 3698 return -EOPNOTSUPP;
3699
3700 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3701 }
73867881
PNA		 3702 break;
3703 default:
bdc837ee 3704 return -EINVAL;
1482bd3d
JL		 3705 }
3706
cc495188
JL		 3707 attr->total_vlan = vlan_idx + 1;
3708
1482bd3d
JL		 3709 return 0;
3710}
3711
d34eb2fc
OG		 3712static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3713 struct net_device *out_dev)
3714{
3715 struct net_device *fdb_out_dev = out_dev;
3716 struct net_device *uplink_upper;
3717
3718 rcu_read_lock();
3719 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3720 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3721 uplink_upper == out_dev) {
3722 fdb_out_dev = uplink_dev;
3723 } else if (netif_is_lag_master(out_dev)) {
3724 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3725 if (fdb_out_dev &&
3726 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3727 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3728 fdb_out_dev = NULL;
3729 }
3730 rcu_read_unlock();
3731 return fdb_out_dev;
3732}
3733
278748a9
EB		 3734static int add_vlan_push_action(struct mlx5e_priv *priv,
3735 struct mlx5_esw_flow_attr *attr,
3736 struct net_device **out_dev,
3737 u32 *action)
3738{
3739 struct net_device *vlan_dev = *out_dev;
3740 struct flow_action_entry vlan_act = {
3741 .id = FLOW_ACTION_VLAN_PUSH,
3742 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3743 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3744 .vlan.prio = 0,
3745 };
3746 int err;
3747
3748 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3749 if (err)
3750 return err;
3751
3752 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3753 dev_get_iflink(vlan_dev));
3754 if (is_vlan_dev(*out_dev))
3755 err = add_vlan_push_action(priv, attr, out_dev, action);
3756
3757 return err;
3758}
3759
35a605db
EB		 3760static int add_vlan_pop_action(struct mlx5e_priv *priv,
3761 struct mlx5_esw_flow_attr *attr,
3762 u32 *action)
3763{
35a605db
EB		 3764 struct flow_action_entry vlan_act = {
3765 .id = FLOW_ACTION_VLAN_POP,
3766 };
70f478ca 3767 int nest_level, err = 0;
35a605db 3768
70f478ca
DL		 3769 nest_level = attr->parse_attr->filter_dev->lower_level -
3770 priv->netdev->lower_level;
35a605db
EB		 3771 while (nest_level--) {
3772 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3773 if (err)
3774 return err;
3775 }
3776
3777 return err;
3778}
3779
32134847
MD		 3780static bool same_hw_reps(struct mlx5e_priv *priv,
3781 struct net_device *peer_netdev)
3782{
3783 struct mlx5e_priv *peer_priv;
3784
3785 peer_priv = netdev_priv(peer_netdev);
3786
3787 return mlx5e_eswitch_rep(priv->netdev) &&
3788 mlx5e_eswitch_rep(peer_netdev) &&
3789 same_hw_devs(priv, peer_priv);
3790}
3791
3792static bool is_lag_dev(struct mlx5e_priv *priv,
3793 struct net_device *peer_netdev)
3794{
3795 return ((mlx5_lag_is_sriov(priv->mdev) ||
3796 mlx5_lag_is_multipath(priv->mdev)) &&
3797 same_hw_reps(priv, peer_netdev));
3798}
3799
f6dc1264
PB		 3800bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3801 struct net_device *out_dev)
3802{
32134847
MD		 3803 if (is_merged_eswitch_vfs(priv, out_dev))
3804 return true;
3805
3806 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3807 return true;
3808
3809 return mlx5e_eswitch_rep(out_dev) &&
32134847 3810 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3811}
3812
554fe75c
DL		 3813static bool is_duplicated_output_device(struct net_device *dev,
3814 struct net_device *out_dev,
3815 int *ifindexes, int if_count,
3816 struct netlink_ext_ack *extack)
3817{
3818 int i;
3819
3820 for (i = 0; i < if_count; i++) {
3821 if (ifindexes[i] == out_dev->ifindex) {
3822 NL_SET_ERR_MSG_MOD(extack,
3823 "can't duplicate output to same device");
3824 netdev_err(dev, "can't duplicate output to same device: %s\n",
3825 out_dev->name);
3826 return true;
3827 }
3828 }
3829
3830 return false;
3831}
3832
2fbbc30d
EC		 3833static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3834 struct mlx5e_tc_flow *flow,
3835 const struct flow_action_entry *act,
3836 u32 actions,
3837 struct netlink_ext_ack *extack)
3838{
3839 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3840 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3841 bool ft_flow = mlx5e_is_ft_flow(flow);
3842 u32 dest_chain = act->chain_index;
3843
3844 if (ft_flow) {
3845 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3846 return -EOPNOTSUPP;
3847 }
3848
3849 if (!mlx5_esw_chains_backwards_supported(esw) &&
3850 dest_chain <= attr->chain) {
3851 NL_SET_ERR_MSG_MOD(extack,
3852 "Goto lower numbered chain isn't supported");
3853 return -EOPNOTSUPP;
3854 }
3855 if (dest_chain > max_chain) {
3856 NL_SET_ERR_MSG_MOD(extack,
3857 "Requested destination chain is out of supported range");
3858 return -EOPNOTSUPP;
3859 }
3860
3861 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3862 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3863 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3864 NL_SET_ERR_MSG_MOD(extack,
3865 "Goto chain is not allowed if action has reformat or decap");
3866 return -EOPNOTSUPP;
3867 }
3868
3869 return 0;
3870}
3871
613f53fe
EC		 3872static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3873 struct mlx5e_tc_flow *flow,
3874 struct net_device *out_dev,
3875 struct netlink_ext_ack *extack)
3876{
3877 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3878 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3879 struct mlx5e_rep_priv *rep_priv;
3880
3881 /* Forwarding non encapsulated traffic between
3882 * uplink ports is allowed only if
3883 * termination_table_raw_traffic cap is set.
3884 *
3885 * Input vport was stored esw_attr->in_rep.
3886 * In LAG case, *priv* is the private data of
3887 * uplink which may be not the input vport.
3888 */
3889 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3890
3891 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3892 mlx5e_eswitch_uplink_rep(out_dev)))
3893 return 0;
3894
3895 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3896 termination_table_raw_traffic)) {
3897 NL_SET_ERR_MSG_MOD(extack,
3898 "devices are both uplink, can't offload forwarding");
3899 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3900 priv->netdev->name, out_dev->name);
3901 return -EOPNOTSUPP;
3902 } else if (out_dev != rep_priv->netdev) {
3903 NL_SET_ERR_MSG_MOD(extack,
3904 "devices are not the same uplink, can't offload forwarding");
3905 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3906 priv->netdev->name, out_dev->name);
3907 return -EOPNOTSUPP;
3908 }
3909 return 0;
3910}
3911
73867881
PNA		 3912static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3913 struct flow_action *flow_action,
e98bedf5 3914 struct mlx5e_tc_flow *flow,
14e6b038
EC		 3915 struct netlink_ext_ack *extack,
3916 struct net_device *filter_dev)
03a9d11e 3917{
73867881 3918 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3919 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3920 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3921 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3922 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3923 const struct ip_tunnel_info *info = NULL;
554fe75c 3924 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3925 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3926 const struct flow_action_entry *act;
0a7fcb78
PB		 3927 bool encap = false, decap = false;
3928 u32 action = attr->action;
554fe75c 3929 int err, i, if_count = 0;
f828ca6a 3930 bool mpls_push = false;
03a9d11e 3931
73867881 3932 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3933 return -EINVAL;
3934
53eca1f3
JK		 3935 if (!flow_action_hw_stats_check(flow_action, extack,
3936 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3937 return -EOPNOTSUPP;
3938
73867881
PNA		 3939 flow_action_for_each(i, act, flow_action) {
3940 switch (act->id) {
3941 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3942 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3943 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3944 break;
f828ca6a
EC		 3945 case FLOW_ACTION_MPLS_PUSH:
3946 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3947 reformat_l2_to_l3_tunnel) ||
3948 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3949 NL_SET_ERR_MSG_MOD(extack,
3950 "mpls push is supported only for mpls_uc protocol");
3951 return -EOPNOTSUPP;
3952 }
3953 mpls_push = true;
3954 break;
14e6b038
EC		 3955 case FLOW_ACTION_MPLS_POP:
3956 /* we only support mpls pop if it is the first action
3957 * and the filter net device is bareudp. Subsequent
3958 * actions can be pedit and the last can be mirred
3959 * egress redirect.
3960 */
3961 if (i) {
3962 NL_SET_ERR_MSG_MOD(extack,
3963 "mpls pop supported only as first action");
3964 return -EOPNOTSUPP;
3965 }
3966 if (!netif_is_bareudp(filter_dev)) {
3967 NL_SET_ERR_MSG_MOD(extack,
3968 "mpls pop supported only on bareudp devices");
3969 return -EOPNOTSUPP;
3970 }
3971
3972 parse_attr->eth.h_proto = act->mpls_pop.proto;
3973 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3974 flow_flag_set(flow, L3_TO_L2_DECAP);
3975 break;
73867881
PNA		 3976 case FLOW_ACTION_MANGLE:
3977 case FLOW_ACTION_ADD:
3978 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3979 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3980 if (err)
3981 return err;
3982
582234b4
EC		 3983 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3984 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3985 attr->split_count = attr->out_count;
3986 }
73867881
PNA		 3987 break;
3988 case FLOW_ACTION_CSUM:
1cab1cd7 3989 if (csum_offload_supported(priv, action,
73867881
PNA		 3990 act->csum_flags, extack))
3991 break;
26c02749
OG		 3992
3993 return -EOPNOTSUPP;
73867881
PNA		 3994 case FLOW_ACTION_REDIRECT:
3995 case FLOW_ACTION_MIRRED: {
03a9d11e 3996 struct mlx5e_priv *out_priv;
592d3651 3997 struct net_device *out_dev;
03a9d11e 3998
73867881 3999 out_dev = act->dev;
ef381359
OS		 4000 if (!out_dev) {
4001 /* out_dev is NULL when filters with
4002 * non-existing mirred device are replayed to
4003 * the driver.
4004 */
4005 return -EINVAL;
4006 }
03a9d11e 4007
f828ca6a
EC		 4008 if (mpls_push && !netif_is_bareudp(out_dev)) {
4009 NL_SET_ERR_MSG_MOD(extack,
4010 "mpls is supported only through a bareudp device");
4011 return -EOPNOTSUPP;
4012 }
4013
84179981
PB		 4014 if (ft_flow && out_dev == priv->netdev) {
4015 /* Ignore forward to self rules generated
4016 * by adding both mlx5 devs to the flow table
4017 * block on a normal nft offload setup.
4018 */
4019 return -EOPNOTSUPP;
4020 }
4021
592d3651 4022 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 4023 NL_SET_ERR_MSG_MOD(extack,
4024 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 4025 netdev_warn(priv->netdev,
4026 "can't support more than %d output ports, can't offload forwarding\n",
4027 attr->out_count);
592d3651
CM		 4028 return -EOPNOTSUPP;
4029 }
4030
f493f155
EB		 4031 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4032 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 4033 if (encap) {
4034 parse_attr->mirred_ifindex[attr->out_count] =
4035 out_dev->ifindex;
4036 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
4037 if (!parse_attr->tun_info[attr->out_count])
4038 return -ENOMEM;
4039 encap = false;
4040 attr->dests[attr->out_count].flags |=
4041 MLX5_ESW_DEST_ENCAP;
4042 attr->out_count++;
4043 /* attr->dests[].rep is resolved when we
4044 * handle encap
4045 */
4046 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 4047 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4048 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 4049
554fe75c
DL		 4050 if (is_duplicated_output_device(priv->netdev,
4051 out_dev,
4052 ifindexes,
4053 if_count,
4054 extack))
4055 return -EOPNOTSUPP;
4056
4057 ifindexes[if_count] = out_dev->ifindex;
4058 if_count++;
4059
d34eb2fc
OG		 4060 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4061 if (!out_dev)
4062 return -ENODEV;
7ba58ba7 4063
278748a9
EB		 4064 if (is_vlan_dev(out_dev)) {
4065 err = add_vlan_push_action(priv, attr,
4066 &out_dev,
4067 &action);
4068 if (err)
4069 return err;
4070 }
f6dc1264 4071
35a605db
EB		 4072 if (is_vlan_dev(parse_attr->filter_dev)) {
4073 err = add_vlan_pop_action(priv, attr,
4074 &action);
4075 if (err)
4076 return err;
4077 }
278748a9 4078
613f53fe
EC		 4079 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4080 if (err)
4081 return err;
ffec9702 4082
f6dc1264
PB		 4083 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4084 NL_SET_ERR_MSG_MOD(extack,
4085 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4086 return -EOPNOTSUPP;
f6dc1264 4087 }
a0646c88 4088
a54e20b4 4089 out_priv = netdev_priv(out_dev);
1d447a39 4090 rpriv = out_priv->ppriv;
df65a573
EB		 4091 attr->dests[attr->out_count].rep = rpriv->rep;
4092 attr->dests[attr->out_count].mdev = out_priv->mdev;
4093 attr->out_count++;
ef381359
OS		 4094 } else if (parse_attr->filter_dev != priv->netdev) {
4095 /* All mlx5 devices are called to configure
4096 * high level device filters. Therefore, the
4097 * *attempt* to install a filter on invalid
4098 * eswitch should not trigger an explicit error
4099 */
4100 return -EINVAL;
a54e20b4 4101 } else {
e98bedf5
EB		 4102 NL_SET_ERR_MSG_MOD(extack,
4103 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4104 netdev_warn(priv->netdev,
4105 "devices %s %s not on same switch HW, can't offload forwarding\n",
4106 priv->netdev->name,
4107 out_dev->name);
03a9d11e
OG		 4108 return -EINVAL;
4109 }
73867881
PNA		 4110 }
4111 break;
4112 case FLOW_ACTION_TUNNEL_ENCAP:
4113 info = act->tunnel;
a54e20b4
HHZ		 4114 if (info)
4115 encap = true;
4116 else
4117 return -EOPNOTSUPP;
1482bd3d 4118
73867881
PNA		 4119 break;
4120 case FLOW_ACTION_VLAN_PUSH:
4121 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4122 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4123 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4124 /* Replace vlan pop+push with vlan modify */
4125 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4126 err = add_vlan_rewrite_action(priv,
4127 MLX5_FLOW_NAMESPACE_FDB,
4128 act, parse_attr, hdrs,
4129 &action, extack);
4130 } else {
4131 err = parse_tc_vlan_action(priv, act, attr, &action);
4132 }
1482bd3d
JL		 4133 if (err)
4134 return err;
4135
bdc837ee
EB		 4136 attr->split_count = attr->out_count;
4137 break;
4138 case FLOW_ACTION_VLAN_MANGLE:
4139 err = add_vlan_rewrite_action(priv,
4140 MLX5_FLOW_NAMESPACE_FDB,
4141 act, parse_attr, hdrs,
4142 &action, extack);
4143 if (err)
4144 return err;
4145
e85e02ba 4146 attr->split_count = attr->out_count;
73867881
PNA		 4147 break;
4148 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4149 decap = true;
73867881 4150 break;
2fbbc30d
EC		 4151 case FLOW_ACTION_GOTO:
4152 err = mlx5_validate_goto_chain(esw, flow, act, action,
4153 extack);
4154 if (err)
4155 return err;
bf07aa73 4156
e88afe75 4157 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4158 attr->dest_chain = act->chain_index;
73867881 4159 break;
4c3844d9
PB		 4160 case FLOW_ACTION_CT:
4161 err = mlx5_tc_ct_parse_action(priv, attr, act, extack);
4162 if (err)
4163 return err;
4164
4165 flow_flag_set(flow, CT);
4166 break;
73867881 4167 default:
2cc1cb1d
TZ		 4168 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4169 return -EOPNOTSUPP;
bf07aa73 4170 }
03a9d11e 4171 }
bdd66ac0 4172
0bac1194
EB		 4173 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4174 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4175 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4176 * tag rewrite.
4177 */
4178 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4179 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4180 &action, extack);
4181 if (err)
4182 return err;
4183 }
4184
c500c86b
PNA		 4185 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4186 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4187 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4188 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4189 if (err)
4190 return err;
27c11b6b
EB		 4191 /* in case all pedit actions are skipped, remove the MOD_HDR
4192 * flag. we might have set split_count either by pedit or
4193 * pop/push. if there is no pop/push either, reset it too.
4194 */
6ae4a6a5 4195 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4196 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4197 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4198 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4199 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
4200 attr->split_count = 0;
4201 }
c500c86b
PNA		 4202 }
4203
1cab1cd7 4204 attr->action = action;
73867881 4205 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4206 return -EOPNOTSUPP;
4207
e88afe75 4208 if (attr->dest_chain) {
0a7fcb78
PB		 4209 if (decap) {
4210 /* It can be supported if we'll create a mapping for
4211 * the tunnel device only (without tunnel), and set
4212 * this tunnel id with this decap flow.
4213 *
4214 * On restore (miss), we'll just set this saved tunnel
4215 * device.
4216 */
4217
4218 NL_SET_ERR_MSG(extack,
4219 "Decap with goto isn't supported");
4220 netdev_warn(priv->netdev,
4221 "Decap with goto isn't supported");
4222 return -EOPNOTSUPP;
4223 }
4224
e88afe75 4225 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 4226 NL_SET_ERR_MSG_MOD(extack,
4227 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 4228 return -EOPNOTSUPP;
4229 }
4230 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4231 }
4232
ae2741e2
VB		 4233 if (!(attr->action &
4234 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4235 NL_SET_ERR_MSG_MOD(extack,
4236 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4237 return -EOPNOTSUPP;
4238 }
4239
e85e02ba 4240 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4241 NL_SET_ERR_MSG_MOD(extack,
4242 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4243 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4244 return -EOPNOTSUPP;
4245 }
4246
31c8eba5 4247 return 0;
03a9d11e
OG		 4248}
4249
226f2ca3 4250static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4251{
226f2ca3 4252 unsigned long __flow_flags = 0;
60bd4af8 4253
226f2ca3
VB		 4254 if (flags & MLX5_TC_FLAG(INGRESS))
4255 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4256 if (flags & MLX5_TC_FLAG(EGRESS))
4257 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4258
226f2ca3
VB		 4259 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4260 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4261 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4262 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4263 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4264 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4265
60bd4af8
OG		 4266 *flow_flags = __flow_flags;
4267}
4268
05866c82
OG		 4269static const struct rhashtable_params tc_ht_params = {
4270 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4271 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4272 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4273 .automatic_shrinking = true,
4274};
4275
226f2ca3
VB		 4276static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4277 unsigned long flags)
05866c82 4278{
655dc3d2
OG		 4279 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4280 struct mlx5e_rep_priv *uplink_rpriv;
4281
226f2ca3 4282 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4283 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4284 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4285 } else /* NIC offload */
655dc3d2 4286 return &priv->fs.tc.ht;
05866c82
OG		 4287}
4288
04de7dda
RD		 4289static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4290{
1418ddd9 4291 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 4292 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4293 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4294 bool act_is_encap = !!(attr->action &
4295 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4296 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
4297 MLX5_DEVCOM_ESW_OFFLOADS);
4298
10fbb1cd
RD		 4299 if (!esw_paired)
4300 return false;
4301
4302 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
4303 mlx5_lag_is_multipath(attr->in_mdev)) &&
4304 (is_rep_ingress || act_is_encap))
4305 return true;
4306
4307 return false;
04de7dda
RD		 4308}
4309
a88780a9
RD		 4310static int
4311mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4312 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4313 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4314 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4315{
17091853 4316 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 4317 struct mlx5e_tc_flow *flow;
5a7e5bcb 4318 int out_index, err;
e3a2b7ed 4319
65ba8fb7 4320 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 4321 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 4322 if (!parse_attr || !flow) {
e3a2b7ed
AV		 4323 err = -ENOMEM;
4324 goto err_free;
4325 }
4326
4327 flow->cookie = f->cookie;
65ba8fb7 4328 flow->flags = flow_flags;
655dc3d2 4329 flow->priv = priv;
5a7e5bcb
VB		 4330 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4331 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4332 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4333 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4334 refcount_set(&flow->refcnt, 1);
95435ad7 4335 init_completion(&flow->init_done);
e3a2b7ed 4336
a88780a9
RD		 4337 *__flow = flow;
4338 *__parse_attr = parse_attr;
4339
4340 return 0;
4341
4342err_free:
4343 kfree(flow);
4344 kvfree(parse_attr);
4345 return err;
4346}
4347
988ab9c7
TZ		 4348static void
4349mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
4350 struct mlx5e_priv *priv,
4351 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4352 struct flow_cls_offload *f,
988ab9c7
TZ		 4353 struct mlx5_eswitch_rep *in_rep,
4354 struct mlx5_core_dev *in_mdev)
4355{
4356 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4357
4358 esw_attr->parse_attr = parse_attr;
4359 esw_attr->chain = f->common.chain_index;
ef01adae 4360 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 4361
4362 esw_attr->in_rep = in_rep;
4363 esw_attr->in_mdev = in_mdev;
4364
4365 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4366 MLX5_COUNTER_SOURCE_ESWITCH)
4367 esw_attr->counter_dev = in_mdev;
4368 else
4369 esw_attr->counter_dev = priv->mdev;
4370}
4371
71129676 4372static struct mlx5e_tc_flow *
04de7dda 4373__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4374 struct flow_cls_offload *f,
226f2ca3 4375 unsigned long flow_flags,
04de7dda
RD		 4376 struct net_device *filter_dev,
4377 struct mlx5_eswitch_rep *in_rep,
71129676 4378 struct mlx5_core_dev *in_mdev)
a88780a9 4379{
f9e30088 4380 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4381 struct netlink_ext_ack *extack = f->common.extack;
4382 struct mlx5e_tc_flow_parse_attr *parse_attr;
4383 struct mlx5e_tc_flow *flow;
4384 int attr_size, err;
e3a2b7ed 4385
226f2ca3 4386 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4387 attr_size = sizeof(struct mlx5_esw_flow_attr);
4388 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4389 &parse_attr, &flow);
4390 if (err)
4391 goto out;
988ab9c7 4392
d11afc26 4393 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 4394 mlx5e_flow_esw_attr_init(flow->esw_attr,
4395 priv, parse_attr,
4396 f, in_rep, in_mdev);
4397
54c177ca
OS		 4398 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4399 f, filter_dev);
d11afc26
OS		 4400 if (err)
4401 goto err_free;
a88780a9 4402
7e36feeb 4403 /* actions validation depends on parsing the ct matches first */
4c8594ad
RD		 4404 err = mlx5_tc_ct_match_add(priv, &parse_attr->spec, f,
4405 &flow->esw_attr->ct_attr, extack);
a88780a9
RD		 4406 if (err)
4407 goto err_free;
4408
7e36feeb 4409 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4410 if (err)
4411 goto err_free;
4412
7040632d 4413 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4414 complete_all(&flow->init_done);
ef06c9ee
RD		 4415 if (err) {
4416 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4417 goto err_free;
4418
b4a23329 4419 add_unready_flow(flow);
ef06c9ee 4420 }
e3a2b7ed 4421
71129676 4422 return flow;
a88780a9
RD		 4423
4424err_free:
5a7e5bcb 4425 mlx5e_flow_put(priv, flow);
a88780a9 4426out:
71129676 4427 return ERR_PTR(err);
a88780a9
RD		 4428}
4429
f9e30088 4430static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4431 struct mlx5e_tc_flow *flow,
226f2ca3 4432 unsigned long flow_flags)
04de7dda
RD		 4433{
4434 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4435 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4436 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4437 struct mlx5e_tc_flow_parse_attr *parse_attr;
4438 struct mlx5e_rep_priv *peer_urpriv;
4439 struct mlx5e_tc_flow *peer_flow;
4440 struct mlx5_core_dev *in_mdev;
4441 int err = 0;
4442
4443 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4444 if (!peer_esw)
4445 return -ENODEV;
4446
4447 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4448 peer_priv = netdev_priv(peer_urpriv->netdev);
4449
4450 /* in_mdev is assigned of which the packet originated from.
4451 * So packets redirected to uplink use the same mdev of the
4452 * original flow and packets redirected from uplink use the
4453 * peer mdev.
4454 */
b05af6aa 4455 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4456 in_mdev = peer_priv->mdev;
4457 else
4458 in_mdev = priv->mdev;
4459
4460 parse_attr = flow->esw_attr->parse_attr;
95dc1902 4461 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 4462 parse_attr->filter_dev,
4463 flow->esw_attr->in_rep, in_mdev);
4464 if (IS_ERR(peer_flow)) {
4465 err = PTR_ERR(peer_flow);
04de7dda 4466 goto out;
71129676 4467 }
04de7dda
RD		 4468
4469 flow->peer_flow = peer_flow;
226f2ca3 4470 flow_flag_set(flow, DUP);
04de7dda
RD		 4471 mutex_lock(&esw->offloads.peer_mutex);
4472 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4473 mutex_unlock(&esw->offloads.peer_mutex);
4474
4475out:
4476 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4477 return err;
4478}
4479
4480static int
4481mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4482 struct flow_cls_offload *f,
226f2ca3 4483 unsigned long flow_flags,
04de7dda
RD		 4484 struct net_device *filter_dev,
4485 struct mlx5e_tc_flow **__flow)
4486{
4487 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4488 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4489 struct mlx5_core_dev *in_mdev = priv->mdev;
4490 struct mlx5e_tc_flow *flow;
4491 int err;
4492
71129676
JG		 4493 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4494 in_mdev);
4495 if (IS_ERR(flow))
4496 return PTR_ERR(flow);
04de7dda
RD		 4497
4498 if (is_peer_flow_needed(flow)) {
95dc1902 4499 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4500 if (err) {
4501 mlx5e_tc_del_fdb_flow(priv, flow);
4502 goto out;
4503 }
4504 }
4505
4506 *__flow = flow;
4507
4508 return 0;
4509
4510out:
4511 return err;
4512}
4513
a88780a9
RD		 4514static int
4515mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4516 struct flow_cls_offload *f,
226f2ca3 4517 unsigned long flow_flags,
d11afc26 4518 struct net_device *filter_dev,
a88780a9
RD		 4519 struct mlx5e_tc_flow **__flow)
4520{
f9e30088 4521 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4522 struct netlink_ext_ack *extack = f->common.extack;
4523 struct mlx5e_tc_flow_parse_attr *parse_attr;
4524 struct mlx5e_tc_flow *flow;
4525 int attr_size, err;
4526
bf07aa73
PB		 4527 /* multi-chain not supported for NIC rules */
4528 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4529 return -EOPNOTSUPP;
4530
226f2ca3 4531 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4532 attr_size = sizeof(struct mlx5_nic_flow_attr);
4533 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4534 &parse_attr, &flow);
4535 if (err)
4536 goto out;
4537
d11afc26 4538 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 4539 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4540 f, filter_dev);
d11afc26
OS		 4541 if (err)
4542 goto err_free;
4543
73867881 4544 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4545 if (err)
4546 goto err_free;
4547
4548 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4549 if (err)
4550 goto err_free;
4551
226f2ca3 4552 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4553 kvfree(parse_attr);
4554 *__flow = flow;
4555
4556 return 0;
e3a2b7ed 4557
e3a2b7ed 4558err_free:
5a7e5bcb 4559 mlx5e_flow_put(priv, flow);
17091853 4560 kvfree(parse_attr);
a88780a9
RD		 4561out:
4562 return err;
4563}
4564
4565static int
4566mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4567 struct flow_cls_offload *f,
226f2ca3 4568 unsigned long flags,
d11afc26 4569 struct net_device *filter_dev,
a88780a9
RD		 4570 struct mlx5e_tc_flow **flow)
4571{
4572 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4573 unsigned long flow_flags;
a88780a9
RD		 4574 int err;
4575
4576 get_flags(flags, &flow_flags);
4577
bf07aa73
PB		 4578 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4579 return -EOPNOTSUPP;
4580
f6455de0 4581 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4582 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4583 filter_dev, flow);
a88780a9 4584 else
d11afc26
OS		 4585 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4586 filter_dev, flow);
a88780a9
RD		 4587
4588 return err;
4589}
4590
553f9328
VP		 4591static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4592 struct mlx5e_rep_priv *rpriv)
4593{
4594 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4595 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4596 * function is called from NIC mode.
553f9328 4597 */
2fb15e72 4598 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4599}
4600
71d82d2a 4601int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4602 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4603{
4604 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4605 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4606 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4607 struct mlx5e_tc_flow *flow;
4608 int err = 0;
4609
c5d326b2
VB		 4610 rcu_read_lock();
4611 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4612 if (flow) {
553f9328
VP		 4613 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4614 * just return 0.
4615 */
4616 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4617 goto rcu_unlock;
553f9328 4618
a88780a9
RD		 4619 NL_SET_ERR_MSG_MOD(extack,
4620 "flow cookie already exists, ignoring");
4621 netdev_warn_once(priv->netdev,
4622 "flow cookie %lx already exists, ignoring\n",
4623 f->cookie);
0e1c1a2f 4624 err = -EEXIST;
c1aea9e1 4625 goto rcu_unlock;
a88780a9 4626 }
c1aea9e1
VB		 4627rcu_unlock:
4628 rcu_read_unlock();
4629 if (flow)
4630 goto out;
a88780a9 4631
7a978759 4632 trace_mlx5e_configure_flower(f);
d11afc26 4633 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4634 if (err)
4635 goto out;
4636
553f9328
VP		 4637 /* Flow rule offloaded to non-uplink representor sharing tc block,
4638 * set the flow's owner dev.
4639 */
4640 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4641 flow->orig_dev = dev;
4642
c5d326b2 4643 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4644 if (err)
4645 goto err_free;
4646
4647 return 0;
4648
4649err_free:
5a7e5bcb 4650 mlx5e_flow_put(priv, flow);
a88780a9 4651out:
e3a2b7ed
AV		 4652 return err;
4653}
4654
8f8ae895
OG		 4655static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4656{
226f2ca3
VB		 4657 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4658 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4659
226f2ca3
VB		 4660 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4661 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4662}
4663
71d82d2a 4664int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4665 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4666{
d9ee0491 4667 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4668 struct mlx5e_tc_flow *flow;
c5d326b2 4669 int err;
e3a2b7ed 4670
c5d326b2 4671 rcu_read_lock();
ab818362 4672 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4673 if (!flow || !same_flow_direction(flow, flags)) {
4674 err = -EINVAL;
4675 goto errout;
4676 }
e3a2b7ed 4677
c5d326b2
VB		 4678 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4679 * set.
4680 */
4681 if (flow_flag_test_and_set(flow, DELETED)) {
4682 err = -EINVAL;
4683 goto errout;
4684 }
05866c82 4685 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4686 rcu_read_unlock();
e3a2b7ed 4687
7a978759 4688 trace_mlx5e_delete_flower(f);
5a7e5bcb 4689 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4690
4691 return 0;
c5d326b2
VB		 4692
4693errout:
4694 rcu_read_unlock();
4695 return err;
e3a2b7ed
AV		 4696}
4697
71d82d2a 4698int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4699 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4700{
04de7dda 4701 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4702 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4703 struct mlx5_eswitch *peer_esw;
aad7e08d 4704 struct mlx5e_tc_flow *flow;
aad7e08d 4705 struct mlx5_fc *counter;
316d5f72
RD		 4706 u64 lastuse = 0;
4707 u64 packets = 0;
4708 u64 bytes = 0;
5a7e5bcb 4709 int err = 0;
aad7e08d 4710
c5d326b2
VB		 4711 rcu_read_lock();
4712 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4713 tc_ht_params));
4714 rcu_read_unlock();
5a7e5bcb
VB		 4715 if (IS_ERR(flow))
4716 return PTR_ERR(flow);
4717
4718 if (!same_flow_direction(flow, flags)) {
4719 err = -EINVAL;
4720 goto errout;
4721 }
aad7e08d 4722
4c3844d9 4723 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4724 counter = mlx5e_tc_get_counter(flow);
4725 if (!counter)
5a7e5bcb 4726 goto errout;
aad7e08d 4727
316d5f72
RD		 4728 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4729 }
aad7e08d 4730
316d5f72
RD		 4731 /* Under multipath it's possible for one rule to be currently
4732 * un-offloaded while the other rule is offloaded.
4733 */
04de7dda
RD		 4734 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4735 if (!peer_esw)
4736 goto out;
4737
226f2ca3
VB		 4738 if (flow_flag_test(flow, DUP) &&
4739 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4740 u64 bytes2;
4741 u64 packets2;
4742 u64 lastuse2;
4743
4744 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4745 if (!counter)
4746 goto no_peer_counter;
04de7dda
RD		 4747 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4748
4749 bytes += bytes2;
4750 packets += packets2;
4751 lastuse = max_t(u64, lastuse, lastuse2);
4752 }
4753
316d5f72 4754no_peer_counter:
04de7dda 4755 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4756out:
4b61d3e8 4757 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4758 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4759 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4760errout:
4761 mlx5e_flow_put(priv, flow);
4762 return err;
aad7e08d
AV		 4763}
4764
fcb64c0f
EC		 4765static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4766 struct netlink_ext_ack *extack)
4767{
4768 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4769 struct mlx5_eswitch *esw;
4770 u16 vport_num;
4771 u32 rate_mbps;
4772 int err;
4773
e401a184
EC		 4774 vport_num = rpriv->rep->vport;
4775 if (vport_num >= MLX5_VPORT_ECPF) {
4776 NL_SET_ERR_MSG_MOD(extack,
4777 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4778 return -EOPNOTSUPP;
4779 }
4780
fcb64c0f
EC		 4781 esw = priv->mdev->priv.eswitch;
4782 /* rate is given in bytes/sec.
4783 * First convert to bits/sec and then round to the nearest mbit/secs.
4784 * mbit means million bits.
4785 * Moreover, if rate is non zero we choose to configure to a minimum of
4786 * 1 mbit/sec.
4787 */
4788 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
fcb64c0f
EC		 4789 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4790 if (err)
4791 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4792
4793 return err;
4794}
4795
4796static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4797 struct flow_action *flow_action,
4798 struct netlink_ext_ack *extack)
4799{
4800 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4801 const struct flow_action_entry *act;
4802 int err;
4803 int i;
4804
4805 if (!flow_action_has_entries(flow_action)) {
4806 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4807 return -EINVAL;
4808 }
4809
4810 if (!flow_offload_has_one_action(flow_action)) {
4811 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4812 return -EOPNOTSUPP;
4813 }
4814
53eca1f3 4815 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4816 return -EOPNOTSUPP;
4817
fcb64c0f
EC		 4818 flow_action_for_each(i, act, flow_action) {
4819 switch (act->id) {
4820 case FLOW_ACTION_POLICE:
4821 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4822 if (err)
4823 return err;
4824
4825 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4826 break;
4827 default:
4828 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4829 return -EOPNOTSUPP;
4830 }
4831 }
4832
4833 return 0;
4834}
4835
4836int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4837 struct tc_cls_matchall_offload *ma)
4838{
b5f814cc 4839 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4840 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4841
b5f814cc
EC		 4842 if (!mlx5_esw_qos_enabled(esw)) {
4843 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4844 return -EOPNOTSUPP;
4845 }
4846
7b83355f 4847 if (ma->common.prio != 1) {
fcb64c0f
EC		 4848 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4849 return -EINVAL;
4850 }
4851
4852 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4853}
4854
4855int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4856 struct tc_cls_matchall_offload *ma)
4857{
4858 struct netlink_ext_ack *extack = ma->common.extack;
4859
4860 return apply_police_params(priv, 0, extack);
4861}
4862
4863void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4864 struct tc_cls_matchall_offload *ma)
4865{
4866 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4867 struct rtnl_link_stats64 cur_stats;
4868 u64 dbytes;
4869 u64 dpkts;
4870
4871 cur_stats = priv->stats.vf_vport;
4872 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4873 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4874 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4875 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4876 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4877}
4878
4d8fcf21
AH		 4879static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4880 struct mlx5e_priv *peer_priv)
4881{
4882 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4883 struct mlx5e_hairpin_entry *hpe, *tmp;
4884 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4885 u16 peer_vhca_id;
4886 int bkt;
4887
4888 if (!same_hw_devs(priv, peer_priv))
4889 return;
4890
4891 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4892
b32accda 4893 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4894 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4895 if (refcount_inc_not_zero(&hpe->refcnt))
4896 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4897 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4898
4899 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4900 wait_for_completion(&hpe->res_ready);
4901 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4902 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4903
4904 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4905 }
4906}
4907
4908static int mlx5e_tc_netdev_event(struct notifier_block *this,
4909 unsigned long event, void *ptr)
4910{
4911 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4912 struct mlx5e_flow_steering *fs;
4913 struct mlx5e_priv *peer_priv;
4914 struct mlx5e_tc_table *tc;
4915 struct mlx5e_priv *priv;
4916
4917 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4918 event != NETDEV_UNREGISTER ||
4919 ndev->reg_state == NETREG_REGISTERED)
4920 return NOTIFY_DONE;
4921
4922 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4923 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4924 priv = container_of(fs, struct mlx5e_priv, fs);
4925 peer_priv = netdev_priv(ndev);
4926 if (priv == peer_priv ||
4927 !(priv->netdev->features & NETIF_F_HW_TC))
4928 return NOTIFY_DONE;
4929
4930 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4931
4932 return NOTIFY_DONE;
4933}
4934
655dc3d2 4935int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4936{
acff797c 4937 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4938 int err;
e8f887ac 4939
b2fdf3d0 4940 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4941 mutex_init(&tc->t_lock);
b32accda 4942 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4943 hash_init(tc->hairpin_tbl);
11c9c548 4944
4d8fcf21
AH		 4945 err = rhashtable_init(&tc->ht, &tc_ht_params);
4946 if (err)
4947 return err;
4948
4949 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4950 err = register_netdevice_notifier_dev_net(priv->netdev,
4951 &tc->netdevice_nb,
4952 &tc->netdevice_nn);
4953 if (err) {
4d8fcf21
AH		 4954 tc->netdevice_nb.notifier_call = NULL;
4955 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4956 }
4957
4958 return err;
e8f887ac
AV		 4959}
4960
4961static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4962{
4963 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4964 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4965
961e8979 4966 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4967 kfree(flow);
4968}
4969
655dc3d2 4970void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4971{
acff797c 4972 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4973
4d8fcf21 4974 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4975 unregister_netdevice_notifier_dev_net(priv->netdev,
4976 &tc->netdevice_nb,
4977 &tc->netdevice_nn);
4d8fcf21 4978
b2fdf3d0 4979 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4980 mutex_destroy(&tc->hairpin_tbl_lock);
4981
d9ee0491 4982 rhashtable_destroy(&tc->ht);
e8f887ac 4983
acff797c
MG		 4984 if (!IS_ERR_OR_NULL(tc->t)) {
4985 mlx5_destroy_flow_table(tc->t);
4986 tc->t = NULL;
e8f887ac 4987 }
b6fac0b4 4988 mutex_destroy(&tc->t_lock);
e8f887ac 4989}
655dc3d2
OG		 4990
4991int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4992{
d7a42ad0 4993 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78
PB		 4994 struct mlx5_rep_uplink_priv *uplink_priv;
4995 struct mlx5e_rep_priv *priv;
4996 struct mapping_ctx *mapping;
4997 int err;
4998
4999 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
5000 priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5001
4c3844d9
PB		 5002 err = mlx5_tc_ct_init(uplink_priv);
5003 if (err)
5004 goto err_ct;
5005
0a7fcb78
PB		 5006 mapping = mapping_create(sizeof(struct tunnel_match_key),
5007 TUNNEL_INFO_BITS_MASK, true);
5008 if (IS_ERR(mapping)) {
5009 err = PTR_ERR(mapping);
5010 goto err_tun_mapping;
5011 }
5012 uplink_priv->tunnel_mapping = mapping;
5013
5014 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
5015 if (IS_ERR(mapping)) {
5016 err = PTR_ERR(mapping);
5017 goto err_enc_opts_mapping;
5018 }
5019 uplink_priv->tunnel_enc_opts_mapping = mapping;
5020
5021 err = rhashtable_init(tc_ht, &tc_ht_params);
5022 if (err)
5023 goto err_ht_init;
5024
5025 return err;
5026
5027err_ht_init:
5028 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5029err_enc_opts_mapping:
5030 mapping_destroy(uplink_priv->tunnel_mapping);
5031err_tun_mapping:
4c3844d9
PB		 5032 mlx5_tc_ct_clean(uplink_priv);
5033err_ct:
0a7fcb78
PB		 5034 netdev_warn(priv->netdev,
5035 "Failed to initialize tc (eswitch), err: %d", err);
5036 return err;
655dc3d2
OG		 5037}
5038
5039void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5040{
0a7fcb78
PB		 5041 struct mlx5_rep_uplink_priv *uplink_priv;
5042
655dc3d2 5043 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 5044
5045 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
5046 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5047 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9
PB		 5048
5049 mlx5_tc_ct_clean(uplink_priv);
655dc3d2 5050}
01252a27 5051
226f2ca3 5052int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5053{
d9ee0491 5054 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5055
5056 return atomic_read(&tc_ht->nelems);
5057}
04de7dda
RD		 5058
5059void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5060{
5061 struct mlx5e_tc_flow *flow, *tmp;
5062
5063 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5064 __mlx5e_tc_del_fdb_peer_flow(flow);
5065}
b4a23329
RD		 5066
5067void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5068{
5069 struct mlx5_rep_uplink_priv *rpriv =
5070 container_of(work, struct mlx5_rep_uplink_priv,
5071 reoffload_flows_work);
5072 struct mlx5e_tc_flow *flow, *tmp;
5073
ad86755b 5074 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5075 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5076 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5077 unready_flow_del(flow);
b4a23329 5078 }
ad86755b 5079 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5080}
e2394a61
VB		 5081
5082static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5083 struct flow_cls_offload *cls_flower,
5084 unsigned long flags)
5085{
5086 switch (cls_flower->command) {
5087 case FLOW_CLS_REPLACE:
5088 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5089 flags);
5090 case FLOW_CLS_DESTROY:
5091 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5092 flags);
5093 case FLOW_CLS_STATS:
5094 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5095 flags);
5096 default:
5097 return -EOPNOTSUPP;
5098 }
5099}
5100
5101int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5102 void *cb_priv)
5103{
5104 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
5105 struct mlx5e_priv *priv = cb_priv;
5106
5107 switch (type) {
5108 case TC_SETUP_CLSFLOWER:
5109 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5110 default:
5111 return -EOPNOTSUPP;
5112 }
5113}
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