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net/mlx5e: Remove redundant filter_dev arg from parse_tc_fdb_actions()
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
d79b6df6 42#include <net/tc_act/tc_pedit.h>
26c02749 43#include <net/tc_act/tc_csum.h>
41c2fd94 44#include <net/psample.h>
f6dfb4c3 45#include <net/arp.h>
3616d08b 46#include <net/ipv6_stubs.h>
f828ca6a 47#include <net/bareudp.h>
d34eb2fc 48#include <net/bonding.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
768c3667 51#include "en/rep/tc.h"
e2394a61 52#include "en/rep/neigh.h"
232c0013 53#include "en_tc.h"
03a9d11e 54#include "eswitch.h"
3f6d08d1 55#include "fs_core.h"
2c81bfd5 56#include "en/port.h"
101f4de9 57#include "en/tc_tun.h"
0a7fcb78 58#include "en/mapping.h"
4c3844d9 59#include "en/tc_ct.h"
b2fdf3d0 60#include "en/mod_hdr.h"
0d9f9647
VB		 61#include "en/tc_priv.h"
62#include "en/tc_tun_encap.h"
2a9ab10a 63#include "esw/sample.h"
04de7dda 64#include "lib/devcom.h"
9272e3df 65#include "lib/geneve.h"
ae430332 66#include "lib/fs_chains.h"
7a978759 67#include "diag/en_tc_tracepoint.h"
1fe3e316 68#include <asm/div64.h>
e8f887ac 69
6a064674 70#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 71#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 72
acff797c 73#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 74#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 75
8f1e0b97
PB		 76struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
77 [CHAIN_TO_REG] = {
78 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
79 .moffset = 0,
ed2fe7ba 80 .mlen = 16,
8f1e0b97 81 },
10742efc
VB		 82 [VPORT_TO_REG] = {
83 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 84 .moffset = 16,
85 .mlen = 16,
10742efc 86 },
0a7fcb78
PB		 87 [TUNNEL_TO_REG] = {
88 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 89 .moffset = 8,
90 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 91 .soffset = MLX5_BYTE_OFF(fte_match_param,
92 misc_parameters_2.metadata_reg_c_1),
93 },
4c3844d9 94 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 95 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 96 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
97 [MARK_TO_REG] = mark_to_reg_ct,
98 [LABELS_TO_REG] = labels_to_reg_ct,
99 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 100 /* For NIC rules we store the retore metadata directly
101 * into reg_b that is passed to SW since we don't
102 * jump between steering domains.
103 */
104 [NIC_CHAIN_TO_REG] = {
105 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
106 .moffset = 0,
ed2fe7ba 107 .mlen = 16,
c7569097 108 },
aedd133d 109 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 110};
111
9ba33339
RD		 112/* To avoid false lock dependency warning set the tc_ht lock
113 * class different than the lock class of the ht being used when deleting
114 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
115 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
116 * it's different than the ht->mutex here.
117 */
118static struct lock_class_key tc_ht_lock_key;
119
0a7fcb78
PB		 120static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
121
122void
123mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
124 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 125 u32 val,
0a7fcb78
PB		 126 u32 mask)
127{
ed2fe7ba 128 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 129 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 130 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 131 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 132 u32 max_mask = GENMASK(match_len - 1, 0);
133 __be32 curr_mask_be, curr_val_be;
134 u32 curr_mask, curr_val;
0a7fcb78
PB		 135
136 fmask = headers_c + soffset;
137 fval = headers_v + soffset;
138
ed2fe7ba
PB		 139 memcpy(&curr_mask_be, fmask, 4);
140 memcpy(&curr_val_be, fval, 4);
141
142 curr_mask = be32_to_cpu(curr_mask_be);
143 curr_val = be32_to_cpu(curr_val_be);
144
145 //move to correct offset
146 WARN_ON(mask > max_mask);
147 mask <<= moffset;
148 val <<= moffset;
149 max_mask <<= moffset;
150
151 //zero val and mask
152 curr_mask &= ~max_mask;
153 curr_val &= ~max_mask;
0a7fcb78 154
ed2fe7ba
PB		 155 //add current to mask
156 curr_mask |= mask;
157 curr_val |= val;
158
159 //back to be32 and write
160 curr_mask_be = cpu_to_be32(curr_mask);
161 curr_val_be = cpu_to_be32(curr_val);
162
163 memcpy(fmask, &curr_mask_be, 4);
164 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 165
166 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
167}
168
7e36feeb
PB		 169void
170mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
171 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 172 u32 *val,
7e36feeb
PB		 173 u32 *mask)
174{
ed2fe7ba 175 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 176 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 177 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 178 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 179 u32 max_mask = GENMASK(match_len - 1, 0);
180 __be32 curr_mask_be, curr_val_be;
181 u32 curr_mask, curr_val;
7e36feeb
PB		 182
183 fmask = headers_c + soffset;
184 fval = headers_v + soffset;
185
ed2fe7ba
PB		 186 memcpy(&curr_mask_be, fmask, 4);
187 memcpy(&curr_val_be, fval, 4);
188
189 curr_mask = be32_to_cpu(curr_mask_be);
190 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 191
ed2fe7ba
PB		 192 *mask = (curr_mask >> moffset) & max_mask;
193 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 194}
195
0a7fcb78 196int
c7b9038d
VB		 197mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
198 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
199 enum mlx5_flow_namespace_type ns,
200 enum mlx5e_tc_attr_to_reg type,
201 u32 data)
0a7fcb78
PB		 202{
203 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
204 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
205 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
206 char *modact;
207 int err;
208
aedd133d 209 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 210 if (err)
211 return err;
212
213 modact = mod_hdr_acts->actions +
214 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
215
216 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 217 if (mlen == 32)
0a7fcb78
PB		 218 mlen = 0;
219
220 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
221 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 222 MLX5_SET(set_action_in, modact, offset, moffset);
223 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 224 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 225 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 226 mod_hdr_acts->num_actions++;
227
c7b9038d 228 return err;
0a7fcb78
PB		 229}
230
aedd133d
AL		 231static struct mlx5_tc_ct_priv *
232get_ct_priv(struct mlx5e_priv *priv)
233{
234 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
235 struct mlx5_rep_uplink_priv *uplink_priv;
236 struct mlx5e_rep_priv *uplink_rpriv;
237
e8711402 238 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 239 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
240 uplink_priv = &uplink_rpriv->uplink_priv;
241
242 return uplink_priv->ct_priv;
243 }
244
245 return priv->fs.tc.ct;
246}
247
f94d6389
CM		 248#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
249static struct mlx5_esw_psample *
250get_sample_priv(struct mlx5e_priv *priv)
251{
252 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
253 struct mlx5_rep_uplink_priv *uplink_priv;
254 struct mlx5e_rep_priv *uplink_rpriv;
255
256 if (is_mdev_switchdev_mode(priv->mdev)) {
257 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
258 uplink_priv = &uplink_rpriv->uplink_priv;
259
260 return uplink_priv->esw_psample;
261 }
262
263 return NULL;
264}
265#endif
266
aedd133d
AL		 267struct mlx5_flow_handle *
268mlx5_tc_rule_insert(struct mlx5e_priv *priv,
269 struct mlx5_flow_spec *spec,
270 struct mlx5_flow_attr *attr)
271{
272 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
273
e8711402 274 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 275 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
276
277 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
278}
279
280void
281mlx5_tc_rule_delete(struct mlx5e_priv *priv,
282 struct mlx5_flow_handle *rule,
283 struct mlx5_flow_attr *attr)
284{
285 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
286
e8711402 287 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 288 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
289
290 return;
291 }
292
293 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
294}
295
c7b9038d
VB		 296int
297mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
298 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
299 enum mlx5_flow_namespace_type ns,
300 enum mlx5e_tc_attr_to_reg type,
301 u32 data)
302{
303 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
304
305 return ret < 0 ? ret : 0;
306}
307
308void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
309 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
310 enum mlx5e_tc_attr_to_reg type,
311 int act_id, u32 data)
312{
313 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
314 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
315 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
316 char *modact;
317
318 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
319
320 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 321 if (mlen == 32)
c7b9038d
VB		 322 mlen = 0;
323
324 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
325 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 326 MLX5_SET(set_action_in, modact, offset, moffset);
327 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 328 MLX5_SET(set_action_in, modact, data, data);
329}
330
77ab67b7
OG		 331struct mlx5e_hairpin {
332 struct mlx5_hairpin *pair;
333
334 struct mlx5_core_dev *func_mdev;
3f6d08d1 335 struct mlx5e_priv *func_priv;
77ab67b7 336 u32 tdn;
a6696735 337 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 338
339 int num_channels;
340 struct mlx5e_rqt indir_rqt;
a6696735 341 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 342 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 343};
344
5c65c564
OG		 345struct mlx5e_hairpin_entry {
346 /* a node of a hash table which keeps all the hairpin entries */
347 struct hlist_node hairpin_hlist;
348
73edca73
VB		 349 /* protects flows list */
350 spinlock_t flows_lock;
5c65c564
OG		 351 /* flows sharing the same hairpin */
352 struct list_head flows;
db76ca24
VB		 353 /* hpe's that were not fully initialized when dead peer update event
354 * function traversed them.
355 */
356 struct list_head dead_peer_wait_list;
5c65c564 357
d8822868 358 u16 peer_vhca_id;
106be53b 359 u8 prio;
5c65c564 360 struct mlx5e_hairpin *hp;
e4f9abbd 361 refcount_t refcnt;
db76ca24 362 struct completion res_ready;
5c65c564
OG		 363};
364
5a7e5bcb
VB		 365static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
366 struct mlx5e_tc_flow *flow);
367
0d9f9647 368struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 369{
370 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
371 return ERR_PTR(-EINVAL);
372 return flow;
373}
374
0d9f9647 375void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 376{
377 if (refcount_dec_and_test(&flow->refcnt)) {
378 mlx5e_tc_del_flow(priv, flow);
c5d326b2 379 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 380 }
381}
382
aedd133d 383bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 384{
385 return flow_flag_test(flow, ESWITCH);
386}
387
84179981
PB		 388static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
389{
390 return flow_flag_test(flow, FT);
391}
392
0d9f9647 393bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 394{
395 return flow_flag_test(flow, OFFLOADED);
396}
397
b2fdf3d0 398static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 399{
b2fdf3d0
PB		 400 return mlx5e_is_eswitch_flow(flow) ?
401 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 402}
403
dd58edc3 404static struct mod_hdr_tbl *
b2fdf3d0 405get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 406{
407 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
408
b2fdf3d0
PB		 409 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
410 &esw->offloads.mod_hdr :
dd58edc3
VB		 411 &priv->fs.tc.mod_hdr;
412}
413
11c9c548
OG		 414static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
415 struct mlx5e_tc_flow *flow,
416 struct mlx5e_tc_flow_parse_attr *parse_attr)
417{
b2fdf3d0
PB		 418 struct mlx5_modify_hdr *modify_hdr;
419 struct mlx5e_mod_hdr_handle *mh;
11c9c548 420
b2fdf3d0
PB		 421 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
422 get_flow_name_space(flow),
423 &parse_attr->mod_hdr_acts);
424 if (IS_ERR(mh))
425 return PTR_ERR(mh);
11c9c548 426
b2fdf3d0 427 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 428 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 429 flow->mh = mh;
11c9c548
OG		 430
431 return 0;
11c9c548
OG		 432}
433
434static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
435 struct mlx5e_tc_flow *flow)
436{
5a7e5bcb 437 /* flow wasn't fully initialized */
dd58edc3 438 if (!flow->mh)
5a7e5bcb
VB		 439 return;
440
b2fdf3d0
PB		 441 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
442 flow->mh);
dd58edc3 443 flow->mh = NULL;
11c9c548
OG		 444}
445
77ab67b7
OG		 446static
447struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
448{
b1c2f631 449 struct mlx5_core_dev *mdev;
77ab67b7
OG		 450 struct net_device *netdev;
451 struct mlx5e_priv *priv;
452
b1c2f631
DC		 453 netdev = dev_get_by_index(net, ifindex);
454 if (!netdev)
455 return ERR_PTR(-ENODEV);
456
77ab67b7 457 priv = netdev_priv(netdev);
b1c2f631
DC		 458 mdev = priv->mdev;
459 dev_put(netdev);
460
461 /* Mirred tc action holds a refcount on the ifindex net_device (see
462 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
463 * after dev_put(netdev), while we're in the context of adding a tc flow.
464 *
465 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
466 * stored in a hairpin object, which exists until all flows, that refer to it, get
467 * removed.
468 *
469 * On the other hand, after a hairpin object has been created, the peer net_device may
470 * be removed/unbound while there are still some hairpin flows that are using it. This
471 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
472 * NETDEV_UNREGISTER event of the peer net_device.
473 */
474 return mdev;
77ab67b7
OG		 475}
476
477static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
478{
a6696735 479 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 480 int err;
481
a6696735
MM		 482 builder = mlx5e_tir_builder_alloc(false);
483 if (!builder)
484 return -ENOMEM;
485
77ab67b7
OG		 486 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
487 if (err)
a6696735 488 goto out;
77ab67b7 489
a6696735
MM		 490 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
491 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 492 if (err)
493 goto create_tir_err;
494
a6696735
MM		 495out:
496 mlx5e_tir_builder_free(builder);
497 return err;
77ab67b7
OG		 498
499create_tir_err:
500 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 501
502 goto out;
77ab67b7
OG		 503}
504
505static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
506{
a6696735 507 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 508 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
509}
510
3f6d08d1
OG		 511static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
512{
3f6d08d1
OG		 513 struct mlx5e_priv *priv = hp->func_priv;
514 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 515 struct mlx5e_rss_params_indir *indir;
516 int err;
3f6d08d1 517
06e9f13a
MM		 518 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
519 if (!indir)
3f6d08d1
OG		 520 return -ENOMEM;
521
43befe99 522 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 523 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 524 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
525 indir);
3f6d08d1 526
06e9f13a 527 kvfree(indir);
3f6d08d1
OG		 528 return err;
529}
530
531static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
532{
533 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 534 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 535 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 536 struct mlx5e_tir_builder *builder;
537 int err = 0;
538
539 builder = mlx5e_tir_builder_alloc(false);
540 if (!builder)
541 return -ENOMEM;
542
43ec0f41 543 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 544
545 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 546 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 547
65d6b6e5 548 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 549
a6696735
MM		 550 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
551 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
552 false);
43ec0f41 553 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 554
a6696735 555 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 556 if (err) {
557 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
558 goto err_destroy_tirs;
559 }
a6696735
MM		 560
561 mlx5e_tir_builder_clear(builder);
3f6d08d1 562 }
3f6d08d1 563
a6696735
MM		 564out:
565 mlx5e_tir_builder_free(builder);
3f6d08d1 566 return err;
a6696735
MM		 567
568err_destroy_tirs:
569 max_tt = tt;
570 for (tt = 0; tt < max_tt; tt++)
571 mlx5e_tir_destroy(&hp->indir_tir[tt]);
572
573 goto out;
3f6d08d1
OG		 574}
575
576static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
577{
578 int tt;
579
580 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 581 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 582}
583
584static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
585 struct ttc_params *ttc_params)
586{
587 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
588 int tt;
589
590 memset(ttc_params, 0, sizeof(*ttc_params));
591
bc29764e
MG		 592 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
593 MLX5_FLOW_NAMESPACE_KERNEL);
594 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
595 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
596 ttc_params->dests[tt].tir_num =
597 tt == MLX5_TT_ANY ?
598 mlx5e_tir_get_tirn(&hp->direct_tir) :
599 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
600 }
3f6d08d1 601
3f6d08d1
OG		 602 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
603 ft_attr->prio = MLX5E_TC_PRIO;
604}
605
606static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
607{
608 struct mlx5e_priv *priv = hp->func_priv;
609 struct ttc_params ttc_params;
610 int err;
611
612 err = mlx5e_hairpin_create_indirect_rqt(hp);
613 if (err)
614 return err;
615
616 err = mlx5e_hairpin_create_indirect_tirs(hp);
617 if (err)
618 goto err_create_indirect_tirs;
619
620 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 621 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
622 if (IS_ERR(hp->ttc)) {
623 err = PTR_ERR(hp->ttc);
3f6d08d1 624 goto err_create_ttc_table;
f4b45940 625 }
3f6d08d1
OG		 626
627 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 628 hp->num_channels,
629 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 630
631 return 0;
632
633err_create_ttc_table:
634 mlx5e_hairpin_destroy_indirect_tirs(hp);
635err_create_indirect_tirs:
06e9f13a 636 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 637
638 return err;
639}
640
641static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
642{
f4b45940 643 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 644 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 645 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 646}
647
77ab67b7
OG		 648static struct mlx5e_hairpin *
649mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
650 int peer_ifindex)
651{
652 struct mlx5_core_dev *func_mdev, *peer_mdev;
653 struct mlx5e_hairpin *hp;
654 struct mlx5_hairpin *pair;
655 int err;
656
657 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
658 if (!hp)
659 return ERR_PTR(-ENOMEM);
660
661 func_mdev = priv->mdev;
662 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 663 if (IS_ERR(peer_mdev)) {
664 err = PTR_ERR(peer_mdev);
665 goto create_pair_err;
666 }
77ab67b7
OG		 667
668 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
669 if (IS_ERR(pair)) {
670 err = PTR_ERR(pair);
671 goto create_pair_err;
672 }
673 hp->pair = pair;
674 hp->func_mdev = func_mdev;
3f6d08d1
OG		 675 hp->func_priv = priv;
676 hp->num_channels = params->num_channels;
77ab67b7
OG		 677
678 err = mlx5e_hairpin_create_transport(hp);
679 if (err)
680 goto create_transport_err;
681
3f6d08d1
OG		 682 if (hp->num_channels > 1) {
683 err = mlx5e_hairpin_rss_init(hp);
684 if (err)
685 goto rss_init_err;
686 }
687
77ab67b7
OG		 688 return hp;
689
3f6d08d1
OG		 690rss_init_err:
691 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 692create_transport_err:
693 mlx5_core_hairpin_destroy(hp->pair);
694create_pair_err:
695 kfree(hp);
696 return ERR_PTR(err);
697}
698
699static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
700{
3f6d08d1
OG		 701 if (hp->num_channels > 1)
702 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 703 mlx5e_hairpin_destroy_transport(hp);
704 mlx5_core_hairpin_destroy(hp->pair);
705 kvfree(hp);
706}
707
106be53b
OG		 708static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
709{
710 return (peer_vhca_id << 16 | prio);
711}
712
5c65c564 713static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 714 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 715{
716 struct mlx5e_hairpin_entry *hpe;
106be53b 717 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 718
719 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 720 hairpin_hlist, hash_key) {
e4f9abbd
VB		 721 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
722 refcount_inc(&hpe->refcnt);
5c65c564 723 return hpe;
e4f9abbd 724 }
5c65c564
OG		 725 }
726
727 return NULL;
728}
729
e4f9abbd
VB		 730static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
731 struct mlx5e_hairpin_entry *hpe)
732{
733 /* no more hairpin flows for us, release the hairpin pair */
b32accda 734 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 735 return;
b32accda
VB		 736 hash_del(&hpe->hairpin_hlist);
737 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 738
db76ca24
VB		 739 if (!IS_ERR_OR_NULL(hpe->hp)) {
740 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
741 dev_name(hpe->hp->pair->peer_mdev->device));
742
743 mlx5e_hairpin_destroy(hpe->hp);
744 }
e4f9abbd
VB		 745
746 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 747 kfree(hpe);
748}
749
106be53b
OG		 750#define UNKNOWN_MATCH_PRIO 8
751
752static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 753 struct mlx5_flow_spec *spec, u8 *match_prio,
754 struct netlink_ext_ack *extack)
106be53b
OG		 755{
756 void *headers_c, *headers_v;
757 u8 prio_val, prio_mask = 0;
758 bool vlan_present;
759
760#ifdef CONFIG_MLX5_CORE_EN_DCB
761 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 762 NL_SET_ERR_MSG_MOD(extack,
763 "only PCP trust state supported for hairpin");
106be53b
OG		 764 return -EOPNOTSUPP;
765 }
766#endif
767 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
768 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
769
770 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
771 if (vlan_present) {
772 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
773 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
774 }
775
776 if (!vlan_present || !prio_mask) {
777 prio_val = UNKNOWN_MATCH_PRIO;
778 } else if (prio_mask != 0x7) {
e98bedf5
EB		 779 NL_SET_ERR_MSG_MOD(extack,
780 "masked priority match not supported for hairpin");
106be53b
OG		 781 return -EOPNOTSUPP;
782 }
783
784 *match_prio = prio_val;
785 return 0;
786}
787
5c65c564
OG		 788static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
789 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 790 struct mlx5e_tc_flow_parse_attr *parse_attr,
791 struct netlink_ext_ack *extack)
5c65c564 792{
98b66cb1 793 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 794 struct mlx5_hairpin_params params;
d8822868 795 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 796 struct mlx5e_hairpin_entry *hpe;
797 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 798 u64 link_speed64;
799 u32 link_speed;
106be53b 800 u8 match_prio;
d8822868 801 u16 peer_id;
5c65c564
OG		 802 int err;
803
d8822868 804 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 805 if (IS_ERR(peer_mdev)) {
806 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
807 return PTR_ERR(peer_mdev);
808 }
809
d8822868 810 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 811 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 812 return -EOPNOTSUPP;
813 }
814
d8822868 815 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 816 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
817 extack);
106be53b
OG		 818 if (err)
819 return err;
b32accda
VB		 820
821 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 822 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 823 if (hpe) {
824 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
825 wait_for_completion(&hpe->res_ready);
826
827 if (IS_ERR(hpe->hp)) {
828 err = -EREMOTEIO;
829 goto out_err;
830 }
5c65c564 831 goto attach_flow;
db76ca24 832 }
5c65c564
OG		 833
834 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 835 if (!hpe) {
db76ca24
VB		 836 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
837 return -ENOMEM;
b32accda 838 }
5c65c564 839
73edca73 840 spin_lock_init(&hpe->flows_lock);
5c65c564 841 INIT_LIST_HEAD(&hpe->flows);
db76ca24 842 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 843 hpe->peer_vhca_id = peer_id;
106be53b 844 hpe->prio = match_prio;
e4f9abbd 845 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 846 init_completion(&hpe->res_ready);
847
848 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
849 hash_hairpin_info(peer_id, match_prio));
850 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 851
6cdc686a 852 params.log_data_size = 16;
5c65c564
OG		 853 params.log_data_size = min_t(u8, params.log_data_size,
854 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
855 params.log_data_size = max_t(u8, params.log_data_size,
856 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 857
eb9180f7
OG		 858 params.log_num_packets = params.log_data_size -
859 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
860 params.log_num_packets = min_t(u8, params.log_num_packets,
861 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
862
863 params.q_counter = priv->q_counter;
3f6d08d1 864 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 865 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 866 link_speed = max_t(u32, link_speed, 50000);
867 link_speed64 = link_speed;
868 do_div(link_speed64, 50000);
869 params.num_channels = link_speed64;
870
5c65c564 871 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 872 hpe->hp = hp;
873 complete_all(&hpe->res_ready);
5c65c564
OG		 874 if (IS_ERR(hp)) {
875 err = PTR_ERR(hp);
db76ca24 876 goto out_err;
5c65c564
OG		 877 }
878
eb9180f7 879 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 880 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 881 dev_name(hp->pair->peer_mdev->device),
eb9180f7 882 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 883
5c65c564 884attach_flow:
3f6d08d1 885 if (hpe->hp->num_channels > 1) {
226f2ca3 886 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 887 flow->attr->nic_attr->hairpin_ft =
888 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 889 } else {
a6696735 890 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 891 }
b32accda 892
e4f9abbd 893 flow->hpe = hpe;
73edca73 894 spin_lock(&hpe->flows_lock);
5c65c564 895 list_add(&flow->hairpin, &hpe->flows);
73edca73 896 spin_unlock(&hpe->flows_lock);
3f6d08d1 897
5c65c564
OG		 898 return 0;
899
db76ca24
VB		 900out_err:
901 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 902 return err;
903}
904
905static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
906 struct mlx5e_tc_flow *flow)
907{
5a7e5bcb 908 /* flow wasn't fully initialized */
e4f9abbd 909 if (!flow->hpe)
5a7e5bcb
VB		 910 return;
911
73edca73 912 spin_lock(&flow->hpe->flows_lock);
5c65c564 913 list_del(&flow->hairpin);
73edca73
VB		 914 spin_unlock(&flow->hpe->flows_lock);
915
e4f9abbd
VB		 916 mlx5e_hairpin_put(priv, flow->hpe);
917 flow->hpe = NULL;
5c65c564
OG		 918}
919
08247066
AL		 920struct mlx5_flow_handle *
921mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
922 struct mlx5_flow_spec *spec,
c620b772 923 struct mlx5_flow_attr *attr)
e8f887ac 924{
08247066 925 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 926 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 927 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 928 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 929 struct mlx5_flow_destination dest[2] = {};
66958ed9 930 struct mlx5_flow_act flow_act = {
3bc4b7bf 931 .action = attr->action,
bb0ee7dc 932 .flags = FLOW_ACT_NO_APPEND,
66958ed9 933 };
08247066 934 struct mlx5_flow_handle *rule;
c7569097 935 struct mlx5_flow_table *ft;
08247066 936 int dest_ix = 0;
e8f887ac 937
bb0ee7dc 938 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 939 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 940
aedd133d
AL		 941 if (attr->dest_ft) {
942 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
943 dest[dest_ix].ft = attr->dest_ft;
944 dest_ix++;
945 } else if (nic_attr->hairpin_ft) {
08247066 946 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 947 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 948 dest_ix++;
c620b772 949 } else if (nic_attr->hairpin_tirn) {
08247066 950 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 951 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 952 dest_ix++;
3f6d08d1
OG		 953 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
954 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 955 if (attr->dest_chain) {
956 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
957 attr->dest_chain, 1,
958 MLX5E_TC_FT_LEVEL);
959 if (IS_ERR(dest[dest_ix].ft))
960 return ERR_CAST(dest[dest_ix].ft);
961 } else {
6783f0a2 962 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 963 }
3f6d08d1 964 dest_ix++;
5c65c564 965 }
aad7e08d 966
c7569097
AL		 967 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
968 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
969 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
970
08247066 971 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 972 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 973 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 974 dest_ix++;
aad7e08d
AV		 975 }
976
08247066 977 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 978 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 979
6a064674
AL		 980 mutex_lock(&tc->t_lock);
981 if (IS_ERR_OR_NULL(tc->t)) {
982 /* Create the root table here if doesn't exist yet */
983 tc->t =
c7569097 984 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 985
986 if (IS_ERR(tc->t)) {
987 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 988 netdev_err(priv->netdev,
989 "Failed to create tc offload table\n");
c7569097
AL		 990 rule = ERR_CAST(priv->fs.tc.t);
991 goto err_ft_get;
e8f887ac 992 }
e8f887ac 993 }
08247066 994 mutex_unlock(&tc->t_lock);
e8f887ac 995
aedd133d
AL		 996 if (attr->chain || attr->prio)
997 ft = mlx5_chains_get_table(nic_chains,
998 attr->chain, attr->prio,
999 MLX5E_TC_FT_LEVEL);
1000 else
1001 ft = attr->ft;
1002
c7569097
AL		 1003 if (IS_ERR(ft)) {
1004 rule = ERR_CAST(ft);
1005 goto err_ft_get;
1006 }
1007
c620b772 1008 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1009 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1010
c7569097 1011 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1012 &flow_act, dest, dest_ix);
1013 if (IS_ERR(rule))
c7569097 1014 goto err_rule;
08247066
AL		 1015
1016 return rule;
c7569097
AL		 1017
1018err_rule:
aedd133d
AL		 1019 if (attr->chain || attr->prio)
1020 mlx5_chains_put_table(nic_chains,
1021 attr->chain, attr->prio,
1022 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1023err_ft_get:
1024 if (attr->dest_chain)
1025 mlx5_chains_put_table(nic_chains,
1026 attr->dest_chain, 1,
1027 MLX5E_TC_FT_LEVEL);
1028
1029 return ERR_CAST(rule);
08247066
AL		 1030}
1031
1032static int
1033mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1034 struct mlx5e_tc_flow_parse_attr *parse_attr,
1035 struct mlx5e_tc_flow *flow,
1036 struct netlink_ext_ack *extack)
1037{
c620b772 1038 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1039 struct mlx5_core_dev *dev = priv->mdev;
1040 struct mlx5_fc *counter = NULL;
1041 int err;
1042
1043 if (flow_flag_test(flow, HAIRPIN)) {
1044 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1045 if (err)
1046 return err;
1047 }
1048
1049 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1050 counter = mlx5_fc_create(dev, true);
1051 if (IS_ERR(counter))
1052 return PTR_ERR(counter);
1053
1054 attr->counter = counter;
1055 }
1056
1057 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1058 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1059 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1060 if (err)
1061 return err;
1062 }
1063
aedd133d
AL		 1064 if (flow_flag_test(flow, CT))
1065 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1066 attr, &parse_attr->mod_hdr_acts);
1067 else
1068 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1069 attr);
aad7e08d 1070
a2b7189b 1071 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1072}
1073
08247066 1074void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1075 struct mlx5_flow_handle *rule,
1076 struct mlx5_flow_attr *attr)
08247066 1077{
c7569097
AL		 1078 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1079
08247066 1080 mlx5_del_flow_rules(rule);
c7569097 1081
aedd133d
AL		 1082 if (attr->chain || attr->prio)
1083 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1084 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1085
1086 if (attr->dest_chain)
1087 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1088 MLX5E_TC_FT_LEVEL);
08247066
AL		 1089}
1090
d85cdccb
OG		 1091static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1092 struct mlx5e_tc_flow *flow)
1093{
c620b772 1094 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1095 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1096
c7569097
AL		 1097 flow_flag_clear(flow, OFFLOADED);
1098
aedd133d
AL		 1099 if (flow_flag_test(flow, CT))
1100 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1101 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1102 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1103
c7569097
AL		 1104 /* Remove root table if no rules are left to avoid
1105 * extra steering hops.
1106 */
b6fac0b4 1107 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1108 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1109 !IS_ERR_OR_NULL(tc->t)) {
1110 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1111 priv->fs.tc.t = NULL;
1112 }
b6fac0b4 1113 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1114
aedd133d
AL		 1115 kvfree(attr->parse_attr);
1116
513f8f7f 1117 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1118 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1119
aedd133d
AL		 1120 mlx5_fc_destroy(priv->mdev, attr->counter);
1121
226f2ca3 1122 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1123 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1124
1125 kfree(flow->attr);
d85cdccb
OG		 1126}
1127
0d9f9647 1128struct mlx5_flow_handle *
6d2a3ed0
OG		 1129mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1130 struct mlx5e_tc_flow *flow,
1131 struct mlx5_flow_spec *spec,
c620b772 1132 struct mlx5_flow_attr *attr)
6d2a3ed0 1133{
1ef3018f 1134 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1135 struct mlx5_flow_handle *rule;
4c3844d9 1136
89e39467
PB		 1137 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1138 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1139
1ef3018f
PB		 1140 if (flow_flag_test(flow, CT)) {
1141 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1142
69e2916e 1143 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1144 flow, spec, attr,
1ef3018f 1145 mod_hdr_acts);
f94d6389
CM		 1146#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1147 } else if (flow_flag_test(flow, SAMPLE)) {
1148 rule = mlx5_esw_sample_offload(get_sample_priv(flow->priv), spec, attr);
1149#endif
69e2916e
PB		 1150 } else {
1151 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1152 }
6d2a3ed0 1153
6d2a3ed0
OG		 1154 if (IS_ERR(rule))
1155 return rule;
1156
c620b772 1157 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1158 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1159 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1160 if (flow_flag_test(flow, CT))
1161 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1162 else
1163 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1164 return flow->rule[1];
1165 }
1166 }
1167
6d2a3ed0
OG		 1168 return rule;
1169}
1170
0d9f9647
VB		 1171void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1172 struct mlx5e_tc_flow *flow,
1173 struct mlx5_flow_attr *attr)
6d2a3ed0 1174{
226f2ca3 1175 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1176
89e39467
PB		 1177 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1178 goto offload_rule_0;
1179
4c3844d9 1180 if (flow_flag_test(flow, CT)) {
aedd133d 1181 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1182 return;
1183 }
1184
f94d6389
CM		 1185#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1186 if (flow_flag_test(flow, SAMPLE)) {
1187 mlx5_esw_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
1188 return;
1189 }
1190#endif
1191
c620b772 1192 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1193 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1194
89e39467 1195offload_rule_0:
6d2a3ed0
OG		 1196 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1197}
1198
0d9f9647 1199struct mlx5_flow_handle *
5dbe906f
PB		 1200mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1201 struct mlx5e_tc_flow *flow,
178f69b4 1202 struct mlx5_flow_spec *spec)
5dbe906f 1203{
c620b772 1204 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1205 struct mlx5_flow_handle *rule;
1206
c620b772
AL		 1207 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1208 if (!slow_attr)
1209 return ERR_PTR(-ENOMEM);
5dbe906f 1210
c620b772
AL		 1211 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1212 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1213 slow_attr->esw_attr->split_count = 0;
1214 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1215
1216 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1217 if (!IS_ERR(rule))
226f2ca3 1218 flow_flag_set(flow, SLOW);
5dbe906f 1219
c620b772
AL		 1220 kfree(slow_attr);
1221
5dbe906f
PB		 1222 return rule;
1223}
1224
0d9f9647
VB		 1225void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1226 struct mlx5e_tc_flow *flow)
5dbe906f 1227{
c620b772 1228 struct mlx5_flow_attr *slow_attr;
178f69b4 1229
c620b772 1230 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1231 if (!slow_attr) {
1232 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1233 return;
1234 }
c620b772
AL		 1235
1236 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1237 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1238 slow_attr->esw_attr->split_count = 0;
1239 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1240 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1241 flow_flag_clear(flow, SLOW);
c620b772 1242 kfree(slow_attr);
5dbe906f
PB		 1243}
1244
ad86755b
VB		 1245/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1246 * function.
1247 */
1248static void unready_flow_add(struct mlx5e_tc_flow *flow,
1249 struct list_head *unready_flows)
1250{
1251 flow_flag_set(flow, NOT_READY);
1252 list_add_tail(&flow->unready, unready_flows);
1253}
1254
1255/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1256 * function.
1257 */
1258static void unready_flow_del(struct mlx5e_tc_flow *flow)
1259{
1260 list_del(&flow->unready);
1261 flow_flag_clear(flow, NOT_READY);
1262}
1263
b4a23329
RD		 1264static void add_unready_flow(struct mlx5e_tc_flow *flow)
1265{
1266 struct mlx5_rep_uplink_priv *uplink_priv;
1267 struct mlx5e_rep_priv *rpriv;
1268 struct mlx5_eswitch *esw;
1269
1270 esw = flow->priv->mdev->priv.eswitch;
1271 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1272 uplink_priv = &rpriv->uplink_priv;
1273
ad86755b
VB		 1274 mutex_lock(&uplink_priv->unready_flows_lock);
1275 unready_flow_add(flow, &uplink_priv->unready_flows);
1276 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1277}
1278
1279static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1280{
ad86755b
VB		 1281 struct mlx5_rep_uplink_priv *uplink_priv;
1282 struct mlx5e_rep_priv *rpriv;
1283 struct mlx5_eswitch *esw;
1284
1285 esw = flow->priv->mdev->priv.eswitch;
1286 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1287 uplink_priv = &rpriv->uplink_priv;
1288
1289 mutex_lock(&uplink_priv->unready_flows_lock);
1290 unready_flow_del(flow);
1291 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1292}
1293
10742efc
VB		 1294static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1295
a508728a 1296bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1297{
1298 struct mlx5_core_dev *out_mdev, *route_mdev;
1299 struct mlx5e_priv *out_priv, *route_priv;
1300
1301 out_priv = netdev_priv(out_dev);
1302 out_mdev = out_priv->mdev;
1303 route_priv = netdev_priv(route_dev);
1304 route_mdev = route_priv->mdev;
1305
1306 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1307 route_mdev->coredev_type != MLX5_COREDEV_VF)
1308 return false;
1309
1310 return same_hw_devs(out_priv, route_priv);
1311}
1312
a508728a 1313int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1314{
1315 struct mlx5e_priv *out_priv, *route_priv;
1316 struct mlx5_core_dev *route_mdev;
1317 struct mlx5_eswitch *esw;
1318 u16 vhca_id;
1319 int err;
1320
1321 out_priv = netdev_priv(out_dev);
1322 esw = out_priv->mdev->priv.eswitch;
1323 route_priv = netdev_priv(route_dev);
1324 route_mdev = route_priv->mdev;
1325
1326 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1327 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1328 return err;
1329}
1330
c7b9038d
VB		 1331int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1332 struct mlx5e_tc_flow_parse_attr *parse_attr,
1333 struct mlx5e_tc_flow *flow)
1334{
1335 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1336 struct mlx5_modify_hdr *mod_hdr;
1337
1338 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1339 get_flow_name_space(flow),
1340 mod_hdr_acts->num_actions,
1341 mod_hdr_acts->actions);
1342 if (IS_ERR(mod_hdr))
1343 return PTR_ERR(mod_hdr);
1344
1345 WARN_ON(flow->attr->modify_hdr);
1346 flow->attr->modify_hdr = mod_hdr;
1347
1348 return 0;
1349}
1350
c83954ab 1351static int
74491de9 1352mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1353 struct mlx5e_tc_flow *flow,
1354 struct netlink_ext_ack *extack)
adb4c123
OG		 1355{
1356 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1357 struct mlx5e_tc_flow_parse_attr *parse_attr;
1358 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1359 bool vf_tun = false, encap_valid = true;
fe7738eb 1360 struct net_device *encap_dev = NULL;
c620b772 1361 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1362 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1363 struct mlx5e_rep_priv *rpriv;
1364 struct mlx5e_priv *out_priv;
39ac237c 1365 u32 max_prio, max_chain;
0ad060ee 1366 int err = 0;
f493f155 1367 int out_index;
8b32580d 1368
84179981
PB		 1369 /* We check chain range only for tc flows.
1370 * For ft flows, we checked attr->chain was originally 0 and set it to
1371 * FDB_FT_CHAIN which is outside tc range.
1372 * See mlx5e_rep_setup_ft_cb().
1373 */
ae430332 1374 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1375 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1376 NL_SET_ERR_MSG_MOD(extack,
1377 "Requested chain is out of supported range");
8914add2
VB		 1378 err = -EOPNOTSUPP;
1379 goto err_out;
bf07aa73
PB		 1380 }
1381
ae430332 1382 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1383 if (attr->prio > max_prio) {
61644c3d
RD		 1384 NL_SET_ERR_MSG_MOD(extack,
1385 "Requested priority is out of supported range");
8914add2
VB		 1386 err = -EOPNOTSUPP;
1387 goto err_out;
bf07aa73 1388 }
e52c2802 1389
777bb800
VB		 1390 if (flow_flag_test(flow, TUN_RX)) {
1391 err = mlx5e_attach_decap_route(priv, flow);
1392 if (err)
8914add2 1393 goto err_out;
777bb800
VB		 1394 }
1395
14e6b038
EC		 1396 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1397 err = mlx5e_attach_decap(priv, flow, extack);
1398 if (err)
8914add2 1399 goto err_out;
14e6b038
EC		 1400 }
1401
c620b772
AL		 1402 parse_attr = attr->parse_attr;
1403 esw_attr = attr->esw_attr;
1404
f493f155 1405 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1406 struct net_device *out_dev;
8c4dc42b
EB		 1407 int mirred_ifindex;
1408
c620b772 1409 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1410 continue;
1411
7040632d 1412 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1413 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1414 if (!out_dev) {
1415 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1416 err = -ENODEV;
1417 goto err_out;
1418 }
733d4f36 1419 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1420 extack, &encap_dev, &encap_valid);
fe7738eb 1421 dev_put(out_dev);
0ad060ee 1422 if (err)
8914add2 1423 goto err_out;
0ad060ee 1424
8914add2
VB		 1425 if (esw_attr->dests[out_index].flags &
1426 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1427 vf_tun = true;
3c37745e
OG		 1428 out_priv = netdev_priv(encap_dev);
1429 rpriv = out_priv->ppriv;
c620b772
AL		 1430 esw_attr->dests[out_index].rep = rpriv->rep;
1431 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1432 }
1433
7d1a3d08
VB		 1434 if (vf_tun && esw_attr->out_count > 1) {
1435 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1436 err = -EOPNOTSUPP;
1437 goto err_out;
1438 }
1439
8b32580d 1440 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1441 if (err)
8914add2 1442 goto err_out;
adb4c123 1443
d5a3c2b6
RD		 1444 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1445 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1446 if (vf_tun) {
1447 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1448 if (err)
1449 goto err_out;
1450 } else {
1451 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1452 if (err)
1453 goto err_out;
1454 }
d7e75a32
OG		 1455 }
1456
b8aee822 1457 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1458 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1459 if (IS_ERR(counter)) {
1460 err = PTR_ERR(counter);
1461 goto err_out;
1462 }
b8aee822
MB		 1463
1464 attr->counter = counter;
1465 }
1466
0ad060ee
RD		 1467 /* we get here if one of the following takes place:
1468 * (1) there's no error
1469 * (2) there's an encap action and we don't have valid neigh
3c37745e 1470 */
bc1d75fa 1471 if (!encap_valid)
178f69b4 1472 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1473 else
6d2a3ed0 1474 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1475
8914add2
VB		 1476 if (IS_ERR(flow->rule[0])) {
1477 err = PTR_ERR(flow->rule[0]);
1478 goto err_out;
1479 }
1480 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1481
1482 return 0;
8914add2
VB		 1483
1484err_out:
1485 flow_flag_set(flow, FAILED);
1486 return err;
aa0cbbae 1487}
d85cdccb 1488
9272e3df
YK		 1489static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1490{
c620b772 1491 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1492 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1493 spec->match_value,
1494 misc_parameters_3);
1495 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1496 headers_v,
1497 geneve_tlv_option_0_data);
1498
1499 return !!geneve_tlv_opt_0_data;
1500}
1501
d85cdccb
OG		 1502static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1503 struct mlx5e_tc_flow *flow)
1504{
1505 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1506 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1507 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1508 bool vf_tun = false;
f493f155 1509 int out_index;
d85cdccb 1510
777bb800 1511 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1512 mlx5e_put_flow_tunnel_id(flow);
1513
12a240a4 1514 if (flow_flag_test(flow, NOT_READY))
b4a23329 1515 remove_unready_flow(flow);
ef06c9ee 1516
226f2ca3
VB		 1517 if (mlx5e_is_offloaded_flow(flow)) {
1518 if (flow_flag_test(flow, SLOW))
178f69b4 1519 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1520 else
1521 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1522 }
d85cdccb 1523
9272e3df
YK		 1524 if (mlx5_flow_has_geneve_opt(flow))
1525 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1526
513f8f7f 1527 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1528
777bb800
VB		 1529 if (flow->decap_route)
1530 mlx5e_detach_decap_route(priv, flow);
1531
1532 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1533 if (esw_attr->dests[out_index].flags &
1534 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1535 vf_tun = true;
777bb800 1536 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1537 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1538 kfree(attr->parse_attr->tun_info[out_index]);
1539 }
777bb800 1540 }
d7e75a32 1541
aedd133d 1542 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1543
c7b9038d
VB		 1544 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1545 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1546 if (vf_tun && attr->modify_hdr)
1547 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1548 else
1549 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1550 }
8914add2
VB		 1551 kvfree(attr->parse_attr);
1552 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1553
1554 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1555 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1556
1557 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1558 mlx5e_detach_decap(priv, flow);
c620b772 1559
41c2fd94 1560 kfree(flow->attr->esw_attr->sample);
c620b772 1561 kfree(flow->attr);
d85cdccb
OG		 1562}
1563
0d9f9647 1564struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1565{
c620b772 1566 return flow->attr->counter;
b8aee822
MB		 1567}
1568
6a06c2f7 1569/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1570void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1571{
1572 struct mlx5e_tc_flow *flow, *tmp;
1573
1574 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1575 mlx5e_flow_put(priv, flow);
1576}
1577
04de7dda
RD		 1578static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1579{
1580 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1581
226f2ca3
VB		 1582 if (!flow_flag_test(flow, ESWITCH) ||
1583 !flow_flag_test(flow, DUP))
04de7dda
RD		 1584 return;
1585
1586 mutex_lock(&esw->offloads.peer_mutex);
1587 list_del(&flow->peer);
1588 mutex_unlock(&esw->offloads.peer_mutex);
1589
226f2ca3 1590 flow_flag_clear(flow, DUP);
04de7dda 1591
eb252c3a
RD		 1592 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1593 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1594 kfree(flow->peer_flow);
1595 }
1596
04de7dda
RD		 1597 flow->peer_flow = NULL;
1598}
1599
1600static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1601{
1602 struct mlx5_core_dev *dev = flow->priv->mdev;
1603 struct mlx5_devcom *devcom = dev->priv.devcom;
1604 struct mlx5_eswitch *peer_esw;
1605
1606 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1607 if (!peer_esw)
1608 return;
1609
1610 __mlx5e_tc_del_fdb_peer_flow(flow);
1611 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1612}
1613
e8f887ac 1614static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1615 struct mlx5e_tc_flow *flow)
e8f887ac 1616{
226f2ca3 1617 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1618 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1619 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1620 } else {
d85cdccb 1621 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1622 }
e8f887ac
AV		 1623}
1624
0a7fcb78
PB		 1625static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1626{
1627 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1628 struct flow_action *flow_action = &rule->action;
1629 const struct flow_action_entry *act;
1630 int i;
1631
1632 flow_action_for_each(i, act, flow_action) {
1633 switch (act->id) {
1634 case FLOW_ACTION_GOTO:
1635 return true;
1636 default:
1637 continue;
1638 }
1639 }
1640
1641 return false;
1642}
bbd00f7e 1643
0a7fcb78
PB		 1644static int
1645enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1646 struct flow_dissector_key_enc_opts *opts,
1647 struct netlink_ext_ack *extack,
1648 bool *dont_care)
1649{
1650 struct geneve_opt *opt;
1651 int off = 0;
1652
1653 *dont_care = true;
1654
1655 while (opts->len > off) {
1656 opt = (struct geneve_opt *)&opts->data[off];
1657
1658 if (!(*dont_care) || opt->opt_class || opt->type ||
1659 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1660 *dont_care = false;
1661
c51323ee 1662 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1663 opt->type != U8_MAX) {
0a7fcb78
PB		 1664 NL_SET_ERR_MSG(extack,
1665 "Partial match of tunnel options in chain > 0 isn't supported");
1666 netdev_warn(priv->netdev,
1667 "Partial match of tunnel options in chain > 0 isn't supported");
1668 return -EOPNOTSUPP;
1669 }
1670 }
1671
1672 off += sizeof(struct geneve_opt) + opt->length * 4;
1673 }
1674
1675 return 0;
1676}
1677
1678#define COPY_DISSECTOR(rule, diss_key, dst)\
1679({ \
1680 struct flow_rule *__rule = (rule);\
1681 typeof(dst) __dst = dst;\
1682\
1683 memcpy(__dst,\
1684 skb_flow_dissector_target(__rule->match.dissector,\
1685 diss_key,\
1686 __rule->match.key),\
1687 sizeof(*__dst));\
1688})
1689
1690static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1691 struct mlx5e_tc_flow *flow,
1692 struct flow_cls_offload *f,
1693 struct net_device *filter_dev)
bbd00f7e 1694{
f9e30088 1695 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1696 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1697 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1698 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1699 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1700 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1701 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1702 struct mlx5e_rep_priv *uplink_rpriv;
1703 struct tunnel_match_key tunnel_key;
1704 bool enc_opts_is_dont_care = true;
1705 u32 tun_id, enc_opts_id = 0;
1706 struct mlx5_eswitch *esw;
1707 u32 value, mask;
8f256622 1708 int err;
2e72eb43 1709
0a7fcb78
PB		 1710 esw = priv->mdev->priv.eswitch;
1711 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1712 uplink_priv = &uplink_rpriv->uplink_priv;
1713
1714 memset(&tunnel_key, 0, sizeof(tunnel_key));
1715 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1716 &tunnel_key.enc_control);
1717 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1718 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1719 &tunnel_key.enc_ipv4);
1720 else
1721 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1722 &tunnel_key.enc_ipv6);
1723 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1724 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1725 &tunnel_key.enc_tp);
1726 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1727 &tunnel_key.enc_key_id);
1728 tunnel_key.filter_ifindex = filter_dev->ifindex;
1729
1730 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1731 if (err)
101f4de9 1732 return err;
bbd00f7e 1733
0a7fcb78
PB		 1734 flow_rule_match_enc_opts(rule, &enc_opts_match);
1735 err = enc_opts_is_dont_care_or_full_match(priv,
1736 enc_opts_match.mask,
1737 extack,
1738 &enc_opts_is_dont_care);
1739 if (err)
1740 goto err_enc_opts;
fe1587a7 1741
0a7fcb78 1742 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1743 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1744 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1745 sizeof(*enc_opts_match.key));
1746 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1747 sizeof(*enc_opts_match.mask));
1748
0a7fcb78 1749 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1750 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1751 if (err)
1752 goto err_enc_opts;
1753 }
fe1587a7 1754
0a7fcb78
PB		 1755 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1756 mask = enc_opts_id ? TUNNEL_ID_MASK :
1757 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1758
0a7fcb78
PB		 1759 if (attr->chain) {
1760 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1761 TUNNEL_TO_REG, value, mask);
1762 } else {
1763 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1764 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1765 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1766 TUNNEL_TO_REG, value);
1767 if (err)
1768 goto err_set;
fe1587a7 1769
0a7fcb78 1770 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1771 }
bbd00f7e 1772
0a7fcb78
PB		 1773 flow->tunnel_id = value;
1774 return 0;
bcef735c 1775
0a7fcb78
PB		 1776err_set:
1777 if (enc_opts_id)
1778 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1779 enc_opts_id);
1780err_enc_opts:
1781 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1782 return err;
1783}
bcef735c 1784
0a7fcb78
PB		 1785static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1786{
1787 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1788 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1789 struct mlx5_rep_uplink_priv *uplink_priv;
1790 struct mlx5e_rep_priv *uplink_rpriv;
1791 struct mlx5_eswitch *esw;
bcef735c 1792
0a7fcb78
PB		 1793 esw = flow->priv->mdev->priv.eswitch;
1794 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1795 uplink_priv = &uplink_rpriv->uplink_priv;
1796
1797 if (tun_id)
1798 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1799 if (enc_opts_id)
1800 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1801 enc_opts_id);
1802}
e98bedf5 1803
4c3844d9
PB		 1804u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1805{
1806 return flow->tunnel_id;
1807}
1808
fca53304
EB		 1809void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1810 struct flow_match_basic *match, bool outer,
1811 void *headers_c, void *headers_v)
1812{
1813 bool ip_version_cap;
1814
1815 ip_version_cap = outer ?
1816 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1817 ft_field_support.outer_ip_version) :
1818 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1819 ft_field_support.inner_ip_version);
1820
1821 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1822 (match->key->n_proto == htons(ETH_P_IP) ||
1823 match->key->n_proto == htons(ETH_P_IPV6))) {
1824 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1825 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1826 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1827 } else {
1828 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1829 ntohs(match->mask->n_proto));
1830 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1831 ntohs(match->key->n_proto));
1832 }
4a5d5d73
EB		 1833}
1834
0d9f9647 1835u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1836{
1837 void *headers_v;
1838 u16 ethertype;
1839 u8 ip_version;
1840
1841 if (outer)
1842 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1843 else
1844 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1845
1846 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1847 /* Return ip_version converted from ethertype anyway */
1848 if (!ip_version) {
1849 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1850 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1851 ip_version = 4;
1852 else if (ethertype == ETH_P_IPV6)
1853 ip_version = 6;
1854 }
1855 return ip_version;
1856}
1857
bbd00f7e 1858static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1859 struct mlx5e_tc_flow *flow,
bbd00f7e 1860 struct mlx5_flow_spec *spec,
f9e30088 1861 struct flow_cls_offload *f,
0a7fcb78
PB		 1862 struct net_device *filter_dev,
1863 u8 *match_level,
1864 bool *match_inner)
bbd00f7e 1865{
a508728a 1866 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1867 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1868 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1869 bool needs_mapping, sets_mapping;
8f256622 1870 int err;
2e72eb43 1871
0a7fcb78
PB		 1872 if (!mlx5e_is_eswitch_flow(flow))
1873 return -EOPNOTSUPP;
1874
c620b772
AL		 1875 needs_mapping = !!flow->attr->chain;
1876 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 1877 *match_inner = !needs_mapping;
1878
1879 if ((needs_mapping || sets_mapping) &&
636bb968 1880 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1881 NL_SET_ERR_MSG(extack,
636bb968 1882 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1883 netdev_warn(priv->netdev,
636bb968 1884 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1885 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1886 }
1887
c620b772 1888 if (!flow->attr->chain) {
0a7fcb78
PB		 1889 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1890 match_level);
1891 if (err) {
e98bedf5 1892 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1893 "Failed to parse tunnel attributes");
1894 netdev_warn(priv->netdev,
1895 "Failed to parse tunnel attributes");
1896 return err;
e98bedf5
EB		 1897 }
1898
14e6b038
EC		 1899 /* With mpls over udp we decapsulate using packet reformat
1900 * object
1901 */
1902 if (!netif_is_bareudp(filter_dev))
c620b772 1903 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1904 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1905 if (err)
1906 return err;
1907 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1908 struct mlx5_flow_spec *tmp_spec;
1909
1910 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1911 if (!tmp_spec) {
1912 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1913 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1914 return -ENOMEM;
1915 }
1916 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1917
1918 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1919 if (err) {
1920 kvfree(tmp_spec);
1921 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1922 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1923 return err;
1924 }
1925 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1926 kvfree(tmp_spec);
1927 if (err)
1928 return err;
bcef735c
OG		 1929 }
1930
0a7fcb78
PB		 1931 if (!needs_mapping && !sets_mapping)
1932 return 0;
bbd00f7e 1933
0a7fcb78 1934 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1935}
bbd00f7e 1936
0a7fcb78 1937static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1938{
0a7fcb78
PB		 1939 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1940 inner_headers);
bbd00f7e
HHZ		 1941}
1942
0a7fcb78 1943static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1944{
0a7fcb78
PB		 1945 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1946 inner_headers);
1947}
1948
1949static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1950{
1951 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1952 outer_headers);
1953}
1954
1955static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1956{
1957 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1958 outer_headers);
8377629e
EB		 1959}
1960
1961static void *get_match_headers_value(u32 flags,
1962 struct mlx5_flow_spec *spec)
1963{
1964 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1965 get_match_inner_headers_value(spec) :
1966 get_match_outer_headers_value(spec);
1967}
1968
1969static void *get_match_headers_criteria(u32 flags,
1970 struct mlx5_flow_spec *spec)
1971{
1972 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1973 get_match_inner_headers_criteria(spec) :
1974 get_match_outer_headers_criteria(spec);
8377629e
EB		 1975}
1976
6d65bc64 1977static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1978 struct flow_cls_offload *f)
1979{
1980 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1981 struct netlink_ext_ack *extack = f->common.extack;
1982 struct net_device *ingress_dev;
1983 struct flow_match_meta match;
1984
1985 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1986 return 0;
1987
1988 flow_rule_match_meta(rule, &match);
e3e0f9b2 1989 if (!match.mask->ingress_ifindex)
1990 return 0;
1991
6d65bc64 1992 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1993 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 1994 return -EOPNOTSUPP;
6d65bc64 1995 }
1996
1997 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1998 match.key->ingress_ifindex);
1999 if (!ingress_dev) {
2000 NL_SET_ERR_MSG_MOD(extack,
2001 "Can't find the ingress port to match on");
a683012a 2002 return -ENOENT;
6d65bc64 2003 }
2004
2005 if (ingress_dev != filter_dev) {
2006 NL_SET_ERR_MSG_MOD(extack,
2007 "Can't match on the ingress filter port");
a683012a 2008 return -EOPNOTSUPP;
6d65bc64 2009 }
2010
2011 return 0;
2012}
2013
72046a91
EC		 2014static bool skip_key_basic(struct net_device *filter_dev,
2015 struct flow_cls_offload *f)
2016{
2017 /* When doing mpls over udp decap, the user needs to provide
2018 * MPLS_UC as the protocol in order to be able to match on mpls
2019 * label fields. However, the actual ethertype is IP so we want to
2020 * avoid matching on this, otherwise we'll fail the match.
2021 */
2022 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2023 return true;
2024
2025 return false;
2026}
2027
de0af0bf 2028static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2029 struct mlx5e_tc_flow *flow,
de0af0bf 2030 struct mlx5_flow_spec *spec,
f9e30088 2031 struct flow_cls_offload *f,
54c177ca 2032 struct net_device *filter_dev,
93b3586e 2033 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2034{
e98bedf5 2035 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2036 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2037 outer_headers);
2038 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2039 outer_headers);
699e96dd
JL		 2040 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2041 misc_parameters);
2042 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2043 misc_parameters);
a3222a2d
MD		 2044 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2045 misc_parameters_3);
2046 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2047 misc_parameters_3);
f9e30088 2048 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2049 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2050 enum fs_flow_table_type fs_type;
e3a2b7ed
AV		 2051 u16 addr_type = 0;
2052 u8 ip_proto = 0;
93b3586e 2053 u8 *match_level;
6d65bc64 2054 int err;
e3a2b7ed 2055
afe93f71 2056 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2057 match_level = outer_match_level;
de0af0bf 2058
8f256622 2059 if (dissector->used_keys &
3d144578
VB		 2060 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2061 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2062 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2063 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2064 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2065 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2066 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2067 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2068 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2069 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2070 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2071 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2072 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2073 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2074 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2075 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2076 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2077 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2078 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2079 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2080 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2081 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2082 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2083 dissector->used_keys);
e3a2b7ed
AV		 2084 return -EOPNOTSUPP;
2085 }
2086
075973c7 2087 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2088 bool match_inner = false;
bbd00f7e 2089
0a7fcb78
PB		 2090 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2091 outer_match_level, &match_inner);
2092 if (err)
2093 return err;
2094
2095 if (match_inner) {
2096 /* header pointers should point to the inner headers
2097 * if the packet was decapsulated already.
2098 * outer headers are set by parse_tunnel_attr.
2099 */
2100 match_level = inner_match_level;
2101 headers_c = get_match_inner_headers_criteria(spec);
2102 headers_v = get_match_inner_headers_value(spec);
2103 }
bbd00f7e
HHZ		 2104 }
2105
6d65bc64 2106 err = mlx5e_flower_parse_meta(filter_dev, f);
2107 if (err)
2108 return err;
2109
72046a91
EC		 2110 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2111 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2112 struct flow_match_basic match;
2113
2114 flow_rule_match_basic(rule, &match);
fca53304
EB		 2115 mlx5e_tc_set_ethertype(priv->mdev, &match,
2116 match_level == outer_match_level,
2117 headers_c, headers_v);
e3a2b7ed 2118
8f256622 2119 if (match.mask->n_proto)
d708f902 2120 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2121 }
35a605db
EB		 2122 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2123 is_vlan_dev(filter_dev)) {
2124 struct flow_dissector_key_vlan filter_dev_mask;
2125 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2126 struct flow_match_vlan match;
2127
35a605db
EB		 2128 if (is_vlan_dev(filter_dev)) {
2129 match.key = &filter_dev_key;
2130 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2131 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2132 match.key->vlan_priority = 0;
2133 match.mask = &filter_dev_mask;
2134 memset(match.mask, 0xff, sizeof(*match.mask));
2135 match.mask->vlan_priority = 0;
2136 } else {
2137 flow_rule_match_vlan(rule, &match);
2138 }
8f256622
PNA		 2139 if (match.mask->vlan_id ||
2140 match.mask->vlan_priority ||
2141 match.mask->vlan_tpid) {
2142 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2143 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2144 svlan_tag, 1);
2145 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2146 svlan_tag, 1);
2147 } else {
2148 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2149 cvlan_tag, 1);
2150 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2151 cvlan_tag, 1);
2152 }
095b6cfd 2153
8f256622
PNA		 2154 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2155 match.mask->vlan_id);
2156 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2157 match.key->vlan_id);
358d79a4 2158
8f256622
PNA		 2159 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2160 match.mask->vlan_priority);
2161 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2162 match.key->vlan_priority);
54782900 2163
d708f902 2164 *match_level = MLX5_MATCH_L2;
54782900 2165 }
d3a80bb5 2166 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2167 /* cvlan_tag enabled in match criteria and
2168 * disabled in match value means both S & C tags
2169 * don't exist (untagged of both)
2170 */
cee26487 2171 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2172 *match_level = MLX5_MATCH_L2;
54782900
OG		 2173 }
2174
8f256622
PNA		 2175 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2176 struct flow_match_vlan match;
2177
12d5cbf8 2178 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2179 if (match.mask->vlan_id ||
2180 match.mask->vlan_priority ||
2181 match.mask->vlan_tpid) {
afe93f71
RD		 2182 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2183 fs_type)) {
2184 NL_SET_ERR_MSG_MOD(extack,
2185 "Matching on CVLAN is not supported");
2186 return -EOPNOTSUPP;
2187 }
2188
8f256622 2189 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2190 MLX5_SET(fte_match_set_misc, misc_c,
2191 outer_second_svlan_tag, 1);
2192 MLX5_SET(fte_match_set_misc, misc_v,
2193 outer_second_svlan_tag, 1);
2194 } else {
2195 MLX5_SET(fte_match_set_misc, misc_c,
2196 outer_second_cvlan_tag, 1);
2197 MLX5_SET(fte_match_set_misc, misc_v,
2198 outer_second_cvlan_tag, 1);
2199 }
2200
2201 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2202 match.mask->vlan_id);
699e96dd 2203 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2204 match.key->vlan_id);
699e96dd 2205 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2206 match.mask->vlan_priority);
699e96dd 2207 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2208 match.key->vlan_priority);
699e96dd
JL		 2209
2210 *match_level = MLX5_MATCH_L2;
0faddfe6 2211 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2212 }
2213 }
2214
8f256622
PNA		 2215 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2216 struct flow_match_eth_addrs match;
54782900 2217
8f256622 2218 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2219 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2220 dmac_47_16),
8f256622 2221 match.mask->dst);
d3a80bb5
OG		 2222 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2223 dmac_47_16),
8f256622 2224 match.key->dst);
d3a80bb5
OG		 2225
2226 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2227 smac_47_16),
8f256622 2228 match.mask->src);
d3a80bb5
OG		 2229 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2230 smac_47_16),
8f256622 2231 match.key->src);
d3a80bb5 2232
8f256622
PNA		 2233 if (!is_zero_ether_addr(match.mask->src) ||
2234 !is_zero_ether_addr(match.mask->dst))
d708f902 2235 *match_level = MLX5_MATCH_L2;
54782900
OG		 2236 }
2237
8f256622
PNA		 2238 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2239 struct flow_match_control match;
54782900 2240
8f256622
PNA		 2241 flow_rule_match_control(rule, &match);
2242 addr_type = match.key->addr_type;
54782900
OG		 2243
2244 /* the HW doesn't support frag first/later */
8f256622 2245 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2246 return -EOPNOTSUPP;
2247
8f256622 2248 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2249 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2250 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2251 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2252
2253 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2254 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2255 *match_level = MLX5_MATCH_L2;
54782900
OG		 2256 /* *** L2 attributes parsing up to here *** */
2257 else
83621b7d 2258 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2259 }
2260 }
2261
8f256622
PNA		 2262 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2263 struct flow_match_basic match;
2264
2265 flow_rule_match_basic(rule, &match);
2266 ip_proto = match.key->ip_proto;
54782900
OG		 2267
2268 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2269 match.mask->ip_proto);
54782900 2270 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2271 match.key->ip_proto);
54782900 2272
8f256622 2273 if (match.mask->ip_proto)
d708f902 2274 *match_level = MLX5_MATCH_L3;
54782900
OG		 2275 }
2276
e3a2b7ed 2277 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2278 struct flow_match_ipv4_addrs match;
e3a2b7ed 2279
8f256622 2280 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2281 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2282 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2283 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2284 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2285 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2286 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2287 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2288 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2289 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2290 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2291 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2292 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2293
8f256622 2294 if (match.mask->src || match.mask->dst)
d708f902 2295 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2296 }
2297
2298 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2299 struct flow_match_ipv6_addrs match;
e3a2b7ed 2300
8f256622 2301 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2302 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2303 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2304 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2305 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2306 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2307 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2308
2309 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2310 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2311 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2312 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2313 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2314 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2315
8f256622
PNA		 2316 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2317 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2318 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2319 }
2320
8f256622
PNA		 2321 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2322 struct flow_match_ip match;
1f97a526 2323
8f256622
PNA		 2324 flow_rule_match_ip(rule, &match);
2325 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2326 match.mask->tos & 0x3);
2327 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2328 match.key->tos & 0x3);
1f97a526 2329
8f256622
PNA		 2330 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2331 match.mask->tos >> 2);
2332 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2333 match.key->tos >> 2);
1f97a526 2334
8f256622
PNA		 2335 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2336 match.mask->ttl);
2337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2338 match.key->ttl);
1f97a526 2339
8f256622 2340 if (match.mask->ttl &&
a8ade55f 2341 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2342 ft_field_support.outer_ipv4_ttl)) {
2343 NL_SET_ERR_MSG_MOD(extack,
2344 "Matching on TTL is not supported");
1f97a526 2345 return -EOPNOTSUPP;
e98bedf5 2346 }
a8ade55f 2347
8f256622 2348 if (match.mask->tos || match.mask->ttl)
d708f902 2349 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2350 }
2351
54782900
OG		 2352 /* *** L3 attributes parsing up to here *** */
2353
8f256622
PNA		 2354 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2355 struct flow_match_ports match;
2356
2357 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2358 switch (ip_proto) {
2359 case IPPROTO_TCP:
2360 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2361 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2362 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2363 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2364
2365 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2366 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2367 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2368 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2369 break;
2370
2371 case IPPROTO_UDP:
2372 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2373 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2374 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2375 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2376
2377 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2378 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2379 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2380 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2381 break;
2382 default:
e98bedf5
EB		 2383 NL_SET_ERR_MSG_MOD(extack,
2384 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2385 netdev_err(priv->netdev,
2386 "Only UDP and TCP transport are supported\n");
2387 return -EINVAL;
2388 }
de0af0bf 2389
8f256622 2390 if (match.mask->src || match.mask->dst)
d708f902 2391 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2392 }
2393
8f256622
PNA		 2394 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2395 struct flow_match_tcp match;
e77834ec 2396
8f256622 2397 flow_rule_match_tcp(rule, &match);
e77834ec 2398 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2399 ntohs(match.mask->flags));
e77834ec 2400 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2401 ntohs(match.key->flags));
e77834ec 2402
8f256622 2403 if (match.mask->flags)
d708f902 2404 *match_level = MLX5_MATCH_L4;
e77834ec 2405 }
a3222a2d
MD		 2406 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2407 struct flow_match_icmp match;
e77834ec 2408
a3222a2d
MD		 2409 flow_rule_match_icmp(rule, &match);
2410 switch (ip_proto) {
2411 case IPPROTO_ICMP:
2412 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2413 MLX5_FLEX_PROTO_ICMP))
2414 return -EOPNOTSUPP;
2415 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2416 match.mask->type);
2417 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2418 match.key->type);
2419 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2420 match.mask->code);
2421 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2422 match.key->code);
2423 break;
2424 case IPPROTO_ICMPV6:
2425 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2426 MLX5_FLEX_PROTO_ICMPV6))
2427 return -EOPNOTSUPP;
2428 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2429 match.mask->type);
2430 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2431 match.key->type);
2432 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2433 match.mask->code);
2434 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2435 match.key->code);
2436 break;
2437 default:
2438 NL_SET_ERR_MSG_MOD(extack,
2439 "Code and type matching only with ICMP and ICMPv6");
2440 netdev_err(priv->netdev,
2441 "Code and type matching only with ICMP and ICMPv6\n");
2442 return -EINVAL;
2443 }
2444 if (match.mask->code || match.mask->type) {
2445 *match_level = MLX5_MATCH_L4;
2446 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2447 }
2448 }
7d6c86e3
AH		 2449 /* Currenlty supported only for MPLS over UDP */
2450 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2451 !netif_is_bareudp(filter_dev)) {
2452 NL_SET_ERR_MSG_MOD(extack,
2453 "Matching on MPLS is supported only for MPLS over UDP");
2454 netdev_err(priv->netdev,
2455 "Matching on MPLS is supported only for MPLS over UDP\n");
2456 return -EOPNOTSUPP;
2457 }
2458
e3a2b7ed
AV		 2459 return 0;
2460}
2461
de0af0bf 2462static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2463 struct mlx5e_tc_flow *flow,
de0af0bf 2464 struct mlx5_flow_spec *spec,
f9e30088 2465 struct flow_cls_offload *f,
54c177ca 2466 struct net_device *filter_dev)
de0af0bf 2467{
93b3586e 2468 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2469 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2470 struct mlx5_core_dev *dev = priv->mdev;
2471 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2472 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2473 struct mlx5_eswitch_rep *rep;
226f2ca3 2474 bool is_eswitch_flow;
de0af0bf
RD		 2475 int err;
2476
93b3586e
HN		 2477 inner_match_level = MLX5_MATCH_NONE;
2478 outer_match_level = MLX5_MATCH_NONE;
2479
0a7fcb78
PB		 2480 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2481 &inner_match_level, &outer_match_level);
93b3586e
HN		 2482 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2483 outer_match_level : inner_match_level;
de0af0bf 2484
226f2ca3
VB		 2485 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2486 if (!err && is_eswitch_flow) {
1d447a39 2487 rep = rpriv->rep;
b05af6aa 2488 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2489 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2490 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2491 NL_SET_ERR_MSG_MOD(extack,
2492 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2493 netdev_warn(priv->netdev,
2494 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2495 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2496 return -EOPNOTSUPP;
2497 }
2498 }
2499
c620b772
AL		 2500 flow->attr->inner_match_level = inner_match_level;
2501 flow->attr->outer_match_level = outer_match_level;
2502
38aa51c1 2503
de0af0bf
RD		 2504 return err;
2505}
2506
d79b6df6
OG		 2507struct pedit_headers {
2508 struct ethhdr eth;
0eb69bb9 2509 struct vlan_hdr vlan;
d79b6df6
OG		 2510 struct iphdr ip4;
2511 struct ipv6hdr ip6;
2512 struct tcphdr tcp;
2513 struct udphdr udp;
2514};
2515
c500c86b
PNA		 2516struct pedit_headers_action {
2517 struct pedit_headers vals;
2518 struct pedit_headers masks;
2519 u32 pedits;
2520};
2521
d79b6df6 2522static int pedit_header_offsets[] = {
73867881
PNA		 2523 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2524 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2525 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2526 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2527 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2528};
2529
2530#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2531
2532static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2533 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2534{
2535 u32 *curr_pmask, *curr_pval;
2536
c500c86b
PNA		 2537 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2538 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2539
2540 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2541 goto out_err;
2542
2543 *curr_pmask |= mask;
2544 *curr_pval |= (val & mask);
2545
2546 return 0;
2547
2548out_err:
2549 return -EOPNOTSUPP;
2550}
2551
2552struct mlx5_fields {
2553 u8 field;
88f30bbc
DL		 2554 u8 field_bsize;
2555 u32 field_mask;
d79b6df6 2556 u32 offset;
27c11b6b 2557 u32 match_offset;
d79b6df6
OG		 2558};
2559
88f30bbc
DL		 2560#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2561 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2562 offsetof(struct pedit_headers, field) + (off), \
2563 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2564
2ef86872
EB		 2565/* masked values are the same and there are no rewrites that do not have a
2566 * match.
2567 */
2568#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2569 type matchmaskx = *(type *)(matchmaskp); \
2570 type matchvalx = *(type *)(matchvalp); \
2571 type maskx = *(type *)(maskp); \
2572 type valx = *(type *)(valp); \
2573 \
2574 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2575 matchmaskx)); \
2576})
2577
27c11b6b 2578static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2579 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2580{
2581 bool same = false;
2582
88f30bbc
DL		 2583 switch (bsize) {
2584 case 8:
2ef86872 2585 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2586 break;
88f30bbc 2587 case 16:
2ef86872 2588 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2589 break;
88f30bbc 2590 case 32:
2ef86872 2591 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2592 break;
2593 }
2594
2595 return same;
2596}
a8e4f0c4 2597
d79b6df6 2598static struct mlx5_fields fields[] = {
88f30bbc
DL		 2599 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2600 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2601 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2602 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2603 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2604 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2605
ab9341b5 2606 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2607 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2608 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2609 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2610
2611 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2612 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2613 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2614 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2615 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2616 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2617 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2618 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2619 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2620 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2621 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2622 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2623 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2624 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2625 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2626 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2627 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2628 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2629
88f30bbc
DL		 2630 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2631 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2632 /* in linux iphdr tcp_flags is 8 bits long */
2633 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2634
88f30bbc
DL		 2635 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2636 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2637};
2638
82198d8b
MD		 2639static unsigned long mask_to_le(unsigned long mask, int size)
2640{
2641 __be32 mask_be32;
2642 __be16 mask_be16;
2643
2644 if (size == 32) {
2645 mask_be32 = (__force __be32)(mask);
2646 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2647 } else if (size == 16) {
2648 mask_be32 = (__force __be32)(mask);
2649 mask_be16 = *(__be16 *)&mask_be32;
2650 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2651 }
2652
2653 return mask;
2654}
6ae4a6a5
PB		 2655static int offload_pedit_fields(struct mlx5e_priv *priv,
2656 int namespace,
2657 struct pedit_headers_action *hdrs,
e98bedf5 2658 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2659 u32 *action_flags,
e98bedf5 2660 struct netlink_ext_ack *extack)
d79b6df6
OG		 2661{
2662 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2663 int i, action_size, first, last, next_z;
88f30bbc
DL		 2664 void *headers_c, *headers_v, *action, *vals_p;
2665 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2666 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2667 struct mlx5_fields *f;
82198d8b 2668 unsigned long mask, field_mask;
6ae4a6a5 2669 int err;
88f30bbc
DL		 2670 u8 cmd;
2671
6ae4a6a5 2672 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2673 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2674 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2675
73867881
PNA		 2676 set_masks = &hdrs[0].masks;
2677 add_masks = &hdrs[1].masks;
2678 set_vals = &hdrs[0].vals;
2679 add_vals = &hdrs[1].vals;
d79b6df6 2680
d65dbedf 2681 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2682
2683 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2684 bool skip;
2685
d79b6df6
OG		 2686 f = &fields[i];
2687 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2688 s_mask = 0;
2689 a_mask = 0;
d79b6df6
OG		 2690
2691 s_masks_p = (void *)set_masks + f->offset;
2692 a_masks_p = (void *)add_masks + f->offset;
2693
88f30bbc
DL		 2694 s_mask = *s_masks_p & f->field_mask;
2695 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2696
2697 if (!s_mask && !a_mask) /* nothing to offload here */
2698 continue;
2699
2700 if (s_mask && a_mask) {
e98bedf5
EB		 2701 NL_SET_ERR_MSG_MOD(extack,
2702 "can't set and add to the same HW field");
d79b6df6
OG		 2703 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2704 return -EOPNOTSUPP;
2705 }
2706
27c11b6b 2707 skip = false;
d79b6df6 2708 if (s_mask) {
27c11b6b
EB		 2709 void *match_mask = headers_c + f->match_offset;
2710 void *match_val = headers_v + f->match_offset;
2711
d79b6df6
OG		 2712 cmd = MLX5_ACTION_TYPE_SET;
2713 mask = s_mask;
2714 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2715 /* don't rewrite if we have a match on the same value */
2716 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2717 match_mask, f->field_bsize))
27c11b6b 2718 skip = true;
d79b6df6 2719 /* clear to denote we consumed this field */
88f30bbc 2720 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2721 } else {
2722 cmd = MLX5_ACTION_TYPE_ADD;
2723 mask = a_mask;
2724 vals_p = (void *)add_vals + f->offset;
27c11b6b 2725 /* add 0 is no change */
88f30bbc 2726 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2727 skip = true;
d79b6df6 2728 /* clear to denote we consumed this field */
88f30bbc 2729 *a_masks_p &= ~f->field_mask;
d79b6df6 2730 }
27c11b6b
EB		 2731 if (skip)
2732 continue;
d79b6df6 2733
82198d8b 2734 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2735
88f30bbc
DL		 2736 first = find_first_bit(&mask, f->field_bsize);
2737 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2738 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2739 if (first < next_z && next_z < last) {
e98bedf5
EB		 2740 NL_SET_ERR_MSG_MOD(extack,
2741 "rewrite of few sub-fields isn't supported");
2b64beba 2742 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2743 mask);
2744 return -EOPNOTSUPP;
2745 }
2746
6ae4a6a5
PB		 2747 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2748 if (err) {
2749 NL_SET_ERR_MSG_MOD(extack,
2750 "too many pedit actions, can't offload");
2751 mlx5_core_warn(priv->mdev,
2752 "mlx5: parsed %d pedit actions, can't do more\n",
2753 mod_acts->num_actions);
2754 return err;
2755 }
2756
2757 action = mod_acts->actions +
2758 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2759 MLX5_SET(set_action_in, action, action_type, cmd);
2760 MLX5_SET(set_action_in, action, field, f->field);
2761
2762 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2763 int start;
2764
82198d8b
MD		 2765 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2766
88f30bbc 2767 /* if field is bit sized it can start not from first bit */
82198d8b 2768 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2769
2770 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2771 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2772 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2773 }
2774
88f30bbc 2775 if (f->field_bsize == 32)
2b64beba 2776 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2777 else if (f->field_bsize == 16)
2b64beba 2778 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2779 else if (f->field_bsize == 8)
2b64beba 2780 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2781
6ae4a6a5 2782 ++mod_acts->num_actions;
d79b6df6
OG		 2783 }
2784
d79b6df6
OG		 2785 return 0;
2786}
2787
2cc1cb1d
TZ		 2788static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2789 int namespace)
2790{
2791 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2792 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2793 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2794 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2795}
2796
6ae4a6a5
PB		 2797int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2798 int namespace,
2799 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2800{
6ae4a6a5
PB		 2801 int action_size, new_num_actions, max_hw_actions;
2802 size_t new_sz, old_sz;
2803 void *ret;
d79b6df6 2804
6ae4a6a5
PB		 2805 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2806 return 0;
d79b6df6 2807
d65dbedf 2808 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2809
6ae4a6a5
PB		 2810 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2811 namespace);
2812 new_num_actions = min(max_hw_actions,
2813 mod_hdr_acts->actions ?
2814 mod_hdr_acts->max_actions * 2 : 1);
2815 if (mod_hdr_acts->max_actions == new_num_actions)
2816 return -ENOSPC;
2817
2818 new_sz = action_size * new_num_actions;
2819 old_sz = mod_hdr_acts->max_actions * action_size;
2820 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2821 if (!ret)
d79b6df6
OG		 2822 return -ENOMEM;
2823
6ae4a6a5
PB		 2824 memset(ret + old_sz, 0, new_sz - old_sz);
2825 mod_hdr_acts->actions = ret;
2826 mod_hdr_acts->max_actions = new_num_actions;
2827
d79b6df6
OG		 2828 return 0;
2829}
2830
6ae4a6a5
PB		 2831void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2832{
2833 kfree(mod_hdr_acts->actions);
2834 mod_hdr_acts->actions = NULL;
2835 mod_hdr_acts->num_actions = 0;
2836 mod_hdr_acts->max_actions = 0;
2837}
2838
d79b6df6
OG		 2839static const struct pedit_headers zero_masks = {};
2840
582234b4
EC		 2841static int
2842parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2843 const struct flow_action_entry *act, int namespace,
2844 struct mlx5e_tc_flow_parse_attr *parse_attr,
2845 struct pedit_headers_action *hdrs,
2846 struct netlink_ext_ack *extack)
d79b6df6 2847{
73867881
PNA		 2848 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2849 int err = -EOPNOTSUPP;
d79b6df6 2850 u32 mask, val, offset;
73867881 2851 u8 htype;
d79b6df6 2852
73867881
PNA		 2853 htype = act->mangle.htype;
2854 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2855
73867881
PNA		 2856 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2857 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2858 goto out_err;
2859 }
d79b6df6 2860
2cc1cb1d
TZ		 2861 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2862 NL_SET_ERR_MSG_MOD(extack,
2863 "The pedit offload action is not supported");
2864 goto out_err;
2865 }
2866
73867881
PNA		 2867 mask = act->mangle.mask;
2868 val = act->mangle.val;
2869 offset = act->mangle.offset;
d79b6df6 2870
73867881
PNA		 2871 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2872 if (err)
2873 goto out_err;
c500c86b 2874
73867881 2875 hdrs[cmd].pedits++;
d79b6df6 2876
c500c86b
PNA		 2877 return 0;
2878out_err:
2879 return err;
2880}
2881
582234b4
EC		 2882static int
2883parse_pedit_to_reformat(struct mlx5e_priv *priv,
2884 const struct flow_action_entry *act,
2885 struct mlx5e_tc_flow_parse_attr *parse_attr,
2886 struct netlink_ext_ack *extack)
2887{
2888 u32 mask, val, offset;
2889 u32 *p;
2890
2891 if (act->id != FLOW_ACTION_MANGLE)
2892 return -EOPNOTSUPP;
2893
2894 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2895 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2896 return -EOPNOTSUPP;
2897 }
2898
2899 mask = ~act->mangle.mask;
2900 val = act->mangle.val;
2901 offset = act->mangle.offset;
2902 p = (u32 *)&parse_attr->eth;
2903 *(p + (offset >> 2)) |= (val & mask);
2904
2905 return 0;
2906}
2907
2908static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2909 const struct flow_action_entry *act, int namespace,
2910 struct mlx5e_tc_flow_parse_attr *parse_attr,
2911 struct pedit_headers_action *hdrs,
2912 struct mlx5e_tc_flow *flow,
2913 struct netlink_ext_ack *extack)
2914{
2915 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2916 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2917
2918 return parse_pedit_to_modify_hdr(priv, act, namespace,
2919 parse_attr, hdrs, extack);
2920}
2921
c500c86b
PNA		 2922static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2923 struct mlx5e_tc_flow_parse_attr *parse_attr,
2924 struct pedit_headers_action *hdrs,
27c11b6b 2925 u32 *action_flags,
c500c86b
PNA		 2926 struct netlink_ext_ack *extack)
2927{
2928 struct pedit_headers *cmd_masks;
2929 int err;
2930 u8 cmd;
2931
6ae4a6a5
PB		 2932 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2933 action_flags, extack);
d79b6df6
OG		 2934 if (err < 0)
2935 goto out_dealloc_parsed_actions;
2936
2937 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2938 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2939 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2940 NL_SET_ERR_MSG_MOD(extack,
2941 "attempt to offload an unsupported field");
b3a433de 2942 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2943 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2944 16, 1, cmd_masks, sizeof(zero_masks), true);
2945 err = -EOPNOTSUPP;
2946 goto out_dealloc_parsed_actions;
2947 }
2948 }
2949
2950 return 0;
2951
2952out_dealloc_parsed_actions:
6ae4a6a5 2953 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2954 return err;
2955}
2956
e98bedf5
EB		 2957static bool csum_offload_supported(struct mlx5e_priv *priv,
2958 u32 action,
2959 u32 update_flags,
2960 struct netlink_ext_ack *extack)
26c02749
OG		 2961{
2962 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2963 TCA_CSUM_UPDATE_FLAG_UDP;
2964
2965 /* The HW recalcs checksums only if re-writing headers */
2966 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2967 NL_SET_ERR_MSG_MOD(extack,
2968 "TC csum action is only offloaded with pedit");
26c02749
OG		 2969 netdev_warn(priv->netdev,
2970 "TC csum action is only offloaded with pedit\n");
2971 return false;
2972 }
2973
2974 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2975 NL_SET_ERR_MSG_MOD(extack,
2976 "can't offload TC csum action for some header/s");
26c02749
OG		 2977 netdev_warn(priv->netdev,
2978 "can't offload TC csum action for some header/s - flags %#x\n",
2979 update_flags);
2980 return false;
2981 }
2982
2983 return true;
2984}
2985
8998576b
DL		 2986struct ip_ttl_word {
2987 __u8 ttl;
2988 __u8 protocol;
2989 __sum16 check;
2990};
2991
2992struct ipv6_hoplimit_word {
2993 __be16 payload_len;
2994 __u8 nexthdr;
2995 __u8 hop_limit;
2996};
2997
4c3844d9
PB		 2998static int is_action_keys_supported(const struct flow_action_entry *act,
2999 bool ct_flow, bool *modify_ip_header,
7e36feeb 3000 bool *modify_tuple,
4c3844d9 3001 struct netlink_ext_ack *extack)
8998576b
DL		 3002{
3003 u32 mask, offset;
3004 u8 htype;
3005
3006 htype = act->mangle.htype;
3007 offset = act->mangle.offset;
3008 mask = ~act->mangle.mask;
3009 /* For IPv4 & IPv6 header check 4 byte word,
3010 * to determine that modified fields
3011 * are NOT ttl & hop_limit only.
3012 */
3013 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3014 struct ip_ttl_word *ttl_word =
3015 (struct ip_ttl_word *)&mask;
3016
3017 if (offset != offsetof(struct iphdr, ttl) ||
3018 ttl_word->protocol ||
3019 ttl_word->check) {
4c3844d9
PB		 3020 *modify_ip_header = true;
3021 }
3022
7e36feeb
PB		 3023 if (offset >= offsetof(struct iphdr, saddr))
3024 *modify_tuple = true;
3025
3026 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3027 NL_SET_ERR_MSG_MOD(extack,
3028 "can't offload re-write of ipv4 address with action ct");
3029 return -EOPNOTSUPP;
8998576b
DL		 3030 }
3031 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3032 struct ipv6_hoplimit_word *hoplimit_word =
3033 (struct ipv6_hoplimit_word *)&mask;
3034
3035 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3036 hoplimit_word->payload_len ||
3037 hoplimit_word->nexthdr) {
4c3844d9
PB		 3038 *modify_ip_header = true;
3039 }
3040
7e36feeb
PB		 3041 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3042 *modify_tuple = true;
3043
3044 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3045 NL_SET_ERR_MSG_MOD(extack,
3046 "can't offload re-write of ipv6 address with action ct");
3047 return -EOPNOTSUPP;
8998576b 3048 }
7e36feeb
PB		 3049 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3050 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3051 *modify_tuple = true;
3052 if (ct_flow) {
3053 NL_SET_ERR_MSG_MOD(extack,
3054 "can't offload re-write of transport header ports with action ct");
3055 return -EOPNOTSUPP;
3056 }
8998576b 3057 }
4c3844d9
PB		 3058
3059 return 0;
8998576b
DL		 3060}
3061
96b5b458
DC		 3062static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3063 bool ct_flow, struct netlink_ext_ack *extack,
3064 struct mlx5e_priv *priv,
3065 struct mlx5_flow_spec *spec)
3066{
3067 if (!modify_tuple || ct_clear)
3068 return true;
3069
3070 if (ct_flow) {
3071 NL_SET_ERR_MSG_MOD(extack,
3072 "can't offload tuple modification with non-clear ct()");
3073 netdev_info(priv->netdev,
3074 "can't offload tuple modification with non-clear ct()");
3075 return false;
3076 }
3077
3078 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3079 * (or after clear action), as otherwise, since the tuple is changed,
3080 * we can't restore ct state
3081 */
3082 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3083 NL_SET_ERR_MSG_MOD(extack,
3084 "can't offload tuple modification with ct matches and no ct(clear) action");
3085 netdev_info(priv->netdev,
3086 "can't offload tuple modification with ct matches and no ct(clear) action");
3087 return false;
3088 }
3089
3090 return true;
3091}
3092
3d486ec4
OS		 3093static bool modify_header_match_supported(struct mlx5e_priv *priv,
3094 struct mlx5_flow_spec *spec,
73867881 3095 struct flow_action *flow_action,
4c3844d9 3096 u32 actions, bool ct_flow,
7e36feeb 3097 bool ct_clear,
e98bedf5 3098 struct netlink_ext_ack *extack)
bdd66ac0 3099{
73867881 3100 const struct flow_action_entry *act;
7e36feeb 3101 bool modify_ip_header, modify_tuple;
fca53304 3102 void *headers_c;
bdd66ac0
OG		 3103 void *headers_v;
3104 u16 ethertype;
8998576b 3105 u8 ip_proto;
4c3844d9 3106 int i, err;
bdd66ac0 3107
fca53304 3108 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3109 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3110 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3111
3112 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3113 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3114 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3115 goto out_ok;
3116
3117 modify_ip_header = false;
7e36feeb 3118 modify_tuple = false;
73867881
PNA		 3119 flow_action_for_each(i, act, flow_action) {
3120 if (act->id != FLOW_ACTION_MANGLE &&
3121 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3122 continue;
3123
4c3844d9 3124 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3125 &modify_ip_header,
3126 &modify_tuple, extack);
4c3844d9
PB		 3127 if (err)
3128 return err;
bdd66ac0
OG		 3129 }
3130
96b5b458
DC		 3131 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3132 priv, spec))
7e36feeb 3133 return false;
7e36feeb 3134
bdd66ac0 3135 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3136 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3137 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3138 NL_SET_ERR_MSG_MOD(extack,
3139 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3140 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3141 ip_proto);
bdd66ac0
OG		 3142 return false;
3143 }
3144
3145out_ok:
3146 return true;
3147}
3148
3149static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3150 struct flow_action *flow_action,
bdd66ac0 3151 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3152 struct mlx5e_tc_flow *flow,
3153 struct netlink_ext_ack *extack)
bdd66ac0 3154{
a7c119bd 3155 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3156 u32 actions;
3157
c620b772
AL		 3158 ct_clear = flow->attr->ct_attr.ct_action &
3159 TCA_CT_ACT_CLEAR;
3160 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3161 actions = flow->attr->action;
3162
4c3844d9 3163 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3164 if (flow->attr->esw_attr->split_count && ct_flow &&
3165 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3166 /* All registers used by ct are cleared when using
3167 * split rules.
3168 */
3169 NL_SET_ERR_MSG_MOD(extack,
3170 "Can't offload mirroring with action ct");
49397b80 3171 return false;
4c3844d9 3172 }
4c3844d9 3173 }
bdd66ac0
OG		 3174
3175 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3176 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3177 flow_action, actions,
7e36feeb
PB		 3178 ct_flow, ct_clear,
3179 extack);
bdd66ac0
OG		 3180
3181 return true;
3182}
3183
32134847
MD		 3184static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3185{
3186 return priv->mdev == peer_priv->mdev;
3187}
3188
5c65c564
OG		 3189static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3190{
3191 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3192 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3193
3194 fmdev = priv->mdev;
3195 pmdev = peer_priv->mdev;
3196
59c9d35e
AH		 3197 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3198 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3199
816f6706 3200 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3201}
3202
bb569657
AL		 3203static bool same_vf_reps(struct mlx5e_priv *priv,
3204 struct net_device *out_dev)
3205{
3206 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3207 priv->netdev == out_dev;
3208}
3209
bdc837ee
EB		 3210static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3211 const struct flow_action_entry *act,
3212 struct mlx5e_tc_flow_parse_attr *parse_attr,
3213 struct pedit_headers_action *hdrs,
3214 u32 *action, struct netlink_ext_ack *extack)
3215{
3216 u16 mask16 = VLAN_VID_MASK;
3217 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3218 const struct flow_action_entry pedit_act = {
3219 .id = FLOW_ACTION_MANGLE,
3220 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3221 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3222 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3223 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3224 };
6fca9d1e 3225 u8 match_prio_mask, match_prio_val;
bf2f3bca 3226 void *headers_c, *headers_v;
bdc837ee
EB		 3227 int err;
3228
bf2f3bca
EB		 3229 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3230 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3231
3232 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3233 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3234 NL_SET_ERR_MSG_MOD(extack,
3235 "VLAN rewrite action must have VLAN protocol match");
3236 return -EOPNOTSUPP;
3237 }
3238
6fca9d1e
EB		 3239 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3240 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3241 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3242 NL_SET_ERR_MSG_MOD(extack,
3243 "Changing VLAN prio is not supported");
bdc837ee
EB		 3244 return -EOPNOTSUPP;
3245 }
3246
582234b4 3247 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3248 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3249
3250 return err;
3251}
3252
0bac1194
EB		 3253static int
3254add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3255 struct mlx5e_tc_flow_parse_attr *parse_attr,
3256 struct pedit_headers_action *hdrs,
3257 u32 *action, struct netlink_ext_ack *extack)
3258{
3259 const struct flow_action_entry prio_tag_act = {
3260 .vlan.vid = 0,
3261 .vlan.prio =
3262 MLX5_GET(fte_match_set_lyr_2_4,
3263 get_match_headers_value(*action,
3264 &parse_attr->spec),
3265 first_prio) &
3266 MLX5_GET(fte_match_set_lyr_2_4,
3267 get_match_headers_criteria(*action,
3268 &parse_attr->spec),
3269 first_prio),
3270 };
3271
3272 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3273 &prio_tag_act, parse_attr, hdrs, action,
3274 extack);
3275}
3276
c7569097
AL		 3277static int validate_goto_chain(struct mlx5e_priv *priv,
3278 struct mlx5e_tc_flow *flow,
3279 const struct flow_action_entry *act,
3280 u32 actions,
3281 struct netlink_ext_ack *extack)
3282{
3283 bool is_esw = mlx5e_is_eswitch_flow(flow);
3284 struct mlx5_flow_attr *attr = flow->attr;
3285 bool ft_flow = mlx5e_is_ft_flow(flow);
3286 u32 dest_chain = act->chain_index;
3287 struct mlx5_fs_chains *chains;
3288 struct mlx5_eswitch *esw;
3289 u32 reformat_and_fwd;
3290 u32 max_chain;
3291
3292 esw = priv->mdev->priv.eswitch;
3293 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3294 max_chain = mlx5_chains_get_chain_range(chains);
3295 reformat_and_fwd = is_esw ?
3296 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3297 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3298
3299 if (ft_flow) {
3300 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3301 return -EOPNOTSUPP;
3302 }
3303
3304 if (!mlx5_chains_backwards_supported(chains) &&
3305 dest_chain <= attr->chain) {
3306 NL_SET_ERR_MSG_MOD(extack,
3307 "Goto lower numbered chain isn't supported");
3308 return -EOPNOTSUPP;
3309 }
3310
3311 if (dest_chain > max_chain) {
3312 NL_SET_ERR_MSG_MOD(extack,
3313 "Requested destination chain is out of supported range");
3314 return -EOPNOTSUPP;
3315 }
3316
3317 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3318 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3319 !reformat_and_fwd) {
3320 NL_SET_ERR_MSG_MOD(extack,
3321 "Goto chain is not allowed if action has reformat or decap");
3322 return -EOPNOTSUPP;
3323 }
3324
3325 return 0;
3326}
3327
73867881
PNA		 3328static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3329 struct flow_action *flow_action,
aa0cbbae 3330 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3331 struct mlx5e_tc_flow *flow,
3332 struct netlink_ext_ack *extack)
e3a2b7ed 3333{
c620b772 3334 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3335 struct pedit_headers_action hdrs[2] = {};
3336 const struct flow_action_entry *act;
c620b772 3337 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3338 u32 action = 0;
244cd96a 3339 int err, i;
e3a2b7ed 3340
73867881 3341 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3342 return -EINVAL;
3343
53eca1f3
JK		 3344 if (!flow_action_hw_stats_check(flow_action, extack,
3345 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3346 return -EOPNOTSUPP;
3347
c620b772
AL		 3348 nic_attr = attr->nic_attr;
3349
3350 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3351
73867881
PNA		 3352 flow_action_for_each(i, act, flow_action) {
3353 switch (act->id) {
15fc92ec
TZ		 3354 case FLOW_ACTION_ACCEPT:
3355 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3356 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3357 break;
73867881 3358 case FLOW_ACTION_DROP:
1cab1cd7 3359 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3360 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3361 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3362 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3363 break;
3364 case FLOW_ACTION_MANGLE:
3365 case FLOW_ACTION_ADD:
3366 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3367 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3368 if (err)
3369 return err;
3370
c7569097 3371 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3372 break;
bdc837ee
EB		 3373 case FLOW_ACTION_VLAN_MANGLE:
3374 err = add_vlan_rewrite_action(priv,
3375 MLX5_FLOW_NAMESPACE_KERNEL,
3376 act, parse_attr, hdrs,
3377 &action, extack);
3378 if (err)
3379 return err;
3380
3381 break;
73867881 3382 case FLOW_ACTION_CSUM:
1cab1cd7 3383 if (csum_offload_supported(priv, action,
73867881 3384 act->csum_flags,
e98bedf5 3385 extack))
73867881 3386 break;
26c02749
OG		 3387
3388 return -EOPNOTSUPP;
73867881
PNA		 3389 case FLOW_ACTION_REDIRECT: {
3390 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3391
3392 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3393 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3394 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3395 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3396 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3397 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3398 } else {
e98bedf5
EB		 3399 NL_SET_ERR_MSG_MOD(extack,
3400 "device is not on same HW, can't offload");
5c65c564
OG		 3401 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3402 peer_dev->name);
3403 return -EINVAL;
3404 }
73867881
PNA		 3405 }
3406 break;
3407 case FLOW_ACTION_MARK: {
3408 u32 mark = act->mark;
e3a2b7ed
AV		 3409
3410 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3411 NL_SET_ERR_MSG_MOD(extack,
3412 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3413 return -EINVAL;
3414 }
3415
c620b772 3416 nic_attr->flow_tag = mark;
1cab1cd7 3417 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3418 }
3419 break;
c7569097
AL		 3420 case FLOW_ACTION_GOTO:
3421 err = validate_goto_chain(priv, flow, act, action,
3422 extack);
3423 if (err)
3424 return err;
3425
3426 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3427 attr->dest_chain = act->chain_index;
3428 break;
aedd133d
AL		 3429 case FLOW_ACTION_CT:
3430 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3431 if (err)
3432 return err;
3433
3434 flow_flag_set(flow, CT);
3435 break;
73867881 3436 default:
2cc1cb1d
TZ		 3437 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3438 return -EOPNOTSUPP;
e3a2b7ed 3439 }
e3a2b7ed
AV		 3440 }
3441
c500c86b
PNA		 3442 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3443 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3444 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3445 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3446 if (err)
3447 return err;
27c11b6b
EB		 3448 /* in case all pedit actions are skipped, remove the MOD_HDR
3449 * flag.
3450 */
6ae4a6a5 3451 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3452 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3453 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3454 }
c500c86b
PNA		 3455 }
3456
1cab1cd7 3457 attr->action = action;
c7569097
AL		 3458
3459 if (attr->dest_chain) {
3460 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3461 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3462 return -EOPNOTSUPP;
3463 }
3464 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3465 }
3466
3467 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3468 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3469
73867881 3470 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3471 return -EOPNOTSUPP;
3472
e3a2b7ed
AV		 3473 return 0;
3474}
3475
32134847 3476static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3477 struct net_device *peer_netdev)
3478{
3479 struct mlx5e_priv *peer_priv;
3480
3481 peer_priv = netdev_priv(peer_netdev);
3482
3483 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3484 mlx5e_eswitch_vf_rep(priv->netdev) &&
3485 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3486 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3487}
3488
1482bd3d 3489static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3490 const struct flow_action_entry *act,
1482bd3d
JL		 3491 struct mlx5_esw_flow_attr *attr,
3492 u32 *action)
3493{
cc495188
JL		 3494 u8 vlan_idx = attr->total_vlan;
3495
3496 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3497 return -EOPNOTSUPP;
3498
73867881
PNA		 3499 switch (act->id) {
3500 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3501 if (vlan_idx) {
3502 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3503 MLX5_FS_VLAN_DEPTH))
3504 return -EOPNOTSUPP;
3505
3506 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3507 } else {
3508 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3509 }
73867881
PNA		 3510 break;
3511 case FLOW_ACTION_VLAN_PUSH:
3512 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3513 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3514 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3515 if (!attr->vlan_proto[vlan_idx])
3516 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3517
3518 if (vlan_idx) {
3519 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3520 MLX5_FS_VLAN_DEPTH))
3521 return -EOPNOTSUPP;
3522
3523 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3524 } else {
3525 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3526 (act->vlan.proto != htons(ETH_P_8021Q) ||
3527 act->vlan.prio))
cc495188
JL		 3528 return -EOPNOTSUPP;
3529
3530 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3531 }
73867881
PNA		 3532 break;
3533 default:
bdc837ee 3534 return -EINVAL;
1482bd3d
JL		 3535 }
3536
cc495188
JL		 3537 attr->total_vlan = vlan_idx + 1;
3538
1482bd3d
JL		 3539 return 0;
3540}
3541
d34eb2fc
OG		 3542static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3543 struct net_device *out_dev)
3544{
3545 struct net_device *fdb_out_dev = out_dev;
3546 struct net_device *uplink_upper;
3547
3548 rcu_read_lock();
3549 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3550 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3551 uplink_upper == out_dev) {
3552 fdb_out_dev = uplink_dev;
3553 } else if (netif_is_lag_master(out_dev)) {
3554 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3555 if (fdb_out_dev &&
3556 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3557 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3558 fdb_out_dev = NULL;
3559 }
3560 rcu_read_unlock();
3561 return fdb_out_dev;
3562}
3563
278748a9 3564static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3565 struct mlx5_flow_attr *attr,
278748a9
EB		 3566 struct net_device **out_dev,
3567 u32 *action)
3568{
3569 struct net_device *vlan_dev = *out_dev;
3570 struct flow_action_entry vlan_act = {
3571 .id = FLOW_ACTION_VLAN_PUSH,
3572 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3573 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3574 .vlan.prio = 0,
3575 };
3576 int err;
3577
c620b772 3578 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3579 if (err)
3580 return err;
3581
dca59f4a
DC		 3582 rcu_read_lock();
3583 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3584 rcu_read_unlock();
3585 if (!*out_dev)
3586 return -ENODEV;
3587
278748a9
EB		 3588 if (is_vlan_dev(*out_dev))
3589 err = add_vlan_push_action(priv, attr, out_dev, action);
3590
3591 return err;
3592}
3593
35a605db 3594static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3595 struct mlx5_flow_attr *attr,
35a605db
EB		 3596 u32 *action)
3597{
35a605db
EB		 3598 struct flow_action_entry vlan_act = {
3599 .id = FLOW_ACTION_VLAN_POP,
3600 };
70f478ca 3601 int nest_level, err = 0;
35a605db 3602
70f478ca
DL		 3603 nest_level = attr->parse_attr->filter_dev->lower_level -
3604 priv->netdev->lower_level;
35a605db 3605 while (nest_level--) {
c620b772 3606 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3607 if (err)
3608 return err;
3609 }
3610
3611 return err;
3612}
3613
32134847
MD		 3614static bool same_hw_reps(struct mlx5e_priv *priv,
3615 struct net_device *peer_netdev)
3616{
3617 struct mlx5e_priv *peer_priv;
3618
3619 peer_priv = netdev_priv(peer_netdev);
3620
3621 return mlx5e_eswitch_rep(priv->netdev) &&
3622 mlx5e_eswitch_rep(peer_netdev) &&
3623 same_hw_devs(priv, peer_priv);
3624}
3625
3626static bool is_lag_dev(struct mlx5e_priv *priv,
3627 struct net_device *peer_netdev)
3628{
3629 return ((mlx5_lag_is_sriov(priv->mdev) ||
3630 mlx5_lag_is_multipath(priv->mdev)) &&
3631 same_hw_reps(priv, peer_netdev));
3632}
3633
f6dc1264
PB		 3634bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3635 struct net_device *out_dev)
3636{
32134847
MD		 3637 if (is_merged_eswitch_vfs(priv, out_dev))
3638 return true;
3639
3640 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3641 return true;
3642
3643 return mlx5e_eswitch_rep(out_dev) &&
32134847 3644 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3645}
3646
554fe75c
DL		 3647static bool is_duplicated_output_device(struct net_device *dev,
3648 struct net_device *out_dev,
3649 int *ifindexes, int if_count,
3650 struct netlink_ext_ack *extack)
3651{
3652 int i;
3653
3654 for (i = 0; i < if_count; i++) {
3655 if (ifindexes[i] == out_dev->ifindex) {
3656 NL_SET_ERR_MSG_MOD(extack,
3657 "can't duplicate output to same device");
3658 netdev_err(dev, "can't duplicate output to same device: %s\n",
3659 out_dev->name);
3660 return true;
3661 }
3662 }
3663
3664 return false;
3665}
3666
613f53fe
EC		 3667static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3668 struct mlx5e_tc_flow *flow,
3669 struct net_device *out_dev,
3670 struct netlink_ext_ack *extack)
3671{
c620b772 3672 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3673 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3674 struct mlx5e_rep_priv *rep_priv;
3675
3676 /* Forwarding non encapsulated traffic between
3677 * uplink ports is allowed only if
3678 * termination_table_raw_traffic cap is set.
3679 *
c620b772 3680 * Input vport was stored attr->in_rep.
613f53fe
EC		 3681 * In LAG case, *priv* is the private data of
3682 * uplink which may be not the input vport.
3683 */
3684 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3685
3686 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3687 mlx5e_eswitch_uplink_rep(out_dev)))
3688 return 0;
3689
3690 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3691 termination_table_raw_traffic)) {
3692 NL_SET_ERR_MSG_MOD(extack,
3693 "devices are both uplink, can't offload forwarding");
3694 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3695 priv->netdev->name, out_dev->name);
3696 return -EOPNOTSUPP;
3697 } else if (out_dev != rep_priv->netdev) {
3698 NL_SET_ERR_MSG_MOD(extack,
3699 "devices are not the same uplink, can't offload forwarding");
3700 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3701 priv->netdev->name, out_dev->name);
3702 return -EOPNOTSUPP;
3703 }
3704 return 0;
3705}
3706
73867881
PNA		 3707static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3708 struct flow_action *flow_action,
e98bedf5 3709 struct mlx5e_tc_flow *flow,
70f8019e 3710 struct netlink_ext_ack *extack)
03a9d11e 3711{
73867881 3712 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3713 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3714 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3715 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3716 const struct ip_tunnel_info *info = NULL;
c620b772 3717 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3718 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3719 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3720 const struct flow_action_entry *act;
c620b772 3721 struct mlx5_esw_flow_attr *esw_attr;
41c2fd94 3722 struct mlx5_sample_attr sample = {};
0a7fcb78
PB		 3723 bool encap = false, decap = false;
3724 u32 action = attr->action;
554fe75c 3725 int err, i, if_count = 0;
f828ca6a 3726 bool mpls_push = false;
03a9d11e 3727
73867881 3728 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3729 return -EINVAL;
3730
53eca1f3
JK		 3731 if (!flow_action_hw_stats_check(flow_action, extack,
3732 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3733 return -EOPNOTSUPP;
3734
c620b772
AL		 3735 esw_attr = attr->esw_attr;
3736 parse_attr = attr->parse_attr;
3737
73867881
PNA		 3738 flow_action_for_each(i, act, flow_action) {
3739 switch (act->id) {
3740 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3741 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3742 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3743 break;
f0288210
EC		 3744 case FLOW_ACTION_TRAP:
3745 if (!flow_offload_has_one_action(flow_action)) {
3746 NL_SET_ERR_MSG_MOD(extack,
3747 "action trap is supported as a sole action only");
3748 return -EOPNOTSUPP;
3749 }
3750 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3751 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3752 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3753 break;
f828ca6a
EC		 3754 case FLOW_ACTION_MPLS_PUSH:
3755 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3756 reformat_l2_to_l3_tunnel) ||
3757 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3758 NL_SET_ERR_MSG_MOD(extack,
3759 "mpls push is supported only for mpls_uc protocol");
3760 return -EOPNOTSUPP;
3761 }
3762 mpls_push = true;
3763 break;
14e6b038
EC		 3764 case FLOW_ACTION_MPLS_POP:
3765 /* we only support mpls pop if it is the first action
3766 * and the filter net device is bareudp. Subsequent
3767 * actions can be pedit and the last can be mirred
3768 * egress redirect.
3769 */
3770 if (i) {
3771 NL_SET_ERR_MSG_MOD(extack,
3772 "mpls pop supported only as first action");
3773 return -EOPNOTSUPP;
3774 }
70f8019e 3775 if (!netif_is_bareudp(parse_attr->filter_dev)) {
14e6b038
EC		 3776 NL_SET_ERR_MSG_MOD(extack,
3777 "mpls pop supported only on bareudp devices");
3778 return -EOPNOTSUPP;
3779 }
3780
3781 parse_attr->eth.h_proto = act->mpls_pop.proto;
3782 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3783 flow_flag_set(flow, L3_TO_L2_DECAP);
3784 break;
73867881
PNA		 3785 case FLOW_ACTION_MANGLE:
3786 case FLOW_ACTION_ADD:
3787 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3788 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3789 if (err)
3790 return err;
3791
582234b4
EC		 3792 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3793 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3794 esw_attr->split_count = esw_attr->out_count;
582234b4 3795 }
73867881
PNA		 3796 break;
3797 case FLOW_ACTION_CSUM:
1cab1cd7 3798 if (csum_offload_supported(priv, action,
73867881
PNA		 3799 act->csum_flags, extack))
3800 break;
26c02749
OG		 3801
3802 return -EOPNOTSUPP;
73867881
PNA		 3803 case FLOW_ACTION_REDIRECT:
3804 case FLOW_ACTION_MIRRED: {
03a9d11e 3805 struct mlx5e_priv *out_priv;
592d3651 3806 struct net_device *out_dev;
03a9d11e 3807
73867881 3808 out_dev = act->dev;
ef381359
OS		 3809 if (!out_dev) {
3810 /* out_dev is NULL when filters with
3811 * non-existing mirred device are replayed to
3812 * the driver.
3813 */
3814 return -EINVAL;
3815 }
03a9d11e 3816
f828ca6a
EC		 3817 if (mpls_push && !netif_is_bareudp(out_dev)) {
3818 NL_SET_ERR_MSG_MOD(extack,
3819 "mpls is supported only through a bareudp device");
3820 return -EOPNOTSUPP;
3821 }
3822
84179981
PB		 3823 if (ft_flow && out_dev == priv->netdev) {
3824 /* Ignore forward to self rules generated
3825 * by adding both mlx5 devs to the flow table
3826 * block on a normal nft offload setup.
3827 */
3828 return -EOPNOTSUPP;
3829 }
3830
c620b772 3831 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3832 NL_SET_ERR_MSG_MOD(extack,
3833 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3834 netdev_warn(priv->netdev,
3835 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3836 esw_attr->out_count);
592d3651
CM		 3837 return -EOPNOTSUPP;
3838 }
3839
f493f155
EB		 3840 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3841 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3842 if (encap) {
c620b772 3843 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3844 out_dev->ifindex;
0d9f9647
VB		 3845 parse_attr->tun_info[esw_attr->out_count] =
3846 mlx5e_dup_tun_info(info);
c620b772 3847 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3848 return -ENOMEM;
3849 encap = false;
c620b772 3850 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3851 MLX5_ESW_DEST_ENCAP;
c620b772 3852 esw_attr->out_count++;
b6a4ac24
VB		 3853 /* attr->dests[].rep is resolved when we
3854 * handle encap
3855 */
3856 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3857 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3858 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3859
554fe75c
DL		 3860 if (is_duplicated_output_device(priv->netdev,
3861 out_dev,
3862 ifindexes,
3863 if_count,
3864 extack))
3865 return -EOPNOTSUPP;
3866
3867 ifindexes[if_count] = out_dev->ifindex;
3868 if_count++;
3869
d34eb2fc
OG		 3870 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3871 if (!out_dev)
3872 return -ENODEV;
7ba58ba7 3873
278748a9
EB		 3874 if (is_vlan_dev(out_dev)) {
3875 err = add_vlan_push_action(priv, attr,
3876 &out_dev,
3877 &action);
3878 if (err)
3879 return err;
3880 }
f6dc1264 3881
35a605db
EB		 3882 if (is_vlan_dev(parse_attr->filter_dev)) {
3883 err = add_vlan_pop_action(priv, attr,
3884 &action);
3885 if (err)
3886 return err;
3887 }
278748a9 3888
613f53fe
EC		 3889 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3890 if (err)
3891 return err;
ffec9702 3892
f6dc1264
PB		 3893 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3894 NL_SET_ERR_MSG_MOD(extack,
3895 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3896 return -EOPNOTSUPP;
f6dc1264 3897 }
a0646c88 3898
bb569657
AL		 3899 if (same_vf_reps(priv, out_dev)) {
3900 NL_SET_ERR_MSG_MOD(extack,
3901 "can't forward from a VF to itself");
3902 return -EOPNOTSUPP;
3903 }
3904
a54e20b4 3905 out_priv = netdev_priv(out_dev);
1d447a39 3906 rpriv = out_priv->ppriv;
c620b772
AL		 3907 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3908 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3909 esw_attr->out_count++;
ef381359
OS		 3910 } else if (parse_attr->filter_dev != priv->netdev) {
3911 /* All mlx5 devices are called to configure
3912 * high level device filters. Therefore, the
3913 * *attempt* to install a filter on invalid
3914 * eswitch should not trigger an explicit error
3915 */
3916 return -EINVAL;
a54e20b4 3917 } else {
e98bedf5
EB		 3918 NL_SET_ERR_MSG_MOD(extack,
3919 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3920 netdev_warn(priv->netdev,
3921 "devices %s %s not on same switch HW, can't offload forwarding\n",
3922 priv->netdev->name,
3923 out_dev->name);
03a9d11e
OG		 3924 return -EINVAL;
3925 }
73867881
PNA		 3926 }
3927 break;
3928 case FLOW_ACTION_TUNNEL_ENCAP:
3929 info = act->tunnel;
a54e20b4
HHZ		 3930 if (info)
3931 encap = true;
3932 else
3933 return -EOPNOTSUPP;
1482bd3d 3934
73867881
PNA		 3935 break;
3936 case FLOW_ACTION_VLAN_PUSH:
3937 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3938 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3939 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3940 /* Replace vlan pop+push with vlan modify */
3941 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3942 err = add_vlan_rewrite_action(priv,
3943 MLX5_FLOW_NAMESPACE_FDB,
3944 act, parse_attr, hdrs,
3945 &action, extack);
3946 } else {
c620b772 3947 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3948 }
1482bd3d
JL		 3949 if (err)
3950 return err;
3951
c620b772 3952 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3953 break;
3954 case FLOW_ACTION_VLAN_MANGLE:
3955 err = add_vlan_rewrite_action(priv,
3956 MLX5_FLOW_NAMESPACE_FDB,
3957 act, parse_attr, hdrs,
3958 &action, extack);
3959 if (err)
3960 return err;
3961
c620b772 3962 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3963 break;
3964 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3965 decap = true;
73867881 3966 break;
2fbbc30d 3967 case FLOW_ACTION_GOTO:
c7569097
AL		 3968 err = validate_goto_chain(priv, flow, act, action,
3969 extack);
2fbbc30d
EC		 3970 if (err)
3971 return err;
bf07aa73 3972
e88afe75 3973 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 3974 attr->dest_chain = act->chain_index;
73867881 3975 break;
4c3844d9 3976 case FLOW_ACTION_CT:
41c2fd94
CM		 3977 if (flow_flag_test(flow, SAMPLE)) {
3978 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
3979 return -EOPNOTSUPP;
3980 }
aedd133d 3981 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 3982 if (err)
3983 return err;
3984
3985 flow_flag_set(flow, CT);
69e2916e 3986 esw_attr->split_count = esw_attr->out_count;
4c3844d9 3987 break;
41c2fd94
CM		 3988 case FLOW_ACTION_SAMPLE:
3989 if (flow_flag_test(flow, CT)) {
3990 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
3991 return -EOPNOTSUPP;
3992 }
3993 sample.rate = act->sample.rate;
3994 sample.group_num = act->sample.psample_group->group_num;
3995 if (act->sample.truncate)
3996 sample.trunc_size = act->sample.trunc_size;
3997 flow_flag_set(flow, SAMPLE);
3998 break;
73867881 3999 default:
2cc1cb1d
TZ		 4000 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4001 return -EOPNOTSUPP;
bf07aa73 4002 }
03a9d11e 4003 }
bdd66ac0 4004
a508728a
VB		 4005 /* always set IP version for indirect table handling */
4006 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4007
0bac1194
EB		 4008 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4009 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4010 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4011 * tag rewrite.
4012 */
4013 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4014 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4015 &action, extack);
4016 if (err)
4017 return err;
4018 }
4019
c500c86b
PNA		 4020 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4021 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4022 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4023 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4024 if (err)
4025 return err;
27c11b6b
EB		 4026 /* in case all pedit actions are skipped, remove the MOD_HDR
4027 * flag. we might have set split_count either by pedit or
4028 * pop/push. if there is no pop/push either, reset it too.
4029 */
6ae4a6a5 4030 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4031 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4032 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4033 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4034 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4035 esw_attr->split_count = 0;
27c11b6b 4036 }
c500c86b
PNA		 4037 }
4038
1cab1cd7 4039 attr->action = action;
73867881 4040 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4041 return -EOPNOTSUPP;
4042
e88afe75 4043 if (attr->dest_chain) {
0a7fcb78
PB		 4044 if (decap) {
4045 /* It can be supported if we'll create a mapping for
4046 * the tunnel device only (without tunnel), and set
4047 * this tunnel id with this decap flow.
4048 *
4049 * On restore (miss), we'll just set this saved tunnel
4050 * device.
4051 */
4052
4053 NL_SET_ERR_MSG(extack,
4054 "Decap with goto isn't supported");
4055 netdev_warn(priv->netdev,
4056 "Decap with goto isn't supported");
4057 return -EOPNOTSUPP;
4058 }
4059
e88afe75
OG		 4060 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4061 }
4062
ae2741e2
VB		 4063 if (!(attr->action &
4064 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4065 NL_SET_ERR_MSG_MOD(extack,
4066 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4067 return -EOPNOTSUPP;
4068 }
4069
c620b772 4070 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4071 NL_SET_ERR_MSG_MOD(extack,
4072 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4073 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4074 return -EOPNOTSUPP;
4075 }
4076
41c2fd94
CM		 4077 /* Allocate sample attribute only when there is a sample action and
4078 * no errors after parsing.
4079 */
4080 if (flow_flag_test(flow, SAMPLE)) {
4081 esw_attr->sample = kzalloc(sizeof(*esw_attr->sample), GFP_KERNEL);
4082 if (!esw_attr->sample)
4083 return -ENOMEM;
4084 *esw_attr->sample = sample;
4085 }
4086
31c8eba5 4087 return 0;
03a9d11e
OG		 4088}
4089
226f2ca3 4090static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4091{
226f2ca3 4092 unsigned long __flow_flags = 0;
60bd4af8 4093
226f2ca3
VB		 4094 if (flags & MLX5_TC_FLAG(INGRESS))
4095 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4096 if (flags & MLX5_TC_FLAG(EGRESS))
4097 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4098
226f2ca3
VB		 4099 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4100 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4101 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4102 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4103 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4104 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4105
60bd4af8
OG		 4106 *flow_flags = __flow_flags;
4107}
4108
05866c82
OG		 4109static const struct rhashtable_params tc_ht_params = {
4110 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4111 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4112 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4113 .automatic_shrinking = true,
4114};
4115
226f2ca3
VB		 4116static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4117 unsigned long flags)
05866c82 4118{
655dc3d2
OG		 4119 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4120 struct mlx5e_rep_priv *uplink_rpriv;
4121
226f2ca3 4122 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4123 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4124 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4125 } else /* NIC offload */
655dc3d2 4126 return &priv->fs.tc.ht;
05866c82
OG		 4127}
4128
04de7dda
RD		 4129static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4130{
c620b772
AL		 4131 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4132 struct mlx5_flow_attr *attr = flow->attr;
4133 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4134 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4135 bool act_is_encap = !!(attr->action &
4136 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4137 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4138 MLX5_DEVCOM_ESW_OFFLOADS);
4139
10fbb1cd
RD		 4140 if (!esw_paired)
4141 return false;
4142
c620b772
AL		 4143 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4144 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4145 (is_rep_ingress || act_is_encap))
4146 return true;
4147
4148 return false;
04de7dda
RD		 4149}
4150
c620b772
AL		 4151struct mlx5_flow_attr *
4152mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4153{
4154 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4155 sizeof(struct mlx5_esw_flow_attr) :
4156 sizeof(struct mlx5_nic_flow_attr);
4157 struct mlx5_flow_attr *attr;
4158
4159 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4160}
4161
a88780a9
RD		 4162static int
4163mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4164 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4165 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4166 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4167{
17091853 4168 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4169 struct mlx5_flow_attr *attr;
3bc4b7bf 4170 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4171 int err = -ENOMEM;
4172 int out_index;
e3a2b7ed 4173
c620b772 4174 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4175 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4176 if (!parse_attr || !flow)
4177 goto err_free;
c620b772
AL		 4178
4179 flow->flags = flow_flags;
4180 flow->cookie = f->cookie;
4181 flow->priv = priv;
4182
4183 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4184 if (!attr)
e3a2b7ed 4185 goto err_free;
ff7ea04a 4186
c620b772 4187 flow->attr = attr;
e3a2b7ed 4188
5a7e5bcb
VB		 4189 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4190 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4191 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4192 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4193 refcount_set(&flow->refcnt, 1);
95435ad7 4194 init_completion(&flow->init_done);
e3a2b7ed 4195
a88780a9
RD		 4196 *__flow = flow;
4197 *__parse_attr = parse_attr;
4198
4199 return 0;
4200
4201err_free:
4202 kfree(flow);
4203 kvfree(parse_attr);
4204 return err;
4205}
4206
c7569097
AL		 4207static void
4208mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4209 struct mlx5e_tc_flow_parse_attr *parse_attr,
4210 struct flow_cls_offload *f)
4211{
4212 attr->parse_attr = parse_attr;
4213 attr->chain = f->common.chain_index;
4214 attr->prio = f->common.prio;
4215}
4216
988ab9c7 4217static void
c620b772 4218mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4219 struct mlx5e_priv *priv,
4220 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4221 struct flow_cls_offload *f,
988ab9c7
TZ		 4222 struct mlx5_eswitch_rep *in_rep,
4223 struct mlx5_core_dev *in_mdev)
4224{
4225 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4226 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4227
c7569097 4228 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4229
4230 esw_attr->in_rep = in_rep;
4231 esw_attr->in_mdev = in_mdev;
4232
4233 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4234 MLX5_COUNTER_SOURCE_ESWITCH)
4235 esw_attr->counter_dev = in_mdev;
4236 else
4237 esw_attr->counter_dev = priv->mdev;
4238}
4239
71129676 4240static struct mlx5e_tc_flow *
04de7dda 4241__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4242 struct flow_cls_offload *f,
226f2ca3 4243 unsigned long flow_flags,
04de7dda
RD		 4244 struct net_device *filter_dev,
4245 struct mlx5_eswitch_rep *in_rep,
71129676 4246 struct mlx5_core_dev *in_mdev)
a88780a9 4247{
f9e30088 4248 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4249 struct netlink_ext_ack *extack = f->common.extack;
4250 struct mlx5e_tc_flow_parse_attr *parse_attr;
4251 struct mlx5e_tc_flow *flow;
4252 int attr_size, err;
e3a2b7ed 4253
226f2ca3 4254 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4255 attr_size = sizeof(struct mlx5_esw_flow_attr);
4256 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4257 &parse_attr, &flow);
4258 if (err)
4259 goto out;
988ab9c7 4260
d11afc26 4261 parse_attr->filter_dev = filter_dev;
c620b772 4262 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4263 priv, parse_attr,
4264 f, in_rep, in_mdev);
4265
54c177ca
OS		 4266 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4267 f, filter_dev);
d11afc26
OS		 4268 if (err)
4269 goto err_free;
a88780a9 4270
7e36feeb 4271 /* actions validation depends on parsing the ct matches first */
aedd133d 4272 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4273 &flow->attr->ct_attr, extack);
a88780a9
RD		 4274 if (err)
4275 goto err_free;
4276
70f8019e 4277 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 4278 if (err)
4279 goto err_free;
4280
7040632d 4281 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4282 complete_all(&flow->init_done);
ef06c9ee
RD		 4283 if (err) {
4284 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4285 goto err_free;
4286
b4a23329 4287 add_unready_flow(flow);
ef06c9ee 4288 }
e3a2b7ed 4289
71129676 4290 return flow;
a88780a9
RD		 4291
4292err_free:
5a7e5bcb 4293 mlx5e_flow_put(priv, flow);
a88780a9 4294out:
71129676 4295 return ERR_PTR(err);
a88780a9
RD		 4296}
4297
f9e30088 4298static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4299 struct mlx5e_tc_flow *flow,
226f2ca3 4300 unsigned long flow_flags)
04de7dda
RD		 4301{
4302 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4303 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4304 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4305 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4306 struct mlx5e_tc_flow_parse_attr *parse_attr;
4307 struct mlx5e_rep_priv *peer_urpriv;
4308 struct mlx5e_tc_flow *peer_flow;
4309 struct mlx5_core_dev *in_mdev;
4310 int err = 0;
4311
4312 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4313 if (!peer_esw)
4314 return -ENODEV;
4315
4316 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4317 peer_priv = netdev_priv(peer_urpriv->netdev);
4318
4319 /* in_mdev is assigned of which the packet originated from.
4320 * So packets redirected to uplink use the same mdev of the
4321 * original flow and packets redirected from uplink use the
4322 * peer mdev.
4323 */
c620b772 4324 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4325 in_mdev = peer_priv->mdev;
4326 else
4327 in_mdev = priv->mdev;
4328
c620b772 4329 parse_attr = flow->attr->parse_attr;
95dc1902 4330 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4331 parse_attr->filter_dev,
c620b772 4332 attr->in_rep, in_mdev);
71129676
JG		 4333 if (IS_ERR(peer_flow)) {
4334 err = PTR_ERR(peer_flow);
04de7dda 4335 goto out;
71129676 4336 }
04de7dda
RD		 4337
4338 flow->peer_flow = peer_flow;
226f2ca3 4339 flow_flag_set(flow, DUP);
04de7dda
RD		 4340 mutex_lock(&esw->offloads.peer_mutex);
4341 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4342 mutex_unlock(&esw->offloads.peer_mutex);
4343
4344out:
4345 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4346 return err;
4347}
4348
4349static int
4350mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4351 struct flow_cls_offload *f,
226f2ca3 4352 unsigned long flow_flags,
04de7dda
RD		 4353 struct net_device *filter_dev,
4354 struct mlx5e_tc_flow **__flow)
4355{
4356 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4357 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4358 struct mlx5_core_dev *in_mdev = priv->mdev;
4359 struct mlx5e_tc_flow *flow;
4360 int err;
4361
71129676
JG		 4362 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4363 in_mdev);
4364 if (IS_ERR(flow))
4365 return PTR_ERR(flow);
04de7dda
RD		 4366
4367 if (is_peer_flow_needed(flow)) {
95dc1902 4368 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4369 if (err) {
4370 mlx5e_tc_del_fdb_flow(priv, flow);
4371 goto out;
4372 }
4373 }
4374
4375 *__flow = flow;
4376
4377 return 0;
4378
4379out:
4380 return err;
4381}
4382
a88780a9
RD		 4383static int
4384mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4385 struct flow_cls_offload *f,
226f2ca3 4386 unsigned long flow_flags,
d11afc26 4387 struct net_device *filter_dev,
a88780a9
RD		 4388 struct mlx5e_tc_flow **__flow)
4389{
f9e30088 4390 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4391 struct netlink_ext_ack *extack = f->common.extack;
4392 struct mlx5e_tc_flow_parse_attr *parse_attr;
4393 struct mlx5e_tc_flow *flow;
4394 int attr_size, err;
4395
c7569097
AL		 4396 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4397 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4398 return -EOPNOTSUPP;
4399 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4400 return -EOPNOTSUPP;
c7569097 4401 }
bf07aa73 4402
226f2ca3 4403 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4404 attr_size = sizeof(struct mlx5_nic_flow_attr);
4405 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4406 &parse_attr, &flow);
4407 if (err)
4408 goto out;
4409
d11afc26 4410 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4411 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4412
54c177ca
OS		 4413 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4414 f, filter_dev);
d11afc26
OS		 4415 if (err)
4416 goto err_free;
4417
aedd133d
AL		 4418 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4419 &flow->attr->ct_attr, extack);
4420 if (err)
4421 goto err_free;
4422
73867881 4423 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4424 if (err)
4425 goto err_free;
4426
4427 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4428 if (err)
4429 goto err_free;
4430
226f2ca3 4431 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4432 *__flow = flow;
4433
4434 return 0;
e3a2b7ed 4435
e3a2b7ed 4436err_free:
8914add2 4437 flow_flag_set(flow, FAILED);
e68e28b4 4438 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4439 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4440out:
4441 return err;
4442}
4443
4444static int
4445mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4446 struct flow_cls_offload *f,
226f2ca3 4447 unsigned long flags,
d11afc26 4448 struct net_device *filter_dev,
a88780a9
RD		 4449 struct mlx5e_tc_flow **flow)
4450{
4451 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4452 unsigned long flow_flags;
a88780a9
RD		 4453 int err;
4454
4455 get_flags(flags, &flow_flags);
4456
bf07aa73
PB		 4457 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4458 return -EOPNOTSUPP;
4459
f6455de0 4460 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4461 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4462 filter_dev, flow);
a88780a9 4463 else
d11afc26
OS		 4464 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4465 filter_dev, flow);
a88780a9
RD		 4466
4467 return err;
4468}
4469
553f9328
VP		 4470static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4471 struct mlx5e_rep_priv *rpriv)
4472{
4473 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4474 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4475 * function is called from NIC mode.
553f9328 4476 */
2fb15e72 4477 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4478}
4479
71d82d2a 4480int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4481 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4482{
4483 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4484 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4485 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4486 struct mlx5e_tc_flow *flow;
4487 int err = 0;
4488
7dc84de9
RD		 4489 if (!mlx5_esw_hold(priv->mdev))
4490 return -EAGAIN;
4491
4492 mlx5_esw_get(priv->mdev);
4493
c5d326b2
VB		 4494 rcu_read_lock();
4495 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4496 if (flow) {
553f9328
VP		 4497 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4498 * just return 0.
4499 */
4500 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4501 goto rcu_unlock;
553f9328 4502
a88780a9
RD		 4503 NL_SET_ERR_MSG_MOD(extack,
4504 "flow cookie already exists, ignoring");
4505 netdev_warn_once(priv->netdev,
4506 "flow cookie %lx already exists, ignoring\n",
4507 f->cookie);
0e1c1a2f 4508 err = -EEXIST;
c1aea9e1 4509 goto rcu_unlock;
a88780a9 4510 }
c1aea9e1
VB		 4511rcu_unlock:
4512 rcu_read_unlock();
4513 if (flow)
4514 goto out;
a88780a9 4515
7a978759 4516 trace_mlx5e_configure_flower(f);
d11afc26 4517 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4518 if (err)
4519 goto out;
4520
553f9328
VP		 4521 /* Flow rule offloaded to non-uplink representor sharing tc block,
4522 * set the flow's owner dev.
4523 */
4524 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4525 flow->orig_dev = dev;
4526
c5d326b2 4527 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4528 if (err)
4529 goto err_free;
4530
7dc84de9 4531 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4532 return 0;
4533
4534err_free:
5a7e5bcb 4535 mlx5e_flow_put(priv, flow);
a88780a9 4536out:
7dc84de9
RD		 4537 mlx5_esw_put(priv->mdev);
4538 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4539 return err;
4540}
4541
8f8ae895
OG		 4542static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4543{
226f2ca3
VB		 4544 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4545 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4546
226f2ca3
VB		 4547 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4548 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4549}
4550
71d82d2a 4551int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4552 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4553{
d9ee0491 4554 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4555 struct mlx5e_tc_flow *flow;
c5d326b2 4556 int err;
e3a2b7ed 4557
c5d326b2 4558 rcu_read_lock();
ab818362 4559 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4560 if (!flow || !same_flow_direction(flow, flags)) {
4561 err = -EINVAL;
4562 goto errout;
4563 }
e3a2b7ed 4564
c5d326b2
VB		 4565 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4566 * set.
4567 */
4568 if (flow_flag_test_and_set(flow, DELETED)) {
4569 err = -EINVAL;
4570 goto errout;
4571 }
05866c82 4572 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4573 rcu_read_unlock();
e3a2b7ed 4574
7a978759 4575 trace_mlx5e_delete_flower(f);
5a7e5bcb 4576 mlx5e_flow_put(priv, flow);
e3a2b7ed 4577
7dc84de9 4578 mlx5_esw_put(priv->mdev);
e3a2b7ed 4579 return 0;
c5d326b2
VB		 4580
4581errout:
4582 rcu_read_unlock();
4583 return err;
e3a2b7ed
AV		 4584}
4585
71d82d2a 4586int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4587 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4588{
04de7dda 4589 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4590 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4591 struct mlx5_eswitch *peer_esw;
aad7e08d 4592 struct mlx5e_tc_flow *flow;
aad7e08d 4593 struct mlx5_fc *counter;
316d5f72
RD		 4594 u64 lastuse = 0;
4595 u64 packets = 0;
4596 u64 bytes = 0;
5a7e5bcb 4597 int err = 0;
aad7e08d 4598
c5d326b2
VB		 4599 rcu_read_lock();
4600 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4601 tc_ht_params));
4602 rcu_read_unlock();
5a7e5bcb
VB		 4603 if (IS_ERR(flow))
4604 return PTR_ERR(flow);
4605
4606 if (!same_flow_direction(flow, flags)) {
4607 err = -EINVAL;
4608 goto errout;
4609 }
aad7e08d 4610
4c3844d9 4611 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4612 counter = mlx5e_tc_get_counter(flow);
4613 if (!counter)
5a7e5bcb 4614 goto errout;
aad7e08d 4615
316d5f72
RD		 4616 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4617 }
aad7e08d 4618
316d5f72
RD		 4619 /* Under multipath it's possible for one rule to be currently
4620 * un-offloaded while the other rule is offloaded.
4621 */
04de7dda
RD		 4622 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4623 if (!peer_esw)
4624 goto out;
4625
226f2ca3
VB		 4626 if (flow_flag_test(flow, DUP) &&
4627 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4628 u64 bytes2;
4629 u64 packets2;
4630 u64 lastuse2;
4631
4632 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4633 if (!counter)
4634 goto no_peer_counter;
04de7dda
RD		 4635 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4636
4637 bytes += bytes2;
4638 packets += packets2;
4639 lastuse = max_t(u64, lastuse, lastuse2);
4640 }
4641
316d5f72 4642no_peer_counter:
04de7dda 4643 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4644out:
4b61d3e8 4645 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4646 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4647 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4648errout:
4649 mlx5e_flow_put(priv, flow);
4650 return err;
aad7e08d
AV		 4651}
4652
1fe3e316 4653static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4654 struct netlink_ext_ack *extack)
4655{
4656 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4657 struct mlx5_eswitch *esw;
1fe3e316 4658 u32 rate_mbps = 0;
fcb64c0f 4659 u16 vport_num;
fcb64c0f
EC		 4660 int err;
4661
e401a184
EC		 4662 vport_num = rpriv->rep->vport;
4663 if (vport_num >= MLX5_VPORT_ECPF) {
4664 NL_SET_ERR_MSG_MOD(extack,
4665 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4666 return -EOPNOTSUPP;
4667 }
4668
fcb64c0f
EC		 4669 esw = priv->mdev->priv.eswitch;
4670 /* rate is given in bytes/sec.
4671 * First convert to bits/sec and then round to the nearest mbit/secs.
4672 * mbit means million bits.
4673 * Moreover, if rate is non zero we choose to configure to a minimum of
4674 * 1 mbit/sec.
4675 */
1fe3e316
PP		 4676 if (rate) {
4677 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4678 do_div(rate, 1000000);
4679 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4680 }
4681
fcb64c0f
EC		 4682 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4683 if (err)
4684 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4685
4686 return err;
4687}
4688
4689static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4690 struct flow_action *flow_action,
4691 struct netlink_ext_ack *extack)
4692{
4693 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4694 const struct flow_action_entry *act;
4695 int err;
4696 int i;
4697
4698 if (!flow_action_has_entries(flow_action)) {
4699 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4700 return -EINVAL;
4701 }
4702
4703 if (!flow_offload_has_one_action(flow_action)) {
4704 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4705 return -EOPNOTSUPP;
4706 }
4707
53eca1f3 4708 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4709 return -EOPNOTSUPP;
4710
fcb64c0f
EC		 4711 flow_action_for_each(i, act, flow_action) {
4712 switch (act->id) {
4713 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4714 if (act->police.rate_pkt_ps) {
4715 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4716 return -EOPNOTSUPP;
4717 }
fcb64c0f
EC		 4718 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4719 if (err)
4720 return err;
4721
4722 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4723 break;
4724 default:
4725 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4726 return -EOPNOTSUPP;
4727 }
4728 }
4729
4730 return 0;
4731}
4732
4733int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4734 struct tc_cls_matchall_offload *ma)
4735{
b5f814cc 4736 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4737 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4738
b5f814cc
EC		 4739 if (!mlx5_esw_qos_enabled(esw)) {
4740 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4741 return -EOPNOTSUPP;
4742 }
4743
7b83355f 4744 if (ma->common.prio != 1) {
fcb64c0f
EC		 4745 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4746 return -EINVAL;
4747 }
4748
4749 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4750}
4751
4752int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4753 struct tc_cls_matchall_offload *ma)
4754{
4755 struct netlink_ext_ack *extack = ma->common.extack;
4756
4757 return apply_police_params(priv, 0, extack);
4758}
4759
4760void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4761 struct tc_cls_matchall_offload *ma)
4762{
4763 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4764 struct rtnl_link_stats64 cur_stats;
4765 u64 dbytes;
4766 u64 dpkts;
4767
4768 cur_stats = priv->stats.vf_vport;
4769 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4770 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4771 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4772 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4773 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4774}
4775
4d8fcf21
AH		 4776static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4777 struct mlx5e_priv *peer_priv)
4778{
4779 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4780 struct mlx5e_hairpin_entry *hpe, *tmp;
4781 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4782 u16 peer_vhca_id;
4783 int bkt;
4784
4785 if (!same_hw_devs(priv, peer_priv))
4786 return;
4787
4788 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4789
b32accda 4790 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4791 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4792 if (refcount_inc_not_zero(&hpe->refcnt))
4793 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4794 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4795
4796 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4797 wait_for_completion(&hpe->res_ready);
4798 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4799 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4800
4801 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4802 }
4803}
4804
4805static int mlx5e_tc_netdev_event(struct notifier_block *this,
4806 unsigned long event, void *ptr)
4807{
4808 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4809 struct mlx5e_flow_steering *fs;
4810 struct mlx5e_priv *peer_priv;
4811 struct mlx5e_tc_table *tc;
4812 struct mlx5e_priv *priv;
4813
4814 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4815 event != NETDEV_UNREGISTER ||
4816 ndev->reg_state == NETREG_REGISTERED)
4817 return NOTIFY_DONE;
4818
4819 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4820 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4821 priv = container_of(fs, struct mlx5e_priv, fs);
4822 peer_priv = netdev_priv(ndev);
4823 if (priv == peer_priv ||
4824 !(priv->netdev->features & NETIF_F_HW_TC))
4825 return NOTIFY_DONE;
4826
4827 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4828
4829 return NOTIFY_DONE;
4830}
4831
6a064674
AL		 4832static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4833{
4834 int tc_grp_size, tc_tbl_size;
4835 u32 max_flow_counter;
4836
4837 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4838 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4839
4840 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4841
4842 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4843 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4844
4845 return tc_tbl_size;
4846}
4847
655dc3d2 4848int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4849{
acff797c 4850 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4851 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4852 struct mapping_ctx *chains_mapping;
6a064674 4853 struct mlx5_chains_attr attr = {};
4d8fcf21 4854 int err;
e8f887ac 4855
b2fdf3d0 4856 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4857 mutex_init(&tc->t_lock);
b32accda 4858 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4859 hash_init(tc->hairpin_tbl);
11c9c548 4860
4d8fcf21
AH		 4861 err = rhashtable_init(&tc->ht, &tc_ht_params);
4862 if (err)
4863 return err;
4864
9ba33339
RD		 4865 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4866
c9355682
CM		 4867 chains_mapping = mapping_create(sizeof(struct mlx5_mapped_obj),
4868 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4869 if (IS_ERR(chains_mapping)) {
4870 err = PTR_ERR(chains_mapping);
4871 goto err_mapping;
4872 }
4873 tc->mapping = chains_mapping;
4874
4875 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4876 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4877 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4878 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4879 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4880 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4881 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4882 attr.mapping = chains_mapping;
6a064674
AL		 4883
4884 tc->chains = mlx5_chains_create(dev, &attr);
4885 if (IS_ERR(tc->chains)) {
4886 err = PTR_ERR(tc->chains);
4887 goto err_chains;
4888 }
4889
aedd133d
AL		 4890 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
4891 MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4892
4d8fcf21 4893 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4894 err = register_netdevice_notifier_dev_net(priv->netdev,
4895 &tc->netdevice_nb,
4896 &tc->netdevice_nn);
4897 if (err) {
4d8fcf21
AH		 4898 tc->netdevice_nb.notifier_call = NULL;
4899 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4900 goto err_reg;
4d8fcf21
AH		 4901 }
4902
6a064674
AL		 4903 return 0;
4904
4905err_reg:
aedd133d 4906 mlx5_tc_ct_clean(tc->ct);
6a064674
AL		 4907 mlx5_chains_destroy(tc->chains);
4908err_chains:
c9355682
CM		 4909 mapping_destroy(chains_mapping);
4910err_mapping:
6a064674 4911 rhashtable_destroy(&tc->ht);
4d8fcf21 4912 return err;
e8f887ac
AV		 4913}
4914
4915static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4916{
4917 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4918 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4919
961e8979 4920 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4921 kfree(flow);
4922}
4923
655dc3d2 4924void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4925{
acff797c 4926 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4927
4d8fcf21 4928 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4929 unregister_netdevice_notifier_dev_net(priv->netdev,
4930 &tc->netdevice_nb,
4931 &tc->netdevice_nn);
4d8fcf21 4932
b2fdf3d0 4933 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4934 mutex_destroy(&tc->hairpin_tbl_lock);
4935
6a064674 4936 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4937
acff797c 4938 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4939 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4940 tc->t = NULL;
e8f887ac 4941 }
b6fac0b4 4942 mutex_destroy(&tc->t_lock);
6a064674 4943
aedd133d 4944 mlx5_tc_ct_clean(tc->ct);
c9355682 4945 mapping_destroy(tc->mapping);
6a064674 4946 mlx5_chains_destroy(tc->chains);
e8f887ac 4947}
655dc3d2
OG		 4948
4949int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4950{
d7a42ad0 4951 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4952 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4953 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4954 struct mapping_ctx *mapping;
aedd133d
AL		 4955 struct mlx5_eswitch *esw;
4956 struct mlx5e_priv *priv;
4957 int err = 0;
0a7fcb78
PB		 4958
4959 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4960 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4961 priv = netdev_priv(rpriv->netdev);
4962 esw = priv->mdev->priv.eswitch;
0a7fcb78 4963
aedd133d
AL		 4964 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4965 esw_chains(esw),
4966 &esw->offloads.mod_hdr,
4967 MLX5_FLOW_NAMESPACE_FDB);
4c3844d9 4968
2a9ab10a
CM		 4969#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4970 uplink_priv->esw_psample = mlx5_esw_sample_init(netdev_priv(priv->netdev));
4971#endif
4972
0a7fcb78
PB		 4973 mapping = mapping_create(sizeof(struct tunnel_match_key),
4974 TUNNEL_INFO_BITS_MASK, true);
4975 if (IS_ERR(mapping)) {
4976 err = PTR_ERR(mapping);
4977 goto err_tun_mapping;
4978 }
4979 uplink_priv->tunnel_mapping = mapping;
4980
8e404fef
VB		 4981 /* 0xFFF is reserved for stack devices slow path table mark */
4982 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 4983 if (IS_ERR(mapping)) {
4984 err = PTR_ERR(mapping);
4985 goto err_enc_opts_mapping;
4986 }
4987 uplink_priv->tunnel_enc_opts_mapping = mapping;
4988
4989 err = rhashtable_init(tc_ht, &tc_ht_params);
4990 if (err)
4991 goto err_ht_init;
4992
9ba33339
RD		 4993 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4994
8914add2 4995 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4996 if (IS_ERR(uplink_priv->encap)) {
4997 err = PTR_ERR(uplink_priv->encap);
8914add2 4998 goto err_register_fib_notifier;
2b6c3c1e 4999 }
8914add2 5000
2b6c3c1e 5001 return 0;
0a7fcb78 5002
8914add2
VB		 5003err_register_fib_notifier:
5004 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5005err_ht_init:
5006 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5007err_enc_opts_mapping:
5008 mapping_destroy(uplink_priv->tunnel_mapping);
5009err_tun_mapping:
2a9ab10a
CM		 5010#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
5011 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
5012#endif
aedd133d 5013 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5014 netdev_warn(priv->netdev,
5015 "Failed to initialize tc (eswitch), err: %d", err);
5016 return err;
655dc3d2
OG		 5017}
5018
5019void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5020{
0a7fcb78
PB		 5021 struct mlx5_rep_uplink_priv *uplink_priv;
5022
0a7fcb78 5023 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5024
8914add2
VB		 5025 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5026 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5027
0a7fcb78
PB		 5028 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5029 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5030
2a9ab10a
CM		 5031#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
5032 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
5033#endif
aedd133d 5034 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 5035}
01252a27 5036
226f2ca3 5037int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5038{
d9ee0491 5039 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5040
5041 return atomic_read(&tc_ht->nelems);
5042}
04de7dda
RD		 5043
5044void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5045{
5046 struct mlx5e_tc_flow *flow, *tmp;
5047
5048 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5049 __mlx5e_tc_del_fdb_peer_flow(flow);
5050}
b4a23329
RD		 5051
5052void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5053{
5054 struct mlx5_rep_uplink_priv *rpriv =
5055 container_of(work, struct mlx5_rep_uplink_priv,
5056 reoffload_flows_work);
5057 struct mlx5e_tc_flow *flow, *tmp;
5058
ad86755b 5059 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5060 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5061 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5062 unready_flow_del(flow);
b4a23329 5063 }
ad86755b 5064 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5065}
e2394a61
VB		 5066
5067static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5068 struct flow_cls_offload *cls_flower,
5069 unsigned long flags)
5070{
5071 switch (cls_flower->command) {
5072 case FLOW_CLS_REPLACE:
5073 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5074 flags);
5075 case FLOW_CLS_DESTROY:
5076 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5077 flags);
5078 case FLOW_CLS_STATS:
5079 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5080 flags);
5081 default:
5082 return -EOPNOTSUPP;
5083 }
5084}
5085
5086int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5087 void *cb_priv)
5088{
ec9457a6 5089 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5090 struct mlx5e_priv *priv = cb_priv;
5091
2ff349c5
RD		 5092 if (!priv->netdev || !netif_device_present(priv->netdev))
5093 return -EOPNOTSUPP;
5094
ec9457a6
RD		 5095 if (mlx5e_is_uplink_rep(priv))
5096 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5097 else
5098 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5099
e2394a61
VB		 5100 switch (type) {
5101 case TC_SETUP_CLSFLOWER:
5102 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5103 default:
5104 return -EOPNOTSUPP;
5105 }
5106}
c7569097
AL		 5107
5108bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5109 struct sk_buff *skb)
5110{
5111#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5112 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5113 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5114 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5115 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5116 struct tc_skb_ext *tc_skb_ext;
5117 int err;
5118
5119 reg_b = be32_to_cpu(cqe->ft_metadata);
5120
5121 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5122
c9355682 5123 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5124 if (err) {
5125 netdev_dbg(priv->netdev,
5126 "Couldn't find chain for chain tag: %d, err: %d\n",
5127 chain_tag, err);
5128 return false;
5129 }
5130
a91d98a0
CM		 5131 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5132 chain = mapped_obj.chain;
9453d45e 5133 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5134 if (WARN_ON(!tc_skb_ext))
5135 return false;
5136
5137 tc_skb_ext->chain = chain;
aedd133d 5138
ed2fe7ba 5139 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5140 ESW_ZONE_ID_MASK;
aedd133d
AL		 5141
5142 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5143 zone_restore_id))
5144 return false;
a91d98a0
CM		 5145 } else {
5146 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5147 return false;
c7569097
AL		 5148 }
5149#endif /* CONFIG_NET_TC_SKB_EXT */
5150
5151 return true;
5152}
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