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net/mlx5e: Remove wrong and superfluous tc pedit header type check
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e 41#include <net/tc_act/tc_mirred.h>
776b12b6 42#include <net/tc_act/tc_vlan.h>
bbd00f7e 43#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 44#include <net/tc_act/tc_pedit.h>
26c02749 45#include <net/tc_act/tc_csum.h>
f6dfb4c3 46#include <net/arp.h>
e8f887ac 47#include "en.h"
1d447a39 48#include "en_rep.h"
232c0013 49#include "en_tc.h"
03a9d11e 50#include "eswitch.h"
3f6d08d1 51#include "fs_core.h"
2c81bfd5 52#include "en/port.h"
101f4de9 53#include "en/tc_tun.h"
04de7dda 54#include "lib/devcom.h"
e8f887ac 55
3bc4b7bf
OG		 56struct mlx5_nic_flow_attr {
57 u32 action;
58 u32 flow_tag;
2f4fe4ca 59 u32 mod_hdr_id;
5c65c564 60 u32 hairpin_tirn;
38aa51c1 61 u8 match_level;
3f6d08d1 62 struct mlx5_flow_table *hairpin_ft;
b8aee822 63 struct mlx5_fc *counter;
3bc4b7bf
OG		 64};
65
60bd4af8
OG		 66#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
67
65ba8fb7 68enum {
60bd4af8
OG		 69 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
70 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
d9ee0491
OG		 71 MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD,
72 MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD,
73 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE),
74 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1),
75 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2),
76 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3),
77 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4),
65ba8fb7
OG		 78};
79
e4ad91f2
CM		 80#define MLX5E_TC_MAX_SPLITS 1
81
79baaec7
EB		 82/* Helper struct for accessing a struct containing list_head array.
83 * Containing struct
84 * |- Helper array
85 * [0] Helper item 0
86 * |- list_head item 0
87 * |- index (0)
88 * [1] Helper item 1
89 * |- list_head item 1
90 * |- index (1)
91 * To access the containing struct from one of the list_head items:
92 * 1. Get the helper item from the list_head item using
93 * helper item =
94 * container_of(list_head item, helper struct type, list_head field)
95 * 2. Get the contining struct from the helper item and its index in the array:
96 * containing struct =
97 * container_of(helper item, containing struct type, helper field[index])
98 */
99struct encap_flow_item {
100 struct list_head list;
101 int index;
102};
103
e8f887ac
AV		 104struct mlx5e_tc_flow {
105 struct rhash_head node;
655dc3d2 106 struct mlx5e_priv *priv;
e8f887ac 107 u64 cookie;
5dbe906f 108 u16 flags;
e4ad91f2 109 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 110 /* Flow can be associated with multiple encap IDs.
111 * The number of encaps is bounded by the number of supported
112 * destinations.
113 */
114 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 115 struct mlx5e_tc_flow *peer_flow;
11c9c548 116 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 117 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 118 struct list_head peer; /* flows with peer flow */
3bc4b7bf
OG		 119 union {
120 struct mlx5_esw_flow_attr esw_attr[0];
121 struct mlx5_nic_flow_attr nic_attr[0];
122 };
e8f887ac
AV		 123};
124
17091853 125struct mlx5e_tc_flow_parse_attr {
98b66cb1 126 struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 127 struct net_device *filter_dev;
17091853 128 struct mlx5_flow_spec spec;
d79b6df6 129 int num_mod_hdr_actions;
218d05ce 130 int max_mod_hdr_actions;
d79b6df6 131 void *mod_hdr_actions;
98b66cb1 132 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 133};
134
acff797c 135#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 136#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 137
77ab67b7
OG		 138struct mlx5e_hairpin {
139 struct mlx5_hairpin *pair;
140
141 struct mlx5_core_dev *func_mdev;
3f6d08d1 142 struct mlx5e_priv *func_priv;
77ab67b7
OG		 143 u32 tdn;
144 u32 tirn;
3f6d08d1
OG		 145
146 int num_channels;
147 struct mlx5e_rqt indir_rqt;
148 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
149 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 150};
151
5c65c564
OG		 152struct mlx5e_hairpin_entry {
153 /* a node of a hash table which keeps all the hairpin entries */
154 struct hlist_node hairpin_hlist;
155
156 /* flows sharing the same hairpin */
157 struct list_head flows;
158
d8822868 159 u16 peer_vhca_id;
106be53b 160 u8 prio;
5c65c564
OG		 161 struct mlx5e_hairpin *hp;
162};
163
11c9c548
OG		 164struct mod_hdr_key {
165 int num_actions;
166 void *actions;
167};
168
169struct mlx5e_mod_hdr_entry {
170 /* a node of a hash table which keeps all the mod_hdr entries */
171 struct hlist_node mod_hdr_hlist;
172
173 /* flows sharing the same mod_hdr entry */
174 struct list_head flows;
175
176 struct mod_hdr_key key;
177
178 u32 mod_hdr_id;
179};
180
181#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
182
183static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
184{
185 return jhash(key->actions,
186 key->num_actions * MLX5_MH_ACT_SZ, 0);
187}
188
189static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
190 struct mod_hdr_key *b)
191{
192 if (a->num_actions != b->num_actions)
193 return 1;
194
195 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
196}
197
198static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
199 struct mlx5e_tc_flow *flow,
200 struct mlx5e_tc_flow_parse_attr *parse_attr)
201{
202 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
203 int num_actions, actions_size, namespace, err;
204 struct mlx5e_mod_hdr_entry *mh;
205 struct mod_hdr_key key;
206 bool found = false;
207 u32 hash_key;
208
209 num_actions = parse_attr->num_mod_hdr_actions;
210 actions_size = MLX5_MH_ACT_SZ * num_actions;
211
212 key.actions = parse_attr->mod_hdr_actions;
213 key.num_actions = num_actions;
214
215 hash_key = hash_mod_hdr_info(&key);
216
217 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
218 namespace = MLX5_FLOW_NAMESPACE_FDB;
219 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
220 mod_hdr_hlist, hash_key) {
221 if (!cmp_mod_hdr_info(&mh->key, &key)) {
222 found = true;
223 break;
224 }
225 }
226 } else {
227 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
228 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
229 mod_hdr_hlist, hash_key) {
230 if (!cmp_mod_hdr_info(&mh->key, &key)) {
231 found = true;
232 break;
233 }
234 }
235 }
236
237 if (found)
238 goto attach_flow;
239
240 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
241 if (!mh)
242 return -ENOMEM;
243
244 mh->key.actions = (void *)mh + sizeof(*mh);
245 memcpy(mh->key.actions, key.actions, actions_size);
246 mh->key.num_actions = num_actions;
247 INIT_LIST_HEAD(&mh->flows);
248
249 err = mlx5_modify_header_alloc(priv->mdev, namespace,
250 mh->key.num_actions,
251 mh->key.actions,
252 &mh->mod_hdr_id);
253 if (err)
254 goto out_err;
255
256 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
257 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
258 else
259 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
260
261attach_flow:
262 list_add(&flow->mod_hdr, &mh->flows);
263 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
264 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
265 else
266 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
267
268 return 0;
269
270out_err:
271 kfree(mh);
272 return err;
273}
274
275static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
276 struct mlx5e_tc_flow *flow)
277{
278 struct list_head *next = flow->mod_hdr.next;
279
280 list_del(&flow->mod_hdr);
281
282 if (list_empty(next)) {
283 struct mlx5e_mod_hdr_entry *mh;
284
285 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
286
287 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
288 hash_del(&mh->mod_hdr_hlist);
289 kfree(mh);
290 }
291}
292
77ab67b7
OG		 293static
294struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
295{
296 struct net_device *netdev;
297 struct mlx5e_priv *priv;
298
299 netdev = __dev_get_by_index(net, ifindex);
300 priv = netdev_priv(netdev);
301 return priv->mdev;
302}
303
304static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
305{
306 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
307 void *tirc;
308 int err;
309
310 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
311 if (err)
312 goto alloc_tdn_err;
313
314 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
315
316 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 317 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 318 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
319
320 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
321 if (err)
322 goto create_tir_err;
323
324 return 0;
325
326create_tir_err:
327 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
328alloc_tdn_err:
329 return err;
330}
331
332static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
333{
334 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
335 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
336}
337
3f6d08d1
OG		 338static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
339{
340 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
341 struct mlx5e_priv *priv = hp->func_priv;
342 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
343
344 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
345 hp->num_channels);
346
347 for (i = 0; i < sz; i++) {
348 ix = i;
bbeb53b8 349 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 350 ix = mlx5e_bits_invert(i, ilog2(sz));
351 ix = indirection_rqt[ix];
352 rqn = hp->pair->rqn[ix];
353 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
354 }
355}
356
357static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
358{
359 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
360 struct mlx5e_priv *priv = hp->func_priv;
361 struct mlx5_core_dev *mdev = priv->mdev;
362 void *rqtc;
363 u32 *in;
364
365 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
366 in = kvzalloc(inlen, GFP_KERNEL);
367 if (!in)
368 return -ENOMEM;
369
370 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
371
372 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
373 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
374
375 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
376
377 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
378 if (!err)
379 hp->indir_rqt.enabled = true;
380
381 kvfree(in);
382 return err;
383}
384
385static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
386{
387 struct mlx5e_priv *priv = hp->func_priv;
388 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
389 int tt, i, err;
390 void *tirc;
391
392 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 393 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
394
3f6d08d1
OG		 395 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
396 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
397
398 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
399 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
400 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 401 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
402
3f6d08d1
OG		 403 err = mlx5_core_create_tir(hp->func_mdev, in,
404 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
405 if (err) {
406 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
407 goto err_destroy_tirs;
408 }
409 }
410 return 0;
411
412err_destroy_tirs:
413 for (i = 0; i < tt; i++)
414 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
415 return err;
416}
417
418static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
419{
420 int tt;
421
422 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
423 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
424}
425
426static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
427 struct ttc_params *ttc_params)
428{
429 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
430 int tt;
431
432 memset(ttc_params, 0, sizeof(*ttc_params));
433
434 ttc_params->any_tt_tirn = hp->tirn;
435
436 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
437 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
438
439 ft_attr->max_fte = MLX5E_NUM_TT;
440 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
441 ft_attr->prio = MLX5E_TC_PRIO;
442}
443
444static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
445{
446 struct mlx5e_priv *priv = hp->func_priv;
447 struct ttc_params ttc_params;
448 int err;
449
450 err = mlx5e_hairpin_create_indirect_rqt(hp);
451 if (err)
452 return err;
453
454 err = mlx5e_hairpin_create_indirect_tirs(hp);
455 if (err)
456 goto err_create_indirect_tirs;
457
458 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
459 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
460 if (err)
461 goto err_create_ttc_table;
462
463 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
464 hp->num_channels, hp->ttc.ft.t->id);
465
466 return 0;
467
468err_create_ttc_table:
469 mlx5e_hairpin_destroy_indirect_tirs(hp);
470err_create_indirect_tirs:
471 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
472
473 return err;
474}
475
476static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
477{
478 struct mlx5e_priv *priv = hp->func_priv;
479
480 mlx5e_destroy_ttc_table(priv, &hp->ttc);
481 mlx5e_hairpin_destroy_indirect_tirs(hp);
482 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
483}
484
77ab67b7
OG		 485static struct mlx5e_hairpin *
486mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
487 int peer_ifindex)
488{
489 struct mlx5_core_dev *func_mdev, *peer_mdev;
490 struct mlx5e_hairpin *hp;
491 struct mlx5_hairpin *pair;
492 int err;
493
494 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
495 if (!hp)
496 return ERR_PTR(-ENOMEM);
497
498 func_mdev = priv->mdev;
499 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
500
501 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
502 if (IS_ERR(pair)) {
503 err = PTR_ERR(pair);
504 goto create_pair_err;
505 }
506 hp->pair = pair;
507 hp->func_mdev = func_mdev;
3f6d08d1
OG		 508 hp->func_priv = priv;
509 hp->num_channels = params->num_channels;
77ab67b7
OG		 510
511 err = mlx5e_hairpin_create_transport(hp);
512 if (err)
513 goto create_transport_err;
514
3f6d08d1
OG		 515 if (hp->num_channels > 1) {
516 err = mlx5e_hairpin_rss_init(hp);
517 if (err)
518 goto rss_init_err;
519 }
520
77ab67b7
OG		 521 return hp;
522
3f6d08d1
OG		 523rss_init_err:
524 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 525create_transport_err:
526 mlx5_core_hairpin_destroy(hp->pair);
527create_pair_err:
528 kfree(hp);
529 return ERR_PTR(err);
530}
531
532static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
533{
3f6d08d1
OG		 534 if (hp->num_channels > 1)
535 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 536 mlx5e_hairpin_destroy_transport(hp);
537 mlx5_core_hairpin_destroy(hp->pair);
538 kvfree(hp);
539}
540
106be53b
OG		 541static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
542{
543 return (peer_vhca_id << 16 | prio);
544}
545
5c65c564 546static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 547 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 548{
549 struct mlx5e_hairpin_entry *hpe;
106be53b 550 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 551
552 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 553 hairpin_hlist, hash_key) {
554 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 555 return hpe;
556 }
557
558 return NULL;
559}
560
106be53b
OG		 561#define UNKNOWN_MATCH_PRIO 8
562
563static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 564 struct mlx5_flow_spec *spec, u8 *match_prio,
565 struct netlink_ext_ack *extack)
106be53b
OG		 566{
567 void *headers_c, *headers_v;
568 u8 prio_val, prio_mask = 0;
569 bool vlan_present;
570
571#ifdef CONFIG_MLX5_CORE_EN_DCB
572 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 573 NL_SET_ERR_MSG_MOD(extack,
574 "only PCP trust state supported for hairpin");
106be53b
OG		 575 return -EOPNOTSUPP;
576 }
577#endif
578 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
579 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
580
581 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
582 if (vlan_present) {
583 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
584 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
585 }
586
587 if (!vlan_present || !prio_mask) {
588 prio_val = UNKNOWN_MATCH_PRIO;
589 } else if (prio_mask != 0x7) {
e98bedf5
EB		 590 NL_SET_ERR_MSG_MOD(extack,
591 "masked priority match not supported for hairpin");
106be53b
OG		 592 return -EOPNOTSUPP;
593 }
594
595 *match_prio = prio_val;
596 return 0;
597}
598
5c65c564
OG		 599static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
600 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 601 struct mlx5e_tc_flow_parse_attr *parse_attr,
602 struct netlink_ext_ack *extack)
5c65c564 603{
98b66cb1 604 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 605 struct mlx5_hairpin_params params;
d8822868 606 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 607 struct mlx5e_hairpin_entry *hpe;
608 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 609 u64 link_speed64;
610 u32 link_speed;
106be53b 611 u8 match_prio;
d8822868 612 u16 peer_id;
5c65c564
OG		 613 int err;
614
d8822868
OG		 615 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
616 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 617 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 618 return -EOPNOTSUPP;
619 }
620
d8822868 621 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 622 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
623 extack);
106be53b
OG		 624 if (err)
625 return err;
626 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 627 if (hpe)
628 goto attach_flow;
629
630 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
631 if (!hpe)
632 return -ENOMEM;
633
634 INIT_LIST_HEAD(&hpe->flows);
d8822868 635 hpe->peer_vhca_id = peer_id;
106be53b 636 hpe->prio = match_prio;
5c65c564
OG		 637
638 params.log_data_size = 15;
639 params.log_data_size = min_t(u8, params.log_data_size,
640 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
641 params.log_data_size = max_t(u8, params.log_data_size,
642 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 643
eb9180f7
OG		 644 params.log_num_packets = params.log_data_size -
645 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
646 params.log_num_packets = min_t(u8, params.log_num_packets,
647 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
648
649 params.q_counter = priv->q_counter;
3f6d08d1 650 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 651 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 652 link_speed = max_t(u32, link_speed, 50000);
653 link_speed64 = link_speed;
654 do_div(link_speed64, 50000);
655 params.num_channels = link_speed64;
656
5c65c564
OG		 657 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
658 if (IS_ERR(hp)) {
659 err = PTR_ERR(hp);
660 goto create_hairpin_err;
661 }
662
eb9180f7 663 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 664 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 665 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 666
667 hpe->hp = hp;
106be53b
OG		 668 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
669 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 670
671attach_flow:
3f6d08d1
OG		 672 if (hpe->hp->num_channels > 1) {
673 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
674 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
675 } else {
676 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
677 }
5c65c564 678 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 679
5c65c564
OG		 680 return 0;
681
682create_hairpin_err:
683 kfree(hpe);
684 return err;
685}
686
687static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
688 struct mlx5e_tc_flow *flow)
689{
690 struct list_head *next = flow->hairpin.next;
691
692 list_del(&flow->hairpin);
693
694 /* no more hairpin flows for us, release the hairpin pair */
695 if (list_empty(next)) {
696 struct mlx5e_hairpin_entry *hpe;
697
698 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
699
700 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
701 hpe->hp->pair->peer_mdev->priv.name);
702
703 mlx5e_hairpin_destroy(hpe->hp);
704 hash_del(&hpe->hairpin_hlist);
705 kfree(hpe);
706 }
707}
708
c83954ab 709static int
74491de9 710mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 711 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 712 struct mlx5e_tc_flow *flow,
713 struct netlink_ext_ack *extack)
e8f887ac 714{
aa0cbbae 715 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 716 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 717 struct mlx5_flow_destination dest[2] = {};
66958ed9 718 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 719 .action = attr->action,
720 .flow_tag = attr->flow_tag,
60786f09 721 .reformat_id = 0,
42f7ad67 722 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 723 };
aad7e08d 724 struct mlx5_fc *counter = NULL;
e8f887ac 725 bool table_created = false;
5c65c564 726 int err, dest_ix = 0;
e8f887ac 727
3f6d08d1 728 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 729 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 730 if (err) {
3f6d08d1
OG		 731 goto err_add_hairpin_flow;
732 }
733 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
734 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
735 dest[dest_ix].ft = attr->hairpin_ft;
736 } else {
5c65c564
OG		 737 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
738 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 739 }
740 dest_ix++;
3f6d08d1
OG		 741 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
742 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
743 dest[dest_ix].ft = priv->fs.vlan.ft.t;
744 dest_ix++;
5c65c564 745 }
aad7e08d 746
5c65c564
OG		 747 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
748 counter = mlx5_fc_create(dev, true);
749 if (IS_ERR(counter)) {
c83954ab 750 err = PTR_ERR(counter);
5c65c564
OG		 751 goto err_fc_create;
752 }
753 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 754 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 755 dest_ix++;
b8aee822 756 attr->counter = counter;
aad7e08d
AV		 757 }
758
2f4fe4ca 759 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 760 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 761 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 762 kfree(parse_attr->mod_hdr_actions);
c83954ab 763 if (err)
2f4fe4ca 764 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 765 }
766
acff797c 767 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 768 int tc_grp_size, tc_tbl_size;
769 u32 max_flow_counter;
770
771 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
772 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
773
774 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
775
776 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
777 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
778
acff797c
MG		 779 priv->fs.tc.t =
780 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
781 MLX5E_TC_PRIO,
21b9c144 782 tc_tbl_size,
acff797c 783 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 784 MLX5E_TC_FT_LEVEL, 0);
acff797c 785 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 786 NL_SET_ERR_MSG_MOD(extack,
787 "Failed to create tc offload table\n");
e8f887ac
AV		 788 netdev_err(priv->netdev,
789 "Failed to create tc offload table\n");
c83954ab 790 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 791 goto err_create_ft;
e8f887ac
AV		 792 }
793
794 table_created = true;
795 }
796
38aa51c1
OG		 797 if (attr->match_level != MLX5_MATCH_NONE)
798 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
799
c83954ab
RL		 800 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
801 &flow_act, dest, dest_ix);
aad7e08d 802
c83954ab
RL		 803 if (IS_ERR(flow->rule[0])) {
804 err = PTR_ERR(flow->rule[0]);
aad7e08d 805 goto err_add_rule;
c83954ab 806 }
aad7e08d 807
c83954ab 808 return 0;
e8f887ac 809
aad7e08d
AV		 810err_add_rule:
811 if (table_created) {
acff797c
MG		 812 mlx5_destroy_flow_table(priv->fs.tc.t);
813 priv->fs.tc.t = NULL;
e8f887ac 814 }
aad7e08d 815err_create_ft:
2f4fe4ca 816 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 817 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 818err_create_mod_hdr_id:
aad7e08d 819 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 820err_fc_create:
821 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
822 mlx5e_hairpin_flow_del(priv, flow);
823err_add_hairpin_flow:
c83954ab 824 return err;
e8f887ac
AV		 825}
826
d85cdccb
OG		 827static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
828 struct mlx5e_tc_flow *flow)
829{
513f8f7f 830 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 831 struct mlx5_fc *counter = NULL;
832
b8aee822 833 counter = attr->counter;
e4ad91f2 834 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 835 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 836
d9ee0491 837 if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) {
d85cdccb
OG		 838 mlx5_destroy_flow_table(priv->fs.tc.t);
839 priv->fs.tc.t = NULL;
840 }
2f4fe4ca 841
513f8f7f 842 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 843 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 844
845 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
846 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 847}
848
aa0cbbae 849static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 850 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 851
3c37745e
OG		 852static int mlx5e_attach_encap(struct mlx5e_priv *priv,
853 struct ip_tunnel_info *tun_info,
854 struct net_device *mirred_dev,
855 struct net_device **encap_dev,
e98bedf5 856 struct mlx5e_tc_flow *flow,
8c4dc42b
EB		 857 struct netlink_ext_ack *extack,
858 int out_index);
3c37745e 859
6d2a3ed0
OG		 860static struct mlx5_flow_handle *
861mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
862 struct mlx5e_tc_flow *flow,
863 struct mlx5_flow_spec *spec,
864 struct mlx5_esw_flow_attr *attr)
865{
866 struct mlx5_flow_handle *rule;
867
868 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
869 if (IS_ERR(rule))
870 return rule;
871
e85e02ba 872 if (attr->split_count) {
6d2a3ed0
OG		 873 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
874 if (IS_ERR(flow->rule[1])) {
875 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
876 return flow->rule[1];
877 }
878 }
879
880 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
881 return rule;
882}
883
884static void
885mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
886 struct mlx5e_tc_flow *flow,
887 struct mlx5_esw_flow_attr *attr)
888{
889 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
890
e85e02ba 891 if (attr->split_count)
6d2a3ed0
OG		 892 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
893
894 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
895}
896
5dbe906f
PB		 897static struct mlx5_flow_handle *
898mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
899 struct mlx5e_tc_flow *flow,
900 struct mlx5_flow_spec *spec,
901 struct mlx5_esw_flow_attr *slow_attr)
902{
903 struct mlx5_flow_handle *rule;
904
905 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 906 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 907 slow_attr->split_count = 0;
154e62ab 908 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 909
910 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
911 if (!IS_ERR(rule))
912 flow->flags |= MLX5E_TC_FLOW_SLOW;
913
914 return rule;
915}
916
917static void
918mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
919 struct mlx5e_tc_flow *flow,
920 struct mlx5_esw_flow_attr *slow_attr)
921{
922 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 923 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 924 slow_attr->split_count = 0;
154e62ab 925 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 926 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
927 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
928}
929
c83954ab 930static int
74491de9 931mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 932 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 933 struct mlx5e_tc_flow *flow,
934 struct netlink_ext_ack *extack)
adb4c123
OG		 935{
936 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 937 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 938 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
bf07aa73 939 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 940 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 941 struct mlx5_fc *counter = NULL;
3c37745e
OG		 942 struct mlx5e_rep_priv *rpriv;
943 struct mlx5e_priv *out_priv;
c83954ab 944 int err = 0, encap_err = 0;
f493f155 945 int out_index;
8b32580d 946
d14f6f2a
OG		 947 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
948 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
949 return -EOPNOTSUPP;
950 }
bf07aa73
PB		 951
952 if (attr->chain > max_chain) {
953 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
954 err = -EOPNOTSUPP;
955 goto err_max_prio_chain;
956 }
957
958 if (attr->prio > max_prio) {
959 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
960 err = -EOPNOTSUPP;
961 goto err_max_prio_chain;
962 }
e52c2802 963
f493f155 964 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 965 int mirred_ifindex;
966
f493f155
EB		 967 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
968 continue;
969
8c4dc42b 970 mirred_ifindex = attr->parse_attr->mirred_ifindex[out_index];
3c37745e 971 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b
EB		 972 mirred_ifindex);
973 err = mlx5e_attach_encap(priv,
974 &parse_attr->tun_info[out_index],
975 out_dev, &encap_dev, flow,
976 extack, out_index);
977 if (err && err != -EAGAIN)
c83954ab 978 goto err_attach_encap;
8c4dc42b
EB		 979 if (err == -EAGAIN)
980 encap_err = err;
3c37745e
OG		 981 out_priv = netdev_priv(encap_dev);
982 rpriv = out_priv->ppriv;
1cc26d74
EB		 983 attr->dests[out_index].rep = rpriv->rep;
984 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 985 }
986
8b32580d 987 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 988 if (err)
aa0cbbae 989 goto err_add_vlan;
adb4c123 990
d7e75a32 991 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 992 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 993 kfree(parse_attr->mod_hdr_actions);
c83954ab 994 if (err)
d7e75a32 995 goto err_mod_hdr;
d7e75a32
OG		 996 }
997
b8aee822 998 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 999 counter = mlx5_fc_create(attr->counter_dev, true);
b8aee822 1000 if (IS_ERR(counter)) {
c83954ab 1001 err = PTR_ERR(counter);
b8aee822
MB		 1002 goto err_create_counter;
1003 }
1004
1005 attr->counter = counter;
1006 }
1007
c83954ab 1008 /* we get here if (1) there's no error or when
3c37745e
OG		 1009 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
1010 */
5dbe906f
PB		 1011 if (encap_err == -EAGAIN) {
1012 /* continue with goto slow path rule instead */
1013 struct mlx5_esw_flow_attr slow_attr;
1014
1015 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1016 } else {
6d2a3ed0 1017 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1018 }
c83954ab 1019
5dbe906f
PB		 1020 if (IS_ERR(flow->rule[0])) {
1021 err = PTR_ERR(flow->rule[0]);
1022 goto err_add_rule;
1023 }
1024
1025 return 0;
aa0cbbae
OG		 1026
1027err_add_rule:
f9392795 1028 mlx5_fc_destroy(attr->counter_dev, counter);
b8aee822 1029err_create_counter:
513f8f7f 1030 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1031 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 1032err_mod_hdr:
aa0cbbae
OG		 1033 mlx5_eswitch_del_vlan_action(esw, attr);
1034err_add_vlan:
f493f155 1035 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1036 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1037 mlx5e_detach_encap(priv, flow, out_index);
3c37745e 1038err_attach_encap:
bf07aa73 1039err_max_prio_chain:
c83954ab 1040 return err;
aa0cbbae 1041}
d85cdccb
OG		 1042
1043static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1044 struct mlx5e_tc_flow *flow)
1045{
1046 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1047 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1048 struct mlx5_esw_flow_attr slow_attr;
f493f155 1049 int out_index;
d85cdccb 1050
5dbe906f
PB		 1051 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1052 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1053 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1054 else
1055 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1056 }
d85cdccb 1057
513f8f7f 1058 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1059
f493f155 1060 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1061 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1062 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1063 kvfree(attr->parse_attr);
d7e75a32 1064
513f8f7f 1065 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1066 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1067
1068 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1069 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1070}
1071
232c0013
HHZ		 1072void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1073 struct mlx5e_encap_entry *e)
1074{
3c37745e 1075 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1076 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1077 struct mlx5_flow_handle *rule;
1078 struct mlx5_flow_spec *spec;
79baaec7 1079 struct encap_flow_item *efi;
232c0013
HHZ		 1080 struct mlx5e_tc_flow *flow;
1081 int err;
1082
54c177ca
OS		 1083 err = mlx5_packet_reformat_alloc(priv->mdev,
1084 e->reformat_type,
60786f09 1085 e->encap_size, e->encap_header,
31ca3648 1086 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1087 &e->encap_id);
232c0013
HHZ		 1088 if (err) {
1089 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1090 err);
1091 return;
1092 }
1093 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1094 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1095
79baaec7 1096 list_for_each_entry(efi, &e->flows, list) {
8c4dc42b
EB		 1097 bool all_flow_encaps_valid = true;
1098 int i;
1099
79baaec7 1100 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
3c37745e 1101 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1102 spec = &esw_attr->parse_attr->spec;
1103
8c4dc42b
EB		 1104 esw_attr->dests[efi->index].encap_id = e->encap_id;
1105 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1106 /* Flow can be associated with multiple encap entries.
1107 * Before offloading the flow verify that all of them have
1108 * a valid neighbour.
1109 */
1110 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1111 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1112 continue;
1113 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1114 all_flow_encaps_valid = false;
1115 break;
1116 }
1117 }
1118 /* Do not offload flows with unresolved neighbors */
1119 if (!all_flow_encaps_valid)
1120 continue;
5dbe906f 1121 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1122 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1123 if (IS_ERR(rule)) {
1124 err = PTR_ERR(rule);
232c0013
HHZ		 1125 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1126 err);
1127 continue;
1128 }
5dbe906f
PB		 1129
1130 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1131 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1132 flow->rule[0] = rule;
232c0013
HHZ		 1133 }
1134}
1135
1136void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1137 struct mlx5e_encap_entry *e)
1138{
3c37745e 1139 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1140 struct mlx5_esw_flow_attr slow_attr;
1141 struct mlx5_flow_handle *rule;
1142 struct mlx5_flow_spec *spec;
79baaec7 1143 struct encap_flow_item *efi;
232c0013 1144 struct mlx5e_tc_flow *flow;
5dbe906f 1145 int err;
232c0013 1146
79baaec7
EB		 1147 list_for_each_entry(efi, &e->flows, list) {
1148 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5dbe906f
PB		 1149 spec = &flow->esw_attr->parse_attr->spec;
1150
1151 /* update from encap rule to slow path rule */
1152 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1153 /* mark the flow's encap dest as non-valid */
1154 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1155
1156 if (IS_ERR(rule)) {
1157 err = PTR_ERR(rule);
1158 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1159 err);
1160 continue;
1161 }
1162
1163 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1164 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1165 flow->rule[0] = rule;
232c0013
HHZ		 1166 }
1167
61c806da
OG		 1168 /* we know that the encap is valid */
1169 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1170 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1171}
1172
b8aee822
MB		 1173static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1174{
1175 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1176 return flow->esw_attr->counter;
1177 else
1178 return flow->nic_attr->counter;
1179}
1180
f6dfb4c3
HHZ		 1181void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1182{
1183 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1184 u64 bytes, packets, lastuse = 0;
1185 struct mlx5e_tc_flow *flow;
1186 struct mlx5e_encap_entry *e;
1187 struct mlx5_fc *counter;
1188 struct neigh_table *tbl;
1189 bool neigh_used = false;
1190 struct neighbour *n;
1191
1192 if (m_neigh->family == AF_INET)
1193 tbl = &arp_tbl;
1194#if IS_ENABLED(CONFIG_IPV6)
1195 else if (m_neigh->family == AF_INET6)
423c9db2 1196 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1197#endif
1198 else
1199 return;
1200
1201 list_for_each_entry(e, &nhe->encap_list, encap_list) {
79baaec7 1202 struct encap_flow_item *efi;
f6dfb4c3
HHZ		 1203 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1204 continue;
79baaec7
EB		 1205 list_for_each_entry(efi, &e->flows, list) {
1206 flow = container_of(efi, struct mlx5e_tc_flow,
1207 encaps[efi->index]);
f6dfb4c3 1208 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1209 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1210 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1211 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1212 neigh_used = true;
1213 break;
1214 }
1215 }
1216 }
e36d4810
RD		 1217 if (neigh_used)
1218 break;
f6dfb4c3
HHZ		 1219 }
1220
1221 if (neigh_used) {
1222 nhe->reported_lastuse = jiffies;
1223
1224 /* find the relevant neigh according to the cached device and
1225 * dst ip pair
1226 */
1227 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1228 if (!n)
f6dfb4c3 1229 return;
f6dfb4c3
HHZ		 1230
1231 neigh_event_send(n, NULL);
1232 neigh_release(n);
1233 }
1234}
1235
d85cdccb 1236static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1237 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1238{
8c4dc42b 1239 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1240
8c4dc42b 1241 list_del(&flow->encaps[out_index].list);
5067b602 1242 if (list_empty(next)) {
c1ae1152 1243 struct mlx5e_encap_entry *e;
5067b602 1244
c1ae1152 1245 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1246 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1247
1248 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1249 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1250
cdc5a7f3 1251 hash_del_rcu(&e->encap_hlist);
232c0013 1252 kfree(e->encap_header);
5067b602
RD		 1253 kfree(e);
1254 }
1255}
1256
04de7dda
RD		 1257static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1258{
1259 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1260
1261 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1262 !(flow->flags & MLX5E_TC_FLOW_DUP))
1263 return;
1264
1265 mutex_lock(&esw->offloads.peer_mutex);
1266 list_del(&flow->peer);
1267 mutex_unlock(&esw->offloads.peer_mutex);
1268
1269 flow->flags &= ~MLX5E_TC_FLOW_DUP;
1270
1271 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1272 kvfree(flow->peer_flow);
1273 flow->peer_flow = NULL;
1274}
1275
1276static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1277{
1278 struct mlx5_core_dev *dev = flow->priv->mdev;
1279 struct mlx5_devcom *devcom = dev->priv.devcom;
1280 struct mlx5_eswitch *peer_esw;
1281
1282 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1283 if (!peer_esw)
1284 return;
1285
1286 __mlx5e_tc_del_fdb_peer_flow(flow);
1287 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1288}
1289
e8f887ac 1290static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1291 struct mlx5e_tc_flow *flow)
e8f887ac 1292{
04de7dda
RD		 1293 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1294 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1295 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1296 } else {
d85cdccb 1297 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1298 }
e8f887ac
AV		 1299}
1300
bbd00f7e
HHZ		 1301
1302static int parse_tunnel_attr(struct mlx5e_priv *priv,
1303 struct mlx5_flow_spec *spec,
54c177ca 1304 struct tc_cls_flower_offload *f,
6363651d 1305 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1306{
e98bedf5 1307 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1308 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1309 outer_headers);
1310 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1311 outer_headers);
8f256622
PNA		 1312 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1313 struct flow_match_control enc_control;
1314 int err;
2e72eb43 1315
101f4de9 1316 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1317 headers_c, headers_v, match_level);
54c177ca
OS		 1318 if (err) {
1319 NL_SET_ERR_MSG_MOD(extack,
1320 "failed to parse tunnel attributes");
101f4de9 1321 return err;
bbd00f7e
HHZ		 1322 }
1323
8f256622
PNA		 1324 flow_rule_match_enc_control(rule, &enc_control);
1325
1326 if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1327 struct flow_match_ipv4_addrs match;
1328
1329 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1330 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1331 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1332 ntohl(match.mask->src));
bbd00f7e
HHZ		 1333 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1334 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1335 ntohl(match.key->src));
bbd00f7e
HHZ		 1336
1337 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1338 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1339 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1340 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1341 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1342 ntohl(match.key->dst));
bbd00f7e 1343
2e72eb43
OG		 1344 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
8f256622
PNA		 1346 } else if (enc_control.key->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1347 struct flow_match_ipv6_addrs match;
19f44401 1348
8f256622 1349 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1350 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1351 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1352 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1353 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1354 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1355 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1356
1357 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1358 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1359 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1360 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1361 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1362 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1363
1364 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1365 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1366 }
bbd00f7e 1367
8f256622
PNA		 1368 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1369 struct flow_match_ip match;
bcef735c 1370
8f256622
PNA		 1371 flow_rule_match_enc_ip(rule, &match);
1372 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1373 match.mask->tos & 0x3);
1374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1375 match.key->tos & 0x3);
bcef735c 1376
8f256622
PNA		 1377 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1378 match.mask->tos >> 2);
1379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1380 match.key->tos >> 2);
bcef735c 1381
8f256622
PNA		 1382 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1383 match.mask->ttl);
1384 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1385 match.key->ttl);
e98bedf5 1386
8f256622 1387 if (match.mask->ttl &&
e98bedf5
EB		 1388 !MLX5_CAP_ESW_FLOWTABLE_FDB
1389 (priv->mdev,
1390 ft_field_support.outer_ipv4_ttl)) {
1391 NL_SET_ERR_MSG_MOD(extack,
1392 "Matching on TTL is not supported");
1393 return -EOPNOTSUPP;
1394 }
1395
bcef735c
OG		 1396 }
1397
bbd00f7e
HHZ		 1398 /* Enforce DMAC when offloading incoming tunneled flows.
1399 * Flow counters require a match on the DMAC.
1400 */
1401 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1402 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1403 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1404 dmac_47_16), priv->netdev->dev_addr);
1405
1406 /* let software handle IP fragments */
1407 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1408 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1409
1410 return 0;
1411}
1412
de0af0bf
RD		 1413static int __parse_cls_flower(struct mlx5e_priv *priv,
1414 struct mlx5_flow_spec *spec,
1415 struct tc_cls_flower_offload *f,
54c177ca 1416 struct net_device *filter_dev,
6363651d 1417 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1418{
e98bedf5 1419 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1420 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1421 outer_headers);
1422 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1423 outer_headers);
699e96dd
JL		 1424 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1425 misc_parameters);
1426 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1427 misc_parameters);
8f256622
PNA		 1428 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1429 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1430 u16 addr_type = 0;
1431 u8 ip_proto = 0;
1432
d708f902 1433 *match_level = MLX5_MATCH_NONE;
de0af0bf 1434
8f256622 1435 if (dissector->used_keys &
e3a2b7ed
AV		 1436 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1437 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1438 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1439 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1440 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1441 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1442 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1443 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1444 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1445 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1446 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1447 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1448 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1449 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1450 BIT(FLOW_DISSECTOR_KEY_IP) |
1451 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1452 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1453 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1454 dissector->used_keys);
e3a2b7ed
AV		 1455 return -EOPNOTSUPP;
1456 }
1457
8f256622
PNA		 1458 if ((flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1459 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1460 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1461 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1462 struct flow_match_control match;
1463
1464 flow_rule_match_enc_control(rule, &match);
1465 switch (match.key->addr_type) {
bbd00f7e 1466 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1467 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
6363651d 1468 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e
HHZ		 1469 return -EOPNOTSUPP;
1470 break;
1471 default:
1472 return -EOPNOTSUPP;
1473 }
1474
1475 /* In decap flow, header pointers should point to the inner
1476 * headers, outer header were already set by parse_tunnel_attr
1477 */
1478 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1479 inner_headers);
1480 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1481 inner_headers);
1482 }
1483
8f256622
PNA		 1484 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1485 struct flow_match_basic match;
1486
1487 flow_rule_match_basic(rule, &match);
d3a80bb5 1488 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1489 ntohs(match.mask->n_proto));
d3a80bb5 1490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1491 ntohs(match.key->n_proto));
e3a2b7ed 1492
8f256622 1493 if (match.mask->n_proto)
d708f902 1494 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1495 }
1496
8f256622
PNA		 1497 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1498 struct flow_match_vlan match;
1499
1500 flow_rule_match_vlan(rule, &match);
1501 if (match.mask->vlan_id ||
1502 match.mask->vlan_priority ||
1503 match.mask->vlan_tpid) {
1504 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1505 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1506 svlan_tag, 1);
1507 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1508 svlan_tag, 1);
1509 } else {
1510 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1511 cvlan_tag, 1);
1512 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1513 cvlan_tag, 1);
1514 }
095b6cfd 1515
8f256622
PNA		 1516 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1517 match.mask->vlan_id);
1518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1519 match.key->vlan_id);
358d79a4 1520
8f256622
PNA		 1521 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1522 match.mask->vlan_priority);
1523 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1524 match.key->vlan_priority);
54782900 1525
d708f902 1526 *match_level = MLX5_MATCH_L2;
54782900 1527 }
d3a80bb5 1528 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1529 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1530 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1531 *match_level = MLX5_MATCH_L2;
54782900
OG		 1532 }
1533
8f256622
PNA		 1534 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1535 struct flow_match_vlan match;
1536
1537 flow_rule_match_vlan(rule, &match);
1538 if (match.mask->vlan_id ||
1539 match.mask->vlan_priority ||
1540 match.mask->vlan_tpid) {
1541 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1542 MLX5_SET(fte_match_set_misc, misc_c,
1543 outer_second_svlan_tag, 1);
1544 MLX5_SET(fte_match_set_misc, misc_v,
1545 outer_second_svlan_tag, 1);
1546 } else {
1547 MLX5_SET(fte_match_set_misc, misc_c,
1548 outer_second_cvlan_tag, 1);
1549 MLX5_SET(fte_match_set_misc, misc_v,
1550 outer_second_cvlan_tag, 1);
1551 }
1552
1553 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1554 match.mask->vlan_id);
699e96dd 1555 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1556 match.key->vlan_id);
699e96dd 1557 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1558 match.mask->vlan_priority);
699e96dd 1559 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1560 match.key->vlan_priority);
699e96dd
JL		 1561
1562 *match_level = MLX5_MATCH_L2;
1563 }
1564 }
1565
8f256622
PNA		 1566 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1567 struct flow_match_eth_addrs match;
54782900 1568
8f256622 1569 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1570 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1571 dmac_47_16),
8f256622 1572 match.mask->dst);
d3a80bb5
OG		 1573 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1574 dmac_47_16),
8f256622 1575 match.key->dst);
d3a80bb5
OG		 1576
1577 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1578 smac_47_16),
8f256622 1579 match.mask->src);
d3a80bb5
OG		 1580 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1581 smac_47_16),
8f256622 1582 match.key->src);
d3a80bb5 1583
8f256622
PNA		 1584 if (!is_zero_ether_addr(match.mask->src) ||
1585 !is_zero_ether_addr(match.mask->dst))
d708f902 1586 *match_level = MLX5_MATCH_L2;
54782900
OG		 1587 }
1588
8f256622
PNA		 1589 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1590 struct flow_match_control match;
54782900 1591
8f256622
PNA		 1592 flow_rule_match_control(rule, &match);
1593 addr_type = match.key->addr_type;
54782900
OG		 1594
1595 /* the HW doesn't support frag first/later */
8f256622 1596 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1597 return -EOPNOTSUPP;
1598
8f256622 1599 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1600 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1601 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1602 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1603
1604 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1605 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1606 *match_level = MLX5_MATCH_L2;
54782900
OG		 1607 /* *** L2 attributes parsing up to here *** */
1608 else
83621b7d 1609 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1610 }
1611 }
1612
8f256622
PNA		 1613 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1614 struct flow_match_basic match;
1615
1616 flow_rule_match_basic(rule, &match);
1617 ip_proto = match.key->ip_proto;
54782900
OG		 1618
1619 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1620 match.mask->ip_proto);
54782900 1621 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1622 match.key->ip_proto);
54782900 1623
8f256622 1624 if (match.mask->ip_proto)
d708f902 1625 *match_level = MLX5_MATCH_L3;
54782900
OG		 1626 }
1627
e3a2b7ed 1628 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1629 struct flow_match_ipv4_addrs match;
e3a2b7ed 1630
8f256622 1631 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1632 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1633 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1634 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1635 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1636 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1637 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1638 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1639 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1640 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1641 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1642 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1643 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1644
8f256622 1645 if (match.mask->src || match.mask->dst)
d708f902 1646 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1647 }
1648
1649 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1650 struct flow_match_ipv6_addrs match;
e3a2b7ed 1651
8f256622 1652 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1654 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1655 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1656 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1657 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1658 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1659
1660 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1661 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1662 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1663 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1664 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1665 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1666
8f256622
PNA		 1667 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1668 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1669 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1670 }
1671
8f256622
PNA		 1672 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1673 struct flow_match_ip match;
1f97a526 1674
8f256622
PNA		 1675 flow_rule_match_ip(rule, &match);
1676 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1677 match.mask->tos & 0x3);
1678 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1679 match.key->tos & 0x3);
1f97a526 1680
8f256622
PNA		 1681 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1682 match.mask->tos >> 2);
1683 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1684 match.key->tos >> 2);
1f97a526 1685
8f256622
PNA		 1686 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1687 match.mask->ttl);
1688 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1689 match.key->ttl);
1f97a526 1690
8f256622 1691 if (match.mask->ttl &&
a8ade55f 1692 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1693 ft_field_support.outer_ipv4_ttl)) {
1694 NL_SET_ERR_MSG_MOD(extack,
1695 "Matching on TTL is not supported");
1f97a526 1696 return -EOPNOTSUPP;
e98bedf5 1697 }
a8ade55f 1698
8f256622 1699 if (match.mask->tos || match.mask->ttl)
d708f902 1700 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1701 }
1702
54782900
OG		 1703 /* *** L3 attributes parsing up to here *** */
1704
8f256622
PNA		 1705 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1706 struct flow_match_ports match;
1707
1708 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1709 switch (ip_proto) {
1710 case IPPROTO_TCP:
1711 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1712 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1713 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1714 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1715
1716 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1717 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1718 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1719 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1720 break;
1721
1722 case IPPROTO_UDP:
1723 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1724 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1725 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1726 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1727
1728 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1729 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1730 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1731 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1732 break;
1733 default:
e98bedf5
EB		 1734 NL_SET_ERR_MSG_MOD(extack,
1735 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1736 netdev_err(priv->netdev,
1737 "Only UDP and TCP transport are supported\n");
1738 return -EINVAL;
1739 }
de0af0bf 1740
8f256622 1741 if (match.mask->src || match.mask->dst)
d708f902 1742 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1743 }
1744
8f256622
PNA		 1745 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1746 struct flow_match_tcp match;
e77834ec 1747
8f256622 1748 flow_rule_match_tcp(rule, &match);
e77834ec 1749 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1750 ntohs(match.mask->flags));
e77834ec 1751 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1752 ntohs(match.key->flags));
e77834ec 1753
8f256622 1754 if (match.mask->flags)
d708f902 1755 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1756 }
1757
e3a2b7ed
AV		 1758 return 0;
1759}
1760
de0af0bf 1761static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1762 struct mlx5e_tc_flow *flow,
de0af0bf 1763 struct mlx5_flow_spec *spec,
54c177ca
OS		 1764 struct tc_cls_flower_offload *f,
1765 struct net_device *filter_dev)
de0af0bf 1766{
e98bedf5 1767 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1768 struct mlx5_core_dev *dev = priv->mdev;
1769 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1770 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1771 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1772 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1773 int err;
1774
6363651d 1775 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 1776
1d447a39
SM		 1777 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1778 rep = rpriv->rep;
b05af6aa 1779 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 1780 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1781 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1782 NL_SET_ERR_MSG_MOD(extack,
1783 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1784 netdev_warn(priv->netdev,
1785 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1786 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1787 return -EOPNOTSUPP;
1788 }
1789 }
1790
6363651d 1791 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
38aa51c1 1792 flow->esw_attr->match_level = match_level;
6363651d
OG		 1793 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1794 } else {
38aa51c1 1795 flow->nic_attr->match_level = match_level;
6363651d 1796 }
38aa51c1 1797
de0af0bf
RD		 1798 return err;
1799}
1800
d79b6df6
OG		 1801struct pedit_headers {
1802 struct ethhdr eth;
1803 struct iphdr ip4;
1804 struct ipv6hdr ip6;
1805 struct tcphdr tcp;
1806 struct udphdr udp;
1807};
1808
c500c86b
PNA		 1809struct pedit_headers_action {
1810 struct pedit_headers vals;
1811 struct pedit_headers masks;
1812 u32 pedits;
1813};
1814
d79b6df6 1815static int pedit_header_offsets[] = {
73867881
PNA		 1816 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1817 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1818 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1819 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1820 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 1821};
1822
1823#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1824
1825static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 1826 struct pedit_headers_action *hdrs)
d79b6df6
OG		 1827{
1828 u32 *curr_pmask, *curr_pval;
1829
c500c86b
PNA		 1830 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
1831 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 1832
1833 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1834 goto out_err;
1835
1836 *curr_pmask |= mask;
1837 *curr_pval |= (val & mask);
1838
1839 return 0;
1840
1841out_err:
1842 return -EOPNOTSUPP;
1843}
1844
1845struct mlx5_fields {
1846 u8 field;
1847 u8 size;
1848 u32 offset;
1849};
1850
a8e4f0c4
OG		 1851#define OFFLOAD(fw_field, size, field, off) \
1852 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1853
d79b6df6 1854static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1855 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1856 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1857 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1858 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1859 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1860
1861 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1862 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1863 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1864
1865 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1866 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1867 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1868 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1869 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1870 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1871 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1872 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1873 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1874
1875 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1876 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1877 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1878
1879 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1880 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1881};
1882
218d05ce
TZ		 1883/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
1884 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
1885 * says how many HW actions were actually parsed.
d79b6df6 1886 */
c500c86b 1887static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5
EB		 1888 struct mlx5e_tc_flow_parse_attr *parse_attr,
1889 struct netlink_ext_ack *extack)
d79b6df6
OG		 1890{
1891 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1892 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1893 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1894 struct mlx5_fields *f;
1895 u8 cmd, field_bsize;
e3ca4e05 1896 u32 s_mask, a_mask;
d79b6df6 1897 unsigned long mask;
2b64beba
OG		 1898 __be32 mask_be32;
1899 __be16 mask_be16;
d79b6df6
OG		 1900 void *action;
1901
73867881
PNA		 1902 set_masks = &hdrs[0].masks;
1903 add_masks = &hdrs[1].masks;
1904 set_vals = &hdrs[0].vals;
1905 add_vals = &hdrs[1].vals;
d79b6df6
OG		 1906
1907 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 1908 action = parse_attr->mod_hdr_actions +
1909 parse_attr->num_mod_hdr_actions * action_size;
1910
1911 max_actions = parse_attr->max_mod_hdr_actions;
1912 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 1913
1914 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1915 f = &fields[i];
1916 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1917 s_mask = 0;
1918 a_mask = 0;
d79b6df6
OG		 1919
1920 s_masks_p = (void *)set_masks + f->offset;
1921 a_masks_p = (void *)add_masks + f->offset;
1922
1923 memcpy(&s_mask, s_masks_p, f->size);
1924 memcpy(&a_mask, a_masks_p, f->size);
1925
1926 if (!s_mask && !a_mask) /* nothing to offload here */
1927 continue;
1928
1929 if (s_mask && a_mask) {
e98bedf5
EB		 1930 NL_SET_ERR_MSG_MOD(extack,
1931 "can't set and add to the same HW field");
d79b6df6
OG		 1932 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1933 return -EOPNOTSUPP;
1934 }
1935
1936 if (nactions == max_actions) {
e98bedf5
EB		 1937 NL_SET_ERR_MSG_MOD(extack,
1938 "too many pedit actions, can't offload");
d79b6df6
OG		 1939 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1940 return -EOPNOTSUPP;
1941 }
1942
1943 if (s_mask) {
1944 cmd = MLX5_ACTION_TYPE_SET;
1945 mask = s_mask;
1946 vals_p = (void *)set_vals + f->offset;
1947 /* clear to denote we consumed this field */
1948 memset(s_masks_p, 0, f->size);
1949 } else {
1950 cmd = MLX5_ACTION_TYPE_ADD;
1951 mask = a_mask;
1952 vals_p = (void *)add_vals + f->offset;
1953 /* clear to denote we consumed this field */
1954 memset(a_masks_p, 0, f->size);
1955 }
1956
d79b6df6 1957 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1958
2b64beba
OG		 1959 if (field_bsize == 32) {
1960 mask_be32 = *(__be32 *)&mask;
1961 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1962 } else if (field_bsize == 16) {
1963 mask_be16 = *(__be16 *)&mask;
1964 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1965 }
1966
d79b6df6 1967 first = find_first_bit(&mask, field_bsize);
2b64beba 1968 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1969 last = find_last_bit(&mask, field_bsize);
2b64beba 1970 if (first < next_z && next_z < last) {
e98bedf5
EB		 1971 NL_SET_ERR_MSG_MOD(extack,
1972 "rewrite of few sub-fields isn't supported");
2b64beba 1973 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1974 mask);
1975 return -EOPNOTSUPP;
1976 }
1977
1978 MLX5_SET(set_action_in, action, action_type, cmd);
1979 MLX5_SET(set_action_in, action, field, f->field);
1980
1981 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1982 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1983 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1984 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1985 }
1986
1987 if (field_bsize == 32)
2b64beba 1988 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1989 else if (field_bsize == 16)
2b64beba 1990 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1991 else if (field_bsize == 8)
2b64beba 1992 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1993
1994 action += action_size;
1995 nactions++;
1996 }
1997
1998 parse_attr->num_mod_hdr_actions = nactions;
1999 return 0;
2000}
2001
2002static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2003 struct pedit_headers_action *hdrs,
2004 int namespace,
d79b6df6
OG		 2005 struct mlx5e_tc_flow_parse_attr *parse_attr)
2006{
2007 int nkeys, action_size, max_actions;
2008
c500c86b
PNA		 2009 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2010 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2011 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2012
2013 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2014 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2015 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2016 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2017
2018 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2019 max_actions = min(max_actions, nkeys * 16);
2020
2021 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2022 if (!parse_attr->mod_hdr_actions)
2023 return -ENOMEM;
2024
218d05ce 2025 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2026 return 0;
2027}
2028
2029static const struct pedit_headers zero_masks = {};
2030
2031static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2032 const struct flow_action_entry *act, int namespace,
e98bedf5 2033 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2034 struct pedit_headers_action *hdrs,
e98bedf5 2035 struct netlink_ext_ack *extack)
d79b6df6 2036{
73867881
PNA		 2037 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2038 int err = -EOPNOTSUPP;
d79b6df6 2039 u32 mask, val, offset;
73867881 2040 u8 htype;
d79b6df6 2041
73867881
PNA		 2042 htype = act->mangle.htype;
2043 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2044
73867881
PNA		 2045 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2046 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2047 goto out_err;
2048 }
d79b6df6 2049
73867881
PNA		 2050 mask = act->mangle.mask;
2051 val = act->mangle.val;
2052 offset = act->mangle.offset;
d79b6df6 2053
73867881
PNA		 2054 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2055 if (err)
2056 goto out_err;
c500c86b 2057
73867881 2058 hdrs[cmd].pedits++;
d79b6df6 2059
c500c86b
PNA		 2060 return 0;
2061out_err:
2062 return err;
2063}
2064
2065static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2066 struct mlx5e_tc_flow_parse_attr *parse_attr,
2067 struct pedit_headers_action *hdrs,
2068 struct netlink_ext_ack *extack)
2069{
2070 struct pedit_headers *cmd_masks;
2071 int err;
2072 u8 cmd;
2073
218d05ce 2074 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2075 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2076 if (err)
2077 goto out_err;
2078 }
d79b6df6 2079
c500c86b 2080 err = offload_pedit_fields(hdrs, parse_attr, extack);
d79b6df6
OG		 2081 if (err < 0)
2082 goto out_dealloc_parsed_actions;
2083
2084 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2085 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2086 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2087 NL_SET_ERR_MSG_MOD(extack,
2088 "attempt to offload an unsupported field");
b3a433de 2089 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2090 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2091 16, 1, cmd_masks, sizeof(zero_masks), true);
2092 err = -EOPNOTSUPP;
2093 goto out_dealloc_parsed_actions;
2094 }
2095 }
2096
2097 return 0;
2098
2099out_dealloc_parsed_actions:
2100 kfree(parse_attr->mod_hdr_actions);
2101out_err:
2102 return err;
2103}
2104
e98bedf5
EB		 2105static bool csum_offload_supported(struct mlx5e_priv *priv,
2106 u32 action,
2107 u32 update_flags,
2108 struct netlink_ext_ack *extack)
26c02749
OG		 2109{
2110 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2111 TCA_CSUM_UPDATE_FLAG_UDP;
2112
2113 /* The HW recalcs checksums only if re-writing headers */
2114 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2115 NL_SET_ERR_MSG_MOD(extack,
2116 "TC csum action is only offloaded with pedit");
26c02749
OG		 2117 netdev_warn(priv->netdev,
2118 "TC csum action is only offloaded with pedit\n");
2119 return false;
2120 }
2121
2122 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2123 NL_SET_ERR_MSG_MOD(extack,
2124 "can't offload TC csum action for some header/s");
26c02749
OG		 2125 netdev_warn(priv->netdev,
2126 "can't offload TC csum action for some header/s - flags %#x\n",
2127 update_flags);
2128 return false;
2129 }
2130
2131 return true;
2132}
2133
bdd66ac0 2134static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2135 struct flow_action *flow_action,
1651925d 2136 u32 actions,
e98bedf5 2137 struct netlink_ext_ack *extack)
bdd66ac0 2138{
73867881 2139 const struct flow_action_entry *act;
bdd66ac0 2140 bool modify_ip_header;
bdd66ac0
OG		 2141 u8 htype, ip_proto;
2142 void *headers_v;
2143 u16 ethertype;
73867881 2144 int i;
bdd66ac0 2145
1651925d
GS		 2146 if (actions & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2147 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2148 else
2149 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2150
bdd66ac0
OG		 2151 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2152
2153 /* for non-IP we only re-write MACs, so we're okay */
2154 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2155 goto out_ok;
2156
2157 modify_ip_header = false;
73867881
PNA		 2158 flow_action_for_each(i, act, flow_action) {
2159 if (act->id != FLOW_ACTION_MANGLE &&
2160 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2161 continue;
2162
73867881
PNA		 2163 htype = act->mangle.htype;
2164 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4 ||
2165 htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2166 modify_ip_header = true;
2167 break;
bdd66ac0
OG		 2168 }
2169 }
2170
2171 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2172 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2173 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2174 NL_SET_ERR_MSG_MOD(extack,
2175 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2176 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2177 return false;
2178 }
2179
2180out_ok:
2181 return true;
2182}
2183
2184static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2185 struct flow_action *flow_action,
bdd66ac0 2186 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2187 struct mlx5e_tc_flow *flow,
2188 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2189{
2190 u32 actions;
2191
2192 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2193 actions = flow->esw_attr->action;
2194 else
2195 actions = flow->nic_attr->action;
2196
7e29392e
RD		 2197 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2198 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2199 return false;
2200
bdd66ac0 2201 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2202 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2203 flow_action, actions,
e98bedf5 2204 extack);
bdd66ac0
OG		 2205
2206 return true;
2207}
2208
5c65c564
OG		 2209static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2210{
2211 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2212 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2213
2214 fmdev = priv->mdev;
2215 pmdev = peer_priv->mdev;
2216
59c9d35e
AH		 2217 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2218 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2219
816f6706 2220 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2221}
2222
73867881
PNA		 2223static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2224 struct flow_action *flow_action,
aa0cbbae 2225 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2226 struct mlx5e_tc_flow *flow,
2227 struct netlink_ext_ack *extack)
e3a2b7ed 2228{
aa0cbbae 2229 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2230 struct pedit_headers_action hdrs[2] = {};
2231 const struct flow_action_entry *act;
1cab1cd7 2232 u32 action = 0;
244cd96a 2233 int err, i;
e3a2b7ed 2234
73867881 2235 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2236 return -EINVAL;
2237
3bc4b7bf 2238 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2239
73867881
PNA		 2240 flow_action_for_each(i, act, flow_action) {
2241 switch (act->id) {
2242 case FLOW_ACTION_DROP:
1cab1cd7 2243 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2244 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2245 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2246 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2247 break;
2248 case FLOW_ACTION_MANGLE:
2249 case FLOW_ACTION_ADD:
2250 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2251 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2252 if (err)
2253 return err;
2254
1cab1cd7
OG		 2255 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2256 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2257 break;
2258 case FLOW_ACTION_CSUM:
1cab1cd7 2259 if (csum_offload_supported(priv, action,
73867881 2260 act->csum_flags,
e98bedf5 2261 extack))
73867881 2262 break;
26c02749
OG		 2263
2264 return -EOPNOTSUPP;
73867881
PNA		 2265 case FLOW_ACTION_REDIRECT: {
2266 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2267
2268 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2269 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2270 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
5c65c564 2271 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2272 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2273 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2274 } else {
e98bedf5
EB		 2275 NL_SET_ERR_MSG_MOD(extack,
2276 "device is not on same HW, can't offload");
5c65c564
OG		 2277 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2278 peer_dev->name);
2279 return -EINVAL;
2280 }
73867881
PNA		 2281 }
2282 break;
2283 case FLOW_ACTION_MARK: {
2284 u32 mark = act->mark;
e3a2b7ed
AV		 2285
2286 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2287 NL_SET_ERR_MSG_MOD(extack,
2288 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2289 return -EINVAL;
2290 }
2291
3bc4b7bf 2292 attr->flow_tag = mark;
1cab1cd7 2293 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2294 }
2295 break;
2296 default:
2297 return -EINVAL;
e3a2b7ed 2298 }
e3a2b7ed
AV		 2299 }
2300
c500c86b
PNA		 2301 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2302 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2303 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2304 parse_attr, hdrs, extack);
2305 if (err)
2306 return err;
2307 }
2308
1cab1cd7 2309 attr->action = action;
73867881 2310 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2311 return -EOPNOTSUPP;
2312
e3a2b7ed
AV		 2313 return 0;
2314}
2315
76f7444d
OG		 2316static inline int cmp_encap_info(struct ip_tunnel_key *a,
2317 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2318{
2319 return memcmp(a, b, sizeof(*a));
2320}
2321
76f7444d 2322static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2323{
76f7444d 2324 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2325}
2326
a54e20b4 2327
b1d90e6b
RL		 2328static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2329 struct net_device *peer_netdev)
2330{
2331 struct mlx5e_priv *peer_priv;
2332
2333 peer_priv = netdev_priv(peer_netdev);
2334
2335 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2336 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2337 same_hw_devs(priv, peer_priv) &&
2338 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2339 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2340}
2341
32f3671f 2342
f5bc2c5d 2343
a54e20b4
HHZ		 2344static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2345 struct ip_tunnel_info *tun_info,
2346 struct net_device *mirred_dev,
45247bf2 2347 struct net_device **encap_dev,
e98bedf5 2348 struct mlx5e_tc_flow *flow,
8c4dc42b
EB		 2349 struct netlink_ext_ack *extack,
2350 int out_index)
a54e20b4
HHZ		 2351{
2352 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2353 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2354 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2355 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2356 struct mlx5e_encap_entry *e;
a54e20b4
HHZ		 2357 uintptr_t hash_key;
2358 bool found = false;
54c177ca 2359 int err = 0;
a54e20b4 2360
76f7444d 2361 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2362
2363 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2364 encap_hlist, hash_key) {
76f7444d 2365 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2366 found = true;
2367 break;
2368 }
2369 }
2370
b2812089 2371 /* must verify if encap is valid or not */
45247bf2
OG		 2372 if (found)
2373 goto attach_flow;
a54e20b4
HHZ		 2374
2375 e = kzalloc(sizeof(*e), GFP_KERNEL);
2376 if (!e)
2377 return -ENOMEM;
2378
76f7444d 2379 e->tun_info = *tun_info;
101f4de9 2380 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2381 if (err)
2382 goto out_err;
2383
a54e20b4
HHZ		 2384 INIT_LIST_HEAD(&e->flows);
2385
ce99f6b9 2386 if (family == AF_INET)
101f4de9 2387 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2388 else if (family == AF_INET6)
101f4de9 2389 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2390
232c0013 2391 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2392 goto out_err;
2393
a54e20b4
HHZ		 2394 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2395
45247bf2 2396attach_flow:
8c4dc42b
EB		 2397 list_add(&flow->encaps[out_index].list, &e->flows);
2398 flow->encaps[out_index].index = out_index;
45247bf2 2399 *encap_dev = e->out_dev;
8c4dc42b
EB		 2400 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2401 attr->dests[out_index].encap_id = e->encap_id;
2402 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
2403 } else {
b2812089 2404 err = -EAGAIN;
8c4dc42b 2405 }
45247bf2 2406
232c0013 2407 return err;
a54e20b4
HHZ		 2408
2409out_err:
2410 kfree(e);
2411 return err;
2412}
2413
1482bd3d 2414static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2415 const struct flow_action_entry *act,
1482bd3d
JL		 2416 struct mlx5_esw_flow_attr *attr,
2417 u32 *action)
2418{
cc495188
JL		 2419 u8 vlan_idx = attr->total_vlan;
2420
2421 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2422 return -EOPNOTSUPP;
2423
73867881
PNA		 2424 switch (act->id) {
2425 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2426 if (vlan_idx) {
2427 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2428 MLX5_FS_VLAN_DEPTH))
2429 return -EOPNOTSUPP;
2430
2431 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2432 } else {
2433 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2434 }
73867881
PNA		 2435 break;
2436 case FLOW_ACTION_VLAN_PUSH:
2437 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2438 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2439 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2440 if (!attr->vlan_proto[vlan_idx])
2441 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2442
2443 if (vlan_idx) {
2444 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2445 MLX5_FS_VLAN_DEPTH))
2446 return -EOPNOTSUPP;
2447
2448 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2449 } else {
2450 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2451 (act->vlan.proto != htons(ETH_P_8021Q) ||
2452 act->vlan.prio))
cc495188
JL		 2453 return -EOPNOTSUPP;
2454
2455 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2456 }
73867881
PNA		 2457 break;
2458 default:
2459 /* action is FLOW_ACT_VLAN_MANGLE */
1482bd3d
JL		 2460 return -EOPNOTSUPP;
2461 }
2462
cc495188
JL		 2463 attr->total_vlan = vlan_idx + 1;
2464
1482bd3d
JL		 2465 return 0;
2466}
2467
73867881
PNA		 2468static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2469 struct flow_action *flow_action,
d7e75a32 2470 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2471 struct mlx5e_tc_flow *flow,
2472 struct netlink_ext_ack *extack)
03a9d11e 2473{
73867881 2474 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2475 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2476 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2477 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2478 const struct ip_tunnel_info *info = NULL;
2479 const struct flow_action_entry *act;
a54e20b4 2480 bool encap = false;
1cab1cd7 2481 u32 action = 0;
244cd96a 2482 int err, i;
03a9d11e 2483
73867881 2484 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2485 return -EINVAL;
2486
1d447a39 2487 attr->in_rep = rpriv->rep;
10ff5359 2488 attr->in_mdev = priv->mdev;
03a9d11e 2489
73867881
PNA		 2490 flow_action_for_each(i, act, flow_action) {
2491 switch (act->id) {
2492 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2493 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2494 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2495 break;
2496 case FLOW_ACTION_MANGLE:
2497 case FLOW_ACTION_ADD:
2498 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 2499 parse_attr, hdrs, extack);
d7e75a32
OG		 2500 if (err)
2501 return err;
2502
1cab1cd7 2503 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2504 attr->split_count = attr->out_count;
73867881
PNA		 2505 break;
2506 case FLOW_ACTION_CSUM:
1cab1cd7 2507 if (csum_offload_supported(priv, action,
73867881
PNA		 2508 act->csum_flags, extack))
2509 break;
26c02749
OG		 2510
2511 return -EOPNOTSUPP;
73867881
PNA		 2512 case FLOW_ACTION_REDIRECT:
2513 case FLOW_ACTION_MIRRED: {
03a9d11e 2514 struct mlx5e_priv *out_priv;
592d3651 2515 struct net_device *out_dev;
03a9d11e 2516
73867881 2517 out_dev = act->dev;
ef381359
OS		 2518 if (!out_dev) {
2519 /* out_dev is NULL when filters with
2520 * non-existing mirred device are replayed to
2521 * the driver.
2522 */
2523 return -EINVAL;
2524 }
03a9d11e 2525
592d3651 2526 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2527 NL_SET_ERR_MSG_MOD(extack,
2528 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2529 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2530 attr->out_count);
2531 return -EOPNOTSUPP;
2532 }
2533
f493f155
EB		 2534 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2535 MLX5_FLOW_CONTEXT_ACTION_COUNT;
6dcfa234
FF		 2536 if (netdev_port_same_parent_id(priv->netdev,
2537 out_dev) ||
b1d90e6b 2538 is_merged_eswitch_dev(priv, out_dev)) {
7ba58ba7
RL		 2539 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2540 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
2541 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev);
2542
2543 if (uplink_upper &&
2544 netif_is_lag_master(uplink_upper) &&
2545 uplink_upper == out_dev)
2546 out_dev = uplink_dev;
2547
a0646c88
EB		 2548 if (!mlx5e_eswitch_rep(out_dev))
2549 return -EOPNOTSUPP;
2550
a54e20b4 2551 out_priv = netdev_priv(out_dev);
1d447a39 2552 rpriv = out_priv->ppriv;
df65a573
EB		 2553 attr->dests[attr->out_count].rep = rpriv->rep;
2554 attr->dests[attr->out_count].mdev = out_priv->mdev;
2555 attr->out_count++;
a54e20b4 2556 } else if (encap) {
8c4dc42b
EB		 2557 parse_attr->mirred_ifindex[attr->out_count] =
2558 out_dev->ifindex;
2559 parse_attr->tun_info[attr->out_count] = *info;
2560 encap = false;
3c37745e 2561 attr->parse_attr = parse_attr;
f493f155
EB		 2562 attr->dests[attr->out_count].flags |=
2563 MLX5_ESW_DEST_ENCAP;
1cc26d74 2564 attr->out_count++;
df65a573
EB		 2565 /* attr->dests[].rep is resolved when we
2566 * handle encap
2567 */
ef381359
OS		 2568 } else if (parse_attr->filter_dev != priv->netdev) {
2569 /* All mlx5 devices are called to configure
2570 * high level device filters. Therefore, the
2571 * *attempt* to install a filter on invalid
2572 * eswitch should not trigger an explicit error
2573 */
2574 return -EINVAL;
a54e20b4 2575 } else {
e98bedf5
EB		 2576 NL_SET_ERR_MSG_MOD(extack,
2577 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2578 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2579 priv->netdev->name, out_dev->name);
2580 return -EINVAL;
2581 }
73867881
PNA		 2582 }
2583 break;
2584 case FLOW_ACTION_TUNNEL_ENCAP:
2585 info = act->tunnel;
a54e20b4
HHZ		 2586 if (info)
2587 encap = true;
2588 else
2589 return -EOPNOTSUPP;
1482bd3d 2590
73867881
PNA		 2591 break;
2592 case FLOW_ACTION_VLAN_PUSH:
2593 case FLOW_ACTION_VLAN_POP:
2594 err = parse_tc_vlan_action(priv, act, attr, &action);
1482bd3d
JL		 2595 if (err)
2596 return err;
2597
e85e02ba 2598 attr->split_count = attr->out_count;
73867881
PNA		 2599 break;
2600 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 2601 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 2602 break;
2603 case FLOW_ACTION_GOTO: {
2604 u32 dest_chain = act->chain_index;
bf07aa73
PB		 2605 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2606
2607 if (dest_chain <= attr->chain) {
2608 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2609 return -EOPNOTSUPP;
2610 }
2611 if (dest_chain > max_chain) {
2612 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2613 return -EOPNOTSUPP;
2614 }
e88afe75 2615 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 2616 attr->dest_chain = dest_chain;
73867881
PNA		 2617 break;
2618 }
2619 default:
2620 return -EINVAL;
bf07aa73 2621 }
03a9d11e 2622 }
bdd66ac0 2623
c500c86b
PNA		 2624 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2625 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2626 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2627 parse_attr, hdrs, extack);
2628 if (err)
2629 return err;
2630 }
2631
1cab1cd7 2632 attr->action = action;
73867881 2633 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2634 return -EOPNOTSUPP;
2635
e88afe75
OG		 2636 if (attr->dest_chain) {
2637 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2638 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
2639 return -EOPNOTSUPP;
2640 }
2641 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2642 }
2643
e85e02ba 2644 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2645 NL_SET_ERR_MSG_MOD(extack,
2646 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2647 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2648 return -EOPNOTSUPP;
2649 }
2650
31c8eba5 2651 return 0;
03a9d11e
OG		 2652}
2653
5dbe906f 2654static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2655{
5dbe906f 2656 u16 __flow_flags = 0;
60bd4af8
OG		 2657
2658 if (flags & MLX5E_TC_INGRESS)
2659 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2660 if (flags & MLX5E_TC_EGRESS)
2661 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2662
d9ee0491
OG		 2663 if (flags & MLX5E_TC_ESW_OFFLOAD)
2664 __flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2665 if (flags & MLX5E_TC_NIC_OFFLOAD)
2666 __flow_flags |= MLX5E_TC_FLOW_NIC;
2667
60bd4af8
OG		 2668 *flow_flags = __flow_flags;
2669}
2670
05866c82
OG		 2671static const struct rhashtable_params tc_ht_params = {
2672 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2673 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2674 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2675 .automatic_shrinking = true,
2676};
2677
d9ee0491 2678static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags)
05866c82 2679{
655dc3d2
OG		 2680 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2681 struct mlx5e_rep_priv *uplink_rpriv;
2682
d9ee0491 2683 if (flags & MLX5E_TC_ESW_OFFLOAD) {
655dc3d2 2684 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 2685 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 2686 } else /* NIC offload */
655dc3d2 2687 return &priv->fs.tc.ht;
05866c82
OG		 2688}
2689
04de7dda
RD		 2690static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
2691{
1418ddd9 2692 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 2693 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
1418ddd9
AH		 2694 flow->flags & MLX5E_TC_FLOW_INGRESS;
2695 bool act_is_encap = !!(attr->action &
2696 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
2697 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
2698 MLX5_DEVCOM_ESW_OFFLOADS);
2699
7c34ec19 2700 return esw_paired && mlx5_lag_is_sriov(attr->in_mdev) &&
1418ddd9 2701 (is_rep_ingress || act_is_encap);
04de7dda
RD		 2702}
2703
a88780a9
RD		 2704static int
2705mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 2706 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 2707 struct mlx5e_tc_flow_parse_attr **__parse_attr,
2708 struct mlx5e_tc_flow **__flow)
e3a2b7ed 2709{
17091853 2710 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 2711 struct mlx5e_tc_flow *flow;
a88780a9 2712 int err;
e3a2b7ed 2713
65ba8fb7 2714 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2715 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2716 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2717 err = -ENOMEM;
2718 goto err_free;
2719 }
2720
2721 flow->cookie = f->cookie;
65ba8fb7 2722 flow->flags = flow_flags;
655dc3d2 2723 flow->priv = priv;
e3a2b7ed 2724
a88780a9
RD		 2725 *__flow = flow;
2726 *__parse_attr = parse_attr;
2727
2728 return 0;
2729
2730err_free:
2731 kfree(flow);
2732 kvfree(parse_attr);
2733 return err;
2734}
2735
71129676 2736static struct mlx5e_tc_flow *
04de7dda
RD		 2737__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2738 struct tc_cls_flower_offload *f,
2739 u16 flow_flags,
2740 struct net_device *filter_dev,
2741 struct mlx5_eswitch_rep *in_rep,
71129676 2742 struct mlx5_core_dev *in_mdev)
a88780a9 2743{
73867881 2744 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9 2745 struct netlink_ext_ack *extack = f->common.extack;
f9392795 2746 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a88780a9
RD		 2747 struct mlx5e_tc_flow_parse_attr *parse_attr;
2748 struct mlx5e_tc_flow *flow;
2749 int attr_size, err;
e3a2b7ed 2750
a88780a9
RD		 2751 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2752 attr_size = sizeof(struct mlx5_esw_flow_attr);
2753 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2754 &parse_attr, &flow);
2755 if (err)
2756 goto out;
d11afc26
OS		 2757 parse_attr->filter_dev = filter_dev;
2758 flow->esw_attr->parse_attr = parse_attr;
54c177ca
OS		 2759 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2760 f, filter_dev);
d11afc26
OS		 2761 if (err)
2762 goto err_free;
a88780a9 2763
bf07aa73
PB		 2764 flow->esw_attr->chain = f->common.chain_index;
2765 flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
73867881 2766 err = parse_tc_fdb_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 2767 if (err)
2768 goto err_free;
2769
04de7dda
RD		 2770 flow->esw_attr->in_rep = in_rep;
2771 flow->esw_attr->in_mdev = in_mdev;
f9392795
SK		 2772
2773 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
2774 MLX5_COUNTER_SOURCE_ESWITCH)
2775 flow->esw_attr->counter_dev = in_mdev;
2776 else
2777 flow->esw_attr->counter_dev = priv->mdev;
2778
a88780a9 2779 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
5dbe906f 2780 if (err)
c83954ab 2781 goto err_free;
e3a2b7ed 2782
71129676 2783 return flow;
a88780a9
RD		 2784
2785err_free:
2786 kfree(flow);
2787 kvfree(parse_attr);
2788out:
71129676 2789 return ERR_PTR(err);
a88780a9
RD		 2790}
2791
04de7dda
RD		 2792static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
2793 struct mlx5e_tc_flow *flow)
2794{
2795 struct mlx5e_priv *priv = flow->priv, *peer_priv;
2796 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
2797 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
2798 struct mlx5e_tc_flow_parse_attr *parse_attr;
2799 struct mlx5e_rep_priv *peer_urpriv;
2800 struct mlx5e_tc_flow *peer_flow;
2801 struct mlx5_core_dev *in_mdev;
2802 int err = 0;
2803
2804 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2805 if (!peer_esw)
2806 return -ENODEV;
2807
2808 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
2809 peer_priv = netdev_priv(peer_urpriv->netdev);
2810
2811 /* in_mdev is assigned of which the packet originated from.
2812 * So packets redirected to uplink use the same mdev of the
2813 * original flow and packets redirected from uplink use the
2814 * peer mdev.
2815 */
b05af6aa 2816 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 2817 in_mdev = peer_priv->mdev;
2818 else
2819 in_mdev = priv->mdev;
2820
2821 parse_attr = flow->esw_attr->parse_attr;
71129676
JG		 2822 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow->flags,
2823 parse_attr->filter_dev,
2824 flow->esw_attr->in_rep, in_mdev);
2825 if (IS_ERR(peer_flow)) {
2826 err = PTR_ERR(peer_flow);
04de7dda 2827 goto out;
71129676 2828 }
04de7dda
RD		 2829
2830 flow->peer_flow = peer_flow;
2831 flow->flags |= MLX5E_TC_FLOW_DUP;
2832 mutex_lock(&esw->offloads.peer_mutex);
2833 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
2834 mutex_unlock(&esw->offloads.peer_mutex);
2835
2836out:
2837 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2838 return err;
2839}
2840
2841static int
2842mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2843 struct tc_cls_flower_offload *f,
2844 u16 flow_flags,
2845 struct net_device *filter_dev,
2846 struct mlx5e_tc_flow **__flow)
2847{
2848 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2849 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
2850 struct mlx5_core_dev *in_mdev = priv->mdev;
2851 struct mlx5e_tc_flow *flow;
2852 int err;
2853
71129676
JG		 2854 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
2855 in_mdev);
2856 if (IS_ERR(flow))
2857 return PTR_ERR(flow);
04de7dda
RD		 2858
2859 if (is_peer_flow_needed(flow)) {
2860 err = mlx5e_tc_add_fdb_peer_flow(f, flow);
2861 if (err) {
2862 mlx5e_tc_del_fdb_flow(priv, flow);
2863 goto out;
2864 }
2865 }
2866
2867 *__flow = flow;
2868
2869 return 0;
2870
2871out:
2872 return err;
2873}
2874
a88780a9
RD		 2875static int
2876mlx5e_add_nic_flow(struct mlx5e_priv *priv,
2877 struct tc_cls_flower_offload *f,
5dbe906f 2878 u16 flow_flags,
d11afc26 2879 struct net_device *filter_dev,
a88780a9
RD		 2880 struct mlx5e_tc_flow **__flow)
2881{
73867881 2882 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 2883 struct netlink_ext_ack *extack = f->common.extack;
2884 struct mlx5e_tc_flow_parse_attr *parse_attr;
2885 struct mlx5e_tc_flow *flow;
2886 int attr_size, err;
2887
bf07aa73
PB		 2888 /* multi-chain not supported for NIC rules */
2889 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
2890 return -EOPNOTSUPP;
2891
a88780a9
RD		 2892 flow_flags |= MLX5E_TC_FLOW_NIC;
2893 attr_size = sizeof(struct mlx5_nic_flow_attr);
2894 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2895 &parse_attr, &flow);
2896 if (err)
2897 goto out;
2898
d11afc26 2899 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 2900 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2901 f, filter_dev);
d11afc26
OS		 2902 if (err)
2903 goto err_free;
2904
73867881 2905 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 2906 if (err)
2907 goto err_free;
2908
2909 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
2910 if (err)
2911 goto err_free;
2912
2913 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2914 kvfree(parse_attr);
2915 *__flow = flow;
2916
2917 return 0;
e3a2b7ed 2918
e3a2b7ed 2919err_free:
a88780a9 2920 kfree(flow);
17091853 2921 kvfree(parse_attr);
a88780a9
RD		 2922out:
2923 return err;
2924}
2925
2926static int
2927mlx5e_tc_add_flow(struct mlx5e_priv *priv,
2928 struct tc_cls_flower_offload *f,
2929 int flags,
d11afc26 2930 struct net_device *filter_dev,
a88780a9
RD		 2931 struct mlx5e_tc_flow **flow)
2932{
2933 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 2934 u16 flow_flags;
a88780a9
RD		 2935 int err;
2936
2937 get_flags(flags, &flow_flags);
2938
bf07aa73
PB		 2939 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
2940 return -EOPNOTSUPP;
2941
a88780a9 2942 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 2943 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
2944 filter_dev, flow);
a88780a9 2945 else
d11afc26
OS		 2946 err = mlx5e_add_nic_flow(priv, f, flow_flags,
2947 filter_dev, flow);
a88780a9
RD		 2948
2949 return err;
2950}
2951
71d82d2a 2952int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 2953 struct tc_cls_flower_offload *f, int flags)
2954{
2955 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 2956 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 2957 struct mlx5e_tc_flow *flow;
2958 int err = 0;
2959
2960 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2961 if (flow) {
2962 NL_SET_ERR_MSG_MOD(extack,
2963 "flow cookie already exists, ignoring");
2964 netdev_warn_once(priv->netdev,
2965 "flow cookie %lx already exists, ignoring\n",
2966 f->cookie);
2967 goto out;
2968 }
2969
d11afc26 2970 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 2971 if (err)
2972 goto out;
2973
2974 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
2975 if (err)
2976 goto err_free;
2977
2978 return 0;
2979
2980err_free:
2981 mlx5e_tc_del_flow(priv, flow);
232c0013 2982 kfree(flow);
a88780a9 2983out:
e3a2b7ed
AV		 2984 return err;
2985}
2986
8f8ae895
OG		 2987#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2988#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2989
2990static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2991{
2992 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2993 return true;
2994
2995 return false;
2996}
2997
71d82d2a 2998int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 2999 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3000{
d9ee0491 3001 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3002 struct mlx5e_tc_flow *flow;
e3a2b7ed 3003
05866c82 3004 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3005 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3006 return -EINVAL;
3007
05866c82 3008 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3009
961e8979 3010 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3011
3012 kfree(flow);
3013
3014 return 0;
3015}
3016
71d82d2a 3017int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3018 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3019{
04de7dda 3020 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3021 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3022 struct mlx5_eswitch *peer_esw;
aad7e08d 3023 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 3024 struct mlx5_fc *counter;
3025 u64 bytes;
3026 u64 packets;
3027 u64 lastuse;
3028
05866c82 3029 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3030 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3031 return -EINVAL;
3032
0b67a38f
HHZ		 3033 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3034 return 0;
3035
b8aee822 3036 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 3037 if (!counter)
3038 return 0;
3039
3040 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3041
04de7dda
RD		 3042 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3043 if (!peer_esw)
3044 goto out;
3045
3046 if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3047 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3048 u64 bytes2;
3049 u64 packets2;
3050 u64 lastuse2;
3051
3052 counter = mlx5e_tc_get_counter(flow->peer_flow);
3053 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3054
3055 bytes += bytes2;
3056 packets += packets2;
3057 lastuse = max_t(u64, lastuse, lastuse2);
3058 }
3059
3060 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3061
3062out:
3b1903ef 3063 flow_stats_update(&f->stats, bytes, packets, lastuse);
fed06ee8 3064
aad7e08d
AV		 3065 return 0;
3066}
3067
4d8fcf21
AH		 3068static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3069 struct mlx5e_priv *peer_priv)
3070{
3071 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3072 struct mlx5e_hairpin_entry *hpe;
3073 u16 peer_vhca_id;
3074 int bkt;
3075
3076 if (!same_hw_devs(priv, peer_priv))
3077 return;
3078
3079 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3080
3081 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3082 if (hpe->peer_vhca_id == peer_vhca_id)
3083 hpe->hp->pair->peer_gone = true;
3084 }
3085}
3086
3087static int mlx5e_tc_netdev_event(struct notifier_block *this,
3088 unsigned long event, void *ptr)
3089{
3090 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3091 struct mlx5e_flow_steering *fs;
3092 struct mlx5e_priv *peer_priv;
3093 struct mlx5e_tc_table *tc;
3094 struct mlx5e_priv *priv;
3095
3096 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3097 event != NETDEV_UNREGISTER ||
3098 ndev->reg_state == NETREG_REGISTERED)
3099 return NOTIFY_DONE;
3100
3101 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3102 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3103 priv = container_of(fs, struct mlx5e_priv, fs);
3104 peer_priv = netdev_priv(ndev);
3105 if (priv == peer_priv ||
3106 !(priv->netdev->features & NETIF_F_HW_TC))
3107 return NOTIFY_DONE;
3108
3109 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3110
3111 return NOTIFY_DONE;
3112}
3113
655dc3d2 3114int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3115{
acff797c 3116 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3117 int err;
e8f887ac 3118
11c9c548 3119 hash_init(tc->mod_hdr_tbl);
5c65c564 3120 hash_init(tc->hairpin_tbl);
11c9c548 3121
4d8fcf21
AH		 3122 err = rhashtable_init(&tc->ht, &tc_ht_params);
3123 if (err)
3124 return err;
3125
3126 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3127 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3128 tc->netdevice_nb.notifier_call = NULL;
3129 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3130 }
3131
3132 return err;
e8f887ac
AV		 3133}
3134
3135static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3136{
3137 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3138 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3139
961e8979 3140 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3141 kfree(flow);
3142}
3143
655dc3d2 3144void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3145{
acff797c 3146 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3147
4d8fcf21
AH		 3148 if (tc->netdevice_nb.notifier_call)
3149 unregister_netdevice_notifier(&tc->netdevice_nb);
3150
d9ee0491 3151 rhashtable_destroy(&tc->ht);
e8f887ac 3152
acff797c
MG		 3153 if (!IS_ERR_OR_NULL(tc->t)) {
3154 mlx5_destroy_flow_table(tc->t);
3155 tc->t = NULL;
e8f887ac
AV		 3156 }
3157}
655dc3d2
OG		 3158
3159int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3160{
3161 return rhashtable_init(tc_ht, &tc_ht_params);
3162}
3163
3164void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3165{
3166 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3167}
01252a27 3168
d9ee0491 3169int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags)
01252a27 3170{
d9ee0491 3171 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3172
3173 return atomic_read(&tc_ht->nelems);
3174}
04de7dda
RD		 3175
3176void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3177{
3178 struct mlx5e_tc_flow *flow, *tmp;
3179
3180 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3181 __mlx5e_tc_del_fdb_peer_flow(flow);
3182}
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