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net/mlx5: Update SW steering new cmd interface
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
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e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
db76ca24 42#include <linux/completion.h>
03a9d11e 43#include <net/tc_act/tc_mirred.h>
776b12b6 44#include <net/tc_act/tc_vlan.h>
bbd00f7e 45#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 46#include <net/tc_act/tc_pedit.h>
26c02749 47#include <net/tc_act/tc_csum.h>
f6dfb4c3 48#include <net/arp.h>
3616d08b 49#include <net/ipv6_stubs.h>
e8f887ac 50#include "en.h"
1d447a39 51#include "en_rep.h"
232c0013 52#include "en_tc.h"
03a9d11e 53#include "eswitch.h"
49964352 54#include "esw/chains.h"
3f6d08d1 55#include "fs_core.h"
2c81bfd5 56#include "en/port.h"
101f4de9 57#include "en/tc_tun.h"
0a7fcb78 58#include "en/mapping.h"
4c3844d9 59#include "en/tc_ct.h"
04de7dda 60#include "lib/devcom.h"
9272e3df 61#include "lib/geneve.h"
7a978759 62#include "diag/en_tc_tracepoint.h"
e8f887ac 63
0a7fcb78
PB		 64#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
65
3bc4b7bf
OG		 66struct mlx5_nic_flow_attr {
67 u32 action;
68 u32 flow_tag;
2b688ea5 69 struct mlx5_modify_hdr *modify_hdr;
5c65c564 70 u32 hairpin_tirn;
38aa51c1 71 u8 match_level;
3f6d08d1 72 struct mlx5_flow_table *hairpin_ft;
b8aee822 73 struct mlx5_fc *counter;
3bc4b7bf
OG		 74};
75
226f2ca3 76#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 77
65ba8fb7 78enum {
226f2ca3
VB		 79 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
80 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
81 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 82 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 83 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
84 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
85 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
86 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
87 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
88 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
89 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 90 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 91 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
65ba8fb7
OG		 92};
93
e4ad91f2
CM		 94#define MLX5E_TC_MAX_SPLITS 1
95
79baaec7
EB		 96/* Helper struct for accessing a struct containing list_head array.
97 * Containing struct
98 * |- Helper array
99 * [0] Helper item 0
100 * |- list_head item 0
101 * |- index (0)
102 * [1] Helper item 1
103 * |- list_head item 1
104 * |- index (1)
105 * To access the containing struct from one of the list_head items:
106 * 1. Get the helper item from the list_head item using
107 * helper item =
108 * container_of(list_head item, helper struct type, list_head field)
109 * 2. Get the contining struct from the helper item and its index in the array:
110 * containing struct =
111 * container_of(helper item, containing struct type, helper field[index])
112 */
113struct encap_flow_item {
948993f2 114 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 115 struct list_head list;
116 int index;
117};
118
e8f887ac
AV		 119struct mlx5e_tc_flow {
120 struct rhash_head node;
655dc3d2 121 struct mlx5e_priv *priv;
e8f887ac 122 u64 cookie;
226f2ca3 123 unsigned long flags;
e4ad91f2 124 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 125 /* Flow can be associated with multiple encap IDs.
126 * The number of encaps is bounded by the number of supported
127 * destinations.
128 */
129 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 130 struct mlx5e_tc_flow *peer_flow;
dd58edc3 131 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 132 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 133 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 134 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 135 struct list_head peer; /* flows with peer flow */
b4a23329 136 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
2a1f1768 137 int tmp_efi_index;
6a06c2f7 138 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 139 refcount_t refcnt;
c5d326b2 140 struct rcu_head rcu_head;
95435ad7 141 struct completion init_done;
0a7fcb78
PB		 142 int tunnel_id; /* the mapped tunnel id of this flow */
143
3bc4b7bf
OG		 144 union {
145 struct mlx5_esw_flow_attr esw_attr[0];
146 struct mlx5_nic_flow_attr nic_attr[0];
147 };
e8f887ac
AV		 148};
149
17091853 150struct mlx5e_tc_flow_parse_attr {
1f6da306 151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 152 struct net_device *filter_dev;
17091853 153 struct mlx5_flow_spec spec;
6ae4a6a5 154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 156};
157
acff797c 158#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 159#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 160
0a7fcb78
PB		 161struct tunnel_match_key {
162 struct flow_dissector_key_control enc_control;
163 struct flow_dissector_key_keyid enc_key_id;
164 struct flow_dissector_key_ports enc_tp;
165 struct flow_dissector_key_ip enc_ip;
166 union {
167 struct flow_dissector_key_ipv4_addrs enc_ipv4;
168 struct flow_dissector_key_ipv6_addrs enc_ipv6;
169 };
170
171 int filter_ifindex;
172};
173
174/* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
175 * Upper TUNNEL_INFO_BITS for general tunnel info.
176 * Lower ENC_OPTS_BITS bits for enc_opts.
177 */
178#define TUNNEL_INFO_BITS 6
179#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
180#define ENC_OPTS_BITS 2
181#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
182#define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
183#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
184
8f1e0b97
PB		 185struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
186 [CHAIN_TO_REG] = {
187 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
188 .moffset = 0,
189 .mlen = 2,
190 },
0a7fcb78
PB		 191 [TUNNEL_TO_REG] = {
192 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
193 .moffset = 3,
194 .mlen = 1,
195 .soffset = MLX5_BYTE_OFF(fte_match_param,
196 misc_parameters_2.metadata_reg_c_1),
197 },
4c3844d9
PB		 198 [ZONE_TO_REG] = zone_to_reg_ct,
199 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
200 [MARK_TO_REG] = mark_to_reg_ct,
201 [LABELS_TO_REG] = labels_to_reg_ct,
202 [FTEID_TO_REG] = fteid_to_reg_ct,
5c6b9460 203 [TUPLEID_TO_REG] = tupleid_to_reg_ct,
8f1e0b97
PB		 204};
205
0a7fcb78
PB		 206static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
207
208void
209mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
210 enum mlx5e_tc_attr_to_reg type,
211 u32 data,
212 u32 mask)
213{
214 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
215 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
216 void *headers_c = spec->match_criteria;
217 void *headers_v = spec->match_value;
218 void *fmask, *fval;
219
220 fmask = headers_c + soffset;
221 fval = headers_v + soffset;
222
223 mask = cpu_to_be32(mask) >> (32 - (match_len * 8));
224 data = cpu_to_be32(data) >> (32 - (match_len * 8));
225
226 memcpy(fmask, &mask, match_len);
227 memcpy(fval, &data, match_len);
228
229 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
230}
231
232int
233mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
234 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
235 enum mlx5e_tc_attr_to_reg type,
236 u32 data)
237{
238 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
239 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
240 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
241 char *modact;
242 int err;
243
244 err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB,
245 mod_hdr_acts);
246 if (err)
247 return err;
248
249 modact = mod_hdr_acts->actions +
250 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
251
252 /* Firmware has 5bit length field and 0 means 32bits */
253 if (mlen == 4)
254 mlen = 0;
255
256 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
257 MLX5_SET(set_action_in, modact, field, mfield);
258 MLX5_SET(set_action_in, modact, offset, moffset * 8);
259 MLX5_SET(set_action_in, modact, length, mlen * 8);
260 MLX5_SET(set_action_in, modact, data, data);
261 mod_hdr_acts->num_actions++;
262
263 return 0;
264}
265
77ab67b7
OG		 266struct mlx5e_hairpin {
267 struct mlx5_hairpin *pair;
268
269 struct mlx5_core_dev *func_mdev;
3f6d08d1 270 struct mlx5e_priv *func_priv;
77ab67b7
OG		 271 u32 tdn;
272 u32 tirn;
3f6d08d1
OG		 273
274 int num_channels;
275 struct mlx5e_rqt indir_rqt;
276 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
277 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 278};
279
5c65c564
OG		 280struct mlx5e_hairpin_entry {
281 /* a node of a hash table which keeps all the hairpin entries */
282 struct hlist_node hairpin_hlist;
283
73edca73
VB		 284 /* protects flows list */
285 spinlock_t flows_lock;
5c65c564
OG		 286 /* flows sharing the same hairpin */
287 struct list_head flows;
db76ca24
VB		 288 /* hpe's that were not fully initialized when dead peer update event
289 * function traversed them.
290 */
291 struct list_head dead_peer_wait_list;
5c65c564 292
d8822868 293 u16 peer_vhca_id;
106be53b 294 u8 prio;
5c65c564 295 struct mlx5e_hairpin *hp;
e4f9abbd 296 refcount_t refcnt;
db76ca24 297 struct completion res_ready;
5c65c564
OG		 298};
299
11c9c548
OG		 300struct mod_hdr_key {
301 int num_actions;
302 void *actions;
303};
304
305struct mlx5e_mod_hdr_entry {
306 /* a node of a hash table which keeps all the mod_hdr entries */
307 struct hlist_node mod_hdr_hlist;
308
83a52f0d
VB		 309 /* protects flows list */
310 spinlock_t flows_lock;
11c9c548
OG		 311 /* flows sharing the same mod_hdr entry */
312 struct list_head flows;
313
314 struct mod_hdr_key key;
315
2b688ea5 316 struct mlx5_modify_hdr *modify_hdr;
dd58edc3
VB		 317
318 refcount_t refcnt;
a734d007
VB		 319 struct completion res_ready;
320 int compl_result;
11c9c548
OG		 321};
322
5a7e5bcb
VB		 323static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
324 struct mlx5e_tc_flow *flow);
325
326static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
327{
328 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
329 return ERR_PTR(-EINVAL);
330 return flow;
331}
332
333static void mlx5e_flow_put(struct mlx5e_priv *priv,
334 struct mlx5e_tc_flow *flow)
335{
336 if (refcount_dec_and_test(&flow->refcnt)) {
337 mlx5e_tc_del_flow(priv, flow);
c5d326b2 338 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 339 }
340}
341
226f2ca3
VB		 342static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
343{
344 /* Complete all memory stores before setting bit. */
345 smp_mb__before_atomic();
346 set_bit(flag, &flow->flags);
347}
348
349#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
350
c5d326b2
VB		 351static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
352 unsigned long flag)
353{
354 /* test_and_set_bit() provides all necessary barriers */
355 return test_and_set_bit(flag, &flow->flags);
356}
357
358#define flow_flag_test_and_set(flow, flag) \
359 __flow_flag_test_and_set(flow, \
360 MLX5E_TC_FLOW_FLAG_##flag)
361
226f2ca3
VB		 362static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
363{
364 /* Complete all memory stores before clearing bit. */
365 smp_mb__before_atomic();
366 clear_bit(flag, &flow->flags);
367}
368
369#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
370 MLX5E_TC_FLOW_FLAG_##flag)
371
372static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
373{
374 bool ret = test_bit(flag, &flow->flags);
375
376 /* Read fields of flow structure only after checking flags. */
377 smp_mb__after_atomic();
378 return ret;
379}
380
381#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
382 MLX5E_TC_FLOW_FLAG_##flag)
383
384static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
385{
386 return flow_flag_test(flow, ESWITCH);
387}
388
84179981
PB		 389static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390{
391 return flow_flag_test(flow, FT);
392}
393
226f2ca3
VB		 394static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
395{
396 return flow_flag_test(flow, OFFLOADED);
397}
398
11c9c548
OG		 399static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
400{
401 return jhash(key->actions,
402 key->num_actions * MLX5_MH_ACT_SZ, 0);
403}
404
405static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
406 struct mod_hdr_key *b)
407{
408 if (a->num_actions != b->num_actions)
409 return 1;
410
411 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
412}
413
dd58edc3
VB		 414static struct mod_hdr_tbl *
415get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
416{
417 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
418
419 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
420 &priv->fs.tc.mod_hdr;
421}
422
423static struct mlx5e_mod_hdr_entry *
424mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
425{
426 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
427
428 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
429 if (!cmp_mod_hdr_info(&mh->key, key)) {
430 refcount_inc(&mh->refcnt);
431 found = mh;
432 break;
433 }
434 }
435
436 return found;
437}
438
439static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
d2faae25
VB		 440 struct mlx5e_mod_hdr_entry *mh,
441 int namespace)
dd58edc3 442{
d2faae25
VB		 443 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
444
445 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
dd58edc3 446 return;
d2faae25
VB		 447 hash_del(&mh->mod_hdr_hlist);
448 mutex_unlock(&tbl->lock);
dd58edc3
VB		 449
450 WARN_ON(!list_empty(&mh->flows));
a734d007 451 if (mh->compl_result > 0)
2b688ea5 452 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
d2faae25 453
dd58edc3
VB		 454 kfree(mh);
455}
456
d2faae25
VB		 457static int get_flow_name_space(struct mlx5e_tc_flow *flow)
458{
459 return mlx5e_is_eswitch_flow(flow) ?
460 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
461}
11c9c548
OG		 462static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
463 struct mlx5e_tc_flow *flow,
464 struct mlx5e_tc_flow_parse_attr *parse_attr)
465{
11c9c548
OG		 466 int num_actions, actions_size, namespace, err;
467 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 468 struct mod_hdr_tbl *tbl;
11c9c548 469 struct mod_hdr_key key;
11c9c548
OG		 470 u32 hash_key;
471
6ae4a6a5 472 num_actions = parse_attr->mod_hdr_acts.num_actions;
11c9c548
OG		 473 actions_size = MLX5_MH_ACT_SZ * num_actions;
474
6ae4a6a5 475 key.actions = parse_attr->mod_hdr_acts.actions;
11c9c548
OG		 476 key.num_actions = num_actions;
477
478 hash_key = hash_mod_hdr_info(&key);
479
d2faae25 480 namespace = get_flow_name_space(flow);
dd58edc3 481 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 482
d2faae25 483 mutex_lock(&tbl->lock);
dd58edc3 484 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
a734d007
VB		 485 if (mh) {
486 mutex_unlock(&tbl->lock);
487 wait_for_completion(&mh->res_ready);
488
489 if (mh->compl_result < 0) {
490 err = -EREMOTEIO;
491 goto attach_header_err;
492 }
11c9c548 493 goto attach_flow;
a734d007 494 }
11c9c548
OG		 495
496 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
d2faae25 497 if (!mh) {
a734d007
VB		 498 mutex_unlock(&tbl->lock);
499 return -ENOMEM;
d2faae25 500 }
11c9c548
OG		 501
502 mh->key.actions = (void *)mh + sizeof(*mh);
503 memcpy(mh->key.actions, key.actions, actions_size);
504 mh->key.num_actions = num_actions;
83a52f0d 505 spin_lock_init(&mh->flows_lock);
11c9c548 506 INIT_LIST_HEAD(&mh->flows);
dd58edc3 507 refcount_set(&mh->refcnt, 1);
a734d007
VB		 508 init_completion(&mh->res_ready);
509
510 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
511 mutex_unlock(&tbl->lock);
11c9c548 512
2b688ea5
MG		 513 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
514 mh->key.num_actions,
515 mh->key.actions);
516 if (IS_ERR(mh->modify_hdr)) {
517 err = PTR_ERR(mh->modify_hdr);
a734d007
VB		 518 mh->compl_result = err;
519 goto alloc_header_err;
520 }
521 mh->compl_result = 1;
522 complete_all(&mh->res_ready);
11c9c548
OG		 523
524attach_flow:
dd58edc3 525 flow->mh = mh;
83a52f0d 526 spin_lock(&mh->flows_lock);
11c9c548 527 list_add(&flow->mod_hdr, &mh->flows);
83a52f0d 528 spin_unlock(&mh->flows_lock);
d2faae25 529 if (mlx5e_is_eswitch_flow(flow))
2b688ea5 530 flow->esw_attr->modify_hdr = mh->modify_hdr;
11c9c548 531 else
2b688ea5 532 flow->nic_attr->modify_hdr = mh->modify_hdr;
11c9c548
OG		 533
534 return 0;
535
a734d007
VB		 536alloc_header_err:
537 complete_all(&mh->res_ready);
538attach_header_err:
539 mlx5e_mod_hdr_put(priv, mh, namespace);
11c9c548
OG		 540 return err;
541}
542
543static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
544 struct mlx5e_tc_flow *flow)
545{
5a7e5bcb 546 /* flow wasn't fully initialized */
dd58edc3 547 if (!flow->mh)
5a7e5bcb
VB		 548 return;
549
83a52f0d 550 spin_lock(&flow->mh->flows_lock);
11c9c548 551 list_del(&flow->mod_hdr);
83a52f0d 552 spin_unlock(&flow->mh->flows_lock);
11c9c548 553
d2faae25 554 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
dd58edc3 555 flow->mh = NULL;
11c9c548
OG		 556}
557
77ab67b7
OG		 558static
559struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
560{
561 struct net_device *netdev;
562 struct mlx5e_priv *priv;
563
564 netdev = __dev_get_by_index(net, ifindex);
565 priv = netdev_priv(netdev);
566 return priv->mdev;
567}
568
569static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
570{
571 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
572 void *tirc;
573 int err;
574
575 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
576 if (err)
577 goto alloc_tdn_err;
578
579 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
580
581 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 582 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 583 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
584
585 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
586 if (err)
587 goto create_tir_err;
588
589 return 0;
590
591create_tir_err:
592 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
593alloc_tdn_err:
594 return err;
595}
596
597static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
598{
599 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
600 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
601}
602
3f6d08d1
OG		 603static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
604{
605 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
606 struct mlx5e_priv *priv = hp->func_priv;
607 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
608
609 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
610 hp->num_channels);
611
612 for (i = 0; i < sz; i++) {
613 ix = i;
bbeb53b8 614 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 615 ix = mlx5e_bits_invert(i, ilog2(sz));
616 ix = indirection_rqt[ix];
617 rqn = hp->pair->rqn[ix];
618 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
619 }
620}
621
622static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
623{
624 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
625 struct mlx5e_priv *priv = hp->func_priv;
626 struct mlx5_core_dev *mdev = priv->mdev;
627 void *rqtc;
628 u32 *in;
629
630 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
631 in = kvzalloc(inlen, GFP_KERNEL);
632 if (!in)
633 return -ENOMEM;
634
635 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
636
637 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
638 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
639
640 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
641
642 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
643 if (!err)
644 hp->indir_rqt.enabled = true;
645
646 kvfree(in);
647 return err;
648}
649
650static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
651{
652 struct mlx5e_priv *priv = hp->func_priv;
653 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
654 int tt, i, err;
655 void *tirc;
656
657 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 658 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
659
3f6d08d1
OG		 660 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
661 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
662
663 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
664 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
665 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 666 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
667
3f6d08d1
OG		 668 err = mlx5_core_create_tir(hp->func_mdev, in,
669 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
670 if (err) {
671 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
672 goto err_destroy_tirs;
673 }
674 }
675 return 0;
676
677err_destroy_tirs:
678 for (i = 0; i < tt; i++)
679 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
680 return err;
681}
682
683static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
684{
685 int tt;
686
687 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
688 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
689}
690
691static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
692 struct ttc_params *ttc_params)
693{
694 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
695 int tt;
696
697 memset(ttc_params, 0, sizeof(*ttc_params));
698
699 ttc_params->any_tt_tirn = hp->tirn;
700
701 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
702 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
703
6412bb39 704 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 705 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
706 ft_attr->prio = MLX5E_TC_PRIO;
707}
708
709static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
710{
711 struct mlx5e_priv *priv = hp->func_priv;
712 struct ttc_params ttc_params;
713 int err;
714
715 err = mlx5e_hairpin_create_indirect_rqt(hp);
716 if (err)
717 return err;
718
719 err = mlx5e_hairpin_create_indirect_tirs(hp);
720 if (err)
721 goto err_create_indirect_tirs;
722
723 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
724 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
725 if (err)
726 goto err_create_ttc_table;
727
728 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
729 hp->num_channels, hp->ttc.ft.t->id);
730
731 return 0;
732
733err_create_ttc_table:
734 mlx5e_hairpin_destroy_indirect_tirs(hp);
735err_create_indirect_tirs:
736 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
737
738 return err;
739}
740
741static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
742{
743 struct mlx5e_priv *priv = hp->func_priv;
744
745 mlx5e_destroy_ttc_table(priv, &hp->ttc);
746 mlx5e_hairpin_destroy_indirect_tirs(hp);
747 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
748}
749
77ab67b7
OG		 750static struct mlx5e_hairpin *
751mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
752 int peer_ifindex)
753{
754 struct mlx5_core_dev *func_mdev, *peer_mdev;
755 struct mlx5e_hairpin *hp;
756 struct mlx5_hairpin *pair;
757 int err;
758
759 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
760 if (!hp)
761 return ERR_PTR(-ENOMEM);
762
763 func_mdev = priv->mdev;
764 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
765
766 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
767 if (IS_ERR(pair)) {
768 err = PTR_ERR(pair);
769 goto create_pair_err;
770 }
771 hp->pair = pair;
772 hp->func_mdev = func_mdev;
3f6d08d1
OG		 773 hp->func_priv = priv;
774 hp->num_channels = params->num_channels;
77ab67b7
OG		 775
776 err = mlx5e_hairpin_create_transport(hp);
777 if (err)
778 goto create_transport_err;
779
3f6d08d1
OG		 780 if (hp->num_channels > 1) {
781 err = mlx5e_hairpin_rss_init(hp);
782 if (err)
783 goto rss_init_err;
784 }
785
77ab67b7
OG		 786 return hp;
787
3f6d08d1
OG		 788rss_init_err:
789 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 790create_transport_err:
791 mlx5_core_hairpin_destroy(hp->pair);
792create_pair_err:
793 kfree(hp);
794 return ERR_PTR(err);
795}
796
797static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
798{
3f6d08d1
OG		 799 if (hp->num_channels > 1)
800 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 801 mlx5e_hairpin_destroy_transport(hp);
802 mlx5_core_hairpin_destroy(hp->pair);
803 kvfree(hp);
804}
805
106be53b
OG		 806static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
807{
808 return (peer_vhca_id << 16 | prio);
809}
810
5c65c564 811static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 812 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 813{
814 struct mlx5e_hairpin_entry *hpe;
106be53b 815 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 816
817 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 818 hairpin_hlist, hash_key) {
e4f9abbd
VB		 819 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
820 refcount_inc(&hpe->refcnt);
5c65c564 821 return hpe;
e4f9abbd 822 }
5c65c564
OG		 823 }
824
825 return NULL;
826}
827
e4f9abbd
VB		 828static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
829 struct mlx5e_hairpin_entry *hpe)
830{
831 /* no more hairpin flows for us, release the hairpin pair */
b32accda 832 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 833 return;
b32accda
VB		 834 hash_del(&hpe->hairpin_hlist);
835 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 836
db76ca24
VB		 837 if (!IS_ERR_OR_NULL(hpe->hp)) {
838 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
839 dev_name(hpe->hp->pair->peer_mdev->device));
840
841 mlx5e_hairpin_destroy(hpe->hp);
842 }
e4f9abbd
VB		 843
844 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 845 kfree(hpe);
846}
847
106be53b
OG		 848#define UNKNOWN_MATCH_PRIO 8
849
850static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 851 struct mlx5_flow_spec *spec, u8 *match_prio,
852 struct netlink_ext_ack *extack)
106be53b
OG		 853{
854 void *headers_c, *headers_v;
855 u8 prio_val, prio_mask = 0;
856 bool vlan_present;
857
858#ifdef CONFIG_MLX5_CORE_EN_DCB
859 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 860 NL_SET_ERR_MSG_MOD(extack,
861 "only PCP trust state supported for hairpin");
106be53b
OG		 862 return -EOPNOTSUPP;
863 }
864#endif
865 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
866 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
867
868 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
869 if (vlan_present) {
870 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
871 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
872 }
873
874 if (!vlan_present || !prio_mask) {
875 prio_val = UNKNOWN_MATCH_PRIO;
876 } else if (prio_mask != 0x7) {
e98bedf5
EB		 877 NL_SET_ERR_MSG_MOD(extack,
878 "masked priority match not supported for hairpin");
106be53b
OG		 879 return -EOPNOTSUPP;
880 }
881
882 *match_prio = prio_val;
883 return 0;
884}
885
5c65c564
OG		 886static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
887 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 888 struct mlx5e_tc_flow_parse_attr *parse_attr,
889 struct netlink_ext_ack *extack)
5c65c564 890{
98b66cb1 891 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 892 struct mlx5_hairpin_params params;
d8822868 893 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 894 struct mlx5e_hairpin_entry *hpe;
895 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 896 u64 link_speed64;
897 u32 link_speed;
106be53b 898 u8 match_prio;
d8822868 899 u16 peer_id;
5c65c564
OG		 900 int err;
901
d8822868
OG		 902 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
903 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 904 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 905 return -EOPNOTSUPP;
906 }
907
d8822868 908 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 909 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
910 extack);
106be53b
OG		 911 if (err)
912 return err;
b32accda
VB		 913
914 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 915 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 916 if (hpe) {
917 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
918 wait_for_completion(&hpe->res_ready);
919
920 if (IS_ERR(hpe->hp)) {
921 err = -EREMOTEIO;
922 goto out_err;
923 }
5c65c564 924 goto attach_flow;
db76ca24 925 }
5c65c564
OG		 926
927 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 928 if (!hpe) {
db76ca24
VB		 929 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
930 return -ENOMEM;
b32accda 931 }
5c65c564 932
73edca73 933 spin_lock_init(&hpe->flows_lock);
5c65c564 934 INIT_LIST_HEAD(&hpe->flows);
db76ca24 935 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 936 hpe->peer_vhca_id = peer_id;
106be53b 937 hpe->prio = match_prio;
e4f9abbd 938 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 939 init_completion(&hpe->res_ready);
940
941 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
942 hash_hairpin_info(peer_id, match_prio));
943 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 944
945 params.log_data_size = 15;
946 params.log_data_size = min_t(u8, params.log_data_size,
947 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
948 params.log_data_size = max_t(u8, params.log_data_size,
949 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 950
eb9180f7
OG		 951 params.log_num_packets = params.log_data_size -
952 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
953 params.log_num_packets = min_t(u8, params.log_num_packets,
954 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
955
956 params.q_counter = priv->q_counter;
3f6d08d1 957 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 958 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 959 link_speed = max_t(u32, link_speed, 50000);
960 link_speed64 = link_speed;
961 do_div(link_speed64, 50000);
962 params.num_channels = link_speed64;
963
5c65c564 964 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 965 hpe->hp = hp;
966 complete_all(&hpe->res_ready);
5c65c564
OG		 967 if (IS_ERR(hp)) {
968 err = PTR_ERR(hp);
db76ca24 969 goto out_err;
5c65c564
OG		 970 }
971
eb9180f7 972 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 973 hp->tirn, hp->pair->rqn[0],
974 dev_name(hp->pair->peer_mdev->device),
eb9180f7 975 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 976
5c65c564 977attach_flow:
3f6d08d1 978 if (hpe->hp->num_channels > 1) {
226f2ca3 979 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 980 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
981 } else {
982 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
983 }
b32accda 984
e4f9abbd 985 flow->hpe = hpe;
73edca73 986 spin_lock(&hpe->flows_lock);
5c65c564 987 list_add(&flow->hairpin, &hpe->flows);
73edca73 988 spin_unlock(&hpe->flows_lock);
3f6d08d1 989
5c65c564
OG		 990 return 0;
991
db76ca24
VB		 992out_err:
993 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 994 return err;
995}
996
997static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
998 struct mlx5e_tc_flow *flow)
999{
5a7e5bcb 1000 /* flow wasn't fully initialized */
e4f9abbd 1001 if (!flow->hpe)
5a7e5bcb
VB		 1002 return;
1003
73edca73 1004 spin_lock(&flow->hpe->flows_lock);
5c65c564 1005 list_del(&flow->hairpin);
73edca73
VB		 1006 spin_unlock(&flow->hpe->flows_lock);
1007
e4f9abbd
VB		 1008 mlx5e_hairpin_put(priv, flow->hpe);
1009 flow->hpe = NULL;
5c65c564
OG		 1010}
1011
c83954ab 1012static int
74491de9 1013mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 1014 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 1015 struct mlx5e_tc_flow *flow,
1016 struct netlink_ext_ack *extack)
e8f887ac 1017{
bb0ee7dc 1018 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 1019 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 1020 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 1021 struct mlx5_flow_destination dest[2] = {};
66958ed9 1022 struct mlx5_flow_act flow_act = {
3bc4b7bf 1023 .action = attr->action,
bb0ee7dc 1024 .flags = FLOW_ACT_NO_APPEND,
66958ed9 1025 };
aad7e08d 1026 struct mlx5_fc *counter = NULL;
5c65c564 1027 int err, dest_ix = 0;
e8f887ac 1028
bb0ee7dc
JL		 1029 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1030 flow_context->flow_tag = attr->flow_tag;
1031
226f2ca3 1032 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 1033 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 1034 if (err)
1035 return err;
1036
226f2ca3 1037 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 1038 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1039 dest[dest_ix].ft = attr->hairpin_ft;
1040 } else {
5c65c564
OG		 1041 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1042 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 1043 }
1044 dest_ix++;
3f6d08d1
OG		 1045 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1046 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1047 dest[dest_ix].ft = priv->fs.vlan.ft.t;
1048 dest_ix++;
5c65c564 1049 }
aad7e08d 1050
5c65c564
OG		 1051 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1052 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 1053 if (IS_ERR(counter))
1054 return PTR_ERR(counter);
1055
5c65c564 1056 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 1057 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 1058 dest_ix++;
b8aee822 1059 attr->counter = counter;
aad7e08d
AV		 1060 }
1061
2f4fe4ca 1062 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 1063 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 1064 flow_act.modify_hdr = attr->modify_hdr;
6ae4a6a5 1065 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1066 if (err)
5a7e5bcb 1067 return err;
2f4fe4ca
OG		 1068 }
1069
b6fac0b4 1070 mutex_lock(&priv->fs.tc.t_lock);
acff797c 1071 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
61dc7b01
PB		 1072 struct mlx5_flow_table_attr ft_attr = {};
1073 int tc_grp_size, tc_tbl_size, tc_num_grps;
21b9c144
OG		 1074 u32 max_flow_counter;
1075
1076 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1077 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1078
1079 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
1080
1081 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
1082 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
61dc7b01 1083 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
21b9c144 1084
61dc7b01
PB		 1085 ft_attr.prio = MLX5E_TC_PRIO;
1086 ft_attr.max_fte = tc_tbl_size;
1087 ft_attr.level = MLX5E_TC_FT_LEVEL;
1088 ft_attr.autogroup.max_num_groups = tc_num_grps;
acff797c
MG		 1089 priv->fs.tc.t =
1090 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
61dc7b01 1091 &ft_attr);
acff797c 1092 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 1093 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 1094 NL_SET_ERR_MSG_MOD(extack,
1095 "Failed to create tc offload table\n");
e8f887ac
AV		 1096 netdev_err(priv->netdev,
1097 "Failed to create tc offload table\n");
5a7e5bcb 1098 return PTR_ERR(priv->fs.tc.t);
e8f887ac 1099 }
e8f887ac
AV		 1100 }
1101
38aa51c1 1102 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 1103 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1104
c83954ab
RL		 1105 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
1106 &flow_act, dest, dest_ix);
b6fac0b4 1107 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 1108
a2b7189b 1109 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1110}
1111
d85cdccb
OG		 1112static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1113 struct mlx5e_tc_flow *flow)
1114{
513f8f7f 1115 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 1116 struct mlx5_fc *counter = NULL;
1117
b8aee822 1118 counter = attr->counter;
5a7e5bcb
VB		 1119 if (!IS_ERR_OR_NULL(flow->rule[0]))
1120 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1121 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1122
b6fac0b4 1123 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1124 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1125 mlx5_destroy_flow_table(priv->fs.tc.t);
1126 priv->fs.tc.t = NULL;
1127 }
b6fac0b4 1128 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1129
513f8f7f 1130 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1131 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1132
226f2ca3 1133 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1134 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1135}
1136
aa0cbbae 1137static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1138 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1139
3c37745e 1140static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1141 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1142 struct net_device *mirred_dev,
1143 int out_index,
8c4dc42b 1144 struct netlink_ext_ack *extack,
0ad060ee
RD		 1145 struct net_device **encap_dev,
1146 bool *encap_valid);
3c37745e 1147
6d2a3ed0
OG		 1148static struct mlx5_flow_handle *
1149mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1150 struct mlx5e_tc_flow *flow,
1151 struct mlx5_flow_spec *spec,
1152 struct mlx5_esw_flow_attr *attr)
1153{
1ef3018f 1154 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1155 struct mlx5_flow_handle *rule;
4c3844d9 1156
1ef3018f
PB		 1157 if (flow_flag_test(flow, CT)) {
1158 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1159
1160 return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr,
1161 mod_hdr_acts);
1162 }
6d2a3ed0
OG		 1163
1164 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1165 if (IS_ERR(rule))
1166 return rule;
1167
e85e02ba 1168 if (attr->split_count) {
6d2a3ed0
OG		 1169 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1170 if (IS_ERR(flow->rule[1])) {
1171 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1172 return flow->rule[1];
1173 }
1174 }
1175
6d2a3ed0
OG		 1176 return rule;
1177}
1178
1179static void
1180mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1181 struct mlx5e_tc_flow *flow,
4c3844d9 1182 struct mlx5_esw_flow_attr *attr)
6d2a3ed0 1183{
226f2ca3 1184 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1185
4c3844d9
PB		 1186 if (flow_flag_test(flow, CT)) {
1187 mlx5_tc_ct_delete_flow(flow->priv, flow, attr);
1188 return;
1189 }
1190
e85e02ba 1191 if (attr->split_count)
6d2a3ed0
OG		 1192 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1193
1194 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1195}
1196
5dbe906f
PB		 1197static struct mlx5_flow_handle *
1198mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1199 struct mlx5e_tc_flow *flow,
178f69b4 1200 struct mlx5_flow_spec *spec)
5dbe906f 1201{
178f69b4 1202 struct mlx5_esw_flow_attr slow_attr;
5dbe906f
PB		 1203 struct mlx5_flow_handle *rule;
1204
178f69b4
EC		 1205 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1206 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1207 slow_attr.split_count = 0;
1208 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f 1209
178f69b4 1210 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
5dbe906f 1211 if (!IS_ERR(rule))
226f2ca3 1212 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1213
1214 return rule;
1215}
1216
1217static void
1218mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1219 struct mlx5e_tc_flow *flow)
5dbe906f 1220{
178f69b4
EC		 1221 struct mlx5_esw_flow_attr slow_attr;
1222
1223 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1224 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1225 slow_attr.split_count = 0;
1226 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1227 mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
226f2ca3 1228 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1229}
1230
ad86755b
VB		 1231/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1232 * function.
1233 */
1234static void unready_flow_add(struct mlx5e_tc_flow *flow,
1235 struct list_head *unready_flows)
1236{
1237 flow_flag_set(flow, NOT_READY);
1238 list_add_tail(&flow->unready, unready_flows);
1239}
1240
1241/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1242 * function.
1243 */
1244static void unready_flow_del(struct mlx5e_tc_flow *flow)
1245{
1246 list_del(&flow->unready);
1247 flow_flag_clear(flow, NOT_READY);
1248}
1249
b4a23329
RD		 1250static void add_unready_flow(struct mlx5e_tc_flow *flow)
1251{
1252 struct mlx5_rep_uplink_priv *uplink_priv;
1253 struct mlx5e_rep_priv *rpriv;
1254 struct mlx5_eswitch *esw;
1255
1256 esw = flow->priv->mdev->priv.eswitch;
1257 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1258 uplink_priv = &rpriv->uplink_priv;
1259
ad86755b
VB		 1260 mutex_lock(&uplink_priv->unready_flows_lock);
1261 unready_flow_add(flow, &uplink_priv->unready_flows);
1262 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1263}
1264
1265static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1266{
ad86755b
VB		 1267 struct mlx5_rep_uplink_priv *uplink_priv;
1268 struct mlx5e_rep_priv *rpriv;
1269 struct mlx5_eswitch *esw;
1270
1271 esw = flow->priv->mdev->priv.eswitch;
1272 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1273 uplink_priv = &rpriv->uplink_priv;
1274
1275 mutex_lock(&uplink_priv->unready_flows_lock);
1276 unready_flow_del(flow);
1277 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1278}
1279
c83954ab 1280static int
74491de9 1281mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1282 struct mlx5e_tc_flow *flow,
1283 struct netlink_ext_ack *extack)
adb4c123
OG		 1284{
1285 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 1286 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1287 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3c37745e 1288 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1289 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1290 struct mlx5e_rep_priv *rpriv;
1291 struct mlx5e_priv *out_priv;
0ad060ee 1292 bool encap_valid = true;
39ac237c 1293 u32 max_prio, max_chain;
0ad060ee 1294 int err = 0;
f493f155 1295 int out_index;
8b32580d 1296
39ac237c 1297 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
61644c3d
RD		 1298 NL_SET_ERR_MSG_MOD(extack,
1299 "E-switch priorities unsupported, upgrade FW");
d14f6f2a
OG		 1300 return -EOPNOTSUPP;
1301 }
bf07aa73 1302
84179981
PB		 1303 /* We check chain range only for tc flows.
1304 * For ft flows, we checked attr->chain was originally 0 and set it to
1305 * FDB_FT_CHAIN which is outside tc range.
1306 * See mlx5e_rep_setup_ft_cb().
1307 */
39ac237c 1308 max_chain = mlx5_esw_chains_get_chain_range(esw);
84179981 1309 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1310 NL_SET_ERR_MSG_MOD(extack,
1311 "Requested chain is out of supported range");
5a7e5bcb 1312 return -EOPNOTSUPP;
bf07aa73
PB		 1313 }
1314
39ac237c 1315 max_prio = mlx5_esw_chains_get_prio_range(esw);
bf07aa73 1316 if (attr->prio > max_prio) {
61644c3d
RD		 1317 NL_SET_ERR_MSG_MOD(extack,
1318 "Requested priority is out of supported range");
5a7e5bcb 1319 return -EOPNOTSUPP;
bf07aa73 1320 }
e52c2802 1321
f493f155 1322 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1323 int mirred_ifindex;
1324
f493f155
EB		 1325 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1326 continue;
1327
7040632d 1328 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1329 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1330 mirred_ifindex);
733d4f36 1331 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1332 extack, &encap_dev, &encap_valid);
1333 if (err)
5a7e5bcb 1334 return err;
0ad060ee 1335
3c37745e
OG		 1336 out_priv = netdev_priv(encap_dev);
1337 rpriv = out_priv->ppriv;
1cc26d74
EB		 1338 attr->dests[out_index].rep = rpriv->rep;
1339 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1340 }
1341
8b32580d 1342 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1343 if (err)
5a7e5bcb 1344 return err;
adb4c123 1345
d7e75a32 1346 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1347 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1348 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1349 if (err)
5a7e5bcb 1350 return err;
d7e75a32
OG		 1351 }
1352
b8aee822 1353 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1354 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1355 if (IS_ERR(counter))
1356 return PTR_ERR(counter);
b8aee822
MB		 1357
1358 attr->counter = counter;
1359 }
1360
0ad060ee
RD		 1361 /* we get here if one of the following takes place:
1362 * (1) there's no error
1363 * (2) there's an encap action and we don't have valid neigh
3c37745e 1364 */
bc1d75fa 1365 if (!encap_valid)
178f69b4 1366 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1367 else
6d2a3ed0 1368 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1369
5a7e5bcb
VB		 1370 if (IS_ERR(flow->rule[0]))
1371 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1372 else
1373 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1374
1375 return 0;
aa0cbbae 1376}
d85cdccb 1377
9272e3df
YK		 1378static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1379{
1380 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1381 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1382 spec->match_value,
1383 misc_parameters_3);
1384 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1385 headers_v,
1386 geneve_tlv_option_0_data);
1387
1388 return !!geneve_tlv_opt_0_data;
1389}
1390
d85cdccb
OG		 1391static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1392 struct mlx5e_tc_flow *flow)
1393{
1394 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1395 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
f493f155 1396 int out_index;
d85cdccb 1397
0a7fcb78
PB		 1398 mlx5e_put_flow_tunnel_id(flow);
1399
226f2ca3 1400 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1401 remove_unready_flow(flow);
ef06c9ee
RD		 1402 kvfree(attr->parse_attr);
1403 return;
1404 }
1405
226f2ca3
VB		 1406 if (mlx5e_is_offloaded_flow(flow)) {
1407 if (flow_flag_test(flow, SLOW))
178f69b4 1408 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1409 else
1410 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1411 }
d85cdccb 1412
9272e3df
YK		 1413 if (mlx5_flow_has_geneve_opt(flow))
1414 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1415
513f8f7f 1416 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1417
f493f155 1418 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1419 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1420 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1421 kfree(attr->parse_attr->tun_info[out_index]);
1422 }
f493f155 1423 kvfree(attr->parse_attr);
d7e75a32 1424
513f8f7f 1425 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1426 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1427
1428 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1429 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1430}
1431
232c0013 1432void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1433 struct mlx5e_encap_entry *e,
1434 struct list_head *flow_list)
232c0013 1435{
3c37745e 1436 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1437 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0
OG		 1438 struct mlx5_flow_handle *rule;
1439 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1440 struct mlx5e_tc_flow *flow;
1441 int err;
1442
2b688ea5
MG		 1443 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1444 e->reformat_type,
1445 e->encap_size, e->encap_header,
1446 MLX5_FLOW_NAMESPACE_FDB);
1447 if (IS_ERR(e->pkt_reformat)) {
1448 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1449 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1450 return;
1451 }
1452 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1453 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1454
2a1f1768 1455 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1456 bool all_flow_encaps_valid = true;
1457 int i;
1458
95435ad7
VB		 1459 if (!mlx5e_is_offloaded_flow(flow))
1460 continue;
3c37745e 1461 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1462 spec = &esw_attr->parse_attr->spec;
1463
2b688ea5 1464 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1465 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1466 /* Flow can be associated with multiple encap entries.
1467 * Before offloading the flow verify that all of them have
1468 * a valid neighbour.
1469 */
1470 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1471 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1472 continue;
1473 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1474 all_flow_encaps_valid = false;
1475 break;
1476 }
1477 }
1478 /* Do not offload flows with unresolved neighbors */
1479 if (!all_flow_encaps_valid)
2a1f1768 1480 continue;
5dbe906f 1481 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1482 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1483 if (IS_ERR(rule)) {
1484 err = PTR_ERR(rule);
232c0013
HHZ		 1485 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1486 err);
2a1f1768 1487 continue;
232c0013 1488 }
5dbe906f 1489
178f69b4 1490 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1491 flow->rule[0] = rule;
226f2ca3
VB		 1492 /* was unset when slow path rule removed */
1493 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1494 }
1495}
1496
1497void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1498 struct mlx5e_encap_entry *e,
1499 struct list_head *flow_list)
232c0013 1500{
3c37745e 1501 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1502 struct mlx5_flow_handle *rule;
1503 struct mlx5_flow_spec *spec;
232c0013 1504 struct mlx5e_tc_flow *flow;
5dbe906f 1505 int err;
232c0013 1506
2a1f1768 1507 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1508 if (!mlx5e_is_offloaded_flow(flow))
1509 continue;
5dbe906f
PB		 1510 spec = &flow->esw_attr->parse_attr->spec;
1511
1512 /* update from encap rule to slow path rule */
178f69b4 1513 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1514 /* mark the flow's encap dest as non-valid */
2a1f1768 1515 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1516
1517 if (IS_ERR(rule)) {
1518 err = PTR_ERR(rule);
1519 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1520 err);
2a1f1768 1521 continue;
5dbe906f
PB		 1522 }
1523
1524 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1525 flow->rule[0] = rule;
226f2ca3
VB		 1526 /* was unset when fast path rule removed */
1527 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1528 }
1529
61c806da
OG		 1530 /* we know that the encap is valid */
1531 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1532 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1533}
1534
b8aee822
MB		 1535static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1536{
226f2ca3 1537 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1538 return flow->esw_attr->counter;
1539 else
1540 return flow->nic_attr->counter;
1541}
1542
2a1f1768
VB		 1543/* Takes reference to all flows attached to encap and adds the flows to
1544 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1545 */
1546void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1547{
1548 struct encap_flow_item *efi;
1549 struct mlx5e_tc_flow *flow;
1550
1551 list_for_each_entry(efi, &e->flows, list) {
1552 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1553 if (IS_ERR(mlx5e_flow_get(flow)))
1554 continue;
95435ad7 1555 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1556
1557 flow->tmp_efi_index = efi->index;
1558 list_add(&flow->tmp_list, flow_list);
1559 }
1560}
1561
6a06c2f7 1562/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1563void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1564{
1565 struct mlx5e_tc_flow *flow, *tmp;
1566
1567 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1568 mlx5e_flow_put(priv, flow);
1569}
1570
ac0d9176
VB		 1571static struct mlx5e_encap_entry *
1572mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1573 struct mlx5e_encap_entry *e)
1574{
1575 struct mlx5e_encap_entry *next = NULL;
1576
1577retry:
1578 rcu_read_lock();
1579
1580 /* find encap with non-zero reference counter value */
1581 for (next = e ?
1582 list_next_or_null_rcu(&nhe->encap_list,
1583 &e->encap_list,
1584 struct mlx5e_encap_entry,
1585 encap_list) :
1586 list_first_or_null_rcu(&nhe->encap_list,
1587 struct mlx5e_encap_entry,
1588 encap_list);
1589 next;
1590 next = list_next_or_null_rcu(&nhe->encap_list,
1591 &next->encap_list,
1592 struct mlx5e_encap_entry,
1593 encap_list))
1594 if (mlx5e_encap_take(next))
1595 break;
1596
1597 rcu_read_unlock();
1598
1599 /* release starting encap */
1600 if (e)
1601 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1602 if (!next)
1603 return next;
1604
1605 /* wait for encap to be fully initialized */
1606 wait_for_completion(&next->res_ready);
1607 /* continue searching if encap entry is not in valid state after completion */
1608 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1609 e = next;
1610 goto retry;
1611 }
1612
1613 return next;
1614}
1615
f6dfb4c3
HHZ		 1616void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1617{
1618 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1619 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1620 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1621 struct mlx5_fc *counter;
1622 struct neigh_table *tbl;
1623 bool neigh_used = false;
1624 struct neighbour *n;
90bb7692 1625 u64 lastuse;
f6dfb4c3
HHZ		 1626
1627 if (m_neigh->family == AF_INET)
1628 tbl = &arp_tbl;
1629#if IS_ENABLED(CONFIG_IPV6)
1630 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1631 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1632#endif
1633 else
1634 return;
1635
ac0d9176
VB		 1636 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1637 * next one.
1638 */
1639 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1640 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1641 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1642 struct mlx5_eswitch *esw;
1643 LIST_HEAD(flow_list);
948993f2 1644
6a06c2f7
VB		 1645 esw = priv->mdev->priv.eswitch;
1646 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1647 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1648 flow = container_of(efi, struct mlx5e_tc_flow,
1649 encaps[efi->index]);
5a7e5bcb
VB		 1650 if (IS_ERR(mlx5e_flow_get(flow)))
1651 continue;
6a06c2f7 1652 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1653
226f2ca3 1654 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1655 counter = mlx5e_tc_get_counter(flow);
90bb7692 1656 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1657 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1658 neigh_used = true;
1659 break;
1660 }
1661 }
1662 }
6a06c2f7 1663 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1664
6a06c2f7 1665 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1666 if (neigh_used) {
1667 /* release current encap before breaking the loop */
6a06c2f7 1668 mlx5e_encap_put(priv, e);
e36d4810 1669 break;
ac0d9176 1670 }
f6dfb4c3
HHZ		 1671 }
1672
c786fe59
VB		 1673 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1674
f6dfb4c3
HHZ		 1675 if (neigh_used) {
1676 nhe->reported_lastuse = jiffies;
1677
1678 /* find the relevant neigh according to the cached device and
1679 * dst ip pair
1680 */
1681 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1682 if (!n)
f6dfb4c3 1683 return;
f6dfb4c3
HHZ		 1684
1685 neigh_event_send(n, NULL);
1686 neigh_release(n);
1687 }
1688}
1689
61086f39 1690static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1691{
948993f2 1692 WARN_ON(!list_empty(&e->flows));
948993f2 1693
3c140dd5
VB		 1694 if (e->compl_result > 0) {
1695 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1696
1697 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1698 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1699 }
948993f2 1700
2a4b6526 1701 kfree(e->tun_info);
948993f2 1702 kfree(e->encap_header);
ac0d9176 1703 kfree_rcu(e, rcu);
948993f2
VB		 1704}
1705
61086f39
VB		 1706void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1707{
1708 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1709
1710 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1711 return;
1712 hash_del_rcu(&e->encap_hlist);
1713 mutex_unlock(&esw->offloads.encap_tbl_lock);
1714
1715 mlx5e_encap_dealloc(priv, e);
1716}
1717
d85cdccb 1718static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1719 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1720{
61086f39
VB		 1721 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1722 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1723
5a7e5bcb 1724 /* flow wasn't fully initialized */
61086f39 1725 if (!e)
5a7e5bcb
VB		 1726 return;
1727
61086f39 1728 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1729 list_del(&flow->encaps[out_index].list);
948993f2 1730 flow->encaps[out_index].e = NULL;
61086f39
VB		 1731 if (!refcount_dec_and_test(&e->refcnt)) {
1732 mutex_unlock(&esw->offloads.encap_tbl_lock);
1733 return;
1734 }
1735 hash_del_rcu(&e->encap_hlist);
1736 mutex_unlock(&esw->offloads.encap_tbl_lock);
1737
1738 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1739}
1740
04de7dda
RD		 1741static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1742{
1743 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1744
226f2ca3
VB		 1745 if (!flow_flag_test(flow, ESWITCH) ||
1746 !flow_flag_test(flow, DUP))
04de7dda
RD		 1747 return;
1748
1749 mutex_lock(&esw->offloads.peer_mutex);
1750 list_del(&flow->peer);
1751 mutex_unlock(&esw->offloads.peer_mutex);
1752
226f2ca3 1753 flow_flag_clear(flow, DUP);
04de7dda 1754
eb252c3a
RD		 1755 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1756 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1757 kfree(flow->peer_flow);
1758 }
1759
04de7dda
RD		 1760 flow->peer_flow = NULL;
1761}
1762
1763static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1764{
1765 struct mlx5_core_dev *dev = flow->priv->mdev;
1766 struct mlx5_devcom *devcom = dev->priv.devcom;
1767 struct mlx5_eswitch *peer_esw;
1768
1769 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1770 if (!peer_esw)
1771 return;
1772
1773 __mlx5e_tc_del_fdb_peer_flow(flow);
1774 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1775}
1776
e8f887ac 1777static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1778 struct mlx5e_tc_flow *flow)
e8f887ac 1779{
226f2ca3 1780 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1781 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1782 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1783 } else {
d85cdccb 1784 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1785 }
e8f887ac
AV		 1786}
1787
0a7fcb78
PB		 1788static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1789{
1790 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1791 struct flow_action *flow_action = &rule->action;
1792 const struct flow_action_entry *act;
1793 int i;
1794
1795 flow_action_for_each(i, act, flow_action) {
1796 switch (act->id) {
1797 case FLOW_ACTION_GOTO:
1798 return true;
1799 default:
1800 continue;
1801 }
1802 }
1803
1804 return false;
1805}
bbd00f7e 1806
0a7fcb78
PB		 1807static int
1808enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1809 struct flow_dissector_key_enc_opts *opts,
1810 struct netlink_ext_ack *extack,
1811 bool *dont_care)
1812{
1813 struct geneve_opt *opt;
1814 int off = 0;
1815
1816 *dont_care = true;
1817
1818 while (opts->len > off) {
1819 opt = (struct geneve_opt *)&opts->data[off];
1820
1821 if (!(*dont_care) || opt->opt_class || opt->type ||
1822 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1823 *dont_care = false;
1824
1825 if (opt->opt_class != U16_MAX ||
1826 opt->type != U8_MAX ||
1827 memchr_inv(opt->opt_data, 0xFF,
1828 opt->length * 4)) {
1829 NL_SET_ERR_MSG(extack,
1830 "Partial match of tunnel options in chain > 0 isn't supported");
1831 netdev_warn(priv->netdev,
1832 "Partial match of tunnel options in chain > 0 isn't supported");
1833 return -EOPNOTSUPP;
1834 }
1835 }
1836
1837 off += sizeof(struct geneve_opt) + opt->length * 4;
1838 }
1839
1840 return 0;
1841}
1842
1843#define COPY_DISSECTOR(rule, diss_key, dst)\
1844({ \
1845 struct flow_rule *__rule = (rule);\
1846 typeof(dst) __dst = dst;\
1847\
1848 memcpy(__dst,\
1849 skb_flow_dissector_target(__rule->match.dissector,\
1850 diss_key,\
1851 __rule->match.key),\
1852 sizeof(*__dst));\
1853})
1854
1855static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1856 struct mlx5e_tc_flow *flow,
1857 struct flow_cls_offload *f,
1858 struct net_device *filter_dev)
bbd00f7e 1859{
f9e30088 1860 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78
PB		 1861 struct netlink_ext_ack *extack = f->common.extack;
1862 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1863 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1864 struct flow_match_enc_opts enc_opts_match;
1865 struct mlx5_rep_uplink_priv *uplink_priv;
1866 struct mlx5e_rep_priv *uplink_rpriv;
1867 struct tunnel_match_key tunnel_key;
1868 bool enc_opts_is_dont_care = true;
1869 u32 tun_id, enc_opts_id = 0;
1870 struct mlx5_eswitch *esw;
1871 u32 value, mask;
8f256622 1872 int err;
2e72eb43 1873
0a7fcb78
PB		 1874 esw = priv->mdev->priv.eswitch;
1875 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1876 uplink_priv = &uplink_rpriv->uplink_priv;
1877
1878 memset(&tunnel_key, 0, sizeof(tunnel_key));
1879 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1880 &tunnel_key.enc_control);
1881 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1882 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1883 &tunnel_key.enc_ipv4);
1884 else
1885 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1886 &tunnel_key.enc_ipv6);
1887 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1888 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1889 &tunnel_key.enc_tp);
1890 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1891 &tunnel_key.enc_key_id);
1892 tunnel_key.filter_ifindex = filter_dev->ifindex;
1893
1894 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1895 if (err)
101f4de9 1896 return err;
bbd00f7e 1897
0a7fcb78
PB		 1898 flow_rule_match_enc_opts(rule, &enc_opts_match);
1899 err = enc_opts_is_dont_care_or_full_match(priv,
1900 enc_opts_match.mask,
1901 extack,
1902 &enc_opts_is_dont_care);
1903 if (err)
1904 goto err_enc_opts;
fe1587a7 1905
0a7fcb78
PB		 1906 if (!enc_opts_is_dont_care) {
1907 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
1908 enc_opts_match.key, &enc_opts_id);
1909 if (err)
1910 goto err_enc_opts;
1911 }
fe1587a7 1912
0a7fcb78
PB		 1913 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1914 mask = enc_opts_id ? TUNNEL_ID_MASK :
1915 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1916
0a7fcb78
PB		 1917 if (attr->chain) {
1918 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1919 TUNNEL_TO_REG, value, mask);
1920 } else {
1921 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1922 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1923 mod_hdr_acts,
1924 TUNNEL_TO_REG, value);
1925 if (err)
1926 goto err_set;
fe1587a7 1927
0a7fcb78 1928 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1929 }
bbd00f7e 1930
0a7fcb78
PB		 1931 flow->tunnel_id = value;
1932 return 0;
bcef735c 1933
0a7fcb78
PB		 1934err_set:
1935 if (enc_opts_id)
1936 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1937 enc_opts_id);
1938err_enc_opts:
1939 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1940 return err;
1941}
bcef735c 1942
0a7fcb78
PB		 1943static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1944{
1945 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1946 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1947 struct mlx5_rep_uplink_priv *uplink_priv;
1948 struct mlx5e_rep_priv *uplink_rpriv;
1949 struct mlx5_eswitch *esw;
bcef735c 1950
0a7fcb78
PB		 1951 esw = flow->priv->mdev->priv.eswitch;
1952 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1953 uplink_priv = &uplink_rpriv->uplink_priv;
1954
1955 if (tun_id)
1956 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1957 if (enc_opts_id)
1958 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1959 enc_opts_id);
1960}
e98bedf5 1961
4c3844d9
PB		 1962u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1963{
1964 return flow->tunnel_id;
1965}
1966
bbd00f7e 1967static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1968 struct mlx5e_tc_flow *flow,
bbd00f7e 1969 struct mlx5_flow_spec *spec,
f9e30088 1970 struct flow_cls_offload *f,
0a7fcb78
PB		 1971 struct net_device *filter_dev,
1972 u8 *match_level,
1973 bool *match_inner)
bbd00f7e 1974{
0a7fcb78 1975 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1976 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1977 bool needs_mapping, sets_mapping;
8f256622 1978 int err;
2e72eb43 1979
0a7fcb78
PB		 1980 if (!mlx5e_is_eswitch_flow(flow))
1981 return -EOPNOTSUPP;
1982
1983 needs_mapping = !!flow->esw_attr->chain;
1984 sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f);
1985 *match_inner = !needs_mapping;
1986
1987 if ((needs_mapping || sets_mapping) &&
636bb968 1988 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1989 NL_SET_ERR_MSG(extack,
636bb968 1990 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1991 netdev_warn(priv->netdev,
636bb968 1992 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1993 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1994 }
1995
0a7fcb78
PB		 1996 if (!flow->esw_attr->chain) {
1997 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1998 match_level);
1999 if (err) {
e98bedf5 2000 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2001 "Failed to parse tunnel attributes");
2002 netdev_warn(priv->netdev,
2003 "Failed to parse tunnel attributes");
2004 return err;
e98bedf5
EB		 2005 }
2006
0a7fcb78 2007 flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 2008 }
2009
0a7fcb78
PB		 2010 if (!needs_mapping && !sets_mapping)
2011 return 0;
bbd00f7e 2012
0a7fcb78 2013 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2014}
bbd00f7e 2015
0a7fcb78 2016static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2017{
0a7fcb78
PB		 2018 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2019 inner_headers);
bbd00f7e
HHZ		 2020}
2021
0a7fcb78 2022static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2023{
0a7fcb78
PB		 2024 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2025 inner_headers);
2026}
2027
2028static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2029{
2030 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2031 outer_headers);
2032}
2033
2034static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2035{
2036 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2037 outer_headers);
8377629e
EB		 2038}
2039
2040static void *get_match_headers_value(u32 flags,
2041 struct mlx5_flow_spec *spec)
2042{
2043 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2044 get_match_inner_headers_value(spec) :
2045 get_match_outer_headers_value(spec);
2046}
2047
2048static void *get_match_headers_criteria(u32 flags,
2049 struct mlx5_flow_spec *spec)
2050{
2051 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2052 get_match_inner_headers_criteria(spec) :
2053 get_match_outer_headers_criteria(spec);
8377629e
EB		 2054}
2055
6d65bc64 2056static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2057 struct flow_cls_offload *f)
2058{
2059 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2060 struct netlink_ext_ack *extack = f->common.extack;
2061 struct net_device *ingress_dev;
2062 struct flow_match_meta match;
2063
2064 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2065 return 0;
2066
2067 flow_rule_match_meta(rule, &match);
2068 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2069 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2070 return -EINVAL;
2071 }
2072
2073 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2074 match.key->ingress_ifindex);
2075 if (!ingress_dev) {
2076 NL_SET_ERR_MSG_MOD(extack,
2077 "Can't find the ingress port to match on");
2078 return -EINVAL;
2079 }
2080
2081 if (ingress_dev != filter_dev) {
2082 NL_SET_ERR_MSG_MOD(extack,
2083 "Can't match on the ingress filter port");
2084 return -EINVAL;
2085 }
2086
2087 return 0;
2088}
2089
de0af0bf 2090static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2091 struct mlx5e_tc_flow *flow,
de0af0bf 2092 struct mlx5_flow_spec *spec,
f9e30088 2093 struct flow_cls_offload *f,
54c177ca 2094 struct net_device *filter_dev,
93b3586e 2095 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2096{
e98bedf5 2097 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2098 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2099 outer_headers);
2100 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2101 outer_headers);
699e96dd
JL		 2102 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2103 misc_parameters);
2104 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2105 misc_parameters);
f9e30088 2106 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2107 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2108 u16 addr_type = 0;
2109 u8 ip_proto = 0;
93b3586e 2110 u8 *match_level;
6d65bc64 2111 int err;
e3a2b7ed 2112
93b3586e 2113 match_level = outer_match_level;
de0af0bf 2114
8f256622 2115 if (dissector->used_keys &
3d144578
VB		 2116 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2117 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2118 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2119 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2120 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2121 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2122 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2123 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2124 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2125 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2126 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2127 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2128 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2129 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2130 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2131 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2132 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df
YK		 2133 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
2134 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 2135 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 2136 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 2137 dissector->used_keys);
e3a2b7ed
AV		 2138 return -EOPNOTSUPP;
2139 }
2140
075973c7 2141 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2142 bool match_inner = false;
bbd00f7e 2143
0a7fcb78
PB		 2144 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2145 outer_match_level, &match_inner);
2146 if (err)
2147 return err;
2148
2149 if (match_inner) {
2150 /* header pointers should point to the inner headers
2151 * if the packet was decapsulated already.
2152 * outer headers are set by parse_tunnel_attr.
2153 */
2154 match_level = inner_match_level;
2155 headers_c = get_match_inner_headers_criteria(spec);
2156 headers_v = get_match_inner_headers_value(spec);
2157 }
bbd00f7e
HHZ		 2158 }
2159
6d65bc64 2160 err = mlx5e_flower_parse_meta(filter_dev, f);
2161 if (err)
2162 return err;
2163
8f256622
PNA		 2164 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2165 struct flow_match_basic match;
2166
2167 flow_rule_match_basic(rule, &match);
d3a80bb5 2168 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 2169 ntohs(match.mask->n_proto));
d3a80bb5 2170 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 2171 ntohs(match.key->n_proto));
e3a2b7ed 2172
8f256622 2173 if (match.mask->n_proto)
d708f902 2174 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2175 }
35a605db
EB		 2176 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2177 is_vlan_dev(filter_dev)) {
2178 struct flow_dissector_key_vlan filter_dev_mask;
2179 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2180 struct flow_match_vlan match;
2181
35a605db
EB		 2182 if (is_vlan_dev(filter_dev)) {
2183 match.key = &filter_dev_key;
2184 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2185 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2186 match.key->vlan_priority = 0;
2187 match.mask = &filter_dev_mask;
2188 memset(match.mask, 0xff, sizeof(*match.mask));
2189 match.mask->vlan_priority = 0;
2190 } else {
2191 flow_rule_match_vlan(rule, &match);
2192 }
8f256622
PNA		 2193 if (match.mask->vlan_id ||
2194 match.mask->vlan_priority ||
2195 match.mask->vlan_tpid) {
2196 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2197 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2198 svlan_tag, 1);
2199 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2200 svlan_tag, 1);
2201 } else {
2202 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2203 cvlan_tag, 1);
2204 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2205 cvlan_tag, 1);
2206 }
095b6cfd 2207
8f256622
PNA		 2208 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2209 match.mask->vlan_id);
2210 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2211 match.key->vlan_id);
358d79a4 2212
8f256622
PNA		 2213 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2214 match.mask->vlan_priority);
2215 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2216 match.key->vlan_priority);
54782900 2217
d708f902 2218 *match_level = MLX5_MATCH_L2;
54782900 2219 }
d3a80bb5 2220 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2221 /* cvlan_tag enabled in match criteria and
2222 * disabled in match value means both S & C tags
2223 * don't exist (untagged of both)
2224 */
cee26487 2225 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2226 *match_level = MLX5_MATCH_L2;
54782900
OG		 2227 }
2228
8f256622
PNA		 2229 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2230 struct flow_match_vlan match;
2231
12d5cbf8 2232 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2233 if (match.mask->vlan_id ||
2234 match.mask->vlan_priority ||
2235 match.mask->vlan_tpid) {
2236 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2237 MLX5_SET(fte_match_set_misc, misc_c,
2238 outer_second_svlan_tag, 1);
2239 MLX5_SET(fte_match_set_misc, misc_v,
2240 outer_second_svlan_tag, 1);
2241 } else {
2242 MLX5_SET(fte_match_set_misc, misc_c,
2243 outer_second_cvlan_tag, 1);
2244 MLX5_SET(fte_match_set_misc, misc_v,
2245 outer_second_cvlan_tag, 1);
2246 }
2247
2248 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2249 match.mask->vlan_id);
699e96dd 2250 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2251 match.key->vlan_id);
699e96dd 2252 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2253 match.mask->vlan_priority);
699e96dd 2254 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2255 match.key->vlan_priority);
699e96dd
JL		 2256
2257 *match_level = MLX5_MATCH_L2;
2258 }
2259 }
2260
8f256622
PNA		 2261 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2262 struct flow_match_eth_addrs match;
54782900 2263
8f256622 2264 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2265 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2266 dmac_47_16),
8f256622 2267 match.mask->dst);
d3a80bb5
OG		 2268 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2269 dmac_47_16),
8f256622 2270 match.key->dst);
d3a80bb5
OG		 2271
2272 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2273 smac_47_16),
8f256622 2274 match.mask->src);
d3a80bb5
OG		 2275 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2276 smac_47_16),
8f256622 2277 match.key->src);
d3a80bb5 2278
8f256622
PNA		 2279 if (!is_zero_ether_addr(match.mask->src) ||
2280 !is_zero_ether_addr(match.mask->dst))
d708f902 2281 *match_level = MLX5_MATCH_L2;
54782900
OG		 2282 }
2283
8f256622
PNA		 2284 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2285 struct flow_match_control match;
54782900 2286
8f256622
PNA		 2287 flow_rule_match_control(rule, &match);
2288 addr_type = match.key->addr_type;
54782900
OG		 2289
2290 /* the HW doesn't support frag first/later */
8f256622 2291 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2292 return -EOPNOTSUPP;
2293
8f256622 2294 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2295 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2296 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2297 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2298
2299 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2300 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2301 *match_level = MLX5_MATCH_L2;
54782900
OG		 2302 /* *** L2 attributes parsing up to here *** */
2303 else
83621b7d 2304 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2305 }
2306 }
2307
8f256622
PNA		 2308 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2309 struct flow_match_basic match;
2310
2311 flow_rule_match_basic(rule, &match);
2312 ip_proto = match.key->ip_proto;
54782900
OG		 2313
2314 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2315 match.mask->ip_proto);
54782900 2316 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2317 match.key->ip_proto);
54782900 2318
8f256622 2319 if (match.mask->ip_proto)
d708f902 2320 *match_level = MLX5_MATCH_L3;
54782900
OG		 2321 }
2322
e3a2b7ed 2323 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2324 struct flow_match_ipv4_addrs match;
e3a2b7ed 2325
8f256622 2326 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2327 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2328 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2329 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2330 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2331 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2332 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2333 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2334 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2335 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2336 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2337 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2338 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2339
8f256622 2340 if (match.mask->src || match.mask->dst)
d708f902 2341 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2342 }
2343
2344 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2345 struct flow_match_ipv6_addrs match;
e3a2b7ed 2346
8f256622 2347 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2348 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2349 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2350 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2351 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2352 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2353 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2354
2355 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2356 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2357 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2358 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2359 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2360 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2361
8f256622
PNA		 2362 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2363 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2364 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2365 }
2366
8f256622
PNA		 2367 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2368 struct flow_match_ip match;
1f97a526 2369
8f256622
PNA		 2370 flow_rule_match_ip(rule, &match);
2371 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2372 match.mask->tos & 0x3);
2373 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2374 match.key->tos & 0x3);
1f97a526 2375
8f256622
PNA		 2376 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2377 match.mask->tos >> 2);
2378 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2379 match.key->tos >> 2);
1f97a526 2380
8f256622
PNA		 2381 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2382 match.mask->ttl);
2383 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2384 match.key->ttl);
1f97a526 2385
8f256622 2386 if (match.mask->ttl &&
a8ade55f 2387 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2388 ft_field_support.outer_ipv4_ttl)) {
2389 NL_SET_ERR_MSG_MOD(extack,
2390 "Matching on TTL is not supported");
1f97a526 2391 return -EOPNOTSUPP;
e98bedf5 2392 }
a8ade55f 2393
8f256622 2394 if (match.mask->tos || match.mask->ttl)
d708f902 2395 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2396 }
2397
54782900
OG		 2398 /* *** L3 attributes parsing up to here *** */
2399
8f256622
PNA		 2400 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2401 struct flow_match_ports match;
2402
2403 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2404 switch (ip_proto) {
2405 case IPPROTO_TCP:
2406 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2407 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2408 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2409 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2410
2411 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2412 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2413 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2414 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2415 break;
2416
2417 case IPPROTO_UDP:
2418 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2419 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2420 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2421 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2422
2423 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2424 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2425 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2426 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2427 break;
2428 default:
e98bedf5
EB		 2429 NL_SET_ERR_MSG_MOD(extack,
2430 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2431 netdev_err(priv->netdev,
2432 "Only UDP and TCP transport are supported\n");
2433 return -EINVAL;
2434 }
de0af0bf 2435
8f256622 2436 if (match.mask->src || match.mask->dst)
d708f902 2437 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2438 }
2439
8f256622
PNA		 2440 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2441 struct flow_match_tcp match;
e77834ec 2442
8f256622 2443 flow_rule_match_tcp(rule, &match);
e77834ec 2444 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2445 ntohs(match.mask->flags));
e77834ec 2446 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2447 ntohs(match.key->flags));
e77834ec 2448
8f256622 2449 if (match.mask->flags)
d708f902 2450 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2451 }
2452
e3a2b7ed
AV		 2453 return 0;
2454}
2455
de0af0bf 2456static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2457 struct mlx5e_tc_flow *flow,
de0af0bf 2458 struct mlx5_flow_spec *spec,
f9e30088 2459 struct flow_cls_offload *f,
54c177ca 2460 struct net_device *filter_dev)
de0af0bf 2461{
93b3586e 2462 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2463 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2464 struct mlx5_core_dev *dev = priv->mdev;
2465 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2466 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2467 struct mlx5_eswitch_rep *rep;
226f2ca3 2468 bool is_eswitch_flow;
de0af0bf
RD		 2469 int err;
2470
93b3586e
HN		 2471 inner_match_level = MLX5_MATCH_NONE;
2472 outer_match_level = MLX5_MATCH_NONE;
2473
0a7fcb78
PB		 2474 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2475 &inner_match_level, &outer_match_level);
93b3586e
HN		 2476 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2477 outer_match_level : inner_match_level;
de0af0bf 2478
226f2ca3
VB		 2479 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2480 if (!err && is_eswitch_flow) {
1d447a39 2481 rep = rpriv->rep;
b05af6aa 2482 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2483 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2484 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2485 NL_SET_ERR_MSG_MOD(extack,
2486 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2487 netdev_warn(priv->netdev,
2488 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2489 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2490 return -EOPNOTSUPP;
2491 }
2492 }
2493
226f2ca3 2494 if (is_eswitch_flow) {
93b3586e
HN		 2495 flow->esw_attr->inner_match_level = inner_match_level;
2496 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2497 } else {
93b3586e 2498 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2499 }
38aa51c1 2500
de0af0bf
RD		 2501 return err;
2502}
2503
d79b6df6
OG		 2504struct pedit_headers {
2505 struct ethhdr eth;
0eb69bb9 2506 struct vlan_hdr vlan;
d79b6df6
OG		 2507 struct iphdr ip4;
2508 struct ipv6hdr ip6;
2509 struct tcphdr tcp;
2510 struct udphdr udp;
2511};
2512
c500c86b
PNA		 2513struct pedit_headers_action {
2514 struct pedit_headers vals;
2515 struct pedit_headers masks;
2516 u32 pedits;
2517};
2518
d79b6df6 2519static int pedit_header_offsets[] = {
73867881
PNA		 2520 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2521 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2522 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2523 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2524 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2525};
2526
2527#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2528
2529static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2530 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2531{
2532 u32 *curr_pmask, *curr_pval;
2533
c500c86b
PNA		 2534 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2535 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2536
2537 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2538 goto out_err;
2539
2540 *curr_pmask |= mask;
2541 *curr_pval |= (val & mask);
2542
2543 return 0;
2544
2545out_err:
2546 return -EOPNOTSUPP;
2547}
2548
2549struct mlx5_fields {
2550 u8 field;
88f30bbc
DL		 2551 u8 field_bsize;
2552 u32 field_mask;
d79b6df6 2553 u32 offset;
27c11b6b 2554 u32 match_offset;
d79b6df6
OG		 2555};
2556
88f30bbc
DL		 2557#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2558 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2559 offsetof(struct pedit_headers, field) + (off), \
2560 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2561
2ef86872
EB		 2562/* masked values are the same and there are no rewrites that do not have a
2563 * match.
2564 */
2565#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2566 type matchmaskx = *(type *)(matchmaskp); \
2567 type matchvalx = *(type *)(matchvalp); \
2568 type maskx = *(type *)(maskp); \
2569 type valx = *(type *)(valp); \
2570 \
2571 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2572 matchmaskx)); \
2573})
2574
27c11b6b 2575static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2576 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2577{
2578 bool same = false;
2579
88f30bbc
DL		 2580 switch (bsize) {
2581 case 8:
2ef86872 2582 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2583 break;
88f30bbc 2584 case 16:
2ef86872 2585 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2586 break;
88f30bbc 2587 case 32:
2ef86872 2588 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2589 break;
2590 }
2591
2592 return same;
2593}
a8e4f0c4 2594
d79b6df6 2595static struct mlx5_fields fields[] = {
88f30bbc
DL		 2596 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2597 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2598 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2599 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2600 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2601 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2602
ab9341b5 2603 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2604 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2605 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2606 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2607
2608 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2609 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2610 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2611 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2612 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2613 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2614 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2615 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2616 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2617 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2618 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2619 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2620 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2621 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2622 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2623 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2624 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
27c11b6b 2625
88f30bbc
DL		 2626 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2627 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2628 /* in linux iphdr tcp_flags is 8 bits long */
2629 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2630
88f30bbc
DL		 2631 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2632 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2633};
2634
6ae4a6a5
PB		 2635static int offload_pedit_fields(struct mlx5e_priv *priv,
2636 int namespace,
2637 struct pedit_headers_action *hdrs,
e98bedf5 2638 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2639 u32 *action_flags,
e98bedf5 2640 struct netlink_ext_ack *extack)
d79b6df6
OG		 2641{
2642 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2643 int i, action_size, first, last, next_z;
88f30bbc
DL		 2644 void *headers_c, *headers_v, *action, *vals_p;
2645 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2646 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2647 struct mlx5_fields *f;
d79b6df6 2648 unsigned long mask;
2b64beba
OG		 2649 __be32 mask_be32;
2650 __be16 mask_be16;
6ae4a6a5 2651 int err;
88f30bbc
DL		 2652 u8 cmd;
2653
6ae4a6a5 2654 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2655 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2656 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2657
73867881
PNA		 2658 set_masks = &hdrs[0].masks;
2659 add_masks = &hdrs[1].masks;
2660 set_vals = &hdrs[0].vals;
2661 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2662
2663 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
d79b6df6
OG		 2664
2665 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2666 bool skip;
2667
d79b6df6
OG		 2668 f = &fields[i];
2669 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2670 s_mask = 0;
2671 a_mask = 0;
d79b6df6
OG		 2672
2673 s_masks_p = (void *)set_masks + f->offset;
2674 a_masks_p = (void *)add_masks + f->offset;
2675
88f30bbc
DL		 2676 s_mask = *s_masks_p & f->field_mask;
2677 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2678
2679 if (!s_mask && !a_mask) /* nothing to offload here */
2680 continue;
2681
2682 if (s_mask && a_mask) {
e98bedf5
EB		 2683 NL_SET_ERR_MSG_MOD(extack,
2684 "can't set and add to the same HW field");
d79b6df6
OG		 2685 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2686 return -EOPNOTSUPP;
2687 }
2688
27c11b6b 2689 skip = false;
d79b6df6 2690 if (s_mask) {
27c11b6b
EB		 2691 void *match_mask = headers_c + f->match_offset;
2692 void *match_val = headers_v + f->match_offset;
2693
d79b6df6
OG		 2694 cmd = MLX5_ACTION_TYPE_SET;
2695 mask = s_mask;
2696 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2697 /* don't rewrite if we have a match on the same value */
2698 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2699 match_mask, f->field_bsize))
27c11b6b 2700 skip = true;
d79b6df6 2701 /* clear to denote we consumed this field */
88f30bbc 2702 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2703 } else {
2704 cmd = MLX5_ACTION_TYPE_ADD;
2705 mask = a_mask;
2706 vals_p = (void *)add_vals + f->offset;
27c11b6b 2707 /* add 0 is no change */
88f30bbc 2708 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2709 skip = true;
d79b6df6 2710 /* clear to denote we consumed this field */
88f30bbc 2711 *a_masks_p &= ~f->field_mask;
d79b6df6 2712 }
27c11b6b
EB		 2713 if (skip)
2714 continue;
d79b6df6 2715
88f30bbc 2716 if (f->field_bsize == 32) {
404402ab 2717 mask_be32 = (__be32)mask;
2b64beba 2718 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
88f30bbc 2719 } else if (f->field_bsize == 16) {
404402ab
SH		 2720 mask_be32 = (__be32)mask;
2721 mask_be16 = *(__be16 *)&mask_be32;
2b64beba
OG		 2722 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2723 }
2724
88f30bbc
DL		 2725 first = find_first_bit(&mask, f->field_bsize);
2726 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2727 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2728 if (first < next_z && next_z < last) {
e98bedf5
EB		 2729 NL_SET_ERR_MSG_MOD(extack,
2730 "rewrite of few sub-fields isn't supported");
2b64beba 2731 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2732 mask);
2733 return -EOPNOTSUPP;
2734 }
2735
6ae4a6a5
PB		 2736 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2737 if (err) {
2738 NL_SET_ERR_MSG_MOD(extack,
2739 "too many pedit actions, can't offload");
2740 mlx5_core_warn(priv->mdev,
2741 "mlx5: parsed %d pedit actions, can't do more\n",
2742 mod_acts->num_actions);
2743 return err;
2744 }
2745
2746 action = mod_acts->actions +
2747 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2748 MLX5_SET(set_action_in, action, action_type, cmd);
2749 MLX5_SET(set_action_in, action, field, f->field);
2750
2751 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2752 int start;
2753
2754 /* if field is bit sized it can start not from first bit */
2755 start = find_first_bit((unsigned long *)&f->field_mask,
2756 f->field_bsize);
2757
2758 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2759 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2760 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2761 }
2762
88f30bbc 2763 if (f->field_bsize == 32)
2b64beba 2764 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2765 else if (f->field_bsize == 16)
2b64beba 2766 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2767 else if (f->field_bsize == 8)
2b64beba 2768 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2769
6ae4a6a5 2770 ++mod_acts->num_actions;
d79b6df6
OG		 2771 }
2772
d79b6df6
OG		 2773 return 0;
2774}
2775
2cc1cb1d
TZ		 2776static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2777 int namespace)
2778{
2779 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2780 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2781 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2782 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2783}
2784
6ae4a6a5
PB		 2785int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2786 int namespace,
2787 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2788{
6ae4a6a5
PB		 2789 int action_size, new_num_actions, max_hw_actions;
2790 size_t new_sz, old_sz;
2791 void *ret;
d79b6df6 2792
6ae4a6a5
PB		 2793 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2794 return 0;
d79b6df6 2795
6ae4a6a5 2796 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
d79b6df6 2797
6ae4a6a5
PB		 2798 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2799 namespace);
2800 new_num_actions = min(max_hw_actions,
2801 mod_hdr_acts->actions ?
2802 mod_hdr_acts->max_actions * 2 : 1);
2803 if (mod_hdr_acts->max_actions == new_num_actions)
2804 return -ENOSPC;
2805
2806 new_sz = action_size * new_num_actions;
2807 old_sz = mod_hdr_acts->max_actions * action_size;
2808 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2809 if (!ret)
d79b6df6
OG		 2810 return -ENOMEM;
2811
6ae4a6a5
PB		 2812 memset(ret + old_sz, 0, new_sz - old_sz);
2813 mod_hdr_acts->actions = ret;
2814 mod_hdr_acts->max_actions = new_num_actions;
2815
d79b6df6
OG		 2816 return 0;
2817}
2818
6ae4a6a5
PB		 2819void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2820{
2821 kfree(mod_hdr_acts->actions);
2822 mod_hdr_acts->actions = NULL;
2823 mod_hdr_acts->num_actions = 0;
2824 mod_hdr_acts->max_actions = 0;
2825}
2826
d79b6df6
OG		 2827static const struct pedit_headers zero_masks = {};
2828
2829static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2830 const struct flow_action_entry *act, int namespace,
c500c86b 2831 struct pedit_headers_action *hdrs,
e98bedf5 2832 struct netlink_ext_ack *extack)
d79b6df6 2833{
73867881
PNA		 2834 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2835 int err = -EOPNOTSUPP;
d79b6df6 2836 u32 mask, val, offset;
73867881 2837 u8 htype;
d79b6df6 2838
73867881
PNA		 2839 htype = act->mangle.htype;
2840 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2841
73867881
PNA		 2842 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2843 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2844 goto out_err;
2845 }
d79b6df6 2846
2cc1cb1d
TZ		 2847 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2848 NL_SET_ERR_MSG_MOD(extack,
2849 "The pedit offload action is not supported");
2850 goto out_err;
2851 }
2852
73867881
PNA		 2853 mask = act->mangle.mask;
2854 val = act->mangle.val;
2855 offset = act->mangle.offset;
d79b6df6 2856
73867881
PNA		 2857 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2858 if (err)
2859 goto out_err;
c500c86b 2860
73867881 2861 hdrs[cmd].pedits++;
d79b6df6 2862
c500c86b
PNA		 2863 return 0;
2864out_err:
2865 return err;
2866}
2867
2868static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2869 struct mlx5e_tc_flow_parse_attr *parse_attr,
2870 struct pedit_headers_action *hdrs,
27c11b6b 2871 u32 *action_flags,
c500c86b
PNA		 2872 struct netlink_ext_ack *extack)
2873{
2874 struct pedit_headers *cmd_masks;
2875 int err;
2876 u8 cmd;
2877
6ae4a6a5
PB		 2878 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2879 action_flags, extack);
d79b6df6
OG		 2880 if (err < 0)
2881 goto out_dealloc_parsed_actions;
2882
2883 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2884 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2885 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2886 NL_SET_ERR_MSG_MOD(extack,
2887 "attempt to offload an unsupported field");
b3a433de 2888 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2889 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2890 16, 1, cmd_masks, sizeof(zero_masks), true);
2891 err = -EOPNOTSUPP;
2892 goto out_dealloc_parsed_actions;
2893 }
2894 }
2895
2896 return 0;
2897
2898out_dealloc_parsed_actions:
6ae4a6a5 2899 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2900 return err;
2901}
2902
e98bedf5
EB		 2903static bool csum_offload_supported(struct mlx5e_priv *priv,
2904 u32 action,
2905 u32 update_flags,
2906 struct netlink_ext_ack *extack)
26c02749
OG		 2907{
2908 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2909 TCA_CSUM_UPDATE_FLAG_UDP;
2910
2911 /* The HW recalcs checksums only if re-writing headers */
2912 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2913 NL_SET_ERR_MSG_MOD(extack,
2914 "TC csum action is only offloaded with pedit");
26c02749
OG		 2915 netdev_warn(priv->netdev,
2916 "TC csum action is only offloaded with pedit\n");
2917 return false;
2918 }
2919
2920 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2921 NL_SET_ERR_MSG_MOD(extack,
2922 "can't offload TC csum action for some header/s");
26c02749
OG		 2923 netdev_warn(priv->netdev,
2924 "can't offload TC csum action for some header/s - flags %#x\n",
2925 update_flags);
2926 return false;
2927 }
2928
2929 return true;
2930}
2931
8998576b
DL		 2932struct ip_ttl_word {
2933 __u8 ttl;
2934 __u8 protocol;
2935 __sum16 check;
2936};
2937
2938struct ipv6_hoplimit_word {
2939 __be16 payload_len;
2940 __u8 nexthdr;
2941 __u8 hop_limit;
2942};
2943
4c3844d9
PB		 2944static int is_action_keys_supported(const struct flow_action_entry *act,
2945 bool ct_flow, bool *modify_ip_header,
2946 struct netlink_ext_ack *extack)
8998576b
DL		 2947{
2948 u32 mask, offset;
2949 u8 htype;
2950
2951 htype = act->mangle.htype;
2952 offset = act->mangle.offset;
2953 mask = ~act->mangle.mask;
2954 /* For IPv4 & IPv6 header check 4 byte word,
2955 * to determine that modified fields
2956 * are NOT ttl & hop_limit only.
2957 */
2958 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2959 struct ip_ttl_word *ttl_word =
2960 (struct ip_ttl_word *)&mask;
2961
2962 if (offset != offsetof(struct iphdr, ttl) ||
2963 ttl_word->protocol ||
2964 ttl_word->check) {
4c3844d9
PB		 2965 *modify_ip_header = true;
2966 }
2967
2968 if (ct_flow && offset >= offsetof(struct iphdr, saddr)) {
2969 NL_SET_ERR_MSG_MOD(extack,
2970 "can't offload re-write of ipv4 address with action ct");
2971 return -EOPNOTSUPP;
8998576b
DL		 2972 }
2973 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2974 struct ipv6_hoplimit_word *hoplimit_word =
2975 (struct ipv6_hoplimit_word *)&mask;
2976
2977 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2978 hoplimit_word->payload_len ||
2979 hoplimit_word->nexthdr) {
4c3844d9
PB		 2980 *modify_ip_header = true;
2981 }
2982
2983 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr)) {
2984 NL_SET_ERR_MSG_MOD(extack,
2985 "can't offload re-write of ipv6 address with action ct");
2986 return -EOPNOTSUPP;
8998576b 2987 }
4c3844d9
PB		 2988 } else if (ct_flow && (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2989 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP)) {
2990 NL_SET_ERR_MSG_MOD(extack,
2991 "can't offload re-write of transport header ports with action ct");
2992 return -EOPNOTSUPP;
8998576b 2993 }
4c3844d9
PB		 2994
2995 return 0;
8998576b
DL		 2996}
2997
bdd66ac0 2998static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2999 struct flow_action *flow_action,
4c3844d9 3000 u32 actions, bool ct_flow,
e98bedf5 3001 struct netlink_ext_ack *extack)
bdd66ac0 3002{
73867881 3003 const struct flow_action_entry *act;
bdd66ac0 3004 bool modify_ip_header;
bdd66ac0
OG		 3005 void *headers_v;
3006 u16 ethertype;
8998576b 3007 u8 ip_proto;
4c3844d9 3008 int i, err;
bdd66ac0 3009
8377629e 3010 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3011 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3012
3013 /* for non-IP we only re-write MACs, so we're okay */
3014 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3015 goto out_ok;
3016
3017 modify_ip_header = false;
73867881
PNA		 3018 flow_action_for_each(i, act, flow_action) {
3019 if (act->id != FLOW_ACTION_MANGLE &&
3020 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3021 continue;
3022
4c3844d9
PB		 3023 err = is_action_keys_supported(act, ct_flow,
3024 &modify_ip_header, extack);
3025 if (err)
3026 return err;
bdd66ac0
OG		 3027 }
3028
3029 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3030 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3031 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3032 NL_SET_ERR_MSG_MOD(extack,
3033 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 3034 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
3035 return false;
3036 }
3037
3038out_ok:
3039 return true;
3040}
3041
3042static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3043 struct flow_action *flow_action,
bdd66ac0 3044 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3045 struct mlx5e_tc_flow *flow,
3046 struct netlink_ext_ack *extack)
bdd66ac0 3047{
d0645b37 3048 bool ct_flow;
bdd66ac0
OG		 3049 u32 actions;
3050
4c3844d9
PB		 3051 ct_flow = flow_flag_test(flow, CT);
3052 if (mlx5e_is_eswitch_flow(flow)) {
bdd66ac0 3053 actions = flow->esw_attr->action;
4c3844d9
PB		 3054
3055 if (flow->esw_attr->split_count && ct_flow) {
3056 /* All registers used by ct are cleared when using
3057 * split rules.
3058 */
3059 NL_SET_ERR_MSG_MOD(extack,
3060 "Can't offload mirroring with action ct");
49397b80 3061 return false;
4c3844d9
PB		 3062 }
3063 } else {
bdd66ac0 3064 actions = flow->nic_attr->action;
4c3844d9 3065 }
bdd66ac0
OG		 3066
3067 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 3068 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 3069 flow_action, actions,
4c3844d9 3070 ct_flow, extack);
bdd66ac0
OG		 3071
3072 return true;
3073}
3074
5c65c564
OG		 3075static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3076{
3077 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3078 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3079
3080 fmdev = priv->mdev;
3081 pmdev = peer_priv->mdev;
3082
59c9d35e
AH		 3083 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3084 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3085
816f6706 3086 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3087}
3088
bdc837ee
EB		 3089static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3090 const struct flow_action_entry *act,
3091 struct mlx5e_tc_flow_parse_attr *parse_attr,
3092 struct pedit_headers_action *hdrs,
3093 u32 *action, struct netlink_ext_ack *extack)
3094{
3095 u16 mask16 = VLAN_VID_MASK;
3096 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3097 const struct flow_action_entry pedit_act = {
3098 .id = FLOW_ACTION_MANGLE,
3099 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3100 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3101 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3102 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3103 };
6fca9d1e 3104 u8 match_prio_mask, match_prio_val;
bf2f3bca 3105 void *headers_c, *headers_v;
bdc837ee
EB		 3106 int err;
3107
bf2f3bca
EB		 3108 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3109 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3110
3111 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3112 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3113 NL_SET_ERR_MSG_MOD(extack,
3114 "VLAN rewrite action must have VLAN protocol match");
3115 return -EOPNOTSUPP;
3116 }
3117
6fca9d1e
EB		 3118 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3119 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3120 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3121 NL_SET_ERR_MSG_MOD(extack,
3122 "Changing VLAN prio is not supported");
bdc837ee
EB		 3123 return -EOPNOTSUPP;
3124 }
3125
dec481c8 3126 err = parse_tc_pedit_action(priv, &pedit_act, namespace, hdrs, NULL);
bdc837ee
EB		 3127 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3128
3129 return err;
3130}
3131
0bac1194
EB		 3132static int
3133add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3134 struct mlx5e_tc_flow_parse_attr *parse_attr,
3135 struct pedit_headers_action *hdrs,
3136 u32 *action, struct netlink_ext_ack *extack)
3137{
3138 const struct flow_action_entry prio_tag_act = {
3139 .vlan.vid = 0,
3140 .vlan.prio =
3141 MLX5_GET(fte_match_set_lyr_2_4,
3142 get_match_headers_value(*action,
3143 &parse_attr->spec),
3144 first_prio) &
3145 MLX5_GET(fte_match_set_lyr_2_4,
3146 get_match_headers_criteria(*action,
3147 &parse_attr->spec),
3148 first_prio),
3149 };
3150
3151 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3152 &prio_tag_act, parse_attr, hdrs, action,
3153 extack);
3154}
3155
73867881
PNA		 3156static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3157 struct flow_action *flow_action,
aa0cbbae 3158 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3159 struct mlx5e_tc_flow *flow,
3160 struct netlink_ext_ack *extack)
e3a2b7ed 3161{
aa0cbbae 3162 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 3163 struct pedit_headers_action hdrs[2] = {};
3164 const struct flow_action_entry *act;
1cab1cd7 3165 u32 action = 0;
244cd96a 3166 int err, i;
e3a2b7ed 3167
73867881 3168 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3169 return -EINVAL;
3170
53eca1f3
JK		 3171 if (!flow_action_hw_stats_check(flow_action, extack,
3172 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3173 return -EOPNOTSUPP;
3174
3bc4b7bf 3175 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3176
73867881
PNA		 3177 flow_action_for_each(i, act, flow_action) {
3178 switch (act->id) {
15fc92ec
TZ		 3179 case FLOW_ACTION_ACCEPT:
3180 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3181 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3182 break;
73867881 3183 case FLOW_ACTION_DROP:
1cab1cd7 3184 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3185 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3186 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3187 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3188 break;
3189 case FLOW_ACTION_MANGLE:
3190 case FLOW_ACTION_ADD:
3191 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
dec481c8 3192 hdrs, extack);
2f4fe4ca
OG		 3193 if (err)
3194 return err;
3195
1cab1cd7
OG		 3196 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
3197 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 3198 break;
bdc837ee
EB		 3199 case FLOW_ACTION_VLAN_MANGLE:
3200 err = add_vlan_rewrite_action(priv,
3201 MLX5_FLOW_NAMESPACE_KERNEL,
3202 act, parse_attr, hdrs,
3203 &action, extack);
3204 if (err)
3205 return err;
3206
3207 break;
73867881 3208 case FLOW_ACTION_CSUM:
1cab1cd7 3209 if (csum_offload_supported(priv, action,
73867881 3210 act->csum_flags,
e98bedf5 3211 extack))
73867881 3212 break;
26c02749
OG		 3213
3214 return -EOPNOTSUPP;
73867881
PNA		 3215 case FLOW_ACTION_REDIRECT: {
3216 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3217
3218 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3219 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3220 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3221 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3222 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3223 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3224 } else {
e98bedf5
EB		 3225 NL_SET_ERR_MSG_MOD(extack,
3226 "device is not on same HW, can't offload");
5c65c564
OG		 3227 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3228 peer_dev->name);
3229 return -EINVAL;
3230 }
73867881
PNA		 3231 }
3232 break;
3233 case FLOW_ACTION_MARK: {
3234 u32 mark = act->mark;
e3a2b7ed
AV		 3235
3236 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3237 NL_SET_ERR_MSG_MOD(extack,
3238 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3239 return -EINVAL;
3240 }
3241
3bc4b7bf 3242 attr->flow_tag = mark;
1cab1cd7 3243 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3244 }
3245 break;
3246 default:
2cc1cb1d
TZ		 3247 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3248 return -EOPNOTSUPP;
e3a2b7ed 3249 }
e3a2b7ed
AV		 3250 }
3251
c500c86b
PNA		 3252 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3253 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3254 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3255 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3256 if (err)
3257 return err;
27c11b6b
EB		 3258 /* in case all pedit actions are skipped, remove the MOD_HDR
3259 * flag.
3260 */
6ae4a6a5 3261 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3262 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3263 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3264 }
c500c86b
PNA		 3265 }
3266
1cab1cd7 3267 attr->action = action;
73867881 3268 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3269 return -EOPNOTSUPP;
3270
e3a2b7ed
AV		 3271 return 0;
3272}
3273
7f1a546e 3274struct encap_key {
1f6da306 3275 const struct ip_tunnel_key *ip_tun_key;
d386939a 3276 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3277};
3278
3279static inline int cmp_encap_info(struct encap_key *a,
3280 struct encap_key *b)
a54e20b4 3281{
7f1a546e 3282 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3283 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3284}
3285
7f1a546e 3286static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3287{
7f1a546e 3288 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3289 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3290}
3291
a54e20b4 3292
b1d90e6b
RL		 3293static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3294 struct net_device *peer_netdev)
3295{
3296 struct mlx5e_priv *peer_priv;
3297
3298 peer_priv = netdev_priv(peer_netdev);
3299
3300 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 3301 mlx5e_eswitch_rep(priv->netdev) &&
3302 mlx5e_eswitch_rep(peer_netdev) &&
3303 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3304}
3305
32f3671f 3306
f5bc2c5d 3307
948993f2
VB		 3308bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3309{
3310 return refcount_inc_not_zero(&e->refcnt);
3311}
3312
3313static struct mlx5e_encap_entry *
3314mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3315 uintptr_t hash_key)
3316{
3317 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3318 struct mlx5e_encap_entry *e;
3319 struct encap_key e_key;
3320
3321 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3322 encap_hlist, hash_key) {
3323 e_key.ip_tun_key = &e->tun_info->key;
3324 e_key.tc_tunnel = e->tunnel;
3325 if (!cmp_encap_info(&e_key, key) &&
3326 mlx5e_encap_take(e))
3327 return e;
3328 }
3329
3330 return NULL;
3331}
3332
2a4b6526
VB		 3333static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3334{
3335 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3336
3337 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3338}
3339
554fe75c
DL		 3340static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3341 struct mlx5e_tc_flow *flow,
3342 int out_index,
3343 struct mlx5e_encap_entry *e,
3344 struct netlink_ext_ack *extack)
3345{
3346 int i;
3347
3348 for (i = 0; i < out_index; i++) {
3349 if (flow->encaps[i].e != e)
3350 continue;
3351 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3352 netdev_err(priv->netdev, "can't duplicate encap action\n");
3353 return true;
3354 }
3355
3356 return false;
3357}
3358
a54e20b4 3359static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3360 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3361 struct net_device *mirred_dev,
3362 int out_index,
8c4dc42b 3363 struct netlink_ext_ack *extack,
0ad060ee
RD		 3364 struct net_device **encap_dev,
3365 bool *encap_valid)
a54e20b4
HHZ		 3366{
3367 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3368 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3369 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3370 const struct ip_tunnel_info *tun_info;
948993f2 3371 struct encap_key key;
c1ae1152 3372 struct mlx5e_encap_entry *e;
733d4f36 3373 unsigned short family;
a54e20b4 3374 uintptr_t hash_key;
54c177ca 3375 int err = 0;
a54e20b4 3376
733d4f36 3377 parse_attr = attr->parse_attr;
1f6da306 3378 tun_info = parse_attr->tun_info[out_index];
733d4f36 3379 family = ip_tunnel_info_af(tun_info);
7f1a546e 3380 key.ip_tun_key = &tun_info->key;
d386939a 3381 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3382 if (!key.tc_tunnel) {
3383 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3384 return -EOPNOTSUPP;
3385 }
733d4f36 3386
7f1a546e 3387 hash_key = hash_encap_info(&key);
a54e20b4 3388
61086f39 3389 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3390 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3391
b2812089 3392 /* must verify if encap is valid or not */
d589e785 3393 if (e) {
554fe75c
DL		 3394 /* Check that entry was not already attached to this flow */
3395 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3396 err = -EOPNOTSUPP;
3397 goto out_err;
3398 }
3399
d589e785
VB		 3400 mutex_unlock(&esw->offloads.encap_tbl_lock);
3401 wait_for_completion(&e->res_ready);
3402
3403 /* Protect against concurrent neigh update. */
3404 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3405 if (e->compl_result < 0) {
d589e785
VB		 3406 err = -EREMOTEIO;
3407 goto out_err;
3408 }
45247bf2 3409 goto attach_flow;
d589e785 3410 }
a54e20b4
HHZ		 3411
3412 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3413 if (!e) {
3414 err = -ENOMEM;
3415 goto out_err;
3416 }
a54e20b4 3417
948993f2 3418 refcount_set(&e->refcnt, 1);
d589e785
VB		 3419 init_completion(&e->res_ready);
3420
2a4b6526
VB		 3421 tun_info = dup_tun_info(tun_info);
3422 if (!tun_info) {
3423 err = -ENOMEM;
3424 goto out_err_init;
3425 }
1f6da306 3426 e->tun_info = tun_info;
101f4de9 3427 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3428 if (err)
3429 goto out_err_init;
54c177ca 3430
a54e20b4 3431 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3432 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3433 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3434
ce99f6b9 3435 if (family == AF_INET)
101f4de9 3436 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3437 else if (family == AF_INET6)
101f4de9 3438 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3439
d589e785
VB		 3440 /* Protect against concurrent neigh update. */
3441 mutex_lock(&esw->offloads.encap_tbl_lock);
3442 complete_all(&e->res_ready);
3443 if (err) {
3444 e->compl_result = err;
a54e20b4 3445 goto out_err;
d589e785 3446 }
3c140dd5 3447 e->compl_result = 1;
a54e20b4 3448
45247bf2 3449attach_flow:
948993f2 3450 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3451 list_add(&flow->encaps[out_index].list, &e->flows);
3452 flow->encaps[out_index].index = out_index;
45247bf2 3453 *encap_dev = e->out_dev;
8c4dc42b 3454 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3455 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3456 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3457 *encap_valid = true;
8c4dc42b 3458 } else {
0ad060ee 3459 *encap_valid = false;
8c4dc42b 3460 }
61086f39 3461 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3462
232c0013 3463 return err;
a54e20b4
HHZ		 3464
3465out_err:
61086f39 3466 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3467 if (e)
3468 mlx5e_encap_put(priv, e);
a54e20b4 3469 return err;
2a4b6526
VB		 3470
3471out_err_init:
3472 mutex_unlock(&esw->offloads.encap_tbl_lock);
3473 kfree(tun_info);
3474 kfree(e);
3475 return err;
a54e20b4
HHZ		 3476}
3477
1482bd3d 3478static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3479 const struct flow_action_entry *act,
1482bd3d
JL		 3480 struct mlx5_esw_flow_attr *attr,
3481 u32 *action)
3482{
cc495188
JL		 3483 u8 vlan_idx = attr->total_vlan;
3484
3485 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3486 return -EOPNOTSUPP;
3487
73867881
PNA		 3488 switch (act->id) {
3489 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3490 if (vlan_idx) {
3491 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3492 MLX5_FS_VLAN_DEPTH))
3493 return -EOPNOTSUPP;
3494
3495 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3496 } else {
3497 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3498 }
73867881
PNA		 3499 break;
3500 case FLOW_ACTION_VLAN_PUSH:
3501 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3502 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3503 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3504 if (!attr->vlan_proto[vlan_idx])
3505 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3506
3507 if (vlan_idx) {
3508 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3509 MLX5_FS_VLAN_DEPTH))
3510 return -EOPNOTSUPP;
3511
3512 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3513 } else {
3514 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3515 (act->vlan.proto != htons(ETH_P_8021Q) ||
3516 act->vlan.prio))
cc495188
JL		 3517 return -EOPNOTSUPP;
3518
3519 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3520 }
73867881
PNA		 3521 break;
3522 default:
bdc837ee 3523 return -EINVAL;
1482bd3d
JL		 3524 }
3525
cc495188
JL		 3526 attr->total_vlan = vlan_idx + 1;
3527
1482bd3d
JL		 3528 return 0;
3529}
3530
278748a9
EB		 3531static int add_vlan_push_action(struct mlx5e_priv *priv,
3532 struct mlx5_esw_flow_attr *attr,
3533 struct net_device **out_dev,
3534 u32 *action)
3535{
3536 struct net_device *vlan_dev = *out_dev;
3537 struct flow_action_entry vlan_act = {
3538 .id = FLOW_ACTION_VLAN_PUSH,
3539 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3540 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3541 .vlan.prio = 0,
3542 };
3543 int err;
3544
3545 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3546 if (err)
3547 return err;
3548
3549 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3550 dev_get_iflink(vlan_dev));
3551 if (is_vlan_dev(*out_dev))
3552 err = add_vlan_push_action(priv, attr, out_dev, action);
3553
3554 return err;
3555}
3556
35a605db
EB		 3557static int add_vlan_pop_action(struct mlx5e_priv *priv,
3558 struct mlx5_esw_flow_attr *attr,
3559 u32 *action)
3560{
f3b0a18b 3561 int nest_level = attr->parse_attr->filter_dev->lower_level;
35a605db
EB		 3562 struct flow_action_entry vlan_act = {
3563 .id = FLOW_ACTION_VLAN_POP,
3564 };
3565 int err = 0;
3566
3567 while (nest_level--) {
3568 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3569 if (err)
3570 return err;
3571 }
3572
3573 return err;
3574}
3575
f6dc1264
PB		 3576bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3577 struct net_device *out_dev)
3578{
3579 if (is_merged_eswitch_dev(priv, out_dev))
3580 return true;
3581
3582 return mlx5e_eswitch_rep(out_dev) &&
3583 same_hw_devs(priv, netdev_priv(out_dev));
3584}
3585
554fe75c
DL		 3586static bool is_duplicated_output_device(struct net_device *dev,
3587 struct net_device *out_dev,
3588 int *ifindexes, int if_count,
3589 struct netlink_ext_ack *extack)
3590{
3591 int i;
3592
3593 for (i = 0; i < if_count; i++) {
3594 if (ifindexes[i] == out_dev->ifindex) {
3595 NL_SET_ERR_MSG_MOD(extack,
3596 "can't duplicate output to same device");
3597 netdev_err(dev, "can't duplicate output to same device: %s\n",
3598 out_dev->name);
3599 return true;
3600 }
3601 }
3602
3603 return false;
3604}
3605
2fbbc30d
EC		 3606static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3607 struct mlx5e_tc_flow *flow,
3608 const struct flow_action_entry *act,
3609 u32 actions,
3610 struct netlink_ext_ack *extack)
3611{
3612 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3613 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3614 bool ft_flow = mlx5e_is_ft_flow(flow);
3615 u32 dest_chain = act->chain_index;
3616
3617 if (ft_flow) {
3618 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3619 return -EOPNOTSUPP;
3620 }
3621
3622 if (!mlx5_esw_chains_backwards_supported(esw) &&
3623 dest_chain <= attr->chain) {
3624 NL_SET_ERR_MSG_MOD(extack,
3625 "Goto lower numbered chain isn't supported");
3626 return -EOPNOTSUPP;
3627 }
3628 if (dest_chain > max_chain) {
3629 NL_SET_ERR_MSG_MOD(extack,
3630 "Requested destination chain is out of supported range");
3631 return -EOPNOTSUPP;
3632 }
3633
3634 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3635 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3636 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3637 NL_SET_ERR_MSG_MOD(extack,
3638 "Goto chain is not allowed if action has reformat or decap");
3639 return -EOPNOTSUPP;
3640 }
3641
3642 return 0;
3643}
3644
613f53fe
EC		 3645static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3646 struct mlx5e_tc_flow *flow,
3647 struct net_device *out_dev,
3648 struct netlink_ext_ack *extack)
3649{
3650 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3651 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3652 struct mlx5e_rep_priv *rep_priv;
3653
3654 /* Forwarding non encapsulated traffic between
3655 * uplink ports is allowed only if
3656 * termination_table_raw_traffic cap is set.
3657 *
3658 * Input vport was stored esw_attr->in_rep.
3659 * In LAG case, *priv* is the private data of
3660 * uplink which may be not the input vport.
3661 */
3662 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3663
3664 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3665 mlx5e_eswitch_uplink_rep(out_dev)))
3666 return 0;
3667
3668 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3669 termination_table_raw_traffic)) {
3670 NL_SET_ERR_MSG_MOD(extack,
3671 "devices are both uplink, can't offload forwarding");
3672 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3673 priv->netdev->name, out_dev->name);
3674 return -EOPNOTSUPP;
3675 } else if (out_dev != rep_priv->netdev) {
3676 NL_SET_ERR_MSG_MOD(extack,
3677 "devices are not the same uplink, can't offload forwarding");
3678 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3679 priv->netdev->name, out_dev->name);
3680 return -EOPNOTSUPP;
3681 }
3682 return 0;
3683}
3684
73867881
PNA		 3685static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3686 struct flow_action *flow_action,
e98bedf5
EB		 3687 struct mlx5e_tc_flow *flow,
3688 struct netlink_ext_ack *extack)
03a9d11e 3689{
73867881 3690 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3691 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3692 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3693 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3694 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3695 const struct ip_tunnel_info *info = NULL;
554fe75c 3696 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3697 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3698 const struct flow_action_entry *act;
0a7fcb78
PB		 3699 bool encap = false, decap = false;
3700 u32 action = attr->action;
554fe75c 3701 int err, i, if_count = 0;
03a9d11e 3702
73867881 3703 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3704 return -EINVAL;
3705
53eca1f3
JK		 3706 if (!flow_action_hw_stats_check(flow_action, extack,
3707 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3708 return -EOPNOTSUPP;
3709
73867881
PNA		 3710 flow_action_for_each(i, act, flow_action) {
3711 switch (act->id) {
3712 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3713 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3714 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3715 break;
3716 case FLOW_ACTION_MANGLE:
3717 case FLOW_ACTION_ADD:
3718 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
dec481c8 3719 hdrs, extack);
d7e75a32
OG		 3720 if (err)
3721 return err;
3722
1cab1cd7 3723 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 3724 attr->split_count = attr->out_count;
73867881
PNA		 3725 break;
3726 case FLOW_ACTION_CSUM:
1cab1cd7 3727 if (csum_offload_supported(priv, action,
73867881
PNA		 3728 act->csum_flags, extack))
3729 break;
26c02749
OG		 3730
3731 return -EOPNOTSUPP;
73867881
PNA		 3732 case FLOW_ACTION_REDIRECT:
3733 case FLOW_ACTION_MIRRED: {
03a9d11e 3734 struct mlx5e_priv *out_priv;
592d3651 3735 struct net_device *out_dev;
03a9d11e 3736
73867881 3737 out_dev = act->dev;
ef381359
OS		 3738 if (!out_dev) {
3739 /* out_dev is NULL when filters with
3740 * non-existing mirred device are replayed to
3741 * the driver.
3742 */
3743 return -EINVAL;
3744 }
03a9d11e 3745
84179981
PB		 3746 if (ft_flow && out_dev == priv->netdev) {
3747 /* Ignore forward to self rules generated
3748 * by adding both mlx5 devs to the flow table
3749 * block on a normal nft offload setup.
3750 */
3751 return -EOPNOTSUPP;
3752 }
3753
592d3651 3754 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3755 NL_SET_ERR_MSG_MOD(extack,
3756 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3757 netdev_warn(priv->netdev,
3758 "can't support more than %d output ports, can't offload forwarding\n",
3759 attr->out_count);
592d3651
CM		 3760 return -EOPNOTSUPP;
3761 }
3762
f493f155
EB		 3763 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3764 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 3765 if (encap) {
3766 parse_attr->mirred_ifindex[attr->out_count] =
3767 out_dev->ifindex;
3768 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3769 if (!parse_attr->tun_info[attr->out_count])
3770 return -ENOMEM;
3771 encap = false;
3772 attr->dests[attr->out_count].flags |=
3773 MLX5_ESW_DEST_ENCAP;
3774 attr->out_count++;
3775 /* attr->dests[].rep is resolved when we
3776 * handle encap
3777 */
3778 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3779 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3780 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3781 struct net_device *uplink_upper;
7ba58ba7 3782
554fe75c
DL		 3783 if (is_duplicated_output_device(priv->netdev,
3784 out_dev,
3785 ifindexes,
3786 if_count,
3787 extack))
3788 return -EOPNOTSUPP;
3789
3790 ifindexes[if_count] = out_dev->ifindex;
3791 if_count++;
3792
fa833bd5
VB		 3793 rcu_read_lock();
3794 uplink_upper =
3795 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3796 if (uplink_upper &&
3797 netif_is_lag_master(uplink_upper) &&
3798 uplink_upper == out_dev)
3799 out_dev = uplink_dev;
fa833bd5 3800 rcu_read_unlock();
7ba58ba7 3801
278748a9
EB		 3802 if (is_vlan_dev(out_dev)) {
3803 err = add_vlan_push_action(priv, attr,
3804 &out_dev,
3805 &action);
3806 if (err)
3807 return err;
3808 }
f6dc1264 3809
35a605db
EB		 3810 if (is_vlan_dev(parse_attr->filter_dev)) {
3811 err = add_vlan_pop_action(priv, attr,
3812 &action);
3813 if (err)
3814 return err;
3815 }
278748a9 3816
613f53fe
EC		 3817 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3818 if (err)
3819 return err;
ffec9702 3820
f6dc1264
PB		 3821 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3822 NL_SET_ERR_MSG_MOD(extack,
3823 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3824 netdev_warn(priv->netdev,
3825 "devices %s %s not on same switch HW, can't offload forwarding\n",
3826 priv->netdev->name,
3827 out_dev->name);
a0646c88 3828 return -EOPNOTSUPP;
f6dc1264 3829 }
a0646c88 3830
a54e20b4 3831 out_priv = netdev_priv(out_dev);
1d447a39 3832 rpriv = out_priv->ppriv;
df65a573
EB		 3833 attr->dests[attr->out_count].rep = rpriv->rep;
3834 attr->dests[attr->out_count].mdev = out_priv->mdev;
3835 attr->out_count++;
ef381359
OS		 3836 } else if (parse_attr->filter_dev != priv->netdev) {
3837 /* All mlx5 devices are called to configure
3838 * high level device filters. Therefore, the
3839 * *attempt* to install a filter on invalid
3840 * eswitch should not trigger an explicit error
3841 */
3842 return -EINVAL;
a54e20b4 3843 } else {
e98bedf5
EB		 3844 NL_SET_ERR_MSG_MOD(extack,
3845 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3846 netdev_warn(priv->netdev,
3847 "devices %s %s not on same switch HW, can't offload forwarding\n",
3848 priv->netdev->name,
3849 out_dev->name);
03a9d11e
OG		 3850 return -EINVAL;
3851 }
73867881
PNA		 3852 }
3853 break;
3854 case FLOW_ACTION_TUNNEL_ENCAP:
3855 info = act->tunnel;
a54e20b4
HHZ		 3856 if (info)
3857 encap = true;
3858 else
3859 return -EOPNOTSUPP;
1482bd3d 3860
73867881
PNA		 3861 break;
3862 case FLOW_ACTION_VLAN_PUSH:
3863 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3864 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3865 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3866 /* Replace vlan pop+push with vlan modify */
3867 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3868 err = add_vlan_rewrite_action(priv,
3869 MLX5_FLOW_NAMESPACE_FDB,
3870 act, parse_attr, hdrs,
3871 &action, extack);
3872 } else {
3873 err = parse_tc_vlan_action(priv, act, attr, &action);
3874 }
1482bd3d
JL		 3875 if (err)
3876 return err;
3877
bdc837ee
EB		 3878 attr->split_count = attr->out_count;
3879 break;
3880 case FLOW_ACTION_VLAN_MANGLE:
3881 err = add_vlan_rewrite_action(priv,
3882 MLX5_FLOW_NAMESPACE_FDB,
3883 act, parse_attr, hdrs,
3884 &action, extack);
3885 if (err)
3886 return err;
3887
e85e02ba 3888 attr->split_count = attr->out_count;
73867881
PNA		 3889 break;
3890 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3891 decap = true;
73867881 3892 break;
2fbbc30d
EC		 3893 case FLOW_ACTION_GOTO:
3894 err = mlx5_validate_goto_chain(esw, flow, act, action,
3895 extack);
3896 if (err)
3897 return err;
bf07aa73 3898
e88afe75 3899 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 3900 attr->dest_chain = act->chain_index;
73867881 3901 break;
4c3844d9
PB		 3902 case FLOW_ACTION_CT:
3903 err = mlx5_tc_ct_parse_action(priv, attr, act, extack);
3904 if (err)
3905 return err;
3906
3907 flow_flag_set(flow, CT);
3908 break;
73867881 3909 default:
2cc1cb1d
TZ		 3910 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3911 return -EOPNOTSUPP;
bf07aa73 3912 }
03a9d11e 3913 }
bdd66ac0 3914
0bac1194
EB		 3915 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3916 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3917 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3918 * tag rewrite.
3919 */
3920 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3921 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3922 &action, extack);
3923 if (err)
3924 return err;
3925 }
3926
c500c86b
PNA		 3927 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3928 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3929 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3930 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3931 if (err)
3932 return err;
27c11b6b
EB		 3933 /* in case all pedit actions are skipped, remove the MOD_HDR
3934 * flag. we might have set split_count either by pedit or
3935 * pop/push. if there is no pop/push either, reset it too.
3936 */
6ae4a6a5 3937 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3938 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3939 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 3940 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3941 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3942 attr->split_count = 0;
3943 }
c500c86b
PNA		 3944 }
3945
1cab1cd7 3946 attr->action = action;
73867881 3947 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3948 return -EOPNOTSUPP;
3949
e88afe75 3950 if (attr->dest_chain) {
0a7fcb78
PB		 3951 if (decap) {
3952 /* It can be supported if we'll create a mapping for
3953 * the tunnel device only (without tunnel), and set
3954 * this tunnel id with this decap flow.
3955 *
3956 * On restore (miss), we'll just set this saved tunnel
3957 * device.
3958 */
3959
3960 NL_SET_ERR_MSG(extack,
3961 "Decap with goto isn't supported");
3962 netdev_warn(priv->netdev,
3963 "Decap with goto isn't supported");
3964 return -EOPNOTSUPP;
3965 }
3966
e88afe75 3967 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 3968 NL_SET_ERR_MSG_MOD(extack,
3969 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 3970 return -EOPNOTSUPP;
3971 }
3972 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3973 }
3974
ae2741e2
VB		 3975 if (!(attr->action &
3976 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 3977 NL_SET_ERR_MSG_MOD(extack,
3978 "Rule must have at least one forward/drop action");
ae2741e2
VB		 3979 return -EOPNOTSUPP;
3980 }
3981
e85e02ba 3982 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3983 NL_SET_ERR_MSG_MOD(extack,
3984 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3985 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3986 return -EOPNOTSUPP;
3987 }
3988
31c8eba5 3989 return 0;
03a9d11e
OG		 3990}
3991
226f2ca3 3992static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3993{
226f2ca3 3994 unsigned long __flow_flags = 0;
60bd4af8 3995
226f2ca3
VB		 3996 if (flags & MLX5_TC_FLAG(INGRESS))
3997 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3998 if (flags & MLX5_TC_FLAG(EGRESS))
3999 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4000
226f2ca3
VB		 4001 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4002 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4003 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4004 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4005 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4006 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4007
60bd4af8
OG		 4008 *flow_flags = __flow_flags;
4009}
4010
05866c82
OG		 4011static const struct rhashtable_params tc_ht_params = {
4012 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4013 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4014 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4015 .automatic_shrinking = true,
4016};
4017
226f2ca3
VB		 4018static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4019 unsigned long flags)
05866c82 4020{
655dc3d2
OG		 4021 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4022 struct mlx5e_rep_priv *uplink_rpriv;
4023
226f2ca3 4024 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4025 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4026 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4027 } else /* NIC offload */
655dc3d2 4028 return &priv->fs.tc.ht;
05866c82
OG		 4029}
4030
04de7dda
RD		 4031static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4032{
1418ddd9 4033 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 4034 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4035 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4036 bool act_is_encap = !!(attr->action &
4037 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4038 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
4039 MLX5_DEVCOM_ESW_OFFLOADS);
4040
10fbb1cd
RD		 4041 if (!esw_paired)
4042 return false;
4043
4044 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
4045 mlx5_lag_is_multipath(attr->in_mdev)) &&
4046 (is_rep_ingress || act_is_encap))
4047 return true;
4048
4049 return false;
04de7dda
RD		 4050}
4051
a88780a9
RD		 4052static int
4053mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4054 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4055 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4056 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4057{
17091853 4058 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 4059 struct mlx5e_tc_flow *flow;
5a7e5bcb 4060 int out_index, err;
e3a2b7ed 4061
65ba8fb7 4062 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 4063 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 4064 if (!parse_attr || !flow) {
e3a2b7ed
AV		 4065 err = -ENOMEM;
4066 goto err_free;
4067 }
4068
4069 flow->cookie = f->cookie;
65ba8fb7 4070 flow->flags = flow_flags;
655dc3d2 4071 flow->priv = priv;
5a7e5bcb
VB		 4072 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4073 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4074 INIT_LIST_HEAD(&flow->mod_hdr);
4075 INIT_LIST_HEAD(&flow->hairpin);
4076 refcount_set(&flow->refcnt, 1);
95435ad7 4077 init_completion(&flow->init_done);
e3a2b7ed 4078
a88780a9
RD		 4079 *__flow = flow;
4080 *__parse_attr = parse_attr;
4081
4082 return 0;
4083
4084err_free:
4085 kfree(flow);
4086 kvfree(parse_attr);
4087 return err;
4088}
4089
988ab9c7
TZ		 4090static void
4091mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
4092 struct mlx5e_priv *priv,
4093 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4094 struct flow_cls_offload *f,
988ab9c7
TZ		 4095 struct mlx5_eswitch_rep *in_rep,
4096 struct mlx5_core_dev *in_mdev)
4097{
4098 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4099
4100 esw_attr->parse_attr = parse_attr;
4101 esw_attr->chain = f->common.chain_index;
ef01adae 4102 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 4103
4104 esw_attr->in_rep = in_rep;
4105 esw_attr->in_mdev = in_mdev;
4106
4107 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4108 MLX5_COUNTER_SOURCE_ESWITCH)
4109 esw_attr->counter_dev = in_mdev;
4110 else
4111 esw_attr->counter_dev = priv->mdev;
4112}
4113
71129676 4114static struct mlx5e_tc_flow *
04de7dda 4115__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4116 struct flow_cls_offload *f,
226f2ca3 4117 unsigned long flow_flags,
04de7dda
RD		 4118 struct net_device *filter_dev,
4119 struct mlx5_eswitch_rep *in_rep,
71129676 4120 struct mlx5_core_dev *in_mdev)
a88780a9 4121{
f9e30088 4122 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4123 struct netlink_ext_ack *extack = f->common.extack;
4124 struct mlx5e_tc_flow_parse_attr *parse_attr;
4125 struct mlx5e_tc_flow *flow;
4126 int attr_size, err;
e3a2b7ed 4127
226f2ca3 4128 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4129 attr_size = sizeof(struct mlx5_esw_flow_attr);
4130 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4131 &parse_attr, &flow);
4132 if (err)
4133 goto out;
988ab9c7 4134
d11afc26 4135 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 4136 mlx5e_flow_esw_attr_init(flow->esw_attr,
4137 priv, parse_attr,
4138 f, in_rep, in_mdev);
4139
54c177ca
OS		 4140 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4141 f, filter_dev);
d11afc26
OS		 4142 if (err)
4143 goto err_free;
a88780a9 4144
6f9af8ff 4145 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4146 if (err)
4147 goto err_free;
4148
4c3844d9
PB		 4149 err = mlx5_tc_ct_parse_match(priv, &parse_attr->spec, f, extack);
4150 if (err)
4151 goto err_free;
4152
7040632d 4153 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4154 complete_all(&flow->init_done);
ef06c9ee
RD		 4155 if (err) {
4156 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4157 goto err_free;
4158
b4a23329 4159 add_unready_flow(flow);
ef06c9ee 4160 }
e3a2b7ed 4161
71129676 4162 return flow;
a88780a9
RD		 4163
4164err_free:
5a7e5bcb 4165 mlx5e_flow_put(priv, flow);
a88780a9 4166out:
71129676 4167 return ERR_PTR(err);
a88780a9
RD		 4168}
4169
f9e30088 4170static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4171 struct mlx5e_tc_flow *flow,
226f2ca3 4172 unsigned long flow_flags)
04de7dda
RD		 4173{
4174 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4175 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4176 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4177 struct mlx5e_tc_flow_parse_attr *parse_attr;
4178 struct mlx5e_rep_priv *peer_urpriv;
4179 struct mlx5e_tc_flow *peer_flow;
4180 struct mlx5_core_dev *in_mdev;
4181 int err = 0;
4182
4183 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4184 if (!peer_esw)
4185 return -ENODEV;
4186
4187 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4188 peer_priv = netdev_priv(peer_urpriv->netdev);
4189
4190 /* in_mdev is assigned of which the packet originated from.
4191 * So packets redirected to uplink use the same mdev of the
4192 * original flow and packets redirected from uplink use the
4193 * peer mdev.
4194 */
b05af6aa 4195 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4196 in_mdev = peer_priv->mdev;
4197 else
4198 in_mdev = priv->mdev;
4199
4200 parse_attr = flow->esw_attr->parse_attr;
95dc1902 4201 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 4202 parse_attr->filter_dev,
4203 flow->esw_attr->in_rep, in_mdev);
4204 if (IS_ERR(peer_flow)) {
4205 err = PTR_ERR(peer_flow);
04de7dda 4206 goto out;
71129676 4207 }
04de7dda
RD		 4208
4209 flow->peer_flow = peer_flow;
226f2ca3 4210 flow_flag_set(flow, DUP);
04de7dda
RD		 4211 mutex_lock(&esw->offloads.peer_mutex);
4212 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4213 mutex_unlock(&esw->offloads.peer_mutex);
4214
4215out:
4216 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4217 return err;
4218}
4219
4220static int
4221mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4222 struct flow_cls_offload *f,
226f2ca3 4223 unsigned long flow_flags,
04de7dda
RD		 4224 struct net_device *filter_dev,
4225 struct mlx5e_tc_flow **__flow)
4226{
4227 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4228 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4229 struct mlx5_core_dev *in_mdev = priv->mdev;
4230 struct mlx5e_tc_flow *flow;
4231 int err;
4232
71129676
JG		 4233 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4234 in_mdev);
4235 if (IS_ERR(flow))
4236 return PTR_ERR(flow);
04de7dda
RD		 4237
4238 if (is_peer_flow_needed(flow)) {
95dc1902 4239 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4240 if (err) {
4241 mlx5e_tc_del_fdb_flow(priv, flow);
4242 goto out;
4243 }
4244 }
4245
4246 *__flow = flow;
4247
4248 return 0;
4249
4250out:
4251 return err;
4252}
4253
a88780a9
RD		 4254static int
4255mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4256 struct flow_cls_offload *f,
226f2ca3 4257 unsigned long flow_flags,
d11afc26 4258 struct net_device *filter_dev,
a88780a9
RD		 4259 struct mlx5e_tc_flow **__flow)
4260{
f9e30088 4261 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4262 struct netlink_ext_ack *extack = f->common.extack;
4263 struct mlx5e_tc_flow_parse_attr *parse_attr;
4264 struct mlx5e_tc_flow *flow;
4265 int attr_size, err;
4266
bf07aa73
PB		 4267 /* multi-chain not supported for NIC rules */
4268 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4269 return -EOPNOTSUPP;
4270
226f2ca3 4271 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4272 attr_size = sizeof(struct mlx5_nic_flow_attr);
4273 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4274 &parse_attr, &flow);
4275 if (err)
4276 goto out;
4277
d11afc26 4278 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 4279 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4280 f, filter_dev);
d11afc26
OS		 4281 if (err)
4282 goto err_free;
4283
73867881 4284 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4285 if (err)
4286 goto err_free;
4287
4288 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4289 if (err)
4290 goto err_free;
4291
226f2ca3 4292 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4293 kvfree(parse_attr);
4294 *__flow = flow;
4295
4296 return 0;
e3a2b7ed 4297
e3a2b7ed 4298err_free:
5a7e5bcb 4299 mlx5e_flow_put(priv, flow);
17091853 4300 kvfree(parse_attr);
a88780a9
RD		 4301out:
4302 return err;
4303}
4304
4305static int
4306mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4307 struct flow_cls_offload *f,
226f2ca3 4308 unsigned long flags,
d11afc26 4309 struct net_device *filter_dev,
a88780a9
RD		 4310 struct mlx5e_tc_flow **flow)
4311{
4312 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4313 unsigned long flow_flags;
a88780a9
RD		 4314 int err;
4315
4316 get_flags(flags, &flow_flags);
4317
bf07aa73
PB		 4318 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4319 return -EOPNOTSUPP;
4320
f6455de0 4321 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4322 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4323 filter_dev, flow);
a88780a9 4324 else
d11afc26
OS		 4325 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4326 filter_dev, flow);
a88780a9
RD		 4327
4328 return err;
4329}
4330
71d82d2a 4331int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4332 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4333{
4334 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4335 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 4336 struct mlx5e_tc_flow *flow;
4337 int err = 0;
4338
c5d326b2
VB		 4339 rcu_read_lock();
4340 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4341 rcu_read_unlock();
a88780a9
RD		 4342 if (flow) {
4343 NL_SET_ERR_MSG_MOD(extack,
4344 "flow cookie already exists, ignoring");
4345 netdev_warn_once(priv->netdev,
4346 "flow cookie %lx already exists, ignoring\n",
4347 f->cookie);
0e1c1a2f 4348 err = -EEXIST;
a88780a9
RD		 4349 goto out;
4350 }
4351
7a978759 4352 trace_mlx5e_configure_flower(f);
d11afc26 4353 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4354 if (err)
4355 goto out;
4356
c5d326b2 4357 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4358 if (err)
4359 goto err_free;
4360
4361 return 0;
4362
4363err_free:
5a7e5bcb 4364 mlx5e_flow_put(priv, flow);
a88780a9 4365out:
e3a2b7ed
AV		 4366 return err;
4367}
4368
8f8ae895
OG		 4369static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4370{
226f2ca3
VB		 4371 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4372 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4373
226f2ca3
VB		 4374 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4375 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4376}
4377
71d82d2a 4378int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4379 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4380{
d9ee0491 4381 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4382 struct mlx5e_tc_flow *flow;
c5d326b2 4383 int err;
e3a2b7ed 4384
c5d326b2 4385 rcu_read_lock();
ab818362 4386 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4387 if (!flow || !same_flow_direction(flow, flags)) {
4388 err = -EINVAL;
4389 goto errout;
4390 }
e3a2b7ed 4391
c5d326b2
VB		 4392 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4393 * set.
4394 */
4395 if (flow_flag_test_and_set(flow, DELETED)) {
4396 err = -EINVAL;
4397 goto errout;
4398 }
05866c82 4399 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4400 rcu_read_unlock();
e3a2b7ed 4401
7a978759 4402 trace_mlx5e_delete_flower(f);
5a7e5bcb 4403 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4404
4405 return 0;
c5d326b2
VB		 4406
4407errout:
4408 rcu_read_unlock();
4409 return err;
e3a2b7ed
AV		 4410}
4411
71d82d2a 4412int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4413 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4414{
04de7dda 4415 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4416 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4417 struct mlx5_eswitch *peer_esw;
aad7e08d 4418 struct mlx5e_tc_flow *flow;
aad7e08d 4419 struct mlx5_fc *counter;
316d5f72
RD		 4420 u64 lastuse = 0;
4421 u64 packets = 0;
4422 u64 bytes = 0;
5a7e5bcb 4423 int err = 0;
aad7e08d 4424
c5d326b2
VB		 4425 rcu_read_lock();
4426 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4427 tc_ht_params));
4428 rcu_read_unlock();
5a7e5bcb
VB		 4429 if (IS_ERR(flow))
4430 return PTR_ERR(flow);
4431
4432 if (!same_flow_direction(flow, flags)) {
4433 err = -EINVAL;
4434 goto errout;
4435 }
aad7e08d 4436
4c3844d9 4437 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4438 counter = mlx5e_tc_get_counter(flow);
4439 if (!counter)
5a7e5bcb 4440 goto errout;
aad7e08d 4441
316d5f72
RD		 4442 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4443 }
aad7e08d 4444
316d5f72
RD		 4445 /* Under multipath it's possible for one rule to be currently
4446 * un-offloaded while the other rule is offloaded.
4447 */
04de7dda
RD		 4448 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4449 if (!peer_esw)
4450 goto out;
4451
226f2ca3
VB		 4452 if (flow_flag_test(flow, DUP) &&
4453 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4454 u64 bytes2;
4455 u64 packets2;
4456 u64 lastuse2;
4457
4458 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4459 if (!counter)
4460 goto no_peer_counter;
04de7dda
RD		 4461 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4462
4463 bytes += bytes2;
4464 packets += packets2;
4465 lastuse = max_t(u64, lastuse, lastuse2);
4466 }
4467
316d5f72 4468no_peer_counter:
04de7dda 4469 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4470out:
93a129eb
JP		 4471 flow_stats_update(&f->stats, bytes, packets, lastuse,
4472 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4473 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4474errout:
4475 mlx5e_flow_put(priv, flow);
4476 return err;
aad7e08d
AV		 4477}
4478
fcb64c0f
EC		 4479static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4480 struct netlink_ext_ack *extack)
4481{
4482 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4483 struct mlx5_eswitch *esw;
4484 u16 vport_num;
4485 u32 rate_mbps;
4486 int err;
4487
e401a184
EC		 4488 vport_num = rpriv->rep->vport;
4489 if (vport_num >= MLX5_VPORT_ECPF) {
4490 NL_SET_ERR_MSG_MOD(extack,
4491 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4492 return -EOPNOTSUPP;
4493 }
4494
fcb64c0f
EC		 4495 esw = priv->mdev->priv.eswitch;
4496 /* rate is given in bytes/sec.
4497 * First convert to bits/sec and then round to the nearest mbit/secs.
4498 * mbit means million bits.
4499 * Moreover, if rate is non zero we choose to configure to a minimum of
4500 * 1 mbit/sec.
4501 */
4502 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
fcb64c0f
EC		 4503 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4504 if (err)
4505 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4506
4507 return err;
4508}
4509
4510static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4511 struct flow_action *flow_action,
4512 struct netlink_ext_ack *extack)
4513{
4514 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4515 const struct flow_action_entry *act;
4516 int err;
4517 int i;
4518
4519 if (!flow_action_has_entries(flow_action)) {
4520 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4521 return -EINVAL;
4522 }
4523
4524 if (!flow_offload_has_one_action(flow_action)) {
4525 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4526 return -EOPNOTSUPP;
4527 }
4528
53eca1f3 4529 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4530 return -EOPNOTSUPP;
4531
fcb64c0f
EC		 4532 flow_action_for_each(i, act, flow_action) {
4533 switch (act->id) {
4534 case FLOW_ACTION_POLICE:
4535 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4536 if (err)
4537 return err;
4538
4539 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4540 break;
4541 default:
4542 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4543 return -EOPNOTSUPP;
4544 }
4545 }
4546
4547 return 0;
4548}
4549
4550int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4551 struct tc_cls_matchall_offload *ma)
4552{
b5f814cc 4553 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4554 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4555
b5f814cc
EC		 4556 if (!mlx5_esw_qos_enabled(esw)) {
4557 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4558 return -EOPNOTSUPP;
4559 }
4560
7b83355f 4561 if (ma->common.prio != 1) {
fcb64c0f
EC		 4562 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4563 return -EINVAL;
4564 }
4565
4566 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4567}
4568
4569int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4570 struct tc_cls_matchall_offload *ma)
4571{
4572 struct netlink_ext_ack *extack = ma->common.extack;
4573
4574 return apply_police_params(priv, 0, extack);
4575}
4576
4577void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4578 struct tc_cls_matchall_offload *ma)
4579{
4580 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4581 struct rtnl_link_stats64 cur_stats;
4582 u64 dbytes;
4583 u64 dpkts;
4584
4585 cur_stats = priv->stats.vf_vport;
4586 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4587 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4588 rpriv->prev_vf_vport_stats = cur_stats;
93a129eb
JP		 4589 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies,
4590 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4591}
4592
4d8fcf21
AH		 4593static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4594 struct mlx5e_priv *peer_priv)
4595{
4596 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4597 struct mlx5e_hairpin_entry *hpe, *tmp;
4598 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4599 u16 peer_vhca_id;
4600 int bkt;
4601
4602 if (!same_hw_devs(priv, peer_priv))
4603 return;
4604
4605 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4606
b32accda 4607 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4608 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4609 if (refcount_inc_not_zero(&hpe->refcnt))
4610 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4611 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4612
4613 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4614 wait_for_completion(&hpe->res_ready);
4615 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4616 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4617
4618 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4619 }
4620}
4621
4622static int mlx5e_tc_netdev_event(struct notifier_block *this,
4623 unsigned long event, void *ptr)
4624{
4625 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4626 struct mlx5e_flow_steering *fs;
4627 struct mlx5e_priv *peer_priv;
4628 struct mlx5e_tc_table *tc;
4629 struct mlx5e_priv *priv;
4630
4631 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4632 event != NETDEV_UNREGISTER ||
4633 ndev->reg_state == NETREG_REGISTERED)
4634 return NOTIFY_DONE;
4635
4636 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4637 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4638 priv = container_of(fs, struct mlx5e_priv, fs);
4639 peer_priv = netdev_priv(ndev);
4640 if (priv == peer_priv ||
4641 !(priv->netdev->features & NETIF_F_HW_TC))
4642 return NOTIFY_DONE;
4643
4644 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4645
4646 return NOTIFY_DONE;
4647}
4648
655dc3d2 4649int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4650{
acff797c 4651 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4652 int err;
e8f887ac 4653
b6fac0b4 4654 mutex_init(&tc->t_lock);
d2faae25 4655 mutex_init(&tc->mod_hdr.lock);
dd58edc3 4656 hash_init(tc->mod_hdr.hlist);
b32accda 4657 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4658 hash_init(tc->hairpin_tbl);
11c9c548 4659
4d8fcf21
AH		 4660 err = rhashtable_init(&tc->ht, &tc_ht_params);
4661 if (err)
4662 return err;
4663
4664 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4665 err = register_netdevice_notifier_dev_net(priv->netdev,
4666 &tc->netdevice_nb,
4667 &tc->netdevice_nn);
4668 if (err) {
4d8fcf21
AH		 4669 tc->netdevice_nb.notifier_call = NULL;
4670 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4671 }
4672
4673 return err;
e8f887ac
AV		 4674}
4675
4676static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4677{
4678 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4679 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4680
961e8979 4681 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4682 kfree(flow);
4683}
4684
655dc3d2 4685void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4686{
acff797c 4687 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4688
4d8fcf21 4689 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4690 unregister_netdevice_notifier_dev_net(priv->netdev,
4691 &tc->netdevice_nb,
4692 &tc->netdevice_nn);
4d8fcf21 4693
d2faae25 4694 mutex_destroy(&tc->mod_hdr.lock);
b32accda
VB		 4695 mutex_destroy(&tc->hairpin_tbl_lock);
4696
d9ee0491 4697 rhashtable_destroy(&tc->ht);
e8f887ac 4698
acff797c
MG		 4699 if (!IS_ERR_OR_NULL(tc->t)) {
4700 mlx5_destroy_flow_table(tc->t);
4701 tc->t = NULL;
e8f887ac 4702 }
b6fac0b4 4703 mutex_destroy(&tc->t_lock);
e8f887ac 4704}
655dc3d2
OG		 4705
4706int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4707{
0a7fcb78
PB		 4708 const size_t sz_enc_opts = sizeof(struct flow_dissector_key_enc_opts);
4709 struct mlx5_rep_uplink_priv *uplink_priv;
4710 struct mlx5e_rep_priv *priv;
4711 struct mapping_ctx *mapping;
4712 int err;
4713
4714 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4715 priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4716
4c3844d9
PB		 4717 err = mlx5_tc_ct_init(uplink_priv);
4718 if (err)
4719 goto err_ct;
4720
0a7fcb78
PB		 4721 mapping = mapping_create(sizeof(struct tunnel_match_key),
4722 TUNNEL_INFO_BITS_MASK, true);
4723 if (IS_ERR(mapping)) {
4724 err = PTR_ERR(mapping);
4725 goto err_tun_mapping;
4726 }
4727 uplink_priv->tunnel_mapping = mapping;
4728
4729 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
4730 if (IS_ERR(mapping)) {
4731 err = PTR_ERR(mapping);
4732 goto err_enc_opts_mapping;
4733 }
4734 uplink_priv->tunnel_enc_opts_mapping = mapping;
4735
4736 err = rhashtable_init(tc_ht, &tc_ht_params);
4737 if (err)
4738 goto err_ht_init;
4739
4740 return err;
4741
4742err_ht_init:
4743 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4744err_enc_opts_mapping:
4745 mapping_destroy(uplink_priv->tunnel_mapping);
4746err_tun_mapping:
4c3844d9
PB		 4747 mlx5_tc_ct_clean(uplink_priv);
4748err_ct:
0a7fcb78
PB		 4749 netdev_warn(priv->netdev,
4750 "Failed to initialize tc (eswitch), err: %d", err);
4751 return err;
655dc3d2
OG		 4752}
4753
4754void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4755{
0a7fcb78
PB		 4756 struct mlx5_rep_uplink_priv *uplink_priv;
4757
655dc3d2 4758 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 4759
4760 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4761 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4762 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9
PB		 4763
4764 mlx5_tc_ct_clean(uplink_priv);
655dc3d2 4765}
01252a27 4766
226f2ca3 4767int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4768{
d9ee0491 4769 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4770
4771 return atomic_read(&tc_ht->nelems);
4772}
04de7dda
RD		 4773
4774void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4775{
4776 struct mlx5e_tc_flow *flow, *tmp;
4777
4778 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4779 __mlx5e_tc_del_fdb_peer_flow(flow);
4780}
b4a23329
RD		 4781
4782void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4783{
4784 struct mlx5_rep_uplink_priv *rpriv =
4785 container_of(work, struct mlx5_rep_uplink_priv,
4786 reoffload_flows_work);
4787 struct mlx5e_tc_flow *flow, *tmp;
4788
ad86755b 4789 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4790 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4791 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4792 unready_flow_del(flow);
b4a23329 4793 }
ad86755b 4794 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4795}
d6d27782 4796
b8ce9037
PB		 4797#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4798static bool mlx5e_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
4799 struct mlx5e_tc_update_priv *tc_priv,
4800 u32 tunnel_id)
4801{
4802 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4803 struct flow_dissector_key_enc_opts enc_opts = {};
4804 struct mlx5_rep_uplink_priv *uplink_priv;
4805 struct mlx5e_rep_priv *uplink_rpriv;
4806 struct metadata_dst *tun_dst;
4807 struct tunnel_match_key key;
4808 u32 tun_id, enc_opts_id;
4809 struct net_device *dev;
4810 int err;
4811
4812 enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
4813 tun_id = tunnel_id >> ENC_OPTS_BITS;
4814
4815 if (!tun_id)
4816 return true;
4817
4818 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4819 uplink_priv = &uplink_rpriv->uplink_priv;
4820
4821 err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
4822 if (err) {
4823 WARN_ON_ONCE(true);
4824 netdev_dbg(priv->netdev,
4825 "Couldn't find tunnel for tun_id: %d, err: %d\n",
4826 tun_id, err);
4827 return false;
4828 }
4829
4830 if (enc_opts_id) {
4831 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
4832 enc_opts_id, &enc_opts);
4833 if (err) {
4834 netdev_dbg(priv->netdev,
4835 "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
4836 enc_opts_id, err);
4837 return false;
4838 }
4839 }
4840
4841 tun_dst = tun_rx_dst(enc_opts.len);
4842 if (!tun_dst) {
4843 WARN_ON_ONCE(true);
4844 return false;
4845 }
4846
4847 ip_tunnel_key_init(&tun_dst->u.tun_info.key,
4848 key.enc_ipv4.src, key.enc_ipv4.dst,
4849 key.enc_ip.tos, key.enc_ip.ttl,
4850 0, /* label */
4851 key.enc_tp.src, key.enc_tp.dst,
4852 key32_to_tunnel_id(key.enc_key_id.keyid),
4853 TUNNEL_KEY);
4854
4855 if (enc_opts.len)
4856 ip_tunnel_info_opts_set(&tun_dst->u.tun_info, enc_opts.data,
4857 enc_opts.len, enc_opts.dst_opt_type);
4858
4859 skb_dst_set(skb, (struct dst_entry *)tun_dst);
4860 dev = dev_get_by_index(&init_net, key.filter_ifindex);
4861 if (!dev) {
4862 netdev_dbg(priv->netdev,
4863 "Couldn't find tunnel device with ifindex: %d\n",
4864 key.filter_ifindex);
4865 return false;
4866 }
4867
4868 /* Set tun_dev so we do dev_put() after datapath */
4869 tc_priv->tun_dev = dev;
4870
4871 skb->dev = dev;
4872
4873 return true;
4874}
4875#endif /* CONFIG_NET_TC_SKB_EXT */
4876
d6d27782 4877bool mlx5e_tc_rep_update_skb(struct mlx5_cqe64 *cqe,
b8ce9037
PB		 4878 struct sk_buff *skb,
4879 struct mlx5e_tc_update_priv *tc_priv)
d6d27782
PB		 4880{
4881#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
5c6b9460
PB		 4882 u32 chain = 0, reg_c0, reg_c1, tunnel_id, tuple_id;
4883 struct mlx5_rep_uplink_priv *uplink_priv;
4884 struct mlx5e_rep_priv *uplink_rpriv;
d6d27782
PB		 4885 struct tc_skb_ext *tc_skb_ext;
4886 struct mlx5_eswitch *esw;
4887 struct mlx5e_priv *priv;
b8ce9037 4888 int tunnel_moffset;
d6d27782
PB		 4889 int err;
4890
4891 reg_c0 = (be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK);
4892 if (reg_c0 == MLX5_FS_DEFAULT_FLOW_TAG)
4893 reg_c0 = 0;
b8ce9037 4894 reg_c1 = be32_to_cpu(cqe->imm_inval_pkey);
d6d27782
PB		 4895
4896 if (!reg_c0)
4897 return true;
4898
4899 priv = netdev_priv(skb->dev);
4900 esw = priv->mdev->priv.eswitch;
4901
4902 err = mlx5_eswitch_get_chain_for_tag(esw, reg_c0, &chain);
4903 if (err) {
4904 netdev_dbg(priv->netdev,
4905 "Couldn't find chain for chain tag: %d, err: %d\n",
4906 reg_c0, err);
4907 return false;
4908 }
4909
b8ce9037
PB		 4910 if (chain) {
4911 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
4912 if (!tc_skb_ext) {
4913 WARN_ON(1);
4914 return false;
4915 }
d6d27782 4916
b8ce9037 4917 tc_skb_ext->chain = chain;
5c6b9460
PB		 4918
4919 tuple_id = reg_c1 & TUPLE_ID_MAX;
4920
4921 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4922 uplink_priv = &uplink_rpriv->uplink_priv;
4923 if (!mlx5e_tc_ct_restore_flow(uplink_priv, skb, tuple_id))
4924 return false;
d6d27782
PB		 4925 }
4926
b8ce9037
PB		 4927 tunnel_moffset = mlx5e_tc_attr_to_reg_mappings[TUNNEL_TO_REG].moffset;
4928 tunnel_id = reg_c1 >> (8 * tunnel_moffset);
4929 return mlx5e_restore_tunnel(priv, skb, tc_priv, tunnel_id);
d6d27782
PB		 4930#endif /* CONFIG_NET_TC_SKB_EXT */
4931
4932 return true;
4933}
b8ce9037
PB		 4934
4935void mlx5_tc_rep_post_napi_receive(struct mlx5e_tc_update_priv *tc_priv)
4936{
4937 if (tc_priv->tun_dev)
4938 dev_put(tc_priv->tun_dev);
4939}
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