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net/mlx5e: Expose same physical switch_id for all representors
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e 41#include <net/tc_act/tc_mirred.h>
776b12b6 42#include <net/tc_act/tc_vlan.h>
bbd00f7e 43#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 44#include <net/tc_act/tc_pedit.h>
26c02749 45#include <net/tc_act/tc_csum.h>
f6dfb4c3 46#include <net/arp.h>
3616d08b 47#include <net/ipv6_stubs.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
3f6d08d1 52#include "fs_core.h"
2c81bfd5 53#include "en/port.h"
101f4de9 54#include "en/tc_tun.h"
04de7dda 55#include "lib/devcom.h"
9272e3df 56#include "lib/geneve.h"
e8f887ac 57
3bc4b7bf
OG		 58struct mlx5_nic_flow_attr {
59 u32 action;
60 u32 flow_tag;
2f4fe4ca 61 u32 mod_hdr_id;
5c65c564 62 u32 hairpin_tirn;
38aa51c1 63 u8 match_level;
3f6d08d1 64 struct mlx5_flow_table *hairpin_ft;
b8aee822 65 struct mlx5_fc *counter;
3bc4b7bf
OG		 66};
67
60bd4af8
OG		 68#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
69
65ba8fb7 70enum {
60bd4af8
OG		 71 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
72 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
d9ee0491
OG		 73 MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD,
74 MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD,
75 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE),
76 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1),
77 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2),
78 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3),
79 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4),
ef06c9ee 80 MLX5E_TC_FLOW_NOT_READY = BIT(MLX5E_TC_FLOW_BASE + 5),
65ba8fb7
OG		 81};
82
e4ad91f2
CM		 83#define MLX5E_TC_MAX_SPLITS 1
84
79baaec7
EB		 85/* Helper struct for accessing a struct containing list_head array.
86 * Containing struct
87 * |- Helper array
88 * [0] Helper item 0
89 * |- list_head item 0
90 * |- index (0)
91 * [1] Helper item 1
92 * |- list_head item 1
93 * |- index (1)
94 * To access the containing struct from one of the list_head items:
95 * 1. Get the helper item from the list_head item using
96 * helper item =
97 * container_of(list_head item, helper struct type, list_head field)
98 * 2. Get the contining struct from the helper item and its index in the array:
99 * containing struct =
100 * container_of(helper item, containing struct type, helper field[index])
101 */
102struct encap_flow_item {
103 struct list_head list;
104 int index;
105};
106
e8f887ac
AV		 107struct mlx5e_tc_flow {
108 struct rhash_head node;
655dc3d2 109 struct mlx5e_priv *priv;
e8f887ac 110 u64 cookie;
5dbe906f 111 u16 flags;
e4ad91f2 112 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 113 /* Flow can be associated with multiple encap IDs.
114 * The number of encaps is bounded by the number of supported
115 * destinations.
116 */
117 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 118 struct mlx5e_tc_flow *peer_flow;
11c9c548 119 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 120 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 121 struct list_head peer; /* flows with peer flow */
b4a23329 122 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
3bc4b7bf
OG		 123 union {
124 struct mlx5_esw_flow_attr esw_attr[0];
125 struct mlx5_nic_flow_attr nic_attr[0];
126 };
e8f887ac
AV		 127};
128
17091853 129struct mlx5e_tc_flow_parse_attr {
1f6da306 130 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 131 struct net_device *filter_dev;
17091853 132 struct mlx5_flow_spec spec;
d79b6df6 133 int num_mod_hdr_actions;
218d05ce 134 int max_mod_hdr_actions;
d79b6df6 135 void *mod_hdr_actions;
98b66cb1 136 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 137};
138
acff797c 139#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 140#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 141
77ab67b7
OG		 142struct mlx5e_hairpin {
143 struct mlx5_hairpin *pair;
144
145 struct mlx5_core_dev *func_mdev;
3f6d08d1 146 struct mlx5e_priv *func_priv;
77ab67b7
OG		 147 u32 tdn;
148 u32 tirn;
3f6d08d1
OG		 149
150 int num_channels;
151 struct mlx5e_rqt indir_rqt;
152 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
153 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 154};
155
5c65c564
OG		 156struct mlx5e_hairpin_entry {
157 /* a node of a hash table which keeps all the hairpin entries */
158 struct hlist_node hairpin_hlist;
159
160 /* flows sharing the same hairpin */
161 struct list_head flows;
162
d8822868 163 u16 peer_vhca_id;
106be53b 164 u8 prio;
5c65c564
OG		 165 struct mlx5e_hairpin *hp;
166};
167
11c9c548
OG		 168struct mod_hdr_key {
169 int num_actions;
170 void *actions;
171};
172
173struct mlx5e_mod_hdr_entry {
174 /* a node of a hash table which keeps all the mod_hdr entries */
175 struct hlist_node mod_hdr_hlist;
176
177 /* flows sharing the same mod_hdr entry */
178 struct list_head flows;
179
180 struct mod_hdr_key key;
181
182 u32 mod_hdr_id;
183};
184
185#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
186
187static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
188{
189 return jhash(key->actions,
190 key->num_actions * MLX5_MH_ACT_SZ, 0);
191}
192
193static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
194 struct mod_hdr_key *b)
195{
196 if (a->num_actions != b->num_actions)
197 return 1;
198
199 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
200}
201
202static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
203 struct mlx5e_tc_flow *flow,
204 struct mlx5e_tc_flow_parse_attr *parse_attr)
205{
206 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
207 int num_actions, actions_size, namespace, err;
208 struct mlx5e_mod_hdr_entry *mh;
209 struct mod_hdr_key key;
210 bool found = false;
211 u32 hash_key;
212
213 num_actions = parse_attr->num_mod_hdr_actions;
214 actions_size = MLX5_MH_ACT_SZ * num_actions;
215
216 key.actions = parse_attr->mod_hdr_actions;
217 key.num_actions = num_actions;
218
219 hash_key = hash_mod_hdr_info(&key);
220
221 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
222 namespace = MLX5_FLOW_NAMESPACE_FDB;
223 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
224 mod_hdr_hlist, hash_key) {
225 if (!cmp_mod_hdr_info(&mh->key, &key)) {
226 found = true;
227 break;
228 }
229 }
230 } else {
231 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
232 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
233 mod_hdr_hlist, hash_key) {
234 if (!cmp_mod_hdr_info(&mh->key, &key)) {
235 found = true;
236 break;
237 }
238 }
239 }
240
241 if (found)
242 goto attach_flow;
243
244 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
245 if (!mh)
246 return -ENOMEM;
247
248 mh->key.actions = (void *)mh + sizeof(*mh);
249 memcpy(mh->key.actions, key.actions, actions_size);
250 mh->key.num_actions = num_actions;
251 INIT_LIST_HEAD(&mh->flows);
252
253 err = mlx5_modify_header_alloc(priv->mdev, namespace,
254 mh->key.num_actions,
255 mh->key.actions,
256 &mh->mod_hdr_id);
257 if (err)
258 goto out_err;
259
260 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
261 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
262 else
263 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
264
265attach_flow:
266 list_add(&flow->mod_hdr, &mh->flows);
267 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
268 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
269 else
270 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
271
272 return 0;
273
274out_err:
275 kfree(mh);
276 return err;
277}
278
279static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
280 struct mlx5e_tc_flow *flow)
281{
282 struct list_head *next = flow->mod_hdr.next;
283
284 list_del(&flow->mod_hdr);
285
286 if (list_empty(next)) {
287 struct mlx5e_mod_hdr_entry *mh;
288
289 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
290
291 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
292 hash_del(&mh->mod_hdr_hlist);
293 kfree(mh);
294 }
295}
296
77ab67b7
OG		 297static
298struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
299{
300 struct net_device *netdev;
301 struct mlx5e_priv *priv;
302
303 netdev = __dev_get_by_index(net, ifindex);
304 priv = netdev_priv(netdev);
305 return priv->mdev;
306}
307
308static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
309{
310 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
311 void *tirc;
312 int err;
313
314 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
315 if (err)
316 goto alloc_tdn_err;
317
318 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
319
320 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 321 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 322 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
323
324 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
325 if (err)
326 goto create_tir_err;
327
328 return 0;
329
330create_tir_err:
331 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
332alloc_tdn_err:
333 return err;
334}
335
336static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
337{
338 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
339 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
340}
341
3f6d08d1
OG		 342static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
343{
344 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
345 struct mlx5e_priv *priv = hp->func_priv;
346 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
347
348 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
349 hp->num_channels);
350
351 for (i = 0; i < sz; i++) {
352 ix = i;
bbeb53b8 353 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 354 ix = mlx5e_bits_invert(i, ilog2(sz));
355 ix = indirection_rqt[ix];
356 rqn = hp->pair->rqn[ix];
357 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
358 }
359}
360
361static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
362{
363 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
364 struct mlx5e_priv *priv = hp->func_priv;
365 struct mlx5_core_dev *mdev = priv->mdev;
366 void *rqtc;
367 u32 *in;
368
369 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
370 in = kvzalloc(inlen, GFP_KERNEL);
371 if (!in)
372 return -ENOMEM;
373
374 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
375
376 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
377 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
378
379 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
380
381 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
382 if (!err)
383 hp->indir_rqt.enabled = true;
384
385 kvfree(in);
386 return err;
387}
388
389static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
390{
391 struct mlx5e_priv *priv = hp->func_priv;
392 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
393 int tt, i, err;
394 void *tirc;
395
396 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 397 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
398
3f6d08d1
OG		 399 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
400 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
401
402 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
403 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
404 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 405 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
406
3f6d08d1
OG		 407 err = mlx5_core_create_tir(hp->func_mdev, in,
408 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
409 if (err) {
410 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
411 goto err_destroy_tirs;
412 }
413 }
414 return 0;
415
416err_destroy_tirs:
417 for (i = 0; i < tt; i++)
418 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
419 return err;
420}
421
422static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
423{
424 int tt;
425
426 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
427 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
428}
429
430static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
431 struct ttc_params *ttc_params)
432{
433 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
434 int tt;
435
436 memset(ttc_params, 0, sizeof(*ttc_params));
437
438 ttc_params->any_tt_tirn = hp->tirn;
439
440 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
441 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
442
443 ft_attr->max_fte = MLX5E_NUM_TT;
444 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
445 ft_attr->prio = MLX5E_TC_PRIO;
446}
447
448static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
449{
450 struct mlx5e_priv *priv = hp->func_priv;
451 struct ttc_params ttc_params;
452 int err;
453
454 err = mlx5e_hairpin_create_indirect_rqt(hp);
455 if (err)
456 return err;
457
458 err = mlx5e_hairpin_create_indirect_tirs(hp);
459 if (err)
460 goto err_create_indirect_tirs;
461
462 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
463 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
464 if (err)
465 goto err_create_ttc_table;
466
467 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
468 hp->num_channels, hp->ttc.ft.t->id);
469
470 return 0;
471
472err_create_ttc_table:
473 mlx5e_hairpin_destroy_indirect_tirs(hp);
474err_create_indirect_tirs:
475 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
476
477 return err;
478}
479
480static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
481{
482 struct mlx5e_priv *priv = hp->func_priv;
483
484 mlx5e_destroy_ttc_table(priv, &hp->ttc);
485 mlx5e_hairpin_destroy_indirect_tirs(hp);
486 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
487}
488
77ab67b7
OG		 489static struct mlx5e_hairpin *
490mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
491 int peer_ifindex)
492{
493 struct mlx5_core_dev *func_mdev, *peer_mdev;
494 struct mlx5e_hairpin *hp;
495 struct mlx5_hairpin *pair;
496 int err;
497
498 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
499 if (!hp)
500 return ERR_PTR(-ENOMEM);
501
502 func_mdev = priv->mdev;
503 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
504
505 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
506 if (IS_ERR(pair)) {
507 err = PTR_ERR(pair);
508 goto create_pair_err;
509 }
510 hp->pair = pair;
511 hp->func_mdev = func_mdev;
3f6d08d1
OG		 512 hp->func_priv = priv;
513 hp->num_channels = params->num_channels;
77ab67b7
OG		 514
515 err = mlx5e_hairpin_create_transport(hp);
516 if (err)
517 goto create_transport_err;
518
3f6d08d1
OG		 519 if (hp->num_channels > 1) {
520 err = mlx5e_hairpin_rss_init(hp);
521 if (err)
522 goto rss_init_err;
523 }
524
77ab67b7
OG		 525 return hp;
526
3f6d08d1
OG		 527rss_init_err:
528 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 529create_transport_err:
530 mlx5_core_hairpin_destroy(hp->pair);
531create_pair_err:
532 kfree(hp);
533 return ERR_PTR(err);
534}
535
536static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
537{
3f6d08d1
OG		 538 if (hp->num_channels > 1)
539 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 540 mlx5e_hairpin_destroy_transport(hp);
541 mlx5_core_hairpin_destroy(hp->pair);
542 kvfree(hp);
543}
544
106be53b
OG		 545static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
546{
547 return (peer_vhca_id << 16 | prio);
548}
549
5c65c564 550static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 551 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 552{
553 struct mlx5e_hairpin_entry *hpe;
106be53b 554 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 555
556 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 557 hairpin_hlist, hash_key) {
558 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 559 return hpe;
560 }
561
562 return NULL;
563}
564
106be53b
OG		 565#define UNKNOWN_MATCH_PRIO 8
566
567static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 568 struct mlx5_flow_spec *spec, u8 *match_prio,
569 struct netlink_ext_ack *extack)
106be53b
OG		 570{
571 void *headers_c, *headers_v;
572 u8 prio_val, prio_mask = 0;
573 bool vlan_present;
574
575#ifdef CONFIG_MLX5_CORE_EN_DCB
576 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 577 NL_SET_ERR_MSG_MOD(extack,
578 "only PCP trust state supported for hairpin");
106be53b
OG		 579 return -EOPNOTSUPP;
580 }
581#endif
582 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
583 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
584
585 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
586 if (vlan_present) {
587 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
588 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
589 }
590
591 if (!vlan_present || !prio_mask) {
592 prio_val = UNKNOWN_MATCH_PRIO;
593 } else if (prio_mask != 0x7) {
e98bedf5
EB		 594 NL_SET_ERR_MSG_MOD(extack,
595 "masked priority match not supported for hairpin");
106be53b
OG		 596 return -EOPNOTSUPP;
597 }
598
599 *match_prio = prio_val;
600 return 0;
601}
602
5c65c564
OG		 603static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
604 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 605 struct mlx5e_tc_flow_parse_attr *parse_attr,
606 struct netlink_ext_ack *extack)
5c65c564 607{
98b66cb1 608 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 609 struct mlx5_hairpin_params params;
d8822868 610 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 611 struct mlx5e_hairpin_entry *hpe;
612 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 613 u64 link_speed64;
614 u32 link_speed;
106be53b 615 u8 match_prio;
d8822868 616 u16 peer_id;
5c65c564
OG		 617 int err;
618
d8822868
OG		 619 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
620 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 621 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 622 return -EOPNOTSUPP;
623 }
624
d8822868 625 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 626 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
627 extack);
106be53b
OG		 628 if (err)
629 return err;
630 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 631 if (hpe)
632 goto attach_flow;
633
634 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
635 if (!hpe)
636 return -ENOMEM;
637
638 INIT_LIST_HEAD(&hpe->flows);
d8822868 639 hpe->peer_vhca_id = peer_id;
106be53b 640 hpe->prio = match_prio;
5c65c564
OG		 641
642 params.log_data_size = 15;
643 params.log_data_size = min_t(u8, params.log_data_size,
644 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
645 params.log_data_size = max_t(u8, params.log_data_size,
646 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 647
eb9180f7
OG		 648 params.log_num_packets = params.log_data_size -
649 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
650 params.log_num_packets = min_t(u8, params.log_num_packets,
651 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
652
653 params.q_counter = priv->q_counter;
3f6d08d1 654 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 655 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 656 link_speed = max_t(u32, link_speed, 50000);
657 link_speed64 = link_speed;
658 do_div(link_speed64, 50000);
659 params.num_channels = link_speed64;
660
5c65c564
OG		 661 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
662 if (IS_ERR(hp)) {
663 err = PTR_ERR(hp);
664 goto create_hairpin_err;
665 }
666
eb9180f7 667 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 668 hp->tirn, hp->pair->rqn[0],
669 dev_name(hp->pair->peer_mdev->device),
eb9180f7 670 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 671
672 hpe->hp = hp;
106be53b
OG		 673 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
674 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 675
676attach_flow:
3f6d08d1
OG		 677 if (hpe->hp->num_channels > 1) {
678 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
679 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
680 } else {
681 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
682 }
5c65c564 683 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 684
5c65c564
OG		 685 return 0;
686
687create_hairpin_err:
688 kfree(hpe);
689 return err;
690}
691
692static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
693 struct mlx5e_tc_flow *flow)
694{
695 struct list_head *next = flow->hairpin.next;
696
697 list_del(&flow->hairpin);
698
699 /* no more hairpin flows for us, release the hairpin pair */
700 if (list_empty(next)) {
701 struct mlx5e_hairpin_entry *hpe;
702
703 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
704
705 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
27b942fb 706 dev_name(hpe->hp->pair->peer_mdev->device));
5c65c564
OG		 707
708 mlx5e_hairpin_destroy(hpe->hp);
709 hash_del(&hpe->hairpin_hlist);
710 kfree(hpe);
711 }
712}
713
c83954ab 714static int
74491de9 715mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 716 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 717 struct mlx5e_tc_flow *flow,
718 struct netlink_ext_ack *extack)
e8f887ac 719{
bb0ee7dc 720 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 721 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 722 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 723 struct mlx5_flow_destination dest[2] = {};
66958ed9 724 struct mlx5_flow_act flow_act = {
3bc4b7bf 725 .action = attr->action,
60786f09 726 .reformat_id = 0,
bb0ee7dc 727 .flags = FLOW_ACT_NO_APPEND,
66958ed9 728 };
aad7e08d 729 struct mlx5_fc *counter = NULL;
e8f887ac 730 bool table_created = false;
5c65c564 731 int err, dest_ix = 0;
e8f887ac 732
bb0ee7dc
JL		 733 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
734 flow_context->flow_tag = attr->flow_tag;
735
3f6d08d1 736 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 737 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 738 if (err) {
3f6d08d1
OG		 739 goto err_add_hairpin_flow;
740 }
741 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
742 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
743 dest[dest_ix].ft = attr->hairpin_ft;
744 } else {
5c65c564
OG		 745 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
746 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 747 }
748 dest_ix++;
3f6d08d1
OG		 749 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
750 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
751 dest[dest_ix].ft = priv->fs.vlan.ft.t;
752 dest_ix++;
5c65c564 753 }
aad7e08d 754
5c65c564
OG		 755 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
756 counter = mlx5_fc_create(dev, true);
757 if (IS_ERR(counter)) {
c83954ab 758 err = PTR_ERR(counter);
5c65c564
OG		 759 goto err_fc_create;
760 }
761 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 762 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 763 dest_ix++;
b8aee822 764 attr->counter = counter;
aad7e08d
AV		 765 }
766
2f4fe4ca 767 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 768 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 769 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 770 kfree(parse_attr->mod_hdr_actions);
c83954ab 771 if (err)
2f4fe4ca 772 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 773 }
774
acff797c 775 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 776 int tc_grp_size, tc_tbl_size;
777 u32 max_flow_counter;
778
779 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
780 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
781
782 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
783
784 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
785 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
786
acff797c
MG		 787 priv->fs.tc.t =
788 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
789 MLX5E_TC_PRIO,
21b9c144 790 tc_tbl_size,
acff797c 791 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 792 MLX5E_TC_FT_LEVEL, 0);
acff797c 793 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 794 NL_SET_ERR_MSG_MOD(extack,
795 "Failed to create tc offload table\n");
e8f887ac
AV		 796 netdev_err(priv->netdev,
797 "Failed to create tc offload table\n");
c83954ab 798 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 799 goto err_create_ft;
e8f887ac
AV		 800 }
801
802 table_created = true;
803 }
804
38aa51c1 805 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 806 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 807
c83954ab
RL		 808 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
809 &flow_act, dest, dest_ix);
aad7e08d 810
c83954ab
RL		 811 if (IS_ERR(flow->rule[0])) {
812 err = PTR_ERR(flow->rule[0]);
aad7e08d 813 goto err_add_rule;
c83954ab 814 }
aad7e08d 815
c83954ab 816 return 0;
e8f887ac 817
aad7e08d
AV		 818err_add_rule:
819 if (table_created) {
acff797c
MG		 820 mlx5_destroy_flow_table(priv->fs.tc.t);
821 priv->fs.tc.t = NULL;
e8f887ac 822 }
aad7e08d 823err_create_ft:
2f4fe4ca 824 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 825 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 826err_create_mod_hdr_id:
aad7e08d 827 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 828err_fc_create:
829 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
830 mlx5e_hairpin_flow_del(priv, flow);
831err_add_hairpin_flow:
c83954ab 832 return err;
e8f887ac
AV		 833}
834
d85cdccb
OG		 835static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
836 struct mlx5e_tc_flow *flow)
837{
513f8f7f 838 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 839 struct mlx5_fc *counter = NULL;
840
b8aee822 841 counter = attr->counter;
e4ad91f2 842 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 843 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 844
d9ee0491 845 if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) {
d85cdccb
OG		 846 mlx5_destroy_flow_table(priv->fs.tc.t);
847 priv->fs.tc.t = NULL;
848 }
2f4fe4ca 849
513f8f7f 850 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 851 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 852
853 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
854 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 855}
856
aa0cbbae 857static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 858 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 859
3c37745e 860static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 861 struct mlx5e_tc_flow *flow,
733d4f36
RD		 862 struct net_device *mirred_dev,
863 int out_index,
8c4dc42b 864 struct netlink_ext_ack *extack,
0ad060ee
RD		 865 struct net_device **encap_dev,
866 bool *encap_valid);
3c37745e 867
6d2a3ed0
OG		 868static struct mlx5_flow_handle *
869mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
870 struct mlx5e_tc_flow *flow,
871 struct mlx5_flow_spec *spec,
872 struct mlx5_esw_flow_attr *attr)
873{
874 struct mlx5_flow_handle *rule;
875
876 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
877 if (IS_ERR(rule))
878 return rule;
879
e85e02ba 880 if (attr->split_count) {
6d2a3ed0
OG		 881 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
882 if (IS_ERR(flow->rule[1])) {
883 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
884 return flow->rule[1];
885 }
886 }
887
888 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
889 return rule;
890}
891
892static void
893mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
894 struct mlx5e_tc_flow *flow,
895 struct mlx5_esw_flow_attr *attr)
896{
897 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
898
e85e02ba 899 if (attr->split_count)
6d2a3ed0
OG		 900 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
901
902 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
903}
904
5dbe906f
PB		 905static struct mlx5_flow_handle *
906mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
907 struct mlx5e_tc_flow *flow,
908 struct mlx5_flow_spec *spec,
909 struct mlx5_esw_flow_attr *slow_attr)
910{
911 struct mlx5_flow_handle *rule;
912
913 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 914 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 915 slow_attr->split_count = 0;
154e62ab 916 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 917
918 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
919 if (!IS_ERR(rule))
920 flow->flags |= MLX5E_TC_FLOW_SLOW;
921
922 return rule;
923}
924
925static void
926mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
927 struct mlx5e_tc_flow *flow,
928 struct mlx5_esw_flow_attr *slow_attr)
929{
930 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 931 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 932 slow_attr->split_count = 0;
154e62ab 933 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 934 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
935 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
936}
937
b4a23329
RD		 938static void add_unready_flow(struct mlx5e_tc_flow *flow)
939{
940 struct mlx5_rep_uplink_priv *uplink_priv;
941 struct mlx5e_rep_priv *rpriv;
942 struct mlx5_eswitch *esw;
943
944 esw = flow->priv->mdev->priv.eswitch;
945 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
946 uplink_priv = &rpriv->uplink_priv;
947
948 flow->flags |= MLX5E_TC_FLOW_NOT_READY;
949 list_add_tail(&flow->unready, &uplink_priv->unready_flows);
950}
951
952static void remove_unready_flow(struct mlx5e_tc_flow *flow)
953{
954 list_del(&flow->unready);
955 flow->flags &= ~MLX5E_TC_FLOW_NOT_READY;
956}
957
c83954ab 958static int
74491de9 959mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 960 struct mlx5e_tc_flow *flow,
961 struct netlink_ext_ack *extack)
adb4c123
OG		 962{
963 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 964 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 965 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 966 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 967 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 968 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 969 struct mlx5_fc *counter = NULL;
3c37745e
OG		 970 struct mlx5e_rep_priv *rpriv;
971 struct mlx5e_priv *out_priv;
0ad060ee
RD		 972 bool encap_valid = true;
973 int err = 0;
f493f155 974 int out_index;
8b32580d 975
d14f6f2a
OG		 976 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
977 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
978 return -EOPNOTSUPP;
979 }
bf07aa73
PB		 980
981 if (attr->chain > max_chain) {
982 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
983 err = -EOPNOTSUPP;
984 goto err_max_prio_chain;
985 }
986
987 if (attr->prio > max_prio) {
988 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
989 err = -EOPNOTSUPP;
990 goto err_max_prio_chain;
991 }
e52c2802 992
f493f155 993 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 994 int mirred_ifindex;
995
f493f155
EB		 996 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
997 continue;
998
7040632d 999 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1000 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1001 mirred_ifindex);
733d4f36 1002 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1003 extack, &encap_dev, &encap_valid);
1004 if (err)
c83954ab 1005 goto err_attach_encap;
0ad060ee 1006
3c37745e
OG		 1007 out_priv = netdev_priv(encap_dev);
1008 rpriv = out_priv->ppriv;
1cc26d74
EB		 1009 attr->dests[out_index].rep = rpriv->rep;
1010 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1011 }
1012
8b32580d 1013 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1014 if (err)
aa0cbbae 1015 goto err_add_vlan;
adb4c123 1016
d7e75a32 1017 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1018 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1019 kfree(parse_attr->mod_hdr_actions);
c83954ab 1020 if (err)
d7e75a32 1021 goto err_mod_hdr;
d7e75a32
OG		 1022 }
1023
b8aee822 1024 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1025 counter = mlx5_fc_create(attr->counter_dev, true);
b8aee822 1026 if (IS_ERR(counter)) {
c83954ab 1027 err = PTR_ERR(counter);
b8aee822
MB		 1028 goto err_create_counter;
1029 }
1030
1031 attr->counter = counter;
1032 }
1033
0ad060ee
RD		 1034 /* we get here if one of the following takes place:
1035 * (1) there's no error
1036 * (2) there's an encap action and we don't have valid neigh
3c37745e 1037 */
0ad060ee 1038 if (!encap_valid) {
5dbe906f
PB		 1039 /* continue with goto slow path rule instead */
1040 struct mlx5_esw_flow_attr slow_attr;
1041
1042 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1043 } else {
6d2a3ed0 1044 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1045 }
c83954ab 1046
5dbe906f
PB		 1047 if (IS_ERR(flow->rule[0])) {
1048 err = PTR_ERR(flow->rule[0]);
1049 goto err_add_rule;
1050 }
1051
1052 return 0;
aa0cbbae
OG		 1053
1054err_add_rule:
f9392795 1055 mlx5_fc_destroy(attr->counter_dev, counter);
b8aee822 1056err_create_counter:
513f8f7f 1057 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1058 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 1059err_mod_hdr:
aa0cbbae
OG		 1060 mlx5_eswitch_del_vlan_action(esw, attr);
1061err_add_vlan:
f493f155 1062 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1063 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1064 mlx5e_detach_encap(priv, flow, out_index);
3c37745e 1065err_attach_encap:
bf07aa73 1066err_max_prio_chain:
c83954ab 1067 return err;
aa0cbbae 1068}
d85cdccb 1069
9272e3df
YK		 1070static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1071{
1072 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1073 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1074 spec->match_value,
1075 misc_parameters_3);
1076 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1077 headers_v,
1078 geneve_tlv_option_0_data);
1079
1080 return !!geneve_tlv_opt_0_data;
1081}
1082
d85cdccb
OG		 1083static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1084 struct mlx5e_tc_flow *flow)
1085{
1086 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1087 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1088 struct mlx5_esw_flow_attr slow_attr;
f493f155 1089 int out_index;
d85cdccb 1090
ef06c9ee 1091 if (flow->flags & MLX5E_TC_FLOW_NOT_READY) {
b4a23329 1092 remove_unready_flow(flow);
ef06c9ee
RD		 1093 kvfree(attr->parse_attr);
1094 return;
1095 }
1096
5dbe906f
PB		 1097 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1098 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1099 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1100 else
1101 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1102 }
d85cdccb 1103
9272e3df
YK		 1104 if (mlx5_flow_has_geneve_opt(flow))
1105 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1106
513f8f7f 1107 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1108
f493f155 1109 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1110 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1111 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1112 kvfree(attr->parse_attr);
d7e75a32 1113
513f8f7f 1114 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1115 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1116
1117 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1118 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1119}
1120
232c0013
HHZ		 1121void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1122 struct mlx5e_encap_entry *e)
1123{
3c37745e 1124 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1125 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1126 struct mlx5_flow_handle *rule;
1127 struct mlx5_flow_spec *spec;
79baaec7 1128 struct encap_flow_item *efi;
232c0013
HHZ		 1129 struct mlx5e_tc_flow *flow;
1130 int err;
1131
54c177ca
OS		 1132 err = mlx5_packet_reformat_alloc(priv->mdev,
1133 e->reformat_type,
60786f09 1134 e->encap_size, e->encap_header,
31ca3648 1135 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1136 &e->encap_id);
232c0013
HHZ		 1137 if (err) {
1138 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1139 err);
1140 return;
1141 }
1142 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1143 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1144
79baaec7 1145 list_for_each_entry(efi, &e->flows, list) {
8c4dc42b
EB		 1146 bool all_flow_encaps_valid = true;
1147 int i;
1148
79baaec7 1149 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
3c37745e 1150 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1151 spec = &esw_attr->parse_attr->spec;
1152
8c4dc42b
EB		 1153 esw_attr->dests[efi->index].encap_id = e->encap_id;
1154 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1155 /* Flow can be associated with multiple encap entries.
1156 * Before offloading the flow verify that all of them have
1157 * a valid neighbour.
1158 */
1159 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1160 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1161 continue;
1162 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1163 all_flow_encaps_valid = false;
1164 break;
1165 }
1166 }
1167 /* Do not offload flows with unresolved neighbors */
1168 if (!all_flow_encaps_valid)
1169 continue;
5dbe906f 1170 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1171 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1172 if (IS_ERR(rule)) {
1173 err = PTR_ERR(rule);
232c0013
HHZ		 1174 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1175 err);
1176 continue;
1177 }
5dbe906f
PB		 1178
1179 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1180 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1181 flow->rule[0] = rule;
232c0013
HHZ		 1182 }
1183}
1184
1185void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1186 struct mlx5e_encap_entry *e)
1187{
3c37745e 1188 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1189 struct mlx5_esw_flow_attr slow_attr;
1190 struct mlx5_flow_handle *rule;
1191 struct mlx5_flow_spec *spec;
79baaec7 1192 struct encap_flow_item *efi;
232c0013 1193 struct mlx5e_tc_flow *flow;
5dbe906f 1194 int err;
232c0013 1195
79baaec7
EB		 1196 list_for_each_entry(efi, &e->flows, list) {
1197 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5dbe906f
PB		 1198 spec = &flow->esw_attr->parse_attr->spec;
1199
1200 /* update from encap rule to slow path rule */
1201 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1202 /* mark the flow's encap dest as non-valid */
1203 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1204
1205 if (IS_ERR(rule)) {
1206 err = PTR_ERR(rule);
1207 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1208 err);
1209 continue;
1210 }
1211
1212 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1213 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1214 flow->rule[0] = rule;
232c0013
HHZ		 1215 }
1216
61c806da
OG		 1217 /* we know that the encap is valid */
1218 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1219 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1220}
1221
b8aee822
MB		 1222static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1223{
1224 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1225 return flow->esw_attr->counter;
1226 else
1227 return flow->nic_attr->counter;
1228}
1229
f6dfb4c3
HHZ		 1230void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1231{
1232 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1233 u64 bytes, packets, lastuse = 0;
1234 struct mlx5e_tc_flow *flow;
1235 struct mlx5e_encap_entry *e;
1236 struct mlx5_fc *counter;
1237 struct neigh_table *tbl;
1238 bool neigh_used = false;
1239 struct neighbour *n;
1240
1241 if (m_neigh->family == AF_INET)
1242 tbl = &arp_tbl;
1243#if IS_ENABLED(CONFIG_IPV6)
1244 else if (m_neigh->family == AF_INET6)
423c9db2 1245 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1246#endif
1247 else
1248 return;
1249
1250 list_for_each_entry(e, &nhe->encap_list, encap_list) {
79baaec7 1251 struct encap_flow_item *efi;
f6dfb4c3
HHZ		 1252 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1253 continue;
79baaec7
EB		 1254 list_for_each_entry(efi, &e->flows, list) {
1255 flow = container_of(efi, struct mlx5e_tc_flow,
1256 encaps[efi->index]);
f6dfb4c3 1257 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1258 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1259 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1260 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1261 neigh_used = true;
1262 break;
1263 }
1264 }
1265 }
e36d4810
RD		 1266 if (neigh_used)
1267 break;
f6dfb4c3
HHZ		 1268 }
1269
1270 if (neigh_used) {
1271 nhe->reported_lastuse = jiffies;
1272
1273 /* find the relevant neigh according to the cached device and
1274 * dst ip pair
1275 */
1276 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1277 if (!n)
f6dfb4c3 1278 return;
f6dfb4c3
HHZ		 1279
1280 neigh_event_send(n, NULL);
1281 neigh_release(n);
1282 }
1283}
1284
d85cdccb 1285static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1286 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1287{
8c4dc42b 1288 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1289
8c4dc42b 1290 list_del(&flow->encaps[out_index].list);
5067b602 1291 if (list_empty(next)) {
c1ae1152 1292 struct mlx5e_encap_entry *e;
5067b602 1293
c1ae1152 1294 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1295 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1296
1297 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1298 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1299
cdc5a7f3 1300 hash_del_rcu(&e->encap_hlist);
232c0013 1301 kfree(e->encap_header);
5067b602
RD		 1302 kfree(e);
1303 }
1304}
1305
04de7dda
RD		 1306static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1307{
1308 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1309
1310 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1311 !(flow->flags & MLX5E_TC_FLOW_DUP))
1312 return;
1313
1314 mutex_lock(&esw->offloads.peer_mutex);
1315 list_del(&flow->peer);
1316 mutex_unlock(&esw->offloads.peer_mutex);
1317
1318 flow->flags &= ~MLX5E_TC_FLOW_DUP;
1319
1320 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1321 kvfree(flow->peer_flow);
1322 flow->peer_flow = NULL;
1323}
1324
1325static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1326{
1327 struct mlx5_core_dev *dev = flow->priv->mdev;
1328 struct mlx5_devcom *devcom = dev->priv.devcom;
1329 struct mlx5_eswitch *peer_esw;
1330
1331 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1332 if (!peer_esw)
1333 return;
1334
1335 __mlx5e_tc_del_fdb_peer_flow(flow);
1336 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1337}
1338
e8f887ac 1339static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1340 struct mlx5e_tc_flow *flow)
e8f887ac 1341{
04de7dda
RD		 1342 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1343 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1344 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1345 } else {
d85cdccb 1346 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1347 }
e8f887ac
AV		 1348}
1349
bbd00f7e
HHZ		 1350
1351static int parse_tunnel_attr(struct mlx5e_priv *priv,
1352 struct mlx5_flow_spec *spec,
54c177ca 1353 struct tc_cls_flower_offload *f,
6363651d 1354 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1355{
e98bedf5 1356 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1357 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1358 outer_headers);
1359 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1360 outer_headers);
8f256622 1361 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
8f256622 1362 int err;
2e72eb43 1363
101f4de9 1364 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1365 headers_c, headers_v, match_level);
54c177ca
OS		 1366 if (err) {
1367 NL_SET_ERR_MSG_MOD(extack,
1368 "failed to parse tunnel attributes");
101f4de9 1369 return err;
bbd00f7e
HHZ		 1370 }
1371
d1bda7ee 1372 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
8f256622
PNA		 1373 struct flow_match_ipv4_addrs match;
1374
1375 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1376 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1377 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1378 ntohl(match.mask->src));
bbd00f7e
HHZ		 1379 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1380 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1381 ntohl(match.key->src));
bbd00f7e
HHZ		 1382
1383 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1384 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1385 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1386 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1387 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1388 ntohl(match.key->dst));
bbd00f7e 1389
2e72eb43
OG		 1390 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1391 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
d1bda7ee 1392 } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
8f256622 1393 struct flow_match_ipv6_addrs match;
19f44401 1394
8f256622 1395 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1396 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1397 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1398 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1399 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1400 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1401 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1402
1403 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1404 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1405 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1406 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1407 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1408 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1409
1410 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1412 }
bbd00f7e 1413
8f256622
PNA		 1414 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1415 struct flow_match_ip match;
bcef735c 1416
8f256622
PNA		 1417 flow_rule_match_enc_ip(rule, &match);
1418 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1419 match.mask->tos & 0x3);
1420 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1421 match.key->tos & 0x3);
bcef735c 1422
8f256622
PNA		 1423 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1424 match.mask->tos >> 2);
1425 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1426 match.key->tos >> 2);
bcef735c 1427
8f256622
PNA		 1428 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1429 match.mask->ttl);
1430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1431 match.key->ttl);
e98bedf5 1432
8f256622 1433 if (match.mask->ttl &&
e98bedf5
EB		 1434 !MLX5_CAP_ESW_FLOWTABLE_FDB
1435 (priv->mdev,
1436 ft_field_support.outer_ipv4_ttl)) {
1437 NL_SET_ERR_MSG_MOD(extack,
1438 "Matching on TTL is not supported");
1439 return -EOPNOTSUPP;
1440 }
1441
bcef735c
OG		 1442 }
1443
bbd00f7e
HHZ		 1444 /* Enforce DMAC when offloading incoming tunneled flows.
1445 * Flow counters require a match on the DMAC.
1446 */
1447 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1448 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1449 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1450 dmac_47_16), priv->netdev->dev_addr);
1451
1452 /* let software handle IP fragments */
1453 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1455
1456 return 0;
1457}
1458
8377629e
EB		 1459static void *get_match_headers_criteria(u32 flags,
1460 struct mlx5_flow_spec *spec)
1461{
1462 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1463 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1464 inner_headers) :
1465 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1466 outer_headers);
1467}
1468
1469static void *get_match_headers_value(u32 flags,
1470 struct mlx5_flow_spec *spec)
1471{
1472 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1473 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1474 inner_headers) :
1475 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1476 outer_headers);
1477}
1478
de0af0bf
RD		 1479static int __parse_cls_flower(struct mlx5e_priv *priv,
1480 struct mlx5_flow_spec *spec,
1481 struct tc_cls_flower_offload *f,
54c177ca 1482 struct net_device *filter_dev,
6363651d 1483 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1484{
e98bedf5 1485 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1486 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1487 outer_headers);
1488 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1489 outer_headers);
699e96dd
JL		 1490 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1491 misc_parameters);
1492 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1493 misc_parameters);
8f256622
PNA		 1494 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
1495 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1496 u16 addr_type = 0;
1497 u8 ip_proto = 0;
1498
d708f902 1499 *match_level = MLX5_MATCH_NONE;
de0af0bf 1500
8f256622 1501 if (dissector->used_keys &
e3a2b7ed
AV		 1502 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1503 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1504 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1505 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1506 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1507 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1508 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1509 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1510 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1511 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1512 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1513 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1514 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1515 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1516 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1517 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1518 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1519 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1520 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1521 dissector->used_keys);
e3a2b7ed
AV		 1522 return -EOPNOTSUPP;
1523 }
1524
d1bda7ee
TZ		 1525 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1526 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) ||
1527 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
9272e3df
YK		 1528 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS) ||
1529 flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_OPTS)) {
d1bda7ee 1530 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e 1531 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1532
1533 /* In decap flow, header pointers should point to the inner
1534 * headers, outer header were already set by parse_tunnel_attr
1535 */
8377629e
EB		 1536 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1537 spec);
1538 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1539 spec);
bbd00f7e
HHZ		 1540 }
1541
8f256622
PNA		 1542 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1543 struct flow_match_basic match;
1544
1545 flow_rule_match_basic(rule, &match);
d3a80bb5 1546 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1547 ntohs(match.mask->n_proto));
d3a80bb5 1548 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1549 ntohs(match.key->n_proto));
e3a2b7ed 1550
8f256622 1551 if (match.mask->n_proto)
d708f902 1552 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1553 }
35a605db
EB		 1554 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1555 is_vlan_dev(filter_dev)) {
1556 struct flow_dissector_key_vlan filter_dev_mask;
1557 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1558 struct flow_match_vlan match;
1559
35a605db
EB		 1560 if (is_vlan_dev(filter_dev)) {
1561 match.key = &filter_dev_key;
1562 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1563 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1564 match.key->vlan_priority = 0;
1565 match.mask = &filter_dev_mask;
1566 memset(match.mask, 0xff, sizeof(*match.mask));
1567 match.mask->vlan_priority = 0;
1568 } else {
1569 flow_rule_match_vlan(rule, &match);
1570 }
8f256622
PNA		 1571 if (match.mask->vlan_id ||
1572 match.mask->vlan_priority ||
1573 match.mask->vlan_tpid) {
1574 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1575 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1576 svlan_tag, 1);
1577 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1578 svlan_tag, 1);
1579 } else {
1580 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1581 cvlan_tag, 1);
1582 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1583 cvlan_tag, 1);
1584 }
095b6cfd 1585
8f256622
PNA		 1586 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1587 match.mask->vlan_id);
1588 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1589 match.key->vlan_id);
358d79a4 1590
8f256622
PNA		 1591 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1592 match.mask->vlan_priority);
1593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1594 match.key->vlan_priority);
54782900 1595
d708f902 1596 *match_level = MLX5_MATCH_L2;
54782900 1597 }
d3a80bb5 1598 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1599 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1600 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1601 *match_level = MLX5_MATCH_L2;
54782900
OG		 1602 }
1603
8f256622
PNA		 1604 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1605 struct flow_match_vlan match;
1606
12d5cbf8 1607 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1608 if (match.mask->vlan_id ||
1609 match.mask->vlan_priority ||
1610 match.mask->vlan_tpid) {
1611 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1612 MLX5_SET(fte_match_set_misc, misc_c,
1613 outer_second_svlan_tag, 1);
1614 MLX5_SET(fte_match_set_misc, misc_v,
1615 outer_second_svlan_tag, 1);
1616 } else {
1617 MLX5_SET(fte_match_set_misc, misc_c,
1618 outer_second_cvlan_tag, 1);
1619 MLX5_SET(fte_match_set_misc, misc_v,
1620 outer_second_cvlan_tag, 1);
1621 }
1622
1623 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1624 match.mask->vlan_id);
699e96dd 1625 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1626 match.key->vlan_id);
699e96dd 1627 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1628 match.mask->vlan_priority);
699e96dd 1629 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1630 match.key->vlan_priority);
699e96dd
JL		 1631
1632 *match_level = MLX5_MATCH_L2;
1633 }
1634 }
1635
8f256622
PNA		 1636 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1637 struct flow_match_eth_addrs match;
54782900 1638
8f256622 1639 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1640 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1641 dmac_47_16),
8f256622 1642 match.mask->dst);
d3a80bb5
OG		 1643 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1644 dmac_47_16),
8f256622 1645 match.key->dst);
d3a80bb5
OG		 1646
1647 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1648 smac_47_16),
8f256622 1649 match.mask->src);
d3a80bb5
OG		 1650 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1651 smac_47_16),
8f256622 1652 match.key->src);
d3a80bb5 1653
8f256622
PNA		 1654 if (!is_zero_ether_addr(match.mask->src) ||
1655 !is_zero_ether_addr(match.mask->dst))
d708f902 1656 *match_level = MLX5_MATCH_L2;
54782900
OG		 1657 }
1658
8f256622
PNA		 1659 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1660 struct flow_match_control match;
54782900 1661
8f256622
PNA		 1662 flow_rule_match_control(rule, &match);
1663 addr_type = match.key->addr_type;
54782900
OG		 1664
1665 /* the HW doesn't support frag first/later */
8f256622 1666 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1667 return -EOPNOTSUPP;
1668
8f256622 1669 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1670 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1672 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1673
1674 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1675 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1676 *match_level = MLX5_MATCH_L2;
54782900
OG		 1677 /* *** L2 attributes parsing up to here *** */
1678 else
83621b7d 1679 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1680 }
1681 }
1682
8f256622
PNA		 1683 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1684 struct flow_match_basic match;
1685
1686 flow_rule_match_basic(rule, &match);
1687 ip_proto = match.key->ip_proto;
54782900
OG		 1688
1689 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1690 match.mask->ip_proto);
54782900 1691 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1692 match.key->ip_proto);
54782900 1693
8f256622 1694 if (match.mask->ip_proto)
d708f902 1695 *match_level = MLX5_MATCH_L3;
54782900
OG		 1696 }
1697
e3a2b7ed 1698 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1699 struct flow_match_ipv4_addrs match;
e3a2b7ed 1700
8f256622 1701 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1702 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1703 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1704 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1705 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1706 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1707 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1708 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1709 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1710 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1711 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1712 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1713 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1714
8f256622 1715 if (match.mask->src || match.mask->dst)
d708f902 1716 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1717 }
1718
1719 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1720 struct flow_match_ipv6_addrs match;
e3a2b7ed 1721
8f256622 1722 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1723 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1724 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1725 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1726 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1727 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1728 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1729
1730 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1731 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1732 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1733 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1734 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1735 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1736
8f256622
PNA		 1737 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1738 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1739 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1740 }
1741
8f256622
PNA		 1742 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1743 struct flow_match_ip match;
1f97a526 1744
8f256622
PNA		 1745 flow_rule_match_ip(rule, &match);
1746 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1747 match.mask->tos & 0x3);
1748 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1749 match.key->tos & 0x3);
1f97a526 1750
8f256622
PNA		 1751 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1752 match.mask->tos >> 2);
1753 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1754 match.key->tos >> 2);
1f97a526 1755
8f256622
PNA		 1756 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1757 match.mask->ttl);
1758 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1759 match.key->ttl);
1f97a526 1760
8f256622 1761 if (match.mask->ttl &&
a8ade55f 1762 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1763 ft_field_support.outer_ipv4_ttl)) {
1764 NL_SET_ERR_MSG_MOD(extack,
1765 "Matching on TTL is not supported");
1f97a526 1766 return -EOPNOTSUPP;
e98bedf5 1767 }
a8ade55f 1768
8f256622 1769 if (match.mask->tos || match.mask->ttl)
d708f902 1770 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1771 }
1772
54782900
OG		 1773 /* *** L3 attributes parsing up to here *** */
1774
8f256622
PNA		 1775 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1776 struct flow_match_ports match;
1777
1778 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1779 switch (ip_proto) {
1780 case IPPROTO_TCP:
1781 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1782 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1783 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1784 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1785
1786 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1787 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1788 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1789 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1790 break;
1791
1792 case IPPROTO_UDP:
1793 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1794 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1795 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1796 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1797
1798 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1799 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1800 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1801 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1802 break;
1803 default:
e98bedf5
EB		 1804 NL_SET_ERR_MSG_MOD(extack,
1805 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1806 netdev_err(priv->netdev,
1807 "Only UDP and TCP transport are supported\n");
1808 return -EINVAL;
1809 }
de0af0bf 1810
8f256622 1811 if (match.mask->src || match.mask->dst)
d708f902 1812 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1813 }
1814
8f256622
PNA		 1815 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1816 struct flow_match_tcp match;
e77834ec 1817
8f256622 1818 flow_rule_match_tcp(rule, &match);
e77834ec 1819 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1820 ntohs(match.mask->flags));
e77834ec 1821 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1822 ntohs(match.key->flags));
e77834ec 1823
8f256622 1824 if (match.mask->flags)
d708f902 1825 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1826 }
1827
e3a2b7ed
AV		 1828 return 0;
1829}
1830
de0af0bf 1831static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1832 struct mlx5e_tc_flow *flow,
de0af0bf 1833 struct mlx5_flow_spec *spec,
54c177ca
OS		 1834 struct tc_cls_flower_offload *f,
1835 struct net_device *filter_dev)
de0af0bf 1836{
e98bedf5 1837 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1838 struct mlx5_core_dev *dev = priv->mdev;
1839 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1840 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1841 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1842 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1843 int err;
1844
6363651d 1845 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 1846
1d447a39
SM		 1847 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1848 rep = rpriv->rep;
b05af6aa 1849 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 1850 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1851 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1852 NL_SET_ERR_MSG_MOD(extack,
1853 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1854 netdev_warn(priv->netdev,
1855 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1856 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1857 return -EOPNOTSUPP;
1858 }
1859 }
1860
6363651d 1861 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
38aa51c1 1862 flow->esw_attr->match_level = match_level;
6363651d
OG		 1863 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1864 } else {
38aa51c1 1865 flow->nic_attr->match_level = match_level;
6363651d 1866 }
38aa51c1 1867
de0af0bf
RD		 1868 return err;
1869}
1870
d79b6df6
OG		 1871struct pedit_headers {
1872 struct ethhdr eth;
0eb69bb9 1873 struct vlan_hdr vlan;
d79b6df6
OG		 1874 struct iphdr ip4;
1875 struct ipv6hdr ip6;
1876 struct tcphdr tcp;
1877 struct udphdr udp;
1878};
1879
c500c86b
PNA		 1880struct pedit_headers_action {
1881 struct pedit_headers vals;
1882 struct pedit_headers masks;
1883 u32 pedits;
1884};
1885
d79b6df6 1886static int pedit_header_offsets[] = {
73867881
PNA		 1887 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1888 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1889 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1890 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1891 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 1892};
1893
1894#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1895
1896static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 1897 struct pedit_headers_action *hdrs)
d79b6df6
OG		 1898{
1899 u32 *curr_pmask, *curr_pval;
1900
c500c86b
PNA		 1901 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
1902 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 1903
1904 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1905 goto out_err;
1906
1907 *curr_pmask |= mask;
1908 *curr_pval |= (val & mask);
1909
1910 return 0;
1911
1912out_err:
1913 return -EOPNOTSUPP;
1914}
1915
1916struct mlx5_fields {
1917 u8 field;
1918 u8 size;
1919 u32 offset;
27c11b6b 1920 u32 match_offset;
d79b6df6
OG		 1921};
1922
27c11b6b
EB		 1923#define OFFLOAD(fw_field, size, field, off, match_field) \
1924 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
1925 offsetof(struct pedit_headers, field) + (off), \
1926 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
1927
2ef86872
EB		 1928/* masked values are the same and there are no rewrites that do not have a
1929 * match.
1930 */
1931#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
1932 type matchmaskx = *(type *)(matchmaskp); \
1933 type matchvalx = *(type *)(matchvalp); \
1934 type maskx = *(type *)(maskp); \
1935 type valx = *(type *)(valp); \
1936 \
1937 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
1938 matchmaskx)); \
1939})
1940
27c11b6b
EB		 1941static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
1942 void *matchmaskp, int size)
1943{
1944 bool same = false;
1945
1946 switch (size) {
1947 case sizeof(u8):
2ef86872 1948 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 1949 break;
1950 case sizeof(u16):
2ef86872 1951 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 1952 break;
1953 case sizeof(u32):
2ef86872 1954 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 1955 break;
1956 }
1957
1958 return same;
1959}
a8e4f0c4 1960
d79b6df6 1961static struct mlx5_fields fields[] = {
27c11b6b
EB		 1962 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
1963 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
1964 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
1965 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
1966 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
1967 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
1968
1969 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
1970 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
1971 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1972
1973 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
1974 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
1975 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
1976 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
1977 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
1978 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
1979 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
1980 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
1981 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
1982 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
1983 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
1984 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
1985 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
1986 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
1987 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
1988 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
1989 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
1990
1991 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
1992 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
1993 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
1994
1995 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
1996 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
d79b6df6
OG		 1997};
1998
218d05ce
TZ		 1999/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2000 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2001 * says how many HW actions were actually parsed.
d79b6df6 2002 */
c500c86b 2003static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2004 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2005 u32 *action_flags,
e98bedf5 2006 struct netlink_ext_ack *extack)
d79b6df6
OG		 2007{
2008 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
27c11b6b
EB		 2009 void *headers_c = get_match_headers_criteria(*action_flags,
2010 &parse_attr->spec);
2011 void *headers_v = get_match_headers_value(*action_flags,
2012 &parse_attr->spec);
2b64beba 2013 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 2014 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 2015 struct mlx5_fields *f;
2016 u8 cmd, field_bsize;
e3ca4e05 2017 u32 s_mask, a_mask;
d79b6df6 2018 unsigned long mask;
2b64beba
OG		 2019 __be32 mask_be32;
2020 __be16 mask_be16;
d79b6df6
OG		 2021 void *action;
2022
73867881
PNA		 2023 set_masks = &hdrs[0].masks;
2024 add_masks = &hdrs[1].masks;
2025 set_vals = &hdrs[0].vals;
2026 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2027
2028 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2029 action = parse_attr->mod_hdr_actions +
2030 parse_attr->num_mod_hdr_actions * action_size;
2031
2032 max_actions = parse_attr->max_mod_hdr_actions;
2033 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2034
2035 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2036 bool skip;
2037
d79b6df6
OG		 2038 f = &fields[i];
2039 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2040 s_mask = 0;
2041 a_mask = 0;
d79b6df6
OG		 2042
2043 s_masks_p = (void *)set_masks + f->offset;
2044 a_masks_p = (void *)add_masks + f->offset;
2045
2046 memcpy(&s_mask, s_masks_p, f->size);
2047 memcpy(&a_mask, a_masks_p, f->size);
2048
2049 if (!s_mask && !a_mask) /* nothing to offload here */
2050 continue;
2051
2052 if (s_mask && a_mask) {
e98bedf5
EB		 2053 NL_SET_ERR_MSG_MOD(extack,
2054 "can't set and add to the same HW field");
d79b6df6
OG		 2055 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2056 return -EOPNOTSUPP;
2057 }
2058
2059 if (nactions == max_actions) {
e98bedf5
EB		 2060 NL_SET_ERR_MSG_MOD(extack,
2061 "too many pedit actions, can't offload");
d79b6df6
OG		 2062 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2063 return -EOPNOTSUPP;
2064 }
2065
27c11b6b 2066 skip = false;
d79b6df6 2067 if (s_mask) {
27c11b6b
EB		 2068 void *match_mask = headers_c + f->match_offset;
2069 void *match_val = headers_v + f->match_offset;
2070
d79b6df6
OG		 2071 cmd = MLX5_ACTION_TYPE_SET;
2072 mask = s_mask;
2073 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2074 /* don't rewrite if we have a match on the same value */
2075 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2076 match_mask, f->size))
2077 skip = true;
d79b6df6
OG		 2078 /* clear to denote we consumed this field */
2079 memset(s_masks_p, 0, f->size);
2080 } else {
27c11b6b
EB		 2081 u32 zero = 0;
2082
d79b6df6
OG		 2083 cmd = MLX5_ACTION_TYPE_ADD;
2084 mask = a_mask;
2085 vals_p = (void *)add_vals + f->offset;
27c11b6b
EB		 2086 /* add 0 is no change */
2087 if (!memcmp(vals_p, &zero, f->size))
2088 skip = true;
d79b6df6
OG		 2089 /* clear to denote we consumed this field */
2090 memset(a_masks_p, 0, f->size);
2091 }
27c11b6b
EB		 2092 if (skip)
2093 continue;
d79b6df6 2094
d79b6df6 2095 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2096
2b64beba
OG		 2097 if (field_bsize == 32) {
2098 mask_be32 = *(__be32 *)&mask;
2099 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2100 } else if (field_bsize == 16) {
2101 mask_be16 = *(__be16 *)&mask;
2102 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2103 }
2104
d79b6df6 2105 first = find_first_bit(&mask, field_bsize);
2b64beba 2106 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2107 last = find_last_bit(&mask, field_bsize);
2b64beba 2108 if (first < next_z && next_z < last) {
e98bedf5
EB		 2109 NL_SET_ERR_MSG_MOD(extack,
2110 "rewrite of few sub-fields isn't supported");
2b64beba 2111 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2112 mask);
2113 return -EOPNOTSUPP;
2114 }
2115
2116 MLX5_SET(set_action_in, action, action_type, cmd);
2117 MLX5_SET(set_action_in, action, field, f->field);
2118
2119 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2120 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2121 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2122 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2123 }
2124
2125 if (field_bsize == 32)
2b64beba 2126 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2127 else if (field_bsize == 16)
2b64beba 2128 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2129 else if (field_bsize == 8)
2b64beba 2130 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2131
2132 action += action_size;
2133 nactions++;
2134 }
2135
2136 parse_attr->num_mod_hdr_actions = nactions;
2137 return 0;
2138}
2139
2cc1cb1d
TZ		 2140static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2141 int namespace)
2142{
2143 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2144 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2145 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2146 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2147}
2148
d79b6df6 2149static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2150 struct pedit_headers_action *hdrs,
2151 int namespace,
d79b6df6
OG		 2152 struct mlx5e_tc_flow_parse_attr *parse_attr)
2153{
2154 int nkeys, action_size, max_actions;
2155
c500c86b
PNA		 2156 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2157 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2158 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2159
2cc1cb1d 2160 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2161 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2162 max_actions = min(max_actions, nkeys * 16);
2163
2164 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2165 if (!parse_attr->mod_hdr_actions)
2166 return -ENOMEM;
2167
218d05ce 2168 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2169 return 0;
2170}
2171
2172static const struct pedit_headers zero_masks = {};
2173
2174static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2175 const struct flow_action_entry *act, int namespace,
e98bedf5 2176 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2177 struct pedit_headers_action *hdrs,
e98bedf5 2178 struct netlink_ext_ack *extack)
d79b6df6 2179{
73867881
PNA		 2180 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2181 int err = -EOPNOTSUPP;
d79b6df6 2182 u32 mask, val, offset;
73867881 2183 u8 htype;
d79b6df6 2184
73867881
PNA		 2185 htype = act->mangle.htype;
2186 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2187
73867881
PNA		 2188 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2189 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2190 goto out_err;
2191 }
d79b6df6 2192
2cc1cb1d
TZ		 2193 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2194 NL_SET_ERR_MSG_MOD(extack,
2195 "The pedit offload action is not supported");
2196 goto out_err;
2197 }
2198
73867881
PNA		 2199 mask = act->mangle.mask;
2200 val = act->mangle.val;
2201 offset = act->mangle.offset;
d79b6df6 2202
73867881
PNA		 2203 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2204 if (err)
2205 goto out_err;
c500c86b 2206
73867881 2207 hdrs[cmd].pedits++;
d79b6df6 2208
c500c86b
PNA		 2209 return 0;
2210out_err:
2211 return err;
2212}
2213
2214static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2215 struct mlx5e_tc_flow_parse_attr *parse_attr,
2216 struct pedit_headers_action *hdrs,
27c11b6b 2217 u32 *action_flags,
c500c86b
PNA		 2218 struct netlink_ext_ack *extack)
2219{
2220 struct pedit_headers *cmd_masks;
2221 int err;
2222 u8 cmd;
2223
218d05ce 2224 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2225 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2226 if (err)
2227 goto out_err;
2228 }
d79b6df6 2229
27c11b6b 2230 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2231 if (err < 0)
2232 goto out_dealloc_parsed_actions;
2233
2234 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2235 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2236 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2237 NL_SET_ERR_MSG_MOD(extack,
2238 "attempt to offload an unsupported field");
b3a433de 2239 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2240 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2241 16, 1, cmd_masks, sizeof(zero_masks), true);
2242 err = -EOPNOTSUPP;
2243 goto out_dealloc_parsed_actions;
2244 }
2245 }
2246
2247 return 0;
2248
2249out_dealloc_parsed_actions:
2250 kfree(parse_attr->mod_hdr_actions);
2251out_err:
2252 return err;
2253}
2254
e98bedf5
EB		 2255static bool csum_offload_supported(struct mlx5e_priv *priv,
2256 u32 action,
2257 u32 update_flags,
2258 struct netlink_ext_ack *extack)
26c02749
OG		 2259{
2260 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2261 TCA_CSUM_UPDATE_FLAG_UDP;
2262
2263 /* The HW recalcs checksums only if re-writing headers */
2264 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2265 NL_SET_ERR_MSG_MOD(extack,
2266 "TC csum action is only offloaded with pedit");
26c02749
OG		 2267 netdev_warn(priv->netdev,
2268 "TC csum action is only offloaded with pedit\n");
2269 return false;
2270 }
2271
2272 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2273 NL_SET_ERR_MSG_MOD(extack,
2274 "can't offload TC csum action for some header/s");
26c02749
OG		 2275 netdev_warn(priv->netdev,
2276 "can't offload TC csum action for some header/s - flags %#x\n",
2277 update_flags);
2278 return false;
2279 }
2280
2281 return true;
2282}
2283
8998576b
DL		 2284struct ip_ttl_word {
2285 __u8 ttl;
2286 __u8 protocol;
2287 __sum16 check;
2288};
2289
2290struct ipv6_hoplimit_word {
2291 __be16 payload_len;
2292 __u8 nexthdr;
2293 __u8 hop_limit;
2294};
2295
2296static bool is_action_keys_supported(const struct flow_action_entry *act)
2297{
2298 u32 mask, offset;
2299 u8 htype;
2300
2301 htype = act->mangle.htype;
2302 offset = act->mangle.offset;
2303 mask = ~act->mangle.mask;
2304 /* For IPv4 & IPv6 header check 4 byte word,
2305 * to determine that modified fields
2306 * are NOT ttl & hop_limit only.
2307 */
2308 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2309 struct ip_ttl_word *ttl_word =
2310 (struct ip_ttl_word *)&mask;
2311
2312 if (offset != offsetof(struct iphdr, ttl) ||
2313 ttl_word->protocol ||
2314 ttl_word->check) {
2315 return true;
2316 }
2317 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2318 struct ipv6_hoplimit_word *hoplimit_word =
2319 (struct ipv6_hoplimit_word *)&mask;
2320
2321 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2322 hoplimit_word->payload_len ||
2323 hoplimit_word->nexthdr) {
2324 return true;
2325 }
2326 }
2327 return false;
2328}
2329
bdd66ac0 2330static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2331 struct flow_action *flow_action,
1651925d 2332 u32 actions,
e98bedf5 2333 struct netlink_ext_ack *extack)
bdd66ac0 2334{
73867881 2335 const struct flow_action_entry *act;
bdd66ac0 2336 bool modify_ip_header;
bdd66ac0
OG		 2337 void *headers_v;
2338 u16 ethertype;
8998576b 2339 u8 ip_proto;
73867881 2340 int i;
bdd66ac0 2341
8377629e 2342 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2343 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2344
2345 /* for non-IP we only re-write MACs, so we're okay */
2346 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2347 goto out_ok;
2348
2349 modify_ip_header = false;
73867881
PNA		 2350 flow_action_for_each(i, act, flow_action) {
2351 if (act->id != FLOW_ACTION_MANGLE &&
2352 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2353 continue;
2354
8998576b 2355 if (is_action_keys_supported(act)) {
73867881
PNA		 2356 modify_ip_header = true;
2357 break;
bdd66ac0
OG		 2358 }
2359 }
2360
2361 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2362 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2363 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2364 NL_SET_ERR_MSG_MOD(extack,
2365 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2366 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2367 return false;
2368 }
2369
2370out_ok:
2371 return true;
2372}
2373
2374static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2375 struct flow_action *flow_action,
bdd66ac0 2376 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2377 struct mlx5e_tc_flow *flow,
2378 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2379{
2380 u32 actions;
2381
2382 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2383 actions = flow->esw_attr->action;
2384 else
2385 actions = flow->nic_attr->action;
2386
7e29392e 2387 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
35a605db
EB		 2388 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2389 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)))
7e29392e
RD		 2390 return false;
2391
bdd66ac0 2392 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2393 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2394 flow_action, actions,
e98bedf5 2395 extack);
bdd66ac0
OG		 2396
2397 return true;
2398}
2399
5c65c564
OG		 2400static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2401{
2402 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2403 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2404
2405 fmdev = priv->mdev;
2406 pmdev = peer_priv->mdev;
2407
59c9d35e
AH		 2408 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2409 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2410
816f6706 2411 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2412}
2413
bdc837ee
EB		 2414static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2415 const struct flow_action_entry *act,
2416 struct mlx5e_tc_flow_parse_attr *parse_attr,
2417 struct pedit_headers_action *hdrs,
2418 u32 *action, struct netlink_ext_ack *extack)
2419{
2420 u16 mask16 = VLAN_VID_MASK;
2421 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2422 const struct flow_action_entry pedit_act = {
2423 .id = FLOW_ACTION_MANGLE,
2424 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2425 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2426 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2427 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2428 };
6fca9d1e 2429 u8 match_prio_mask, match_prio_val;
bf2f3bca 2430 void *headers_c, *headers_v;
bdc837ee
EB		 2431 int err;
2432
bf2f3bca
EB		 2433 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2434 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2435
2436 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2437 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2438 NL_SET_ERR_MSG_MOD(extack,
2439 "VLAN rewrite action must have VLAN protocol match");
2440 return -EOPNOTSUPP;
2441 }
2442
6fca9d1e
EB		 2443 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2444 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2445 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2446 NL_SET_ERR_MSG_MOD(extack,
2447 "Changing VLAN prio is not supported");
bdc837ee
EB		 2448 return -EOPNOTSUPP;
2449 }
2450
2451 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2452 hdrs, NULL);
2453 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2454
2455 return err;
2456}
2457
0bac1194
EB		 2458static int
2459add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2460 struct mlx5e_tc_flow_parse_attr *parse_attr,
2461 struct pedit_headers_action *hdrs,
2462 u32 *action, struct netlink_ext_ack *extack)
2463{
2464 const struct flow_action_entry prio_tag_act = {
2465 .vlan.vid = 0,
2466 .vlan.prio =
2467 MLX5_GET(fte_match_set_lyr_2_4,
2468 get_match_headers_value(*action,
2469 &parse_attr->spec),
2470 first_prio) &
2471 MLX5_GET(fte_match_set_lyr_2_4,
2472 get_match_headers_criteria(*action,
2473 &parse_attr->spec),
2474 first_prio),
2475 };
2476
2477 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2478 &prio_tag_act, parse_attr, hdrs, action,
2479 extack);
2480}
2481
73867881
PNA		 2482static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2483 struct flow_action *flow_action,
aa0cbbae 2484 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2485 struct mlx5e_tc_flow *flow,
2486 struct netlink_ext_ack *extack)
e3a2b7ed 2487{
aa0cbbae 2488 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2489 struct pedit_headers_action hdrs[2] = {};
2490 const struct flow_action_entry *act;
1cab1cd7 2491 u32 action = 0;
244cd96a 2492 int err, i;
e3a2b7ed 2493
73867881 2494 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2495 return -EINVAL;
2496
3bc4b7bf 2497 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2498
73867881
PNA		 2499 flow_action_for_each(i, act, flow_action) {
2500 switch (act->id) {
2501 case FLOW_ACTION_DROP:
1cab1cd7 2502 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2503 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2504 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2505 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2506 break;
2507 case FLOW_ACTION_MANGLE:
2508 case FLOW_ACTION_ADD:
2509 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2510 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2511 if (err)
2512 return err;
2513
1cab1cd7
OG		 2514 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2515 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2516 break;
bdc837ee
EB		 2517 case FLOW_ACTION_VLAN_MANGLE:
2518 err = add_vlan_rewrite_action(priv,
2519 MLX5_FLOW_NAMESPACE_KERNEL,
2520 act, parse_attr, hdrs,
2521 &action, extack);
2522 if (err)
2523 return err;
2524
2525 break;
73867881 2526 case FLOW_ACTION_CSUM:
1cab1cd7 2527 if (csum_offload_supported(priv, action,
73867881 2528 act->csum_flags,
e98bedf5 2529 extack))
73867881 2530 break;
26c02749
OG		 2531
2532 return -EOPNOTSUPP;
73867881
PNA		 2533 case FLOW_ACTION_REDIRECT: {
2534 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2535
2536 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2537 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2538 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
5c65c564 2539 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2540 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2541 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2542 } else {
e98bedf5
EB		 2543 NL_SET_ERR_MSG_MOD(extack,
2544 "device is not on same HW, can't offload");
5c65c564
OG		 2545 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2546 peer_dev->name);
2547 return -EINVAL;
2548 }
73867881
PNA		 2549 }
2550 break;
2551 case FLOW_ACTION_MARK: {
2552 u32 mark = act->mark;
e3a2b7ed
AV		 2553
2554 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2555 NL_SET_ERR_MSG_MOD(extack,
2556 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2557 return -EINVAL;
2558 }
2559
3bc4b7bf 2560 attr->flow_tag = mark;
1cab1cd7 2561 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2562 }
2563 break;
2564 default:
2cc1cb1d
TZ		 2565 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2566 return -EOPNOTSUPP;
e3a2b7ed 2567 }
e3a2b7ed
AV		 2568 }
2569
c500c86b
PNA		 2570 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2571 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2572 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2573 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2574 if (err)
2575 return err;
27c11b6b
EB		 2576 /* in case all pedit actions are skipped, remove the MOD_HDR
2577 * flag.
2578 */
e7739a60 2579 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2580 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2581 kfree(parse_attr->mod_hdr_actions);
2582 }
c500c86b
PNA		 2583 }
2584
1cab1cd7 2585 attr->action = action;
73867881 2586 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2587 return -EOPNOTSUPP;
2588
e3a2b7ed
AV		 2589 return 0;
2590}
2591
7f1a546e 2592struct encap_key {
1f6da306 2593 const struct ip_tunnel_key *ip_tun_key;
d386939a 2594 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2595};
2596
2597static inline int cmp_encap_info(struct encap_key *a,
2598 struct encap_key *b)
a54e20b4 2599{
7f1a546e 2600 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2601 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2602}
2603
7f1a546e 2604static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2605{
7f1a546e 2606 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2607 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 2608}
2609
a54e20b4 2610
b1d90e6b
RL		 2611static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2612 struct net_device *peer_netdev)
2613{
2614 struct mlx5e_priv *peer_priv;
2615
2616 peer_priv = netdev_priv(peer_netdev);
2617
2618 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2619 mlx5e_eswitch_rep(priv->netdev) &&
2620 mlx5e_eswitch_rep(peer_netdev) &&
2621 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2622}
2623
32f3671f 2624
f5bc2c5d 2625
a54e20b4 2626static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 2627 struct mlx5e_tc_flow *flow,
733d4f36
RD		 2628 struct net_device *mirred_dev,
2629 int out_index,
8c4dc42b 2630 struct netlink_ext_ack *extack,
0ad060ee
RD		 2631 struct net_device **encap_dev,
2632 bool *encap_valid)
a54e20b4
HHZ		 2633{
2634 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 2635 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 2636 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 2637 const struct ip_tunnel_info *tun_info;
7f1a546e 2638 struct encap_key key, e_key;
c1ae1152 2639 struct mlx5e_encap_entry *e;
733d4f36 2640 unsigned short family;
a54e20b4
HHZ		 2641 uintptr_t hash_key;
2642 bool found = false;
54c177ca 2643 int err = 0;
a54e20b4 2644
733d4f36 2645 parse_attr = attr->parse_attr;
1f6da306 2646 tun_info = parse_attr->tun_info[out_index];
733d4f36 2647 family = ip_tunnel_info_af(tun_info);
7f1a546e 2648 key.ip_tun_key = &tun_info->key;
d386939a 2649 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
733d4f36 2650
7f1a546e 2651 hash_key = hash_encap_info(&key);
a54e20b4
HHZ		 2652
2653 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2654 encap_hlist, hash_key) {
1f6da306 2655 e_key.ip_tun_key = &e->tun_info->key;
d386939a 2656 e_key.tc_tunnel = e->tunnel;
7f1a546e 2657 if (!cmp_encap_info(&e_key, &key)) {
a54e20b4
HHZ		 2658 found = true;
2659 break;
2660 }
2661 }
2662
b2812089 2663 /* must verify if encap is valid or not */
45247bf2
OG		 2664 if (found)
2665 goto attach_flow;
a54e20b4
HHZ		 2666
2667 e = kzalloc(sizeof(*e), GFP_KERNEL);
2668 if (!e)
2669 return -ENOMEM;
2670
1f6da306 2671 e->tun_info = tun_info;
101f4de9 2672 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2673 if (err)
2674 goto out_err;
2675
a54e20b4
HHZ		 2676 INIT_LIST_HEAD(&e->flows);
2677
ce99f6b9 2678 if (family == AF_INET)
101f4de9 2679 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2680 else if (family == AF_INET6)
101f4de9 2681 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2682
0ad060ee 2683 if (err)
a54e20b4
HHZ		 2684 goto out_err;
2685
a54e20b4
HHZ		 2686 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2687
45247bf2 2688attach_flow:
8c4dc42b
EB		 2689 list_add(&flow->encaps[out_index].list, &e->flows);
2690 flow->encaps[out_index].index = out_index;
45247bf2 2691 *encap_dev = e->out_dev;
8c4dc42b
EB		 2692 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2693 attr->dests[out_index].encap_id = e->encap_id;
2694 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 2695 *encap_valid = true;
8c4dc42b 2696 } else {
0ad060ee 2697 *encap_valid = false;
8c4dc42b 2698 }
45247bf2 2699
232c0013 2700 return err;
a54e20b4
HHZ		 2701
2702out_err:
2703 kfree(e);
2704 return err;
2705}
2706
1482bd3d 2707static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2708 const struct flow_action_entry *act,
1482bd3d
JL		 2709 struct mlx5_esw_flow_attr *attr,
2710 u32 *action)
2711{
cc495188
JL		 2712 u8 vlan_idx = attr->total_vlan;
2713
2714 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2715 return -EOPNOTSUPP;
2716
73867881
PNA		 2717 switch (act->id) {
2718 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2719 if (vlan_idx) {
2720 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2721 MLX5_FS_VLAN_DEPTH))
2722 return -EOPNOTSUPP;
2723
2724 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2725 } else {
2726 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2727 }
73867881
PNA		 2728 break;
2729 case FLOW_ACTION_VLAN_PUSH:
2730 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2731 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2732 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2733 if (!attr->vlan_proto[vlan_idx])
2734 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2735
2736 if (vlan_idx) {
2737 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2738 MLX5_FS_VLAN_DEPTH))
2739 return -EOPNOTSUPP;
2740
2741 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2742 } else {
2743 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2744 (act->vlan.proto != htons(ETH_P_8021Q) ||
2745 act->vlan.prio))
cc495188
JL		 2746 return -EOPNOTSUPP;
2747
2748 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2749 }
73867881
PNA		 2750 break;
2751 default:
bdc837ee 2752 return -EINVAL;
1482bd3d
JL		 2753 }
2754
cc495188
JL		 2755 attr->total_vlan = vlan_idx + 1;
2756
1482bd3d
JL		 2757 return 0;
2758}
2759
278748a9
EB		 2760static int add_vlan_push_action(struct mlx5e_priv *priv,
2761 struct mlx5_esw_flow_attr *attr,
2762 struct net_device **out_dev,
2763 u32 *action)
2764{
2765 struct net_device *vlan_dev = *out_dev;
2766 struct flow_action_entry vlan_act = {
2767 .id = FLOW_ACTION_VLAN_PUSH,
2768 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
2769 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
2770 .vlan.prio = 0,
2771 };
2772 int err;
2773
2774 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2775 if (err)
2776 return err;
2777
2778 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
2779 dev_get_iflink(vlan_dev));
2780 if (is_vlan_dev(*out_dev))
2781 err = add_vlan_push_action(priv, attr, out_dev, action);
2782
2783 return err;
2784}
2785
35a605db
EB		 2786static int add_vlan_pop_action(struct mlx5e_priv *priv,
2787 struct mlx5_esw_flow_attr *attr,
2788 u32 *action)
2789{
2790 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
2791 struct flow_action_entry vlan_act = {
2792 .id = FLOW_ACTION_VLAN_POP,
2793 };
2794 int err = 0;
2795
2796 while (nest_level--) {
2797 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2798 if (err)
2799 return err;
2800 }
2801
2802 return err;
2803}
2804
73867881
PNA		 2805static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2806 struct flow_action *flow_action,
e98bedf5
EB		 2807 struct mlx5e_tc_flow *flow,
2808 struct netlink_ext_ack *extack)
03a9d11e 2809{
73867881 2810 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2811 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2812 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 2813 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 2814 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2815 const struct ip_tunnel_info *info = NULL;
2816 const struct flow_action_entry *act;
a54e20b4 2817 bool encap = false;
1cab1cd7 2818 u32 action = 0;
244cd96a 2819 int err, i;
03a9d11e 2820
73867881 2821 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2822 return -EINVAL;
2823
73867881
PNA		 2824 flow_action_for_each(i, act, flow_action) {
2825 switch (act->id) {
2826 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2827 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2828 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2829 break;
2830 case FLOW_ACTION_MANGLE:
2831 case FLOW_ACTION_ADD:
2832 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 2833 parse_attr, hdrs, extack);
d7e75a32
OG		 2834 if (err)
2835 return err;
2836
1cab1cd7 2837 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2838 attr->split_count = attr->out_count;
73867881
PNA		 2839 break;
2840 case FLOW_ACTION_CSUM:
1cab1cd7 2841 if (csum_offload_supported(priv, action,
73867881
PNA		 2842 act->csum_flags, extack))
2843 break;
26c02749
OG		 2844
2845 return -EOPNOTSUPP;
73867881
PNA		 2846 case FLOW_ACTION_REDIRECT:
2847 case FLOW_ACTION_MIRRED: {
03a9d11e 2848 struct mlx5e_priv *out_priv;
592d3651 2849 struct net_device *out_dev;
03a9d11e 2850
73867881 2851 out_dev = act->dev;
ef381359
OS		 2852 if (!out_dev) {
2853 /* out_dev is NULL when filters with
2854 * non-existing mirred device are replayed to
2855 * the driver.
2856 */
2857 return -EINVAL;
2858 }
03a9d11e 2859
592d3651 2860 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2861 NL_SET_ERR_MSG_MOD(extack,
2862 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2863 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2864 attr->out_count);
2865 return -EOPNOTSUPP;
2866 }
2867
f493f155
EB		 2868 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2869 MLX5_FLOW_CONTEXT_ACTION_COUNT;
6dcfa234
FF		 2870 if (netdev_port_same_parent_id(priv->netdev,
2871 out_dev) ||
b1d90e6b 2872 is_merged_eswitch_dev(priv, out_dev)) {
7ba58ba7
RL		 2873 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2874 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
2875 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev);
2876
2877 if (uplink_upper &&
2878 netif_is_lag_master(uplink_upper) &&
2879 uplink_upper == out_dev)
2880 out_dev = uplink_dev;
2881
278748a9
EB		 2882 if (is_vlan_dev(out_dev)) {
2883 err = add_vlan_push_action(priv, attr,
2884 &out_dev,
2885 &action);
2886 if (err)
2887 return err;
2888 }
35a605db
EB		 2889 if (is_vlan_dev(parse_attr->filter_dev)) {
2890 err = add_vlan_pop_action(priv, attr,
2891 &action);
2892 if (err)
2893 return err;
2894 }
278748a9 2895
a0646c88
EB		 2896 if (!mlx5e_eswitch_rep(out_dev))
2897 return -EOPNOTSUPP;
2898
a54e20b4 2899 out_priv = netdev_priv(out_dev);
1d447a39 2900 rpriv = out_priv->ppriv;
df65a573
EB		 2901 attr->dests[attr->out_count].rep = rpriv->rep;
2902 attr->dests[attr->out_count].mdev = out_priv->mdev;
2903 attr->out_count++;
a54e20b4 2904 } else if (encap) {
8c4dc42b
EB		 2905 parse_attr->mirred_ifindex[attr->out_count] =
2906 out_dev->ifindex;
1f6da306 2907 parse_attr->tun_info[attr->out_count] = info;
8c4dc42b 2908 encap = false;
f493f155
EB		 2909 attr->dests[attr->out_count].flags |=
2910 MLX5_ESW_DEST_ENCAP;
1cc26d74 2911 attr->out_count++;
df65a573
EB		 2912 /* attr->dests[].rep is resolved when we
2913 * handle encap
2914 */
ef381359
OS		 2915 } else if (parse_attr->filter_dev != priv->netdev) {
2916 /* All mlx5 devices are called to configure
2917 * high level device filters. Therefore, the
2918 * *attempt* to install a filter on invalid
2919 * eswitch should not trigger an explicit error
2920 */
2921 return -EINVAL;
a54e20b4 2922 } else {
e98bedf5
EB		 2923 NL_SET_ERR_MSG_MOD(extack,
2924 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2925 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2926 priv->netdev->name, out_dev->name);
2927 return -EINVAL;
2928 }
73867881
PNA		 2929 }
2930 break;
2931 case FLOW_ACTION_TUNNEL_ENCAP:
2932 info = act->tunnel;
a54e20b4
HHZ		 2933 if (info)
2934 encap = true;
2935 else
2936 return -EOPNOTSUPP;
1482bd3d 2937
73867881
PNA		 2938 break;
2939 case FLOW_ACTION_VLAN_PUSH:
2940 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 2941 if (act->id == FLOW_ACTION_VLAN_PUSH &&
2942 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
2943 /* Replace vlan pop+push with vlan modify */
2944 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2945 err = add_vlan_rewrite_action(priv,
2946 MLX5_FLOW_NAMESPACE_FDB,
2947 act, parse_attr, hdrs,
2948 &action, extack);
2949 } else {
2950 err = parse_tc_vlan_action(priv, act, attr, &action);
2951 }
1482bd3d
JL		 2952 if (err)
2953 return err;
2954
bdc837ee
EB		 2955 attr->split_count = attr->out_count;
2956 break;
2957 case FLOW_ACTION_VLAN_MANGLE:
2958 err = add_vlan_rewrite_action(priv,
2959 MLX5_FLOW_NAMESPACE_FDB,
2960 act, parse_attr, hdrs,
2961 &action, extack);
2962 if (err)
2963 return err;
2964
e85e02ba 2965 attr->split_count = attr->out_count;
73867881
PNA		 2966 break;
2967 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 2968 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 2969 break;
2970 case FLOW_ACTION_GOTO: {
2971 u32 dest_chain = act->chain_index;
bf07aa73
PB		 2972 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2973
2974 if (dest_chain <= attr->chain) {
2975 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2976 return -EOPNOTSUPP;
2977 }
2978 if (dest_chain > max_chain) {
2979 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2980 return -EOPNOTSUPP;
2981 }
e88afe75 2982 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 2983 attr->dest_chain = dest_chain;
73867881
PNA		 2984 break;
2985 }
2986 default:
2cc1cb1d
TZ		 2987 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2988 return -EOPNOTSUPP;
bf07aa73 2989 }
03a9d11e 2990 }
bdd66ac0 2991
0bac1194
EB		 2992 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
2993 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
2994 /* For prio tag mode, replace vlan pop with rewrite vlan prio
2995 * tag rewrite.
2996 */
2997 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2998 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
2999 &action, extack);
3000 if (err)
3001 return err;
3002 }
3003
c500c86b
PNA		 3004 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3005 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3006 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3007 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3008 if (err)
3009 return err;
27c11b6b
EB		 3010 /* in case all pedit actions are skipped, remove the MOD_HDR
3011 * flag. we might have set split_count either by pedit or
3012 * pop/push. if there is no pop/push either, reset it too.
3013 */
3014 if (parse_attr->num_mod_hdr_actions == 0) {
3015 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3016 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3017 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3018 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3019 attr->split_count = 0;
3020 }
c500c86b
PNA		 3021 }
3022
1cab1cd7 3023 attr->action = action;
73867881 3024 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3025 return -EOPNOTSUPP;
3026
e88afe75
OG		 3027 if (attr->dest_chain) {
3028 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3029 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3030 return -EOPNOTSUPP;
3031 }
3032 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3033 }
3034
e85e02ba 3035 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3036 NL_SET_ERR_MSG_MOD(extack,
3037 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3038 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3039 return -EOPNOTSUPP;
3040 }
3041
31c8eba5 3042 return 0;
03a9d11e
OG		 3043}
3044
5dbe906f 3045static void get_flags(int flags, u16 *flow_flags)
60bd4af8 3046{
5dbe906f 3047 u16 __flow_flags = 0;
60bd4af8
OG		 3048
3049 if (flags & MLX5E_TC_INGRESS)
3050 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
3051 if (flags & MLX5E_TC_EGRESS)
3052 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
3053
d9ee0491
OG		 3054 if (flags & MLX5E_TC_ESW_OFFLOAD)
3055 __flow_flags |= MLX5E_TC_FLOW_ESWITCH;
3056 if (flags & MLX5E_TC_NIC_OFFLOAD)
3057 __flow_flags |= MLX5E_TC_FLOW_NIC;
3058
60bd4af8
OG		 3059 *flow_flags = __flow_flags;
3060}
3061
05866c82
OG		 3062static const struct rhashtable_params tc_ht_params = {
3063 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3064 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3065 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3066 .automatic_shrinking = true,
3067};
3068
d9ee0491 3069static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags)
05866c82 3070{
655dc3d2
OG		 3071 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3072 struct mlx5e_rep_priv *uplink_rpriv;
3073
d9ee0491 3074 if (flags & MLX5E_TC_ESW_OFFLOAD) {
655dc3d2 3075 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3076 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3077 } else /* NIC offload */
655dc3d2 3078 return &priv->fs.tc.ht;
05866c82
OG		 3079}
3080
04de7dda
RD		 3081static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3082{
1418ddd9 3083 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3084 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
1418ddd9
AH		 3085 flow->flags & MLX5E_TC_FLOW_INGRESS;
3086 bool act_is_encap = !!(attr->action &
3087 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3088 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3089 MLX5_DEVCOM_ESW_OFFLOADS);
3090
10fbb1cd
RD		 3091 if (!esw_paired)
3092 return false;
3093
3094 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3095 mlx5_lag_is_multipath(attr->in_mdev)) &&
3096 (is_rep_ingress || act_is_encap))
3097 return true;
3098
3099 return false;
04de7dda
RD		 3100}
3101
a88780a9
RD		 3102static int
3103mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 3104 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 3105 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3106 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3107{
17091853 3108 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3109 struct mlx5e_tc_flow *flow;
a88780a9 3110 int err;
e3a2b7ed 3111
65ba8fb7 3112 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3113 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3114 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3115 err = -ENOMEM;
3116 goto err_free;
3117 }
3118
3119 flow->cookie = f->cookie;
65ba8fb7 3120 flow->flags = flow_flags;
655dc3d2 3121 flow->priv = priv;
e3a2b7ed 3122
a88780a9
RD		 3123 *__flow = flow;
3124 *__parse_attr = parse_attr;
3125
3126 return 0;
3127
3128err_free:
3129 kfree(flow);
3130 kvfree(parse_attr);
3131 return err;
3132}
3133
988ab9c7
TZ		 3134static void
3135mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3136 struct mlx5e_priv *priv,
3137 struct mlx5e_tc_flow_parse_attr *parse_attr,
3138 struct tc_cls_flower_offload *f,
3139 struct mlx5_eswitch_rep *in_rep,
3140 struct mlx5_core_dev *in_mdev)
3141{
3142 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3143
3144 esw_attr->parse_attr = parse_attr;
3145 esw_attr->chain = f->common.chain_index;
3146 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
3147
3148 esw_attr->in_rep = in_rep;
3149 esw_attr->in_mdev = in_mdev;
3150
3151 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3152 MLX5_COUNTER_SOURCE_ESWITCH)
3153 esw_attr->counter_dev = in_mdev;
3154 else
3155 esw_attr->counter_dev = priv->mdev;
3156}
3157
71129676 3158static struct mlx5e_tc_flow *
04de7dda
RD		 3159__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3160 struct tc_cls_flower_offload *f,
3161 u16 flow_flags,
3162 struct net_device *filter_dev,
3163 struct mlx5_eswitch_rep *in_rep,
71129676 3164 struct mlx5_core_dev *in_mdev)
a88780a9 3165{
73867881 3166 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 3167 struct netlink_ext_ack *extack = f->common.extack;
3168 struct mlx5e_tc_flow_parse_attr *parse_attr;
3169 struct mlx5e_tc_flow *flow;
3170 int attr_size, err;
e3a2b7ed 3171
a88780a9
RD		 3172 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
3173 attr_size = sizeof(struct mlx5_esw_flow_attr);
3174 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3175 &parse_attr, &flow);
3176 if (err)
3177 goto out;
988ab9c7 3178
d11afc26 3179 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3180 mlx5e_flow_esw_attr_init(flow->esw_attr,
3181 priv, parse_attr,
3182 f, in_rep, in_mdev);
3183
54c177ca
OS		 3184 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3185 f, filter_dev);
d11afc26
OS		 3186 if (err)
3187 goto err_free;
a88780a9 3188
6f9af8ff 3189 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3190 if (err)
3191 goto err_free;
3192
7040632d 3193 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
ef06c9ee
RD		 3194 if (err) {
3195 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3196 goto err_free;
3197
b4a23329 3198 add_unready_flow(flow);
ef06c9ee 3199 }
e3a2b7ed 3200
71129676 3201 return flow;
a88780a9
RD		 3202
3203err_free:
3204 kfree(flow);
3205 kvfree(parse_attr);
3206out:
71129676 3207 return ERR_PTR(err);
a88780a9
RD		 3208}
3209
04de7dda 3210static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
95dc1902
RD		 3211 struct mlx5e_tc_flow *flow,
3212 u16 flow_flags)
04de7dda
RD		 3213{
3214 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3215 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3216 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3217 struct mlx5e_tc_flow_parse_attr *parse_attr;
3218 struct mlx5e_rep_priv *peer_urpriv;
3219 struct mlx5e_tc_flow *peer_flow;
3220 struct mlx5_core_dev *in_mdev;
3221 int err = 0;
3222
3223 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3224 if (!peer_esw)
3225 return -ENODEV;
3226
3227 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3228 peer_priv = netdev_priv(peer_urpriv->netdev);
3229
3230 /* in_mdev is assigned of which the packet originated from.
3231 * So packets redirected to uplink use the same mdev of the
3232 * original flow and packets redirected from uplink use the
3233 * peer mdev.
3234 */
b05af6aa 3235 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3236 in_mdev = peer_priv->mdev;
3237 else
3238 in_mdev = priv->mdev;
3239
3240 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3241 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3242 parse_attr->filter_dev,
3243 flow->esw_attr->in_rep, in_mdev);
3244 if (IS_ERR(peer_flow)) {
3245 err = PTR_ERR(peer_flow);
04de7dda 3246 goto out;
71129676 3247 }
04de7dda
RD		 3248
3249 flow->peer_flow = peer_flow;
3250 flow->flags |= MLX5E_TC_FLOW_DUP;
3251 mutex_lock(&esw->offloads.peer_mutex);
3252 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3253 mutex_unlock(&esw->offloads.peer_mutex);
3254
3255out:
3256 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3257 return err;
3258}
3259
3260static int
3261mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3262 struct tc_cls_flower_offload *f,
3263 u16 flow_flags,
3264 struct net_device *filter_dev,
3265 struct mlx5e_tc_flow **__flow)
3266{
3267 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3268 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3269 struct mlx5_core_dev *in_mdev = priv->mdev;
3270 struct mlx5e_tc_flow *flow;
3271 int err;
3272
71129676
JG		 3273 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3274 in_mdev);
3275 if (IS_ERR(flow))
3276 return PTR_ERR(flow);
04de7dda
RD		 3277
3278 if (is_peer_flow_needed(flow)) {
95dc1902 3279 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3280 if (err) {
3281 mlx5e_tc_del_fdb_flow(priv, flow);
3282 goto out;
3283 }
3284 }
3285
3286 *__flow = flow;
3287
3288 return 0;
3289
3290out:
3291 return err;
3292}
3293
a88780a9
RD		 3294static int
3295mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3296 struct tc_cls_flower_offload *f,
5dbe906f 3297 u16 flow_flags,
d11afc26 3298 struct net_device *filter_dev,
a88780a9
RD		 3299 struct mlx5e_tc_flow **__flow)
3300{
73867881 3301 struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
a88780a9
RD		 3302 struct netlink_ext_ack *extack = f->common.extack;
3303 struct mlx5e_tc_flow_parse_attr *parse_attr;
3304 struct mlx5e_tc_flow *flow;
3305 int attr_size, err;
3306
bf07aa73
PB		 3307 /* multi-chain not supported for NIC rules */
3308 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3309 return -EOPNOTSUPP;
3310
a88780a9
RD		 3311 flow_flags |= MLX5E_TC_FLOW_NIC;
3312 attr_size = sizeof(struct mlx5_nic_flow_attr);
3313 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3314 &parse_attr, &flow);
3315 if (err)
3316 goto out;
3317
d11afc26 3318 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3319 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3320 f, filter_dev);
d11afc26
OS		 3321 if (err)
3322 goto err_free;
3323
73867881 3324 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3325 if (err)
3326 goto err_free;
3327
3328 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3329 if (err)
3330 goto err_free;
3331
3332 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
3333 kvfree(parse_attr);
3334 *__flow = flow;
3335
3336 return 0;
e3a2b7ed 3337
e3a2b7ed 3338err_free:
a88780a9 3339 kfree(flow);
17091853 3340 kvfree(parse_attr);
a88780a9
RD		 3341out:
3342 return err;
3343}
3344
3345static int
3346mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3347 struct tc_cls_flower_offload *f,
3348 int flags,
d11afc26 3349 struct net_device *filter_dev,
a88780a9
RD		 3350 struct mlx5e_tc_flow **flow)
3351{
3352 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 3353 u16 flow_flags;
a88780a9
RD		 3354 int err;
3355
3356 get_flags(flags, &flow_flags);
3357
bf07aa73
PB		 3358 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3359 return -EOPNOTSUPP;
3360
a88780a9 3361 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 3362 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3363 filter_dev, flow);
a88780a9 3364 else
d11afc26
OS		 3365 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3366 filter_dev, flow);
a88780a9
RD		 3367
3368 return err;
3369}
3370
71d82d2a 3371int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 3372 struct tc_cls_flower_offload *f, int flags)
3373{
3374 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3375 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3376 struct mlx5e_tc_flow *flow;
3377 int err = 0;
3378
3379 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3380 if (flow) {
3381 NL_SET_ERR_MSG_MOD(extack,
3382 "flow cookie already exists, ignoring");
3383 netdev_warn_once(priv->netdev,
3384 "flow cookie %lx already exists, ignoring\n",
3385 f->cookie);
0e1c1a2f 3386 err = -EEXIST;
a88780a9
RD		 3387 goto out;
3388 }
3389
d11afc26 3390 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3391 if (err)
3392 goto out;
3393
3394 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
3395 if (err)
3396 goto err_free;
3397
3398 return 0;
3399
3400err_free:
3401 mlx5e_tc_del_flow(priv, flow);
232c0013 3402 kfree(flow);
a88780a9 3403out:
e3a2b7ed
AV		 3404 return err;
3405}
3406
8f8ae895
OG		 3407#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
3408#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
3409
3410static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3411{
3412 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
3413 return true;
3414
3415 return false;
3416}
3417
71d82d2a 3418int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3419 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3420{
d9ee0491 3421 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3422 struct mlx5e_tc_flow *flow;
e3a2b7ed 3423
05866c82 3424 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3425 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3426 return -EINVAL;
3427
05866c82 3428 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3429
961e8979 3430 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3431
3432 kfree(flow);
3433
3434 return 0;
3435}
3436
71d82d2a 3437int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3438 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3439{
04de7dda 3440 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3441 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3442 struct mlx5_eswitch *peer_esw;
aad7e08d 3443 struct mlx5e_tc_flow *flow;
aad7e08d 3444 struct mlx5_fc *counter;
316d5f72
RD		 3445 u64 lastuse = 0;
3446 u64 packets = 0;
3447 u64 bytes = 0;
aad7e08d 3448
05866c82 3449 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3450 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3451 return -EINVAL;
3452
316d5f72
RD		 3453 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
3454 counter = mlx5e_tc_get_counter(flow);
3455 if (!counter)
3456 return 0;
aad7e08d 3457
316d5f72
RD		 3458 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3459 }
aad7e08d 3460
316d5f72
RD		 3461 /* Under multipath it's possible for one rule to be currently
3462 * un-offloaded while the other rule is offloaded.
3463 */
04de7dda
RD		 3464 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3465 if (!peer_esw)
3466 goto out;
3467
3468 if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3469 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3470 u64 bytes2;
3471 u64 packets2;
3472 u64 lastuse2;
3473
3474 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3475 if (!counter)
3476 goto no_peer_counter;
04de7dda
RD		 3477 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3478
3479 bytes += bytes2;
3480 packets += packets2;
3481 lastuse = max_t(u64, lastuse, lastuse2);
3482 }
3483
316d5f72 3484no_peer_counter:
04de7dda 3485 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3486out:
3b1903ef 3487 flow_stats_update(&f->stats, bytes, packets, lastuse);
fed06ee8 3488
aad7e08d
AV		 3489 return 0;
3490}
3491
4d8fcf21
AH		 3492static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3493 struct mlx5e_priv *peer_priv)
3494{
3495 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3496 struct mlx5e_hairpin_entry *hpe;
3497 u16 peer_vhca_id;
3498 int bkt;
3499
3500 if (!same_hw_devs(priv, peer_priv))
3501 return;
3502
3503 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3504
3505 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3506 if (hpe->peer_vhca_id == peer_vhca_id)
3507 hpe->hp->pair->peer_gone = true;
3508 }
3509}
3510
3511static int mlx5e_tc_netdev_event(struct notifier_block *this,
3512 unsigned long event, void *ptr)
3513{
3514 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3515 struct mlx5e_flow_steering *fs;
3516 struct mlx5e_priv *peer_priv;
3517 struct mlx5e_tc_table *tc;
3518 struct mlx5e_priv *priv;
3519
3520 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3521 event != NETDEV_UNREGISTER ||
3522 ndev->reg_state == NETREG_REGISTERED)
3523 return NOTIFY_DONE;
3524
3525 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3526 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3527 priv = container_of(fs, struct mlx5e_priv, fs);
3528 peer_priv = netdev_priv(ndev);
3529 if (priv == peer_priv ||
3530 !(priv->netdev->features & NETIF_F_HW_TC))
3531 return NOTIFY_DONE;
3532
3533 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3534
3535 return NOTIFY_DONE;
3536}
3537
655dc3d2 3538int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3539{
acff797c 3540 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3541 int err;
e8f887ac 3542
11c9c548 3543 hash_init(tc->mod_hdr_tbl);
5c65c564 3544 hash_init(tc->hairpin_tbl);
11c9c548 3545
4d8fcf21
AH		 3546 err = rhashtable_init(&tc->ht, &tc_ht_params);
3547 if (err)
3548 return err;
3549
3550 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3551 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3552 tc->netdevice_nb.notifier_call = NULL;
3553 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3554 }
3555
3556 return err;
e8f887ac
AV		 3557}
3558
3559static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3560{
3561 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3562 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3563
961e8979 3564 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3565 kfree(flow);
3566}
3567
655dc3d2 3568void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3569{
acff797c 3570 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3571
4d8fcf21
AH		 3572 if (tc->netdevice_nb.notifier_call)
3573 unregister_netdevice_notifier(&tc->netdevice_nb);
3574
d9ee0491 3575 rhashtable_destroy(&tc->ht);
e8f887ac 3576
acff797c
MG		 3577 if (!IS_ERR_OR_NULL(tc->t)) {
3578 mlx5_destroy_flow_table(tc->t);
3579 tc->t = NULL;
e8f887ac
AV		 3580 }
3581}
655dc3d2
OG		 3582
3583int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3584{
3585 return rhashtable_init(tc_ht, &tc_ht_params);
3586}
3587
3588void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3589{
3590 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3591}
01252a27 3592
d9ee0491 3593int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags)
01252a27 3594{
d9ee0491 3595 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3596
3597 return atomic_read(&tc_ht->nelems);
3598}
04de7dda
RD		 3599
3600void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3601{
3602 struct mlx5e_tc_flow *flow, *tmp;
3603
3604 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3605 __mlx5e_tc_del_fdb_peer_flow(flow);
3606}
b4a23329
RD		 3607
3608void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
3609{
3610 struct mlx5_rep_uplink_priv *rpriv =
3611 container_of(work, struct mlx5_rep_uplink_priv,
3612 reoffload_flows_work);
3613 struct mlx5e_tc_flow *flow, *tmp;
3614
3615 rtnl_lock();
3616 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
3617 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
3618 remove_unready_flow(flow);
3619 }
3620 rtnl_unlock();
3621}
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