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net/mlx5: Add missing mutex destroy
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
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e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
49964352 60#include "esw/chains.h"
3f6d08d1 61#include "fs_core.h"
2c81bfd5 62#include "en/port.h"
101f4de9 63#include "en/tc_tun.h"
0a7fcb78 64#include "en/mapping.h"
4c3844d9 65#include "en/tc_ct.h"
04de7dda 66#include "lib/devcom.h"
9272e3df 67#include "lib/geneve.h"
7a978759 68#include "diag/en_tc_tracepoint.h"
e8f887ac 69
d65dbedf 70#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
0a7fcb78 71
3bc4b7bf
OG		 72struct mlx5_nic_flow_attr {
73 u32 action;
74 u32 flow_tag;
2b688ea5 75 struct mlx5_modify_hdr *modify_hdr;
5c65c564 76 u32 hairpin_tirn;
38aa51c1 77 u8 match_level;
3f6d08d1 78 struct mlx5_flow_table *hairpin_ft;
b8aee822 79 struct mlx5_fc *counter;
3bc4b7bf
OG		 80};
81
226f2ca3 82#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 83
65ba8fb7 84enum {
226f2ca3
VB		 85 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
86 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
87 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 88 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 89 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
90 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
91 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
92 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
93 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
94 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
95 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 96 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 97 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
14e6b038 98 MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8,
65ba8fb7
OG		 99};
100
e4ad91f2
CM		 101#define MLX5E_TC_MAX_SPLITS 1
102
79baaec7
EB		 103/* Helper struct for accessing a struct containing list_head array.
104 * Containing struct
105 * |- Helper array
106 * [0] Helper item 0
107 * |- list_head item 0
108 * |- index (0)
109 * [1] Helper item 1
110 * |- list_head item 1
111 * |- index (1)
112 * To access the containing struct from one of the list_head items:
113 * 1. Get the helper item from the list_head item using
114 * helper item =
115 * container_of(list_head item, helper struct type, list_head field)
116 * 2. Get the contining struct from the helper item and its index in the array:
117 * containing struct =
118 * container_of(helper item, containing struct type, helper field[index])
119 */
120struct encap_flow_item {
948993f2 121 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 122 struct list_head list;
123 int index;
124};
125
e8f887ac
AV		 126struct mlx5e_tc_flow {
127 struct rhash_head node;
655dc3d2 128 struct mlx5e_priv *priv;
e8f887ac 129 u64 cookie;
226f2ca3 130 unsigned long flags;
e4ad91f2 131 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
14e6b038
EC		 132
133 /* flows sharing the same reformat object - currently mpls decap */
134 struct list_head l3_to_l2_reformat;
135 struct mlx5e_decap_entry *decap_reformat;
136
79baaec7
EB		 137 /* Flow can be associated with multiple encap IDs.
138 * The number of encaps is bounded by the number of supported
139 * destinations.
140 */
141 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 142 struct mlx5e_tc_flow *peer_flow;
dd58edc3 143 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 144 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 145 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 146 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 147 struct list_head peer; /* flows with peer flow */
b4a23329 148 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
553f9328 149 struct net_device *orig_dev; /* netdev adding flow first */
2a1f1768 150 int tmp_efi_index;
6a06c2f7 151 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 152 refcount_t refcnt;
c5d326b2 153 struct rcu_head rcu_head;
95435ad7 154 struct completion init_done;
0a7fcb78
PB		 155 int tunnel_id; /* the mapped tunnel id of this flow */
156
3bc4b7bf
OG		 157 union {
158 struct mlx5_esw_flow_attr esw_attr[0];
159 struct mlx5_nic_flow_attr nic_attr[0];
160 };
e8f887ac
AV		 161};
162
17091853 163struct mlx5e_tc_flow_parse_attr {
1f6da306 164 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 165 struct net_device *filter_dev;
17091853 166 struct mlx5_flow_spec spec;
6ae4a6a5 167 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 168 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
14e6b038 169 struct ethhdr eth;
17091853
OG		 170};
171
acff797c 172#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 173#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 174
8f1e0b97
PB		 175struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
176 [CHAIN_TO_REG] = {
177 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
178 .moffset = 0,
179 .mlen = 2,
180 },
0a7fcb78
PB		 181 [TUNNEL_TO_REG] = {
182 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
183 .moffset = 3,
184 .mlen = 1,
185 .soffset = MLX5_BYTE_OFF(fte_match_param,
186 misc_parameters_2.metadata_reg_c_1),
187 },
4c3844d9
PB		 188 [ZONE_TO_REG] = zone_to_reg_ct,
189 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
190 [MARK_TO_REG] = mark_to_reg_ct,
191 [LABELS_TO_REG] = labels_to_reg_ct,
192 [FTEID_TO_REG] = fteid_to_reg_ct,
5c6b9460 193 [TUPLEID_TO_REG] = tupleid_to_reg_ct,
8f1e0b97
PB		 194};
195
0a7fcb78
PB		 196static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
197
198void
199mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
200 enum mlx5e_tc_attr_to_reg type,
201 u32 data,
202 u32 mask)
203{
204 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
205 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
206 void *headers_c = spec->match_criteria;
207 void *headers_v = spec->match_value;
208 void *fmask, *fval;
209
210 fmask = headers_c + soffset;
211 fval = headers_v + soffset;
212
213 mask = cpu_to_be32(mask) >> (32 - (match_len * 8));
214 data = cpu_to_be32(data) >> (32 - (match_len * 8));
215
216 memcpy(fmask, &mask, match_len);
217 memcpy(fval, &data, match_len);
218
219 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
220}
221
222int
223mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
224 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
225 enum mlx5e_tc_attr_to_reg type,
226 u32 data)
227{
228 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
229 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
230 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
231 char *modact;
232 int err;
233
234 err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB,
235 mod_hdr_acts);
236 if (err)
237 return err;
238
239 modact = mod_hdr_acts->actions +
240 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
241
242 /* Firmware has 5bit length field and 0 means 32bits */
243 if (mlen == 4)
244 mlen = 0;
245
246 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
247 MLX5_SET(set_action_in, modact, field, mfield);
248 MLX5_SET(set_action_in, modact, offset, moffset * 8);
249 MLX5_SET(set_action_in, modact, length, mlen * 8);
250 MLX5_SET(set_action_in, modact, data, data);
251 mod_hdr_acts->num_actions++;
252
253 return 0;
254}
255
77ab67b7
OG		 256struct mlx5e_hairpin {
257 struct mlx5_hairpin *pair;
258
259 struct mlx5_core_dev *func_mdev;
3f6d08d1 260 struct mlx5e_priv *func_priv;
77ab67b7
OG		 261 u32 tdn;
262 u32 tirn;
3f6d08d1
OG		 263
264 int num_channels;
265 struct mlx5e_rqt indir_rqt;
266 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
267 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 268};
269
5c65c564
OG		 270struct mlx5e_hairpin_entry {
271 /* a node of a hash table which keeps all the hairpin entries */
272 struct hlist_node hairpin_hlist;
273
73edca73
VB		 274 /* protects flows list */
275 spinlock_t flows_lock;
5c65c564
OG		 276 /* flows sharing the same hairpin */
277 struct list_head flows;
db76ca24
VB		 278 /* hpe's that were not fully initialized when dead peer update event
279 * function traversed them.
280 */
281 struct list_head dead_peer_wait_list;
5c65c564 282
d8822868 283 u16 peer_vhca_id;
106be53b 284 u8 prio;
5c65c564 285 struct mlx5e_hairpin *hp;
e4f9abbd 286 refcount_t refcnt;
db76ca24 287 struct completion res_ready;
5c65c564
OG		 288};
289
11c9c548
OG		 290struct mod_hdr_key {
291 int num_actions;
292 void *actions;
293};
294
295struct mlx5e_mod_hdr_entry {
296 /* a node of a hash table which keeps all the mod_hdr entries */
297 struct hlist_node mod_hdr_hlist;
298
83a52f0d
VB		 299 /* protects flows list */
300 spinlock_t flows_lock;
11c9c548
OG		 301 /* flows sharing the same mod_hdr entry */
302 struct list_head flows;
303
304 struct mod_hdr_key key;
305
2b688ea5 306 struct mlx5_modify_hdr *modify_hdr;
dd58edc3
VB		 307
308 refcount_t refcnt;
a734d007
VB		 309 struct completion res_ready;
310 int compl_result;
11c9c548
OG		 311};
312
5a7e5bcb
VB		 313static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
314 struct mlx5e_tc_flow *flow);
315
316static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
317{
318 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
319 return ERR_PTR(-EINVAL);
320 return flow;
321}
322
323static void mlx5e_flow_put(struct mlx5e_priv *priv,
324 struct mlx5e_tc_flow *flow)
325{
326 if (refcount_dec_and_test(&flow->refcnt)) {
327 mlx5e_tc_del_flow(priv, flow);
c5d326b2 328 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 329 }
330}
331
226f2ca3
VB		 332static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
333{
334 /* Complete all memory stores before setting bit. */
335 smp_mb__before_atomic();
336 set_bit(flag, &flow->flags);
337}
338
339#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
340
c5d326b2
VB		 341static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
342 unsigned long flag)
343{
344 /* test_and_set_bit() provides all necessary barriers */
345 return test_and_set_bit(flag, &flow->flags);
346}
347
348#define flow_flag_test_and_set(flow, flag) \
349 __flow_flag_test_and_set(flow, \
350 MLX5E_TC_FLOW_FLAG_##flag)
351
226f2ca3
VB		 352static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
353{
354 /* Complete all memory stores before clearing bit. */
355 smp_mb__before_atomic();
356 clear_bit(flag, &flow->flags);
357}
358
359#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
360 MLX5E_TC_FLOW_FLAG_##flag)
361
362static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
363{
364 bool ret = test_bit(flag, &flow->flags);
365
366 /* Read fields of flow structure only after checking flags. */
367 smp_mb__after_atomic();
368 return ret;
369}
370
371#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
372 MLX5E_TC_FLOW_FLAG_##flag)
373
374static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
375{
376 return flow_flag_test(flow, ESWITCH);
377}
378
84179981
PB		 379static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
380{
381 return flow_flag_test(flow, FT);
382}
383
226f2ca3
VB		 384static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
385{
386 return flow_flag_test(flow, OFFLOADED);
387}
388
11c9c548
OG		 389static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
390{
391 return jhash(key->actions,
392 key->num_actions * MLX5_MH_ACT_SZ, 0);
393}
394
395static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
396 struct mod_hdr_key *b)
397{
398 if (a->num_actions != b->num_actions)
399 return 1;
400
401 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
402}
403
dd58edc3
VB		 404static struct mod_hdr_tbl *
405get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
406{
407 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
408
409 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
410 &priv->fs.tc.mod_hdr;
411}
412
413static struct mlx5e_mod_hdr_entry *
414mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
415{
416 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
417
418 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
419 if (!cmp_mod_hdr_info(&mh->key, key)) {
420 refcount_inc(&mh->refcnt);
421 found = mh;
422 break;
423 }
424 }
425
426 return found;
427}
428
429static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
d2faae25
VB		 430 struct mlx5e_mod_hdr_entry *mh,
431 int namespace)
dd58edc3 432{
d2faae25
VB		 433 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
434
435 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
dd58edc3 436 return;
d2faae25
VB		 437 hash_del(&mh->mod_hdr_hlist);
438 mutex_unlock(&tbl->lock);
dd58edc3
VB		 439
440 WARN_ON(!list_empty(&mh->flows));
a734d007 441 if (mh->compl_result > 0)
2b688ea5 442 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
d2faae25 443
dd58edc3
VB		 444 kfree(mh);
445}
446
d2faae25
VB		 447static int get_flow_name_space(struct mlx5e_tc_flow *flow)
448{
449 return mlx5e_is_eswitch_flow(flow) ?
450 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
451}
11c9c548
OG		 452static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
453 struct mlx5e_tc_flow *flow,
454 struct mlx5e_tc_flow_parse_attr *parse_attr)
455{
11c9c548
OG		 456 int num_actions, actions_size, namespace, err;
457 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 458 struct mod_hdr_tbl *tbl;
11c9c548 459 struct mod_hdr_key key;
11c9c548
OG		 460 u32 hash_key;
461
6ae4a6a5 462 num_actions = parse_attr->mod_hdr_acts.num_actions;
11c9c548
OG		 463 actions_size = MLX5_MH_ACT_SZ * num_actions;
464
6ae4a6a5 465 key.actions = parse_attr->mod_hdr_acts.actions;
11c9c548
OG		 466 key.num_actions = num_actions;
467
468 hash_key = hash_mod_hdr_info(&key);
469
d2faae25 470 namespace = get_flow_name_space(flow);
dd58edc3 471 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 472
d2faae25 473 mutex_lock(&tbl->lock);
dd58edc3 474 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
a734d007
VB		 475 if (mh) {
476 mutex_unlock(&tbl->lock);
477 wait_for_completion(&mh->res_ready);
478
479 if (mh->compl_result < 0) {
480 err = -EREMOTEIO;
481 goto attach_header_err;
482 }
11c9c548 483 goto attach_flow;
a734d007 484 }
11c9c548
OG		 485
486 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
d2faae25 487 if (!mh) {
a734d007
VB		 488 mutex_unlock(&tbl->lock);
489 return -ENOMEM;
d2faae25 490 }
11c9c548
OG		 491
492 mh->key.actions = (void *)mh + sizeof(*mh);
493 memcpy(mh->key.actions, key.actions, actions_size);
494 mh->key.num_actions = num_actions;
83a52f0d 495 spin_lock_init(&mh->flows_lock);
11c9c548 496 INIT_LIST_HEAD(&mh->flows);
dd58edc3 497 refcount_set(&mh->refcnt, 1);
a734d007
VB		 498 init_completion(&mh->res_ready);
499
500 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
501 mutex_unlock(&tbl->lock);
11c9c548 502
2b688ea5
MG		 503 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
504 mh->key.num_actions,
505 mh->key.actions);
506 if (IS_ERR(mh->modify_hdr)) {
507 err = PTR_ERR(mh->modify_hdr);
a734d007
VB		 508 mh->compl_result = err;
509 goto alloc_header_err;
510 }
511 mh->compl_result = 1;
512 complete_all(&mh->res_ready);
11c9c548
OG		 513
514attach_flow:
dd58edc3 515 flow->mh = mh;
83a52f0d 516 spin_lock(&mh->flows_lock);
11c9c548 517 list_add(&flow->mod_hdr, &mh->flows);
83a52f0d 518 spin_unlock(&mh->flows_lock);
d2faae25 519 if (mlx5e_is_eswitch_flow(flow))
2b688ea5 520 flow->esw_attr->modify_hdr = mh->modify_hdr;
11c9c548 521 else
2b688ea5 522 flow->nic_attr->modify_hdr = mh->modify_hdr;
11c9c548
OG		 523
524 return 0;
525
a734d007
VB		 526alloc_header_err:
527 complete_all(&mh->res_ready);
528attach_header_err:
529 mlx5e_mod_hdr_put(priv, mh, namespace);
11c9c548
OG		 530 return err;
531}
532
533static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
534 struct mlx5e_tc_flow *flow)
535{
5a7e5bcb 536 /* flow wasn't fully initialized */
dd58edc3 537 if (!flow->mh)
5a7e5bcb
VB		 538 return;
539
83a52f0d 540 spin_lock(&flow->mh->flows_lock);
11c9c548 541 list_del(&flow->mod_hdr);
83a52f0d 542 spin_unlock(&flow->mh->flows_lock);
11c9c548 543
d2faae25 544 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
dd58edc3 545 flow->mh = NULL;
11c9c548
OG		 546}
547
77ab67b7
OG		 548static
549struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
550{
551 struct net_device *netdev;
552 struct mlx5e_priv *priv;
553
554 netdev = __dev_get_by_index(net, ifindex);
555 priv = netdev_priv(netdev);
556 return priv->mdev;
557}
558
559static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
560{
e0b4b472 561 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 562 void *tirc;
563 int err;
564
565 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
566 if (err)
567 goto alloc_tdn_err;
568
569 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
570
571 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 572 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 573 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
574
e0b4b472 575 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 576 if (err)
577 goto create_tir_err;
578
579 return 0;
580
581create_tir_err:
582 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
583alloc_tdn_err:
584 return err;
585}
586
587static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
588{
589 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
590 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
591}
592
3f6d08d1
OG		 593static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
594{
595 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
596 struct mlx5e_priv *priv = hp->func_priv;
597 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
598
599 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
600 hp->num_channels);
601
602 for (i = 0; i < sz; i++) {
603 ix = i;
bbeb53b8 604 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 605 ix = mlx5e_bits_invert(i, ilog2(sz));
606 ix = indirection_rqt[ix];
607 rqn = hp->pair->rqn[ix];
608 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
609 }
610}
611
612static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
613{
614 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
615 struct mlx5e_priv *priv = hp->func_priv;
616 struct mlx5_core_dev *mdev = priv->mdev;
617 void *rqtc;
618 u32 *in;
619
620 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
621 in = kvzalloc(inlen, GFP_KERNEL);
622 if (!in)
623 return -ENOMEM;
624
625 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
626
627 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
628 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
629
630 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
631
632 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
633 if (!err)
634 hp->indir_rqt.enabled = true;
635
636 kvfree(in);
637 return err;
638}
639
640static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
641{
642 struct mlx5e_priv *priv = hp->func_priv;
643 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
644 int tt, i, err;
645 void *tirc;
646
647 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 648 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
649
3f6d08d1
OG		 650 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
651 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
652
653 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
654 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
655 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 656 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
657
3f6d08d1 658 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 659 &hp->indir_tirn[tt]);
3f6d08d1
OG		 660 if (err) {
661 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
662 goto err_destroy_tirs;
663 }
664 }
665 return 0;
666
667err_destroy_tirs:
668 for (i = 0; i < tt; i++)
669 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
670 return err;
671}
672
673static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
674{
675 int tt;
676
677 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
678 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
679}
680
681static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
682 struct ttc_params *ttc_params)
683{
684 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
685 int tt;
686
687 memset(ttc_params, 0, sizeof(*ttc_params));
688
689 ttc_params->any_tt_tirn = hp->tirn;
690
691 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
692 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
693
6412bb39 694 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 695 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
696 ft_attr->prio = MLX5E_TC_PRIO;
697}
698
699static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
700{
701 struct mlx5e_priv *priv = hp->func_priv;
702 struct ttc_params ttc_params;
703 int err;
704
705 err = mlx5e_hairpin_create_indirect_rqt(hp);
706 if (err)
707 return err;
708
709 err = mlx5e_hairpin_create_indirect_tirs(hp);
710 if (err)
711 goto err_create_indirect_tirs;
712
713 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
714 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
715 if (err)
716 goto err_create_ttc_table;
717
718 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
719 hp->num_channels, hp->ttc.ft.t->id);
720
721 return 0;
722
723err_create_ttc_table:
724 mlx5e_hairpin_destroy_indirect_tirs(hp);
725err_create_indirect_tirs:
726 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
727
728 return err;
729}
730
731static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
732{
733 struct mlx5e_priv *priv = hp->func_priv;
734
735 mlx5e_destroy_ttc_table(priv, &hp->ttc);
736 mlx5e_hairpin_destroy_indirect_tirs(hp);
737 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
738}
739
77ab67b7
OG		 740static struct mlx5e_hairpin *
741mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
742 int peer_ifindex)
743{
744 struct mlx5_core_dev *func_mdev, *peer_mdev;
745 struct mlx5e_hairpin *hp;
746 struct mlx5_hairpin *pair;
747 int err;
748
749 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
750 if (!hp)
751 return ERR_PTR(-ENOMEM);
752
753 func_mdev = priv->mdev;
754 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
755
756 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
757 if (IS_ERR(pair)) {
758 err = PTR_ERR(pair);
759 goto create_pair_err;
760 }
761 hp->pair = pair;
762 hp->func_mdev = func_mdev;
3f6d08d1
OG		 763 hp->func_priv = priv;
764 hp->num_channels = params->num_channels;
77ab67b7
OG		 765
766 err = mlx5e_hairpin_create_transport(hp);
767 if (err)
768 goto create_transport_err;
769
3f6d08d1
OG		 770 if (hp->num_channels > 1) {
771 err = mlx5e_hairpin_rss_init(hp);
772 if (err)
773 goto rss_init_err;
774 }
775
77ab67b7
OG		 776 return hp;
777
3f6d08d1
OG		 778rss_init_err:
779 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 780create_transport_err:
781 mlx5_core_hairpin_destroy(hp->pair);
782create_pair_err:
783 kfree(hp);
784 return ERR_PTR(err);
785}
786
787static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
788{
3f6d08d1
OG		 789 if (hp->num_channels > 1)
790 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 791 mlx5e_hairpin_destroy_transport(hp);
792 mlx5_core_hairpin_destroy(hp->pair);
793 kvfree(hp);
794}
795
106be53b
OG		 796static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
797{
798 return (peer_vhca_id << 16 | prio);
799}
800
5c65c564 801static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 802 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 803{
804 struct mlx5e_hairpin_entry *hpe;
106be53b 805 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 806
807 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 808 hairpin_hlist, hash_key) {
e4f9abbd
VB		 809 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
810 refcount_inc(&hpe->refcnt);
5c65c564 811 return hpe;
e4f9abbd 812 }
5c65c564
OG		 813 }
814
815 return NULL;
816}
817
e4f9abbd
VB		 818static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
819 struct mlx5e_hairpin_entry *hpe)
820{
821 /* no more hairpin flows for us, release the hairpin pair */
b32accda 822 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 823 return;
b32accda
VB		 824 hash_del(&hpe->hairpin_hlist);
825 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 826
db76ca24
VB		 827 if (!IS_ERR_OR_NULL(hpe->hp)) {
828 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
829 dev_name(hpe->hp->pair->peer_mdev->device));
830
831 mlx5e_hairpin_destroy(hpe->hp);
832 }
e4f9abbd
VB		 833
834 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 835 kfree(hpe);
836}
837
106be53b
OG		 838#define UNKNOWN_MATCH_PRIO 8
839
840static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 841 struct mlx5_flow_spec *spec, u8 *match_prio,
842 struct netlink_ext_ack *extack)
106be53b
OG		 843{
844 void *headers_c, *headers_v;
845 u8 prio_val, prio_mask = 0;
846 bool vlan_present;
847
848#ifdef CONFIG_MLX5_CORE_EN_DCB
849 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 850 NL_SET_ERR_MSG_MOD(extack,
851 "only PCP trust state supported for hairpin");
106be53b
OG		 852 return -EOPNOTSUPP;
853 }
854#endif
855 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
856 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
857
858 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
859 if (vlan_present) {
860 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
861 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
862 }
863
864 if (!vlan_present || !prio_mask) {
865 prio_val = UNKNOWN_MATCH_PRIO;
866 } else if (prio_mask != 0x7) {
e98bedf5
EB		 867 NL_SET_ERR_MSG_MOD(extack,
868 "masked priority match not supported for hairpin");
106be53b
OG		 869 return -EOPNOTSUPP;
870 }
871
872 *match_prio = prio_val;
873 return 0;
874}
875
5c65c564
OG		 876static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
877 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 878 struct mlx5e_tc_flow_parse_attr *parse_attr,
879 struct netlink_ext_ack *extack)
5c65c564 880{
98b66cb1 881 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 882 struct mlx5_hairpin_params params;
d8822868 883 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 884 struct mlx5e_hairpin_entry *hpe;
885 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 886 u64 link_speed64;
887 u32 link_speed;
106be53b 888 u8 match_prio;
d8822868 889 u16 peer_id;
5c65c564
OG		 890 int err;
891
d8822868
OG		 892 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
893 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 894 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 895 return -EOPNOTSUPP;
896 }
897
d8822868 898 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 899 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
900 extack);
106be53b
OG		 901 if (err)
902 return err;
b32accda
VB		 903
904 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 905 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 906 if (hpe) {
907 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
908 wait_for_completion(&hpe->res_ready);
909
910 if (IS_ERR(hpe->hp)) {
911 err = -EREMOTEIO;
912 goto out_err;
913 }
5c65c564 914 goto attach_flow;
db76ca24 915 }
5c65c564
OG		 916
917 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 918 if (!hpe) {
db76ca24
VB		 919 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
920 return -ENOMEM;
b32accda 921 }
5c65c564 922
73edca73 923 spin_lock_init(&hpe->flows_lock);
5c65c564 924 INIT_LIST_HEAD(&hpe->flows);
db76ca24 925 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 926 hpe->peer_vhca_id = peer_id;
106be53b 927 hpe->prio = match_prio;
e4f9abbd 928 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 929 init_completion(&hpe->res_ready);
930
931 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
932 hash_hairpin_info(peer_id, match_prio));
933 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 934
935 params.log_data_size = 15;
936 params.log_data_size = min_t(u8, params.log_data_size,
937 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
938 params.log_data_size = max_t(u8, params.log_data_size,
939 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 940
eb9180f7
OG		 941 params.log_num_packets = params.log_data_size -
942 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
943 params.log_num_packets = min_t(u8, params.log_num_packets,
944 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
945
946 params.q_counter = priv->q_counter;
3f6d08d1 947 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 948 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 949 link_speed = max_t(u32, link_speed, 50000);
950 link_speed64 = link_speed;
951 do_div(link_speed64, 50000);
952 params.num_channels = link_speed64;
953
5c65c564 954 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 955 hpe->hp = hp;
956 complete_all(&hpe->res_ready);
5c65c564
OG		 957 if (IS_ERR(hp)) {
958 err = PTR_ERR(hp);
db76ca24 959 goto out_err;
5c65c564
OG		 960 }
961
eb9180f7 962 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 963 hp->tirn, hp->pair->rqn[0],
964 dev_name(hp->pair->peer_mdev->device),
eb9180f7 965 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 966
5c65c564 967attach_flow:
3f6d08d1 968 if (hpe->hp->num_channels > 1) {
226f2ca3 969 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 970 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
971 } else {
972 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
973 }
b32accda 974
e4f9abbd 975 flow->hpe = hpe;
73edca73 976 spin_lock(&hpe->flows_lock);
5c65c564 977 list_add(&flow->hairpin, &hpe->flows);
73edca73 978 spin_unlock(&hpe->flows_lock);
3f6d08d1 979
5c65c564
OG		 980 return 0;
981
db76ca24
VB		 982out_err:
983 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 984 return err;
985}
986
987static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
988 struct mlx5e_tc_flow *flow)
989{
5a7e5bcb 990 /* flow wasn't fully initialized */
e4f9abbd 991 if (!flow->hpe)
5a7e5bcb
VB		 992 return;
993
73edca73 994 spin_lock(&flow->hpe->flows_lock);
5c65c564 995 list_del(&flow->hairpin);
73edca73
VB		 996 spin_unlock(&flow->hpe->flows_lock);
997
e4f9abbd
VB		 998 mlx5e_hairpin_put(priv, flow->hpe);
999 flow->hpe = NULL;
5c65c564
OG		 1000}
1001
c83954ab 1002static int
74491de9 1003mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 1004 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 1005 struct mlx5e_tc_flow *flow,
1006 struct netlink_ext_ack *extack)
e8f887ac 1007{
bb0ee7dc 1008 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 1009 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 1010 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 1011 struct mlx5_flow_destination dest[2] = {};
66958ed9 1012 struct mlx5_flow_act flow_act = {
3bc4b7bf 1013 .action = attr->action,
bb0ee7dc 1014 .flags = FLOW_ACT_NO_APPEND,
66958ed9 1015 };
aad7e08d 1016 struct mlx5_fc *counter = NULL;
5c65c564 1017 int err, dest_ix = 0;
e8f887ac 1018
bb0ee7dc
JL		 1019 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1020 flow_context->flow_tag = attr->flow_tag;
1021
226f2ca3 1022 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 1023 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 1024 if (err)
1025 return err;
1026
226f2ca3 1027 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 1028 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1029 dest[dest_ix].ft = attr->hairpin_ft;
1030 } else {
5c65c564
OG		 1031 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1032 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 1033 }
1034 dest_ix++;
3f6d08d1
OG		 1035 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1036 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1037 dest[dest_ix].ft = priv->fs.vlan.ft.t;
1038 dest_ix++;
5c65c564 1039 }
aad7e08d 1040
5c65c564
OG		 1041 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1042 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 1043 if (IS_ERR(counter))
1044 return PTR_ERR(counter);
1045
5c65c564 1046 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 1047 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 1048 dest_ix++;
b8aee822 1049 attr->counter = counter;
aad7e08d
AV		 1050 }
1051
2f4fe4ca 1052 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 1053 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 1054 flow_act.modify_hdr = attr->modify_hdr;
6ae4a6a5 1055 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1056 if (err)
5a7e5bcb 1057 return err;
2f4fe4ca
OG		 1058 }
1059
b6fac0b4 1060 mutex_lock(&priv->fs.tc.t_lock);
acff797c 1061 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
61dc7b01
PB		 1062 struct mlx5_flow_table_attr ft_attr = {};
1063 int tc_grp_size, tc_tbl_size, tc_num_grps;
21b9c144
OG		 1064 u32 max_flow_counter;
1065
1066 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1067 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1068
1069 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
1070
1071 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
1072 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
61dc7b01 1073 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
21b9c144 1074
61dc7b01
PB		 1075 ft_attr.prio = MLX5E_TC_PRIO;
1076 ft_attr.max_fte = tc_tbl_size;
1077 ft_attr.level = MLX5E_TC_FT_LEVEL;
1078 ft_attr.autogroup.max_num_groups = tc_num_grps;
acff797c
MG		 1079 priv->fs.tc.t =
1080 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
61dc7b01 1081 &ft_attr);
acff797c 1082 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 1083 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5 1084 NL_SET_ERR_MSG_MOD(extack,
c75a33c8 1085 "Failed to create tc offload table");
e8f887ac
AV		 1086 netdev_err(priv->netdev,
1087 "Failed to create tc offload table\n");
5a7e5bcb 1088 return PTR_ERR(priv->fs.tc.t);
e8f887ac 1089 }
e8f887ac
AV		 1090 }
1091
38aa51c1 1092 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 1093 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1094
c83954ab
RL		 1095 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
1096 &flow_act, dest, dest_ix);
b6fac0b4 1097 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 1098
a2b7189b 1099 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1100}
1101
d85cdccb
OG		 1102static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1103 struct mlx5e_tc_flow *flow)
1104{
513f8f7f 1105 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 1106 struct mlx5_fc *counter = NULL;
1107
b8aee822 1108 counter = attr->counter;
5a7e5bcb
VB		 1109 if (!IS_ERR_OR_NULL(flow->rule[0]))
1110 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1111 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1112
b6fac0b4 1113 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1114 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1115 mlx5_destroy_flow_table(priv->fs.tc.t);
1116 priv->fs.tc.t = NULL;
1117 }
b6fac0b4 1118 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1119
513f8f7f 1120 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1121 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1122
226f2ca3 1123 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1124 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1125}
1126
aa0cbbae 1127static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1128 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1129
3c37745e 1130static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1131 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1132 struct net_device *mirred_dev,
1133 int out_index,
8c4dc42b 1134 struct netlink_ext_ack *extack,
0ad060ee
RD		 1135 struct net_device **encap_dev,
1136 bool *encap_valid);
14e6b038
EC		 1137static int mlx5e_attach_decap(struct mlx5e_priv *priv,
1138 struct mlx5e_tc_flow *flow,
1139 struct netlink_ext_ack *extack);
1140static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1141 struct mlx5e_tc_flow *flow);
3c37745e 1142
6d2a3ed0
OG		 1143static struct mlx5_flow_handle *
1144mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1145 struct mlx5e_tc_flow *flow,
1146 struct mlx5_flow_spec *spec,
1147 struct mlx5_esw_flow_attr *attr)
1148{
1ef3018f 1149 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1150 struct mlx5_flow_handle *rule;
4c3844d9 1151
1ef3018f
PB		 1152 if (flow_flag_test(flow, CT)) {
1153 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1154
1155 return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr,
1156 mod_hdr_acts);
1157 }
6d2a3ed0
OG		 1158
1159 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1160 if (IS_ERR(rule))
1161 return rule;
1162
e85e02ba 1163 if (attr->split_count) {
6d2a3ed0
OG		 1164 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1165 if (IS_ERR(flow->rule[1])) {
1166 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1167 return flow->rule[1];
1168 }
1169 }
1170
6d2a3ed0
OG		 1171 return rule;
1172}
1173
1174static void
1175mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1176 struct mlx5e_tc_flow *flow,
4c3844d9 1177 struct mlx5_esw_flow_attr *attr)
6d2a3ed0 1178{
226f2ca3 1179 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1180
4c3844d9
PB		 1181 if (flow_flag_test(flow, CT)) {
1182 mlx5_tc_ct_delete_flow(flow->priv, flow, attr);
1183 return;
1184 }
1185
e85e02ba 1186 if (attr->split_count)
6d2a3ed0
OG		 1187 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1188
1189 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1190}
1191
5dbe906f
PB		 1192static struct mlx5_flow_handle *
1193mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1194 struct mlx5e_tc_flow *flow,
178f69b4 1195 struct mlx5_flow_spec *spec)
5dbe906f 1196{
178f69b4 1197 struct mlx5_esw_flow_attr slow_attr;
5dbe906f
PB		 1198 struct mlx5_flow_handle *rule;
1199
178f69b4
EC		 1200 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1201 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1202 slow_attr.split_count = 0;
1203 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f 1204
178f69b4 1205 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
5dbe906f 1206 if (!IS_ERR(rule))
226f2ca3 1207 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1208
1209 return rule;
1210}
1211
1212static void
1213mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1214 struct mlx5e_tc_flow *flow)
5dbe906f 1215{
178f69b4
EC		 1216 struct mlx5_esw_flow_attr slow_attr;
1217
1218 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1219 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1220 slow_attr.split_count = 0;
1221 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1222 mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
226f2ca3 1223 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1224}
1225
ad86755b
VB		 1226/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1227 * function.
1228 */
1229static void unready_flow_add(struct mlx5e_tc_flow *flow,
1230 struct list_head *unready_flows)
1231{
1232 flow_flag_set(flow, NOT_READY);
1233 list_add_tail(&flow->unready, unready_flows);
1234}
1235
1236/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1237 * function.
1238 */
1239static void unready_flow_del(struct mlx5e_tc_flow *flow)
1240{
1241 list_del(&flow->unready);
1242 flow_flag_clear(flow, NOT_READY);
1243}
1244
b4a23329
RD		 1245static void add_unready_flow(struct mlx5e_tc_flow *flow)
1246{
1247 struct mlx5_rep_uplink_priv *uplink_priv;
1248 struct mlx5e_rep_priv *rpriv;
1249 struct mlx5_eswitch *esw;
1250
1251 esw = flow->priv->mdev->priv.eswitch;
1252 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1253 uplink_priv = &rpriv->uplink_priv;
1254
ad86755b
VB		 1255 mutex_lock(&uplink_priv->unready_flows_lock);
1256 unready_flow_add(flow, &uplink_priv->unready_flows);
1257 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1258}
1259
1260static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1261{
ad86755b
VB		 1262 struct mlx5_rep_uplink_priv *uplink_priv;
1263 struct mlx5e_rep_priv *rpriv;
1264 struct mlx5_eswitch *esw;
1265
1266 esw = flow->priv->mdev->priv.eswitch;
1267 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1268 uplink_priv = &rpriv->uplink_priv;
1269
1270 mutex_lock(&uplink_priv->unready_flows_lock);
1271 unready_flow_del(flow);
1272 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1273}
1274
c83954ab 1275static int
74491de9 1276mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1277 struct mlx5e_tc_flow *flow,
1278 struct netlink_ext_ack *extack)
adb4c123
OG		 1279{
1280 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 1281 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1282 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3c37745e 1283 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1284 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1285 struct mlx5e_rep_priv *rpriv;
1286 struct mlx5e_priv *out_priv;
0ad060ee 1287 bool encap_valid = true;
39ac237c 1288 u32 max_prio, max_chain;
0ad060ee 1289 int err = 0;
f493f155 1290 int out_index;
8b32580d 1291
39ac237c 1292 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
61644c3d
RD		 1293 NL_SET_ERR_MSG_MOD(extack,
1294 "E-switch priorities unsupported, upgrade FW");
d14f6f2a
OG		 1295 return -EOPNOTSUPP;
1296 }
bf07aa73 1297
84179981
PB		 1298 /* We check chain range only for tc flows.
1299 * For ft flows, we checked attr->chain was originally 0 and set it to
1300 * FDB_FT_CHAIN which is outside tc range.
1301 * See mlx5e_rep_setup_ft_cb().
1302 */
39ac237c 1303 max_chain = mlx5_esw_chains_get_chain_range(esw);
84179981 1304 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1305 NL_SET_ERR_MSG_MOD(extack,
1306 "Requested chain is out of supported range");
5a7e5bcb 1307 return -EOPNOTSUPP;
bf07aa73
PB		 1308 }
1309
39ac237c 1310 max_prio = mlx5_esw_chains_get_prio_range(esw);
bf07aa73 1311 if (attr->prio > max_prio) {
61644c3d
RD		 1312 NL_SET_ERR_MSG_MOD(extack,
1313 "Requested priority is out of supported range");
5a7e5bcb 1314 return -EOPNOTSUPP;
bf07aa73 1315 }
e52c2802 1316
14e6b038
EC		 1317 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1318 err = mlx5e_attach_decap(priv, flow, extack);
1319 if (err)
1320 return err;
1321 }
1322
f493f155 1323 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1324 int mirred_ifindex;
1325
f493f155
EB		 1326 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1327 continue;
1328
7040632d 1329 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1330 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1331 mirred_ifindex);
733d4f36 1332 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1333 extack, &encap_dev, &encap_valid);
1334 if (err)
5a7e5bcb 1335 return err;
0ad060ee 1336
3c37745e
OG		 1337 out_priv = netdev_priv(encap_dev);
1338 rpriv = out_priv->ppriv;
1cc26d74
EB		 1339 attr->dests[out_index].rep = rpriv->rep;
1340 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1341 }
1342
8b32580d 1343 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1344 if (err)
5a7e5bcb 1345 return err;
adb4c123 1346
d5a3c2b6
RD		 1347 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1348 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1a9527bb 1349 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1350 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1351 if (err)
5a7e5bcb 1352 return err;
d7e75a32
OG		 1353 }
1354
b8aee822 1355 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1356 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1357 if (IS_ERR(counter))
1358 return PTR_ERR(counter);
b8aee822
MB		 1359
1360 attr->counter = counter;
1361 }
1362
0ad060ee
RD		 1363 /* we get here if one of the following takes place:
1364 * (1) there's no error
1365 * (2) there's an encap action and we don't have valid neigh
3c37745e 1366 */
bc1d75fa 1367 if (!encap_valid)
178f69b4 1368 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1369 else
6d2a3ed0 1370 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1371
5a7e5bcb
VB		 1372 if (IS_ERR(flow->rule[0]))
1373 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1374 else
1375 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1376
1377 return 0;
aa0cbbae 1378}
d85cdccb 1379
9272e3df
YK		 1380static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1381{
1382 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1383 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1384 spec->match_value,
1385 misc_parameters_3);
1386 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1387 headers_v,
1388 geneve_tlv_option_0_data);
1389
1390 return !!geneve_tlv_opt_0_data;
1391}
1392
d85cdccb
OG		 1393static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1394 struct mlx5e_tc_flow *flow)
1395{
1396 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1397 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
f493f155 1398 int out_index;
d85cdccb 1399
0a7fcb78
PB		 1400 mlx5e_put_flow_tunnel_id(flow);
1401
226f2ca3 1402 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1403 remove_unready_flow(flow);
ef06c9ee
RD		 1404 kvfree(attr->parse_attr);
1405 return;
1406 }
1407
226f2ca3
VB		 1408 if (mlx5e_is_offloaded_flow(flow)) {
1409 if (flow_flag_test(flow, SLOW))
178f69b4 1410 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1411 else
1412 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1413 }
d85cdccb 1414
9272e3df
YK		 1415 if (mlx5_flow_has_geneve_opt(flow))
1416 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1417
513f8f7f 1418 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1419
f493f155 1420 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1421 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1422 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1423 kfree(attr->parse_attr->tun_info[out_index]);
1424 }
f493f155 1425 kvfree(attr->parse_attr);
d7e75a32 1426
513f8f7f 1427 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1428 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1429
1430 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1431 mlx5_fc_destroy(attr->counter_dev, attr->counter);
14e6b038
EC		 1432
1433 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1434 mlx5e_detach_decap(priv, flow);
d85cdccb
OG		 1435}
1436
232c0013 1437void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1438 struct mlx5e_encap_entry *e,
1439 struct list_head *flow_list)
232c0013 1440{
3c37745e 1441 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1442 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0
OG		 1443 struct mlx5_flow_handle *rule;
1444 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1445 struct mlx5e_tc_flow *flow;
1446 int err;
1447
2b688ea5
MG		 1448 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1449 e->reformat_type,
1450 e->encap_size, e->encap_header,
1451 MLX5_FLOW_NAMESPACE_FDB);
1452 if (IS_ERR(e->pkt_reformat)) {
1453 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1454 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1455 return;
1456 }
1457 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1458 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1459
2a1f1768 1460 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1461 bool all_flow_encaps_valid = true;
1462 int i;
1463
95435ad7
VB		 1464 if (!mlx5e_is_offloaded_flow(flow))
1465 continue;
3c37745e 1466 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1467 spec = &esw_attr->parse_attr->spec;
1468
2b688ea5 1469 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1470 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1471 /* Flow can be associated with multiple encap entries.
1472 * Before offloading the flow verify that all of them have
1473 * a valid neighbour.
1474 */
1475 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1476 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1477 continue;
1478 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1479 all_flow_encaps_valid = false;
1480 break;
1481 }
1482 }
1483 /* Do not offload flows with unresolved neighbors */
1484 if (!all_flow_encaps_valid)
2a1f1768 1485 continue;
5dbe906f 1486 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1487 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1488 if (IS_ERR(rule)) {
1489 err = PTR_ERR(rule);
232c0013
HHZ		 1490 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1491 err);
2a1f1768 1492 continue;
232c0013 1493 }
5dbe906f 1494
178f69b4 1495 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1496 flow->rule[0] = rule;
226f2ca3
VB		 1497 /* was unset when slow path rule removed */
1498 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1499 }
1500}
1501
1502void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1503 struct mlx5e_encap_entry *e,
1504 struct list_head *flow_list)
232c0013 1505{
3c37745e 1506 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1507 struct mlx5_flow_handle *rule;
1508 struct mlx5_flow_spec *spec;
232c0013 1509 struct mlx5e_tc_flow *flow;
5dbe906f 1510 int err;
232c0013 1511
2a1f1768 1512 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1513 if (!mlx5e_is_offloaded_flow(flow))
1514 continue;
5dbe906f
PB		 1515 spec = &flow->esw_attr->parse_attr->spec;
1516
1517 /* update from encap rule to slow path rule */
178f69b4 1518 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1519 /* mark the flow's encap dest as non-valid */
2a1f1768 1520 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1521
1522 if (IS_ERR(rule)) {
1523 err = PTR_ERR(rule);
1524 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1525 err);
2a1f1768 1526 continue;
5dbe906f
PB		 1527 }
1528
1529 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1530 flow->rule[0] = rule;
226f2ca3
VB		 1531 /* was unset when fast path rule removed */
1532 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1533 }
1534
61c806da
OG		 1535 /* we know that the encap is valid */
1536 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1537 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1538}
1539
b8aee822
MB		 1540static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1541{
226f2ca3 1542 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1543 return flow->esw_attr->counter;
1544 else
1545 return flow->nic_attr->counter;
1546}
1547
2a1f1768
VB		 1548/* Takes reference to all flows attached to encap and adds the flows to
1549 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1550 */
1551void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1552{
1553 struct encap_flow_item *efi;
1554 struct mlx5e_tc_flow *flow;
1555
1556 list_for_each_entry(efi, &e->flows, list) {
1557 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1558 if (IS_ERR(mlx5e_flow_get(flow)))
1559 continue;
95435ad7 1560 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1561
1562 flow->tmp_efi_index = efi->index;
1563 list_add(&flow->tmp_list, flow_list);
1564 }
1565}
1566
6a06c2f7 1567/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1568void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1569{
1570 struct mlx5e_tc_flow *flow, *tmp;
1571
1572 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1573 mlx5e_flow_put(priv, flow);
1574}
1575
ac0d9176
VB		 1576static struct mlx5e_encap_entry *
1577mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1578 struct mlx5e_encap_entry *e)
1579{
1580 struct mlx5e_encap_entry *next = NULL;
1581
1582retry:
1583 rcu_read_lock();
1584
1585 /* find encap with non-zero reference counter value */
1586 for (next = e ?
1587 list_next_or_null_rcu(&nhe->encap_list,
1588 &e->encap_list,
1589 struct mlx5e_encap_entry,
1590 encap_list) :
1591 list_first_or_null_rcu(&nhe->encap_list,
1592 struct mlx5e_encap_entry,
1593 encap_list);
1594 next;
1595 next = list_next_or_null_rcu(&nhe->encap_list,
1596 &next->encap_list,
1597 struct mlx5e_encap_entry,
1598 encap_list))
1599 if (mlx5e_encap_take(next))
1600 break;
1601
1602 rcu_read_unlock();
1603
1604 /* release starting encap */
1605 if (e)
1606 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1607 if (!next)
1608 return next;
1609
1610 /* wait for encap to be fully initialized */
1611 wait_for_completion(&next->res_ready);
1612 /* continue searching if encap entry is not in valid state after completion */
1613 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1614 e = next;
1615 goto retry;
1616 }
1617
1618 return next;
1619}
1620
f6dfb4c3
HHZ		 1621void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1622{
1623 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1624 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1625 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1626 struct mlx5_fc *counter;
1627 struct neigh_table *tbl;
1628 bool neigh_used = false;
1629 struct neighbour *n;
90bb7692 1630 u64 lastuse;
f6dfb4c3
HHZ		 1631
1632 if (m_neigh->family == AF_INET)
1633 tbl = &arp_tbl;
1634#if IS_ENABLED(CONFIG_IPV6)
1635 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1636 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1637#endif
1638 else
1639 return;
1640
ac0d9176
VB		 1641 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1642 * next one.
1643 */
1644 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1645 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1646 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1647 struct mlx5_eswitch *esw;
1648 LIST_HEAD(flow_list);
948993f2 1649
6a06c2f7
VB		 1650 esw = priv->mdev->priv.eswitch;
1651 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1652 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1653 flow = container_of(efi, struct mlx5e_tc_flow,
1654 encaps[efi->index]);
5a7e5bcb
VB		 1655 if (IS_ERR(mlx5e_flow_get(flow)))
1656 continue;
6a06c2f7 1657 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1658
226f2ca3 1659 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1660 counter = mlx5e_tc_get_counter(flow);
90bb7692 1661 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1662 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1663 neigh_used = true;
1664 break;
1665 }
1666 }
1667 }
6a06c2f7 1668 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1669
6a06c2f7 1670 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1671 if (neigh_used) {
1672 /* release current encap before breaking the loop */
6a06c2f7 1673 mlx5e_encap_put(priv, e);
e36d4810 1674 break;
ac0d9176 1675 }
f6dfb4c3
HHZ		 1676 }
1677
c786fe59
VB		 1678 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1679
f6dfb4c3
HHZ		 1680 if (neigh_used) {
1681 nhe->reported_lastuse = jiffies;
1682
1683 /* find the relevant neigh according to the cached device and
1684 * dst ip pair
1685 */
1686 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1687 if (!n)
f6dfb4c3 1688 return;
f6dfb4c3
HHZ		 1689
1690 neigh_event_send(n, NULL);
1691 neigh_release(n);
1692 }
1693}
1694
61086f39 1695static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1696{
948993f2 1697 WARN_ON(!list_empty(&e->flows));
948993f2 1698
3c140dd5
VB		 1699 if (e->compl_result > 0) {
1700 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1701
1702 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1703 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1704 }
948993f2 1705
2a4b6526 1706 kfree(e->tun_info);
948993f2 1707 kfree(e->encap_header);
ac0d9176 1708 kfree_rcu(e, rcu);
948993f2
VB		 1709}
1710
14e6b038
EC		 1711static void mlx5e_decap_dealloc(struct mlx5e_priv *priv,
1712 struct mlx5e_decap_entry *d)
1713{
1714 WARN_ON(!list_empty(&d->flows));
1715
1716 if (!d->compl_result)
1717 mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat);
1718
1719 kfree_rcu(d, rcu);
1720}
1721
61086f39
VB		 1722void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1723{
1724 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1725
1726 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1727 return;
1728 hash_del_rcu(&e->encap_hlist);
1729 mutex_unlock(&esw->offloads.encap_tbl_lock);
1730
1731 mlx5e_encap_dealloc(priv, e);
1732}
1733
14e6b038
EC		 1734static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d)
1735{
1736 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1737
1738 if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock))
1739 return;
1740 hash_del_rcu(&d->hlist);
1741 mutex_unlock(&esw->offloads.decap_tbl_lock);
1742
1743 mlx5e_decap_dealloc(priv, d);
1744}
1745
d85cdccb 1746static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1747 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1748{
61086f39
VB		 1749 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1750 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1751
5a7e5bcb 1752 /* flow wasn't fully initialized */
61086f39 1753 if (!e)
5a7e5bcb
VB		 1754 return;
1755
61086f39 1756 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1757 list_del(&flow->encaps[out_index].list);
948993f2 1758 flow->encaps[out_index].e = NULL;
61086f39
VB		 1759 if (!refcount_dec_and_test(&e->refcnt)) {
1760 mutex_unlock(&esw->offloads.encap_tbl_lock);
1761 return;
1762 }
1763 hash_del_rcu(&e->encap_hlist);
1764 mutex_unlock(&esw->offloads.encap_tbl_lock);
1765
1766 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1767}
1768
14e6b038
EC		 1769static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1770 struct mlx5e_tc_flow *flow)
1771{
1772 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1773 struct mlx5e_decap_entry *d = flow->decap_reformat;
1774
1775 if (!d)
1776 return;
1777
1778 mutex_lock(&esw->offloads.decap_tbl_lock);
1779 list_del(&flow->l3_to_l2_reformat);
1780 flow->decap_reformat = NULL;
1781
1782 if (!refcount_dec_and_test(&d->refcnt)) {
1783 mutex_unlock(&esw->offloads.decap_tbl_lock);
1784 return;
1785 }
1786 hash_del_rcu(&d->hlist);
1787 mutex_unlock(&esw->offloads.decap_tbl_lock);
1788
1789 mlx5e_decap_dealloc(priv, d);
1790}
1791
04de7dda
RD		 1792static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1793{
1794 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1795
226f2ca3
VB		 1796 if (!flow_flag_test(flow, ESWITCH) ||
1797 !flow_flag_test(flow, DUP))
04de7dda
RD		 1798 return;
1799
1800 mutex_lock(&esw->offloads.peer_mutex);
1801 list_del(&flow->peer);
1802 mutex_unlock(&esw->offloads.peer_mutex);
1803
226f2ca3 1804 flow_flag_clear(flow, DUP);
04de7dda 1805
eb252c3a
RD		 1806 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1807 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1808 kfree(flow->peer_flow);
1809 }
1810
04de7dda
RD		 1811 flow->peer_flow = NULL;
1812}
1813
1814static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1815{
1816 struct mlx5_core_dev *dev = flow->priv->mdev;
1817 struct mlx5_devcom *devcom = dev->priv.devcom;
1818 struct mlx5_eswitch *peer_esw;
1819
1820 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1821 if (!peer_esw)
1822 return;
1823
1824 __mlx5e_tc_del_fdb_peer_flow(flow);
1825 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1826}
1827
e8f887ac 1828static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1829 struct mlx5e_tc_flow *flow)
e8f887ac 1830{
226f2ca3 1831 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1832 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1833 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1834 } else {
d85cdccb 1835 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1836 }
e8f887ac
AV		 1837}
1838
0a7fcb78
PB		 1839static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1840{
1841 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1842 struct flow_action *flow_action = &rule->action;
1843 const struct flow_action_entry *act;
1844 int i;
1845
1846 flow_action_for_each(i, act, flow_action) {
1847 switch (act->id) {
1848 case FLOW_ACTION_GOTO:
1849 return true;
1850 default:
1851 continue;
1852 }
1853 }
1854
1855 return false;
1856}
bbd00f7e 1857
0a7fcb78
PB		 1858static int
1859enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1860 struct flow_dissector_key_enc_opts *opts,
1861 struct netlink_ext_ack *extack,
1862 bool *dont_care)
1863{
1864 struct geneve_opt *opt;
1865 int off = 0;
1866
1867 *dont_care = true;
1868
1869 while (opts->len > off) {
1870 opt = (struct geneve_opt *)&opts->data[off];
1871
1872 if (!(*dont_care) || opt->opt_class || opt->type ||
1873 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1874 *dont_care = false;
1875
1876 if (opt->opt_class != U16_MAX ||
d7a42ad0 1877 opt->type != U8_MAX) {
0a7fcb78
PB		 1878 NL_SET_ERR_MSG(extack,
1879 "Partial match of tunnel options in chain > 0 isn't supported");
1880 netdev_warn(priv->netdev,
1881 "Partial match of tunnel options in chain > 0 isn't supported");
1882 return -EOPNOTSUPP;
1883 }
1884 }
1885
1886 off += sizeof(struct geneve_opt) + opt->length * 4;
1887 }
1888
1889 return 0;
1890}
1891
1892#define COPY_DISSECTOR(rule, diss_key, dst)\
1893({ \
1894 struct flow_rule *__rule = (rule);\
1895 typeof(dst) __dst = dst;\
1896\
1897 memcpy(__dst,\
1898 skb_flow_dissector_target(__rule->match.dissector,\
1899 diss_key,\
1900 __rule->match.key),\
1901 sizeof(*__dst));\
1902})
1903
1904static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1905 struct mlx5e_tc_flow *flow,
1906 struct flow_cls_offload *f,
1907 struct net_device *filter_dev)
bbd00f7e 1908{
f9e30088 1909 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78
PB		 1910 struct netlink_ext_ack *extack = f->common.extack;
1911 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1912 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1913 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1914 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78
PB		 1915 struct mlx5_rep_uplink_priv *uplink_priv;
1916 struct mlx5e_rep_priv *uplink_rpriv;
1917 struct tunnel_match_key tunnel_key;
1918 bool enc_opts_is_dont_care = true;
1919 u32 tun_id, enc_opts_id = 0;
1920 struct mlx5_eswitch *esw;
1921 u32 value, mask;
8f256622 1922 int err;
2e72eb43 1923
0a7fcb78
PB		 1924 esw = priv->mdev->priv.eswitch;
1925 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1926 uplink_priv = &uplink_rpriv->uplink_priv;
1927
1928 memset(&tunnel_key, 0, sizeof(tunnel_key));
1929 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1930 &tunnel_key.enc_control);
1931 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1932 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1933 &tunnel_key.enc_ipv4);
1934 else
1935 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1936 &tunnel_key.enc_ipv6);
1937 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1938 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1939 &tunnel_key.enc_tp);
1940 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1941 &tunnel_key.enc_key_id);
1942 tunnel_key.filter_ifindex = filter_dev->ifindex;
1943
1944 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1945 if (err)
101f4de9 1946 return err;
bbd00f7e 1947
0a7fcb78
PB		 1948 flow_rule_match_enc_opts(rule, &enc_opts_match);
1949 err = enc_opts_is_dont_care_or_full_match(priv,
1950 enc_opts_match.mask,
1951 extack,
1952 &enc_opts_is_dont_care);
1953 if (err)
1954 goto err_enc_opts;
fe1587a7 1955
0a7fcb78 1956 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1957 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1958 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1959 sizeof(*enc_opts_match.key));
1960 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1961 sizeof(*enc_opts_match.mask));
1962
0a7fcb78 1963 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1964 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1965 if (err)
1966 goto err_enc_opts;
1967 }
fe1587a7 1968
0a7fcb78
PB		 1969 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1970 mask = enc_opts_id ? TUNNEL_ID_MASK :
1971 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1972
0a7fcb78
PB		 1973 if (attr->chain) {
1974 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1975 TUNNEL_TO_REG, value, mask);
1976 } else {
1977 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1978 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1979 mod_hdr_acts,
1980 TUNNEL_TO_REG, value);
1981 if (err)
1982 goto err_set;
fe1587a7 1983
0a7fcb78 1984 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1985 }
bbd00f7e 1986
0a7fcb78
PB		 1987 flow->tunnel_id = value;
1988 return 0;
bcef735c 1989
0a7fcb78
PB		 1990err_set:
1991 if (enc_opts_id)
1992 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1993 enc_opts_id);
1994err_enc_opts:
1995 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1996 return err;
1997}
bcef735c 1998
0a7fcb78
PB		 1999static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2000{
2001 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
2002 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
2003 struct mlx5_rep_uplink_priv *uplink_priv;
2004 struct mlx5e_rep_priv *uplink_rpriv;
2005 struct mlx5_eswitch *esw;
bcef735c 2006
0a7fcb78
PB		 2007 esw = flow->priv->mdev->priv.eswitch;
2008 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2009 uplink_priv = &uplink_rpriv->uplink_priv;
2010
2011 if (tun_id)
2012 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2013 if (enc_opts_id)
2014 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2015 enc_opts_id);
2016}
e98bedf5 2017
4c3844d9
PB		 2018u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
2019{
2020 return flow->tunnel_id;
2021}
2022
bbd00f7e 2023static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2024 struct mlx5e_tc_flow *flow,
bbd00f7e 2025 struct mlx5_flow_spec *spec,
f9e30088 2026 struct flow_cls_offload *f,
0a7fcb78
PB		 2027 struct net_device *filter_dev,
2028 u8 *match_level,
2029 bool *match_inner)
bbd00f7e 2030{
0a7fcb78 2031 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2032 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2033 bool needs_mapping, sets_mapping;
8f256622 2034 int err;
2e72eb43 2035
0a7fcb78
PB		 2036 if (!mlx5e_is_eswitch_flow(flow))
2037 return -EOPNOTSUPP;
2038
2039 needs_mapping = !!flow->esw_attr->chain;
2040 sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f);
2041 *match_inner = !needs_mapping;
2042
2043 if ((needs_mapping || sets_mapping) &&
636bb968 2044 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 2045 NL_SET_ERR_MSG(extack,
636bb968 2046 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2047 netdev_warn(priv->netdev,
636bb968 2048 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2049 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2050 }
2051
0a7fcb78
PB		 2052 if (!flow->esw_attr->chain) {
2053 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2054 match_level);
2055 if (err) {
e98bedf5 2056 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2057 "Failed to parse tunnel attributes");
2058 netdev_warn(priv->netdev,
2059 "Failed to parse tunnel attributes");
2060 return err;
e98bedf5
EB		 2061 }
2062
14e6b038
EC		 2063 /* With mpls over udp we decapsulate using packet reformat
2064 * object
2065 */
2066 if (!netif_is_bareudp(filter_dev))
2067 flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 2068 }
2069
0a7fcb78
PB		 2070 if (!needs_mapping && !sets_mapping)
2071 return 0;
bbd00f7e 2072
0a7fcb78 2073 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2074}
bbd00f7e 2075
0a7fcb78 2076static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2077{
0a7fcb78
PB		 2078 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2079 inner_headers);
bbd00f7e
HHZ		 2080}
2081
0a7fcb78 2082static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2083{
0a7fcb78
PB		 2084 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2085 inner_headers);
2086}
2087
2088static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2089{
2090 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2091 outer_headers);
2092}
2093
2094static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2095{
2096 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2097 outer_headers);
8377629e
EB		 2098}
2099
2100static void *get_match_headers_value(u32 flags,
2101 struct mlx5_flow_spec *spec)
2102{
2103 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2104 get_match_inner_headers_value(spec) :
2105 get_match_outer_headers_value(spec);
2106}
2107
2108static void *get_match_headers_criteria(u32 flags,
2109 struct mlx5_flow_spec *spec)
2110{
2111 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2112 get_match_inner_headers_criteria(spec) :
2113 get_match_outer_headers_criteria(spec);
8377629e
EB		 2114}
2115
6d65bc64 2116static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2117 struct flow_cls_offload *f)
2118{
2119 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2120 struct netlink_ext_ack *extack = f->common.extack;
2121 struct net_device *ingress_dev;
2122 struct flow_match_meta match;
2123
2124 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2125 return 0;
2126
2127 flow_rule_match_meta(rule, &match);
2128 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2129 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2130 return -EINVAL;
2131 }
2132
2133 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2134 match.key->ingress_ifindex);
2135 if (!ingress_dev) {
2136 NL_SET_ERR_MSG_MOD(extack,
2137 "Can't find the ingress port to match on");
2138 return -EINVAL;
2139 }
2140
2141 if (ingress_dev != filter_dev) {
2142 NL_SET_ERR_MSG_MOD(extack,
2143 "Can't match on the ingress filter port");
2144 return -EINVAL;
2145 }
2146
2147 return 0;
2148}
2149
72046a91
EC		 2150static bool skip_key_basic(struct net_device *filter_dev,
2151 struct flow_cls_offload *f)
2152{
2153 /* When doing mpls over udp decap, the user needs to provide
2154 * MPLS_UC as the protocol in order to be able to match on mpls
2155 * label fields. However, the actual ethertype is IP so we want to
2156 * avoid matching on this, otherwise we'll fail the match.
2157 */
2158 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2159 return true;
2160
2161 return false;
2162}
2163
de0af0bf 2164static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2165 struct mlx5e_tc_flow *flow,
de0af0bf 2166 struct mlx5_flow_spec *spec,
f9e30088 2167 struct flow_cls_offload *f,
54c177ca 2168 struct net_device *filter_dev,
93b3586e 2169 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2170{
e98bedf5 2171 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2172 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2173 outer_headers);
2174 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2175 outer_headers);
699e96dd
JL		 2176 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2177 misc_parameters);
2178 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2179 misc_parameters);
f9e30088 2180 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2181 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2182 u16 addr_type = 0;
2183 u8 ip_proto = 0;
93b3586e 2184 u8 *match_level;
6d65bc64 2185 int err;
e3a2b7ed 2186
93b3586e 2187 match_level = outer_match_level;
de0af0bf 2188
8f256622 2189 if (dissector->used_keys &
3d144578
VB		 2190 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2191 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2192 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2193 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2194 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2195 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2196 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2197 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2198 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2199 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2200 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2201 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2202 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2203 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2204 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2205 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2206 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2207 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91
EC		 2208 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2209 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2210 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 2211 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 2212 dissector->used_keys);
e3a2b7ed
AV		 2213 return -EOPNOTSUPP;
2214 }
2215
075973c7 2216 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2217 bool match_inner = false;
bbd00f7e 2218
0a7fcb78
PB		 2219 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2220 outer_match_level, &match_inner);
2221 if (err)
2222 return err;
2223
2224 if (match_inner) {
2225 /* header pointers should point to the inner headers
2226 * if the packet was decapsulated already.
2227 * outer headers are set by parse_tunnel_attr.
2228 */
2229 match_level = inner_match_level;
2230 headers_c = get_match_inner_headers_criteria(spec);
2231 headers_v = get_match_inner_headers_value(spec);
2232 }
bbd00f7e
HHZ		 2233 }
2234
6d65bc64 2235 err = mlx5e_flower_parse_meta(filter_dev, f);
2236 if (err)
2237 return err;
2238
72046a91
EC		 2239 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2240 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2241 struct flow_match_basic match;
2242
2243 flow_rule_match_basic(rule, &match);
d3a80bb5 2244 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 2245 ntohs(match.mask->n_proto));
d3a80bb5 2246 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 2247 ntohs(match.key->n_proto));
e3a2b7ed 2248
8f256622 2249 if (match.mask->n_proto)
d708f902 2250 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2251 }
35a605db
EB		 2252 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2253 is_vlan_dev(filter_dev)) {
2254 struct flow_dissector_key_vlan filter_dev_mask;
2255 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2256 struct flow_match_vlan match;
2257
35a605db
EB		 2258 if (is_vlan_dev(filter_dev)) {
2259 match.key = &filter_dev_key;
2260 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2261 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2262 match.key->vlan_priority = 0;
2263 match.mask = &filter_dev_mask;
2264 memset(match.mask, 0xff, sizeof(*match.mask));
2265 match.mask->vlan_priority = 0;
2266 } else {
2267 flow_rule_match_vlan(rule, &match);
2268 }
8f256622
PNA		 2269 if (match.mask->vlan_id ||
2270 match.mask->vlan_priority ||
2271 match.mask->vlan_tpid) {
2272 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2273 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2274 svlan_tag, 1);
2275 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2276 svlan_tag, 1);
2277 } else {
2278 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2279 cvlan_tag, 1);
2280 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2281 cvlan_tag, 1);
2282 }
095b6cfd 2283
8f256622
PNA		 2284 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2285 match.mask->vlan_id);
2286 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2287 match.key->vlan_id);
358d79a4 2288
8f256622
PNA		 2289 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2290 match.mask->vlan_priority);
2291 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2292 match.key->vlan_priority);
54782900 2293
d708f902 2294 *match_level = MLX5_MATCH_L2;
54782900 2295 }
d3a80bb5 2296 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2297 /* cvlan_tag enabled in match criteria and
2298 * disabled in match value means both S & C tags
2299 * don't exist (untagged of both)
2300 */
cee26487 2301 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2302 *match_level = MLX5_MATCH_L2;
54782900
OG		 2303 }
2304
8f256622
PNA		 2305 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2306 struct flow_match_vlan match;
2307
12d5cbf8 2308 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2309 if (match.mask->vlan_id ||
2310 match.mask->vlan_priority ||
2311 match.mask->vlan_tpid) {
2312 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2313 MLX5_SET(fte_match_set_misc, misc_c,
2314 outer_second_svlan_tag, 1);
2315 MLX5_SET(fte_match_set_misc, misc_v,
2316 outer_second_svlan_tag, 1);
2317 } else {
2318 MLX5_SET(fte_match_set_misc, misc_c,
2319 outer_second_cvlan_tag, 1);
2320 MLX5_SET(fte_match_set_misc, misc_v,
2321 outer_second_cvlan_tag, 1);
2322 }
2323
2324 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2325 match.mask->vlan_id);
699e96dd 2326 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2327 match.key->vlan_id);
699e96dd 2328 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2329 match.mask->vlan_priority);
699e96dd 2330 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2331 match.key->vlan_priority);
699e96dd
JL		 2332
2333 *match_level = MLX5_MATCH_L2;
2334 }
2335 }
2336
8f256622
PNA		 2337 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2338 struct flow_match_eth_addrs match;
54782900 2339
8f256622 2340 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2341 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2342 dmac_47_16),
8f256622 2343 match.mask->dst);
d3a80bb5
OG		 2344 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2345 dmac_47_16),
8f256622 2346 match.key->dst);
d3a80bb5
OG		 2347
2348 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2349 smac_47_16),
8f256622 2350 match.mask->src);
d3a80bb5
OG		 2351 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2352 smac_47_16),
8f256622 2353 match.key->src);
d3a80bb5 2354
8f256622
PNA		 2355 if (!is_zero_ether_addr(match.mask->src) ||
2356 !is_zero_ether_addr(match.mask->dst))
d708f902 2357 *match_level = MLX5_MATCH_L2;
54782900
OG		 2358 }
2359
8f256622
PNA		 2360 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2361 struct flow_match_control match;
54782900 2362
8f256622
PNA		 2363 flow_rule_match_control(rule, &match);
2364 addr_type = match.key->addr_type;
54782900
OG		 2365
2366 /* the HW doesn't support frag first/later */
8f256622 2367 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2368 return -EOPNOTSUPP;
2369
8f256622 2370 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2371 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2372 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2373 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2374
2375 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2376 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2377 *match_level = MLX5_MATCH_L2;
54782900
OG		 2378 /* *** L2 attributes parsing up to here *** */
2379 else
83621b7d 2380 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2381 }
2382 }
2383
8f256622
PNA		 2384 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2385 struct flow_match_basic match;
2386
2387 flow_rule_match_basic(rule, &match);
2388 ip_proto = match.key->ip_proto;
54782900
OG		 2389
2390 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2391 match.mask->ip_proto);
54782900 2392 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2393 match.key->ip_proto);
54782900 2394
8f256622 2395 if (match.mask->ip_proto)
d708f902 2396 *match_level = MLX5_MATCH_L3;
54782900
OG		 2397 }
2398
e3a2b7ed 2399 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2400 struct flow_match_ipv4_addrs match;
e3a2b7ed 2401
8f256622 2402 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2403 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2404 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2405 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2406 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2407 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2408 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2409 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2410 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2411 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2412 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2413 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2414 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2415
8f256622 2416 if (match.mask->src || match.mask->dst)
d708f902 2417 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2418 }
2419
2420 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2421 struct flow_match_ipv6_addrs match;
e3a2b7ed 2422
8f256622 2423 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2424 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2425 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2426 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2427 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2428 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2429 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2430
2431 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2432 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2433 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2434 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2435 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2436 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2437
8f256622
PNA		 2438 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2439 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2440 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2441 }
2442
8f256622
PNA		 2443 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2444 struct flow_match_ip match;
1f97a526 2445
8f256622
PNA		 2446 flow_rule_match_ip(rule, &match);
2447 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2448 match.mask->tos & 0x3);
2449 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2450 match.key->tos & 0x3);
1f97a526 2451
8f256622
PNA		 2452 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2453 match.mask->tos >> 2);
2454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2455 match.key->tos >> 2);
1f97a526 2456
8f256622
PNA		 2457 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2458 match.mask->ttl);
2459 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2460 match.key->ttl);
1f97a526 2461
8f256622 2462 if (match.mask->ttl &&
a8ade55f 2463 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2464 ft_field_support.outer_ipv4_ttl)) {
2465 NL_SET_ERR_MSG_MOD(extack,
2466 "Matching on TTL is not supported");
1f97a526 2467 return -EOPNOTSUPP;
e98bedf5 2468 }
a8ade55f 2469
8f256622 2470 if (match.mask->tos || match.mask->ttl)
d708f902 2471 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2472 }
2473
54782900
OG		 2474 /* *** L3 attributes parsing up to here *** */
2475
8f256622
PNA		 2476 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2477 struct flow_match_ports match;
2478
2479 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2480 switch (ip_proto) {
2481 case IPPROTO_TCP:
2482 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2483 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2484 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2485 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2486
2487 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2488 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2489 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2490 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2491 break;
2492
2493 case IPPROTO_UDP:
2494 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2495 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2496 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2497 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2498
2499 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2500 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2501 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2502 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2503 break;
2504 default:
e98bedf5
EB		 2505 NL_SET_ERR_MSG_MOD(extack,
2506 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2507 netdev_err(priv->netdev,
2508 "Only UDP and TCP transport are supported\n");
2509 return -EINVAL;
2510 }
de0af0bf 2511
8f256622 2512 if (match.mask->src || match.mask->dst)
d708f902 2513 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2514 }
2515
8f256622
PNA		 2516 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2517 struct flow_match_tcp match;
e77834ec 2518
8f256622 2519 flow_rule_match_tcp(rule, &match);
e77834ec 2520 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2521 ntohs(match.mask->flags));
e77834ec 2522 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2523 ntohs(match.key->flags));
e77834ec 2524
8f256622 2525 if (match.mask->flags)
d708f902 2526 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2527 }
2528
e3a2b7ed
AV		 2529 return 0;
2530}
2531
de0af0bf 2532static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2533 struct mlx5e_tc_flow *flow,
de0af0bf 2534 struct mlx5_flow_spec *spec,
f9e30088 2535 struct flow_cls_offload *f,
54c177ca 2536 struct net_device *filter_dev)
de0af0bf 2537{
93b3586e 2538 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2539 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2540 struct mlx5_core_dev *dev = priv->mdev;
2541 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2542 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2543 struct mlx5_eswitch_rep *rep;
226f2ca3 2544 bool is_eswitch_flow;
de0af0bf
RD		 2545 int err;
2546
93b3586e
HN		 2547 inner_match_level = MLX5_MATCH_NONE;
2548 outer_match_level = MLX5_MATCH_NONE;
2549
0a7fcb78
PB		 2550 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2551 &inner_match_level, &outer_match_level);
93b3586e
HN		 2552 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2553 outer_match_level : inner_match_level;
de0af0bf 2554
226f2ca3
VB		 2555 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2556 if (!err && is_eswitch_flow) {
1d447a39 2557 rep = rpriv->rep;
b05af6aa 2558 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2559 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2560 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2561 NL_SET_ERR_MSG_MOD(extack,
2562 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2563 netdev_warn(priv->netdev,
2564 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2565 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2566 return -EOPNOTSUPP;
2567 }
2568 }
2569
226f2ca3 2570 if (is_eswitch_flow) {
93b3586e
HN		 2571 flow->esw_attr->inner_match_level = inner_match_level;
2572 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2573 } else {
93b3586e 2574 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2575 }
38aa51c1 2576
de0af0bf
RD		 2577 return err;
2578}
2579
d79b6df6
OG		 2580struct pedit_headers {
2581 struct ethhdr eth;
0eb69bb9 2582 struct vlan_hdr vlan;
d79b6df6
OG		 2583 struct iphdr ip4;
2584 struct ipv6hdr ip6;
2585 struct tcphdr tcp;
2586 struct udphdr udp;
2587};
2588
c500c86b
PNA		 2589struct pedit_headers_action {
2590 struct pedit_headers vals;
2591 struct pedit_headers masks;
2592 u32 pedits;
2593};
2594
d79b6df6 2595static int pedit_header_offsets[] = {
73867881
PNA		 2596 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2597 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2598 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2599 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2600 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2601};
2602
2603#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2604
2605static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2606 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2607{
2608 u32 *curr_pmask, *curr_pval;
2609
c500c86b
PNA		 2610 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2611 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2612
2613 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2614 goto out_err;
2615
2616 *curr_pmask |= mask;
2617 *curr_pval |= (val & mask);
2618
2619 return 0;
2620
2621out_err:
2622 return -EOPNOTSUPP;
2623}
2624
2625struct mlx5_fields {
2626 u8 field;
88f30bbc
DL		 2627 u8 field_bsize;
2628 u32 field_mask;
d79b6df6 2629 u32 offset;
27c11b6b 2630 u32 match_offset;
d79b6df6
OG		 2631};
2632
88f30bbc
DL		 2633#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2634 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2635 offsetof(struct pedit_headers, field) + (off), \
2636 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2637
2ef86872
EB		 2638/* masked values are the same and there are no rewrites that do not have a
2639 * match.
2640 */
2641#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2642 type matchmaskx = *(type *)(matchmaskp); \
2643 type matchvalx = *(type *)(matchvalp); \
2644 type maskx = *(type *)(maskp); \
2645 type valx = *(type *)(valp); \
2646 \
2647 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2648 matchmaskx)); \
2649})
2650
27c11b6b 2651static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2652 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2653{
2654 bool same = false;
2655
88f30bbc
DL		 2656 switch (bsize) {
2657 case 8:
2ef86872 2658 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2659 break;
88f30bbc 2660 case 16:
2ef86872 2661 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2662 break;
88f30bbc 2663 case 32:
2ef86872 2664 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2665 break;
2666 }
2667
2668 return same;
2669}
a8e4f0c4 2670
d79b6df6 2671static struct mlx5_fields fields[] = {
88f30bbc
DL		 2672 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2673 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2674 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2675 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2676 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2677 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2678
ab9341b5 2679 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2680 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2681 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2682 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2683
2684 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2685 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2686 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2687 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2688 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2689 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2690 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2691 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2692 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2693 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2694 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2695 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2696 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2697 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2698 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2699 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2700 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
27c11b6b 2701
88f30bbc
DL		 2702 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2703 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2704 /* in linux iphdr tcp_flags is 8 bits long */
2705 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2706
88f30bbc
DL		 2707 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2708 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2709};
2710
6ae4a6a5
PB		 2711static int offload_pedit_fields(struct mlx5e_priv *priv,
2712 int namespace,
2713 struct pedit_headers_action *hdrs,
e98bedf5 2714 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2715 u32 *action_flags,
e98bedf5 2716 struct netlink_ext_ack *extack)
d79b6df6
OG		 2717{
2718 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2719 int i, action_size, first, last, next_z;
88f30bbc
DL		 2720 void *headers_c, *headers_v, *action, *vals_p;
2721 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2722 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2723 struct mlx5_fields *f;
d79b6df6 2724 unsigned long mask;
2b64beba
OG		 2725 __be32 mask_be32;
2726 __be16 mask_be16;
6ae4a6a5 2727 int err;
88f30bbc
DL		 2728 u8 cmd;
2729
6ae4a6a5 2730 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2731 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2732 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2733
73867881
PNA		 2734 set_masks = &hdrs[0].masks;
2735 add_masks = &hdrs[1].masks;
2736 set_vals = &hdrs[0].vals;
2737 add_vals = &hdrs[1].vals;
d79b6df6 2738
d65dbedf 2739 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2740
2741 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2742 bool skip;
2743
d79b6df6
OG		 2744 f = &fields[i];
2745 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2746 s_mask = 0;
2747 a_mask = 0;
d79b6df6
OG		 2748
2749 s_masks_p = (void *)set_masks + f->offset;
2750 a_masks_p = (void *)add_masks + f->offset;
2751
88f30bbc
DL		 2752 s_mask = *s_masks_p & f->field_mask;
2753 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2754
2755 if (!s_mask && !a_mask) /* nothing to offload here */
2756 continue;
2757
2758 if (s_mask && a_mask) {
e98bedf5
EB		 2759 NL_SET_ERR_MSG_MOD(extack,
2760 "can't set and add to the same HW field");
d79b6df6
OG		 2761 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2762 return -EOPNOTSUPP;
2763 }
2764
27c11b6b 2765 skip = false;
d79b6df6 2766 if (s_mask) {
27c11b6b
EB		 2767 void *match_mask = headers_c + f->match_offset;
2768 void *match_val = headers_v + f->match_offset;
2769
d79b6df6
OG		 2770 cmd = MLX5_ACTION_TYPE_SET;
2771 mask = s_mask;
2772 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2773 /* don't rewrite if we have a match on the same value */
2774 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2775 match_mask, f->field_bsize))
27c11b6b 2776 skip = true;
d79b6df6 2777 /* clear to denote we consumed this field */
88f30bbc 2778 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2779 } else {
2780 cmd = MLX5_ACTION_TYPE_ADD;
2781 mask = a_mask;
2782 vals_p = (void *)add_vals + f->offset;
27c11b6b 2783 /* add 0 is no change */
88f30bbc 2784 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2785 skip = true;
d79b6df6 2786 /* clear to denote we consumed this field */
88f30bbc 2787 *a_masks_p &= ~f->field_mask;
d79b6df6 2788 }
27c11b6b
EB		 2789 if (skip)
2790 continue;
d79b6df6 2791
88f30bbc 2792 if (f->field_bsize == 32) {
404402ab 2793 mask_be32 = (__be32)mask;
2b64beba 2794 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
88f30bbc 2795 } else if (f->field_bsize == 16) {
404402ab
SH		 2796 mask_be32 = (__be32)mask;
2797 mask_be16 = *(__be16 *)&mask_be32;
2b64beba
OG		 2798 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2799 }
2800
88f30bbc
DL		 2801 first = find_first_bit(&mask, f->field_bsize);
2802 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2803 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2804 if (first < next_z && next_z < last) {
e98bedf5
EB		 2805 NL_SET_ERR_MSG_MOD(extack,
2806 "rewrite of few sub-fields isn't supported");
2b64beba 2807 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2808 mask);
2809 return -EOPNOTSUPP;
2810 }
2811
6ae4a6a5
PB		 2812 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2813 if (err) {
2814 NL_SET_ERR_MSG_MOD(extack,
2815 "too many pedit actions, can't offload");
2816 mlx5_core_warn(priv->mdev,
2817 "mlx5: parsed %d pedit actions, can't do more\n",
2818 mod_acts->num_actions);
2819 return err;
2820 }
2821
2822 action = mod_acts->actions +
2823 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2824 MLX5_SET(set_action_in, action, action_type, cmd);
2825 MLX5_SET(set_action_in, action, field, f->field);
2826
2827 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2828 int start;
2829
2830 /* if field is bit sized it can start not from first bit */
2831 start = find_first_bit((unsigned long *)&f->field_mask,
2832 f->field_bsize);
2833
2834 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2835 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2836 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2837 }
2838
88f30bbc 2839 if (f->field_bsize == 32)
2b64beba 2840 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2841 else if (f->field_bsize == 16)
2b64beba 2842 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2843 else if (f->field_bsize == 8)
2b64beba 2844 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2845
6ae4a6a5 2846 ++mod_acts->num_actions;
d79b6df6
OG		 2847 }
2848
d79b6df6
OG		 2849 return 0;
2850}
2851
2cc1cb1d
TZ		 2852static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2853 int namespace)
2854{
2855 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2856 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2857 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2858 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2859}
2860
6ae4a6a5
PB		 2861int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2862 int namespace,
2863 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2864{
6ae4a6a5
PB		 2865 int action_size, new_num_actions, max_hw_actions;
2866 size_t new_sz, old_sz;
2867 void *ret;
d79b6df6 2868
6ae4a6a5
PB		 2869 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2870 return 0;
d79b6df6 2871
d65dbedf 2872 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2873
6ae4a6a5
PB		 2874 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2875 namespace);
2876 new_num_actions = min(max_hw_actions,
2877 mod_hdr_acts->actions ?
2878 mod_hdr_acts->max_actions * 2 : 1);
2879 if (mod_hdr_acts->max_actions == new_num_actions)
2880 return -ENOSPC;
2881
2882 new_sz = action_size * new_num_actions;
2883 old_sz = mod_hdr_acts->max_actions * action_size;
2884 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2885 if (!ret)
d79b6df6
OG		 2886 return -ENOMEM;
2887
6ae4a6a5
PB		 2888 memset(ret + old_sz, 0, new_sz - old_sz);
2889 mod_hdr_acts->actions = ret;
2890 mod_hdr_acts->max_actions = new_num_actions;
2891
d79b6df6
OG		 2892 return 0;
2893}
2894
6ae4a6a5
PB		 2895void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2896{
2897 kfree(mod_hdr_acts->actions);
2898 mod_hdr_acts->actions = NULL;
2899 mod_hdr_acts->num_actions = 0;
2900 mod_hdr_acts->max_actions = 0;
2901}
2902
d79b6df6
OG		 2903static const struct pedit_headers zero_masks = {};
2904
582234b4
EC		 2905static int
2906parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2907 const struct flow_action_entry *act, int namespace,
2908 struct mlx5e_tc_flow_parse_attr *parse_attr,
2909 struct pedit_headers_action *hdrs,
2910 struct netlink_ext_ack *extack)
d79b6df6 2911{
73867881
PNA		 2912 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2913 int err = -EOPNOTSUPP;
d79b6df6 2914 u32 mask, val, offset;
73867881 2915 u8 htype;
d79b6df6 2916
73867881
PNA		 2917 htype = act->mangle.htype;
2918 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2919
73867881
PNA		 2920 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2921 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2922 goto out_err;
2923 }
d79b6df6 2924
2cc1cb1d
TZ		 2925 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2926 NL_SET_ERR_MSG_MOD(extack,
2927 "The pedit offload action is not supported");
2928 goto out_err;
2929 }
2930
73867881
PNA		 2931 mask = act->mangle.mask;
2932 val = act->mangle.val;
2933 offset = act->mangle.offset;
d79b6df6 2934
73867881
PNA		 2935 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2936 if (err)
2937 goto out_err;
c500c86b 2938
73867881 2939 hdrs[cmd].pedits++;
d79b6df6 2940
c500c86b
PNA		 2941 return 0;
2942out_err:
2943 return err;
2944}
2945
582234b4
EC		 2946static int
2947parse_pedit_to_reformat(struct mlx5e_priv *priv,
2948 const struct flow_action_entry *act,
2949 struct mlx5e_tc_flow_parse_attr *parse_attr,
2950 struct netlink_ext_ack *extack)
2951{
2952 u32 mask, val, offset;
2953 u32 *p;
2954
2955 if (act->id != FLOW_ACTION_MANGLE)
2956 return -EOPNOTSUPP;
2957
2958 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2959 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2960 return -EOPNOTSUPP;
2961 }
2962
2963 mask = ~act->mangle.mask;
2964 val = act->mangle.val;
2965 offset = act->mangle.offset;
2966 p = (u32 *)&parse_attr->eth;
2967 *(p + (offset >> 2)) |= (val & mask);
2968
2969 return 0;
2970}
2971
2972static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2973 const struct flow_action_entry *act, int namespace,
2974 struct mlx5e_tc_flow_parse_attr *parse_attr,
2975 struct pedit_headers_action *hdrs,
2976 struct mlx5e_tc_flow *flow,
2977 struct netlink_ext_ack *extack)
2978{
2979 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2980 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2981
2982 return parse_pedit_to_modify_hdr(priv, act, namespace,
2983 parse_attr, hdrs, extack);
2984}
2985
c500c86b
PNA		 2986static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2987 struct mlx5e_tc_flow_parse_attr *parse_attr,
2988 struct pedit_headers_action *hdrs,
27c11b6b 2989 u32 *action_flags,
c500c86b
PNA		 2990 struct netlink_ext_ack *extack)
2991{
2992 struct pedit_headers *cmd_masks;
2993 int err;
2994 u8 cmd;
2995
6ae4a6a5
PB		 2996 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2997 action_flags, extack);
d79b6df6
OG		 2998 if (err < 0)
2999 goto out_dealloc_parsed_actions;
3000
3001 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 3002 cmd_masks = &hdrs[cmd].masks;
d79b6df6 3003 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 3004 NL_SET_ERR_MSG_MOD(extack,
3005 "attempt to offload an unsupported field");
b3a433de 3006 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3007 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3008 16, 1, cmd_masks, sizeof(zero_masks), true);
3009 err = -EOPNOTSUPP;
3010 goto out_dealloc_parsed_actions;
3011 }
3012 }
3013
3014 return 0;
3015
3016out_dealloc_parsed_actions:
6ae4a6a5 3017 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3018 return err;
3019}
3020
e98bedf5
EB		 3021static bool csum_offload_supported(struct mlx5e_priv *priv,
3022 u32 action,
3023 u32 update_flags,
3024 struct netlink_ext_ack *extack)
26c02749
OG		 3025{
3026 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3027 TCA_CSUM_UPDATE_FLAG_UDP;
3028
3029 /* The HW recalcs checksums only if re-writing headers */
3030 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3031 NL_SET_ERR_MSG_MOD(extack,
3032 "TC csum action is only offloaded with pedit");
26c02749
OG		 3033 netdev_warn(priv->netdev,
3034 "TC csum action is only offloaded with pedit\n");
3035 return false;
3036 }
3037
3038 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3039 NL_SET_ERR_MSG_MOD(extack,
3040 "can't offload TC csum action for some header/s");
26c02749
OG		 3041 netdev_warn(priv->netdev,
3042 "can't offload TC csum action for some header/s - flags %#x\n",
3043 update_flags);
3044 return false;
3045 }
3046
3047 return true;
3048}
3049
8998576b
DL		 3050struct ip_ttl_word {
3051 __u8 ttl;
3052 __u8 protocol;
3053 __sum16 check;
3054};
3055
3056struct ipv6_hoplimit_word {
3057 __be16 payload_len;
3058 __u8 nexthdr;
3059 __u8 hop_limit;
3060};
3061
4c3844d9
PB		 3062static int is_action_keys_supported(const struct flow_action_entry *act,
3063 bool ct_flow, bool *modify_ip_header,
3064 struct netlink_ext_ack *extack)
8998576b
DL		 3065{
3066 u32 mask, offset;
3067 u8 htype;
3068
3069 htype = act->mangle.htype;
3070 offset = act->mangle.offset;
3071 mask = ~act->mangle.mask;
3072 /* For IPv4 & IPv6 header check 4 byte word,
3073 * to determine that modified fields
3074 * are NOT ttl & hop_limit only.
3075 */
3076 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3077 struct ip_ttl_word *ttl_word =
3078 (struct ip_ttl_word *)&mask;
3079
3080 if (offset != offsetof(struct iphdr, ttl) ||
3081 ttl_word->protocol ||
3082 ttl_word->check) {
4c3844d9
PB		 3083 *modify_ip_header = true;
3084 }
3085
3086 if (ct_flow && offset >= offsetof(struct iphdr, saddr)) {
3087 NL_SET_ERR_MSG_MOD(extack,
3088 "can't offload re-write of ipv4 address with action ct");
3089 return -EOPNOTSUPP;
8998576b
DL		 3090 }
3091 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3092 struct ipv6_hoplimit_word *hoplimit_word =
3093 (struct ipv6_hoplimit_word *)&mask;
3094
3095 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3096 hoplimit_word->payload_len ||
3097 hoplimit_word->nexthdr) {
4c3844d9
PB		 3098 *modify_ip_header = true;
3099 }
3100
3101 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr)) {
3102 NL_SET_ERR_MSG_MOD(extack,
3103 "can't offload re-write of ipv6 address with action ct");
3104 return -EOPNOTSUPP;
8998576b 3105 }
4c3844d9
PB		 3106 } else if (ct_flow && (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3107 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP)) {
3108 NL_SET_ERR_MSG_MOD(extack,
3109 "can't offload re-write of transport header ports with action ct");
3110 return -EOPNOTSUPP;
8998576b 3111 }
4c3844d9
PB		 3112
3113 return 0;
8998576b
DL		 3114}
3115
bdd66ac0 3116static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 3117 struct flow_action *flow_action,
4c3844d9 3118 u32 actions, bool ct_flow,
e98bedf5 3119 struct netlink_ext_ack *extack)
bdd66ac0 3120{
73867881 3121 const struct flow_action_entry *act;
bdd66ac0 3122 bool modify_ip_header;
bdd66ac0
OG		 3123 void *headers_v;
3124 u16 ethertype;
8998576b 3125 u8 ip_proto;
4c3844d9 3126 int i, err;
bdd66ac0 3127
8377629e 3128 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3129 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3130
3131 /* for non-IP we only re-write MACs, so we're okay */
3132 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3133 goto out_ok;
3134
3135 modify_ip_header = false;
73867881
PNA		 3136 flow_action_for_each(i, act, flow_action) {
3137 if (act->id != FLOW_ACTION_MANGLE &&
3138 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3139 continue;
3140
4c3844d9
PB		 3141 err = is_action_keys_supported(act, ct_flow,
3142 &modify_ip_header, extack);
3143 if (err)
3144 return err;
bdd66ac0
OG		 3145 }
3146
3147 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3148 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3149 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3150 NL_SET_ERR_MSG_MOD(extack,
3151 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 3152 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
3153 return false;
3154 }
3155
3156out_ok:
3157 return true;
3158}
3159
3160static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3161 struct flow_action *flow_action,
bdd66ac0 3162 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3163 struct mlx5e_tc_flow *flow,
3164 struct netlink_ext_ack *extack)
bdd66ac0 3165{
d0645b37 3166 bool ct_flow;
bdd66ac0
OG		 3167 u32 actions;
3168
4c3844d9
PB		 3169 ct_flow = flow_flag_test(flow, CT);
3170 if (mlx5e_is_eswitch_flow(flow)) {
bdd66ac0 3171 actions = flow->esw_attr->action;
4c3844d9
PB		 3172
3173 if (flow->esw_attr->split_count && ct_flow) {
3174 /* All registers used by ct are cleared when using
3175 * split rules.
3176 */
3177 NL_SET_ERR_MSG_MOD(extack,
3178 "Can't offload mirroring with action ct");
49397b80 3179 return false;
4c3844d9
PB		 3180 }
3181 } else {
bdd66ac0 3182 actions = flow->nic_attr->action;
4c3844d9 3183 }
bdd66ac0
OG		 3184
3185 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 3186 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 3187 flow_action, actions,
4c3844d9 3188 ct_flow, extack);
bdd66ac0
OG		 3189
3190 return true;
3191}
3192
32134847
MD		 3193static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3194{
3195 return priv->mdev == peer_priv->mdev;
3196}
3197
5c65c564
OG		 3198static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3199{
3200 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3201 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3202
3203 fmdev = priv->mdev;
3204 pmdev = peer_priv->mdev;
3205
59c9d35e
AH		 3206 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3207 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3208
816f6706 3209 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3210}
3211
bdc837ee
EB		 3212static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3213 const struct flow_action_entry *act,
3214 struct mlx5e_tc_flow_parse_attr *parse_attr,
3215 struct pedit_headers_action *hdrs,
3216 u32 *action, struct netlink_ext_ack *extack)
3217{
3218 u16 mask16 = VLAN_VID_MASK;
3219 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3220 const struct flow_action_entry pedit_act = {
3221 .id = FLOW_ACTION_MANGLE,
3222 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3223 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3224 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3225 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3226 };
6fca9d1e 3227 u8 match_prio_mask, match_prio_val;
bf2f3bca 3228 void *headers_c, *headers_v;
bdc837ee
EB		 3229 int err;
3230
bf2f3bca
EB		 3231 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3232 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3233
3234 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3235 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3236 NL_SET_ERR_MSG_MOD(extack,
3237 "VLAN rewrite action must have VLAN protocol match");
3238 return -EOPNOTSUPP;
3239 }
3240
6fca9d1e
EB		 3241 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3242 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3243 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3244 NL_SET_ERR_MSG_MOD(extack,
3245 "Changing VLAN prio is not supported");
bdc837ee
EB		 3246 return -EOPNOTSUPP;
3247 }
3248
582234b4 3249 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3250 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3251
3252 return err;
3253}
3254
0bac1194
EB		 3255static int
3256add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3257 struct mlx5e_tc_flow_parse_attr *parse_attr,
3258 struct pedit_headers_action *hdrs,
3259 u32 *action, struct netlink_ext_ack *extack)
3260{
3261 const struct flow_action_entry prio_tag_act = {
3262 .vlan.vid = 0,
3263 .vlan.prio =
3264 MLX5_GET(fte_match_set_lyr_2_4,
3265 get_match_headers_value(*action,
3266 &parse_attr->spec),
3267 first_prio) &
3268 MLX5_GET(fte_match_set_lyr_2_4,
3269 get_match_headers_criteria(*action,
3270 &parse_attr->spec),
3271 first_prio),
3272 };
3273
3274 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3275 &prio_tag_act, parse_attr, hdrs, action,
3276 extack);
3277}
3278
73867881
PNA		 3279static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3280 struct flow_action *flow_action,
aa0cbbae 3281 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3282 struct mlx5e_tc_flow *flow,
3283 struct netlink_ext_ack *extack)
e3a2b7ed 3284{
aa0cbbae 3285 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 3286 struct pedit_headers_action hdrs[2] = {};
3287 const struct flow_action_entry *act;
1cab1cd7 3288 u32 action = 0;
244cd96a 3289 int err, i;
e3a2b7ed 3290
73867881 3291 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3292 return -EINVAL;
3293
53eca1f3
JK		 3294 if (!flow_action_hw_stats_check(flow_action, extack,
3295 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3296 return -EOPNOTSUPP;
3297
3bc4b7bf 3298 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3299
73867881
PNA		 3300 flow_action_for_each(i, act, flow_action) {
3301 switch (act->id) {
15fc92ec
TZ		 3302 case FLOW_ACTION_ACCEPT:
3303 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3304 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3305 break;
73867881 3306 case FLOW_ACTION_DROP:
1cab1cd7 3307 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3308 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3309 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3310 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3311 break;
3312 case FLOW_ACTION_MANGLE:
3313 case FLOW_ACTION_ADD:
3314 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3315 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3316 if (err)
3317 return err;
3318
1cab1cd7
OG		 3319 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
3320 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 3321 break;
bdc837ee
EB		 3322 case FLOW_ACTION_VLAN_MANGLE:
3323 err = add_vlan_rewrite_action(priv,
3324 MLX5_FLOW_NAMESPACE_KERNEL,
3325 act, parse_attr, hdrs,
3326 &action, extack);
3327 if (err)
3328 return err;
3329
3330 break;
73867881 3331 case FLOW_ACTION_CSUM:
1cab1cd7 3332 if (csum_offload_supported(priv, action,
73867881 3333 act->csum_flags,
e98bedf5 3334 extack))
73867881 3335 break;
26c02749
OG		 3336
3337 return -EOPNOTSUPP;
73867881
PNA		 3338 case FLOW_ACTION_REDIRECT: {
3339 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3340
3341 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3342 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3343 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3344 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3345 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3346 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3347 } else {
e98bedf5
EB		 3348 NL_SET_ERR_MSG_MOD(extack,
3349 "device is not on same HW, can't offload");
5c65c564
OG		 3350 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3351 peer_dev->name);
3352 return -EINVAL;
3353 }
73867881
PNA		 3354 }
3355 break;
3356 case FLOW_ACTION_MARK: {
3357 u32 mark = act->mark;
e3a2b7ed
AV		 3358
3359 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3360 NL_SET_ERR_MSG_MOD(extack,
3361 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3362 return -EINVAL;
3363 }
3364
3bc4b7bf 3365 attr->flow_tag = mark;
1cab1cd7 3366 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3367 }
3368 break;
3369 default:
2cc1cb1d
TZ		 3370 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3371 return -EOPNOTSUPP;
e3a2b7ed 3372 }
e3a2b7ed
AV		 3373 }
3374
c500c86b
PNA		 3375 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3376 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3377 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3378 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3379 if (err)
3380 return err;
27c11b6b
EB		 3381 /* in case all pedit actions are skipped, remove the MOD_HDR
3382 * flag.
3383 */
6ae4a6a5 3384 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3385 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3386 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3387 }
c500c86b
PNA		 3388 }
3389
1cab1cd7 3390 attr->action = action;
73867881 3391 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3392 return -EOPNOTSUPP;
3393
e3a2b7ed
AV		 3394 return 0;
3395}
3396
7f1a546e 3397struct encap_key {
1f6da306 3398 const struct ip_tunnel_key *ip_tun_key;
d386939a 3399 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3400};
3401
3402static inline int cmp_encap_info(struct encap_key *a,
3403 struct encap_key *b)
a54e20b4 3404{
7f1a546e 3405 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3406 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3407}
3408
14e6b038
EC		 3409static inline int cmp_decap_info(struct mlx5e_decap_key *a,
3410 struct mlx5e_decap_key *b)
3411{
3412 return memcmp(&a->key, &b->key, sizeof(b->key));
3413}
3414
7f1a546e 3415static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3416{
7f1a546e 3417 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3418 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3419}
3420
14e6b038
EC		 3421static inline int hash_decap_info(struct mlx5e_decap_key *key)
3422{
3423 return jhash(&key->key, sizeof(key->key), 0);
3424}
a54e20b4 3425
32134847 3426static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3427 struct net_device *peer_netdev)
3428{
3429 struct mlx5e_priv *peer_priv;
3430
3431 peer_priv = netdev_priv(peer_netdev);
3432
3433 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3434 mlx5e_eswitch_vf_rep(priv->netdev) &&
3435 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3436 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3437}
3438
948993f2
VB		 3439bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3440{
3441 return refcount_inc_not_zero(&e->refcnt);
3442}
3443
14e6b038
EC		 3444static bool mlx5e_decap_take(struct mlx5e_decap_entry *e)
3445{
3446 return refcount_inc_not_zero(&e->refcnt);
3447}
3448
948993f2
VB		 3449static struct mlx5e_encap_entry *
3450mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3451 uintptr_t hash_key)
3452{
3453 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3454 struct mlx5e_encap_entry *e;
3455 struct encap_key e_key;
3456
3457 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3458 encap_hlist, hash_key) {
3459 e_key.ip_tun_key = &e->tun_info->key;
3460 e_key.tc_tunnel = e->tunnel;
3461 if (!cmp_encap_info(&e_key, key) &&
3462 mlx5e_encap_take(e))
3463 return e;
3464 }
3465
3466 return NULL;
3467}
3468
14e6b038
EC		 3469static struct mlx5e_decap_entry *
3470mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key,
3471 uintptr_t hash_key)
3472{
3473 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3474 struct mlx5e_decap_key r_key;
3475 struct mlx5e_decap_entry *e;
3476
3477 hash_for_each_possible_rcu(esw->offloads.decap_tbl, e,
3478 hlist, hash_key) {
3479 r_key = e->key;
3480 if (!cmp_decap_info(&r_key, key) &&
3481 mlx5e_decap_take(e))
3482 return e;
3483 }
3484 return NULL;
3485}
3486
2a4b6526
VB		 3487static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3488{
3489 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3490
3491 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3492}
3493
554fe75c
DL		 3494static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3495 struct mlx5e_tc_flow *flow,
3496 int out_index,
3497 struct mlx5e_encap_entry *e,
3498 struct netlink_ext_ack *extack)
3499{
3500 int i;
3501
3502 for (i = 0; i < out_index; i++) {
3503 if (flow->encaps[i].e != e)
3504 continue;
3505 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3506 netdev_err(priv->netdev, "can't duplicate encap action\n");
3507 return true;
3508 }
3509
3510 return false;
3511}
3512
a54e20b4 3513static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3514 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3515 struct net_device *mirred_dev,
3516 int out_index,
8c4dc42b 3517 struct netlink_ext_ack *extack,
0ad060ee
RD		 3518 struct net_device **encap_dev,
3519 bool *encap_valid)
a54e20b4
HHZ		 3520{
3521 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3522 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3523 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3524 const struct ip_tunnel_info *tun_info;
948993f2 3525 struct encap_key key;
c1ae1152 3526 struct mlx5e_encap_entry *e;
733d4f36 3527 unsigned short family;
a54e20b4 3528 uintptr_t hash_key;
54c177ca 3529 int err = 0;
a54e20b4 3530
733d4f36 3531 parse_attr = attr->parse_attr;
1f6da306 3532 tun_info = parse_attr->tun_info[out_index];
733d4f36 3533 family = ip_tunnel_info_af(tun_info);
7f1a546e 3534 key.ip_tun_key = &tun_info->key;
d386939a 3535 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3536 if (!key.tc_tunnel) {
3537 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3538 return -EOPNOTSUPP;
3539 }
733d4f36 3540
7f1a546e 3541 hash_key = hash_encap_info(&key);
a54e20b4 3542
61086f39 3543 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3544 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3545
b2812089 3546 /* must verify if encap is valid or not */
d589e785 3547 if (e) {
554fe75c
DL		 3548 /* Check that entry was not already attached to this flow */
3549 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3550 err = -EOPNOTSUPP;
3551 goto out_err;
3552 }
3553
d589e785
VB		 3554 mutex_unlock(&esw->offloads.encap_tbl_lock);
3555 wait_for_completion(&e->res_ready);
3556
3557 /* Protect against concurrent neigh update. */
3558 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3559 if (e->compl_result < 0) {
d589e785
VB		 3560 err = -EREMOTEIO;
3561 goto out_err;
3562 }
45247bf2 3563 goto attach_flow;
d589e785 3564 }
a54e20b4
HHZ		 3565
3566 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3567 if (!e) {
3568 err = -ENOMEM;
3569 goto out_err;
3570 }
a54e20b4 3571
948993f2 3572 refcount_set(&e->refcnt, 1);
d589e785
VB		 3573 init_completion(&e->res_ready);
3574
2a4b6526
VB		 3575 tun_info = dup_tun_info(tun_info);
3576 if (!tun_info) {
3577 err = -ENOMEM;
3578 goto out_err_init;
3579 }
1f6da306 3580 e->tun_info = tun_info;
101f4de9 3581 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3582 if (err)
3583 goto out_err_init;
54c177ca 3584
a54e20b4 3585 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3586 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3587 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3588
ce99f6b9 3589 if (family == AF_INET)
101f4de9 3590 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3591 else if (family == AF_INET6)
101f4de9 3592 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3593
d589e785
VB		 3594 /* Protect against concurrent neigh update. */
3595 mutex_lock(&esw->offloads.encap_tbl_lock);
3596 complete_all(&e->res_ready);
3597 if (err) {
3598 e->compl_result = err;
a54e20b4 3599 goto out_err;
d589e785 3600 }
3c140dd5 3601 e->compl_result = 1;
a54e20b4 3602
45247bf2 3603attach_flow:
948993f2 3604 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3605 list_add(&flow->encaps[out_index].list, &e->flows);
3606 flow->encaps[out_index].index = out_index;
45247bf2 3607 *encap_dev = e->out_dev;
8c4dc42b 3608 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3609 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3610 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3611 *encap_valid = true;
8c4dc42b 3612 } else {
0ad060ee 3613 *encap_valid = false;
8c4dc42b 3614 }
61086f39 3615 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3616
232c0013 3617 return err;
a54e20b4
HHZ		 3618
3619out_err:
61086f39 3620 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3621 if (e)
3622 mlx5e_encap_put(priv, e);
a54e20b4 3623 return err;
2a4b6526
VB		 3624
3625out_err_init:
3626 mutex_unlock(&esw->offloads.encap_tbl_lock);
3627 kfree(tun_info);
3628 kfree(e);
3629 return err;
a54e20b4
HHZ		 3630}
3631
14e6b038
EC		 3632static int mlx5e_attach_decap(struct mlx5e_priv *priv,
3633 struct mlx5e_tc_flow *flow,
3634 struct netlink_ext_ack *extack)
3635{
3636 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3637 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3638 struct mlx5e_tc_flow_parse_attr *parse_attr;
3639 struct mlx5e_decap_entry *d;
3640 struct mlx5e_decap_key key;
3641 uintptr_t hash_key;
3642 int err;
3643
3644 parse_attr = attr->parse_attr;
3645 if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {
3646 NL_SET_ERR_MSG_MOD(extack,
3647 "encap header larger than max supported");
3648 return -EOPNOTSUPP;
3649 }
3650
3651 key.key = parse_attr->eth;
3652 hash_key = hash_decap_info(&key);
3653 mutex_lock(&esw->offloads.decap_tbl_lock);
3654 d = mlx5e_decap_get(priv, &key, hash_key);
3655 if (d) {
3656 mutex_unlock(&esw->offloads.decap_tbl_lock);
3657 wait_for_completion(&d->res_ready);
3658 mutex_lock(&esw->offloads.decap_tbl_lock);
3659 if (d->compl_result) {
3660 err = -EREMOTEIO;
3661 goto out_free;
3662 }
3663 goto found;
3664 }
3665
3666 d = kzalloc(sizeof(*d), GFP_KERNEL);
3667 if (!d) {
3668 err = -ENOMEM;
3669 goto out_err;
3670 }
3671
3672 d->key = key;
3673 refcount_set(&d->refcnt, 1);
3674 init_completion(&d->res_ready);
3675 INIT_LIST_HEAD(&d->flows);
3676 hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key);
3677 mutex_unlock(&esw->offloads.decap_tbl_lock);
3678
3679 d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
3680 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2,
3681 sizeof(parse_attr->eth),
3682 &parse_attr->eth,
3683 MLX5_FLOW_NAMESPACE_FDB);
3684 if (IS_ERR(d->pkt_reformat)) {
3685 err = PTR_ERR(d->pkt_reformat);
3686 d->compl_result = err;
3687 }
3688 mutex_lock(&esw->offloads.decap_tbl_lock);
3689 complete_all(&d->res_ready);
3690 if (err)
3691 goto out_free;
3692
3693found:
3694 flow->decap_reformat = d;
3695 attr->decap_pkt_reformat = d->pkt_reformat;
3696 list_add(&flow->l3_to_l2_reformat, &d->flows);
3697 mutex_unlock(&esw->offloads.decap_tbl_lock);
3698 return 0;
3699
3700out_free:
3701 mutex_unlock(&esw->offloads.decap_tbl_lock);
3702 mlx5e_decap_put(priv, d);
3703 return err;
3704
3705out_err:
3706 mutex_unlock(&esw->offloads.decap_tbl_lock);
3707 return err;
3708}
3709
1482bd3d 3710static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3711 const struct flow_action_entry *act,
1482bd3d
JL		 3712 struct mlx5_esw_flow_attr *attr,
3713 u32 *action)
3714{
cc495188
JL		 3715 u8 vlan_idx = attr->total_vlan;
3716
3717 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3718 return -EOPNOTSUPP;
3719
73867881
PNA		 3720 switch (act->id) {
3721 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3722 if (vlan_idx) {
3723 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3724 MLX5_FS_VLAN_DEPTH))
3725 return -EOPNOTSUPP;
3726
3727 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3728 } else {
3729 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3730 }
73867881
PNA		 3731 break;
3732 case FLOW_ACTION_VLAN_PUSH:
3733 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3734 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3735 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3736 if (!attr->vlan_proto[vlan_idx])
3737 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3738
3739 if (vlan_idx) {
3740 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3741 MLX5_FS_VLAN_DEPTH))
3742 return -EOPNOTSUPP;
3743
3744 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3745 } else {
3746 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3747 (act->vlan.proto != htons(ETH_P_8021Q) ||
3748 act->vlan.prio))
cc495188
JL		 3749 return -EOPNOTSUPP;
3750
3751 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3752 }
73867881
PNA		 3753 break;
3754 default:
bdc837ee 3755 return -EINVAL;
1482bd3d
JL		 3756 }
3757
cc495188
JL		 3758 attr->total_vlan = vlan_idx + 1;
3759
1482bd3d
JL		 3760 return 0;
3761}
3762
d34eb2fc
OG		 3763static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3764 struct net_device *out_dev)
3765{
3766 struct net_device *fdb_out_dev = out_dev;
3767 struct net_device *uplink_upper;
3768
3769 rcu_read_lock();
3770 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3771 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3772 uplink_upper == out_dev) {
3773 fdb_out_dev = uplink_dev;
3774 } else if (netif_is_lag_master(out_dev)) {
3775 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3776 if (fdb_out_dev &&
3777 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3778 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3779 fdb_out_dev = NULL;
3780 }
3781 rcu_read_unlock();
3782 return fdb_out_dev;
3783}
3784
278748a9
EB		 3785static int add_vlan_push_action(struct mlx5e_priv *priv,
3786 struct mlx5_esw_flow_attr *attr,
3787 struct net_device **out_dev,
3788 u32 *action)
3789{
3790 struct net_device *vlan_dev = *out_dev;
3791 struct flow_action_entry vlan_act = {
3792 .id = FLOW_ACTION_VLAN_PUSH,
3793 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3794 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3795 .vlan.prio = 0,
3796 };
3797 int err;
3798
3799 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3800 if (err)
3801 return err;
3802
3803 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3804 dev_get_iflink(vlan_dev));
3805 if (is_vlan_dev(*out_dev))
3806 err = add_vlan_push_action(priv, attr, out_dev, action);
3807
3808 return err;
3809}
3810
35a605db
EB		 3811static int add_vlan_pop_action(struct mlx5e_priv *priv,
3812 struct mlx5_esw_flow_attr *attr,
3813 u32 *action)
3814{
35a605db
EB		 3815 struct flow_action_entry vlan_act = {
3816 .id = FLOW_ACTION_VLAN_POP,
3817 };
70f478ca 3818 int nest_level, err = 0;
35a605db 3819
70f478ca
DL		 3820 nest_level = attr->parse_attr->filter_dev->lower_level -
3821 priv->netdev->lower_level;
35a605db
EB		 3822 while (nest_level--) {
3823 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3824 if (err)
3825 return err;
3826 }
3827
3828 return err;
3829}
3830
32134847
MD		 3831static bool same_hw_reps(struct mlx5e_priv *priv,
3832 struct net_device *peer_netdev)
3833{
3834 struct mlx5e_priv *peer_priv;
3835
3836 peer_priv = netdev_priv(peer_netdev);
3837
3838 return mlx5e_eswitch_rep(priv->netdev) &&
3839 mlx5e_eswitch_rep(peer_netdev) &&
3840 same_hw_devs(priv, peer_priv);
3841}
3842
3843static bool is_lag_dev(struct mlx5e_priv *priv,
3844 struct net_device *peer_netdev)
3845{
3846 return ((mlx5_lag_is_sriov(priv->mdev) ||
3847 mlx5_lag_is_multipath(priv->mdev)) &&
3848 same_hw_reps(priv, peer_netdev));
3849}
3850
f6dc1264
PB		 3851bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3852 struct net_device *out_dev)
3853{
32134847
MD		 3854 if (is_merged_eswitch_vfs(priv, out_dev))
3855 return true;
3856
3857 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3858 return true;
3859
3860 return mlx5e_eswitch_rep(out_dev) &&
32134847 3861 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3862}
3863
554fe75c
DL		 3864static bool is_duplicated_output_device(struct net_device *dev,
3865 struct net_device *out_dev,
3866 int *ifindexes, int if_count,
3867 struct netlink_ext_ack *extack)
3868{
3869 int i;
3870
3871 for (i = 0; i < if_count; i++) {
3872 if (ifindexes[i] == out_dev->ifindex) {
3873 NL_SET_ERR_MSG_MOD(extack,
3874 "can't duplicate output to same device");
3875 netdev_err(dev, "can't duplicate output to same device: %s\n",
3876 out_dev->name);
3877 return true;
3878 }
3879 }
3880
3881 return false;
3882}
3883
2fbbc30d
EC		 3884static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3885 struct mlx5e_tc_flow *flow,
3886 const struct flow_action_entry *act,
3887 u32 actions,
3888 struct netlink_ext_ack *extack)
3889{
3890 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3891 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3892 bool ft_flow = mlx5e_is_ft_flow(flow);
3893 u32 dest_chain = act->chain_index;
3894
3895 if (ft_flow) {
3896 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3897 return -EOPNOTSUPP;
3898 }
3899
3900 if (!mlx5_esw_chains_backwards_supported(esw) &&
3901 dest_chain <= attr->chain) {
3902 NL_SET_ERR_MSG_MOD(extack,
3903 "Goto lower numbered chain isn't supported");
3904 return -EOPNOTSUPP;
3905 }
3906 if (dest_chain > max_chain) {
3907 NL_SET_ERR_MSG_MOD(extack,
3908 "Requested destination chain is out of supported range");
3909 return -EOPNOTSUPP;
3910 }
3911
3912 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3913 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3914 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3915 NL_SET_ERR_MSG_MOD(extack,
3916 "Goto chain is not allowed if action has reformat or decap");
3917 return -EOPNOTSUPP;
3918 }
3919
3920 return 0;
3921}
3922
613f53fe
EC		 3923static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3924 struct mlx5e_tc_flow *flow,
3925 struct net_device *out_dev,
3926 struct netlink_ext_ack *extack)
3927{
3928 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3929 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3930 struct mlx5e_rep_priv *rep_priv;
3931
3932 /* Forwarding non encapsulated traffic between
3933 * uplink ports is allowed only if
3934 * termination_table_raw_traffic cap is set.
3935 *
3936 * Input vport was stored esw_attr->in_rep.
3937 * In LAG case, *priv* is the private data of
3938 * uplink which may be not the input vport.
3939 */
3940 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3941
3942 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3943 mlx5e_eswitch_uplink_rep(out_dev)))
3944 return 0;
3945
3946 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3947 termination_table_raw_traffic)) {
3948 NL_SET_ERR_MSG_MOD(extack,
3949 "devices are both uplink, can't offload forwarding");
3950 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3951 priv->netdev->name, out_dev->name);
3952 return -EOPNOTSUPP;
3953 } else if (out_dev != rep_priv->netdev) {
3954 NL_SET_ERR_MSG_MOD(extack,
3955 "devices are not the same uplink, can't offload forwarding");
3956 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3957 priv->netdev->name, out_dev->name);
3958 return -EOPNOTSUPP;
3959 }
3960 return 0;
3961}
3962
73867881
PNA		 3963static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3964 struct flow_action *flow_action,
e98bedf5 3965 struct mlx5e_tc_flow *flow,
14e6b038
EC		 3966 struct netlink_ext_ack *extack,
3967 struct net_device *filter_dev)
03a9d11e 3968{
73867881 3969 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3970 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3971 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3972 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3973 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3974 const struct ip_tunnel_info *info = NULL;
554fe75c 3975 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3976 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3977 const struct flow_action_entry *act;
0a7fcb78
PB		 3978 bool encap = false, decap = false;
3979 u32 action = attr->action;
554fe75c 3980 int err, i, if_count = 0;
f828ca6a 3981 bool mpls_push = false;
03a9d11e 3982
73867881 3983 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3984 return -EINVAL;
3985
53eca1f3
JK		 3986 if (!flow_action_hw_stats_check(flow_action, extack,
3987 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3988 return -EOPNOTSUPP;
3989
73867881
PNA		 3990 flow_action_for_each(i, act, flow_action) {
3991 switch (act->id) {
3992 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3993 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3994 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3995 break;
f828ca6a
EC		 3996 case FLOW_ACTION_MPLS_PUSH:
3997 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3998 reformat_l2_to_l3_tunnel) ||
3999 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
4000 NL_SET_ERR_MSG_MOD(extack,
4001 "mpls push is supported only for mpls_uc protocol");
4002 return -EOPNOTSUPP;
4003 }
4004 mpls_push = true;
4005 break;
14e6b038
EC		 4006 case FLOW_ACTION_MPLS_POP:
4007 /* we only support mpls pop if it is the first action
4008 * and the filter net device is bareudp. Subsequent
4009 * actions can be pedit and the last can be mirred
4010 * egress redirect.
4011 */
4012 if (i) {
4013 NL_SET_ERR_MSG_MOD(extack,
4014 "mpls pop supported only as first action");
4015 return -EOPNOTSUPP;
4016 }
4017 if (!netif_is_bareudp(filter_dev)) {
4018 NL_SET_ERR_MSG_MOD(extack,
4019 "mpls pop supported only on bareudp devices");
4020 return -EOPNOTSUPP;
4021 }
4022
4023 parse_attr->eth.h_proto = act->mpls_pop.proto;
4024 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
4025 flow_flag_set(flow, L3_TO_L2_DECAP);
4026 break;
73867881
PNA		 4027 case FLOW_ACTION_MANGLE:
4028 case FLOW_ACTION_ADD:
4029 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 4030 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 4031 if (err)
4032 return err;
4033
582234b4
EC		 4034 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
4035 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4036 attr->split_count = attr->out_count;
4037 }
73867881
PNA		 4038 break;
4039 case FLOW_ACTION_CSUM:
1cab1cd7 4040 if (csum_offload_supported(priv, action,
73867881
PNA		 4041 act->csum_flags, extack))
4042 break;
26c02749
OG		 4043
4044 return -EOPNOTSUPP;
73867881
PNA		 4045 case FLOW_ACTION_REDIRECT:
4046 case FLOW_ACTION_MIRRED: {
03a9d11e 4047 struct mlx5e_priv *out_priv;
592d3651 4048 struct net_device *out_dev;
03a9d11e 4049
73867881 4050 out_dev = act->dev;
ef381359
OS		 4051 if (!out_dev) {
4052 /* out_dev is NULL when filters with
4053 * non-existing mirred device are replayed to
4054 * the driver.
4055 */
4056 return -EINVAL;
4057 }
03a9d11e 4058
f828ca6a
EC		 4059 if (mpls_push && !netif_is_bareudp(out_dev)) {
4060 NL_SET_ERR_MSG_MOD(extack,
4061 "mpls is supported only through a bareudp device");
4062 return -EOPNOTSUPP;
4063 }
4064
84179981
PB		 4065 if (ft_flow && out_dev == priv->netdev) {
4066 /* Ignore forward to self rules generated
4067 * by adding both mlx5 devs to the flow table
4068 * block on a normal nft offload setup.
4069 */
4070 return -EOPNOTSUPP;
4071 }
4072
592d3651 4073 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 4074 NL_SET_ERR_MSG_MOD(extack,
4075 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 4076 netdev_warn(priv->netdev,
4077 "can't support more than %d output ports, can't offload forwarding\n",
4078 attr->out_count);
592d3651
CM		 4079 return -EOPNOTSUPP;
4080 }
4081
f493f155
EB		 4082 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4083 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 4084 if (encap) {
4085 parse_attr->mirred_ifindex[attr->out_count] =
4086 out_dev->ifindex;
4087 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
4088 if (!parse_attr->tun_info[attr->out_count])
4089 return -ENOMEM;
4090 encap = false;
4091 attr->dests[attr->out_count].flags |=
4092 MLX5_ESW_DEST_ENCAP;
4093 attr->out_count++;
4094 /* attr->dests[].rep is resolved when we
4095 * handle encap
4096 */
4097 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 4098 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4099 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 4100
554fe75c
DL		 4101 if (is_duplicated_output_device(priv->netdev,
4102 out_dev,
4103 ifindexes,
4104 if_count,
4105 extack))
4106 return -EOPNOTSUPP;
4107
4108 ifindexes[if_count] = out_dev->ifindex;
4109 if_count++;
4110
d34eb2fc
OG		 4111 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4112 if (!out_dev)
4113 return -ENODEV;
7ba58ba7 4114
278748a9
EB		 4115 if (is_vlan_dev(out_dev)) {
4116 err = add_vlan_push_action(priv, attr,
4117 &out_dev,
4118 &action);
4119 if (err)
4120 return err;
4121 }
f6dc1264 4122
35a605db
EB		 4123 if (is_vlan_dev(parse_attr->filter_dev)) {
4124 err = add_vlan_pop_action(priv, attr,
4125 &action);
4126 if (err)
4127 return err;
4128 }
278748a9 4129
613f53fe
EC		 4130 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4131 if (err)
4132 return err;
ffec9702 4133
f6dc1264
PB		 4134 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4135 NL_SET_ERR_MSG_MOD(extack,
4136 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4137 netdev_warn(priv->netdev,
4138 "devices %s %s not on same switch HW, can't offload forwarding\n",
4139 priv->netdev->name,
4140 out_dev->name);
a0646c88 4141 return -EOPNOTSUPP;
f6dc1264 4142 }
a0646c88 4143
a54e20b4 4144 out_priv = netdev_priv(out_dev);
1d447a39 4145 rpriv = out_priv->ppriv;
df65a573
EB		 4146 attr->dests[attr->out_count].rep = rpriv->rep;
4147 attr->dests[attr->out_count].mdev = out_priv->mdev;
4148 attr->out_count++;
ef381359
OS		 4149 } else if (parse_attr->filter_dev != priv->netdev) {
4150 /* All mlx5 devices are called to configure
4151 * high level device filters. Therefore, the
4152 * *attempt* to install a filter on invalid
4153 * eswitch should not trigger an explicit error
4154 */
4155 return -EINVAL;
a54e20b4 4156 } else {
e98bedf5
EB		 4157 NL_SET_ERR_MSG_MOD(extack,
4158 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4159 netdev_warn(priv->netdev,
4160 "devices %s %s not on same switch HW, can't offload forwarding\n",
4161 priv->netdev->name,
4162 out_dev->name);
03a9d11e
OG		 4163 return -EINVAL;
4164 }
73867881
PNA		 4165 }
4166 break;
4167 case FLOW_ACTION_TUNNEL_ENCAP:
4168 info = act->tunnel;
a54e20b4
HHZ		 4169 if (info)
4170 encap = true;
4171 else
4172 return -EOPNOTSUPP;
1482bd3d 4173
73867881
PNA		 4174 break;
4175 case FLOW_ACTION_VLAN_PUSH:
4176 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4177 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4178 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4179 /* Replace vlan pop+push with vlan modify */
4180 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4181 err = add_vlan_rewrite_action(priv,
4182 MLX5_FLOW_NAMESPACE_FDB,
4183 act, parse_attr, hdrs,
4184 &action, extack);
4185 } else {
4186 err = parse_tc_vlan_action(priv, act, attr, &action);
4187 }
1482bd3d
JL		 4188 if (err)
4189 return err;
4190
bdc837ee
EB		 4191 attr->split_count = attr->out_count;
4192 break;
4193 case FLOW_ACTION_VLAN_MANGLE:
4194 err = add_vlan_rewrite_action(priv,
4195 MLX5_FLOW_NAMESPACE_FDB,
4196 act, parse_attr, hdrs,
4197 &action, extack);
4198 if (err)
4199 return err;
4200
e85e02ba 4201 attr->split_count = attr->out_count;
73867881
PNA		 4202 break;
4203 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4204 decap = true;
73867881 4205 break;
2fbbc30d
EC		 4206 case FLOW_ACTION_GOTO:
4207 err = mlx5_validate_goto_chain(esw, flow, act, action,
4208 extack);
4209 if (err)
4210 return err;
bf07aa73 4211
e88afe75 4212 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4213 attr->dest_chain = act->chain_index;
73867881 4214 break;
4c3844d9
PB		 4215 case FLOW_ACTION_CT:
4216 err = mlx5_tc_ct_parse_action(priv, attr, act, extack);
4217 if (err)
4218 return err;
4219
4220 flow_flag_set(flow, CT);
4221 break;
73867881 4222 default:
2cc1cb1d
TZ		 4223 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4224 return -EOPNOTSUPP;
bf07aa73 4225 }
03a9d11e 4226 }
bdd66ac0 4227
0bac1194
EB		 4228 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4229 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4230 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4231 * tag rewrite.
4232 */
4233 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4234 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4235 &action, extack);
4236 if (err)
4237 return err;
4238 }
4239
c500c86b
PNA		 4240 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4241 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4242 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4243 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4244 if (err)
4245 return err;
27c11b6b
EB		 4246 /* in case all pedit actions are skipped, remove the MOD_HDR
4247 * flag. we might have set split_count either by pedit or
4248 * pop/push. if there is no pop/push either, reset it too.
4249 */
6ae4a6a5 4250 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4251 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4252 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4253 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4254 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
4255 attr->split_count = 0;
4256 }
c500c86b
PNA		 4257 }
4258
1cab1cd7 4259 attr->action = action;
73867881 4260 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4261 return -EOPNOTSUPP;
4262
e88afe75 4263 if (attr->dest_chain) {
0a7fcb78
PB		 4264 if (decap) {
4265 /* It can be supported if we'll create a mapping for
4266 * the tunnel device only (without tunnel), and set
4267 * this tunnel id with this decap flow.
4268 *
4269 * On restore (miss), we'll just set this saved tunnel
4270 * device.
4271 */
4272
4273 NL_SET_ERR_MSG(extack,
4274 "Decap with goto isn't supported");
4275 netdev_warn(priv->netdev,
4276 "Decap with goto isn't supported");
4277 return -EOPNOTSUPP;
4278 }
4279
e88afe75 4280 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 4281 NL_SET_ERR_MSG_MOD(extack,
4282 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 4283 return -EOPNOTSUPP;
4284 }
4285 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4286 }
4287
ae2741e2
VB		 4288 if (!(attr->action &
4289 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4290 NL_SET_ERR_MSG_MOD(extack,
4291 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4292 return -EOPNOTSUPP;
4293 }
4294
e85e02ba 4295 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4296 NL_SET_ERR_MSG_MOD(extack,
4297 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4298 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4299 return -EOPNOTSUPP;
4300 }
4301
31c8eba5 4302 return 0;
03a9d11e
OG		 4303}
4304
226f2ca3 4305static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4306{
226f2ca3 4307 unsigned long __flow_flags = 0;
60bd4af8 4308
226f2ca3
VB		 4309 if (flags & MLX5_TC_FLAG(INGRESS))
4310 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4311 if (flags & MLX5_TC_FLAG(EGRESS))
4312 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4313
226f2ca3
VB		 4314 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4315 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4316 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4317 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4318 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4319 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4320
60bd4af8
OG		 4321 *flow_flags = __flow_flags;
4322}
4323
05866c82
OG		 4324static const struct rhashtable_params tc_ht_params = {
4325 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4326 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4327 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4328 .automatic_shrinking = true,
4329};
4330
226f2ca3
VB		 4331static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4332 unsigned long flags)
05866c82 4333{
655dc3d2
OG		 4334 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4335 struct mlx5e_rep_priv *uplink_rpriv;
4336
226f2ca3 4337 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4338 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4339 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4340 } else /* NIC offload */
655dc3d2 4341 return &priv->fs.tc.ht;
05866c82
OG		 4342}
4343
04de7dda
RD		 4344static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4345{
1418ddd9 4346 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 4347 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4348 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4349 bool act_is_encap = !!(attr->action &
4350 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4351 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
4352 MLX5_DEVCOM_ESW_OFFLOADS);
4353
10fbb1cd
RD		 4354 if (!esw_paired)
4355 return false;
4356
4357 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
4358 mlx5_lag_is_multipath(attr->in_mdev)) &&
4359 (is_rep_ingress || act_is_encap))
4360 return true;
4361
4362 return false;
04de7dda
RD		 4363}
4364
a88780a9
RD		 4365static int
4366mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4367 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4368 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4369 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4370{
17091853 4371 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 4372 struct mlx5e_tc_flow *flow;
5a7e5bcb 4373 int out_index, err;
e3a2b7ed 4374
65ba8fb7 4375 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 4376 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 4377 if (!parse_attr || !flow) {
e3a2b7ed
AV		 4378 err = -ENOMEM;
4379 goto err_free;
4380 }
4381
4382 flow->cookie = f->cookie;
65ba8fb7 4383 flow->flags = flow_flags;
655dc3d2 4384 flow->priv = priv;
5a7e5bcb
VB		 4385 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4386 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4387 INIT_LIST_HEAD(&flow->mod_hdr);
4388 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4389 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4390 refcount_set(&flow->refcnt, 1);
95435ad7 4391 init_completion(&flow->init_done);
e3a2b7ed 4392
a88780a9
RD		 4393 *__flow = flow;
4394 *__parse_attr = parse_attr;
4395
4396 return 0;
4397
4398err_free:
4399 kfree(flow);
4400 kvfree(parse_attr);
4401 return err;
4402}
4403
988ab9c7
TZ		 4404static void
4405mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
4406 struct mlx5e_priv *priv,
4407 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4408 struct flow_cls_offload *f,
988ab9c7
TZ		 4409 struct mlx5_eswitch_rep *in_rep,
4410 struct mlx5_core_dev *in_mdev)
4411{
4412 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4413
4414 esw_attr->parse_attr = parse_attr;
4415 esw_attr->chain = f->common.chain_index;
ef01adae 4416 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 4417
4418 esw_attr->in_rep = in_rep;
4419 esw_attr->in_mdev = in_mdev;
4420
4421 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4422 MLX5_COUNTER_SOURCE_ESWITCH)
4423 esw_attr->counter_dev = in_mdev;
4424 else
4425 esw_attr->counter_dev = priv->mdev;
4426}
4427
71129676 4428static struct mlx5e_tc_flow *
04de7dda 4429__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4430 struct flow_cls_offload *f,
226f2ca3 4431 unsigned long flow_flags,
04de7dda
RD		 4432 struct net_device *filter_dev,
4433 struct mlx5_eswitch_rep *in_rep,
71129676 4434 struct mlx5_core_dev *in_mdev)
a88780a9 4435{
f9e30088 4436 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4437 struct netlink_ext_ack *extack = f->common.extack;
4438 struct mlx5e_tc_flow_parse_attr *parse_attr;
4439 struct mlx5e_tc_flow *flow;
4440 int attr_size, err;
e3a2b7ed 4441
226f2ca3 4442 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4443 attr_size = sizeof(struct mlx5_esw_flow_attr);
4444 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4445 &parse_attr, &flow);
4446 if (err)
4447 goto out;
988ab9c7 4448
d11afc26 4449 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 4450 mlx5e_flow_esw_attr_init(flow->esw_attr,
4451 priv, parse_attr,
4452 f, in_rep, in_mdev);
4453
54c177ca
OS		 4454 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4455 f, filter_dev);
d11afc26
OS		 4456 if (err)
4457 goto err_free;
a88780a9 4458
14e6b038 4459 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
a88780a9
RD		 4460 if (err)
4461 goto err_free;
4462
4c3844d9
PB		 4463 err = mlx5_tc_ct_parse_match(priv, &parse_attr->spec, f, extack);
4464 if (err)
4465 goto err_free;
4466
7040632d 4467 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4468 complete_all(&flow->init_done);
ef06c9ee
RD		 4469 if (err) {
4470 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4471 goto err_free;
4472
b4a23329 4473 add_unready_flow(flow);
ef06c9ee 4474 }
e3a2b7ed 4475
71129676 4476 return flow;
a88780a9
RD		 4477
4478err_free:
5a7e5bcb 4479 mlx5e_flow_put(priv, flow);
a88780a9 4480out:
71129676 4481 return ERR_PTR(err);
a88780a9
RD		 4482}
4483
f9e30088 4484static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4485 struct mlx5e_tc_flow *flow,
226f2ca3 4486 unsigned long flow_flags)
04de7dda
RD		 4487{
4488 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4489 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4490 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4491 struct mlx5e_tc_flow_parse_attr *parse_attr;
4492 struct mlx5e_rep_priv *peer_urpriv;
4493 struct mlx5e_tc_flow *peer_flow;
4494 struct mlx5_core_dev *in_mdev;
4495 int err = 0;
4496
4497 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4498 if (!peer_esw)
4499 return -ENODEV;
4500
4501 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4502 peer_priv = netdev_priv(peer_urpriv->netdev);
4503
4504 /* in_mdev is assigned of which the packet originated from.
4505 * So packets redirected to uplink use the same mdev of the
4506 * original flow and packets redirected from uplink use the
4507 * peer mdev.
4508 */
b05af6aa 4509 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4510 in_mdev = peer_priv->mdev;
4511 else
4512 in_mdev = priv->mdev;
4513
4514 parse_attr = flow->esw_attr->parse_attr;
95dc1902 4515 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 4516 parse_attr->filter_dev,
4517 flow->esw_attr->in_rep, in_mdev);
4518 if (IS_ERR(peer_flow)) {
4519 err = PTR_ERR(peer_flow);
04de7dda 4520 goto out;
71129676 4521 }
04de7dda
RD		 4522
4523 flow->peer_flow = peer_flow;
226f2ca3 4524 flow_flag_set(flow, DUP);
04de7dda
RD		 4525 mutex_lock(&esw->offloads.peer_mutex);
4526 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4527 mutex_unlock(&esw->offloads.peer_mutex);
4528
4529out:
4530 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4531 return err;
4532}
4533
4534static int
4535mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4536 struct flow_cls_offload *f,
226f2ca3 4537 unsigned long flow_flags,
04de7dda
RD		 4538 struct net_device *filter_dev,
4539 struct mlx5e_tc_flow **__flow)
4540{
4541 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4542 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4543 struct mlx5_core_dev *in_mdev = priv->mdev;
4544 struct mlx5e_tc_flow *flow;
4545 int err;
4546
71129676
JG		 4547 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4548 in_mdev);
4549 if (IS_ERR(flow))
4550 return PTR_ERR(flow);
04de7dda
RD		 4551
4552 if (is_peer_flow_needed(flow)) {
95dc1902 4553 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4554 if (err) {
4555 mlx5e_tc_del_fdb_flow(priv, flow);
4556 goto out;
4557 }
4558 }
4559
4560 *__flow = flow;
4561
4562 return 0;
4563
4564out:
4565 return err;
4566}
4567
a88780a9
RD		 4568static int
4569mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4570 struct flow_cls_offload *f,
226f2ca3 4571 unsigned long flow_flags,
d11afc26 4572 struct net_device *filter_dev,
a88780a9
RD		 4573 struct mlx5e_tc_flow **__flow)
4574{
f9e30088 4575 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4576 struct netlink_ext_ack *extack = f->common.extack;
4577 struct mlx5e_tc_flow_parse_attr *parse_attr;
4578 struct mlx5e_tc_flow *flow;
4579 int attr_size, err;
4580
bf07aa73
PB		 4581 /* multi-chain not supported for NIC rules */
4582 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4583 return -EOPNOTSUPP;
4584
226f2ca3 4585 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4586 attr_size = sizeof(struct mlx5_nic_flow_attr);
4587 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4588 &parse_attr, &flow);
4589 if (err)
4590 goto out;
4591
d11afc26 4592 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 4593 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4594 f, filter_dev);
d11afc26
OS		 4595 if (err)
4596 goto err_free;
4597
73867881 4598 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4599 if (err)
4600 goto err_free;
4601
4602 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4603 if (err)
4604 goto err_free;
4605
226f2ca3 4606 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4607 kvfree(parse_attr);
4608 *__flow = flow;
4609
4610 return 0;
e3a2b7ed 4611
e3a2b7ed 4612err_free:
5a7e5bcb 4613 mlx5e_flow_put(priv, flow);
17091853 4614 kvfree(parse_attr);
a88780a9
RD		 4615out:
4616 return err;
4617}
4618
4619static int
4620mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4621 struct flow_cls_offload *f,
226f2ca3 4622 unsigned long flags,
d11afc26 4623 struct net_device *filter_dev,
a88780a9
RD		 4624 struct mlx5e_tc_flow **flow)
4625{
4626 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4627 unsigned long flow_flags;
a88780a9
RD		 4628 int err;
4629
4630 get_flags(flags, &flow_flags);
4631
bf07aa73
PB		 4632 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4633 return -EOPNOTSUPP;
4634
f6455de0 4635 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4636 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4637 filter_dev, flow);
a88780a9 4638 else
d11afc26
OS		 4639 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4640 filter_dev, flow);
a88780a9
RD		 4641
4642 return err;
4643}
4644
553f9328
VP		 4645static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4646 struct mlx5e_rep_priv *rpriv)
4647{
4648 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4649 * sharing tc block with other slaves of a lag device.
4650 */
4651 return netif_is_lag_port(dev) && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4652}
4653
71d82d2a 4654int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4655 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4656{
4657 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4658 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4659 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4660 struct mlx5e_tc_flow *flow;
4661 int err = 0;
4662
c5d326b2
VB		 4663 rcu_read_lock();
4664 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4665 rcu_read_unlock();
a88780a9 4666 if (flow) {
553f9328
VP		 4667 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4668 * just return 0.
4669 */
4670 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4671 goto out;
4672
a88780a9
RD		 4673 NL_SET_ERR_MSG_MOD(extack,
4674 "flow cookie already exists, ignoring");
4675 netdev_warn_once(priv->netdev,
4676 "flow cookie %lx already exists, ignoring\n",
4677 f->cookie);
0e1c1a2f 4678 err = -EEXIST;
a88780a9
RD		 4679 goto out;
4680 }
4681
7a978759 4682 trace_mlx5e_configure_flower(f);
d11afc26 4683 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4684 if (err)
4685 goto out;
4686
553f9328
VP		 4687 /* Flow rule offloaded to non-uplink representor sharing tc block,
4688 * set the flow's owner dev.
4689 */
4690 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4691 flow->orig_dev = dev;
4692
c5d326b2 4693 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4694 if (err)
4695 goto err_free;
4696
4697 return 0;
4698
4699err_free:
5a7e5bcb 4700 mlx5e_flow_put(priv, flow);
a88780a9 4701out:
e3a2b7ed
AV		 4702 return err;
4703}
4704
8f8ae895
OG		 4705static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4706{
226f2ca3
VB		 4707 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4708 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4709
226f2ca3
VB		 4710 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4711 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4712}
4713
71d82d2a 4714int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4715 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4716{
d9ee0491 4717 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4718 struct mlx5e_tc_flow *flow;
c5d326b2 4719 int err;
e3a2b7ed 4720
c5d326b2 4721 rcu_read_lock();
ab818362 4722 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4723 if (!flow || !same_flow_direction(flow, flags)) {
4724 err = -EINVAL;
4725 goto errout;
4726 }
e3a2b7ed 4727
c5d326b2
VB		 4728 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4729 * set.
4730 */
4731 if (flow_flag_test_and_set(flow, DELETED)) {
4732 err = -EINVAL;
4733 goto errout;
4734 }
05866c82 4735 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4736 rcu_read_unlock();
e3a2b7ed 4737
7a978759 4738 trace_mlx5e_delete_flower(f);
5a7e5bcb 4739 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4740
4741 return 0;
c5d326b2
VB		 4742
4743errout:
4744 rcu_read_unlock();
4745 return err;
e3a2b7ed
AV		 4746}
4747
71d82d2a 4748int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4749 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4750{
04de7dda 4751 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4752 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4753 struct mlx5_eswitch *peer_esw;
aad7e08d 4754 struct mlx5e_tc_flow *flow;
aad7e08d 4755 struct mlx5_fc *counter;
316d5f72
RD		 4756 u64 lastuse = 0;
4757 u64 packets = 0;
4758 u64 bytes = 0;
5a7e5bcb 4759 int err = 0;
aad7e08d 4760
c5d326b2
VB		 4761 rcu_read_lock();
4762 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4763 tc_ht_params));
4764 rcu_read_unlock();
5a7e5bcb
VB		 4765 if (IS_ERR(flow))
4766 return PTR_ERR(flow);
4767
4768 if (!same_flow_direction(flow, flags)) {
4769 err = -EINVAL;
4770 goto errout;
4771 }
aad7e08d 4772
4c3844d9 4773 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4774 counter = mlx5e_tc_get_counter(flow);
4775 if (!counter)
5a7e5bcb 4776 goto errout;
aad7e08d 4777
316d5f72
RD		 4778 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4779 }
aad7e08d 4780
316d5f72
RD		 4781 /* Under multipath it's possible for one rule to be currently
4782 * un-offloaded while the other rule is offloaded.
4783 */
04de7dda
RD		 4784 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4785 if (!peer_esw)
4786 goto out;
4787
226f2ca3
VB		 4788 if (flow_flag_test(flow, DUP) &&
4789 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4790 u64 bytes2;
4791 u64 packets2;
4792 u64 lastuse2;
4793
4794 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4795 if (!counter)
4796 goto no_peer_counter;
04de7dda
RD		 4797 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4798
4799 bytes += bytes2;
4800 packets += packets2;
4801 lastuse = max_t(u64, lastuse, lastuse2);
4802 }
4803
316d5f72 4804no_peer_counter:
04de7dda 4805 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4806out:
93a129eb
JP		 4807 flow_stats_update(&f->stats, bytes, packets, lastuse,
4808 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4809 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4810errout:
4811 mlx5e_flow_put(priv, flow);
4812 return err;
aad7e08d
AV		 4813}
4814
fcb64c0f
EC		 4815static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4816 struct netlink_ext_ack *extack)
4817{
4818 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4819 struct mlx5_eswitch *esw;
4820 u16 vport_num;
4821 u32 rate_mbps;
4822 int err;
4823
e401a184
EC		 4824 vport_num = rpriv->rep->vport;
4825 if (vport_num >= MLX5_VPORT_ECPF) {
4826 NL_SET_ERR_MSG_MOD(extack,
4827 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4828 return -EOPNOTSUPP;
4829 }
4830
fcb64c0f
EC		 4831 esw = priv->mdev->priv.eswitch;
4832 /* rate is given in bytes/sec.
4833 * First convert to bits/sec and then round to the nearest mbit/secs.
4834 * mbit means million bits.
4835 * Moreover, if rate is non zero we choose to configure to a minimum of
4836 * 1 mbit/sec.
4837 */
4838 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
fcb64c0f
EC		 4839 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4840 if (err)
4841 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4842
4843 return err;
4844}
4845
4846static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4847 struct flow_action *flow_action,
4848 struct netlink_ext_ack *extack)
4849{
4850 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4851 const struct flow_action_entry *act;
4852 int err;
4853 int i;
4854
4855 if (!flow_action_has_entries(flow_action)) {
4856 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4857 return -EINVAL;
4858 }
4859
4860 if (!flow_offload_has_one_action(flow_action)) {
4861 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4862 return -EOPNOTSUPP;
4863 }
4864
53eca1f3 4865 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4866 return -EOPNOTSUPP;
4867
fcb64c0f
EC		 4868 flow_action_for_each(i, act, flow_action) {
4869 switch (act->id) {
4870 case FLOW_ACTION_POLICE:
4871 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4872 if (err)
4873 return err;
4874
4875 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4876 break;
4877 default:
4878 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4879 return -EOPNOTSUPP;
4880 }
4881 }
4882
4883 return 0;
4884}
4885
4886int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4887 struct tc_cls_matchall_offload *ma)
4888{
b5f814cc 4889 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4890 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4891
b5f814cc
EC		 4892 if (!mlx5_esw_qos_enabled(esw)) {
4893 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4894 return -EOPNOTSUPP;
4895 }
4896
7b83355f 4897 if (ma->common.prio != 1) {
fcb64c0f
EC		 4898 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4899 return -EINVAL;
4900 }
4901
4902 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4903}
4904
4905int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4906 struct tc_cls_matchall_offload *ma)
4907{
4908 struct netlink_ext_ack *extack = ma->common.extack;
4909
4910 return apply_police_params(priv, 0, extack);
4911}
4912
4913void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4914 struct tc_cls_matchall_offload *ma)
4915{
4916 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4917 struct rtnl_link_stats64 cur_stats;
4918 u64 dbytes;
4919 u64 dpkts;
4920
4921 cur_stats = priv->stats.vf_vport;
4922 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4923 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4924 rpriv->prev_vf_vport_stats = cur_stats;
93a129eb
JP		 4925 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies,
4926 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4927}
4928
4d8fcf21
AH		 4929static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4930 struct mlx5e_priv *peer_priv)
4931{
4932 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4933 struct mlx5e_hairpin_entry *hpe, *tmp;
4934 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4935 u16 peer_vhca_id;
4936 int bkt;
4937
4938 if (!same_hw_devs(priv, peer_priv))
4939 return;
4940
4941 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4942
b32accda 4943 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4944 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4945 if (refcount_inc_not_zero(&hpe->refcnt))
4946 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4947 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4948
4949 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4950 wait_for_completion(&hpe->res_ready);
4951 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4952 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4953
4954 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4955 }
4956}
4957
4958static int mlx5e_tc_netdev_event(struct notifier_block *this,
4959 unsigned long event, void *ptr)
4960{
4961 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4962 struct mlx5e_flow_steering *fs;
4963 struct mlx5e_priv *peer_priv;
4964 struct mlx5e_tc_table *tc;
4965 struct mlx5e_priv *priv;
4966
4967 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4968 event != NETDEV_UNREGISTER ||
4969 ndev->reg_state == NETREG_REGISTERED)
4970 return NOTIFY_DONE;
4971
4972 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4973 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4974 priv = container_of(fs, struct mlx5e_priv, fs);
4975 peer_priv = netdev_priv(ndev);
4976 if (priv == peer_priv ||
4977 !(priv->netdev->features & NETIF_F_HW_TC))
4978 return NOTIFY_DONE;
4979
4980 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4981
4982 return NOTIFY_DONE;
4983}
4984
655dc3d2 4985int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4986{
acff797c 4987 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4988 int err;
e8f887ac 4989
b6fac0b4 4990 mutex_init(&tc->t_lock);
d2faae25 4991 mutex_init(&tc->mod_hdr.lock);
dd58edc3 4992 hash_init(tc->mod_hdr.hlist);
b32accda 4993 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4994 hash_init(tc->hairpin_tbl);
11c9c548 4995
4d8fcf21
AH		 4996 err = rhashtable_init(&tc->ht, &tc_ht_params);
4997 if (err)
4998 return err;
4999
5000 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 5001 err = register_netdevice_notifier_dev_net(priv->netdev,
5002 &tc->netdevice_nb,
5003 &tc->netdevice_nn);
5004 if (err) {
4d8fcf21
AH		 5005 tc->netdevice_nb.notifier_call = NULL;
5006 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5007 }
5008
5009 return err;
e8f887ac
AV		 5010}
5011
5012static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5013{
5014 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5015 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5016
961e8979 5017 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5018 kfree(flow);
5019}
5020
655dc3d2 5021void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5022{
acff797c 5023 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5024
4d8fcf21 5025 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5026 unregister_netdevice_notifier_dev_net(priv->netdev,
5027 &tc->netdevice_nb,
5028 &tc->netdevice_nn);
4d8fcf21 5029
d2faae25 5030 mutex_destroy(&tc->mod_hdr.lock);
b32accda
VB		 5031 mutex_destroy(&tc->hairpin_tbl_lock);
5032
d9ee0491 5033 rhashtable_destroy(&tc->ht);
e8f887ac 5034
acff797c
MG		 5035 if (!IS_ERR_OR_NULL(tc->t)) {
5036 mlx5_destroy_flow_table(tc->t);
5037 tc->t = NULL;
e8f887ac 5038 }
b6fac0b4 5039 mutex_destroy(&tc->t_lock);
e8f887ac 5040}
655dc3d2
OG		 5041
5042int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5043{
d7a42ad0 5044 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78
PB		 5045 struct mlx5_rep_uplink_priv *uplink_priv;
5046 struct mlx5e_rep_priv *priv;
5047 struct mapping_ctx *mapping;
5048 int err;
5049
5050 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
5051 priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5052
4c3844d9
PB		 5053 err = mlx5_tc_ct_init(uplink_priv);
5054 if (err)
5055 goto err_ct;
5056
0a7fcb78
PB		 5057 mapping = mapping_create(sizeof(struct tunnel_match_key),
5058 TUNNEL_INFO_BITS_MASK, true);
5059 if (IS_ERR(mapping)) {
5060 err = PTR_ERR(mapping);
5061 goto err_tun_mapping;
5062 }
5063 uplink_priv->tunnel_mapping = mapping;
5064
5065 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
5066 if (IS_ERR(mapping)) {
5067 err = PTR_ERR(mapping);
5068 goto err_enc_opts_mapping;
5069 }
5070 uplink_priv->tunnel_enc_opts_mapping = mapping;
5071
5072 err = rhashtable_init(tc_ht, &tc_ht_params);
5073 if (err)
5074 goto err_ht_init;
5075
5076 return err;
5077
5078err_ht_init:
5079 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5080err_enc_opts_mapping:
5081 mapping_destroy(uplink_priv->tunnel_mapping);
5082err_tun_mapping:
4c3844d9
PB		 5083 mlx5_tc_ct_clean(uplink_priv);
5084err_ct:
0a7fcb78
PB		 5085 netdev_warn(priv->netdev,
5086 "Failed to initialize tc (eswitch), err: %d", err);
5087 return err;
655dc3d2
OG		 5088}
5089
5090void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5091{
0a7fcb78
PB		 5092 struct mlx5_rep_uplink_priv *uplink_priv;
5093
655dc3d2 5094 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 5095
5096 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
5097 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5098 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9
PB		 5099
5100 mlx5_tc_ct_clean(uplink_priv);
655dc3d2 5101}
01252a27 5102
226f2ca3 5103int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5104{
d9ee0491 5105 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5106
5107 return atomic_read(&tc_ht->nelems);
5108}
04de7dda
RD		 5109
5110void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5111{
5112 struct mlx5e_tc_flow *flow, *tmp;
5113
5114 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5115 __mlx5e_tc_del_fdb_peer_flow(flow);
5116}
b4a23329
RD		 5117
5118void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5119{
5120 struct mlx5_rep_uplink_priv *rpriv =
5121 container_of(work, struct mlx5_rep_uplink_priv,
5122 reoffload_flows_work);
5123 struct mlx5e_tc_flow *flow, *tmp;
5124
ad86755b 5125 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5126 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5127 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5128 unready_flow_del(flow);
b4a23329 5129 }
ad86755b 5130 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5131}
e2394a61
VB		 5132
5133static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5134 struct flow_cls_offload *cls_flower,
5135 unsigned long flags)
5136{
5137 switch (cls_flower->command) {
5138 case FLOW_CLS_REPLACE:
5139 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5140 flags);
5141 case FLOW_CLS_DESTROY:
5142 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5143 flags);
5144 case FLOW_CLS_STATS:
5145 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5146 flags);
5147 default:
5148 return -EOPNOTSUPP;
5149 }
5150}
5151
5152int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5153 void *cb_priv)
5154{
5155 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
5156 struct mlx5e_priv *priv = cb_priv;
5157
5158 switch (type) {
5159 case TC_SETUP_CLSFLOWER:
5160 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5161 default:
5162 return -EOPNOTSUPP;
5163 }
5164}
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