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net/mlx5: SF, Fix show state inactive when its inactivated
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
41c2fd94 50#include <net/psample.h>
f6dfb4c3 51#include <net/arp.h>
3616d08b 52#include <net/ipv6_stubs.h>
f828ca6a 53#include <net/bareudp.h>
d34eb2fc 54#include <net/bonding.h>
e8f887ac 55#include "en.h"
1d447a39 56#include "en_rep.h"
768c3667 57#include "en/rep/tc.h"
e2394a61 58#include "en/rep/neigh.h"
232c0013 59#include "en_tc.h"
03a9d11e 60#include "eswitch.h"
3f6d08d1 61#include "fs_core.h"
2c81bfd5 62#include "en/port.h"
101f4de9 63#include "en/tc_tun.h"
0a7fcb78 64#include "en/mapping.h"
4c3844d9 65#include "en/tc_ct.h"
b2fdf3d0 66#include "en/mod_hdr.h"
0d9f9647
VB		 67#include "en/tc_priv.h"
68#include "en/tc_tun_encap.h"
2a9ab10a 69#include "esw/sample.h"
04de7dda 70#include "lib/devcom.h"
9272e3df 71#include "lib/geneve.h"
ae430332 72#include "lib/fs_chains.h"
7a978759 73#include "diag/en_tc_tracepoint.h"
1fe3e316 74#include <asm/div64.h>
e8f887ac 75
6a064674 76#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 77#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 78
acff797c 79#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 80#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 81
8f1e0b97
PB		 82struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
83 [CHAIN_TO_REG] = {
84 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
85 .moffset = 0,
86 .mlen = 2,
87 },
10742efc
VB		 88 [VPORT_TO_REG] = {
89 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
90 .moffset = 2,
91 .mlen = 2,
92 },
0a7fcb78
PB		 93 [TUNNEL_TO_REG] = {
94 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521 95 .moffset = 1,
48d216e5 96 .mlen = ((ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS) / 8),
0a7fcb78
PB		 97 .soffset = MLX5_BYTE_OFF(fte_match_param,
98 misc_parameters_2.metadata_reg_c_1),
99 },
4c3844d9 100 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 101 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 102 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
103 [MARK_TO_REG] = mark_to_reg_ct,
104 [LABELS_TO_REG] = labels_to_reg_ct,
105 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 106 /* For NIC rules we store the retore metadata directly
107 * into reg_b that is passed to SW since we don't
108 * jump between steering domains.
109 */
110 [NIC_CHAIN_TO_REG] = {
111 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
112 .moffset = 0,
113 .mlen = 2,
114 },
aedd133d 115 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 116};
117
9ba33339
RD		 118/* To avoid false lock dependency warning set the tc_ht lock
119 * class different than the lock class of the ht being used when deleting
120 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
121 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
122 * it's different than the ht->mutex here.
123 */
124static struct lock_class_key tc_ht_lock_key;
125
0a7fcb78
PB		 126static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
127
128void
129mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
130 enum mlx5e_tc_attr_to_reg type,
131 u32 data,
132 u32 mask)
133{
134 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
135 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
136 void *headers_c = spec->match_criteria;
137 void *headers_v = spec->match_value;
138 void *fmask, *fval;
139
140 fmask = headers_c + soffset;
141 fval = headers_v + soffset;
142
58ff18e1
SM		 143 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
144 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 145
146 memcpy(fmask, &mask, match_len);
147 memcpy(fval, &data, match_len);
148
149 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
150}
151
7e36feeb
PB		 152void
153mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
154 enum mlx5e_tc_attr_to_reg type,
155 u32 *data,
156 u32 *mask)
157{
158 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
159 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
160 void *headers_c = spec->match_criteria;
161 void *headers_v = spec->match_value;
162 void *fmask, *fval;
163
164 fmask = headers_c + soffset;
165 fval = headers_v + soffset;
166
167 memcpy(mask, fmask, match_len);
168 memcpy(data, fval, match_len);
169
170 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
171 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
172}
173
0a7fcb78 174int
c7b9038d
VB		 175mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
176 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
177 enum mlx5_flow_namespace_type ns,
178 enum mlx5e_tc_attr_to_reg type,
179 u32 data)
0a7fcb78
PB		 180{
181 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
182 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
183 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
184 char *modact;
185 int err;
186
aedd133d 187 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 188 if (err)
189 return err;
190
191 modact = mod_hdr_acts->actions +
192 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
193
194 /* Firmware has 5bit length field and 0 means 32bits */
195 if (mlen == 4)
196 mlen = 0;
197
198 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
199 MLX5_SET(set_action_in, modact, field, mfield);
200 MLX5_SET(set_action_in, modact, offset, moffset * 8);
201 MLX5_SET(set_action_in, modact, length, mlen * 8);
202 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 203 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 204 mod_hdr_acts->num_actions++;
205
c7b9038d 206 return err;
0a7fcb78
PB		 207}
208
aedd133d
AL		 209static struct mlx5_tc_ct_priv *
210get_ct_priv(struct mlx5e_priv *priv)
211{
212 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
213 struct mlx5_rep_uplink_priv *uplink_priv;
214 struct mlx5e_rep_priv *uplink_rpriv;
215
e8711402 216 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 217 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
218 uplink_priv = &uplink_rpriv->uplink_priv;
219
220 return uplink_priv->ct_priv;
221 }
222
223 return priv->fs.tc.ct;
224}
225
f94d6389
CM		 226#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
227static struct mlx5_esw_psample *
228get_sample_priv(struct mlx5e_priv *priv)
229{
230 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
231 struct mlx5_rep_uplink_priv *uplink_priv;
232 struct mlx5e_rep_priv *uplink_rpriv;
233
234 if (is_mdev_switchdev_mode(priv->mdev)) {
235 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
236 uplink_priv = &uplink_rpriv->uplink_priv;
237
238 return uplink_priv->esw_psample;
239 }
240
241 return NULL;
242}
243#endif
244
aedd133d
AL		 245struct mlx5_flow_handle *
246mlx5_tc_rule_insert(struct mlx5e_priv *priv,
247 struct mlx5_flow_spec *spec,
248 struct mlx5_flow_attr *attr)
249{
250 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
251
e8711402 252 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 253 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
254
255 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
256}
257
258void
259mlx5_tc_rule_delete(struct mlx5e_priv *priv,
260 struct mlx5_flow_handle *rule,
261 struct mlx5_flow_attr *attr)
262{
263 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
264
e8711402 265 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 266 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
267
268 return;
269 }
270
271 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
272}
273
c7b9038d
VB		 274int
275mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
276 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
277 enum mlx5_flow_namespace_type ns,
278 enum mlx5e_tc_attr_to_reg type,
279 u32 data)
280{
281 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
282
283 return ret < 0 ? ret : 0;
284}
285
286void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
287 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
288 enum mlx5e_tc_attr_to_reg type,
289 int act_id, u32 data)
290{
291 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
292 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
293 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
294 char *modact;
295
296 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
297
298 /* Firmware has 5bit length field and 0 means 32bits */
299 if (mlen == 4)
300 mlen = 0;
301
302 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
303 MLX5_SET(set_action_in, modact, field, mfield);
304 MLX5_SET(set_action_in, modact, offset, moffset * 8);
305 MLX5_SET(set_action_in, modact, length, mlen * 8);
306 MLX5_SET(set_action_in, modact, data, data);
307}
308
77ab67b7
OG		 309struct mlx5e_hairpin {
310 struct mlx5_hairpin *pair;
311
312 struct mlx5_core_dev *func_mdev;
3f6d08d1 313 struct mlx5e_priv *func_priv;
77ab67b7
OG		 314 u32 tdn;
315 u32 tirn;
3f6d08d1
OG		 316
317 int num_channels;
318 struct mlx5e_rqt indir_rqt;
319 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
320 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 321};
322
5c65c564
OG		 323struct mlx5e_hairpin_entry {
324 /* a node of a hash table which keeps all the hairpin entries */
325 struct hlist_node hairpin_hlist;
326
73edca73
VB		 327 /* protects flows list */
328 spinlock_t flows_lock;
5c65c564
OG		 329 /* flows sharing the same hairpin */
330 struct list_head flows;
db76ca24
VB		 331 /* hpe's that were not fully initialized when dead peer update event
332 * function traversed them.
333 */
334 struct list_head dead_peer_wait_list;
5c65c564 335
d8822868 336 u16 peer_vhca_id;
106be53b 337 u8 prio;
5c65c564 338 struct mlx5e_hairpin *hp;
e4f9abbd 339 refcount_t refcnt;
db76ca24 340 struct completion res_ready;
5c65c564
OG		 341};
342
5a7e5bcb
VB		 343static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
344 struct mlx5e_tc_flow *flow);
345
0d9f9647 346struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 347{
348 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
349 return ERR_PTR(-EINVAL);
350 return flow;
351}
352
0d9f9647 353void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 354{
355 if (refcount_dec_and_test(&flow->refcnt)) {
356 mlx5e_tc_del_flow(priv, flow);
c5d326b2 357 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 358 }
359}
360
aedd133d 361bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 362{
363 return flow_flag_test(flow, ESWITCH);
364}
365
84179981
PB		 366static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
367{
368 return flow_flag_test(flow, FT);
369}
370
0d9f9647 371bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 372{
373 return flow_flag_test(flow, OFFLOADED);
374}
375
b2fdf3d0 376static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 377{
b2fdf3d0
PB		 378 return mlx5e_is_eswitch_flow(flow) ?
379 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 380}
381
dd58edc3 382static struct mod_hdr_tbl *
b2fdf3d0 383get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 384{
385 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
386
b2fdf3d0
PB		 387 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
388 &esw->offloads.mod_hdr :
dd58edc3
VB		 389 &priv->fs.tc.mod_hdr;
390}
391
11c9c548
OG		 392static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
393 struct mlx5e_tc_flow *flow,
394 struct mlx5e_tc_flow_parse_attr *parse_attr)
395{
b2fdf3d0
PB		 396 struct mlx5_modify_hdr *modify_hdr;
397 struct mlx5e_mod_hdr_handle *mh;
11c9c548 398
b2fdf3d0
PB		 399 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
400 get_flow_name_space(flow),
401 &parse_attr->mod_hdr_acts);
402 if (IS_ERR(mh))
403 return PTR_ERR(mh);
11c9c548 404
b2fdf3d0 405 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 406 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 407 flow->mh = mh;
11c9c548
OG		 408
409 return 0;
11c9c548
OG		 410}
411
412static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
413 struct mlx5e_tc_flow *flow)
414{
5a7e5bcb 415 /* flow wasn't fully initialized */
dd58edc3 416 if (!flow->mh)
5a7e5bcb
VB		 417 return;
418
b2fdf3d0
PB		 419 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
420 flow->mh);
dd58edc3 421 flow->mh = NULL;
11c9c548
OG		 422}
423
77ab67b7
OG		 424static
425struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
426{
427 struct net_device *netdev;
428 struct mlx5e_priv *priv;
429
430 netdev = __dev_get_by_index(net, ifindex);
431 priv = netdev_priv(netdev);
432 return priv->mdev;
433}
434
435static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
436{
e0b4b472 437 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 438 void *tirc;
439 int err;
440
441 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
442 if (err)
443 goto alloc_tdn_err;
444
445 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
446
447 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 448 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 449 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
450
e0b4b472 451 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 452 if (err)
453 goto create_tir_err;
454
455 return 0;
456
457create_tir_err:
458 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
459alloc_tdn_err:
460 return err;
461}
462
463static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
464{
465 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
466 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
467}
468
2119bda6 469static int mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
3f6d08d1 470{
3f6d08d1
OG		 471 struct mlx5e_priv *priv = hp->func_priv;
472 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
6def6e47 473 u32 *indirection_rqt, rqn;
3f6d08d1 474
6def6e47 475 indirection_rqt = kcalloc(sz, sizeof(*indirection_rqt), GFP_KERNEL);
2119bda6
AB		 476 if (!indirection_rqt)
477 return -ENOMEM;
478
3f6d08d1
OG		 479 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
480 hp->num_channels);
481
482 for (i = 0; i < sz; i++) {
483 ix = i;
bbeb53b8 484 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 485 ix = mlx5e_bits_invert(i, ilog2(sz));
486 ix = indirection_rqt[ix];
487 rqn = hp->pair->rqn[ix];
488 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
489 }
2119bda6
AB		 490
491 kfree(indirection_rqt);
492 return 0;
3f6d08d1
OG		 493}
494
495static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
496{
497 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
498 struct mlx5e_priv *priv = hp->func_priv;
499 struct mlx5_core_dev *mdev = priv->mdev;
500 void *rqtc;
501 u32 *in;
502
503 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
504 in = kvzalloc(inlen, GFP_KERNEL);
505 if (!in)
506 return -ENOMEM;
507
508 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
509
510 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
511 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
512
2119bda6
AB		 513 err = mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
514 if (err)
515 goto out;
3f6d08d1
OG		 516
517 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
518 if (!err)
519 hp->indir_rqt.enabled = true;
520
2119bda6 521out:
3f6d08d1
OG		 522 kvfree(in);
523 return err;
524}
525
526static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
527{
528 struct mlx5e_priv *priv = hp->func_priv;
529 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
530 int tt, i, err;
531 void *tirc;
532
533 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 534 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
535
3f6d08d1
OG		 536 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
537 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
538
539 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
540 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
541 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 542 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
543
3f6d08d1 544 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 545 &hp->indir_tirn[tt]);
3f6d08d1
OG		 546 if (err) {
547 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
548 goto err_destroy_tirs;
549 }
550 }
551 return 0;
552
553err_destroy_tirs:
554 for (i = 0; i < tt; i++)
555 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
556 return err;
557}
558
559static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
560{
561 int tt;
562
563 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
564 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
565}
566
567static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
568 struct ttc_params *ttc_params)
569{
570 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
571 int tt;
572
573 memset(ttc_params, 0, sizeof(*ttc_params));
574
575 ttc_params->any_tt_tirn = hp->tirn;
576
577 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
578 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
579
6412bb39 580 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 581 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
582 ft_attr->prio = MLX5E_TC_PRIO;
583}
584
585static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
586{
587 struct mlx5e_priv *priv = hp->func_priv;
588 struct ttc_params ttc_params;
589 int err;
590
591 err = mlx5e_hairpin_create_indirect_rqt(hp);
592 if (err)
593 return err;
594
595 err = mlx5e_hairpin_create_indirect_tirs(hp);
596 if (err)
597 goto err_create_indirect_tirs;
598
599 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
600 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
601 if (err)
602 goto err_create_ttc_table;
603
604 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
605 hp->num_channels, hp->ttc.ft.t->id);
606
607 return 0;
608
609err_create_ttc_table:
610 mlx5e_hairpin_destroy_indirect_tirs(hp);
611err_create_indirect_tirs:
612 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
613
614 return err;
615}
616
617static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
618{
619 struct mlx5e_priv *priv = hp->func_priv;
620
621 mlx5e_destroy_ttc_table(priv, &hp->ttc);
622 mlx5e_hairpin_destroy_indirect_tirs(hp);
623 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
624}
625
77ab67b7
OG		 626static struct mlx5e_hairpin *
627mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
628 int peer_ifindex)
629{
630 struct mlx5_core_dev *func_mdev, *peer_mdev;
631 struct mlx5e_hairpin *hp;
632 struct mlx5_hairpin *pair;
633 int err;
634
635 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
636 if (!hp)
637 return ERR_PTR(-ENOMEM);
638
639 func_mdev = priv->mdev;
640 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
641
642 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
643 if (IS_ERR(pair)) {
644 err = PTR_ERR(pair);
645 goto create_pair_err;
646 }
647 hp->pair = pair;
648 hp->func_mdev = func_mdev;
3f6d08d1
OG		 649 hp->func_priv = priv;
650 hp->num_channels = params->num_channels;
77ab67b7
OG		 651
652 err = mlx5e_hairpin_create_transport(hp);
653 if (err)
654 goto create_transport_err;
655
3f6d08d1
OG		 656 if (hp->num_channels > 1) {
657 err = mlx5e_hairpin_rss_init(hp);
658 if (err)
659 goto rss_init_err;
660 }
661
77ab67b7
OG		 662 return hp;
663
3f6d08d1
OG		 664rss_init_err:
665 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 666create_transport_err:
667 mlx5_core_hairpin_destroy(hp->pair);
668create_pair_err:
669 kfree(hp);
670 return ERR_PTR(err);
671}
672
673static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
674{
3f6d08d1
OG		 675 if (hp->num_channels > 1)
676 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 677 mlx5e_hairpin_destroy_transport(hp);
678 mlx5_core_hairpin_destroy(hp->pair);
679 kvfree(hp);
680}
681
106be53b
OG		 682static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
683{
684 return (peer_vhca_id << 16 | prio);
685}
686
5c65c564 687static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 688 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 689{
690 struct mlx5e_hairpin_entry *hpe;
106be53b 691 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 692
693 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 694 hairpin_hlist, hash_key) {
e4f9abbd
VB		 695 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
696 refcount_inc(&hpe->refcnt);
5c65c564 697 return hpe;
e4f9abbd 698 }
5c65c564
OG		 699 }
700
701 return NULL;
702}
703
e4f9abbd
VB		 704static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
705 struct mlx5e_hairpin_entry *hpe)
706{
707 /* no more hairpin flows for us, release the hairpin pair */
b32accda 708 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 709 return;
b32accda
VB		 710 hash_del(&hpe->hairpin_hlist);
711 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 712
db76ca24
VB		 713 if (!IS_ERR_OR_NULL(hpe->hp)) {
714 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
715 dev_name(hpe->hp->pair->peer_mdev->device));
716
717 mlx5e_hairpin_destroy(hpe->hp);
718 }
e4f9abbd
VB		 719
720 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 721 kfree(hpe);
722}
723
106be53b
OG		 724#define UNKNOWN_MATCH_PRIO 8
725
726static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 727 struct mlx5_flow_spec *spec, u8 *match_prio,
728 struct netlink_ext_ack *extack)
106be53b
OG		 729{
730 void *headers_c, *headers_v;
731 u8 prio_val, prio_mask = 0;
732 bool vlan_present;
733
734#ifdef CONFIG_MLX5_CORE_EN_DCB
735 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 736 NL_SET_ERR_MSG_MOD(extack,
737 "only PCP trust state supported for hairpin");
106be53b
OG		 738 return -EOPNOTSUPP;
739 }
740#endif
741 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
742 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
743
744 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
745 if (vlan_present) {
746 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
747 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
748 }
749
750 if (!vlan_present || !prio_mask) {
751 prio_val = UNKNOWN_MATCH_PRIO;
752 } else if (prio_mask != 0x7) {
e98bedf5
EB		 753 NL_SET_ERR_MSG_MOD(extack,
754 "masked priority match not supported for hairpin");
106be53b
OG		 755 return -EOPNOTSUPP;
756 }
757
758 *match_prio = prio_val;
759 return 0;
760}
761
5c65c564
OG		 762static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
763 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 764 struct mlx5e_tc_flow_parse_attr *parse_attr,
765 struct netlink_ext_ack *extack)
5c65c564 766{
98b66cb1 767 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 768 struct mlx5_hairpin_params params;
d8822868 769 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 770 struct mlx5e_hairpin_entry *hpe;
771 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 772 u64 link_speed64;
773 u32 link_speed;
106be53b 774 u8 match_prio;
d8822868 775 u16 peer_id;
5c65c564
OG		 776 int err;
777
d8822868
OG		 778 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
779 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 780 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 781 return -EOPNOTSUPP;
782 }
783
d8822868 784 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 785 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
786 extack);
106be53b
OG		 787 if (err)
788 return err;
b32accda
VB		 789
790 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 791 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 792 if (hpe) {
793 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
794 wait_for_completion(&hpe->res_ready);
795
796 if (IS_ERR(hpe->hp)) {
797 err = -EREMOTEIO;
798 goto out_err;
799 }
5c65c564 800 goto attach_flow;
db76ca24 801 }
5c65c564
OG		 802
803 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 804 if (!hpe) {
db76ca24
VB		 805 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
806 return -ENOMEM;
b32accda 807 }
5c65c564 808
73edca73 809 spin_lock_init(&hpe->flows_lock);
5c65c564 810 INIT_LIST_HEAD(&hpe->flows);
db76ca24 811 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 812 hpe->peer_vhca_id = peer_id;
106be53b 813 hpe->prio = match_prio;
e4f9abbd 814 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 815 init_completion(&hpe->res_ready);
816
817 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
818 hash_hairpin_info(peer_id, match_prio));
819 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 820
821 params.log_data_size = 15;
822 params.log_data_size = min_t(u8, params.log_data_size,
823 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
824 params.log_data_size = max_t(u8, params.log_data_size,
825 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 826
eb9180f7
OG		 827 params.log_num_packets = params.log_data_size -
828 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
829 params.log_num_packets = min_t(u8, params.log_num_packets,
830 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
831
832 params.q_counter = priv->q_counter;
3f6d08d1 833 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 834 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 835 link_speed = max_t(u32, link_speed, 50000);
836 link_speed64 = link_speed;
837 do_div(link_speed64, 50000);
838 params.num_channels = link_speed64;
839
5c65c564 840 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 841 hpe->hp = hp;
842 complete_all(&hpe->res_ready);
5c65c564
OG		 843 if (IS_ERR(hp)) {
844 err = PTR_ERR(hp);
db76ca24 845 goto out_err;
5c65c564
OG		 846 }
847
eb9180f7 848 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 849 hp->tirn, hp->pair->rqn[0],
850 dev_name(hp->pair->peer_mdev->device),
eb9180f7 851 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 852
5c65c564 853attach_flow:
3f6d08d1 854 if (hpe->hp->num_channels > 1) {
226f2ca3 855 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 856 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 857 } else {
c620b772 858 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 859 }
b32accda 860
e4f9abbd 861 flow->hpe = hpe;
73edca73 862 spin_lock(&hpe->flows_lock);
5c65c564 863 list_add(&flow->hairpin, &hpe->flows);
73edca73 864 spin_unlock(&hpe->flows_lock);
3f6d08d1 865
5c65c564
OG		 866 return 0;
867
db76ca24
VB		 868out_err:
869 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 870 return err;
871}
872
873static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
874 struct mlx5e_tc_flow *flow)
875{
5a7e5bcb 876 /* flow wasn't fully initialized */
e4f9abbd 877 if (!flow->hpe)
5a7e5bcb
VB		 878 return;
879
73edca73 880 spin_lock(&flow->hpe->flows_lock);
5c65c564 881 list_del(&flow->hairpin);
73edca73
VB		 882 spin_unlock(&flow->hpe->flows_lock);
883
e4f9abbd
VB		 884 mlx5e_hairpin_put(priv, flow->hpe);
885 flow->hpe = NULL;
5c65c564
OG		 886}
887
08247066
AL		 888struct mlx5_flow_handle *
889mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
890 struct mlx5_flow_spec *spec,
c620b772 891 struct mlx5_flow_attr *attr)
e8f887ac 892{
08247066 893 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 894 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 895 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 896 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 897 struct mlx5_flow_destination dest[2] = {};
66958ed9 898 struct mlx5_flow_act flow_act = {
3bc4b7bf 899 .action = attr->action,
bb0ee7dc 900 .flags = FLOW_ACT_NO_APPEND,
66958ed9 901 };
08247066 902 struct mlx5_flow_handle *rule;
c7569097 903 struct mlx5_flow_table *ft;
08247066 904 int dest_ix = 0;
e8f887ac 905
bb0ee7dc 906 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 907 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 908
aedd133d
AL		 909 if (attr->dest_ft) {
910 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
911 dest[dest_ix].ft = attr->dest_ft;
912 dest_ix++;
913 } else if (nic_attr->hairpin_ft) {
08247066 914 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 915 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 916 dest_ix++;
c620b772 917 } else if (nic_attr->hairpin_tirn) {
08247066 918 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 919 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 920 dest_ix++;
3f6d08d1
OG		 921 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
922 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 923 if (attr->dest_chain) {
924 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
925 attr->dest_chain, 1,
926 MLX5E_TC_FT_LEVEL);
927 if (IS_ERR(dest[dest_ix].ft))
928 return ERR_CAST(dest[dest_ix].ft);
929 } else {
6783f0a2 930 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 931 }
3f6d08d1 932 dest_ix++;
5c65c564 933 }
aad7e08d 934
c7569097
AL		 935 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
936 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
937 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
938
08247066 939 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 940 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 941 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 942 dest_ix++;
aad7e08d
AV		 943 }
944
08247066 945 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 946 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 947
6a064674
AL		 948 mutex_lock(&tc->t_lock);
949 if (IS_ERR_OR_NULL(tc->t)) {
950 /* Create the root table here if doesn't exist yet */
951 tc->t =
c7569097 952 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 953
954 if (IS_ERR(tc->t)) {
955 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 956 netdev_err(priv->netdev,
957 "Failed to create tc offload table\n");
c7569097
AL		 958 rule = ERR_CAST(priv->fs.tc.t);
959 goto err_ft_get;
e8f887ac 960 }
e8f887ac 961 }
08247066 962 mutex_unlock(&tc->t_lock);
e8f887ac 963
aedd133d
AL		 964 if (attr->chain || attr->prio)
965 ft = mlx5_chains_get_table(nic_chains,
966 attr->chain, attr->prio,
967 MLX5E_TC_FT_LEVEL);
968 else
969 ft = attr->ft;
970
c7569097
AL		 971 if (IS_ERR(ft)) {
972 rule = ERR_CAST(ft);
973 goto err_ft_get;
974 }
975
c620b772 976 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 977 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 978
c7569097 979 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 980 &flow_act, dest, dest_ix);
981 if (IS_ERR(rule))
c7569097 982 goto err_rule;
08247066
AL		 983
984 return rule;
c7569097
AL		 985
986err_rule:
aedd133d
AL		 987 if (attr->chain || attr->prio)
988 mlx5_chains_put_table(nic_chains,
989 attr->chain, attr->prio,
990 MLX5E_TC_FT_LEVEL);
c7569097
AL		 991err_ft_get:
992 if (attr->dest_chain)
993 mlx5_chains_put_table(nic_chains,
994 attr->dest_chain, 1,
995 MLX5E_TC_FT_LEVEL);
996
997 return ERR_CAST(rule);
08247066
AL		 998}
999
1000static int
1001mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1002 struct mlx5e_tc_flow_parse_attr *parse_attr,
1003 struct mlx5e_tc_flow *flow,
1004 struct netlink_ext_ack *extack)
1005{
c620b772 1006 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1007 struct mlx5_core_dev *dev = priv->mdev;
1008 struct mlx5_fc *counter = NULL;
1009 int err;
1010
1011 if (flow_flag_test(flow, HAIRPIN)) {
1012 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1013 if (err)
1014 return err;
1015 }
1016
1017 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1018 counter = mlx5_fc_create(dev, true);
1019 if (IS_ERR(counter))
1020 return PTR_ERR(counter);
1021
1022 attr->counter = counter;
1023 }
1024
1025 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1026 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1027 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1028 if (err)
1029 return err;
1030 }
1031
aedd133d
AL		 1032 if (flow_flag_test(flow, CT))
1033 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1034 attr, &parse_attr->mod_hdr_acts);
1035 else
1036 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1037 attr);
aad7e08d 1038
a2b7189b 1039 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1040}
1041
08247066 1042void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1043 struct mlx5_flow_handle *rule,
1044 struct mlx5_flow_attr *attr)
08247066 1045{
c7569097
AL		 1046 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1047
08247066 1048 mlx5_del_flow_rules(rule);
c7569097 1049
aedd133d
AL		 1050 if (attr->chain || attr->prio)
1051 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1052 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1053
1054 if (attr->dest_chain)
1055 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1056 MLX5E_TC_FT_LEVEL);
08247066
AL		 1057}
1058
d85cdccb
OG		 1059static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1060 struct mlx5e_tc_flow *flow)
1061{
c620b772 1062 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1063 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1064
c7569097
AL		 1065 flow_flag_clear(flow, OFFLOADED);
1066
aedd133d
AL		 1067 if (flow_flag_test(flow, CT))
1068 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1069 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1070 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1071
c7569097
AL		 1072 /* Remove root table if no rules are left to avoid
1073 * extra steering hops.
1074 */
b6fac0b4 1075 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1076 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1077 !IS_ERR_OR_NULL(tc->t)) {
1078 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1079 priv->fs.tc.t = NULL;
1080 }
b6fac0b4 1081 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1082
aedd133d
AL		 1083 kvfree(attr->parse_attr);
1084
513f8f7f 1085 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1086 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1087
aedd133d
AL		 1088 mlx5_fc_destroy(priv->mdev, attr->counter);
1089
226f2ca3 1090 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1091 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1092
1093 kfree(flow->attr);
d85cdccb
OG		 1094}
1095
0d9f9647 1096struct mlx5_flow_handle *
6d2a3ed0
OG		 1097mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1098 struct mlx5e_tc_flow *flow,
1099 struct mlx5_flow_spec *spec,
c620b772 1100 struct mlx5_flow_attr *attr)
6d2a3ed0 1101{
1ef3018f 1102 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1103 struct mlx5_flow_handle *rule;
4c3844d9 1104
89e39467
PB		 1105 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1106 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1107
1ef3018f
PB		 1108 if (flow_flag_test(flow, CT)) {
1109 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1110
69e2916e 1111 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1112 flow, spec, attr,
1ef3018f 1113 mod_hdr_acts);
f94d6389
CM		 1114#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1115 } else if (flow_flag_test(flow, SAMPLE)) {
1116 rule = mlx5_esw_sample_offload(get_sample_priv(flow->priv), spec, attr);
1117#endif
69e2916e
PB		 1118 } else {
1119 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1120 }
6d2a3ed0 1121
6d2a3ed0
OG		 1122 if (IS_ERR(rule))
1123 return rule;
1124
c620b772 1125 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1126 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1127 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1128 if (flow_flag_test(flow, CT))
1129 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1130 else
1131 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1132 return flow->rule[1];
1133 }
1134 }
1135
6d2a3ed0
OG		 1136 return rule;
1137}
1138
0d9f9647
VB		 1139void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1140 struct mlx5e_tc_flow *flow,
1141 struct mlx5_flow_attr *attr)
6d2a3ed0 1142{
226f2ca3 1143 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1144
89e39467
PB		 1145 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1146 goto offload_rule_0;
1147
4c3844d9 1148 if (flow_flag_test(flow, CT)) {
aedd133d 1149 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1150 return;
1151 }
1152
f94d6389
CM		 1153#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1154 if (flow_flag_test(flow, SAMPLE)) {
1155 mlx5_esw_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
1156 return;
1157 }
1158#endif
1159
c620b772 1160 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1161 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1162
89e39467 1163offload_rule_0:
6d2a3ed0
OG		 1164 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1165}
1166
0d9f9647 1167struct mlx5_flow_handle *
5dbe906f
PB		 1168mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1169 struct mlx5e_tc_flow *flow,
178f69b4 1170 struct mlx5_flow_spec *spec)
5dbe906f 1171{
c620b772 1172 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1173 struct mlx5_flow_handle *rule;
1174
c620b772
AL		 1175 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1176 if (!slow_attr)
1177 return ERR_PTR(-ENOMEM);
5dbe906f 1178
c620b772
AL		 1179 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1180 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1181 slow_attr->esw_attr->split_count = 0;
1182 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1183
1184 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1185 if (!IS_ERR(rule))
226f2ca3 1186 flow_flag_set(flow, SLOW);
5dbe906f 1187
c620b772
AL		 1188 kfree(slow_attr);
1189
5dbe906f
PB		 1190 return rule;
1191}
1192
0d9f9647
VB		 1193void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1194 struct mlx5e_tc_flow *flow)
5dbe906f 1195{
c620b772 1196 struct mlx5_flow_attr *slow_attr;
178f69b4 1197
c620b772 1198 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1199 if (!slow_attr) {
1200 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1201 return;
1202 }
c620b772
AL		 1203
1204 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1205 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1206 slow_attr->esw_attr->split_count = 0;
1207 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1208 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1209 flow_flag_clear(flow, SLOW);
c620b772 1210 kfree(slow_attr);
5dbe906f
PB		 1211}
1212
ad86755b
VB		 1213/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1214 * function.
1215 */
1216static void unready_flow_add(struct mlx5e_tc_flow *flow,
1217 struct list_head *unready_flows)
1218{
1219 flow_flag_set(flow, NOT_READY);
1220 list_add_tail(&flow->unready, unready_flows);
1221}
1222
1223/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1224 * function.
1225 */
1226static void unready_flow_del(struct mlx5e_tc_flow *flow)
1227{
1228 list_del(&flow->unready);
1229 flow_flag_clear(flow, NOT_READY);
1230}
1231
b4a23329
RD		 1232static void add_unready_flow(struct mlx5e_tc_flow *flow)
1233{
1234 struct mlx5_rep_uplink_priv *uplink_priv;
1235 struct mlx5e_rep_priv *rpriv;
1236 struct mlx5_eswitch *esw;
1237
1238 esw = flow->priv->mdev->priv.eswitch;
1239 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1240 uplink_priv = &rpriv->uplink_priv;
1241
ad86755b
VB		 1242 mutex_lock(&uplink_priv->unready_flows_lock);
1243 unready_flow_add(flow, &uplink_priv->unready_flows);
1244 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1245}
1246
1247static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1248{
ad86755b
VB		 1249 struct mlx5_rep_uplink_priv *uplink_priv;
1250 struct mlx5e_rep_priv *rpriv;
1251 struct mlx5_eswitch *esw;
1252
1253 esw = flow->priv->mdev->priv.eswitch;
1254 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1255 uplink_priv = &rpriv->uplink_priv;
1256
1257 mutex_lock(&uplink_priv->unready_flows_lock);
1258 unready_flow_del(flow);
1259 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1260}
1261
10742efc
VB		 1262static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1263
a508728a 1264bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1265{
1266 struct mlx5_core_dev *out_mdev, *route_mdev;
1267 struct mlx5e_priv *out_priv, *route_priv;
1268
1269 out_priv = netdev_priv(out_dev);
1270 out_mdev = out_priv->mdev;
1271 route_priv = netdev_priv(route_dev);
1272 route_mdev = route_priv->mdev;
1273
1274 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1275 route_mdev->coredev_type != MLX5_COREDEV_VF)
1276 return false;
1277
1278 return same_hw_devs(out_priv, route_priv);
1279}
1280
a508728a 1281int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1282{
1283 struct mlx5e_priv *out_priv, *route_priv;
1284 struct mlx5_core_dev *route_mdev;
1285 struct mlx5_eswitch *esw;
1286 u16 vhca_id;
1287 int err;
1288
1289 out_priv = netdev_priv(out_dev);
1290 esw = out_priv->mdev->priv.eswitch;
1291 route_priv = netdev_priv(route_dev);
1292 route_mdev = route_priv->mdev;
1293
1294 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1295 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1296 return err;
1297}
1298
c7b9038d
VB		 1299int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1300 struct mlx5e_tc_flow_parse_attr *parse_attr,
1301 struct mlx5e_tc_flow *flow)
1302{
1303 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1304 struct mlx5_modify_hdr *mod_hdr;
1305
1306 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1307 get_flow_name_space(flow),
1308 mod_hdr_acts->num_actions,
1309 mod_hdr_acts->actions);
1310 if (IS_ERR(mod_hdr))
1311 return PTR_ERR(mod_hdr);
1312
1313 WARN_ON(flow->attr->modify_hdr);
1314 flow->attr->modify_hdr = mod_hdr;
1315
1316 return 0;
1317}
1318
c83954ab 1319static int
74491de9 1320mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1321 struct mlx5e_tc_flow *flow,
1322 struct netlink_ext_ack *extack)
adb4c123
OG		 1323{
1324 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1325 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1326 struct mlx5e_tc_flow_parse_attr *parse_attr;
1327 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1328 bool vf_tun = false, encap_valid = true;
c620b772 1329 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1330 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1331 struct mlx5e_rep_priv *rpriv;
1332 struct mlx5e_priv *out_priv;
39ac237c 1333 u32 max_prio, max_chain;
0ad060ee 1334 int err = 0;
f493f155 1335 int out_index;
8b32580d 1336
84179981
PB		 1337 /* We check chain range only for tc flows.
1338 * For ft flows, we checked attr->chain was originally 0 and set it to
1339 * FDB_FT_CHAIN which is outside tc range.
1340 * See mlx5e_rep_setup_ft_cb().
1341 */
ae430332 1342 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1343 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1344 NL_SET_ERR_MSG_MOD(extack,
1345 "Requested chain is out of supported range");
8914add2
VB		 1346 err = -EOPNOTSUPP;
1347 goto err_out;
bf07aa73
PB		 1348 }
1349
ae430332 1350 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1351 if (attr->prio > max_prio) {
61644c3d
RD		 1352 NL_SET_ERR_MSG_MOD(extack,
1353 "Requested priority is out of supported range");
8914add2
VB		 1354 err = -EOPNOTSUPP;
1355 goto err_out;
bf07aa73 1356 }
e52c2802 1357
777bb800
VB		 1358 if (flow_flag_test(flow, TUN_RX)) {
1359 err = mlx5e_attach_decap_route(priv, flow);
1360 if (err)
8914add2 1361 goto err_out;
777bb800
VB		 1362 }
1363
14e6b038
EC		 1364 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1365 err = mlx5e_attach_decap(priv, flow, extack);
1366 if (err)
8914add2 1367 goto err_out;
14e6b038
EC		 1368 }
1369
c620b772
AL		 1370 parse_attr = attr->parse_attr;
1371 esw_attr = attr->esw_attr;
1372
f493f155 1373 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1374 int mirred_ifindex;
1375
c620b772 1376 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1377 continue;
1378
7040632d 1379 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1380 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1381 mirred_ifindex);
733d4f36 1382 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1383 extack, &encap_dev, &encap_valid);
1384 if (err)
8914add2 1385 goto err_out;
0ad060ee 1386
8914add2
VB		 1387 if (esw_attr->dests[out_index].flags &
1388 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1389 vf_tun = true;
3c37745e
OG		 1390 out_priv = netdev_priv(encap_dev);
1391 rpriv = out_priv->ppriv;
c620b772
AL		 1392 esw_attr->dests[out_index].rep = rpriv->rep;
1393 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1394 }
1395
8b32580d 1396 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1397 if (err)
8914add2 1398 goto err_out;
adb4c123 1399
d5a3c2b6
RD		 1400 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1401 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1402 if (vf_tun) {
1403 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1404 if (err)
1405 goto err_out;
1406 } else {
1407 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1408 if (err)
1409 goto err_out;
1410 }
d7e75a32
OG		 1411 }
1412
b8aee822 1413 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1414 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1415 if (IS_ERR(counter)) {
1416 err = PTR_ERR(counter);
1417 goto err_out;
1418 }
b8aee822
MB		 1419
1420 attr->counter = counter;
1421 }
1422
0ad060ee
RD		 1423 /* we get here if one of the following takes place:
1424 * (1) there's no error
1425 * (2) there's an encap action and we don't have valid neigh
3c37745e 1426 */
bc1d75fa 1427 if (!encap_valid)
178f69b4 1428 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1429 else
6d2a3ed0 1430 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1431
8914add2
VB		 1432 if (IS_ERR(flow->rule[0])) {
1433 err = PTR_ERR(flow->rule[0]);
1434 goto err_out;
1435 }
1436 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1437
1438 return 0;
8914add2
VB		 1439
1440err_out:
1441 flow_flag_set(flow, FAILED);
1442 return err;
aa0cbbae 1443}
d85cdccb 1444
9272e3df
YK		 1445static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1446{
c620b772 1447 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1448 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1449 spec->match_value,
1450 misc_parameters_3);
1451 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1452 headers_v,
1453 geneve_tlv_option_0_data);
1454
1455 return !!geneve_tlv_opt_0_data;
1456}
1457
d85cdccb
OG		 1458static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1459 struct mlx5e_tc_flow *flow)
1460{
1461 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1462 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1463 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1464 bool vf_tun = false;
f493f155 1465 int out_index;
d85cdccb 1466
777bb800 1467 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1468 mlx5e_put_flow_tunnel_id(flow);
1469
12a240a4 1470 if (flow_flag_test(flow, NOT_READY))
b4a23329 1471 remove_unready_flow(flow);
ef06c9ee 1472
226f2ca3
VB		 1473 if (mlx5e_is_offloaded_flow(flow)) {
1474 if (flow_flag_test(flow, SLOW))
178f69b4 1475 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1476 else
1477 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1478 }
d85cdccb 1479
9272e3df
YK		 1480 if (mlx5_flow_has_geneve_opt(flow))
1481 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1482
513f8f7f 1483 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1484
777bb800
VB		 1485 if (flow->decap_route)
1486 mlx5e_detach_decap_route(priv, flow);
1487
1488 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1489 if (esw_attr->dests[out_index].flags &
1490 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1491 vf_tun = true;
777bb800 1492 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1493 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1494 kfree(attr->parse_attr->tun_info[out_index]);
1495 }
777bb800 1496 }
d7e75a32 1497
aedd133d 1498 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1499
c7b9038d
VB		 1500 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1501 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1502 if (vf_tun && attr->modify_hdr)
1503 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1504 else
1505 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1506 }
8914add2
VB		 1507 kvfree(attr->parse_attr);
1508 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1509
1510 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1511 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1512
1513 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1514 mlx5e_detach_decap(priv, flow);
c620b772 1515
41c2fd94 1516 kfree(flow->attr->esw_attr->sample);
c620b772 1517 kfree(flow->attr);
d85cdccb
OG		 1518}
1519
0d9f9647 1520struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1521{
c620b772 1522 return flow->attr->counter;
b8aee822
MB		 1523}
1524
6a06c2f7 1525/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1526void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1527{
1528 struct mlx5e_tc_flow *flow, *tmp;
1529
1530 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1531 mlx5e_flow_put(priv, flow);
1532}
1533
04de7dda
RD		 1534static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1535{
1536 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1537
226f2ca3
VB		 1538 if (!flow_flag_test(flow, ESWITCH) ||
1539 !flow_flag_test(flow, DUP))
04de7dda
RD		 1540 return;
1541
1542 mutex_lock(&esw->offloads.peer_mutex);
1543 list_del(&flow->peer);
1544 mutex_unlock(&esw->offloads.peer_mutex);
1545
226f2ca3 1546 flow_flag_clear(flow, DUP);
04de7dda 1547
eb252c3a
RD		 1548 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1549 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1550 kfree(flow->peer_flow);
1551 }
1552
04de7dda
RD		 1553 flow->peer_flow = NULL;
1554}
1555
1556static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1557{
1558 struct mlx5_core_dev *dev = flow->priv->mdev;
1559 struct mlx5_devcom *devcom = dev->priv.devcom;
1560 struct mlx5_eswitch *peer_esw;
1561
1562 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1563 if (!peer_esw)
1564 return;
1565
1566 __mlx5e_tc_del_fdb_peer_flow(flow);
1567 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1568}
1569
e8f887ac 1570static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1571 struct mlx5e_tc_flow *flow)
e8f887ac 1572{
226f2ca3 1573 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1574 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1575 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1576 } else {
d85cdccb 1577 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1578 }
e8f887ac
AV		 1579}
1580
0a7fcb78
PB		 1581static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1582{
1583 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1584 struct flow_action *flow_action = &rule->action;
1585 const struct flow_action_entry *act;
1586 int i;
1587
1588 flow_action_for_each(i, act, flow_action) {
1589 switch (act->id) {
1590 case FLOW_ACTION_GOTO:
1591 return true;
1592 default:
1593 continue;
1594 }
1595 }
1596
1597 return false;
1598}
bbd00f7e 1599
0a7fcb78
PB		 1600static int
1601enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1602 struct flow_dissector_key_enc_opts *opts,
1603 struct netlink_ext_ack *extack,
1604 bool *dont_care)
1605{
1606 struct geneve_opt *opt;
1607 int off = 0;
1608
1609 *dont_care = true;
1610
1611 while (opts->len > off) {
1612 opt = (struct geneve_opt *)&opts->data[off];
1613
1614 if (!(*dont_care) || opt->opt_class || opt->type ||
1615 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1616 *dont_care = false;
1617
c51323ee 1618 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1619 opt->type != U8_MAX) {
0a7fcb78
PB		 1620 NL_SET_ERR_MSG(extack,
1621 "Partial match of tunnel options in chain > 0 isn't supported");
1622 netdev_warn(priv->netdev,
1623 "Partial match of tunnel options in chain > 0 isn't supported");
1624 return -EOPNOTSUPP;
1625 }
1626 }
1627
1628 off += sizeof(struct geneve_opt) + opt->length * 4;
1629 }
1630
1631 return 0;
1632}
1633
1634#define COPY_DISSECTOR(rule, diss_key, dst)\
1635({ \
1636 struct flow_rule *__rule = (rule);\
1637 typeof(dst) __dst = dst;\
1638\
1639 memcpy(__dst,\
1640 skb_flow_dissector_target(__rule->match.dissector,\
1641 diss_key,\
1642 __rule->match.key),\
1643 sizeof(*__dst));\
1644})
1645
1646static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1647 struct mlx5e_tc_flow *flow,
1648 struct flow_cls_offload *f,
1649 struct net_device *filter_dev)
bbd00f7e 1650{
f9e30088 1651 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1652 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1653 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1654 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1655 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1656 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1657 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1658 struct mlx5e_rep_priv *uplink_rpriv;
1659 struct tunnel_match_key tunnel_key;
1660 bool enc_opts_is_dont_care = true;
1661 u32 tun_id, enc_opts_id = 0;
1662 struct mlx5_eswitch *esw;
1663 u32 value, mask;
8f256622 1664 int err;
2e72eb43 1665
0a7fcb78
PB		 1666 esw = priv->mdev->priv.eswitch;
1667 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1668 uplink_priv = &uplink_rpriv->uplink_priv;
1669
1670 memset(&tunnel_key, 0, sizeof(tunnel_key));
1671 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1672 &tunnel_key.enc_control);
1673 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1674 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1675 &tunnel_key.enc_ipv4);
1676 else
1677 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1678 &tunnel_key.enc_ipv6);
1679 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1680 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1681 &tunnel_key.enc_tp);
1682 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1683 &tunnel_key.enc_key_id);
1684 tunnel_key.filter_ifindex = filter_dev->ifindex;
1685
1686 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1687 if (err)
101f4de9 1688 return err;
bbd00f7e 1689
0a7fcb78
PB		 1690 flow_rule_match_enc_opts(rule, &enc_opts_match);
1691 err = enc_opts_is_dont_care_or_full_match(priv,
1692 enc_opts_match.mask,
1693 extack,
1694 &enc_opts_is_dont_care);
1695 if (err)
1696 goto err_enc_opts;
fe1587a7 1697
0a7fcb78 1698 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1699 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1700 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1701 sizeof(*enc_opts_match.key));
1702 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1703 sizeof(*enc_opts_match.mask));
1704
0a7fcb78 1705 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1706 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1707 if (err)
1708 goto err_enc_opts;
1709 }
fe1587a7 1710
0a7fcb78
PB		 1711 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1712 mask = enc_opts_id ? TUNNEL_ID_MASK :
1713 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1714
0a7fcb78
PB		 1715 if (attr->chain) {
1716 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1717 TUNNEL_TO_REG, value, mask);
1718 } else {
1719 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1720 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1721 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1722 TUNNEL_TO_REG, value);
1723 if (err)
1724 goto err_set;
fe1587a7 1725
0a7fcb78 1726 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1727 }
bbd00f7e 1728
0a7fcb78
PB		 1729 flow->tunnel_id = value;
1730 return 0;
bcef735c 1731
0a7fcb78
PB		 1732err_set:
1733 if (enc_opts_id)
1734 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1735 enc_opts_id);
1736err_enc_opts:
1737 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1738 return err;
1739}
bcef735c 1740
0a7fcb78
PB		 1741static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1742{
1743 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1744 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1745 struct mlx5_rep_uplink_priv *uplink_priv;
1746 struct mlx5e_rep_priv *uplink_rpriv;
1747 struct mlx5_eswitch *esw;
bcef735c 1748
0a7fcb78
PB		 1749 esw = flow->priv->mdev->priv.eswitch;
1750 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1751 uplink_priv = &uplink_rpriv->uplink_priv;
1752
1753 if (tun_id)
1754 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1755 if (enc_opts_id)
1756 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1757 enc_opts_id);
1758}
e98bedf5 1759
4c3844d9
PB		 1760u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1761{
1762 return flow->tunnel_id;
1763}
1764
fca53304
EB		 1765void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1766 struct flow_match_basic *match, bool outer,
1767 void *headers_c, void *headers_v)
1768{
1769 bool ip_version_cap;
1770
1771 ip_version_cap = outer ?
1772 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1773 ft_field_support.outer_ip_version) :
1774 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1775 ft_field_support.inner_ip_version);
1776
1777 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1778 (match->key->n_proto == htons(ETH_P_IP) ||
1779 match->key->n_proto == htons(ETH_P_IPV6))) {
1780 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1781 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1782 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1783 } else {
1784 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1785 ntohs(match->mask->n_proto));
1786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1787 ntohs(match->key->n_proto));
1788 }
4a5d5d73
EB		 1789}
1790
0d9f9647 1791u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1792{
1793 void *headers_v;
1794 u16 ethertype;
1795 u8 ip_version;
1796
1797 if (outer)
1798 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1799 else
1800 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1801
1802 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1803 /* Return ip_version converted from ethertype anyway */
1804 if (!ip_version) {
1805 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1806 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1807 ip_version = 4;
1808 else if (ethertype == ETH_P_IPV6)
1809 ip_version = 6;
1810 }
1811 return ip_version;
1812}
1813
bbd00f7e 1814static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1815 struct mlx5e_tc_flow *flow,
bbd00f7e 1816 struct mlx5_flow_spec *spec,
f9e30088 1817 struct flow_cls_offload *f,
0a7fcb78
PB		 1818 struct net_device *filter_dev,
1819 u8 *match_level,
1820 bool *match_inner)
bbd00f7e 1821{
a508728a 1822 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1823 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1824 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1825 bool needs_mapping, sets_mapping;
8f256622 1826 int err;
2e72eb43 1827
0a7fcb78
PB		 1828 if (!mlx5e_is_eswitch_flow(flow))
1829 return -EOPNOTSUPP;
1830
c620b772
AL		 1831 needs_mapping = !!flow->attr->chain;
1832 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 1833 *match_inner = !needs_mapping;
1834
1835 if ((needs_mapping || sets_mapping) &&
636bb968 1836 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1837 NL_SET_ERR_MSG(extack,
636bb968 1838 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1839 netdev_warn(priv->netdev,
636bb968 1840 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1841 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1842 }
1843
c620b772 1844 if (!flow->attr->chain) {
0a7fcb78
PB		 1845 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1846 match_level);
1847 if (err) {
e98bedf5 1848 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1849 "Failed to parse tunnel attributes");
1850 netdev_warn(priv->netdev,
1851 "Failed to parse tunnel attributes");
1852 return err;
e98bedf5
EB		 1853 }
1854
14e6b038
EC		 1855 /* With mpls over udp we decapsulate using packet reformat
1856 * object
1857 */
1858 if (!netif_is_bareudp(filter_dev))
c620b772 1859 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1860 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1861 if (err)
1862 return err;
1863 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1864 struct mlx5_flow_spec *tmp_spec;
1865
1866 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1867 if (!tmp_spec) {
1868 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1869 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1870 return -ENOMEM;
1871 }
1872 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1873
1874 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1875 if (err) {
1876 kvfree(tmp_spec);
1877 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1878 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1879 return err;
1880 }
1881 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1882 kvfree(tmp_spec);
1883 if (err)
1884 return err;
bcef735c
OG		 1885 }
1886
0a7fcb78
PB		 1887 if (!needs_mapping && !sets_mapping)
1888 return 0;
bbd00f7e 1889
0a7fcb78 1890 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1891}
bbd00f7e 1892
0a7fcb78 1893static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1894{
0a7fcb78
PB		 1895 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1896 inner_headers);
bbd00f7e
HHZ		 1897}
1898
0a7fcb78 1899static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1900{
0a7fcb78
PB		 1901 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1902 inner_headers);
1903}
1904
1905static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1906{
1907 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1908 outer_headers);
1909}
1910
1911static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1912{
1913 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1914 outer_headers);
8377629e
EB		 1915}
1916
1917static void *get_match_headers_value(u32 flags,
1918 struct mlx5_flow_spec *spec)
1919{
1920 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1921 get_match_inner_headers_value(spec) :
1922 get_match_outer_headers_value(spec);
1923}
1924
1925static void *get_match_headers_criteria(u32 flags,
1926 struct mlx5_flow_spec *spec)
1927{
1928 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1929 get_match_inner_headers_criteria(spec) :
1930 get_match_outer_headers_criteria(spec);
8377629e
EB		 1931}
1932
6d65bc64 1933static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1934 struct flow_cls_offload *f)
1935{
1936 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1937 struct netlink_ext_ack *extack = f->common.extack;
1938 struct net_device *ingress_dev;
1939 struct flow_match_meta match;
1940
1941 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1942 return 0;
1943
1944 flow_rule_match_meta(rule, &match);
e3e0f9b2 1945 if (!match.mask->ingress_ifindex)
1946 return 0;
1947
6d65bc64 1948 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1949 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 1950 return -EOPNOTSUPP;
6d65bc64 1951 }
1952
1953 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1954 match.key->ingress_ifindex);
1955 if (!ingress_dev) {
1956 NL_SET_ERR_MSG_MOD(extack,
1957 "Can't find the ingress port to match on");
a683012a 1958 return -ENOENT;
6d65bc64 1959 }
1960
1961 if (ingress_dev != filter_dev) {
1962 NL_SET_ERR_MSG_MOD(extack,
1963 "Can't match on the ingress filter port");
a683012a 1964 return -EOPNOTSUPP;
6d65bc64 1965 }
1966
1967 return 0;
1968}
1969
72046a91
EC		 1970static bool skip_key_basic(struct net_device *filter_dev,
1971 struct flow_cls_offload *f)
1972{
1973 /* When doing mpls over udp decap, the user needs to provide
1974 * MPLS_UC as the protocol in order to be able to match on mpls
1975 * label fields. However, the actual ethertype is IP so we want to
1976 * avoid matching on this, otherwise we'll fail the match.
1977 */
1978 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
1979 return true;
1980
1981 return false;
1982}
1983
de0af0bf 1984static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 1985 struct mlx5e_tc_flow *flow,
de0af0bf 1986 struct mlx5_flow_spec *spec,
f9e30088 1987 struct flow_cls_offload *f,
54c177ca 1988 struct net_device *filter_dev,
93b3586e 1989 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 1990{
e98bedf5 1991 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1992 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1993 outer_headers);
1994 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1995 outer_headers);
699e96dd
JL		 1996 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1997 misc_parameters);
1998 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1999 misc_parameters);
a3222a2d
MD		 2000 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2001 misc_parameters_3);
2002 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2003 misc_parameters_3);
f9e30088 2004 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2005 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2006 u16 addr_type = 0;
2007 u8 ip_proto = 0;
93b3586e 2008 u8 *match_level;
6d65bc64 2009 int err;
e3a2b7ed 2010
93b3586e 2011 match_level = outer_match_level;
de0af0bf 2012
8f256622 2013 if (dissector->used_keys &
3d144578
VB		 2014 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2015 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2016 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2017 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2018 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2019 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2020 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2021 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2022 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2023 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2024 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2025 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2026 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2027 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2028 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2029 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2030 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2031 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2032 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2033 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2034 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2035 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2036 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2037 dissector->used_keys);
e3a2b7ed
AV		 2038 return -EOPNOTSUPP;
2039 }
2040
075973c7 2041 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2042 bool match_inner = false;
bbd00f7e 2043
0a7fcb78
PB		 2044 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2045 outer_match_level, &match_inner);
2046 if (err)
2047 return err;
2048
2049 if (match_inner) {
2050 /* header pointers should point to the inner headers
2051 * if the packet was decapsulated already.
2052 * outer headers are set by parse_tunnel_attr.
2053 */
2054 match_level = inner_match_level;
2055 headers_c = get_match_inner_headers_criteria(spec);
2056 headers_v = get_match_inner_headers_value(spec);
2057 }
bbd00f7e
HHZ		 2058 }
2059
6d65bc64 2060 err = mlx5e_flower_parse_meta(filter_dev, f);
2061 if (err)
2062 return err;
2063
72046a91
EC		 2064 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2065 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2066 struct flow_match_basic match;
2067
2068 flow_rule_match_basic(rule, &match);
fca53304
EB		 2069 mlx5e_tc_set_ethertype(priv->mdev, &match,
2070 match_level == outer_match_level,
2071 headers_c, headers_v);
e3a2b7ed 2072
8f256622 2073 if (match.mask->n_proto)
d708f902 2074 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2075 }
35a605db
EB		 2076 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2077 is_vlan_dev(filter_dev)) {
2078 struct flow_dissector_key_vlan filter_dev_mask;
2079 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2080 struct flow_match_vlan match;
2081
35a605db
EB		 2082 if (is_vlan_dev(filter_dev)) {
2083 match.key = &filter_dev_key;
2084 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2085 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2086 match.key->vlan_priority = 0;
2087 match.mask = &filter_dev_mask;
2088 memset(match.mask, 0xff, sizeof(*match.mask));
2089 match.mask->vlan_priority = 0;
2090 } else {
2091 flow_rule_match_vlan(rule, &match);
2092 }
8f256622
PNA		 2093 if (match.mask->vlan_id ||
2094 match.mask->vlan_priority ||
2095 match.mask->vlan_tpid) {
2096 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2097 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2098 svlan_tag, 1);
2099 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2100 svlan_tag, 1);
2101 } else {
2102 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2103 cvlan_tag, 1);
2104 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2105 cvlan_tag, 1);
2106 }
095b6cfd 2107
8f256622
PNA		 2108 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2109 match.mask->vlan_id);
2110 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2111 match.key->vlan_id);
358d79a4 2112
8f256622
PNA		 2113 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2114 match.mask->vlan_priority);
2115 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2116 match.key->vlan_priority);
54782900 2117
d708f902 2118 *match_level = MLX5_MATCH_L2;
54782900 2119 }
d3a80bb5 2120 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2121 /* cvlan_tag enabled in match criteria and
2122 * disabled in match value means both S & C tags
2123 * don't exist (untagged of both)
2124 */
cee26487 2125 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2126 *match_level = MLX5_MATCH_L2;
54782900
OG		 2127 }
2128
8f256622
PNA		 2129 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2130 struct flow_match_vlan match;
2131
12d5cbf8 2132 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2133 if (match.mask->vlan_id ||
2134 match.mask->vlan_priority ||
2135 match.mask->vlan_tpid) {
2136 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2137 MLX5_SET(fte_match_set_misc, misc_c,
2138 outer_second_svlan_tag, 1);
2139 MLX5_SET(fte_match_set_misc, misc_v,
2140 outer_second_svlan_tag, 1);
2141 } else {
2142 MLX5_SET(fte_match_set_misc, misc_c,
2143 outer_second_cvlan_tag, 1);
2144 MLX5_SET(fte_match_set_misc, misc_v,
2145 outer_second_cvlan_tag, 1);
2146 }
2147
2148 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2149 match.mask->vlan_id);
699e96dd 2150 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2151 match.key->vlan_id);
699e96dd 2152 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2153 match.mask->vlan_priority);
699e96dd 2154 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2155 match.key->vlan_priority);
699e96dd
JL		 2156
2157 *match_level = MLX5_MATCH_L2;
0faddfe6 2158 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2159 }
2160 }
2161
8f256622
PNA		 2162 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2163 struct flow_match_eth_addrs match;
54782900 2164
8f256622 2165 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2166 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2167 dmac_47_16),
8f256622 2168 match.mask->dst);
d3a80bb5
OG		 2169 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2170 dmac_47_16),
8f256622 2171 match.key->dst);
d3a80bb5
OG		 2172
2173 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2174 smac_47_16),
8f256622 2175 match.mask->src);
d3a80bb5
OG		 2176 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2177 smac_47_16),
8f256622 2178 match.key->src);
d3a80bb5 2179
8f256622
PNA		 2180 if (!is_zero_ether_addr(match.mask->src) ||
2181 !is_zero_ether_addr(match.mask->dst))
d708f902 2182 *match_level = MLX5_MATCH_L2;
54782900
OG		 2183 }
2184
8f256622
PNA		 2185 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2186 struct flow_match_control match;
54782900 2187
8f256622
PNA		 2188 flow_rule_match_control(rule, &match);
2189 addr_type = match.key->addr_type;
54782900
OG		 2190
2191 /* the HW doesn't support frag first/later */
8f256622 2192 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2193 return -EOPNOTSUPP;
2194
8f256622 2195 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2196 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2197 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2198 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2199
2200 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2201 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2202 *match_level = MLX5_MATCH_L2;
54782900
OG		 2203 /* *** L2 attributes parsing up to here *** */
2204 else
83621b7d 2205 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2206 }
2207 }
2208
8f256622
PNA		 2209 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2210 struct flow_match_basic match;
2211
2212 flow_rule_match_basic(rule, &match);
2213 ip_proto = match.key->ip_proto;
54782900
OG		 2214
2215 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2216 match.mask->ip_proto);
54782900 2217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2218 match.key->ip_proto);
54782900 2219
8f256622 2220 if (match.mask->ip_proto)
d708f902 2221 *match_level = MLX5_MATCH_L3;
54782900
OG		 2222 }
2223
e3a2b7ed 2224 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2225 struct flow_match_ipv4_addrs match;
e3a2b7ed 2226
8f256622 2227 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2228 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2229 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2230 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2231 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2232 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2233 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2234 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2235 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2236 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2237 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2238 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2239 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2240
8f256622 2241 if (match.mask->src || match.mask->dst)
d708f902 2242 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2243 }
2244
2245 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2246 struct flow_match_ipv6_addrs match;
e3a2b7ed 2247
8f256622 2248 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2249 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2250 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2251 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2252 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2253 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2254 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2255
2256 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2257 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2258 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2259 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2260 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2261 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2262
8f256622
PNA		 2263 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2264 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2265 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2266 }
2267
8f256622
PNA		 2268 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2269 struct flow_match_ip match;
1f97a526 2270
8f256622
PNA		 2271 flow_rule_match_ip(rule, &match);
2272 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2273 match.mask->tos & 0x3);
2274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2275 match.key->tos & 0x3);
1f97a526 2276
8f256622
PNA		 2277 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2278 match.mask->tos >> 2);
2279 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2280 match.key->tos >> 2);
1f97a526 2281
8f256622
PNA		 2282 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2283 match.mask->ttl);
2284 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2285 match.key->ttl);
1f97a526 2286
8f256622 2287 if (match.mask->ttl &&
a8ade55f 2288 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2289 ft_field_support.outer_ipv4_ttl)) {
2290 NL_SET_ERR_MSG_MOD(extack,
2291 "Matching on TTL is not supported");
1f97a526 2292 return -EOPNOTSUPP;
e98bedf5 2293 }
a8ade55f 2294
8f256622 2295 if (match.mask->tos || match.mask->ttl)
d708f902 2296 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2297 }
2298
54782900
OG		 2299 /* *** L3 attributes parsing up to here *** */
2300
8f256622
PNA		 2301 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2302 struct flow_match_ports match;
2303
2304 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2305 switch (ip_proto) {
2306 case IPPROTO_TCP:
2307 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2308 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2309 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2310 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2311
2312 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2313 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2314 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2315 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2316 break;
2317
2318 case IPPROTO_UDP:
2319 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2320 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2321 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2322 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2323
2324 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2325 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2326 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2327 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2328 break;
2329 default:
e98bedf5
EB		 2330 NL_SET_ERR_MSG_MOD(extack,
2331 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2332 netdev_err(priv->netdev,
2333 "Only UDP and TCP transport are supported\n");
2334 return -EINVAL;
2335 }
de0af0bf 2336
8f256622 2337 if (match.mask->src || match.mask->dst)
d708f902 2338 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2339 }
2340
8f256622
PNA		 2341 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2342 struct flow_match_tcp match;
e77834ec 2343
8f256622 2344 flow_rule_match_tcp(rule, &match);
e77834ec 2345 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2346 ntohs(match.mask->flags));
e77834ec 2347 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2348 ntohs(match.key->flags));
e77834ec 2349
8f256622 2350 if (match.mask->flags)
d708f902 2351 *match_level = MLX5_MATCH_L4;
e77834ec 2352 }
a3222a2d
MD		 2353 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2354 struct flow_match_icmp match;
e77834ec 2355
a3222a2d
MD		 2356 flow_rule_match_icmp(rule, &match);
2357 switch (ip_proto) {
2358 case IPPROTO_ICMP:
2359 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2360 MLX5_FLEX_PROTO_ICMP))
2361 return -EOPNOTSUPP;
2362 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2363 match.mask->type);
2364 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2365 match.key->type);
2366 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2367 match.mask->code);
2368 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2369 match.key->code);
2370 break;
2371 case IPPROTO_ICMPV6:
2372 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2373 MLX5_FLEX_PROTO_ICMPV6))
2374 return -EOPNOTSUPP;
2375 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2376 match.mask->type);
2377 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2378 match.key->type);
2379 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2380 match.mask->code);
2381 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2382 match.key->code);
2383 break;
2384 default:
2385 NL_SET_ERR_MSG_MOD(extack,
2386 "Code and type matching only with ICMP and ICMPv6");
2387 netdev_err(priv->netdev,
2388 "Code and type matching only with ICMP and ICMPv6\n");
2389 return -EINVAL;
2390 }
2391 if (match.mask->code || match.mask->type) {
2392 *match_level = MLX5_MATCH_L4;
2393 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2394 }
2395 }
7d6c86e3
AH		 2396 /* Currenlty supported only for MPLS over UDP */
2397 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2398 !netif_is_bareudp(filter_dev)) {
2399 NL_SET_ERR_MSG_MOD(extack,
2400 "Matching on MPLS is supported only for MPLS over UDP");
2401 netdev_err(priv->netdev,
2402 "Matching on MPLS is supported only for MPLS over UDP\n");
2403 return -EOPNOTSUPP;
2404 }
2405
e3a2b7ed
AV		 2406 return 0;
2407}
2408
de0af0bf 2409static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2410 struct mlx5e_tc_flow *flow,
de0af0bf 2411 struct mlx5_flow_spec *spec,
f9e30088 2412 struct flow_cls_offload *f,
54c177ca 2413 struct net_device *filter_dev)
de0af0bf 2414{
93b3586e 2415 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2416 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2417 struct mlx5_core_dev *dev = priv->mdev;
2418 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2419 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2420 struct mlx5_eswitch_rep *rep;
226f2ca3 2421 bool is_eswitch_flow;
de0af0bf
RD		 2422 int err;
2423
93b3586e
HN		 2424 inner_match_level = MLX5_MATCH_NONE;
2425 outer_match_level = MLX5_MATCH_NONE;
2426
0a7fcb78
PB		 2427 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2428 &inner_match_level, &outer_match_level);
93b3586e
HN		 2429 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2430 outer_match_level : inner_match_level;
de0af0bf 2431
226f2ca3
VB		 2432 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2433 if (!err && is_eswitch_flow) {
1d447a39 2434 rep = rpriv->rep;
b05af6aa 2435 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2436 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2437 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2438 NL_SET_ERR_MSG_MOD(extack,
2439 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2440 netdev_warn(priv->netdev,
2441 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2442 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2443 return -EOPNOTSUPP;
2444 }
2445 }
2446
c620b772
AL		 2447 flow->attr->inner_match_level = inner_match_level;
2448 flow->attr->outer_match_level = outer_match_level;
2449
38aa51c1 2450
de0af0bf
RD		 2451 return err;
2452}
2453
d79b6df6
OG		 2454struct pedit_headers {
2455 struct ethhdr eth;
0eb69bb9 2456 struct vlan_hdr vlan;
d79b6df6
OG		 2457 struct iphdr ip4;
2458 struct ipv6hdr ip6;
2459 struct tcphdr tcp;
2460 struct udphdr udp;
2461};
2462
c500c86b
PNA		 2463struct pedit_headers_action {
2464 struct pedit_headers vals;
2465 struct pedit_headers masks;
2466 u32 pedits;
2467};
2468
d79b6df6 2469static int pedit_header_offsets[] = {
73867881
PNA		 2470 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2471 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2472 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2473 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2474 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2475};
2476
2477#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2478
2479static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2480 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2481{
2482 u32 *curr_pmask, *curr_pval;
2483
c500c86b
PNA		 2484 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2485 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2486
2487 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2488 goto out_err;
2489
2490 *curr_pmask |= mask;
2491 *curr_pval |= (val & mask);
2492
2493 return 0;
2494
2495out_err:
2496 return -EOPNOTSUPP;
2497}
2498
2499struct mlx5_fields {
2500 u8 field;
88f30bbc
DL		 2501 u8 field_bsize;
2502 u32 field_mask;
d79b6df6 2503 u32 offset;
27c11b6b 2504 u32 match_offset;
d79b6df6
OG		 2505};
2506
88f30bbc
DL		 2507#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2508 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2509 offsetof(struct pedit_headers, field) + (off), \
2510 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2511
2ef86872
EB		 2512/* masked values are the same and there are no rewrites that do not have a
2513 * match.
2514 */
2515#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2516 type matchmaskx = *(type *)(matchmaskp); \
2517 type matchvalx = *(type *)(matchvalp); \
2518 type maskx = *(type *)(maskp); \
2519 type valx = *(type *)(valp); \
2520 \
2521 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2522 matchmaskx)); \
2523})
2524
27c11b6b 2525static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2526 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2527{
2528 bool same = false;
2529
88f30bbc
DL		 2530 switch (bsize) {
2531 case 8:
2ef86872 2532 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2533 break;
88f30bbc 2534 case 16:
2ef86872 2535 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2536 break;
88f30bbc 2537 case 32:
2ef86872 2538 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2539 break;
2540 }
2541
2542 return same;
2543}
a8e4f0c4 2544
d79b6df6 2545static struct mlx5_fields fields[] = {
88f30bbc
DL		 2546 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2547 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2548 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2549 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2550 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2551 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2552
ab9341b5 2553 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2554 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2555 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2556 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2557
2558 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2559 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2560 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2561 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2562 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2563 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2564 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2565 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2566 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2567 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2568 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2569 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2570 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2571 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2572 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2573 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2574 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2575 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2576
88f30bbc
DL		 2577 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2578 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2579 /* in linux iphdr tcp_flags is 8 bits long */
2580 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2581
88f30bbc
DL		 2582 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2583 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2584};
2585
82198d8b
MD		 2586static unsigned long mask_to_le(unsigned long mask, int size)
2587{
2588 __be32 mask_be32;
2589 __be16 mask_be16;
2590
2591 if (size == 32) {
2592 mask_be32 = (__force __be32)(mask);
2593 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2594 } else if (size == 16) {
2595 mask_be32 = (__force __be32)(mask);
2596 mask_be16 = *(__be16 *)&mask_be32;
2597 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2598 }
2599
2600 return mask;
2601}
6ae4a6a5
PB		 2602static int offload_pedit_fields(struct mlx5e_priv *priv,
2603 int namespace,
2604 struct pedit_headers_action *hdrs,
e98bedf5 2605 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2606 u32 *action_flags,
e98bedf5 2607 struct netlink_ext_ack *extack)
d79b6df6
OG		 2608{
2609 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2610 int i, action_size, first, last, next_z;
88f30bbc
DL		 2611 void *headers_c, *headers_v, *action, *vals_p;
2612 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2613 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2614 struct mlx5_fields *f;
82198d8b 2615 unsigned long mask, field_mask;
6ae4a6a5 2616 int err;
88f30bbc
DL		 2617 u8 cmd;
2618
6ae4a6a5 2619 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2620 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2621 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2622
73867881
PNA		 2623 set_masks = &hdrs[0].masks;
2624 add_masks = &hdrs[1].masks;
2625 set_vals = &hdrs[0].vals;
2626 add_vals = &hdrs[1].vals;
d79b6df6 2627
d65dbedf 2628 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2629
2630 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2631 bool skip;
2632
d79b6df6
OG		 2633 f = &fields[i];
2634 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2635 s_mask = 0;
2636 a_mask = 0;
d79b6df6
OG		 2637
2638 s_masks_p = (void *)set_masks + f->offset;
2639 a_masks_p = (void *)add_masks + f->offset;
2640
88f30bbc
DL		 2641 s_mask = *s_masks_p & f->field_mask;
2642 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2643
2644 if (!s_mask && !a_mask) /* nothing to offload here */
2645 continue;
2646
2647 if (s_mask && a_mask) {
e98bedf5
EB		 2648 NL_SET_ERR_MSG_MOD(extack,
2649 "can't set and add to the same HW field");
d79b6df6
OG		 2650 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2651 return -EOPNOTSUPP;
2652 }
2653
27c11b6b 2654 skip = false;
d79b6df6 2655 if (s_mask) {
27c11b6b
EB		 2656 void *match_mask = headers_c + f->match_offset;
2657 void *match_val = headers_v + f->match_offset;
2658
d79b6df6
OG		 2659 cmd = MLX5_ACTION_TYPE_SET;
2660 mask = s_mask;
2661 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2662 /* don't rewrite if we have a match on the same value */
2663 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2664 match_mask, f->field_bsize))
27c11b6b 2665 skip = true;
d79b6df6 2666 /* clear to denote we consumed this field */
88f30bbc 2667 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2668 } else {
2669 cmd = MLX5_ACTION_TYPE_ADD;
2670 mask = a_mask;
2671 vals_p = (void *)add_vals + f->offset;
27c11b6b 2672 /* add 0 is no change */
88f30bbc 2673 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2674 skip = true;
d79b6df6 2675 /* clear to denote we consumed this field */
88f30bbc 2676 *a_masks_p &= ~f->field_mask;
d79b6df6 2677 }
27c11b6b
EB		 2678 if (skip)
2679 continue;
d79b6df6 2680
82198d8b 2681 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2682
88f30bbc
DL		 2683 first = find_first_bit(&mask, f->field_bsize);
2684 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2685 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2686 if (first < next_z && next_z < last) {
e98bedf5
EB		 2687 NL_SET_ERR_MSG_MOD(extack,
2688 "rewrite of few sub-fields isn't supported");
2b64beba 2689 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2690 mask);
2691 return -EOPNOTSUPP;
2692 }
2693
6ae4a6a5
PB		 2694 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2695 if (err) {
2696 NL_SET_ERR_MSG_MOD(extack,
2697 "too many pedit actions, can't offload");
2698 mlx5_core_warn(priv->mdev,
2699 "mlx5: parsed %d pedit actions, can't do more\n",
2700 mod_acts->num_actions);
2701 return err;
2702 }
2703
2704 action = mod_acts->actions +
2705 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2706 MLX5_SET(set_action_in, action, action_type, cmd);
2707 MLX5_SET(set_action_in, action, field, f->field);
2708
2709 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2710 int start;
2711
82198d8b
MD		 2712 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2713
88f30bbc 2714 /* if field is bit sized it can start not from first bit */
82198d8b 2715 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2716
2717 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2718 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2719 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2720 }
2721
88f30bbc 2722 if (f->field_bsize == 32)
2b64beba 2723 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2724 else if (f->field_bsize == 16)
2b64beba 2725 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2726 else if (f->field_bsize == 8)
2b64beba 2727 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2728
6ae4a6a5 2729 ++mod_acts->num_actions;
d79b6df6
OG		 2730 }
2731
d79b6df6
OG		 2732 return 0;
2733}
2734
2cc1cb1d
TZ		 2735static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2736 int namespace)
2737{
2738 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2739 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2740 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2741 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2742}
2743
6ae4a6a5
PB		 2744int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2745 int namespace,
2746 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2747{
6ae4a6a5
PB		 2748 int action_size, new_num_actions, max_hw_actions;
2749 size_t new_sz, old_sz;
2750 void *ret;
d79b6df6 2751
6ae4a6a5
PB		 2752 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2753 return 0;
d79b6df6 2754
d65dbedf 2755 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2756
6ae4a6a5
PB		 2757 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2758 namespace);
2759 new_num_actions = min(max_hw_actions,
2760 mod_hdr_acts->actions ?
2761 mod_hdr_acts->max_actions * 2 : 1);
2762 if (mod_hdr_acts->max_actions == new_num_actions)
2763 return -ENOSPC;
2764
2765 new_sz = action_size * new_num_actions;
2766 old_sz = mod_hdr_acts->max_actions * action_size;
2767 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2768 if (!ret)
d79b6df6
OG		 2769 return -ENOMEM;
2770
6ae4a6a5
PB		 2771 memset(ret + old_sz, 0, new_sz - old_sz);
2772 mod_hdr_acts->actions = ret;
2773 mod_hdr_acts->max_actions = new_num_actions;
2774
d79b6df6
OG		 2775 return 0;
2776}
2777
6ae4a6a5
PB		 2778void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2779{
2780 kfree(mod_hdr_acts->actions);
2781 mod_hdr_acts->actions = NULL;
2782 mod_hdr_acts->num_actions = 0;
2783 mod_hdr_acts->max_actions = 0;
2784}
2785
d79b6df6
OG		 2786static const struct pedit_headers zero_masks = {};
2787
582234b4
EC		 2788static int
2789parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2790 const struct flow_action_entry *act, int namespace,
2791 struct mlx5e_tc_flow_parse_attr *parse_attr,
2792 struct pedit_headers_action *hdrs,
2793 struct netlink_ext_ack *extack)
d79b6df6 2794{
73867881
PNA		 2795 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2796 int err = -EOPNOTSUPP;
d79b6df6 2797 u32 mask, val, offset;
73867881 2798 u8 htype;
d79b6df6 2799
73867881
PNA		 2800 htype = act->mangle.htype;
2801 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2802
73867881
PNA		 2803 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2804 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2805 goto out_err;
2806 }
d79b6df6 2807
2cc1cb1d
TZ		 2808 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2809 NL_SET_ERR_MSG_MOD(extack,
2810 "The pedit offload action is not supported");
2811 goto out_err;
2812 }
2813
73867881
PNA		 2814 mask = act->mangle.mask;
2815 val = act->mangle.val;
2816 offset = act->mangle.offset;
d79b6df6 2817
73867881
PNA		 2818 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2819 if (err)
2820 goto out_err;
c500c86b 2821
73867881 2822 hdrs[cmd].pedits++;
d79b6df6 2823
c500c86b
PNA		 2824 return 0;
2825out_err:
2826 return err;
2827}
2828
582234b4
EC		 2829static int
2830parse_pedit_to_reformat(struct mlx5e_priv *priv,
2831 const struct flow_action_entry *act,
2832 struct mlx5e_tc_flow_parse_attr *parse_attr,
2833 struct netlink_ext_ack *extack)
2834{
2835 u32 mask, val, offset;
2836 u32 *p;
2837
2838 if (act->id != FLOW_ACTION_MANGLE)
2839 return -EOPNOTSUPP;
2840
2841 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2842 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2843 return -EOPNOTSUPP;
2844 }
2845
2846 mask = ~act->mangle.mask;
2847 val = act->mangle.val;
2848 offset = act->mangle.offset;
2849 p = (u32 *)&parse_attr->eth;
2850 *(p + (offset >> 2)) |= (val & mask);
2851
2852 return 0;
2853}
2854
2855static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2856 const struct flow_action_entry *act, int namespace,
2857 struct mlx5e_tc_flow_parse_attr *parse_attr,
2858 struct pedit_headers_action *hdrs,
2859 struct mlx5e_tc_flow *flow,
2860 struct netlink_ext_ack *extack)
2861{
2862 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2863 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2864
2865 return parse_pedit_to_modify_hdr(priv, act, namespace,
2866 parse_attr, hdrs, extack);
2867}
2868
c500c86b
PNA		 2869static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2870 struct mlx5e_tc_flow_parse_attr *parse_attr,
2871 struct pedit_headers_action *hdrs,
27c11b6b 2872 u32 *action_flags,
c500c86b
PNA		 2873 struct netlink_ext_ack *extack)
2874{
2875 struct pedit_headers *cmd_masks;
2876 int err;
2877 u8 cmd;
2878
6ae4a6a5
PB		 2879 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2880 action_flags, extack);
d79b6df6
OG		 2881 if (err < 0)
2882 goto out_dealloc_parsed_actions;
2883
2884 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2885 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2886 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2887 NL_SET_ERR_MSG_MOD(extack,
2888 "attempt to offload an unsupported field");
b3a433de 2889 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2890 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2891 16, 1, cmd_masks, sizeof(zero_masks), true);
2892 err = -EOPNOTSUPP;
2893 goto out_dealloc_parsed_actions;
2894 }
2895 }
2896
2897 return 0;
2898
2899out_dealloc_parsed_actions:
6ae4a6a5 2900 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2901 return err;
2902}
2903
e98bedf5
EB		 2904static bool csum_offload_supported(struct mlx5e_priv *priv,
2905 u32 action,
2906 u32 update_flags,
2907 struct netlink_ext_ack *extack)
26c02749
OG		 2908{
2909 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2910 TCA_CSUM_UPDATE_FLAG_UDP;
2911
2912 /* The HW recalcs checksums only if re-writing headers */
2913 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2914 NL_SET_ERR_MSG_MOD(extack,
2915 "TC csum action is only offloaded with pedit");
26c02749
OG		 2916 netdev_warn(priv->netdev,
2917 "TC csum action is only offloaded with pedit\n");
2918 return false;
2919 }
2920
2921 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2922 NL_SET_ERR_MSG_MOD(extack,
2923 "can't offload TC csum action for some header/s");
26c02749
OG		 2924 netdev_warn(priv->netdev,
2925 "can't offload TC csum action for some header/s - flags %#x\n",
2926 update_flags);
2927 return false;
2928 }
2929
2930 return true;
2931}
2932
8998576b
DL		 2933struct ip_ttl_word {
2934 __u8 ttl;
2935 __u8 protocol;
2936 __sum16 check;
2937};
2938
2939struct ipv6_hoplimit_word {
2940 __be16 payload_len;
2941 __u8 nexthdr;
2942 __u8 hop_limit;
2943};
2944
4c3844d9
PB		 2945static int is_action_keys_supported(const struct flow_action_entry *act,
2946 bool ct_flow, bool *modify_ip_header,
7e36feeb 2947 bool *modify_tuple,
4c3844d9 2948 struct netlink_ext_ack *extack)
8998576b
DL		 2949{
2950 u32 mask, offset;
2951 u8 htype;
2952
2953 htype = act->mangle.htype;
2954 offset = act->mangle.offset;
2955 mask = ~act->mangle.mask;
2956 /* For IPv4 & IPv6 header check 4 byte word,
2957 * to determine that modified fields
2958 * are NOT ttl & hop_limit only.
2959 */
2960 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2961 struct ip_ttl_word *ttl_word =
2962 (struct ip_ttl_word *)&mask;
2963
2964 if (offset != offsetof(struct iphdr, ttl) ||
2965 ttl_word->protocol ||
2966 ttl_word->check) {
4c3844d9
PB		 2967 *modify_ip_header = true;
2968 }
2969
7e36feeb
PB		 2970 if (offset >= offsetof(struct iphdr, saddr))
2971 *modify_tuple = true;
2972
2973 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 2974 NL_SET_ERR_MSG_MOD(extack,
2975 "can't offload re-write of ipv4 address with action ct");
2976 return -EOPNOTSUPP;
8998576b
DL		 2977 }
2978 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2979 struct ipv6_hoplimit_word *hoplimit_word =
2980 (struct ipv6_hoplimit_word *)&mask;
2981
2982 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2983 hoplimit_word->payload_len ||
2984 hoplimit_word->nexthdr) {
4c3844d9
PB		 2985 *modify_ip_header = true;
2986 }
2987
7e36feeb
PB		 2988 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
2989 *modify_tuple = true;
2990
2991 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 2992 NL_SET_ERR_MSG_MOD(extack,
2993 "can't offload re-write of ipv6 address with action ct");
2994 return -EOPNOTSUPP;
8998576b 2995 }
7e36feeb
PB		 2996 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2997 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
2998 *modify_tuple = true;
2999 if (ct_flow) {
3000 NL_SET_ERR_MSG_MOD(extack,
3001 "can't offload re-write of transport header ports with action ct");
3002 return -EOPNOTSUPP;
3003 }
8998576b 3004 }
4c3844d9
PB		 3005
3006 return 0;
8998576b
DL		 3007}
3008
96b5b458
DC		 3009static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3010 bool ct_flow, struct netlink_ext_ack *extack,
3011 struct mlx5e_priv *priv,
3012 struct mlx5_flow_spec *spec)
3013{
3014 if (!modify_tuple || ct_clear)
3015 return true;
3016
3017 if (ct_flow) {
3018 NL_SET_ERR_MSG_MOD(extack,
3019 "can't offload tuple modification with non-clear ct()");
3020 netdev_info(priv->netdev,
3021 "can't offload tuple modification with non-clear ct()");
3022 return false;
3023 }
3024
3025 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3026 * (or after clear action), as otherwise, since the tuple is changed,
3027 * we can't restore ct state
3028 */
3029 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3030 NL_SET_ERR_MSG_MOD(extack,
3031 "can't offload tuple modification with ct matches and no ct(clear) action");
3032 netdev_info(priv->netdev,
3033 "can't offload tuple modification with ct matches and no ct(clear) action");
3034 return false;
3035 }
3036
3037 return true;
3038}
3039
3d486ec4
OS		 3040static bool modify_header_match_supported(struct mlx5e_priv *priv,
3041 struct mlx5_flow_spec *spec,
73867881 3042 struct flow_action *flow_action,
4c3844d9 3043 u32 actions, bool ct_flow,
7e36feeb 3044 bool ct_clear,
e98bedf5 3045 struct netlink_ext_ack *extack)
bdd66ac0 3046{
73867881 3047 const struct flow_action_entry *act;
7e36feeb 3048 bool modify_ip_header, modify_tuple;
fca53304 3049 void *headers_c;
bdd66ac0
OG		 3050 void *headers_v;
3051 u16 ethertype;
8998576b 3052 u8 ip_proto;
4c3844d9 3053 int i, err;
bdd66ac0 3054
fca53304 3055 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3056 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3057 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3058
3059 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3060 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3061 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3062 goto out_ok;
3063
3064 modify_ip_header = false;
7e36feeb 3065 modify_tuple = false;
73867881
PNA		 3066 flow_action_for_each(i, act, flow_action) {
3067 if (act->id != FLOW_ACTION_MANGLE &&
3068 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3069 continue;
3070
4c3844d9 3071 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3072 &modify_ip_header,
3073 &modify_tuple, extack);
4c3844d9
PB		 3074 if (err)
3075 return err;
bdd66ac0
OG		 3076 }
3077
96b5b458
DC		 3078 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3079 priv, spec))
7e36feeb 3080 return false;
7e36feeb 3081
bdd66ac0 3082 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3083 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3084 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3085 NL_SET_ERR_MSG_MOD(extack,
3086 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3087 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3088 ip_proto);
bdd66ac0
OG		 3089 return false;
3090 }
3091
3092out_ok:
3093 return true;
3094}
3095
3096static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3097 struct flow_action *flow_action,
bdd66ac0 3098 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3099 struct mlx5e_tc_flow *flow,
3100 struct netlink_ext_ack *extack)
bdd66ac0 3101{
a7c119bd 3102 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3103 u32 actions;
3104
c620b772
AL		 3105 ct_clear = flow->attr->ct_attr.ct_action &
3106 TCA_CT_ACT_CLEAR;
3107 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3108 actions = flow->attr->action;
3109
4c3844d9 3110 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3111 if (flow->attr->esw_attr->split_count && ct_flow &&
3112 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3113 /* All registers used by ct are cleared when using
3114 * split rules.
3115 */
3116 NL_SET_ERR_MSG_MOD(extack,
3117 "Can't offload mirroring with action ct");
49397b80 3118 return false;
4c3844d9 3119 }
4c3844d9 3120 }
bdd66ac0
OG		 3121
3122 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3123 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3124 flow_action, actions,
7e36feeb
PB		 3125 ct_flow, ct_clear,
3126 extack);
bdd66ac0
OG		 3127
3128 return true;
3129}
3130
32134847
MD		 3131static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3132{
3133 return priv->mdev == peer_priv->mdev;
3134}
3135
5c65c564
OG		 3136static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3137{
3138 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3139 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3140
3141 fmdev = priv->mdev;
3142 pmdev = peer_priv->mdev;
3143
59c9d35e
AH		 3144 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3145 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3146
816f6706 3147 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3148}
3149
bb569657
AL		 3150static bool same_vf_reps(struct mlx5e_priv *priv,
3151 struct net_device *out_dev)
3152{
3153 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3154 priv->netdev == out_dev;
3155}
3156
bdc837ee
EB		 3157static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3158 const struct flow_action_entry *act,
3159 struct mlx5e_tc_flow_parse_attr *parse_attr,
3160 struct pedit_headers_action *hdrs,
3161 u32 *action, struct netlink_ext_ack *extack)
3162{
3163 u16 mask16 = VLAN_VID_MASK;
3164 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3165 const struct flow_action_entry pedit_act = {
3166 .id = FLOW_ACTION_MANGLE,
3167 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3168 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3169 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3170 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3171 };
6fca9d1e 3172 u8 match_prio_mask, match_prio_val;
bf2f3bca 3173 void *headers_c, *headers_v;
bdc837ee
EB		 3174 int err;
3175
bf2f3bca
EB		 3176 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3177 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3178
3179 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3180 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3181 NL_SET_ERR_MSG_MOD(extack,
3182 "VLAN rewrite action must have VLAN protocol match");
3183 return -EOPNOTSUPP;
3184 }
3185
6fca9d1e
EB		 3186 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3187 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3188 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3189 NL_SET_ERR_MSG_MOD(extack,
3190 "Changing VLAN prio is not supported");
bdc837ee
EB		 3191 return -EOPNOTSUPP;
3192 }
3193
582234b4 3194 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3195 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3196
3197 return err;
3198}
3199
0bac1194
EB		 3200static int
3201add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3202 struct mlx5e_tc_flow_parse_attr *parse_attr,
3203 struct pedit_headers_action *hdrs,
3204 u32 *action, struct netlink_ext_ack *extack)
3205{
3206 const struct flow_action_entry prio_tag_act = {
3207 .vlan.vid = 0,
3208 .vlan.prio =
3209 MLX5_GET(fte_match_set_lyr_2_4,
3210 get_match_headers_value(*action,
3211 &parse_attr->spec),
3212 first_prio) &
3213 MLX5_GET(fte_match_set_lyr_2_4,
3214 get_match_headers_criteria(*action,
3215 &parse_attr->spec),
3216 first_prio),
3217 };
3218
3219 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3220 &prio_tag_act, parse_attr, hdrs, action,
3221 extack);
3222}
3223
c7569097
AL		 3224static int validate_goto_chain(struct mlx5e_priv *priv,
3225 struct mlx5e_tc_flow *flow,
3226 const struct flow_action_entry *act,
3227 u32 actions,
3228 struct netlink_ext_ack *extack)
3229{
3230 bool is_esw = mlx5e_is_eswitch_flow(flow);
3231 struct mlx5_flow_attr *attr = flow->attr;
3232 bool ft_flow = mlx5e_is_ft_flow(flow);
3233 u32 dest_chain = act->chain_index;
3234 struct mlx5_fs_chains *chains;
3235 struct mlx5_eswitch *esw;
3236 u32 reformat_and_fwd;
3237 u32 max_chain;
3238
3239 esw = priv->mdev->priv.eswitch;
3240 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3241 max_chain = mlx5_chains_get_chain_range(chains);
3242 reformat_and_fwd = is_esw ?
3243 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3244 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3245
3246 if (ft_flow) {
3247 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3248 return -EOPNOTSUPP;
3249 }
3250
3251 if (!mlx5_chains_backwards_supported(chains) &&
3252 dest_chain <= attr->chain) {
3253 NL_SET_ERR_MSG_MOD(extack,
3254 "Goto lower numbered chain isn't supported");
3255 return -EOPNOTSUPP;
3256 }
3257
3258 if (dest_chain > max_chain) {
3259 NL_SET_ERR_MSG_MOD(extack,
3260 "Requested destination chain is out of supported range");
3261 return -EOPNOTSUPP;
3262 }
3263
3264 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3265 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3266 !reformat_and_fwd) {
3267 NL_SET_ERR_MSG_MOD(extack,
3268 "Goto chain is not allowed if action has reformat or decap");
3269 return -EOPNOTSUPP;
3270 }
3271
3272 return 0;
3273}
3274
73867881
PNA		 3275static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3276 struct flow_action *flow_action,
aa0cbbae 3277 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3278 struct mlx5e_tc_flow *flow,
3279 struct netlink_ext_ack *extack)
e3a2b7ed 3280{
c620b772 3281 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3282 struct pedit_headers_action hdrs[2] = {};
3283 const struct flow_action_entry *act;
c620b772 3284 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3285 u32 action = 0;
244cd96a 3286 int err, i;
e3a2b7ed 3287
73867881 3288 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3289 return -EINVAL;
3290
53eca1f3
JK		 3291 if (!flow_action_hw_stats_check(flow_action, extack,
3292 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3293 return -EOPNOTSUPP;
3294
c620b772
AL		 3295 nic_attr = attr->nic_attr;
3296
3297 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3298
73867881
PNA		 3299 flow_action_for_each(i, act, flow_action) {
3300 switch (act->id) {
15fc92ec
TZ		 3301 case FLOW_ACTION_ACCEPT:
3302 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3303 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3304 break;
73867881 3305 case FLOW_ACTION_DROP:
1cab1cd7 3306 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3307 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3308 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3309 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3310 break;
3311 case FLOW_ACTION_MANGLE:
3312 case FLOW_ACTION_ADD:
3313 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3314 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3315 if (err)
3316 return err;
3317
c7569097 3318 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3319 break;
bdc837ee
EB		 3320 case FLOW_ACTION_VLAN_MANGLE:
3321 err = add_vlan_rewrite_action(priv,
3322 MLX5_FLOW_NAMESPACE_KERNEL,
3323 act, parse_attr, hdrs,
3324 &action, extack);
3325 if (err)
3326 return err;
3327
3328 break;
73867881 3329 case FLOW_ACTION_CSUM:
1cab1cd7 3330 if (csum_offload_supported(priv, action,
73867881 3331 act->csum_flags,
e98bedf5 3332 extack))
73867881 3333 break;
26c02749
OG		 3334
3335 return -EOPNOTSUPP;
73867881
PNA		 3336 case FLOW_ACTION_REDIRECT: {
3337 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3338
3339 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3340 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3341 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3342 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3343 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3344 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3345 } else {
e98bedf5
EB		 3346 NL_SET_ERR_MSG_MOD(extack,
3347 "device is not on same HW, can't offload");
5c65c564
OG		 3348 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3349 peer_dev->name);
3350 return -EINVAL;
3351 }
73867881
PNA		 3352 }
3353 break;
3354 case FLOW_ACTION_MARK: {
3355 u32 mark = act->mark;
e3a2b7ed
AV		 3356
3357 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3358 NL_SET_ERR_MSG_MOD(extack,
3359 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3360 return -EINVAL;
3361 }
3362
c620b772 3363 nic_attr->flow_tag = mark;
1cab1cd7 3364 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3365 }
3366 break;
c7569097
AL		 3367 case FLOW_ACTION_GOTO:
3368 err = validate_goto_chain(priv, flow, act, action,
3369 extack);
3370 if (err)
3371 return err;
3372
3373 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3374 attr->dest_chain = act->chain_index;
3375 break;
aedd133d
AL		 3376 case FLOW_ACTION_CT:
3377 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3378 if (err)
3379 return err;
3380
3381 flow_flag_set(flow, CT);
3382 break;
73867881 3383 default:
2cc1cb1d
TZ		 3384 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3385 return -EOPNOTSUPP;
e3a2b7ed 3386 }
e3a2b7ed
AV		 3387 }
3388
c500c86b
PNA		 3389 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3390 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3391 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3392 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3393 if (err)
3394 return err;
27c11b6b
EB		 3395 /* in case all pedit actions are skipped, remove the MOD_HDR
3396 * flag.
3397 */
6ae4a6a5 3398 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3399 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3400 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3401 }
c500c86b
PNA		 3402 }
3403
1cab1cd7 3404 attr->action = action;
c7569097
AL		 3405
3406 if (attr->dest_chain) {
3407 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3408 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3409 return -EOPNOTSUPP;
3410 }
3411 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3412 }
3413
3414 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3415 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3416
73867881 3417 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3418 return -EOPNOTSUPP;
3419
e3a2b7ed
AV		 3420 return 0;
3421}
3422
32134847 3423static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3424 struct net_device *peer_netdev)
3425{
3426 struct mlx5e_priv *peer_priv;
3427
3428 peer_priv = netdev_priv(peer_netdev);
3429
3430 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3431 mlx5e_eswitch_vf_rep(priv->netdev) &&
3432 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3433 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3434}
3435
1482bd3d 3436static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3437 const struct flow_action_entry *act,
1482bd3d
JL		 3438 struct mlx5_esw_flow_attr *attr,
3439 u32 *action)
3440{
cc495188
JL		 3441 u8 vlan_idx = attr->total_vlan;
3442
3443 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3444 return -EOPNOTSUPP;
3445
73867881
PNA		 3446 switch (act->id) {
3447 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3448 if (vlan_idx) {
3449 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3450 MLX5_FS_VLAN_DEPTH))
3451 return -EOPNOTSUPP;
3452
3453 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3454 } else {
3455 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3456 }
73867881
PNA		 3457 break;
3458 case FLOW_ACTION_VLAN_PUSH:
3459 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3460 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3461 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3462 if (!attr->vlan_proto[vlan_idx])
3463 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3464
3465 if (vlan_idx) {
3466 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3467 MLX5_FS_VLAN_DEPTH))
3468 return -EOPNOTSUPP;
3469
3470 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3471 } else {
3472 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3473 (act->vlan.proto != htons(ETH_P_8021Q) ||
3474 act->vlan.prio))
cc495188
JL		 3475 return -EOPNOTSUPP;
3476
3477 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3478 }
73867881
PNA		 3479 break;
3480 default:
bdc837ee 3481 return -EINVAL;
1482bd3d
JL		 3482 }
3483
cc495188
JL		 3484 attr->total_vlan = vlan_idx + 1;
3485
1482bd3d
JL		 3486 return 0;
3487}
3488
d34eb2fc
OG		 3489static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3490 struct net_device *out_dev)
3491{
3492 struct net_device *fdb_out_dev = out_dev;
3493 struct net_device *uplink_upper;
3494
3495 rcu_read_lock();
3496 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3497 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3498 uplink_upper == out_dev) {
3499 fdb_out_dev = uplink_dev;
3500 } else if (netif_is_lag_master(out_dev)) {
3501 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3502 if (fdb_out_dev &&
3503 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3504 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3505 fdb_out_dev = NULL;
3506 }
3507 rcu_read_unlock();
3508 return fdb_out_dev;
3509}
3510
278748a9 3511static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3512 struct mlx5_flow_attr *attr,
278748a9
EB		 3513 struct net_device **out_dev,
3514 u32 *action)
3515{
3516 struct net_device *vlan_dev = *out_dev;
3517 struct flow_action_entry vlan_act = {
3518 .id = FLOW_ACTION_VLAN_PUSH,
3519 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3520 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3521 .vlan.prio = 0,
3522 };
3523 int err;
3524
c620b772 3525 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3526 if (err)
3527 return err;
3528
dca59f4a
DC		 3529 rcu_read_lock();
3530 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3531 rcu_read_unlock();
3532 if (!*out_dev)
3533 return -ENODEV;
3534
278748a9
EB		 3535 if (is_vlan_dev(*out_dev))
3536 err = add_vlan_push_action(priv, attr, out_dev, action);
3537
3538 return err;
3539}
3540
35a605db 3541static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3542 struct mlx5_flow_attr *attr,
35a605db
EB		 3543 u32 *action)
3544{
35a605db
EB		 3545 struct flow_action_entry vlan_act = {
3546 .id = FLOW_ACTION_VLAN_POP,
3547 };
70f478ca 3548 int nest_level, err = 0;
35a605db 3549
70f478ca
DL		 3550 nest_level = attr->parse_attr->filter_dev->lower_level -
3551 priv->netdev->lower_level;
35a605db 3552 while (nest_level--) {
c620b772 3553 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3554 if (err)
3555 return err;
3556 }
3557
3558 return err;
3559}
3560
32134847
MD		 3561static bool same_hw_reps(struct mlx5e_priv *priv,
3562 struct net_device *peer_netdev)
3563{
3564 struct mlx5e_priv *peer_priv;
3565
3566 peer_priv = netdev_priv(peer_netdev);
3567
3568 return mlx5e_eswitch_rep(priv->netdev) &&
3569 mlx5e_eswitch_rep(peer_netdev) &&
3570 same_hw_devs(priv, peer_priv);
3571}
3572
3573static bool is_lag_dev(struct mlx5e_priv *priv,
3574 struct net_device *peer_netdev)
3575{
3576 return ((mlx5_lag_is_sriov(priv->mdev) ||
3577 mlx5_lag_is_multipath(priv->mdev)) &&
3578 same_hw_reps(priv, peer_netdev));
3579}
3580
f6dc1264
PB		 3581bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3582 struct net_device *out_dev)
3583{
32134847
MD		 3584 if (is_merged_eswitch_vfs(priv, out_dev))
3585 return true;
3586
3587 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3588 return true;
3589
3590 return mlx5e_eswitch_rep(out_dev) &&
32134847 3591 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3592}
3593
554fe75c
DL		 3594static bool is_duplicated_output_device(struct net_device *dev,
3595 struct net_device *out_dev,
3596 int *ifindexes, int if_count,
3597 struct netlink_ext_ack *extack)
3598{
3599 int i;
3600
3601 for (i = 0; i < if_count; i++) {
3602 if (ifindexes[i] == out_dev->ifindex) {
3603 NL_SET_ERR_MSG_MOD(extack,
3604 "can't duplicate output to same device");
3605 netdev_err(dev, "can't duplicate output to same device: %s\n",
3606 out_dev->name);
3607 return true;
3608 }
3609 }
3610
3611 return false;
3612}
3613
613f53fe
EC		 3614static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3615 struct mlx5e_tc_flow *flow,
3616 struct net_device *out_dev,
3617 struct netlink_ext_ack *extack)
3618{
c620b772 3619 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3620 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3621 struct mlx5e_rep_priv *rep_priv;
3622
3623 /* Forwarding non encapsulated traffic between
3624 * uplink ports is allowed only if
3625 * termination_table_raw_traffic cap is set.
3626 *
c620b772 3627 * Input vport was stored attr->in_rep.
613f53fe
EC		 3628 * In LAG case, *priv* is the private data of
3629 * uplink which may be not the input vport.
3630 */
3631 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3632
3633 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3634 mlx5e_eswitch_uplink_rep(out_dev)))
3635 return 0;
3636
3637 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3638 termination_table_raw_traffic)) {
3639 NL_SET_ERR_MSG_MOD(extack,
3640 "devices are both uplink, can't offload forwarding");
3641 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3642 priv->netdev->name, out_dev->name);
3643 return -EOPNOTSUPP;
3644 } else if (out_dev != rep_priv->netdev) {
3645 NL_SET_ERR_MSG_MOD(extack,
3646 "devices are not the same uplink, can't offload forwarding");
3647 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3648 priv->netdev->name, out_dev->name);
3649 return -EOPNOTSUPP;
3650 }
3651 return 0;
3652}
3653
73867881
PNA		 3654static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3655 struct flow_action *flow_action,
e98bedf5 3656 struct mlx5e_tc_flow *flow,
14e6b038
EC		 3657 struct netlink_ext_ack *extack,
3658 struct net_device *filter_dev)
03a9d11e 3659{
73867881 3660 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3661 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3662 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3663 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3664 const struct ip_tunnel_info *info = NULL;
c620b772 3665 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3666 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3667 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3668 const struct flow_action_entry *act;
c620b772 3669 struct mlx5_esw_flow_attr *esw_attr;
41c2fd94 3670 struct mlx5_sample_attr sample = {};
0a7fcb78
PB		 3671 bool encap = false, decap = false;
3672 u32 action = attr->action;
554fe75c 3673 int err, i, if_count = 0;
f828ca6a 3674 bool mpls_push = false;
03a9d11e 3675
73867881 3676 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3677 return -EINVAL;
3678
53eca1f3
JK		 3679 if (!flow_action_hw_stats_check(flow_action, extack,
3680 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3681 return -EOPNOTSUPP;
3682
c620b772
AL		 3683 esw_attr = attr->esw_attr;
3684 parse_attr = attr->parse_attr;
3685
73867881
PNA		 3686 flow_action_for_each(i, act, flow_action) {
3687 switch (act->id) {
3688 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3689 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3690 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3691 break;
f0288210
EC		 3692 case FLOW_ACTION_TRAP:
3693 if (!flow_offload_has_one_action(flow_action)) {
3694 NL_SET_ERR_MSG_MOD(extack,
3695 "action trap is supported as a sole action only");
3696 return -EOPNOTSUPP;
3697 }
3698 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3699 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3700 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3701 break;
f828ca6a
EC		 3702 case FLOW_ACTION_MPLS_PUSH:
3703 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3704 reformat_l2_to_l3_tunnel) ||
3705 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3706 NL_SET_ERR_MSG_MOD(extack,
3707 "mpls push is supported only for mpls_uc protocol");
3708 return -EOPNOTSUPP;
3709 }
3710 mpls_push = true;
3711 break;
14e6b038
EC		 3712 case FLOW_ACTION_MPLS_POP:
3713 /* we only support mpls pop if it is the first action
3714 * and the filter net device is bareudp. Subsequent
3715 * actions can be pedit and the last can be mirred
3716 * egress redirect.
3717 */
3718 if (i) {
3719 NL_SET_ERR_MSG_MOD(extack,
3720 "mpls pop supported only as first action");
3721 return -EOPNOTSUPP;
3722 }
3723 if (!netif_is_bareudp(filter_dev)) {
3724 NL_SET_ERR_MSG_MOD(extack,
3725 "mpls pop supported only on bareudp devices");
3726 return -EOPNOTSUPP;
3727 }
3728
3729 parse_attr->eth.h_proto = act->mpls_pop.proto;
3730 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3731 flow_flag_set(flow, L3_TO_L2_DECAP);
3732 break;
73867881
PNA		 3733 case FLOW_ACTION_MANGLE:
3734 case FLOW_ACTION_ADD:
3735 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3736 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3737 if (err)
3738 return err;
3739
582234b4
EC		 3740 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3741 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3742 esw_attr->split_count = esw_attr->out_count;
582234b4 3743 }
73867881
PNA		 3744 break;
3745 case FLOW_ACTION_CSUM:
1cab1cd7 3746 if (csum_offload_supported(priv, action,
73867881
PNA		 3747 act->csum_flags, extack))
3748 break;
26c02749
OG		 3749
3750 return -EOPNOTSUPP;
73867881
PNA		 3751 case FLOW_ACTION_REDIRECT:
3752 case FLOW_ACTION_MIRRED: {
03a9d11e 3753 struct mlx5e_priv *out_priv;
592d3651 3754 struct net_device *out_dev;
03a9d11e 3755
73867881 3756 out_dev = act->dev;
ef381359
OS		 3757 if (!out_dev) {
3758 /* out_dev is NULL when filters with
3759 * non-existing mirred device are replayed to
3760 * the driver.
3761 */
3762 return -EINVAL;
3763 }
03a9d11e 3764
f828ca6a
EC		 3765 if (mpls_push && !netif_is_bareudp(out_dev)) {
3766 NL_SET_ERR_MSG_MOD(extack,
3767 "mpls is supported only through a bareudp device");
3768 return -EOPNOTSUPP;
3769 }
3770
84179981
PB		 3771 if (ft_flow && out_dev == priv->netdev) {
3772 /* Ignore forward to self rules generated
3773 * by adding both mlx5 devs to the flow table
3774 * block on a normal nft offload setup.
3775 */
3776 return -EOPNOTSUPP;
3777 }
3778
c620b772 3779 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3780 NL_SET_ERR_MSG_MOD(extack,
3781 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3782 netdev_warn(priv->netdev,
3783 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3784 esw_attr->out_count);
592d3651
CM		 3785 return -EOPNOTSUPP;
3786 }
3787
f493f155
EB		 3788 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3789 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3790 if (encap) {
c620b772 3791 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3792 out_dev->ifindex;
0d9f9647
VB		 3793 parse_attr->tun_info[esw_attr->out_count] =
3794 mlx5e_dup_tun_info(info);
c620b772 3795 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3796 return -ENOMEM;
3797 encap = false;
c620b772 3798 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3799 MLX5_ESW_DEST_ENCAP;
c620b772 3800 esw_attr->out_count++;
b6a4ac24
VB		 3801 /* attr->dests[].rep is resolved when we
3802 * handle encap
3803 */
3804 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3805 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3806 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3807
554fe75c
DL		 3808 if (is_duplicated_output_device(priv->netdev,
3809 out_dev,
3810 ifindexes,
3811 if_count,
3812 extack))
3813 return -EOPNOTSUPP;
3814
3815 ifindexes[if_count] = out_dev->ifindex;
3816 if_count++;
3817
d34eb2fc
OG		 3818 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3819 if (!out_dev)
3820 return -ENODEV;
7ba58ba7 3821
278748a9
EB		 3822 if (is_vlan_dev(out_dev)) {
3823 err = add_vlan_push_action(priv, attr,
3824 &out_dev,
3825 &action);
3826 if (err)
3827 return err;
3828 }
f6dc1264 3829
35a605db
EB		 3830 if (is_vlan_dev(parse_attr->filter_dev)) {
3831 err = add_vlan_pop_action(priv, attr,
3832 &action);
3833 if (err)
3834 return err;
3835 }
278748a9 3836
613f53fe
EC		 3837 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3838 if (err)
3839 return err;
ffec9702 3840
f6dc1264
PB		 3841 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3842 NL_SET_ERR_MSG_MOD(extack,
3843 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3844 return -EOPNOTSUPP;
f6dc1264 3845 }
a0646c88 3846
bb569657
AL		 3847 if (same_vf_reps(priv, out_dev)) {
3848 NL_SET_ERR_MSG_MOD(extack,
3849 "can't forward from a VF to itself");
3850 return -EOPNOTSUPP;
3851 }
3852
a54e20b4 3853 out_priv = netdev_priv(out_dev);
1d447a39 3854 rpriv = out_priv->ppriv;
c620b772
AL		 3855 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3856 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3857 esw_attr->out_count++;
ef381359
OS		 3858 } else if (parse_attr->filter_dev != priv->netdev) {
3859 /* All mlx5 devices are called to configure
3860 * high level device filters. Therefore, the
3861 * *attempt* to install a filter on invalid
3862 * eswitch should not trigger an explicit error
3863 */
3864 return -EINVAL;
a54e20b4 3865 } else {
e98bedf5
EB		 3866 NL_SET_ERR_MSG_MOD(extack,
3867 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3868 netdev_warn(priv->netdev,
3869 "devices %s %s not on same switch HW, can't offload forwarding\n",
3870 priv->netdev->name,
3871 out_dev->name);
03a9d11e
OG		 3872 return -EINVAL;
3873 }
73867881
PNA		 3874 }
3875 break;
3876 case FLOW_ACTION_TUNNEL_ENCAP:
3877 info = act->tunnel;
a54e20b4
HHZ		 3878 if (info)
3879 encap = true;
3880 else
3881 return -EOPNOTSUPP;
1482bd3d 3882
73867881
PNA		 3883 break;
3884 case FLOW_ACTION_VLAN_PUSH:
3885 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3886 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3887 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3888 /* Replace vlan pop+push with vlan modify */
3889 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3890 err = add_vlan_rewrite_action(priv,
3891 MLX5_FLOW_NAMESPACE_FDB,
3892 act, parse_attr, hdrs,
3893 &action, extack);
3894 } else {
c620b772 3895 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3896 }
1482bd3d
JL		 3897 if (err)
3898 return err;
3899
c620b772 3900 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3901 break;
3902 case FLOW_ACTION_VLAN_MANGLE:
3903 err = add_vlan_rewrite_action(priv,
3904 MLX5_FLOW_NAMESPACE_FDB,
3905 act, parse_attr, hdrs,
3906 &action, extack);
3907 if (err)
3908 return err;
3909
c620b772 3910 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3911 break;
3912 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3913 decap = true;
73867881 3914 break;
2fbbc30d 3915 case FLOW_ACTION_GOTO:
c7569097
AL		 3916 err = validate_goto_chain(priv, flow, act, action,
3917 extack);
2fbbc30d
EC		 3918 if (err)
3919 return err;
bf07aa73 3920
e88afe75 3921 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 3922 attr->dest_chain = act->chain_index;
73867881 3923 break;
4c3844d9 3924 case FLOW_ACTION_CT:
41c2fd94
CM		 3925 if (flow_flag_test(flow, SAMPLE)) {
3926 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
3927 return -EOPNOTSUPP;
3928 }
aedd133d 3929 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 3930 if (err)
3931 return err;
3932
3933 flow_flag_set(flow, CT);
69e2916e 3934 esw_attr->split_count = esw_attr->out_count;
4c3844d9 3935 break;
41c2fd94
CM		 3936 case FLOW_ACTION_SAMPLE:
3937 if (flow_flag_test(flow, CT)) {
3938 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
3939 return -EOPNOTSUPP;
3940 }
3941 sample.rate = act->sample.rate;
3942 sample.group_num = act->sample.psample_group->group_num;
3943 if (act->sample.truncate)
3944 sample.trunc_size = act->sample.trunc_size;
3945 flow_flag_set(flow, SAMPLE);
3946 break;
73867881 3947 default:
2cc1cb1d
TZ		 3948 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3949 return -EOPNOTSUPP;
bf07aa73 3950 }
03a9d11e 3951 }
bdd66ac0 3952
a508728a
VB		 3953 /* always set IP version for indirect table handling */
3954 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3955
0bac1194
EB		 3956 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3957 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3958 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3959 * tag rewrite.
3960 */
3961 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3962 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3963 &action, extack);
3964 if (err)
3965 return err;
3966 }
3967
c500c86b
PNA		 3968 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3969 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3970 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3971 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3972 if (err)
3973 return err;
27c11b6b
EB		 3974 /* in case all pedit actions are skipped, remove the MOD_HDR
3975 * flag. we might have set split_count either by pedit or
3976 * pop/push. if there is no pop/push either, reset it too.
3977 */
6ae4a6a5 3978 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3979 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3980 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 3981 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3982 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 3983 esw_attr->split_count = 0;
27c11b6b 3984 }
c500c86b
PNA		 3985 }
3986
1cab1cd7 3987 attr->action = action;
73867881 3988 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3989 return -EOPNOTSUPP;
3990
e88afe75 3991 if (attr->dest_chain) {
0a7fcb78
PB		 3992 if (decap) {
3993 /* It can be supported if we'll create a mapping for
3994 * the tunnel device only (without tunnel), and set
3995 * this tunnel id with this decap flow.
3996 *
3997 * On restore (miss), we'll just set this saved tunnel
3998 * device.
3999 */
4000
4001 NL_SET_ERR_MSG(extack,
4002 "Decap with goto isn't supported");
4003 netdev_warn(priv->netdev,
4004 "Decap with goto isn't supported");
4005 return -EOPNOTSUPP;
4006 }
4007
e88afe75
OG		 4008 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4009 }
4010
ae2741e2
VB		 4011 if (!(attr->action &
4012 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4013 NL_SET_ERR_MSG_MOD(extack,
4014 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4015 return -EOPNOTSUPP;
4016 }
4017
c620b772 4018 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4019 NL_SET_ERR_MSG_MOD(extack,
4020 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4021 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4022 return -EOPNOTSUPP;
4023 }
4024
41c2fd94
CM		 4025 /* Allocate sample attribute only when there is a sample action and
4026 * no errors after parsing.
4027 */
4028 if (flow_flag_test(flow, SAMPLE)) {
4029 esw_attr->sample = kzalloc(sizeof(*esw_attr->sample), GFP_KERNEL);
4030 if (!esw_attr->sample)
4031 return -ENOMEM;
4032 *esw_attr->sample = sample;
4033 }
4034
31c8eba5 4035 return 0;
03a9d11e
OG		 4036}
4037
226f2ca3 4038static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4039{
226f2ca3 4040 unsigned long __flow_flags = 0;
60bd4af8 4041
226f2ca3
VB		 4042 if (flags & MLX5_TC_FLAG(INGRESS))
4043 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4044 if (flags & MLX5_TC_FLAG(EGRESS))
4045 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4046
226f2ca3
VB		 4047 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4048 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4049 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4050 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4051 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4052 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4053
60bd4af8
OG		 4054 *flow_flags = __flow_flags;
4055}
4056
05866c82
OG		 4057static const struct rhashtable_params tc_ht_params = {
4058 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4059 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4060 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4061 .automatic_shrinking = true,
4062};
4063
226f2ca3
VB		 4064static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4065 unsigned long flags)
05866c82 4066{
655dc3d2
OG		 4067 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4068 struct mlx5e_rep_priv *uplink_rpriv;
4069
226f2ca3 4070 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4071 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4072 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4073 } else /* NIC offload */
655dc3d2 4074 return &priv->fs.tc.ht;
05866c82
OG		 4075}
4076
04de7dda
RD		 4077static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4078{
c620b772
AL		 4079 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4080 struct mlx5_flow_attr *attr = flow->attr;
4081 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4082 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4083 bool act_is_encap = !!(attr->action &
4084 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4085 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4086 MLX5_DEVCOM_ESW_OFFLOADS);
4087
10fbb1cd
RD		 4088 if (!esw_paired)
4089 return false;
4090
c620b772
AL		 4091 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4092 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4093 (is_rep_ingress || act_is_encap))
4094 return true;
4095
4096 return false;
04de7dda
RD		 4097}
4098
c620b772
AL		 4099struct mlx5_flow_attr *
4100mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4101{
4102 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4103 sizeof(struct mlx5_esw_flow_attr) :
4104 sizeof(struct mlx5_nic_flow_attr);
4105 struct mlx5_flow_attr *attr;
4106
4107 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4108}
4109
a88780a9
RD		 4110static int
4111mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4112 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4113 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4114 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4115{
17091853 4116 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4117 struct mlx5_flow_attr *attr;
3bc4b7bf 4118 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4119 int err = -ENOMEM;
4120 int out_index;
e3a2b7ed 4121
c620b772 4122 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4123 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4124 if (!parse_attr || !flow)
4125 goto err_free;
c620b772
AL		 4126
4127 flow->flags = flow_flags;
4128 flow->cookie = f->cookie;
4129 flow->priv = priv;
4130
4131 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4132 if (!attr)
e3a2b7ed 4133 goto err_free;
ff7ea04a 4134
c620b772 4135 flow->attr = attr;
e3a2b7ed 4136
5a7e5bcb
VB		 4137 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4138 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4139 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4140 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4141 refcount_set(&flow->refcnt, 1);
95435ad7 4142 init_completion(&flow->init_done);
e3a2b7ed 4143
a88780a9
RD		 4144 *__flow = flow;
4145 *__parse_attr = parse_attr;
4146
4147 return 0;
4148
4149err_free:
4150 kfree(flow);
4151 kvfree(parse_attr);
4152 return err;
4153}
4154
c7569097
AL		 4155static void
4156mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4157 struct mlx5e_tc_flow_parse_attr *parse_attr,
4158 struct flow_cls_offload *f)
4159{
4160 attr->parse_attr = parse_attr;
4161 attr->chain = f->common.chain_index;
4162 attr->prio = f->common.prio;
4163}
4164
988ab9c7 4165static void
c620b772 4166mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4167 struct mlx5e_priv *priv,
4168 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4169 struct flow_cls_offload *f,
988ab9c7
TZ		 4170 struct mlx5_eswitch_rep *in_rep,
4171 struct mlx5_core_dev *in_mdev)
4172{
4173 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4174 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4175
c7569097 4176 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4177
4178 esw_attr->in_rep = in_rep;
4179 esw_attr->in_mdev = in_mdev;
4180
4181 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4182 MLX5_COUNTER_SOURCE_ESWITCH)
4183 esw_attr->counter_dev = in_mdev;
4184 else
4185 esw_attr->counter_dev = priv->mdev;
4186}
4187
71129676 4188static struct mlx5e_tc_flow *
04de7dda 4189__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4190 struct flow_cls_offload *f,
226f2ca3 4191 unsigned long flow_flags,
04de7dda
RD		 4192 struct net_device *filter_dev,
4193 struct mlx5_eswitch_rep *in_rep,
71129676 4194 struct mlx5_core_dev *in_mdev)
a88780a9 4195{
f9e30088 4196 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4197 struct netlink_ext_ack *extack = f->common.extack;
4198 struct mlx5e_tc_flow_parse_attr *parse_attr;
4199 struct mlx5e_tc_flow *flow;
4200 int attr_size, err;
e3a2b7ed 4201
226f2ca3 4202 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4203 attr_size = sizeof(struct mlx5_esw_flow_attr);
4204 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4205 &parse_attr, &flow);
4206 if (err)
4207 goto out;
988ab9c7 4208
d11afc26 4209 parse_attr->filter_dev = filter_dev;
c620b772 4210 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4211 priv, parse_attr,
4212 f, in_rep, in_mdev);
4213
54c177ca
OS		 4214 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4215 f, filter_dev);
d11afc26
OS		 4216 if (err)
4217 goto err_free;
a88780a9 4218
7e36feeb 4219 /* actions validation depends on parsing the ct matches first */
aedd133d 4220 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4221 &flow->attr->ct_attr, extack);
a88780a9
RD		 4222 if (err)
4223 goto err_free;
4224
7e36feeb 4225 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4226 if (err)
4227 goto err_free;
4228
7040632d 4229 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4230 complete_all(&flow->init_done);
ef06c9ee
RD		 4231 if (err) {
4232 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4233 goto err_free;
4234
b4a23329 4235 add_unready_flow(flow);
ef06c9ee 4236 }
e3a2b7ed 4237
71129676 4238 return flow;
a88780a9
RD		 4239
4240err_free:
5a7e5bcb 4241 mlx5e_flow_put(priv, flow);
a88780a9 4242out:
71129676 4243 return ERR_PTR(err);
a88780a9
RD		 4244}
4245
f9e30088 4246static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4247 struct mlx5e_tc_flow *flow,
226f2ca3 4248 unsigned long flow_flags)
04de7dda
RD		 4249{
4250 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4251 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4252 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4253 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4254 struct mlx5e_tc_flow_parse_attr *parse_attr;
4255 struct mlx5e_rep_priv *peer_urpriv;
4256 struct mlx5e_tc_flow *peer_flow;
4257 struct mlx5_core_dev *in_mdev;
4258 int err = 0;
4259
4260 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4261 if (!peer_esw)
4262 return -ENODEV;
4263
4264 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4265 peer_priv = netdev_priv(peer_urpriv->netdev);
4266
4267 /* in_mdev is assigned of which the packet originated from.
4268 * So packets redirected to uplink use the same mdev of the
4269 * original flow and packets redirected from uplink use the
4270 * peer mdev.
4271 */
c620b772 4272 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4273 in_mdev = peer_priv->mdev;
4274 else
4275 in_mdev = priv->mdev;
4276
c620b772 4277 parse_attr = flow->attr->parse_attr;
95dc1902 4278 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4279 parse_attr->filter_dev,
c620b772 4280 attr->in_rep, in_mdev);
71129676
JG		 4281 if (IS_ERR(peer_flow)) {
4282 err = PTR_ERR(peer_flow);
04de7dda 4283 goto out;
71129676 4284 }
04de7dda
RD		 4285
4286 flow->peer_flow = peer_flow;
226f2ca3 4287 flow_flag_set(flow, DUP);
04de7dda
RD		 4288 mutex_lock(&esw->offloads.peer_mutex);
4289 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4290 mutex_unlock(&esw->offloads.peer_mutex);
4291
4292out:
4293 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4294 return err;
4295}
4296
4297static int
4298mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4299 struct flow_cls_offload *f,
226f2ca3 4300 unsigned long flow_flags,
04de7dda
RD		 4301 struct net_device *filter_dev,
4302 struct mlx5e_tc_flow **__flow)
4303{
4304 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4305 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4306 struct mlx5_core_dev *in_mdev = priv->mdev;
4307 struct mlx5e_tc_flow *flow;
4308 int err;
4309
71129676
JG		 4310 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4311 in_mdev);
4312 if (IS_ERR(flow))
4313 return PTR_ERR(flow);
04de7dda
RD		 4314
4315 if (is_peer_flow_needed(flow)) {
95dc1902 4316 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4317 if (err) {
4318 mlx5e_tc_del_fdb_flow(priv, flow);
4319 goto out;
4320 }
4321 }
4322
4323 *__flow = flow;
4324
4325 return 0;
4326
4327out:
4328 return err;
4329}
4330
a88780a9
RD		 4331static int
4332mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4333 struct flow_cls_offload *f,
226f2ca3 4334 unsigned long flow_flags,
d11afc26 4335 struct net_device *filter_dev,
a88780a9
RD		 4336 struct mlx5e_tc_flow **__flow)
4337{
f9e30088 4338 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4339 struct netlink_ext_ack *extack = f->common.extack;
4340 struct mlx5e_tc_flow_parse_attr *parse_attr;
4341 struct mlx5e_tc_flow *flow;
4342 int attr_size, err;
4343
c7569097
AL		 4344 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4345 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4346 return -EOPNOTSUPP;
4347 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4348 return -EOPNOTSUPP;
c7569097 4349 }
bf07aa73 4350
226f2ca3 4351 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4352 attr_size = sizeof(struct mlx5_nic_flow_attr);
4353 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4354 &parse_attr, &flow);
4355 if (err)
4356 goto out;
4357
d11afc26 4358 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4359 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4360
54c177ca
OS		 4361 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4362 f, filter_dev);
d11afc26
OS		 4363 if (err)
4364 goto err_free;
4365
aedd133d
AL		 4366 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4367 &flow->attr->ct_attr, extack);
4368 if (err)
4369 goto err_free;
4370
73867881 4371 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4372 if (err)
4373 goto err_free;
4374
4375 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4376 if (err)
4377 goto err_free;
4378
226f2ca3 4379 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4380 *__flow = flow;
4381
4382 return 0;
e3a2b7ed 4383
e3a2b7ed 4384err_free:
8914add2 4385 flow_flag_set(flow, FAILED);
e68e28b4 4386 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4387 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4388out:
4389 return err;
4390}
4391
4392static int
4393mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4394 struct flow_cls_offload *f,
226f2ca3 4395 unsigned long flags,
d11afc26 4396 struct net_device *filter_dev,
a88780a9
RD		 4397 struct mlx5e_tc_flow **flow)
4398{
4399 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4400 unsigned long flow_flags;
a88780a9
RD		 4401 int err;
4402
4403 get_flags(flags, &flow_flags);
4404
bf07aa73
PB		 4405 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4406 return -EOPNOTSUPP;
4407
f6455de0 4408 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4409 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4410 filter_dev, flow);
a88780a9 4411 else
d11afc26
OS		 4412 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4413 filter_dev, flow);
a88780a9
RD		 4414
4415 return err;
4416}
4417
553f9328
VP		 4418static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4419 struct mlx5e_rep_priv *rpriv)
4420{
4421 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4422 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4423 * function is called from NIC mode.
553f9328 4424 */
2fb15e72 4425 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4426}
4427
71d82d2a 4428int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4429 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4430{
4431 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4432 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4433 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4434 struct mlx5e_tc_flow *flow;
4435 int err = 0;
4436
7dc84de9
RD		 4437 if (!mlx5_esw_hold(priv->mdev))
4438 return -EAGAIN;
4439
4440 mlx5_esw_get(priv->mdev);
4441
c5d326b2
VB		 4442 rcu_read_lock();
4443 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4444 if (flow) {
553f9328
VP		 4445 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4446 * just return 0.
4447 */
4448 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4449 goto rcu_unlock;
553f9328 4450
a88780a9
RD		 4451 NL_SET_ERR_MSG_MOD(extack,
4452 "flow cookie already exists, ignoring");
4453 netdev_warn_once(priv->netdev,
4454 "flow cookie %lx already exists, ignoring\n",
4455 f->cookie);
0e1c1a2f 4456 err = -EEXIST;
c1aea9e1 4457 goto rcu_unlock;
a88780a9 4458 }
c1aea9e1
VB		 4459rcu_unlock:
4460 rcu_read_unlock();
4461 if (flow)
4462 goto out;
a88780a9 4463
7a978759 4464 trace_mlx5e_configure_flower(f);
d11afc26 4465 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4466 if (err)
4467 goto out;
4468
553f9328
VP		 4469 /* Flow rule offloaded to non-uplink representor sharing tc block,
4470 * set the flow's owner dev.
4471 */
4472 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4473 flow->orig_dev = dev;
4474
c5d326b2 4475 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4476 if (err)
4477 goto err_free;
4478
7dc84de9 4479 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4480 return 0;
4481
4482err_free:
5a7e5bcb 4483 mlx5e_flow_put(priv, flow);
a88780a9 4484out:
7dc84de9
RD		 4485 mlx5_esw_put(priv->mdev);
4486 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4487 return err;
4488}
4489
8f8ae895
OG		 4490static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4491{
226f2ca3
VB		 4492 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4493 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4494
226f2ca3
VB		 4495 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4496 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4497}
4498
71d82d2a 4499int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4500 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4501{
d9ee0491 4502 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4503 struct mlx5e_tc_flow *flow;
c5d326b2 4504 int err;
e3a2b7ed 4505
c5d326b2 4506 rcu_read_lock();
ab818362 4507 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4508 if (!flow || !same_flow_direction(flow, flags)) {
4509 err = -EINVAL;
4510 goto errout;
4511 }
e3a2b7ed 4512
c5d326b2
VB		 4513 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4514 * set.
4515 */
4516 if (flow_flag_test_and_set(flow, DELETED)) {
4517 err = -EINVAL;
4518 goto errout;
4519 }
05866c82 4520 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4521 rcu_read_unlock();
e3a2b7ed 4522
7a978759 4523 trace_mlx5e_delete_flower(f);
5a7e5bcb 4524 mlx5e_flow_put(priv, flow);
e3a2b7ed 4525
7dc84de9 4526 mlx5_esw_put(priv->mdev);
e3a2b7ed 4527 return 0;
c5d326b2
VB		 4528
4529errout:
4530 rcu_read_unlock();
4531 return err;
e3a2b7ed
AV		 4532}
4533
71d82d2a 4534int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4535 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4536{
04de7dda 4537 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4538 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4539 struct mlx5_eswitch *peer_esw;
aad7e08d 4540 struct mlx5e_tc_flow *flow;
aad7e08d 4541 struct mlx5_fc *counter;
316d5f72
RD		 4542 u64 lastuse = 0;
4543 u64 packets = 0;
4544 u64 bytes = 0;
5a7e5bcb 4545 int err = 0;
aad7e08d 4546
c5d326b2
VB		 4547 rcu_read_lock();
4548 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4549 tc_ht_params));
4550 rcu_read_unlock();
5a7e5bcb
VB		 4551 if (IS_ERR(flow))
4552 return PTR_ERR(flow);
4553
4554 if (!same_flow_direction(flow, flags)) {
4555 err = -EINVAL;
4556 goto errout;
4557 }
aad7e08d 4558
4c3844d9 4559 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4560 counter = mlx5e_tc_get_counter(flow);
4561 if (!counter)
5a7e5bcb 4562 goto errout;
aad7e08d 4563
316d5f72
RD		 4564 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4565 }
aad7e08d 4566
316d5f72
RD		 4567 /* Under multipath it's possible for one rule to be currently
4568 * un-offloaded while the other rule is offloaded.
4569 */
04de7dda
RD		 4570 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4571 if (!peer_esw)
4572 goto out;
4573
226f2ca3
VB		 4574 if (flow_flag_test(flow, DUP) &&
4575 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4576 u64 bytes2;
4577 u64 packets2;
4578 u64 lastuse2;
4579
4580 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4581 if (!counter)
4582 goto no_peer_counter;
04de7dda
RD		 4583 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4584
4585 bytes += bytes2;
4586 packets += packets2;
4587 lastuse = max_t(u64, lastuse, lastuse2);
4588 }
4589
316d5f72 4590no_peer_counter:
04de7dda 4591 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4592out:
4b61d3e8 4593 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4594 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4595 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4596errout:
4597 mlx5e_flow_put(priv, flow);
4598 return err;
aad7e08d
AV		 4599}
4600
1fe3e316 4601static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4602 struct netlink_ext_ack *extack)
4603{
4604 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4605 struct mlx5_eswitch *esw;
1fe3e316 4606 u32 rate_mbps = 0;
fcb64c0f 4607 u16 vport_num;
fcb64c0f
EC		 4608 int err;
4609
e401a184
EC		 4610 vport_num = rpriv->rep->vport;
4611 if (vport_num >= MLX5_VPORT_ECPF) {
4612 NL_SET_ERR_MSG_MOD(extack,
4613 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4614 return -EOPNOTSUPP;
4615 }
4616
fcb64c0f
EC		 4617 esw = priv->mdev->priv.eswitch;
4618 /* rate is given in bytes/sec.
4619 * First convert to bits/sec and then round to the nearest mbit/secs.
4620 * mbit means million bits.
4621 * Moreover, if rate is non zero we choose to configure to a minimum of
4622 * 1 mbit/sec.
4623 */
1fe3e316
PP		 4624 if (rate) {
4625 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4626 do_div(rate, 1000000);
4627 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4628 }
4629
fcb64c0f
EC		 4630 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4631 if (err)
4632 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4633
4634 return err;
4635}
4636
4637static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4638 struct flow_action *flow_action,
4639 struct netlink_ext_ack *extack)
4640{
4641 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4642 const struct flow_action_entry *act;
4643 int err;
4644 int i;
4645
4646 if (!flow_action_has_entries(flow_action)) {
4647 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4648 return -EINVAL;
4649 }
4650
4651 if (!flow_offload_has_one_action(flow_action)) {
4652 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4653 return -EOPNOTSUPP;
4654 }
4655
53eca1f3 4656 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4657 return -EOPNOTSUPP;
4658
fcb64c0f
EC		 4659 flow_action_for_each(i, act, flow_action) {
4660 switch (act->id) {
4661 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4662 if (act->police.rate_pkt_ps) {
4663 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4664 return -EOPNOTSUPP;
4665 }
fcb64c0f
EC		 4666 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4667 if (err)
4668 return err;
4669
4670 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4671 break;
4672 default:
4673 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4674 return -EOPNOTSUPP;
4675 }
4676 }
4677
4678 return 0;
4679}
4680
4681int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4682 struct tc_cls_matchall_offload *ma)
4683{
b5f814cc 4684 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4685 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4686
b5f814cc
EC		 4687 if (!mlx5_esw_qos_enabled(esw)) {
4688 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4689 return -EOPNOTSUPP;
4690 }
4691
7b83355f 4692 if (ma->common.prio != 1) {
fcb64c0f
EC		 4693 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4694 return -EINVAL;
4695 }
4696
4697 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4698}
4699
4700int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4701 struct tc_cls_matchall_offload *ma)
4702{
4703 struct netlink_ext_ack *extack = ma->common.extack;
4704
4705 return apply_police_params(priv, 0, extack);
4706}
4707
4708void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4709 struct tc_cls_matchall_offload *ma)
4710{
4711 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4712 struct rtnl_link_stats64 cur_stats;
4713 u64 dbytes;
4714 u64 dpkts;
4715
4716 cur_stats = priv->stats.vf_vport;
4717 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4718 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4719 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4720 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4721 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4722}
4723
4d8fcf21
AH		 4724static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4725 struct mlx5e_priv *peer_priv)
4726{
4727 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4728 struct mlx5e_hairpin_entry *hpe, *tmp;
4729 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4730 u16 peer_vhca_id;
4731 int bkt;
4732
4733 if (!same_hw_devs(priv, peer_priv))
4734 return;
4735
4736 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4737
b32accda 4738 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4739 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4740 if (refcount_inc_not_zero(&hpe->refcnt))
4741 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4742 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4743
4744 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4745 wait_for_completion(&hpe->res_ready);
4746 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4747 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4748
4749 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4750 }
4751}
4752
4753static int mlx5e_tc_netdev_event(struct notifier_block *this,
4754 unsigned long event, void *ptr)
4755{
4756 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4757 struct mlx5e_flow_steering *fs;
4758 struct mlx5e_priv *peer_priv;
4759 struct mlx5e_tc_table *tc;
4760 struct mlx5e_priv *priv;
4761
4762 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4763 event != NETDEV_UNREGISTER ||
4764 ndev->reg_state == NETREG_REGISTERED)
4765 return NOTIFY_DONE;
4766
4767 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4768 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4769 priv = container_of(fs, struct mlx5e_priv, fs);
4770 peer_priv = netdev_priv(ndev);
4771 if (priv == peer_priv ||
4772 !(priv->netdev->features & NETIF_F_HW_TC))
4773 return NOTIFY_DONE;
4774
4775 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4776
4777 return NOTIFY_DONE;
4778}
4779
6a064674
AL		 4780static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4781{
4782 int tc_grp_size, tc_tbl_size;
4783 u32 max_flow_counter;
4784
4785 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4786 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4787
4788 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4789
4790 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4791 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4792
4793 return tc_tbl_size;
4794}
4795
655dc3d2 4796int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4797{
acff797c 4798 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4799 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4800 struct mapping_ctx *chains_mapping;
6a064674 4801 struct mlx5_chains_attr attr = {};
4d8fcf21 4802 int err;
e8f887ac 4803
b2fdf3d0 4804 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4805 mutex_init(&tc->t_lock);
b32accda 4806 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4807 hash_init(tc->hairpin_tbl);
11c9c548 4808
4d8fcf21
AH		 4809 err = rhashtable_init(&tc->ht, &tc_ht_params);
4810 if (err)
4811 return err;
4812
9ba33339
RD		 4813 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4814
c9355682
CM		 4815 chains_mapping = mapping_create(sizeof(struct mlx5_mapped_obj),
4816 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4817 if (IS_ERR(chains_mapping)) {
4818 err = PTR_ERR(chains_mapping);
4819 goto err_mapping;
4820 }
4821 tc->mapping = chains_mapping;
4822
4823 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4824 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4825 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4826 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4827 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4828 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4829 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4830 attr.mapping = chains_mapping;
6a064674
AL		 4831
4832 tc->chains = mlx5_chains_create(dev, &attr);
4833 if (IS_ERR(tc->chains)) {
4834 err = PTR_ERR(tc->chains);
4835 goto err_chains;
4836 }
4837
aedd133d
AL		 4838 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
4839 MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4840
4d8fcf21 4841 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4842 err = register_netdevice_notifier_dev_net(priv->netdev,
4843 &tc->netdevice_nb,
4844 &tc->netdevice_nn);
4845 if (err) {
4d8fcf21
AH		 4846 tc->netdevice_nb.notifier_call = NULL;
4847 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4848 goto err_reg;
4d8fcf21
AH		 4849 }
4850
6a064674
AL		 4851 return 0;
4852
4853err_reg:
aedd133d 4854 mlx5_tc_ct_clean(tc->ct);
6a064674
AL		 4855 mlx5_chains_destroy(tc->chains);
4856err_chains:
c9355682
CM		 4857 mapping_destroy(chains_mapping);
4858err_mapping:
6a064674 4859 rhashtable_destroy(&tc->ht);
4d8fcf21 4860 return err;
e8f887ac
AV		 4861}
4862
4863static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4864{
4865 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4866 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4867
961e8979 4868 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4869 kfree(flow);
4870}
4871
655dc3d2 4872void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4873{
acff797c 4874 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4875
4d8fcf21 4876 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4877 unregister_netdevice_notifier_dev_net(priv->netdev,
4878 &tc->netdevice_nb,
4879 &tc->netdevice_nn);
4d8fcf21 4880
b2fdf3d0 4881 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4882 mutex_destroy(&tc->hairpin_tbl_lock);
4883
6a064674 4884 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4885
acff797c 4886 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4887 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4888 tc->t = NULL;
e8f887ac 4889 }
b6fac0b4 4890 mutex_destroy(&tc->t_lock);
6a064674 4891
aedd133d 4892 mlx5_tc_ct_clean(tc->ct);
c9355682 4893 mapping_destroy(tc->mapping);
6a064674 4894 mlx5_chains_destroy(tc->chains);
e8f887ac 4895}
655dc3d2
OG		 4896
4897int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4898{
d7a42ad0 4899 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4900 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4901 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4902 struct mapping_ctx *mapping;
aedd133d
AL		 4903 struct mlx5_eswitch *esw;
4904 struct mlx5e_priv *priv;
4905 int err = 0;
0a7fcb78
PB		 4906
4907 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4908 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4909 priv = netdev_priv(rpriv->netdev);
4910 esw = priv->mdev->priv.eswitch;
0a7fcb78 4911
aedd133d
AL		 4912 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4913 esw_chains(esw),
4914 &esw->offloads.mod_hdr,
4915 MLX5_FLOW_NAMESPACE_FDB);
4c3844d9 4916
2a9ab10a
CM		 4917#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4918 uplink_priv->esw_psample = mlx5_esw_sample_init(netdev_priv(priv->netdev));
4919#endif
4920
0a7fcb78
PB		 4921 mapping = mapping_create(sizeof(struct tunnel_match_key),
4922 TUNNEL_INFO_BITS_MASK, true);
4923 if (IS_ERR(mapping)) {
4924 err = PTR_ERR(mapping);
4925 goto err_tun_mapping;
4926 }
4927 uplink_priv->tunnel_mapping = mapping;
4928
8e404fef
VB		 4929 /* 0xFFF is reserved for stack devices slow path table mark */
4930 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 4931 if (IS_ERR(mapping)) {
4932 err = PTR_ERR(mapping);
4933 goto err_enc_opts_mapping;
4934 }
4935 uplink_priv->tunnel_enc_opts_mapping = mapping;
4936
4937 err = rhashtable_init(tc_ht, &tc_ht_params);
4938 if (err)
4939 goto err_ht_init;
4940
9ba33339
RD		 4941 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4942
8914add2 4943 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4944 if (IS_ERR(uplink_priv->encap)) {
4945 err = PTR_ERR(uplink_priv->encap);
8914add2 4946 goto err_register_fib_notifier;
2b6c3c1e 4947 }
8914add2 4948
2b6c3c1e 4949 return 0;
0a7fcb78 4950
8914add2
VB		 4951err_register_fib_notifier:
4952 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 4953err_ht_init:
4954 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4955err_enc_opts_mapping:
4956 mapping_destroy(uplink_priv->tunnel_mapping);
4957err_tun_mapping:
2a9ab10a
CM		 4958#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4959 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
4960#endif
aedd133d 4961 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 4962 netdev_warn(priv->netdev,
4963 "Failed to initialize tc (eswitch), err: %d", err);
4964 return err;
655dc3d2
OG		 4965}
4966
4967void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4968{
0a7fcb78
PB		 4969 struct mlx5_rep_uplink_priv *uplink_priv;
4970
0a7fcb78 4971 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 4972
8914add2
VB		 4973 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4974 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4975
0a7fcb78
PB		 4976 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4977 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 4978
2a9ab10a
CM		 4979#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4980 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
4981#endif
aedd133d 4982 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 4983}
01252a27 4984
226f2ca3 4985int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4986{
d9ee0491 4987 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4988
4989 return atomic_read(&tc_ht->nelems);
4990}
04de7dda
RD		 4991
4992void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4993{
4994 struct mlx5e_tc_flow *flow, *tmp;
4995
4996 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4997 __mlx5e_tc_del_fdb_peer_flow(flow);
4998}
b4a23329
RD		 4999
5000void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5001{
5002 struct mlx5_rep_uplink_priv *rpriv =
5003 container_of(work, struct mlx5_rep_uplink_priv,
5004 reoffload_flows_work);
5005 struct mlx5e_tc_flow *flow, *tmp;
5006
ad86755b 5007 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5008 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5009 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5010 unready_flow_del(flow);
b4a23329 5011 }
ad86755b 5012 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5013}
e2394a61
VB		 5014
5015static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5016 struct flow_cls_offload *cls_flower,
5017 unsigned long flags)
5018{
5019 switch (cls_flower->command) {
5020 case FLOW_CLS_REPLACE:
5021 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5022 flags);
5023 case FLOW_CLS_DESTROY:
5024 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5025 flags);
5026 case FLOW_CLS_STATS:
5027 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5028 flags);
5029 default:
5030 return -EOPNOTSUPP;
5031 }
5032}
5033
5034int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5035 void *cb_priv)
5036{
ec9457a6 5037 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5038 struct mlx5e_priv *priv = cb_priv;
5039
2ff349c5
RD		 5040 if (!priv->netdev || !netif_device_present(priv->netdev))
5041 return -EOPNOTSUPP;
5042
ec9457a6
RD		 5043 if (mlx5e_is_uplink_rep(priv))
5044 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5045 else
5046 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5047
e2394a61
VB		 5048 switch (type) {
5049 case TC_SETUP_CLSFLOWER:
5050 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5051 default:
5052 return -EOPNOTSUPP;
5053 }
5054}
c7569097
AL		 5055
5056bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5057 struct sk_buff *skb)
5058{
5059#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5060 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5061 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5062 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5063 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5064 struct tc_skb_ext *tc_skb_ext;
5065 int err;
5066
5067 reg_b = be32_to_cpu(cqe->ft_metadata);
5068
5069 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5070
c9355682 5071 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5072 if (err) {
5073 netdev_dbg(priv->netdev,
5074 "Couldn't find chain for chain tag: %d, err: %d\n",
5075 chain_tag, err);
5076 return false;
5077 }
5078
a91d98a0
CM		 5079 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5080 chain = mapped_obj.chain;
c7569097
AL		 5081 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
5082 if (WARN_ON(!tc_skb_ext))
5083 return false;
5084
5085 tc_skb_ext->chain = chain;
aedd133d
AL		 5086
5087 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5088 ESW_ZONE_ID_MASK;
aedd133d
AL		 5089
5090 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5091 zone_restore_id))
5092 return false;
a91d98a0
CM		 5093 } else {
5094 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5095 return false;
c7569097
AL		 5096 }
5097#endif /* CONFIG_NET_TC_SKB_EXT */
5098
5099 return true;
5100}
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