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net/mlx5: E-Switch, Refactor rule offload forward action processing
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
3f6d08d1 60#include "fs_core.h"
2c81bfd5 61#include "en/port.h"
101f4de9 62#include "en/tc_tun.h"
0a7fcb78 63#include "en/mapping.h"
4c3844d9 64#include "en/tc_ct.h"
b2fdf3d0 65#include "en/mod_hdr.h"
04de7dda 66#include "lib/devcom.h"
9272e3df 67#include "lib/geneve.h"
ae430332 68#include "lib/fs_chains.h"
7a978759 69#include "diag/en_tc_tracepoint.h"
1fe3e316 70#include <asm/div64.h>
e8f887ac 71
6a064674 72#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 73#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
226f2ca3 74#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 75
65ba8fb7 76enum {
226f2ca3
VB		 77 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
78 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
79 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 80 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 81 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
82 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
83 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
84 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
85 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
86 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
87 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 88 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 89 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
14e6b038 90 MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8,
65ba8fb7
OG		 91};
92
e4ad91f2
CM		 93#define MLX5E_TC_MAX_SPLITS 1
94
79baaec7
EB		 95/* Helper struct for accessing a struct containing list_head array.
96 * Containing struct
97 * |- Helper array
98 * [0] Helper item 0
99 * |- list_head item 0
100 * |- index (0)
101 * [1] Helper item 1
102 * |- list_head item 1
103 * |- index (1)
104 * To access the containing struct from one of the list_head items:
105 * 1. Get the helper item from the list_head item using
106 * helper item =
107 * container_of(list_head item, helper struct type, list_head field)
108 * 2. Get the contining struct from the helper item and its index in the array:
109 * containing struct =
110 * container_of(helper item, containing struct type, helper field[index])
111 */
112struct encap_flow_item {
948993f2 113 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 114 struct list_head list;
115 int index;
116};
117
e8f887ac
AV		 118struct mlx5e_tc_flow {
119 struct rhash_head node;
655dc3d2 120 struct mlx5e_priv *priv;
e8f887ac 121 u64 cookie;
226f2ca3 122 unsigned long flags;
e4ad91f2 123 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
14e6b038
EC		 124
125 /* flows sharing the same reformat object - currently mpls decap */
126 struct list_head l3_to_l2_reformat;
127 struct mlx5e_decap_entry *decap_reformat;
128
79baaec7
EB		 129 /* Flow can be associated with multiple encap IDs.
130 * The number of encaps is bounded by the number of supported
131 * destinations.
132 */
133 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 134 struct mlx5e_tc_flow *peer_flow;
b2fdf3d0 135 struct mlx5e_mod_hdr_handle *mh; /* attached mod header instance */
e4f9abbd 136 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 137 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 138 struct list_head peer; /* flows with peer flow */
b4a23329 139 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
553f9328 140 struct net_device *orig_dev; /* netdev adding flow first */
2a1f1768 141 int tmp_efi_index;
6a06c2f7 142 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 143 refcount_t refcnt;
c5d326b2 144 struct rcu_head rcu_head;
95435ad7 145 struct completion init_done;
0a7fcb78 146 int tunnel_id; /* the mapped tunnel id of this flow */
c620b772 147 struct mlx5_flow_attr *attr;
e8f887ac
AV		 148};
149
17091853 150struct mlx5e_tc_flow_parse_attr {
1f6da306 151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 152 struct net_device *filter_dev;
17091853 153 struct mlx5_flow_spec spec;
6ae4a6a5 154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
14e6b038 156 struct ethhdr eth;
17091853
OG		 157};
158
acff797c 159#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 160#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 161
8f1e0b97
PB		 162struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
163 [CHAIN_TO_REG] = {
164 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
165 .moffset = 0,
166 .mlen = 2,
167 },
0a7fcb78
PB		 168 [TUNNEL_TO_REG] = {
169 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521
PB		 170 .moffset = 1,
171 .mlen = 3,
0a7fcb78
PB		 172 .soffset = MLX5_BYTE_OFF(fte_match_param,
173 misc_parameters_2.metadata_reg_c_1),
174 },
4c3844d9 175 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 176 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 177 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
178 [MARK_TO_REG] = mark_to_reg_ct,
179 [LABELS_TO_REG] = labels_to_reg_ct,
180 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 181 /* For NIC rules we store the retore metadata directly
182 * into reg_b that is passed to SW since we don't
183 * jump between steering domains.
184 */
185 [NIC_CHAIN_TO_REG] = {
186 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
187 .moffset = 0,
188 .mlen = 2,
189 },
aedd133d 190 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 191};
192
9ba33339
RD		 193/* To avoid false lock dependency warning set the tc_ht lock
194 * class different than the lock class of the ht being used when deleting
195 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
196 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
197 * it's different than the ht->mutex here.
198 */
199static struct lock_class_key tc_ht_lock_key;
200
0a7fcb78
PB		 201static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
202
203void
204mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
205 enum mlx5e_tc_attr_to_reg type,
206 u32 data,
207 u32 mask)
208{
209 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
210 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
211 void *headers_c = spec->match_criteria;
212 void *headers_v = spec->match_value;
213 void *fmask, *fval;
214
215 fmask = headers_c + soffset;
216 fval = headers_v + soffset;
217
58ff18e1
SM		 218 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
219 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 220
221 memcpy(fmask, &mask, match_len);
222 memcpy(fval, &data, match_len);
223
224 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
225}
226
7e36feeb
PB		 227void
228mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
229 enum mlx5e_tc_attr_to_reg type,
230 u32 *data,
231 u32 *mask)
232{
233 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
234 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
235 void *headers_c = spec->match_criteria;
236 void *headers_v = spec->match_value;
237 void *fmask, *fval;
238
239 fmask = headers_c + soffset;
240 fval = headers_v + soffset;
241
242 memcpy(mask, fmask, match_len);
243 memcpy(data, fval, match_len);
244
245 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
246 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
247}
248
0a7fcb78
PB		 249int
250mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
251 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
aedd133d 252 enum mlx5_flow_namespace_type ns,
0a7fcb78
PB		 253 enum mlx5e_tc_attr_to_reg type,
254 u32 data)
255{
256 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
257 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
258 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
259 char *modact;
260 int err;
261
aedd133d 262 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 263 if (err)
264 return err;
265
266 modact = mod_hdr_acts->actions +
267 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
268
269 /* Firmware has 5bit length field and 0 means 32bits */
270 if (mlen == 4)
271 mlen = 0;
272
273 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
274 MLX5_SET(set_action_in, modact, field, mfield);
275 MLX5_SET(set_action_in, modact, offset, moffset * 8);
276 MLX5_SET(set_action_in, modact, length, mlen * 8);
277 MLX5_SET(set_action_in, modact, data, data);
278 mod_hdr_acts->num_actions++;
279
280 return 0;
281}
282
aedd133d
AL		 283static struct mlx5_tc_ct_priv *
284get_ct_priv(struct mlx5e_priv *priv)
285{
286 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
287 struct mlx5_rep_uplink_priv *uplink_priv;
288 struct mlx5e_rep_priv *uplink_rpriv;
289
e8711402 290 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 291 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
292 uplink_priv = &uplink_rpriv->uplink_priv;
293
294 return uplink_priv->ct_priv;
295 }
296
297 return priv->fs.tc.ct;
298}
299
300struct mlx5_flow_handle *
301mlx5_tc_rule_insert(struct mlx5e_priv *priv,
302 struct mlx5_flow_spec *spec,
303 struct mlx5_flow_attr *attr)
304{
305 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
306
e8711402 307 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 308 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
309
310 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
311}
312
313void
314mlx5_tc_rule_delete(struct mlx5e_priv *priv,
315 struct mlx5_flow_handle *rule,
316 struct mlx5_flow_attr *attr)
317{
318 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
319
e8711402 320 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 321 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
322
323 return;
324 }
325
326 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
327}
328
77ab67b7
OG		 329struct mlx5e_hairpin {
330 struct mlx5_hairpin *pair;
331
332 struct mlx5_core_dev *func_mdev;
3f6d08d1 333 struct mlx5e_priv *func_priv;
77ab67b7
OG		 334 u32 tdn;
335 u32 tirn;
3f6d08d1
OG		 336
337 int num_channels;
338 struct mlx5e_rqt indir_rqt;
339 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
340 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 341};
342
5c65c564
OG		 343struct mlx5e_hairpin_entry {
344 /* a node of a hash table which keeps all the hairpin entries */
345 struct hlist_node hairpin_hlist;
346
73edca73
VB		 347 /* protects flows list */
348 spinlock_t flows_lock;
5c65c564
OG		 349 /* flows sharing the same hairpin */
350 struct list_head flows;
db76ca24
VB		 351 /* hpe's that were not fully initialized when dead peer update event
352 * function traversed them.
353 */
354 struct list_head dead_peer_wait_list;
5c65c564 355
d8822868 356 u16 peer_vhca_id;
106be53b 357 u8 prio;
5c65c564 358 struct mlx5e_hairpin *hp;
e4f9abbd 359 refcount_t refcnt;
db76ca24 360 struct completion res_ready;
5c65c564
OG		 361};
362
5a7e5bcb
VB		 363static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
364 struct mlx5e_tc_flow *flow);
365
366static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
367{
368 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
369 return ERR_PTR(-EINVAL);
370 return flow;
371}
372
373static void mlx5e_flow_put(struct mlx5e_priv *priv,
374 struct mlx5e_tc_flow *flow)
375{
376 if (refcount_dec_and_test(&flow->refcnt)) {
377 mlx5e_tc_del_flow(priv, flow);
c5d326b2 378 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 379 }
380}
381
226f2ca3
VB		 382static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
383{
384 /* Complete all memory stores before setting bit. */
385 smp_mb__before_atomic();
386 set_bit(flag, &flow->flags);
387}
388
389#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
390
c5d326b2
VB		 391static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
392 unsigned long flag)
393{
394 /* test_and_set_bit() provides all necessary barriers */
395 return test_and_set_bit(flag, &flow->flags);
396}
397
398#define flow_flag_test_and_set(flow, flag) \
399 __flow_flag_test_and_set(flow, \
400 MLX5E_TC_FLOW_FLAG_##flag)
401
226f2ca3
VB		 402static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
403{
404 /* Complete all memory stores before clearing bit. */
405 smp_mb__before_atomic();
406 clear_bit(flag, &flow->flags);
407}
408
409#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
410 MLX5E_TC_FLOW_FLAG_##flag)
411
412static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
413{
414 bool ret = test_bit(flag, &flow->flags);
415
416 /* Read fields of flow structure only after checking flags. */
417 smp_mb__after_atomic();
418 return ret;
419}
420
421#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
422 MLX5E_TC_FLOW_FLAG_##flag)
423
aedd133d 424bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 425{
426 return flow_flag_test(flow, ESWITCH);
427}
428
84179981
PB		 429static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
430{
431 return flow_flag_test(flow, FT);
432}
433
226f2ca3
VB		 434static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
435{
436 return flow_flag_test(flow, OFFLOADED);
437}
438
b2fdf3d0 439static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 440{
b2fdf3d0
PB		 441 return mlx5e_is_eswitch_flow(flow) ?
442 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 443}
444
dd58edc3 445static struct mod_hdr_tbl *
b2fdf3d0 446get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 447{
448 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
449
b2fdf3d0
PB		 450 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
451 &esw->offloads.mod_hdr :
dd58edc3
VB		 452 &priv->fs.tc.mod_hdr;
453}
454
11c9c548
OG		 455static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
456 struct mlx5e_tc_flow *flow,
457 struct mlx5e_tc_flow_parse_attr *parse_attr)
458{
b2fdf3d0
PB		 459 struct mlx5_modify_hdr *modify_hdr;
460 struct mlx5e_mod_hdr_handle *mh;
11c9c548 461
b2fdf3d0
PB		 462 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
463 get_flow_name_space(flow),
464 &parse_attr->mod_hdr_acts);
465 if (IS_ERR(mh))
466 return PTR_ERR(mh);
11c9c548 467
b2fdf3d0 468 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 469 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 470 flow->mh = mh;
11c9c548
OG		 471
472 return 0;
11c9c548
OG		 473}
474
475static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
476 struct mlx5e_tc_flow *flow)
477{
5a7e5bcb 478 /* flow wasn't fully initialized */
dd58edc3 479 if (!flow->mh)
5a7e5bcb
VB		 480 return;
481
b2fdf3d0
PB		 482 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
483 flow->mh);
dd58edc3 484 flow->mh = NULL;
11c9c548
OG		 485}
486
77ab67b7
OG		 487static
488struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
489{
490 struct net_device *netdev;
491 struct mlx5e_priv *priv;
492
493 netdev = __dev_get_by_index(net, ifindex);
494 priv = netdev_priv(netdev);
495 return priv->mdev;
496}
497
498static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
499{
e0b4b472 500 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 501 void *tirc;
502 int err;
503
504 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
505 if (err)
506 goto alloc_tdn_err;
507
508 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
509
510 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 511 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 512 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
513
e0b4b472 514 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 515 if (err)
516 goto create_tir_err;
517
518 return 0;
519
520create_tir_err:
521 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
522alloc_tdn_err:
523 return err;
524}
525
526static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
527{
528 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
529 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
530}
531
3f6d08d1
OG		 532static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
533{
534 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
535 struct mlx5e_priv *priv = hp->func_priv;
536 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
537
538 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
539 hp->num_channels);
540
541 for (i = 0; i < sz; i++) {
542 ix = i;
bbeb53b8 543 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 544 ix = mlx5e_bits_invert(i, ilog2(sz));
545 ix = indirection_rqt[ix];
546 rqn = hp->pair->rqn[ix];
547 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
548 }
549}
550
551static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
552{
553 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
554 struct mlx5e_priv *priv = hp->func_priv;
555 struct mlx5_core_dev *mdev = priv->mdev;
556 void *rqtc;
557 u32 *in;
558
559 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
560 in = kvzalloc(inlen, GFP_KERNEL);
561 if (!in)
562 return -ENOMEM;
563
564 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
565
566 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
567 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
568
569 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
570
571 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
572 if (!err)
573 hp->indir_rqt.enabled = true;
574
575 kvfree(in);
576 return err;
577}
578
579static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
580{
581 struct mlx5e_priv *priv = hp->func_priv;
582 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
583 int tt, i, err;
584 void *tirc;
585
586 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 587 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
588
3f6d08d1
OG		 589 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
590 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
591
592 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
593 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
594 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 595 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
596
3f6d08d1 597 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 598 &hp->indir_tirn[tt]);
3f6d08d1
OG		 599 if (err) {
600 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
601 goto err_destroy_tirs;
602 }
603 }
604 return 0;
605
606err_destroy_tirs:
607 for (i = 0; i < tt; i++)
608 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
609 return err;
610}
611
612static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
613{
614 int tt;
615
616 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
617 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
618}
619
620static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
621 struct ttc_params *ttc_params)
622{
623 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
624 int tt;
625
626 memset(ttc_params, 0, sizeof(*ttc_params));
627
628 ttc_params->any_tt_tirn = hp->tirn;
629
630 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
631 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
632
6412bb39 633 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 634 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
635 ft_attr->prio = MLX5E_TC_PRIO;
636}
637
638static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
639{
640 struct mlx5e_priv *priv = hp->func_priv;
641 struct ttc_params ttc_params;
642 int err;
643
644 err = mlx5e_hairpin_create_indirect_rqt(hp);
645 if (err)
646 return err;
647
648 err = mlx5e_hairpin_create_indirect_tirs(hp);
649 if (err)
650 goto err_create_indirect_tirs;
651
652 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
653 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
654 if (err)
655 goto err_create_ttc_table;
656
657 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
658 hp->num_channels, hp->ttc.ft.t->id);
659
660 return 0;
661
662err_create_ttc_table:
663 mlx5e_hairpin_destroy_indirect_tirs(hp);
664err_create_indirect_tirs:
665 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
666
667 return err;
668}
669
670static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
671{
672 struct mlx5e_priv *priv = hp->func_priv;
673
674 mlx5e_destroy_ttc_table(priv, &hp->ttc);
675 mlx5e_hairpin_destroy_indirect_tirs(hp);
676 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
677}
678
77ab67b7
OG		 679static struct mlx5e_hairpin *
680mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
681 int peer_ifindex)
682{
683 struct mlx5_core_dev *func_mdev, *peer_mdev;
684 struct mlx5e_hairpin *hp;
685 struct mlx5_hairpin *pair;
686 int err;
687
688 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
689 if (!hp)
690 return ERR_PTR(-ENOMEM);
691
692 func_mdev = priv->mdev;
693 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
694
695 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
696 if (IS_ERR(pair)) {
697 err = PTR_ERR(pair);
698 goto create_pair_err;
699 }
700 hp->pair = pair;
701 hp->func_mdev = func_mdev;
3f6d08d1
OG		 702 hp->func_priv = priv;
703 hp->num_channels = params->num_channels;
77ab67b7
OG		 704
705 err = mlx5e_hairpin_create_transport(hp);
706 if (err)
707 goto create_transport_err;
708
3f6d08d1
OG		 709 if (hp->num_channels > 1) {
710 err = mlx5e_hairpin_rss_init(hp);
711 if (err)
712 goto rss_init_err;
713 }
714
77ab67b7
OG		 715 return hp;
716
3f6d08d1
OG		 717rss_init_err:
718 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 719create_transport_err:
720 mlx5_core_hairpin_destroy(hp->pair);
721create_pair_err:
722 kfree(hp);
723 return ERR_PTR(err);
724}
725
726static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
727{
3f6d08d1
OG		 728 if (hp->num_channels > 1)
729 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 730 mlx5e_hairpin_destroy_transport(hp);
731 mlx5_core_hairpin_destroy(hp->pair);
732 kvfree(hp);
733}
734
106be53b
OG		 735static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
736{
737 return (peer_vhca_id << 16 | prio);
738}
739
5c65c564 740static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 741 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 742{
743 struct mlx5e_hairpin_entry *hpe;
106be53b 744 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 745
746 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 747 hairpin_hlist, hash_key) {
e4f9abbd
VB		 748 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
749 refcount_inc(&hpe->refcnt);
5c65c564 750 return hpe;
e4f9abbd 751 }
5c65c564
OG		 752 }
753
754 return NULL;
755}
756
e4f9abbd
VB		 757static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
758 struct mlx5e_hairpin_entry *hpe)
759{
760 /* no more hairpin flows for us, release the hairpin pair */
b32accda 761 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 762 return;
b32accda
VB		 763 hash_del(&hpe->hairpin_hlist);
764 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 765
db76ca24
VB		 766 if (!IS_ERR_OR_NULL(hpe->hp)) {
767 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
768 dev_name(hpe->hp->pair->peer_mdev->device));
769
770 mlx5e_hairpin_destroy(hpe->hp);
771 }
e4f9abbd
VB		 772
773 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 774 kfree(hpe);
775}
776
106be53b
OG		 777#define UNKNOWN_MATCH_PRIO 8
778
779static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 780 struct mlx5_flow_spec *spec, u8 *match_prio,
781 struct netlink_ext_ack *extack)
106be53b
OG		 782{
783 void *headers_c, *headers_v;
784 u8 prio_val, prio_mask = 0;
785 bool vlan_present;
786
787#ifdef CONFIG_MLX5_CORE_EN_DCB
788 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 789 NL_SET_ERR_MSG_MOD(extack,
790 "only PCP trust state supported for hairpin");
106be53b
OG		 791 return -EOPNOTSUPP;
792 }
793#endif
794 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
795 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
796
797 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
798 if (vlan_present) {
799 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
800 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
801 }
802
803 if (!vlan_present || !prio_mask) {
804 prio_val = UNKNOWN_MATCH_PRIO;
805 } else if (prio_mask != 0x7) {
e98bedf5
EB		 806 NL_SET_ERR_MSG_MOD(extack,
807 "masked priority match not supported for hairpin");
106be53b
OG		 808 return -EOPNOTSUPP;
809 }
810
811 *match_prio = prio_val;
812 return 0;
813}
814
5c65c564
OG		 815static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
816 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 817 struct mlx5e_tc_flow_parse_attr *parse_attr,
818 struct netlink_ext_ack *extack)
5c65c564 819{
98b66cb1 820 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 821 struct mlx5_hairpin_params params;
d8822868 822 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 823 struct mlx5e_hairpin_entry *hpe;
824 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 825 u64 link_speed64;
826 u32 link_speed;
106be53b 827 u8 match_prio;
d8822868 828 u16 peer_id;
5c65c564
OG		 829 int err;
830
d8822868
OG		 831 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
832 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 833 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 834 return -EOPNOTSUPP;
835 }
836
d8822868 837 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 838 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
839 extack);
106be53b
OG		 840 if (err)
841 return err;
b32accda
VB		 842
843 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 844 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 845 if (hpe) {
846 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
847 wait_for_completion(&hpe->res_ready);
848
849 if (IS_ERR(hpe->hp)) {
850 err = -EREMOTEIO;
851 goto out_err;
852 }
5c65c564 853 goto attach_flow;
db76ca24 854 }
5c65c564
OG		 855
856 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 857 if (!hpe) {
db76ca24
VB		 858 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
859 return -ENOMEM;
b32accda 860 }
5c65c564 861
73edca73 862 spin_lock_init(&hpe->flows_lock);
5c65c564 863 INIT_LIST_HEAD(&hpe->flows);
db76ca24 864 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 865 hpe->peer_vhca_id = peer_id;
106be53b 866 hpe->prio = match_prio;
e4f9abbd 867 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 868 init_completion(&hpe->res_ready);
869
870 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
871 hash_hairpin_info(peer_id, match_prio));
872 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 873
874 params.log_data_size = 15;
875 params.log_data_size = min_t(u8, params.log_data_size,
876 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
877 params.log_data_size = max_t(u8, params.log_data_size,
878 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 879
eb9180f7
OG		 880 params.log_num_packets = params.log_data_size -
881 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
882 params.log_num_packets = min_t(u8, params.log_num_packets,
883 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
884
885 params.q_counter = priv->q_counter;
3f6d08d1 886 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 887 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 888 link_speed = max_t(u32, link_speed, 50000);
889 link_speed64 = link_speed;
890 do_div(link_speed64, 50000);
891 params.num_channels = link_speed64;
892
5c65c564 893 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 894 hpe->hp = hp;
895 complete_all(&hpe->res_ready);
5c65c564
OG		 896 if (IS_ERR(hp)) {
897 err = PTR_ERR(hp);
db76ca24 898 goto out_err;
5c65c564
OG		 899 }
900
eb9180f7 901 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 902 hp->tirn, hp->pair->rqn[0],
903 dev_name(hp->pair->peer_mdev->device),
eb9180f7 904 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 905
5c65c564 906attach_flow:
3f6d08d1 907 if (hpe->hp->num_channels > 1) {
226f2ca3 908 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 909 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 910 } else {
c620b772 911 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 912 }
b32accda 913
e4f9abbd 914 flow->hpe = hpe;
73edca73 915 spin_lock(&hpe->flows_lock);
5c65c564 916 list_add(&flow->hairpin, &hpe->flows);
73edca73 917 spin_unlock(&hpe->flows_lock);
3f6d08d1 918
5c65c564
OG		 919 return 0;
920
db76ca24
VB		 921out_err:
922 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 923 return err;
924}
925
926static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
927 struct mlx5e_tc_flow *flow)
928{
5a7e5bcb 929 /* flow wasn't fully initialized */
e4f9abbd 930 if (!flow->hpe)
5a7e5bcb
VB		 931 return;
932
73edca73 933 spin_lock(&flow->hpe->flows_lock);
5c65c564 934 list_del(&flow->hairpin);
73edca73
VB		 935 spin_unlock(&flow->hpe->flows_lock);
936
e4f9abbd
VB		 937 mlx5e_hairpin_put(priv, flow->hpe);
938 flow->hpe = NULL;
5c65c564
OG		 939}
940
08247066
AL		 941struct mlx5_flow_handle *
942mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
943 struct mlx5_flow_spec *spec,
c620b772 944 struct mlx5_flow_attr *attr)
e8f887ac 945{
08247066 946 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 947 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 948 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 949 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 950 struct mlx5_flow_destination dest[2] = {};
66958ed9 951 struct mlx5_flow_act flow_act = {
3bc4b7bf 952 .action = attr->action,
bb0ee7dc 953 .flags = FLOW_ACT_NO_APPEND,
66958ed9 954 };
08247066 955 struct mlx5_flow_handle *rule;
c7569097 956 struct mlx5_flow_table *ft;
08247066 957 int dest_ix = 0;
e8f887ac 958
bb0ee7dc 959 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 960 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 961
aedd133d
AL		 962 if (attr->dest_ft) {
963 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
964 dest[dest_ix].ft = attr->dest_ft;
965 dest_ix++;
966 } else if (nic_attr->hairpin_ft) {
08247066 967 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 968 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 969 dest_ix++;
c620b772 970 } else if (nic_attr->hairpin_tirn) {
08247066 971 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 972 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 973 dest_ix++;
3f6d08d1
OG		 974 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
975 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 976 if (attr->dest_chain) {
977 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
978 attr->dest_chain, 1,
979 MLX5E_TC_FT_LEVEL);
980 if (IS_ERR(dest[dest_ix].ft))
981 return ERR_CAST(dest[dest_ix].ft);
982 } else {
983 dest[dest_ix].ft = priv->fs.vlan.ft.t;
984 }
3f6d08d1 985 dest_ix++;
5c65c564 986 }
aad7e08d 987
c7569097
AL		 988 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
989 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
990 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
991
08247066 992 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 993 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 994 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 995 dest_ix++;
aad7e08d
AV		 996 }
997
08247066 998 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 999 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 1000
6a064674
AL		 1001 mutex_lock(&tc->t_lock);
1002 if (IS_ERR_OR_NULL(tc->t)) {
1003 /* Create the root table here if doesn't exist yet */
1004 tc->t =
c7569097 1005 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 1006
1007 if (IS_ERR(tc->t)) {
1008 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 1009 netdev_err(priv->netdev,
1010 "Failed to create tc offload table\n");
c7569097
AL		 1011 rule = ERR_CAST(priv->fs.tc.t);
1012 goto err_ft_get;
e8f887ac 1013 }
e8f887ac 1014 }
08247066 1015 mutex_unlock(&tc->t_lock);
e8f887ac 1016
aedd133d
AL		 1017 if (attr->chain || attr->prio)
1018 ft = mlx5_chains_get_table(nic_chains,
1019 attr->chain, attr->prio,
1020 MLX5E_TC_FT_LEVEL);
1021 else
1022 ft = attr->ft;
1023
c7569097
AL		 1024 if (IS_ERR(ft)) {
1025 rule = ERR_CAST(ft);
1026 goto err_ft_get;
1027 }
1028
c620b772 1029 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1030 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1031
c7569097 1032 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1033 &flow_act, dest, dest_ix);
1034 if (IS_ERR(rule))
c7569097 1035 goto err_rule;
08247066
AL		 1036
1037 return rule;
c7569097
AL		 1038
1039err_rule:
aedd133d
AL		 1040 if (attr->chain || attr->prio)
1041 mlx5_chains_put_table(nic_chains,
1042 attr->chain, attr->prio,
1043 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1044err_ft_get:
1045 if (attr->dest_chain)
1046 mlx5_chains_put_table(nic_chains,
1047 attr->dest_chain, 1,
1048 MLX5E_TC_FT_LEVEL);
1049
1050 return ERR_CAST(rule);
08247066
AL		 1051}
1052
1053static int
1054mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1055 struct mlx5e_tc_flow_parse_attr *parse_attr,
1056 struct mlx5e_tc_flow *flow,
1057 struct netlink_ext_ack *extack)
1058{
c620b772 1059 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1060 struct mlx5_core_dev *dev = priv->mdev;
1061 struct mlx5_fc *counter = NULL;
1062 int err;
1063
1064 if (flow_flag_test(flow, HAIRPIN)) {
1065 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1066 if (err)
1067 return err;
1068 }
1069
1070 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1071 counter = mlx5_fc_create(dev, true);
1072 if (IS_ERR(counter))
1073 return PTR_ERR(counter);
1074
1075 attr->counter = counter;
1076 }
1077
1078 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1079 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1080 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1081 if (err)
1082 return err;
1083 }
1084
aedd133d
AL		 1085 if (flow_flag_test(flow, CT))
1086 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1087 attr, &parse_attr->mod_hdr_acts);
1088 else
1089 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1090 attr);
aad7e08d 1091
a2b7189b 1092 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1093}
1094
08247066 1095void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1096 struct mlx5_flow_handle *rule,
1097 struct mlx5_flow_attr *attr)
08247066 1098{
c7569097
AL		 1099 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1100
08247066 1101 mlx5_del_flow_rules(rule);
c7569097 1102
aedd133d
AL		 1103 if (attr->chain || attr->prio)
1104 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1105 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1106
1107 if (attr->dest_chain)
1108 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1109 MLX5E_TC_FT_LEVEL);
08247066
AL		 1110}
1111
d85cdccb
OG		 1112static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1113 struct mlx5e_tc_flow *flow)
1114{
c620b772 1115 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1116 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1117
c7569097
AL		 1118 flow_flag_clear(flow, OFFLOADED);
1119
aedd133d
AL		 1120 if (flow_flag_test(flow, CT))
1121 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1122 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1123 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1124
c7569097
AL		 1125 /* Remove root table if no rules are left to avoid
1126 * extra steering hops.
1127 */
b6fac0b4 1128 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1129 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1130 !IS_ERR_OR_NULL(tc->t)) {
1131 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1132 priv->fs.tc.t = NULL;
1133 }
b6fac0b4 1134 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1135
aedd133d
AL		 1136 kvfree(attr->parse_attr);
1137
513f8f7f 1138 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1139 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1140
aedd133d
AL		 1141 mlx5_fc_destroy(priv->mdev, attr->counter);
1142
226f2ca3 1143 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1144 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1145
1146 kfree(flow->attr);
d85cdccb
OG		 1147}
1148
aa0cbbae 1149static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1150 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1151
3c37745e 1152static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1153 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1154 struct net_device *mirred_dev,
1155 int out_index,
8c4dc42b 1156 struct netlink_ext_ack *extack,
0ad060ee
RD		 1157 struct net_device **encap_dev,
1158 bool *encap_valid);
14e6b038
EC		 1159static int mlx5e_attach_decap(struct mlx5e_priv *priv,
1160 struct mlx5e_tc_flow *flow,
1161 struct netlink_ext_ack *extack);
1162static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1163 struct mlx5e_tc_flow *flow);
3c37745e 1164
6d2a3ed0
OG		 1165static struct mlx5_flow_handle *
1166mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1167 struct mlx5e_tc_flow *flow,
1168 struct mlx5_flow_spec *spec,
c620b772 1169 struct mlx5_flow_attr *attr)
6d2a3ed0 1170{
1ef3018f 1171 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1172 struct mlx5_flow_handle *rule;
4c3844d9 1173
89e39467
PB		 1174 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1175 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1176
1ef3018f
PB		 1177 if (flow_flag_test(flow, CT)) {
1178 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1179
aedd133d
AL		 1180 return mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
1181 flow, spec, attr,
1ef3018f
PB		 1182 mod_hdr_acts);
1183 }
6d2a3ed0
OG		 1184
1185 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1186 if (IS_ERR(rule))
1187 return rule;
1188
c620b772 1189 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1190 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1191 if (IS_ERR(flow->rule[1])) {
1192 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1193 return flow->rule[1];
1194 }
1195 }
1196
6d2a3ed0
OG		 1197 return rule;
1198}
1199
1200static void
1201mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1202 struct mlx5e_tc_flow *flow,
c620b772 1203 struct mlx5_flow_attr *attr)
6d2a3ed0 1204{
226f2ca3 1205 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1206
89e39467
PB		 1207 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1208 goto offload_rule_0;
1209
4c3844d9 1210 if (flow_flag_test(flow, CT)) {
aedd133d 1211 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1212 return;
1213 }
1214
c620b772 1215 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1216 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1217
89e39467 1218offload_rule_0:
6d2a3ed0
OG		 1219 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1220}
1221
5dbe906f
PB		 1222static struct mlx5_flow_handle *
1223mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1224 struct mlx5e_tc_flow *flow,
178f69b4 1225 struct mlx5_flow_spec *spec)
5dbe906f 1226{
c620b772 1227 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1228 struct mlx5_flow_handle *rule;
1229
c620b772
AL		 1230 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1231 if (!slow_attr)
1232 return ERR_PTR(-ENOMEM);
5dbe906f 1233
c620b772
AL		 1234 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1235 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1236 slow_attr->esw_attr->split_count = 0;
1237 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1238
1239 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1240 if (!IS_ERR(rule))
226f2ca3 1241 flow_flag_set(flow, SLOW);
5dbe906f 1242
c620b772
AL		 1243 kfree(slow_attr);
1244
5dbe906f
PB		 1245 return rule;
1246}
1247
1248static void
1249mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1250 struct mlx5e_tc_flow *flow)
5dbe906f 1251{
c620b772 1252 struct mlx5_flow_attr *slow_attr;
178f69b4 1253
c620b772 1254 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1255 if (!slow_attr) {
1256 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1257 return;
1258 }
c620b772
AL		 1259
1260 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1261 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1262 slow_attr->esw_attr->split_count = 0;
1263 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1264 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1265 flow_flag_clear(flow, SLOW);
c620b772 1266 kfree(slow_attr);
5dbe906f
PB		 1267}
1268
ad86755b
VB		 1269/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1270 * function.
1271 */
1272static void unready_flow_add(struct mlx5e_tc_flow *flow,
1273 struct list_head *unready_flows)
1274{
1275 flow_flag_set(flow, NOT_READY);
1276 list_add_tail(&flow->unready, unready_flows);
1277}
1278
1279/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1280 * function.
1281 */
1282static void unready_flow_del(struct mlx5e_tc_flow *flow)
1283{
1284 list_del(&flow->unready);
1285 flow_flag_clear(flow, NOT_READY);
1286}
1287
b4a23329
RD		 1288static void add_unready_flow(struct mlx5e_tc_flow *flow)
1289{
1290 struct mlx5_rep_uplink_priv *uplink_priv;
1291 struct mlx5e_rep_priv *rpriv;
1292 struct mlx5_eswitch *esw;
1293
1294 esw = flow->priv->mdev->priv.eswitch;
1295 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1296 uplink_priv = &rpriv->uplink_priv;
1297
ad86755b
VB		 1298 mutex_lock(&uplink_priv->unready_flows_lock);
1299 unready_flow_add(flow, &uplink_priv->unready_flows);
1300 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1301}
1302
1303static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1304{
ad86755b
VB		 1305 struct mlx5_rep_uplink_priv *uplink_priv;
1306 struct mlx5e_rep_priv *rpriv;
1307 struct mlx5_eswitch *esw;
1308
1309 esw = flow->priv->mdev->priv.eswitch;
1310 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1311 uplink_priv = &rpriv->uplink_priv;
1312
1313 mutex_lock(&uplink_priv->unready_flows_lock);
1314 unready_flow_del(flow);
1315 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1316}
1317
c83954ab 1318static int
74491de9 1319mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1320 struct mlx5e_tc_flow *flow,
1321 struct netlink_ext_ack *extack)
adb4c123
OG		 1322{
1323 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1324 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1325 struct mlx5e_tc_flow_parse_attr *parse_attr;
1326 struct mlx5_flow_attr *attr = flow->attr;
1327 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1328 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1329 struct mlx5e_rep_priv *rpriv;
1330 struct mlx5e_priv *out_priv;
0ad060ee 1331 bool encap_valid = true;
39ac237c 1332 u32 max_prio, max_chain;
0ad060ee 1333 int err = 0;
f493f155 1334 int out_index;
8b32580d 1335
84179981
PB		 1336 /* We check chain range only for tc flows.
1337 * For ft flows, we checked attr->chain was originally 0 and set it to
1338 * FDB_FT_CHAIN which is outside tc range.
1339 * See mlx5e_rep_setup_ft_cb().
1340 */
ae430332 1341 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1342 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1343 NL_SET_ERR_MSG_MOD(extack,
1344 "Requested chain is out of supported range");
5a7e5bcb 1345 return -EOPNOTSUPP;
bf07aa73
PB		 1346 }
1347
ae430332 1348 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1349 if (attr->prio > max_prio) {
61644c3d
RD		 1350 NL_SET_ERR_MSG_MOD(extack,
1351 "Requested priority is out of supported range");
5a7e5bcb 1352 return -EOPNOTSUPP;
bf07aa73 1353 }
e52c2802 1354
14e6b038
EC		 1355 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1356 err = mlx5e_attach_decap(priv, flow, extack);
1357 if (err)
1358 return err;
1359 }
1360
c620b772
AL		 1361 parse_attr = attr->parse_attr;
1362 esw_attr = attr->esw_attr;
1363
f493f155 1364 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1365 int mirred_ifindex;
1366
c620b772 1367 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1368 continue;
1369
7040632d 1370 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1371 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1372 mirred_ifindex);
733d4f36 1373 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1374 extack, &encap_dev, &encap_valid);
1375 if (err)
5a7e5bcb 1376 return err;
0ad060ee 1377
3c37745e
OG		 1378 out_priv = netdev_priv(encap_dev);
1379 rpriv = out_priv->ppriv;
c620b772
AL		 1380 esw_attr->dests[out_index].rep = rpriv->rep;
1381 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1382 }
1383
8b32580d 1384 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1385 if (err)
5a7e5bcb 1386 return err;
adb4c123 1387
d5a3c2b6
RD		 1388 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1389 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1a9527bb 1390 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1391 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1392 if (err)
5a7e5bcb 1393 return err;
d7e75a32
OG		 1394 }
1395
b8aee822 1396 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1397 counter = mlx5_fc_create(esw_attr->counter_dev, true);
5a7e5bcb
VB		 1398 if (IS_ERR(counter))
1399 return PTR_ERR(counter);
b8aee822
MB		 1400
1401 attr->counter = counter;
1402 }
1403
0ad060ee
RD		 1404 /* we get here if one of the following takes place:
1405 * (1) there's no error
1406 * (2) there's an encap action and we don't have valid neigh
3c37745e 1407 */
bc1d75fa 1408 if (!encap_valid)
178f69b4 1409 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1410 else
6d2a3ed0 1411 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1412
5a7e5bcb
VB		 1413 if (IS_ERR(flow->rule[0]))
1414 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1415 else
1416 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1417
1418 return 0;
aa0cbbae 1419}
d85cdccb 1420
9272e3df
YK		 1421static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1422{
c620b772 1423 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1424 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1425 spec->match_value,
1426 misc_parameters_3);
1427 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1428 headers_v,
1429 geneve_tlv_option_0_data);
1430
1431 return !!geneve_tlv_opt_0_data;
1432}
1433
d85cdccb
OG		 1434static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1435 struct mlx5e_tc_flow *flow)
1436{
1437 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1438 struct mlx5_flow_attr *attr = flow->attr;
f493f155 1439 int out_index;
d85cdccb 1440
0a7fcb78
PB		 1441 mlx5e_put_flow_tunnel_id(flow);
1442
12a240a4 1443 if (flow_flag_test(flow, NOT_READY))
b4a23329 1444 remove_unready_flow(flow);
ef06c9ee 1445
226f2ca3
VB		 1446 if (mlx5e_is_offloaded_flow(flow)) {
1447 if (flow_flag_test(flow, SLOW))
178f69b4 1448 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1449 else
1450 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1451 }
d85cdccb 1452
9272e3df
YK		 1453 if (mlx5_flow_has_geneve_opt(flow))
1454 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1455
513f8f7f 1456 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1457
f493f155 1458 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
c620b772 1459 if (attr->esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1460 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1461 kfree(attr->parse_attr->tun_info[out_index]);
1462 }
f493f155 1463 kvfree(attr->parse_attr);
d7e75a32 1464
aedd133d 1465 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1466
513f8f7f 1467 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1468 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1469
1470 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
c620b772 1471 mlx5_fc_destroy(attr->esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1472
1473 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1474 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1475
1476 kfree(flow->attr);
d85cdccb
OG		 1477}
1478
232c0013 1479void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1480 struct mlx5e_encap_entry *e,
1481 struct list_head *flow_list)
232c0013 1482{
3c37745e 1483 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1484 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0 1485 struct mlx5_flow_handle *rule;
c620b772 1486 struct mlx5_flow_attr *attr;
6d2a3ed0 1487 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1488 struct mlx5e_tc_flow *flow;
1489 int err;
1490
2b688ea5
MG		 1491 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1492 e->reformat_type,
1493 e->encap_size, e->encap_header,
1494 MLX5_FLOW_NAMESPACE_FDB);
1495 if (IS_ERR(e->pkt_reformat)) {
1496 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1497 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1498 return;
1499 }
1500 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1501 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1502
2a1f1768 1503 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1504 bool all_flow_encaps_valid = true;
1505 int i;
1506
95435ad7
VB		 1507 if (!mlx5e_is_offloaded_flow(flow))
1508 continue;
c620b772
AL		 1509 attr = flow->attr;
1510 esw_attr = attr->esw_attr;
1511 spec = &attr->parse_attr->spec;
6d2a3ed0 1512
2b688ea5 1513 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1514 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1515 /* Flow can be associated with multiple encap entries.
1516 * Before offloading the flow verify that all of them have
1517 * a valid neighbour.
1518 */
1519 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1520 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1521 continue;
1522 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1523 all_flow_encaps_valid = false;
1524 break;
1525 }
1526 }
1527 /* Do not offload flows with unresolved neighbors */
1528 if (!all_flow_encaps_valid)
2a1f1768 1529 continue;
5dbe906f 1530 /* update from slow path rule to encap rule */
c620b772 1531 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, attr);
6d2a3ed0
OG		 1532 if (IS_ERR(rule)) {
1533 err = PTR_ERR(rule);
232c0013
HHZ		 1534 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1535 err);
2a1f1768 1536 continue;
232c0013 1537 }
5dbe906f 1538
178f69b4 1539 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1540 flow->rule[0] = rule;
226f2ca3
VB		 1541 /* was unset when slow path rule removed */
1542 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1543 }
1544}
1545
1546void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1547 struct mlx5e_encap_entry *e,
1548 struct list_head *flow_list)
232c0013 1549{
3c37745e 1550 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1551 struct mlx5_esw_flow_attr *esw_attr;
5dbe906f 1552 struct mlx5_flow_handle *rule;
c620b772 1553 struct mlx5_flow_attr *attr;
5dbe906f 1554 struct mlx5_flow_spec *spec;
232c0013 1555 struct mlx5e_tc_flow *flow;
5dbe906f 1556 int err;
232c0013 1557
2a1f1768 1558 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1559 if (!mlx5e_is_offloaded_flow(flow))
1560 continue;
c620b772
AL		 1561 attr = flow->attr;
1562 esw_attr = attr->esw_attr;
1563 spec = &attr->parse_attr->spec;
5dbe906f
PB		 1564
1565 /* update from encap rule to slow path rule */
178f69b4 1566 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1567 /* mark the flow's encap dest as non-valid */
c620b772 1568 esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1569
1570 if (IS_ERR(rule)) {
1571 err = PTR_ERR(rule);
1572 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1573 err);
2a1f1768 1574 continue;
5dbe906f
PB		 1575 }
1576
c620b772 1577 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
5dbe906f 1578 flow->rule[0] = rule;
226f2ca3
VB		 1579 /* was unset when fast path rule removed */
1580 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1581 }
1582
61c806da
OG		 1583 /* we know that the encap is valid */
1584 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1585 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1586}
1587
b8aee822
MB		 1588static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1589{
c620b772 1590 return flow->attr->counter;
b8aee822
MB		 1591}
1592
2a1f1768
VB		 1593/* Takes reference to all flows attached to encap and adds the flows to
1594 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1595 */
1596void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1597{
1598 struct encap_flow_item *efi;
1599 struct mlx5e_tc_flow *flow;
1600
1601 list_for_each_entry(efi, &e->flows, list) {
1602 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1603 if (IS_ERR(mlx5e_flow_get(flow)))
1604 continue;
95435ad7 1605 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1606
1607 flow->tmp_efi_index = efi->index;
1608 list_add(&flow->tmp_list, flow_list);
1609 }
1610}
1611
6a06c2f7 1612/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1613void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1614{
1615 struct mlx5e_tc_flow *flow, *tmp;
1616
1617 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1618 mlx5e_flow_put(priv, flow);
1619}
1620
ac0d9176
VB		 1621static struct mlx5e_encap_entry *
1622mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1623 struct mlx5e_encap_entry *e)
1624{
1625 struct mlx5e_encap_entry *next = NULL;
1626
1627retry:
1628 rcu_read_lock();
1629
1630 /* find encap with non-zero reference counter value */
1631 for (next = e ?
1632 list_next_or_null_rcu(&nhe->encap_list,
1633 &e->encap_list,
1634 struct mlx5e_encap_entry,
1635 encap_list) :
1636 list_first_or_null_rcu(&nhe->encap_list,
1637 struct mlx5e_encap_entry,
1638 encap_list);
1639 next;
1640 next = list_next_or_null_rcu(&nhe->encap_list,
1641 &next->encap_list,
1642 struct mlx5e_encap_entry,
1643 encap_list))
1644 if (mlx5e_encap_take(next))
1645 break;
1646
1647 rcu_read_unlock();
1648
1649 /* release starting encap */
1650 if (e)
1651 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1652 if (!next)
1653 return next;
1654
1655 /* wait for encap to be fully initialized */
1656 wait_for_completion(&next->res_ready);
1657 /* continue searching if encap entry is not in valid state after completion */
1658 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1659 e = next;
1660 goto retry;
1661 }
1662
1663 return next;
1664}
1665
f6dfb4c3
HHZ		 1666void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1667{
1668 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1669 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1670 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1671 struct mlx5_fc *counter;
1672 struct neigh_table *tbl;
1673 bool neigh_used = false;
1674 struct neighbour *n;
90bb7692 1675 u64 lastuse;
f6dfb4c3
HHZ		 1676
1677 if (m_neigh->family == AF_INET)
1678 tbl = &arp_tbl;
1679#if IS_ENABLED(CONFIG_IPV6)
1680 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1681 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1682#endif
1683 else
1684 return;
1685
ac0d9176
VB		 1686 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1687 * next one.
1688 */
1689 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1690 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1691 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1692 struct mlx5_eswitch *esw;
1693 LIST_HEAD(flow_list);
948993f2 1694
6a06c2f7
VB		 1695 esw = priv->mdev->priv.eswitch;
1696 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1697 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1698 flow = container_of(efi, struct mlx5e_tc_flow,
1699 encaps[efi->index]);
5a7e5bcb
VB		 1700 if (IS_ERR(mlx5e_flow_get(flow)))
1701 continue;
6a06c2f7 1702 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1703
226f2ca3 1704 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1705 counter = mlx5e_tc_get_counter(flow);
90bb7692 1706 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1707 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1708 neigh_used = true;
1709 break;
1710 }
1711 }
1712 }
6a06c2f7 1713 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1714
6a06c2f7 1715 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1716 if (neigh_used) {
1717 /* release current encap before breaking the loop */
6a06c2f7 1718 mlx5e_encap_put(priv, e);
e36d4810 1719 break;
ac0d9176 1720 }
f6dfb4c3
HHZ		 1721 }
1722
c786fe59
VB		 1723 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1724
f6dfb4c3
HHZ		 1725 if (neigh_used) {
1726 nhe->reported_lastuse = jiffies;
1727
1728 /* find the relevant neigh according to the cached device and
1729 * dst ip pair
1730 */
1731 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1732 if (!n)
f6dfb4c3 1733 return;
f6dfb4c3
HHZ		 1734
1735 neigh_event_send(n, NULL);
1736 neigh_release(n);
1737 }
1738}
1739
61086f39 1740static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1741{
948993f2 1742 WARN_ON(!list_empty(&e->flows));
948993f2 1743
3c140dd5
VB		 1744 if (e->compl_result > 0) {
1745 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1746
1747 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1748 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1749 }
948993f2 1750
2a4b6526 1751 kfree(e->tun_info);
948993f2 1752 kfree(e->encap_header);
ac0d9176 1753 kfree_rcu(e, rcu);
948993f2
VB		 1754}
1755
14e6b038
EC		 1756static void mlx5e_decap_dealloc(struct mlx5e_priv *priv,
1757 struct mlx5e_decap_entry *d)
1758{
1759 WARN_ON(!list_empty(&d->flows));
1760
1761 if (!d->compl_result)
1762 mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat);
1763
1764 kfree_rcu(d, rcu);
1765}
1766
61086f39
VB		 1767void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1768{
1769 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1770
1771 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1772 return;
1773 hash_del_rcu(&e->encap_hlist);
1774 mutex_unlock(&esw->offloads.encap_tbl_lock);
1775
1776 mlx5e_encap_dealloc(priv, e);
1777}
1778
14e6b038
EC		 1779static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d)
1780{
1781 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1782
1783 if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock))
1784 return;
1785 hash_del_rcu(&d->hlist);
1786 mutex_unlock(&esw->offloads.decap_tbl_lock);
1787
1788 mlx5e_decap_dealloc(priv, d);
1789}
1790
d85cdccb 1791static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1792 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1793{
61086f39
VB		 1794 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1795 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1796
5a7e5bcb 1797 /* flow wasn't fully initialized */
61086f39 1798 if (!e)
5a7e5bcb
VB		 1799 return;
1800
61086f39 1801 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1802 list_del(&flow->encaps[out_index].list);
948993f2 1803 flow->encaps[out_index].e = NULL;
61086f39
VB		 1804 if (!refcount_dec_and_test(&e->refcnt)) {
1805 mutex_unlock(&esw->offloads.encap_tbl_lock);
1806 return;
1807 }
1808 hash_del_rcu(&e->encap_hlist);
1809 mutex_unlock(&esw->offloads.encap_tbl_lock);
1810
1811 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1812}
1813
14e6b038
EC		 1814static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1815 struct mlx5e_tc_flow *flow)
1816{
1817 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1818 struct mlx5e_decap_entry *d = flow->decap_reformat;
1819
1820 if (!d)
1821 return;
1822
1823 mutex_lock(&esw->offloads.decap_tbl_lock);
1824 list_del(&flow->l3_to_l2_reformat);
1825 flow->decap_reformat = NULL;
1826
1827 if (!refcount_dec_and_test(&d->refcnt)) {
1828 mutex_unlock(&esw->offloads.decap_tbl_lock);
1829 return;
1830 }
1831 hash_del_rcu(&d->hlist);
1832 mutex_unlock(&esw->offloads.decap_tbl_lock);
1833
1834 mlx5e_decap_dealloc(priv, d);
1835}
1836
04de7dda
RD		 1837static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1838{
1839 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1840
226f2ca3
VB		 1841 if (!flow_flag_test(flow, ESWITCH) ||
1842 !flow_flag_test(flow, DUP))
04de7dda
RD		 1843 return;
1844
1845 mutex_lock(&esw->offloads.peer_mutex);
1846 list_del(&flow->peer);
1847 mutex_unlock(&esw->offloads.peer_mutex);
1848
226f2ca3 1849 flow_flag_clear(flow, DUP);
04de7dda 1850
eb252c3a
RD		 1851 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1852 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1853 kfree(flow->peer_flow);
1854 }
1855
04de7dda
RD		 1856 flow->peer_flow = NULL;
1857}
1858
1859static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1860{
1861 struct mlx5_core_dev *dev = flow->priv->mdev;
1862 struct mlx5_devcom *devcom = dev->priv.devcom;
1863 struct mlx5_eswitch *peer_esw;
1864
1865 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1866 if (!peer_esw)
1867 return;
1868
1869 __mlx5e_tc_del_fdb_peer_flow(flow);
1870 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1871}
1872
e8f887ac 1873static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1874 struct mlx5e_tc_flow *flow)
e8f887ac 1875{
226f2ca3 1876 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1877 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1878 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1879 } else {
d85cdccb 1880 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1881 }
e8f887ac
AV		 1882}
1883
0a7fcb78
PB		 1884static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1885{
1886 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1887 struct flow_action *flow_action = &rule->action;
1888 const struct flow_action_entry *act;
1889 int i;
1890
1891 flow_action_for_each(i, act, flow_action) {
1892 switch (act->id) {
1893 case FLOW_ACTION_GOTO:
1894 return true;
1895 default:
1896 continue;
1897 }
1898 }
1899
1900 return false;
1901}
bbd00f7e 1902
0a7fcb78
PB		 1903static int
1904enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1905 struct flow_dissector_key_enc_opts *opts,
1906 struct netlink_ext_ack *extack,
1907 bool *dont_care)
1908{
1909 struct geneve_opt *opt;
1910 int off = 0;
1911
1912 *dont_care = true;
1913
1914 while (opts->len > off) {
1915 opt = (struct geneve_opt *)&opts->data[off];
1916
1917 if (!(*dont_care) || opt->opt_class || opt->type ||
1918 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1919 *dont_care = false;
1920
c51323ee 1921 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1922 opt->type != U8_MAX) {
0a7fcb78
PB		 1923 NL_SET_ERR_MSG(extack,
1924 "Partial match of tunnel options in chain > 0 isn't supported");
1925 netdev_warn(priv->netdev,
1926 "Partial match of tunnel options in chain > 0 isn't supported");
1927 return -EOPNOTSUPP;
1928 }
1929 }
1930
1931 off += sizeof(struct geneve_opt) + opt->length * 4;
1932 }
1933
1934 return 0;
1935}
1936
1937#define COPY_DISSECTOR(rule, diss_key, dst)\
1938({ \
1939 struct flow_rule *__rule = (rule);\
1940 typeof(dst) __dst = dst;\
1941\
1942 memcpy(__dst,\
1943 skb_flow_dissector_target(__rule->match.dissector,\
1944 diss_key,\
1945 __rule->match.key),\
1946 sizeof(*__dst));\
1947})
1948
1949static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1950 struct mlx5e_tc_flow *flow,
1951 struct flow_cls_offload *f,
1952 struct net_device *filter_dev)
bbd00f7e 1953{
f9e30088 1954 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1955 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1956 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1957 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1958 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1959 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1960 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1961 struct mlx5e_rep_priv *uplink_rpriv;
1962 struct tunnel_match_key tunnel_key;
1963 bool enc_opts_is_dont_care = true;
1964 u32 tun_id, enc_opts_id = 0;
1965 struct mlx5_eswitch *esw;
1966 u32 value, mask;
8f256622 1967 int err;
2e72eb43 1968
0a7fcb78
PB		 1969 esw = priv->mdev->priv.eswitch;
1970 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1971 uplink_priv = &uplink_rpriv->uplink_priv;
1972
1973 memset(&tunnel_key, 0, sizeof(tunnel_key));
1974 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1975 &tunnel_key.enc_control);
1976 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1977 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1978 &tunnel_key.enc_ipv4);
1979 else
1980 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1981 &tunnel_key.enc_ipv6);
1982 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1983 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1984 &tunnel_key.enc_tp);
1985 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1986 &tunnel_key.enc_key_id);
1987 tunnel_key.filter_ifindex = filter_dev->ifindex;
1988
1989 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1990 if (err)
101f4de9 1991 return err;
bbd00f7e 1992
0a7fcb78
PB		 1993 flow_rule_match_enc_opts(rule, &enc_opts_match);
1994 err = enc_opts_is_dont_care_or_full_match(priv,
1995 enc_opts_match.mask,
1996 extack,
1997 &enc_opts_is_dont_care);
1998 if (err)
1999 goto err_enc_opts;
fe1587a7 2000
0a7fcb78 2001 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 2002 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2003 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2004 sizeof(*enc_opts_match.key));
2005 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2006 sizeof(*enc_opts_match.mask));
2007
0a7fcb78 2008 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 2009 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 2010 if (err)
2011 goto err_enc_opts;
2012 }
fe1587a7 2013
0a7fcb78
PB		 2014 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2015 mask = enc_opts_id ? TUNNEL_ID_MASK :
2016 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 2017
0a7fcb78
PB		 2018 if (attr->chain) {
2019 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2020 TUNNEL_TO_REG, value, mask);
2021 } else {
2022 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2023 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 2024 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 2025 TUNNEL_TO_REG, value);
2026 if (err)
2027 goto err_set;
fe1587a7 2028
0a7fcb78 2029 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 2030 }
bbd00f7e 2031
0a7fcb78
PB		 2032 flow->tunnel_id = value;
2033 return 0;
bcef735c 2034
0a7fcb78
PB		 2035err_set:
2036 if (enc_opts_id)
2037 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2038 enc_opts_id);
2039err_enc_opts:
2040 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2041 return err;
2042}
bcef735c 2043
0a7fcb78
PB		 2044static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2045{
2046 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
2047 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
2048 struct mlx5_rep_uplink_priv *uplink_priv;
2049 struct mlx5e_rep_priv *uplink_rpriv;
2050 struct mlx5_eswitch *esw;
bcef735c 2051
0a7fcb78
PB		 2052 esw = flow->priv->mdev->priv.eswitch;
2053 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2054 uplink_priv = &uplink_rpriv->uplink_priv;
2055
2056 if (tun_id)
2057 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2058 if (enc_opts_id)
2059 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2060 enc_opts_id);
2061}
e98bedf5 2062
4c3844d9
PB		 2063u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
2064{
2065 return flow->tunnel_id;
2066}
2067
fca53304
EB		 2068void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2069 struct flow_match_basic *match, bool outer,
2070 void *headers_c, void *headers_v)
2071{
2072 bool ip_version_cap;
2073
2074 ip_version_cap = outer ?
2075 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2076 ft_field_support.outer_ip_version) :
2077 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2078 ft_field_support.inner_ip_version);
2079
2080 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2081 (match->key->n_proto == htons(ETH_P_IP) ||
2082 match->key->n_proto == htons(ETH_P_IPV6))) {
2083 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2085 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2086 } else {
2087 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2088 ntohs(match->mask->n_proto));
2089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2090 ntohs(match->key->n_proto));
2091 }
4a5d5d73
EB		 2092}
2093
bbd00f7e 2094static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2095 struct mlx5e_tc_flow *flow,
bbd00f7e 2096 struct mlx5_flow_spec *spec,
f9e30088 2097 struct flow_cls_offload *f,
0a7fcb78
PB		 2098 struct net_device *filter_dev,
2099 u8 *match_level,
2100 bool *match_inner)
bbd00f7e 2101{
0a7fcb78 2102 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2103 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2104 bool needs_mapping, sets_mapping;
8f256622 2105 int err;
2e72eb43 2106
0a7fcb78
PB		 2107 if (!mlx5e_is_eswitch_flow(flow))
2108 return -EOPNOTSUPP;
2109
c620b772
AL		 2110 needs_mapping = !!flow->attr->chain;
2111 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 2112 *match_inner = !needs_mapping;
2113
2114 if ((needs_mapping || sets_mapping) &&
636bb968 2115 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 2116 NL_SET_ERR_MSG(extack,
636bb968 2117 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2118 netdev_warn(priv->netdev,
636bb968 2119 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2120 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2121 }
2122
c620b772 2123 if (!flow->attr->chain) {
0a7fcb78
PB		 2124 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2125 match_level);
2126 if (err) {
e98bedf5 2127 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2128 "Failed to parse tunnel attributes");
2129 netdev_warn(priv->netdev,
2130 "Failed to parse tunnel attributes");
2131 return err;
e98bedf5
EB		 2132 }
2133
14e6b038
EC		 2134 /* With mpls over udp we decapsulate using packet reformat
2135 * object
2136 */
2137 if (!netif_is_bareudp(filter_dev))
c620b772 2138 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 2139 }
2140
0a7fcb78
PB		 2141 if (!needs_mapping && !sets_mapping)
2142 return 0;
bbd00f7e 2143
0a7fcb78 2144 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2145}
bbd00f7e 2146
0a7fcb78 2147static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2148{
0a7fcb78
PB		 2149 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2150 inner_headers);
bbd00f7e
HHZ		 2151}
2152
0a7fcb78 2153static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2154{
0a7fcb78
PB		 2155 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2156 inner_headers);
2157}
2158
2159static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2160{
2161 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2162 outer_headers);
2163}
2164
2165static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2166{
2167 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2168 outer_headers);
8377629e
EB		 2169}
2170
2171static void *get_match_headers_value(u32 flags,
2172 struct mlx5_flow_spec *spec)
2173{
2174 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2175 get_match_inner_headers_value(spec) :
2176 get_match_outer_headers_value(spec);
2177}
2178
2179static void *get_match_headers_criteria(u32 flags,
2180 struct mlx5_flow_spec *spec)
2181{
2182 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2183 get_match_inner_headers_criteria(spec) :
2184 get_match_outer_headers_criteria(spec);
8377629e
EB		 2185}
2186
6d65bc64 2187static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2188 struct flow_cls_offload *f)
2189{
2190 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2191 struct netlink_ext_ack *extack = f->common.extack;
2192 struct net_device *ingress_dev;
2193 struct flow_match_meta match;
2194
2195 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2196 return 0;
2197
2198 flow_rule_match_meta(rule, &match);
2199 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2200 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2201 return -EOPNOTSUPP;
6d65bc64 2202 }
2203
2204 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2205 match.key->ingress_ifindex);
2206 if (!ingress_dev) {
2207 NL_SET_ERR_MSG_MOD(extack,
2208 "Can't find the ingress port to match on");
a683012a 2209 return -ENOENT;
6d65bc64 2210 }
2211
2212 if (ingress_dev != filter_dev) {
2213 NL_SET_ERR_MSG_MOD(extack,
2214 "Can't match on the ingress filter port");
a683012a 2215 return -EOPNOTSUPP;
6d65bc64 2216 }
2217
2218 return 0;
2219}
2220
72046a91
EC		 2221static bool skip_key_basic(struct net_device *filter_dev,
2222 struct flow_cls_offload *f)
2223{
2224 /* When doing mpls over udp decap, the user needs to provide
2225 * MPLS_UC as the protocol in order to be able to match on mpls
2226 * label fields. However, the actual ethertype is IP so we want to
2227 * avoid matching on this, otherwise we'll fail the match.
2228 */
2229 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2230 return true;
2231
2232 return false;
2233}
2234
de0af0bf 2235static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2236 struct mlx5e_tc_flow *flow,
de0af0bf 2237 struct mlx5_flow_spec *spec,
f9e30088 2238 struct flow_cls_offload *f,
54c177ca 2239 struct net_device *filter_dev,
93b3586e 2240 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2241{
e98bedf5 2242 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2243 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2244 outer_headers);
2245 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2246 outer_headers);
699e96dd
JL		 2247 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2248 misc_parameters);
2249 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2250 misc_parameters);
f9e30088 2251 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2252 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2253 u16 addr_type = 0;
2254 u8 ip_proto = 0;
93b3586e 2255 u8 *match_level;
6d65bc64 2256 int err;
e3a2b7ed 2257
93b3586e 2258 match_level = outer_match_level;
de0af0bf 2259
8f256622 2260 if (dissector->used_keys &
3d144578
VB		 2261 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2262 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2263 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2264 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2265 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2266 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2267 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2268 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2269 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2270 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2271 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2272 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2273 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2274 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2275 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2276 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2277 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2278 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91
EC		 2279 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2280 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2281 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2282 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2283 dissector->used_keys);
e3a2b7ed
AV		 2284 return -EOPNOTSUPP;
2285 }
2286
075973c7 2287 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2288 bool match_inner = false;
bbd00f7e 2289
0a7fcb78
PB		 2290 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2291 outer_match_level, &match_inner);
2292 if (err)
2293 return err;
2294
2295 if (match_inner) {
2296 /* header pointers should point to the inner headers
2297 * if the packet was decapsulated already.
2298 * outer headers are set by parse_tunnel_attr.
2299 */
2300 match_level = inner_match_level;
2301 headers_c = get_match_inner_headers_criteria(spec);
2302 headers_v = get_match_inner_headers_value(spec);
2303 }
bbd00f7e
HHZ		 2304 }
2305
6d65bc64 2306 err = mlx5e_flower_parse_meta(filter_dev, f);
2307 if (err)
2308 return err;
2309
72046a91
EC		 2310 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2311 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2312 struct flow_match_basic match;
2313
2314 flow_rule_match_basic(rule, &match);
fca53304
EB		 2315 mlx5e_tc_set_ethertype(priv->mdev, &match,
2316 match_level == outer_match_level,
2317 headers_c, headers_v);
e3a2b7ed 2318
8f256622 2319 if (match.mask->n_proto)
d708f902 2320 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2321 }
35a605db
EB		 2322 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2323 is_vlan_dev(filter_dev)) {
2324 struct flow_dissector_key_vlan filter_dev_mask;
2325 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2326 struct flow_match_vlan match;
2327
35a605db
EB		 2328 if (is_vlan_dev(filter_dev)) {
2329 match.key = &filter_dev_key;
2330 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2331 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2332 match.key->vlan_priority = 0;
2333 match.mask = &filter_dev_mask;
2334 memset(match.mask, 0xff, sizeof(*match.mask));
2335 match.mask->vlan_priority = 0;
2336 } else {
2337 flow_rule_match_vlan(rule, &match);
2338 }
8f256622
PNA		 2339 if (match.mask->vlan_id ||
2340 match.mask->vlan_priority ||
2341 match.mask->vlan_tpid) {
2342 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2343 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2344 svlan_tag, 1);
2345 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2346 svlan_tag, 1);
2347 } else {
2348 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2349 cvlan_tag, 1);
2350 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2351 cvlan_tag, 1);
2352 }
095b6cfd 2353
8f256622
PNA		 2354 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2355 match.mask->vlan_id);
2356 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2357 match.key->vlan_id);
358d79a4 2358
8f256622
PNA		 2359 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2360 match.mask->vlan_priority);
2361 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2362 match.key->vlan_priority);
54782900 2363
d708f902 2364 *match_level = MLX5_MATCH_L2;
54782900 2365 }
d3a80bb5 2366 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2367 /* cvlan_tag enabled in match criteria and
2368 * disabled in match value means both S & C tags
2369 * don't exist (untagged of both)
2370 */
cee26487 2371 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2372 *match_level = MLX5_MATCH_L2;
54782900
OG		 2373 }
2374
8f256622
PNA		 2375 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2376 struct flow_match_vlan match;
2377
12d5cbf8 2378 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2379 if (match.mask->vlan_id ||
2380 match.mask->vlan_priority ||
2381 match.mask->vlan_tpid) {
2382 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2383 MLX5_SET(fte_match_set_misc, misc_c,
2384 outer_second_svlan_tag, 1);
2385 MLX5_SET(fte_match_set_misc, misc_v,
2386 outer_second_svlan_tag, 1);
2387 } else {
2388 MLX5_SET(fte_match_set_misc, misc_c,
2389 outer_second_cvlan_tag, 1);
2390 MLX5_SET(fte_match_set_misc, misc_v,
2391 outer_second_cvlan_tag, 1);
2392 }
2393
2394 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2395 match.mask->vlan_id);
699e96dd 2396 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2397 match.key->vlan_id);
699e96dd 2398 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2399 match.mask->vlan_priority);
699e96dd 2400 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2401 match.key->vlan_priority);
699e96dd
JL		 2402
2403 *match_level = MLX5_MATCH_L2;
0faddfe6 2404 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2405 }
2406 }
2407
8f256622
PNA		 2408 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2409 struct flow_match_eth_addrs match;
54782900 2410
8f256622 2411 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2412 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2413 dmac_47_16),
8f256622 2414 match.mask->dst);
d3a80bb5
OG		 2415 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2416 dmac_47_16),
8f256622 2417 match.key->dst);
d3a80bb5
OG		 2418
2419 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2420 smac_47_16),
8f256622 2421 match.mask->src);
d3a80bb5
OG		 2422 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2423 smac_47_16),
8f256622 2424 match.key->src);
d3a80bb5 2425
8f256622
PNA		 2426 if (!is_zero_ether_addr(match.mask->src) ||
2427 !is_zero_ether_addr(match.mask->dst))
d708f902 2428 *match_level = MLX5_MATCH_L2;
54782900
OG		 2429 }
2430
8f256622
PNA		 2431 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2432 struct flow_match_control match;
54782900 2433
8f256622
PNA		 2434 flow_rule_match_control(rule, &match);
2435 addr_type = match.key->addr_type;
54782900
OG		 2436
2437 /* the HW doesn't support frag first/later */
8f256622 2438 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2439 return -EOPNOTSUPP;
2440
8f256622 2441 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2442 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2443 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2444 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2445
2446 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2447 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2448 *match_level = MLX5_MATCH_L2;
54782900
OG		 2449 /* *** L2 attributes parsing up to here *** */
2450 else
83621b7d 2451 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2452 }
2453 }
2454
8f256622
PNA		 2455 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2456 struct flow_match_basic match;
2457
2458 flow_rule_match_basic(rule, &match);
2459 ip_proto = match.key->ip_proto;
54782900
OG		 2460
2461 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2462 match.mask->ip_proto);
54782900 2463 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2464 match.key->ip_proto);
54782900 2465
8f256622 2466 if (match.mask->ip_proto)
d708f902 2467 *match_level = MLX5_MATCH_L3;
54782900
OG		 2468 }
2469
e3a2b7ed 2470 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2471 struct flow_match_ipv4_addrs match;
e3a2b7ed 2472
8f256622 2473 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2474 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2475 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2476 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2477 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2478 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2479 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2480 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2481 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2482 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2483 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2484 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2485 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2486
8f256622 2487 if (match.mask->src || match.mask->dst)
d708f902 2488 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2489 }
2490
2491 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2492 struct flow_match_ipv6_addrs match;
e3a2b7ed 2493
8f256622 2494 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2495 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2496 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2497 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2498 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2499 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2500 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2501
2502 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2503 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2504 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2505 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2506 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2507 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2508
8f256622
PNA		 2509 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2510 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2511 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2512 }
2513
8f256622
PNA		 2514 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2515 struct flow_match_ip match;
1f97a526 2516
8f256622
PNA		 2517 flow_rule_match_ip(rule, &match);
2518 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2519 match.mask->tos & 0x3);
2520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2521 match.key->tos & 0x3);
1f97a526 2522
8f256622
PNA		 2523 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2524 match.mask->tos >> 2);
2525 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2526 match.key->tos >> 2);
1f97a526 2527
8f256622
PNA		 2528 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2529 match.mask->ttl);
2530 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2531 match.key->ttl);
1f97a526 2532
8f256622 2533 if (match.mask->ttl &&
a8ade55f 2534 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2535 ft_field_support.outer_ipv4_ttl)) {
2536 NL_SET_ERR_MSG_MOD(extack,
2537 "Matching on TTL is not supported");
1f97a526 2538 return -EOPNOTSUPP;
e98bedf5 2539 }
a8ade55f 2540
8f256622 2541 if (match.mask->tos || match.mask->ttl)
d708f902 2542 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2543 }
2544
54782900
OG		 2545 /* *** L3 attributes parsing up to here *** */
2546
8f256622
PNA		 2547 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2548 struct flow_match_ports match;
2549
2550 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2551 switch (ip_proto) {
2552 case IPPROTO_TCP:
2553 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2554 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2555 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2556 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2557
2558 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2559 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2560 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2561 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2562 break;
2563
2564 case IPPROTO_UDP:
2565 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2566 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2567 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2568 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2569
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2571 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2572 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2573 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2574 break;
2575 default:
e98bedf5
EB		 2576 NL_SET_ERR_MSG_MOD(extack,
2577 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2578 netdev_err(priv->netdev,
2579 "Only UDP and TCP transport are supported\n");
2580 return -EINVAL;
2581 }
de0af0bf 2582
8f256622 2583 if (match.mask->src || match.mask->dst)
d708f902 2584 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2585 }
2586
8f256622
PNA		 2587 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2588 struct flow_match_tcp match;
e77834ec 2589
8f256622 2590 flow_rule_match_tcp(rule, &match);
e77834ec 2591 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2592 ntohs(match.mask->flags));
e77834ec 2593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2594 ntohs(match.key->flags));
e77834ec 2595
8f256622 2596 if (match.mask->flags)
d708f902 2597 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2598 }
2599
e3a2b7ed
AV		 2600 return 0;
2601}
2602
de0af0bf 2603static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2604 struct mlx5e_tc_flow *flow,
de0af0bf 2605 struct mlx5_flow_spec *spec,
f9e30088 2606 struct flow_cls_offload *f,
54c177ca 2607 struct net_device *filter_dev)
de0af0bf 2608{
93b3586e 2609 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2610 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2611 struct mlx5_core_dev *dev = priv->mdev;
2612 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2613 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2614 struct mlx5_eswitch_rep *rep;
226f2ca3 2615 bool is_eswitch_flow;
de0af0bf
RD		 2616 int err;
2617
93b3586e
HN		 2618 inner_match_level = MLX5_MATCH_NONE;
2619 outer_match_level = MLX5_MATCH_NONE;
2620
0a7fcb78
PB		 2621 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2622 &inner_match_level, &outer_match_level);
93b3586e
HN		 2623 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2624 outer_match_level : inner_match_level;
de0af0bf 2625
226f2ca3
VB		 2626 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2627 if (!err && is_eswitch_flow) {
1d447a39 2628 rep = rpriv->rep;
b05af6aa 2629 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2630 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2631 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2632 NL_SET_ERR_MSG_MOD(extack,
2633 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2634 netdev_warn(priv->netdev,
2635 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2636 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2637 return -EOPNOTSUPP;
2638 }
2639 }
2640
c620b772
AL		 2641 flow->attr->inner_match_level = inner_match_level;
2642 flow->attr->outer_match_level = outer_match_level;
2643
38aa51c1 2644
de0af0bf
RD		 2645 return err;
2646}
2647
d79b6df6
OG		 2648struct pedit_headers {
2649 struct ethhdr eth;
0eb69bb9 2650 struct vlan_hdr vlan;
d79b6df6
OG		 2651 struct iphdr ip4;
2652 struct ipv6hdr ip6;
2653 struct tcphdr tcp;
2654 struct udphdr udp;
2655};
2656
c500c86b
PNA		 2657struct pedit_headers_action {
2658 struct pedit_headers vals;
2659 struct pedit_headers masks;
2660 u32 pedits;
2661};
2662
d79b6df6 2663static int pedit_header_offsets[] = {
73867881
PNA		 2664 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2665 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2666 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2667 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2668 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2669};
2670
2671#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2672
2673static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2674 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2675{
2676 u32 *curr_pmask, *curr_pval;
2677
c500c86b
PNA		 2678 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2679 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2680
2681 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2682 goto out_err;
2683
2684 *curr_pmask |= mask;
2685 *curr_pval |= (val & mask);
2686
2687 return 0;
2688
2689out_err:
2690 return -EOPNOTSUPP;
2691}
2692
2693struct mlx5_fields {
2694 u8 field;
88f30bbc
DL		 2695 u8 field_bsize;
2696 u32 field_mask;
d79b6df6 2697 u32 offset;
27c11b6b 2698 u32 match_offset;
d79b6df6
OG		 2699};
2700
88f30bbc
DL		 2701#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2702 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2703 offsetof(struct pedit_headers, field) + (off), \
2704 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2705
2ef86872
EB		 2706/* masked values are the same and there are no rewrites that do not have a
2707 * match.
2708 */
2709#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2710 type matchmaskx = *(type *)(matchmaskp); \
2711 type matchvalx = *(type *)(matchvalp); \
2712 type maskx = *(type *)(maskp); \
2713 type valx = *(type *)(valp); \
2714 \
2715 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2716 matchmaskx)); \
2717})
2718
27c11b6b 2719static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2720 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2721{
2722 bool same = false;
2723
88f30bbc
DL		 2724 switch (bsize) {
2725 case 8:
2ef86872 2726 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2727 break;
88f30bbc 2728 case 16:
2ef86872 2729 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2730 break;
88f30bbc 2731 case 32:
2ef86872 2732 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2733 break;
2734 }
2735
2736 return same;
2737}
a8e4f0c4 2738
d79b6df6 2739static struct mlx5_fields fields[] = {
88f30bbc
DL		 2740 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2741 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2742 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2743 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2744 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2745 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2746
ab9341b5 2747 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2748 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2749 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2750 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2751
2752 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2753 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2754 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2755 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2756 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2757 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2758 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2759 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2760 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2761 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2762 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2763 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2764 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2765 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2766 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2767 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2768 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2769 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2770
88f30bbc
DL		 2771 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2772 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2773 /* in linux iphdr tcp_flags is 8 bits long */
2774 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2775
88f30bbc
DL		 2776 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2777 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2778};
2779
82198d8b
MD		 2780static unsigned long mask_to_le(unsigned long mask, int size)
2781{
2782 __be32 mask_be32;
2783 __be16 mask_be16;
2784
2785 if (size == 32) {
2786 mask_be32 = (__force __be32)(mask);
2787 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2788 } else if (size == 16) {
2789 mask_be32 = (__force __be32)(mask);
2790 mask_be16 = *(__be16 *)&mask_be32;
2791 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2792 }
2793
2794 return mask;
2795}
6ae4a6a5
PB		 2796static int offload_pedit_fields(struct mlx5e_priv *priv,
2797 int namespace,
2798 struct pedit_headers_action *hdrs,
e98bedf5 2799 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2800 u32 *action_flags,
e98bedf5 2801 struct netlink_ext_ack *extack)
d79b6df6
OG		 2802{
2803 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2804 int i, action_size, first, last, next_z;
88f30bbc
DL		 2805 void *headers_c, *headers_v, *action, *vals_p;
2806 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2807 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2808 struct mlx5_fields *f;
82198d8b 2809 unsigned long mask, field_mask;
6ae4a6a5 2810 int err;
88f30bbc
DL		 2811 u8 cmd;
2812
6ae4a6a5 2813 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2814 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2815 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2816
73867881
PNA		 2817 set_masks = &hdrs[0].masks;
2818 add_masks = &hdrs[1].masks;
2819 set_vals = &hdrs[0].vals;
2820 add_vals = &hdrs[1].vals;
d79b6df6 2821
d65dbedf 2822 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2823
2824 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2825 bool skip;
2826
d79b6df6
OG		 2827 f = &fields[i];
2828 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2829 s_mask = 0;
2830 a_mask = 0;
d79b6df6
OG		 2831
2832 s_masks_p = (void *)set_masks + f->offset;
2833 a_masks_p = (void *)add_masks + f->offset;
2834
88f30bbc
DL		 2835 s_mask = *s_masks_p & f->field_mask;
2836 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2837
2838 if (!s_mask && !a_mask) /* nothing to offload here */
2839 continue;
2840
2841 if (s_mask && a_mask) {
e98bedf5
EB		 2842 NL_SET_ERR_MSG_MOD(extack,
2843 "can't set and add to the same HW field");
d79b6df6
OG		 2844 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2845 return -EOPNOTSUPP;
2846 }
2847
27c11b6b 2848 skip = false;
d79b6df6 2849 if (s_mask) {
27c11b6b
EB		 2850 void *match_mask = headers_c + f->match_offset;
2851 void *match_val = headers_v + f->match_offset;
2852
d79b6df6
OG		 2853 cmd = MLX5_ACTION_TYPE_SET;
2854 mask = s_mask;
2855 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2856 /* don't rewrite if we have a match on the same value */
2857 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2858 match_mask, f->field_bsize))
27c11b6b 2859 skip = true;
d79b6df6 2860 /* clear to denote we consumed this field */
88f30bbc 2861 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2862 } else {
2863 cmd = MLX5_ACTION_TYPE_ADD;
2864 mask = a_mask;
2865 vals_p = (void *)add_vals + f->offset;
27c11b6b 2866 /* add 0 is no change */
88f30bbc 2867 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2868 skip = true;
d79b6df6 2869 /* clear to denote we consumed this field */
88f30bbc 2870 *a_masks_p &= ~f->field_mask;
d79b6df6 2871 }
27c11b6b
EB		 2872 if (skip)
2873 continue;
d79b6df6 2874
82198d8b 2875 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2876
88f30bbc
DL		 2877 first = find_first_bit(&mask, f->field_bsize);
2878 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2879 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2880 if (first < next_z && next_z < last) {
e98bedf5
EB		 2881 NL_SET_ERR_MSG_MOD(extack,
2882 "rewrite of few sub-fields isn't supported");
2b64beba 2883 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2884 mask);
2885 return -EOPNOTSUPP;
2886 }
2887
6ae4a6a5
PB		 2888 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2889 if (err) {
2890 NL_SET_ERR_MSG_MOD(extack,
2891 "too many pedit actions, can't offload");
2892 mlx5_core_warn(priv->mdev,
2893 "mlx5: parsed %d pedit actions, can't do more\n",
2894 mod_acts->num_actions);
2895 return err;
2896 }
2897
2898 action = mod_acts->actions +
2899 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2900 MLX5_SET(set_action_in, action, action_type, cmd);
2901 MLX5_SET(set_action_in, action, field, f->field);
2902
2903 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2904 int start;
2905
82198d8b
MD		 2906 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2907
88f30bbc 2908 /* if field is bit sized it can start not from first bit */
82198d8b 2909 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2910
2911 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2912 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2913 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2914 }
2915
88f30bbc 2916 if (f->field_bsize == 32)
2b64beba 2917 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2918 else if (f->field_bsize == 16)
2b64beba 2919 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2920 else if (f->field_bsize == 8)
2b64beba 2921 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2922
6ae4a6a5 2923 ++mod_acts->num_actions;
d79b6df6
OG		 2924 }
2925
d79b6df6
OG		 2926 return 0;
2927}
2928
2cc1cb1d
TZ		 2929static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2930 int namespace)
2931{
2932 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2933 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2934 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2935 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2936}
2937
6ae4a6a5
PB		 2938int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2939 int namespace,
2940 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2941{
6ae4a6a5
PB		 2942 int action_size, new_num_actions, max_hw_actions;
2943 size_t new_sz, old_sz;
2944 void *ret;
d79b6df6 2945
6ae4a6a5
PB		 2946 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2947 return 0;
d79b6df6 2948
d65dbedf 2949 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2950
6ae4a6a5
PB		 2951 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2952 namespace);
2953 new_num_actions = min(max_hw_actions,
2954 mod_hdr_acts->actions ?
2955 mod_hdr_acts->max_actions * 2 : 1);
2956 if (mod_hdr_acts->max_actions == new_num_actions)
2957 return -ENOSPC;
2958
2959 new_sz = action_size * new_num_actions;
2960 old_sz = mod_hdr_acts->max_actions * action_size;
2961 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2962 if (!ret)
d79b6df6
OG		 2963 return -ENOMEM;
2964
6ae4a6a5
PB		 2965 memset(ret + old_sz, 0, new_sz - old_sz);
2966 mod_hdr_acts->actions = ret;
2967 mod_hdr_acts->max_actions = new_num_actions;
2968
d79b6df6
OG		 2969 return 0;
2970}
2971
6ae4a6a5
PB		 2972void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2973{
2974 kfree(mod_hdr_acts->actions);
2975 mod_hdr_acts->actions = NULL;
2976 mod_hdr_acts->num_actions = 0;
2977 mod_hdr_acts->max_actions = 0;
2978}
2979
d79b6df6
OG		 2980static const struct pedit_headers zero_masks = {};
2981
582234b4
EC		 2982static int
2983parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2984 const struct flow_action_entry *act, int namespace,
2985 struct mlx5e_tc_flow_parse_attr *parse_attr,
2986 struct pedit_headers_action *hdrs,
2987 struct netlink_ext_ack *extack)
d79b6df6 2988{
73867881
PNA		 2989 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2990 int err = -EOPNOTSUPP;
d79b6df6 2991 u32 mask, val, offset;
73867881 2992 u8 htype;
d79b6df6 2993
73867881
PNA		 2994 htype = act->mangle.htype;
2995 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2996
73867881
PNA		 2997 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2998 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2999 goto out_err;
3000 }
d79b6df6 3001
2cc1cb1d
TZ		 3002 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
3003 NL_SET_ERR_MSG_MOD(extack,
3004 "The pedit offload action is not supported");
3005 goto out_err;
3006 }
3007
73867881
PNA		 3008 mask = act->mangle.mask;
3009 val = act->mangle.val;
3010 offset = act->mangle.offset;
d79b6df6 3011
73867881
PNA		 3012 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
3013 if (err)
3014 goto out_err;
c500c86b 3015
73867881 3016 hdrs[cmd].pedits++;
d79b6df6 3017
c500c86b
PNA		 3018 return 0;
3019out_err:
3020 return err;
3021}
3022
582234b4
EC		 3023static int
3024parse_pedit_to_reformat(struct mlx5e_priv *priv,
3025 const struct flow_action_entry *act,
3026 struct mlx5e_tc_flow_parse_attr *parse_attr,
3027 struct netlink_ext_ack *extack)
3028{
3029 u32 mask, val, offset;
3030 u32 *p;
3031
3032 if (act->id != FLOW_ACTION_MANGLE)
3033 return -EOPNOTSUPP;
3034
3035 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
3036 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
3037 return -EOPNOTSUPP;
3038 }
3039
3040 mask = ~act->mangle.mask;
3041 val = act->mangle.val;
3042 offset = act->mangle.offset;
3043 p = (u32 *)&parse_attr->eth;
3044 *(p + (offset >> 2)) |= (val & mask);
3045
3046 return 0;
3047}
3048
3049static int parse_tc_pedit_action(struct mlx5e_priv *priv,
3050 const struct flow_action_entry *act, int namespace,
3051 struct mlx5e_tc_flow_parse_attr *parse_attr,
3052 struct pedit_headers_action *hdrs,
3053 struct mlx5e_tc_flow *flow,
3054 struct netlink_ext_ack *extack)
3055{
3056 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
3057 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
3058
3059 return parse_pedit_to_modify_hdr(priv, act, namespace,
3060 parse_attr, hdrs, extack);
3061}
3062
c500c86b
PNA		 3063static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3064 struct mlx5e_tc_flow_parse_attr *parse_attr,
3065 struct pedit_headers_action *hdrs,
27c11b6b 3066 u32 *action_flags,
c500c86b
PNA		 3067 struct netlink_ext_ack *extack)
3068{
3069 struct pedit_headers *cmd_masks;
3070 int err;
3071 u8 cmd;
3072
6ae4a6a5
PB		 3073 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
3074 action_flags, extack);
d79b6df6
OG		 3075 if (err < 0)
3076 goto out_dealloc_parsed_actions;
3077
3078 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 3079 cmd_masks = &hdrs[cmd].masks;
d79b6df6 3080 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 3081 NL_SET_ERR_MSG_MOD(extack,
3082 "attempt to offload an unsupported field");
b3a433de 3083 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3084 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3085 16, 1, cmd_masks, sizeof(zero_masks), true);
3086 err = -EOPNOTSUPP;
3087 goto out_dealloc_parsed_actions;
3088 }
3089 }
3090
3091 return 0;
3092
3093out_dealloc_parsed_actions:
6ae4a6a5 3094 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3095 return err;
3096}
3097
e98bedf5
EB		 3098static bool csum_offload_supported(struct mlx5e_priv *priv,
3099 u32 action,
3100 u32 update_flags,
3101 struct netlink_ext_ack *extack)
26c02749
OG		 3102{
3103 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3104 TCA_CSUM_UPDATE_FLAG_UDP;
3105
3106 /* The HW recalcs checksums only if re-writing headers */
3107 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3108 NL_SET_ERR_MSG_MOD(extack,
3109 "TC csum action is only offloaded with pedit");
26c02749
OG		 3110 netdev_warn(priv->netdev,
3111 "TC csum action is only offloaded with pedit\n");
3112 return false;
3113 }
3114
3115 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3116 NL_SET_ERR_MSG_MOD(extack,
3117 "can't offload TC csum action for some header/s");
26c02749
OG		 3118 netdev_warn(priv->netdev,
3119 "can't offload TC csum action for some header/s - flags %#x\n",
3120 update_flags);
3121 return false;
3122 }
3123
3124 return true;
3125}
3126
8998576b
DL		 3127struct ip_ttl_word {
3128 __u8 ttl;
3129 __u8 protocol;
3130 __sum16 check;
3131};
3132
3133struct ipv6_hoplimit_word {
3134 __be16 payload_len;
3135 __u8 nexthdr;
3136 __u8 hop_limit;
3137};
3138
4c3844d9
PB		 3139static int is_action_keys_supported(const struct flow_action_entry *act,
3140 bool ct_flow, bool *modify_ip_header,
7e36feeb 3141 bool *modify_tuple,
4c3844d9 3142 struct netlink_ext_ack *extack)
8998576b
DL		 3143{
3144 u32 mask, offset;
3145 u8 htype;
3146
3147 htype = act->mangle.htype;
3148 offset = act->mangle.offset;
3149 mask = ~act->mangle.mask;
3150 /* For IPv4 & IPv6 header check 4 byte word,
3151 * to determine that modified fields
3152 * are NOT ttl & hop_limit only.
3153 */
3154 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3155 struct ip_ttl_word *ttl_word =
3156 (struct ip_ttl_word *)&mask;
3157
3158 if (offset != offsetof(struct iphdr, ttl) ||
3159 ttl_word->protocol ||
3160 ttl_word->check) {
4c3844d9
PB		 3161 *modify_ip_header = true;
3162 }
3163
7e36feeb
PB		 3164 if (offset >= offsetof(struct iphdr, saddr))
3165 *modify_tuple = true;
3166
3167 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3168 NL_SET_ERR_MSG_MOD(extack,
3169 "can't offload re-write of ipv4 address with action ct");
3170 return -EOPNOTSUPP;
8998576b
DL		 3171 }
3172 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3173 struct ipv6_hoplimit_word *hoplimit_word =
3174 (struct ipv6_hoplimit_word *)&mask;
3175
3176 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3177 hoplimit_word->payload_len ||
3178 hoplimit_word->nexthdr) {
4c3844d9
PB		 3179 *modify_ip_header = true;
3180 }
3181
7e36feeb
PB		 3182 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3183 *modify_tuple = true;
3184
3185 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3186 NL_SET_ERR_MSG_MOD(extack,
3187 "can't offload re-write of ipv6 address with action ct");
3188 return -EOPNOTSUPP;
8998576b 3189 }
7e36feeb
PB		 3190 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3191 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3192 *modify_tuple = true;
3193 if (ct_flow) {
3194 NL_SET_ERR_MSG_MOD(extack,
3195 "can't offload re-write of transport header ports with action ct");
3196 return -EOPNOTSUPP;
3197 }
8998576b 3198 }
4c3844d9
PB		 3199
3200 return 0;
8998576b
DL		 3201}
3202
3d486ec4
OS		 3203static bool modify_header_match_supported(struct mlx5e_priv *priv,
3204 struct mlx5_flow_spec *spec,
73867881 3205 struct flow_action *flow_action,
4c3844d9 3206 u32 actions, bool ct_flow,
7e36feeb 3207 bool ct_clear,
e98bedf5 3208 struct netlink_ext_ack *extack)
bdd66ac0 3209{
73867881 3210 const struct flow_action_entry *act;
7e36feeb 3211 bool modify_ip_header, modify_tuple;
fca53304 3212 void *headers_c;
bdd66ac0
OG		 3213 void *headers_v;
3214 u16 ethertype;
8998576b 3215 u8 ip_proto;
4c3844d9 3216 int i, err;
bdd66ac0 3217
fca53304 3218 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3219 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3220 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3221
3222 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3223 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3224 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3225 goto out_ok;
3226
3227 modify_ip_header = false;
7e36feeb 3228 modify_tuple = false;
73867881
PNA		 3229 flow_action_for_each(i, act, flow_action) {
3230 if (act->id != FLOW_ACTION_MANGLE &&
3231 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3232 continue;
3233
4c3844d9 3234 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3235 &modify_ip_header,
3236 &modify_tuple, extack);
4c3844d9
PB		 3237 if (err)
3238 return err;
bdd66ac0
OG		 3239 }
3240
7e36feeb
PB		 3241 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3242 * (or after clear action), as otherwise, since the tuple is changed,
3243 * we can't restore ct state
3244 */
3245 if (!ct_clear && modify_tuple &&
89fbdbae 3246 mlx5_tc_ct_add_no_trk_match(spec)) {
7e36feeb
PB		 3247 NL_SET_ERR_MSG_MOD(extack,
3248 "can't offload tuple modify header with ct matches");
3249 netdev_info(priv->netdev,
3250 "can't offload tuple modify header with ct matches");
3251 return false;
3252 }
3253
bdd66ac0 3254 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3255 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3256 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3257 NL_SET_ERR_MSG_MOD(extack,
3258 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3259 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3260 ip_proto);
bdd66ac0
OG		 3261 return false;
3262 }
3263
3264out_ok:
3265 return true;
3266}
3267
3268static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3269 struct flow_action *flow_action,
bdd66ac0 3270 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3271 struct mlx5e_tc_flow *flow,
3272 struct netlink_ext_ack *extack)
bdd66ac0 3273{
a7c119bd 3274 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3275 u32 actions;
3276
c620b772
AL		 3277 ct_clear = flow->attr->ct_attr.ct_action &
3278 TCA_CT_ACT_CLEAR;
3279 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3280 actions = flow->attr->action;
3281
4c3844d9 3282 if (mlx5e_is_eswitch_flow(flow)) {
c620b772 3283 if (flow->attr->esw_attr->split_count && ct_flow) {
4c3844d9
PB		 3284 /* All registers used by ct are cleared when using
3285 * split rules.
3286 */
3287 NL_SET_ERR_MSG_MOD(extack,
3288 "Can't offload mirroring with action ct");
49397b80 3289 return false;
4c3844d9 3290 }
4c3844d9 3291 }
bdd66ac0
OG		 3292
3293 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3294 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3295 flow_action, actions,
7e36feeb
PB		 3296 ct_flow, ct_clear,
3297 extack);
bdd66ac0
OG		 3298
3299 return true;
3300}
3301
32134847
MD		 3302static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3303{
3304 return priv->mdev == peer_priv->mdev;
3305}
3306
5c65c564
OG		 3307static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3308{
3309 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3310 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3311
3312 fmdev = priv->mdev;
3313 pmdev = peer_priv->mdev;
3314
59c9d35e
AH		 3315 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3316 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3317
816f6706 3318 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3319}
3320
bdc837ee
EB		 3321static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3322 const struct flow_action_entry *act,
3323 struct mlx5e_tc_flow_parse_attr *parse_attr,
3324 struct pedit_headers_action *hdrs,
3325 u32 *action, struct netlink_ext_ack *extack)
3326{
3327 u16 mask16 = VLAN_VID_MASK;
3328 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3329 const struct flow_action_entry pedit_act = {
3330 .id = FLOW_ACTION_MANGLE,
3331 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3332 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3333 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3334 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3335 };
6fca9d1e 3336 u8 match_prio_mask, match_prio_val;
bf2f3bca 3337 void *headers_c, *headers_v;
bdc837ee
EB		 3338 int err;
3339
bf2f3bca
EB		 3340 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3341 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3342
3343 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3344 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3345 NL_SET_ERR_MSG_MOD(extack,
3346 "VLAN rewrite action must have VLAN protocol match");
3347 return -EOPNOTSUPP;
3348 }
3349
6fca9d1e
EB		 3350 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3351 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3352 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3353 NL_SET_ERR_MSG_MOD(extack,
3354 "Changing VLAN prio is not supported");
bdc837ee
EB		 3355 return -EOPNOTSUPP;
3356 }
3357
582234b4 3358 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3359 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3360
3361 return err;
3362}
3363
0bac1194
EB		 3364static int
3365add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3366 struct mlx5e_tc_flow_parse_attr *parse_attr,
3367 struct pedit_headers_action *hdrs,
3368 u32 *action, struct netlink_ext_ack *extack)
3369{
3370 const struct flow_action_entry prio_tag_act = {
3371 .vlan.vid = 0,
3372 .vlan.prio =
3373 MLX5_GET(fte_match_set_lyr_2_4,
3374 get_match_headers_value(*action,
3375 &parse_attr->spec),
3376 first_prio) &
3377 MLX5_GET(fte_match_set_lyr_2_4,
3378 get_match_headers_criteria(*action,
3379 &parse_attr->spec),
3380 first_prio),
3381 };
3382
3383 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3384 &prio_tag_act, parse_attr, hdrs, action,
3385 extack);
3386}
3387
c7569097
AL		 3388static int validate_goto_chain(struct mlx5e_priv *priv,
3389 struct mlx5e_tc_flow *flow,
3390 const struct flow_action_entry *act,
3391 u32 actions,
3392 struct netlink_ext_ack *extack)
3393{
3394 bool is_esw = mlx5e_is_eswitch_flow(flow);
3395 struct mlx5_flow_attr *attr = flow->attr;
3396 bool ft_flow = mlx5e_is_ft_flow(flow);
3397 u32 dest_chain = act->chain_index;
3398 struct mlx5_fs_chains *chains;
3399 struct mlx5_eswitch *esw;
3400 u32 reformat_and_fwd;
3401 u32 max_chain;
3402
3403 esw = priv->mdev->priv.eswitch;
3404 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3405 max_chain = mlx5_chains_get_chain_range(chains);
3406 reformat_and_fwd = is_esw ?
3407 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3408 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3409
3410 if (ft_flow) {
3411 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3412 return -EOPNOTSUPP;
3413 }
3414
3415 if (!mlx5_chains_backwards_supported(chains) &&
3416 dest_chain <= attr->chain) {
3417 NL_SET_ERR_MSG_MOD(extack,
3418 "Goto lower numbered chain isn't supported");
3419 return -EOPNOTSUPP;
3420 }
3421
3422 if (dest_chain > max_chain) {
3423 NL_SET_ERR_MSG_MOD(extack,
3424 "Requested destination chain is out of supported range");
3425 return -EOPNOTSUPP;
3426 }
3427
3428 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3429 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3430 !reformat_and_fwd) {
3431 NL_SET_ERR_MSG_MOD(extack,
3432 "Goto chain is not allowed if action has reformat or decap");
3433 return -EOPNOTSUPP;
3434 }
3435
3436 return 0;
3437}
3438
73867881
PNA		 3439static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3440 struct flow_action *flow_action,
aa0cbbae 3441 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3442 struct mlx5e_tc_flow *flow,
3443 struct netlink_ext_ack *extack)
e3a2b7ed 3444{
c620b772 3445 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3446 struct pedit_headers_action hdrs[2] = {};
3447 const struct flow_action_entry *act;
c620b772 3448 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3449 u32 action = 0;
244cd96a 3450 int err, i;
e3a2b7ed 3451
73867881 3452 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3453 return -EINVAL;
3454
53eca1f3
JK		 3455 if (!flow_action_hw_stats_check(flow_action, extack,
3456 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3457 return -EOPNOTSUPP;
3458
c620b772
AL		 3459 nic_attr = attr->nic_attr;
3460
3461 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3462
73867881
PNA		 3463 flow_action_for_each(i, act, flow_action) {
3464 switch (act->id) {
15fc92ec
TZ		 3465 case FLOW_ACTION_ACCEPT:
3466 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3467 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3468 break;
73867881 3469 case FLOW_ACTION_DROP:
1cab1cd7 3470 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3471 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3472 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3473 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3474 break;
3475 case FLOW_ACTION_MANGLE:
3476 case FLOW_ACTION_ADD:
3477 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3478 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3479 if (err)
3480 return err;
3481
c7569097 3482 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3483 break;
bdc837ee
EB		 3484 case FLOW_ACTION_VLAN_MANGLE:
3485 err = add_vlan_rewrite_action(priv,
3486 MLX5_FLOW_NAMESPACE_KERNEL,
3487 act, parse_attr, hdrs,
3488 &action, extack);
3489 if (err)
3490 return err;
3491
3492 break;
73867881 3493 case FLOW_ACTION_CSUM:
1cab1cd7 3494 if (csum_offload_supported(priv, action,
73867881 3495 act->csum_flags,
e98bedf5 3496 extack))
73867881 3497 break;
26c02749
OG		 3498
3499 return -EOPNOTSUPP;
73867881
PNA		 3500 case FLOW_ACTION_REDIRECT: {
3501 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3502
3503 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3504 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3505 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3506 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3507 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3508 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3509 } else {
e98bedf5
EB		 3510 NL_SET_ERR_MSG_MOD(extack,
3511 "device is not on same HW, can't offload");
5c65c564
OG		 3512 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3513 peer_dev->name);
3514 return -EINVAL;
3515 }
73867881
PNA		 3516 }
3517 break;
3518 case FLOW_ACTION_MARK: {
3519 u32 mark = act->mark;
e3a2b7ed
AV		 3520
3521 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3522 NL_SET_ERR_MSG_MOD(extack,
3523 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3524 return -EINVAL;
3525 }
3526
c620b772 3527 nic_attr->flow_tag = mark;
1cab1cd7 3528 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3529 }
3530 break;
c7569097
AL		 3531 case FLOW_ACTION_GOTO:
3532 err = validate_goto_chain(priv, flow, act, action,
3533 extack);
3534 if (err)
3535 return err;
3536
3537 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3538 attr->dest_chain = act->chain_index;
3539 break;
aedd133d
AL		 3540 case FLOW_ACTION_CT:
3541 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3542 if (err)
3543 return err;
3544
3545 flow_flag_set(flow, CT);
3546 break;
73867881 3547 default:
2cc1cb1d
TZ		 3548 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3549 return -EOPNOTSUPP;
e3a2b7ed 3550 }
e3a2b7ed
AV		 3551 }
3552
c500c86b
PNA		 3553 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3554 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3555 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3556 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3557 if (err)
3558 return err;
27c11b6b
EB		 3559 /* in case all pedit actions are skipped, remove the MOD_HDR
3560 * flag.
3561 */
6ae4a6a5 3562 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3563 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3564 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3565 }
c500c86b
PNA		 3566 }
3567
1cab1cd7 3568 attr->action = action;
c7569097
AL		 3569
3570 if (attr->dest_chain) {
3571 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3572 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3573 return -EOPNOTSUPP;
3574 }
3575 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3576 }
3577
3578 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3579 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3580
73867881 3581 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3582 return -EOPNOTSUPP;
3583
e3a2b7ed
AV		 3584 return 0;
3585}
3586
7f1a546e 3587struct encap_key {
1f6da306 3588 const struct ip_tunnel_key *ip_tun_key;
d386939a 3589 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3590};
3591
3592static inline int cmp_encap_info(struct encap_key *a,
3593 struct encap_key *b)
a54e20b4 3594{
7f1a546e 3595 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3596 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3597}
3598
14e6b038
EC		 3599static inline int cmp_decap_info(struct mlx5e_decap_key *a,
3600 struct mlx5e_decap_key *b)
3601{
3602 return memcmp(&a->key, &b->key, sizeof(b->key));
3603}
3604
7f1a546e 3605static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3606{
7f1a546e 3607 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3608 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3609}
3610
14e6b038
EC		 3611static inline int hash_decap_info(struct mlx5e_decap_key *key)
3612{
3613 return jhash(&key->key, sizeof(key->key), 0);
3614}
a54e20b4 3615
32134847 3616static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3617 struct net_device *peer_netdev)
3618{
3619 struct mlx5e_priv *peer_priv;
3620
3621 peer_priv = netdev_priv(peer_netdev);
3622
3623 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3624 mlx5e_eswitch_vf_rep(priv->netdev) &&
3625 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3626 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3627}
3628
948993f2
VB		 3629bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3630{
3631 return refcount_inc_not_zero(&e->refcnt);
3632}
3633
14e6b038
EC		 3634static bool mlx5e_decap_take(struct mlx5e_decap_entry *e)
3635{
3636 return refcount_inc_not_zero(&e->refcnt);
3637}
3638
948993f2
VB		 3639static struct mlx5e_encap_entry *
3640mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3641 uintptr_t hash_key)
3642{
3643 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3644 struct mlx5e_encap_entry *e;
3645 struct encap_key e_key;
3646
3647 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3648 encap_hlist, hash_key) {
3649 e_key.ip_tun_key = &e->tun_info->key;
3650 e_key.tc_tunnel = e->tunnel;
3651 if (!cmp_encap_info(&e_key, key) &&
3652 mlx5e_encap_take(e))
3653 return e;
3654 }
3655
3656 return NULL;
3657}
3658
14e6b038
EC		 3659static struct mlx5e_decap_entry *
3660mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key,
3661 uintptr_t hash_key)
3662{
3663 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3664 struct mlx5e_decap_key r_key;
3665 struct mlx5e_decap_entry *e;
3666
3667 hash_for_each_possible_rcu(esw->offloads.decap_tbl, e,
3668 hlist, hash_key) {
3669 r_key = e->key;
3670 if (!cmp_decap_info(&r_key, key) &&
3671 mlx5e_decap_take(e))
3672 return e;
3673 }
3674 return NULL;
3675}
3676
2a4b6526
VB		 3677static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3678{
3679 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3680
3681 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3682}
3683
554fe75c
DL		 3684static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3685 struct mlx5e_tc_flow *flow,
3686 int out_index,
3687 struct mlx5e_encap_entry *e,
3688 struct netlink_ext_ack *extack)
3689{
3690 int i;
3691
3692 for (i = 0; i < out_index; i++) {
3693 if (flow->encaps[i].e != e)
3694 continue;
3695 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3696 netdev_err(priv->netdev, "can't duplicate encap action\n");
3697 return true;
3698 }
3699
3700 return false;
3701}
3702
a54e20b4 3703static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3704 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3705 struct net_device *mirred_dev,
3706 int out_index,
8c4dc42b 3707 struct netlink_ext_ack *extack,
0ad060ee
RD		 3708 struct net_device **encap_dev,
3709 bool *encap_valid)
a54e20b4
HHZ		 3710{
3711 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
733d4f36 3712 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3713 struct mlx5_flow_attr *attr = flow->attr;
1f6da306 3714 const struct ip_tunnel_info *tun_info;
948993f2 3715 struct encap_key key;
c1ae1152 3716 struct mlx5e_encap_entry *e;
733d4f36 3717 unsigned short family;
a54e20b4 3718 uintptr_t hash_key;
54c177ca 3719 int err = 0;
a54e20b4 3720
733d4f36 3721 parse_attr = attr->parse_attr;
1f6da306 3722 tun_info = parse_attr->tun_info[out_index];
733d4f36 3723 family = ip_tunnel_info_af(tun_info);
7f1a546e 3724 key.ip_tun_key = &tun_info->key;
d386939a 3725 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3726 if (!key.tc_tunnel) {
3727 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3728 return -EOPNOTSUPP;
3729 }
733d4f36 3730
7f1a546e 3731 hash_key = hash_encap_info(&key);
a54e20b4 3732
61086f39 3733 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3734 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3735
b2812089 3736 /* must verify if encap is valid or not */
d589e785 3737 if (e) {
554fe75c
DL		 3738 /* Check that entry was not already attached to this flow */
3739 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3740 err = -EOPNOTSUPP;
3741 goto out_err;
3742 }
3743
d589e785
VB		 3744 mutex_unlock(&esw->offloads.encap_tbl_lock);
3745 wait_for_completion(&e->res_ready);
3746
3747 /* Protect against concurrent neigh update. */
3748 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3749 if (e->compl_result < 0) {
d589e785
VB		 3750 err = -EREMOTEIO;
3751 goto out_err;
3752 }
45247bf2 3753 goto attach_flow;
d589e785 3754 }
a54e20b4
HHZ		 3755
3756 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3757 if (!e) {
3758 err = -ENOMEM;
3759 goto out_err;
3760 }
a54e20b4 3761
948993f2 3762 refcount_set(&e->refcnt, 1);
d589e785
VB		 3763 init_completion(&e->res_ready);
3764
2a4b6526
VB		 3765 tun_info = dup_tun_info(tun_info);
3766 if (!tun_info) {
3767 err = -ENOMEM;
3768 goto out_err_init;
3769 }
1f6da306 3770 e->tun_info = tun_info;
101f4de9 3771 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3772 if (err)
3773 goto out_err_init;
54c177ca 3774
a54e20b4 3775 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3776 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3777 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3778
ce99f6b9 3779 if (family == AF_INET)
101f4de9 3780 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3781 else if (family == AF_INET6)
101f4de9 3782 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3783
d589e785
VB		 3784 /* Protect against concurrent neigh update. */
3785 mutex_lock(&esw->offloads.encap_tbl_lock);
3786 complete_all(&e->res_ready);
3787 if (err) {
3788 e->compl_result = err;
a54e20b4 3789 goto out_err;
d589e785 3790 }
3c140dd5 3791 e->compl_result = 1;
a54e20b4 3792
45247bf2 3793attach_flow:
948993f2 3794 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3795 list_add(&flow->encaps[out_index].list, &e->flows);
3796 flow->encaps[out_index].index = out_index;
45247bf2 3797 *encap_dev = e->out_dev;
8c4dc42b 3798 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
c620b772
AL		 3799 attr->esw_attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3800 attr->esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3801 *encap_valid = true;
8c4dc42b 3802 } else {
0ad060ee 3803 *encap_valid = false;
8c4dc42b 3804 }
61086f39 3805 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3806
232c0013 3807 return err;
a54e20b4
HHZ		 3808
3809out_err:
61086f39 3810 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3811 if (e)
3812 mlx5e_encap_put(priv, e);
a54e20b4 3813 return err;
2a4b6526
VB		 3814
3815out_err_init:
3816 mutex_unlock(&esw->offloads.encap_tbl_lock);
3817 kfree(tun_info);
3818 kfree(e);
3819 return err;
a54e20b4
HHZ		 3820}
3821
14e6b038
EC		 3822static int mlx5e_attach_decap(struct mlx5e_priv *priv,
3823 struct mlx5e_tc_flow *flow,
3824 struct netlink_ext_ack *extack)
3825{
3826 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3827 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
14e6b038
EC		 3828 struct mlx5e_tc_flow_parse_attr *parse_attr;
3829 struct mlx5e_decap_entry *d;
3830 struct mlx5e_decap_key key;
3831 uintptr_t hash_key;
28619046 3832 int err = 0;
14e6b038 3833
c620b772 3834 parse_attr = flow->attr->parse_attr;
14e6b038
EC		 3835 if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {
3836 NL_SET_ERR_MSG_MOD(extack,
3837 "encap header larger than max supported");
3838 return -EOPNOTSUPP;
3839 }
3840
3841 key.key = parse_attr->eth;
3842 hash_key = hash_decap_info(&key);
3843 mutex_lock(&esw->offloads.decap_tbl_lock);
3844 d = mlx5e_decap_get(priv, &key, hash_key);
3845 if (d) {
3846 mutex_unlock(&esw->offloads.decap_tbl_lock);
3847 wait_for_completion(&d->res_ready);
3848 mutex_lock(&esw->offloads.decap_tbl_lock);
3849 if (d->compl_result) {
3850 err = -EREMOTEIO;
3851 goto out_free;
3852 }
3853 goto found;
3854 }
3855
3856 d = kzalloc(sizeof(*d), GFP_KERNEL);
3857 if (!d) {
3858 err = -ENOMEM;
3859 goto out_err;
3860 }
3861
3862 d->key = key;
3863 refcount_set(&d->refcnt, 1);
3864 init_completion(&d->res_ready);
3865 INIT_LIST_HEAD(&d->flows);
3866 hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key);
3867 mutex_unlock(&esw->offloads.decap_tbl_lock);
3868
3869 d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
3870 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2,
3871 sizeof(parse_attr->eth),
3872 &parse_attr->eth,
3873 MLX5_FLOW_NAMESPACE_FDB);
3874 if (IS_ERR(d->pkt_reformat)) {
3875 err = PTR_ERR(d->pkt_reformat);
3876 d->compl_result = err;
3877 }
3878 mutex_lock(&esw->offloads.decap_tbl_lock);
3879 complete_all(&d->res_ready);
3880 if (err)
3881 goto out_free;
3882
3883found:
3884 flow->decap_reformat = d;
3885 attr->decap_pkt_reformat = d->pkt_reformat;
3886 list_add(&flow->l3_to_l2_reformat, &d->flows);
3887 mutex_unlock(&esw->offloads.decap_tbl_lock);
3888 return 0;
3889
3890out_free:
3891 mutex_unlock(&esw->offloads.decap_tbl_lock);
3892 mlx5e_decap_put(priv, d);
3893 return err;
3894
3895out_err:
3896 mutex_unlock(&esw->offloads.decap_tbl_lock);
3897 return err;
3898}
3899
1482bd3d 3900static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3901 const struct flow_action_entry *act,
1482bd3d
JL		 3902 struct mlx5_esw_flow_attr *attr,
3903 u32 *action)
3904{
cc495188
JL		 3905 u8 vlan_idx = attr->total_vlan;
3906
3907 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3908 return -EOPNOTSUPP;
3909
73867881
PNA		 3910 switch (act->id) {
3911 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3912 if (vlan_idx) {
3913 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3914 MLX5_FS_VLAN_DEPTH))
3915 return -EOPNOTSUPP;
3916
3917 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3918 } else {
3919 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3920 }
73867881
PNA		 3921 break;
3922 case FLOW_ACTION_VLAN_PUSH:
3923 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3924 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3925 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3926 if (!attr->vlan_proto[vlan_idx])
3927 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3928
3929 if (vlan_idx) {
3930 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3931 MLX5_FS_VLAN_DEPTH))
3932 return -EOPNOTSUPP;
3933
3934 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3935 } else {
3936 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3937 (act->vlan.proto != htons(ETH_P_8021Q) ||
3938 act->vlan.prio))
cc495188
JL		 3939 return -EOPNOTSUPP;
3940
3941 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3942 }
73867881
PNA		 3943 break;
3944 default:
bdc837ee 3945 return -EINVAL;
1482bd3d
JL		 3946 }
3947
cc495188
JL		 3948 attr->total_vlan = vlan_idx + 1;
3949
1482bd3d
JL		 3950 return 0;
3951}
3952
d34eb2fc
OG		 3953static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3954 struct net_device *out_dev)
3955{
3956 struct net_device *fdb_out_dev = out_dev;
3957 struct net_device *uplink_upper;
3958
3959 rcu_read_lock();
3960 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3961 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3962 uplink_upper == out_dev) {
3963 fdb_out_dev = uplink_dev;
3964 } else if (netif_is_lag_master(out_dev)) {
3965 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3966 if (fdb_out_dev &&
3967 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3968 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3969 fdb_out_dev = NULL;
3970 }
3971 rcu_read_unlock();
3972 return fdb_out_dev;
3973}
3974
278748a9 3975static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3976 struct mlx5_flow_attr *attr,
278748a9
EB		 3977 struct net_device **out_dev,
3978 u32 *action)
3979{
3980 struct net_device *vlan_dev = *out_dev;
3981 struct flow_action_entry vlan_act = {
3982 .id = FLOW_ACTION_VLAN_PUSH,
3983 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3984 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3985 .vlan.prio = 0,
3986 };
3987 int err;
3988
c620b772 3989 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3990 if (err)
3991 return err;
3992
3993 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3994 dev_get_iflink(vlan_dev));
3995 if (is_vlan_dev(*out_dev))
3996 err = add_vlan_push_action(priv, attr, out_dev, action);
3997
3998 return err;
3999}
4000
35a605db 4001static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 4002 struct mlx5_flow_attr *attr,
35a605db
EB		 4003 u32 *action)
4004{
35a605db
EB		 4005 struct flow_action_entry vlan_act = {
4006 .id = FLOW_ACTION_VLAN_POP,
4007 };
70f478ca 4008 int nest_level, err = 0;
35a605db 4009
70f478ca
DL		 4010 nest_level = attr->parse_attr->filter_dev->lower_level -
4011 priv->netdev->lower_level;
35a605db 4012 while (nest_level--) {
c620b772 4013 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 4014 if (err)
4015 return err;
4016 }
4017
4018 return err;
4019}
4020
32134847
MD		 4021static bool same_hw_reps(struct mlx5e_priv *priv,
4022 struct net_device *peer_netdev)
4023{
4024 struct mlx5e_priv *peer_priv;
4025
4026 peer_priv = netdev_priv(peer_netdev);
4027
4028 return mlx5e_eswitch_rep(priv->netdev) &&
4029 mlx5e_eswitch_rep(peer_netdev) &&
4030 same_hw_devs(priv, peer_priv);
4031}
4032
4033static bool is_lag_dev(struct mlx5e_priv *priv,
4034 struct net_device *peer_netdev)
4035{
4036 return ((mlx5_lag_is_sriov(priv->mdev) ||
4037 mlx5_lag_is_multipath(priv->mdev)) &&
4038 same_hw_reps(priv, peer_netdev));
4039}
4040
f6dc1264
PB		 4041bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4042 struct net_device *out_dev)
4043{
32134847
MD		 4044 if (is_merged_eswitch_vfs(priv, out_dev))
4045 return true;
4046
4047 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 4048 return true;
4049
4050 return mlx5e_eswitch_rep(out_dev) &&
32134847 4051 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 4052}
4053
554fe75c
DL		 4054static bool is_duplicated_output_device(struct net_device *dev,
4055 struct net_device *out_dev,
4056 int *ifindexes, int if_count,
4057 struct netlink_ext_ack *extack)
4058{
4059 int i;
4060
4061 for (i = 0; i < if_count; i++) {
4062 if (ifindexes[i] == out_dev->ifindex) {
4063 NL_SET_ERR_MSG_MOD(extack,
4064 "can't duplicate output to same device");
4065 netdev_err(dev, "can't duplicate output to same device: %s\n",
4066 out_dev->name);
4067 return true;
4068 }
4069 }
4070
4071 return false;
4072}
4073
613f53fe
EC		 4074static int verify_uplink_forwarding(struct mlx5e_priv *priv,
4075 struct mlx5e_tc_flow *flow,
4076 struct net_device *out_dev,
4077 struct netlink_ext_ack *extack)
4078{
c620b772 4079 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 4080 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 4081 struct mlx5e_rep_priv *rep_priv;
4082
4083 /* Forwarding non encapsulated traffic between
4084 * uplink ports is allowed only if
4085 * termination_table_raw_traffic cap is set.
4086 *
c620b772 4087 * Input vport was stored attr->in_rep.
613f53fe
EC		 4088 * In LAG case, *priv* is the private data of
4089 * uplink which may be not the input vport.
4090 */
4091 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
4092
4093 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
4094 mlx5e_eswitch_uplink_rep(out_dev)))
4095 return 0;
4096
4097 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
4098 termination_table_raw_traffic)) {
4099 NL_SET_ERR_MSG_MOD(extack,
4100 "devices are both uplink, can't offload forwarding");
4101 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
4102 priv->netdev->name, out_dev->name);
4103 return -EOPNOTSUPP;
4104 } else if (out_dev != rep_priv->netdev) {
4105 NL_SET_ERR_MSG_MOD(extack,
4106 "devices are not the same uplink, can't offload forwarding");
4107 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
4108 priv->netdev->name, out_dev->name);
4109 return -EOPNOTSUPP;
4110 }
4111 return 0;
4112}
4113
73867881
PNA		 4114static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
4115 struct flow_action *flow_action,
e98bedf5 4116 struct mlx5e_tc_flow *flow,
14e6b038
EC		 4117 struct netlink_ext_ack *extack,
4118 struct net_device *filter_dev)
03a9d11e 4119{
73867881 4120 struct pedit_headers_action hdrs[2] = {};
bf07aa73 4121 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4122 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 4123 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 4124 const struct ip_tunnel_info *info = NULL;
c620b772 4125 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 4126 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 4127 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 4128 const struct flow_action_entry *act;
c620b772 4129 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 4130 bool encap = false, decap = false;
4131 u32 action = attr->action;
554fe75c 4132 int err, i, if_count = 0;
f828ca6a 4133 bool mpls_push = false;
03a9d11e 4134
73867881 4135 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 4136 return -EINVAL;
4137
53eca1f3
JK		 4138 if (!flow_action_hw_stats_check(flow_action, extack,
4139 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 4140 return -EOPNOTSUPP;
4141
c620b772
AL		 4142 esw_attr = attr->esw_attr;
4143 parse_attr = attr->parse_attr;
4144
73867881
PNA		 4145 flow_action_for_each(i, act, flow_action) {
4146 switch (act->id) {
4147 case FLOW_ACTION_DROP:
1cab1cd7
OG		 4148 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
4149 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 4150 break;
f0288210
EC		 4151 case FLOW_ACTION_TRAP:
4152 if (!flow_offload_has_one_action(flow_action)) {
4153 NL_SET_ERR_MSG_MOD(extack,
4154 "action trap is supported as a sole action only");
4155 return -EOPNOTSUPP;
4156 }
4157 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4158 MLX5_FLOW_CONTEXT_ACTION_COUNT);
4159 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
4160 break;
f828ca6a
EC		 4161 case FLOW_ACTION_MPLS_PUSH:
4162 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
4163 reformat_l2_to_l3_tunnel) ||
4164 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
4165 NL_SET_ERR_MSG_MOD(extack,
4166 "mpls push is supported only for mpls_uc protocol");
4167 return -EOPNOTSUPP;
4168 }
4169 mpls_push = true;
4170 break;
14e6b038
EC		 4171 case FLOW_ACTION_MPLS_POP:
4172 /* we only support mpls pop if it is the first action
4173 * and the filter net device is bareudp. Subsequent
4174 * actions can be pedit and the last can be mirred
4175 * egress redirect.
4176 */
4177 if (i) {
4178 NL_SET_ERR_MSG_MOD(extack,
4179 "mpls pop supported only as first action");
4180 return -EOPNOTSUPP;
4181 }
4182 if (!netif_is_bareudp(filter_dev)) {
4183 NL_SET_ERR_MSG_MOD(extack,
4184 "mpls pop supported only on bareudp devices");
4185 return -EOPNOTSUPP;
4186 }
4187
4188 parse_attr->eth.h_proto = act->mpls_pop.proto;
4189 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
4190 flow_flag_set(flow, L3_TO_L2_DECAP);
4191 break;
73867881
PNA		 4192 case FLOW_ACTION_MANGLE:
4193 case FLOW_ACTION_ADD:
4194 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 4195 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 4196 if (err)
4197 return err;
4198
582234b4
EC		 4199 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
4200 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 4201 esw_attr->split_count = esw_attr->out_count;
582234b4 4202 }
73867881
PNA		 4203 break;
4204 case FLOW_ACTION_CSUM:
1cab1cd7 4205 if (csum_offload_supported(priv, action,
73867881
PNA		 4206 act->csum_flags, extack))
4207 break;
26c02749
OG		 4208
4209 return -EOPNOTSUPP;
73867881
PNA		 4210 case FLOW_ACTION_REDIRECT:
4211 case FLOW_ACTION_MIRRED: {
03a9d11e 4212 struct mlx5e_priv *out_priv;
592d3651 4213 struct net_device *out_dev;
03a9d11e 4214
73867881 4215 out_dev = act->dev;
ef381359
OS		 4216 if (!out_dev) {
4217 /* out_dev is NULL when filters with
4218 * non-existing mirred device are replayed to
4219 * the driver.
4220 */
4221 return -EINVAL;
4222 }
03a9d11e 4223
f828ca6a
EC		 4224 if (mpls_push && !netif_is_bareudp(out_dev)) {
4225 NL_SET_ERR_MSG_MOD(extack,
4226 "mpls is supported only through a bareudp device");
4227 return -EOPNOTSUPP;
4228 }
4229
84179981
PB		 4230 if (ft_flow && out_dev == priv->netdev) {
4231 /* Ignore forward to self rules generated
4232 * by adding both mlx5 devs to the flow table
4233 * block on a normal nft offload setup.
4234 */
4235 return -EOPNOTSUPP;
4236 }
4237
c620b772 4238 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 4239 NL_SET_ERR_MSG_MOD(extack,
4240 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 4241 netdev_warn(priv->netdev,
4242 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 4243 esw_attr->out_count);
592d3651
CM		 4244 return -EOPNOTSUPP;
4245 }
4246
f493f155
EB		 4247 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4248 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 4249 if (encap) {
c620b772 4250 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 4251 out_dev->ifindex;
c620b772
AL		 4252 parse_attr->tun_info[esw_attr->out_count] = dup_tun_info(info);
4253 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 4254 return -ENOMEM;
4255 encap = false;
c620b772 4256 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 4257 MLX5_ESW_DEST_ENCAP;
c620b772 4258 esw_attr->out_count++;
b6a4ac24
VB		 4259 /* attr->dests[].rep is resolved when we
4260 * handle encap
4261 */
4262 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 4263 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4264 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 4265
554fe75c
DL		 4266 if (is_duplicated_output_device(priv->netdev,
4267 out_dev,
4268 ifindexes,
4269 if_count,
4270 extack))
4271 return -EOPNOTSUPP;
4272
4273 ifindexes[if_count] = out_dev->ifindex;
4274 if_count++;
4275
d34eb2fc
OG		 4276 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4277 if (!out_dev)
4278 return -ENODEV;
7ba58ba7 4279
278748a9
EB		 4280 if (is_vlan_dev(out_dev)) {
4281 err = add_vlan_push_action(priv, attr,
4282 &out_dev,
4283 &action);
4284 if (err)
4285 return err;
4286 }
f6dc1264 4287
35a605db
EB		 4288 if (is_vlan_dev(parse_attr->filter_dev)) {
4289 err = add_vlan_pop_action(priv, attr,
4290 &action);
4291 if (err)
4292 return err;
4293 }
278748a9 4294
613f53fe
EC		 4295 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4296 if (err)
4297 return err;
ffec9702 4298
f6dc1264
PB		 4299 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4300 NL_SET_ERR_MSG_MOD(extack,
4301 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4302 return -EOPNOTSUPP;
f6dc1264 4303 }
a0646c88 4304
a54e20b4 4305 out_priv = netdev_priv(out_dev);
1d447a39 4306 rpriv = out_priv->ppriv;
c620b772
AL		 4307 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
4308 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
4309 esw_attr->out_count++;
ef381359
OS		 4310 } else if (parse_attr->filter_dev != priv->netdev) {
4311 /* All mlx5 devices are called to configure
4312 * high level device filters. Therefore, the
4313 * *attempt* to install a filter on invalid
4314 * eswitch should not trigger an explicit error
4315 */
4316 return -EINVAL;
a54e20b4 4317 } else {
e98bedf5
EB		 4318 NL_SET_ERR_MSG_MOD(extack,
4319 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4320 netdev_warn(priv->netdev,
4321 "devices %s %s not on same switch HW, can't offload forwarding\n",
4322 priv->netdev->name,
4323 out_dev->name);
03a9d11e
OG		 4324 return -EINVAL;
4325 }
73867881
PNA		 4326 }
4327 break;
4328 case FLOW_ACTION_TUNNEL_ENCAP:
4329 info = act->tunnel;
a54e20b4
HHZ		 4330 if (info)
4331 encap = true;
4332 else
4333 return -EOPNOTSUPP;
1482bd3d 4334
73867881
PNA		 4335 break;
4336 case FLOW_ACTION_VLAN_PUSH:
4337 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4338 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4339 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4340 /* Replace vlan pop+push with vlan modify */
4341 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4342 err = add_vlan_rewrite_action(priv,
4343 MLX5_FLOW_NAMESPACE_FDB,
4344 act, parse_attr, hdrs,
4345 &action, extack);
4346 } else {
c620b772 4347 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 4348 }
1482bd3d
JL		 4349 if (err)
4350 return err;
4351
c620b772 4352 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 4353 break;
4354 case FLOW_ACTION_VLAN_MANGLE:
4355 err = add_vlan_rewrite_action(priv,
4356 MLX5_FLOW_NAMESPACE_FDB,
4357 act, parse_attr, hdrs,
4358 &action, extack);
4359 if (err)
4360 return err;
4361
c620b772 4362 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 4363 break;
4364 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4365 decap = true;
73867881 4366 break;
2fbbc30d 4367 case FLOW_ACTION_GOTO:
c7569097
AL		 4368 err = validate_goto_chain(priv, flow, act, action,
4369 extack);
2fbbc30d
EC		 4370 if (err)
4371 return err;
bf07aa73 4372
e88afe75 4373 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4374 attr->dest_chain = act->chain_index;
73867881 4375 break;
4c3844d9 4376 case FLOW_ACTION_CT:
aedd133d 4377 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4378 if (err)
4379 return err;
4380
4381 flow_flag_set(flow, CT);
4382 break;
73867881 4383 default:
2cc1cb1d
TZ		 4384 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4385 return -EOPNOTSUPP;
bf07aa73 4386 }
03a9d11e 4387 }
bdd66ac0 4388
0bac1194
EB		 4389 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4390 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4391 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4392 * tag rewrite.
4393 */
4394 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4395 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4396 &action, extack);
4397 if (err)
4398 return err;
4399 }
4400
c500c86b
PNA		 4401 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4402 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4403 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4404 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4405 if (err)
4406 return err;
27c11b6b
EB		 4407 /* in case all pedit actions are skipped, remove the MOD_HDR
4408 * flag. we might have set split_count either by pedit or
4409 * pop/push. if there is no pop/push either, reset it too.
4410 */
6ae4a6a5 4411 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4412 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4413 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4414 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4415 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4416 esw_attr->split_count = 0;
27c11b6b 4417 }
c500c86b
PNA		 4418 }
4419
1cab1cd7 4420 attr->action = action;
73867881 4421 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4422 return -EOPNOTSUPP;
4423
e88afe75 4424 if (attr->dest_chain) {
0a7fcb78
PB		 4425 if (decap) {
4426 /* It can be supported if we'll create a mapping for
4427 * the tunnel device only (without tunnel), and set
4428 * this tunnel id with this decap flow.
4429 *
4430 * On restore (miss), we'll just set this saved tunnel
4431 * device.
4432 */
4433
4434 NL_SET_ERR_MSG(extack,
4435 "Decap with goto isn't supported");
4436 netdev_warn(priv->netdev,
4437 "Decap with goto isn't supported");
4438 return -EOPNOTSUPP;
4439 }
4440
e88afe75 4441 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 4442 NL_SET_ERR_MSG_MOD(extack,
4443 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 4444 return -EOPNOTSUPP;
4445 }
4446 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4447 }
4448
ae2741e2
VB		 4449 if (!(attr->action &
4450 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4451 NL_SET_ERR_MSG_MOD(extack,
4452 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4453 return -EOPNOTSUPP;
4454 }
4455
c620b772 4456 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4457 NL_SET_ERR_MSG_MOD(extack,
4458 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4459 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4460 return -EOPNOTSUPP;
4461 }
4462
31c8eba5 4463 return 0;
03a9d11e
OG		 4464}
4465
226f2ca3 4466static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4467{
226f2ca3 4468 unsigned long __flow_flags = 0;
60bd4af8 4469
226f2ca3
VB		 4470 if (flags & MLX5_TC_FLAG(INGRESS))
4471 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4472 if (flags & MLX5_TC_FLAG(EGRESS))
4473 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4474
226f2ca3
VB		 4475 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4476 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4477 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4478 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4479 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4480 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4481
60bd4af8
OG		 4482 *flow_flags = __flow_flags;
4483}
4484
05866c82
OG		 4485static const struct rhashtable_params tc_ht_params = {
4486 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4487 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4488 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4489 .automatic_shrinking = true,
4490};
4491
226f2ca3
VB		 4492static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4493 unsigned long flags)
05866c82 4494{
655dc3d2
OG		 4495 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4496 struct mlx5e_rep_priv *uplink_rpriv;
4497
226f2ca3 4498 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4499 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4500 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4501 } else /* NIC offload */
655dc3d2 4502 return &priv->fs.tc.ht;
05866c82
OG		 4503}
4504
04de7dda
RD		 4505static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4506{
c620b772
AL		 4507 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4508 struct mlx5_flow_attr *attr = flow->attr;
4509 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4510 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4511 bool act_is_encap = !!(attr->action &
4512 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4513 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4514 MLX5_DEVCOM_ESW_OFFLOADS);
4515
10fbb1cd
RD		 4516 if (!esw_paired)
4517 return false;
4518
c620b772
AL		 4519 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4520 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4521 (is_rep_ingress || act_is_encap))
4522 return true;
4523
4524 return false;
04de7dda
RD		 4525}
4526
c620b772
AL		 4527struct mlx5_flow_attr *
4528mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4529{
4530 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4531 sizeof(struct mlx5_esw_flow_attr) :
4532 sizeof(struct mlx5_nic_flow_attr);
4533 struct mlx5_flow_attr *attr;
4534
4535 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4536}
4537
a88780a9
RD		 4538static int
4539mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4540 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4541 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4542 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4543{
17091853 4544 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4545 struct mlx5_flow_attr *attr;
3bc4b7bf 4546 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4547 int err = -ENOMEM;
4548 int out_index;
e3a2b7ed 4549
c620b772 4550 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4551 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4552 if (!parse_attr || !flow)
4553 goto err_free;
c620b772
AL		 4554
4555 flow->flags = flow_flags;
4556 flow->cookie = f->cookie;
4557 flow->priv = priv;
4558
4559 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4560 if (!attr)
e3a2b7ed 4561 goto err_free;
ff7ea04a 4562
c620b772 4563 flow->attr = attr;
e3a2b7ed 4564
5a7e5bcb
VB		 4565 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4566 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4567 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4568 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4569 refcount_set(&flow->refcnt, 1);
95435ad7 4570 init_completion(&flow->init_done);
e3a2b7ed 4571
a88780a9
RD		 4572 *__flow = flow;
4573 *__parse_attr = parse_attr;
4574
4575 return 0;
4576
4577err_free:
4578 kfree(flow);
4579 kvfree(parse_attr);
4580 return err;
4581}
4582
c7569097
AL		 4583static void
4584mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4585 struct mlx5e_tc_flow_parse_attr *parse_attr,
4586 struct flow_cls_offload *f)
4587{
4588 attr->parse_attr = parse_attr;
4589 attr->chain = f->common.chain_index;
4590 attr->prio = f->common.prio;
4591}
4592
988ab9c7 4593static void
c620b772 4594mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4595 struct mlx5e_priv *priv,
4596 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4597 struct flow_cls_offload *f,
988ab9c7
TZ		 4598 struct mlx5_eswitch_rep *in_rep,
4599 struct mlx5_core_dev *in_mdev)
4600{
4601 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4602 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4603
c7569097 4604 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4605
4606 esw_attr->in_rep = in_rep;
4607 esw_attr->in_mdev = in_mdev;
4608
4609 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4610 MLX5_COUNTER_SOURCE_ESWITCH)
4611 esw_attr->counter_dev = in_mdev;
4612 else
4613 esw_attr->counter_dev = priv->mdev;
4614}
4615
71129676 4616static struct mlx5e_tc_flow *
04de7dda 4617__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4618 struct flow_cls_offload *f,
226f2ca3 4619 unsigned long flow_flags,
04de7dda
RD		 4620 struct net_device *filter_dev,
4621 struct mlx5_eswitch_rep *in_rep,
71129676 4622 struct mlx5_core_dev *in_mdev)
a88780a9 4623{
f9e30088 4624 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4625 struct netlink_ext_ack *extack = f->common.extack;
4626 struct mlx5e_tc_flow_parse_attr *parse_attr;
4627 struct mlx5e_tc_flow *flow;
4628 int attr_size, err;
e3a2b7ed 4629
226f2ca3 4630 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4631 attr_size = sizeof(struct mlx5_esw_flow_attr);
4632 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4633 &parse_attr, &flow);
4634 if (err)
4635 goto out;
988ab9c7 4636
d11afc26 4637 parse_attr->filter_dev = filter_dev;
c620b772 4638 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4639 priv, parse_attr,
4640 f, in_rep, in_mdev);
4641
54c177ca
OS		 4642 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4643 f, filter_dev);
d11afc26
OS		 4644 if (err)
4645 goto err_free;
a88780a9 4646
7e36feeb 4647 /* actions validation depends on parsing the ct matches first */
aedd133d 4648 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4649 &flow->attr->ct_attr, extack);
a88780a9
RD		 4650 if (err)
4651 goto err_free;
4652
7e36feeb 4653 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4654 if (err)
4655 goto err_free;
4656
7040632d 4657 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4658 complete_all(&flow->init_done);
ef06c9ee
RD		 4659 if (err) {
4660 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4661 goto err_free;
4662
b4a23329 4663 add_unready_flow(flow);
ef06c9ee 4664 }
e3a2b7ed 4665
71129676 4666 return flow;
a88780a9
RD		 4667
4668err_free:
e68e28b4 4669 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4670 mlx5e_flow_put(priv, flow);
a88780a9 4671out:
71129676 4672 return ERR_PTR(err);
a88780a9
RD		 4673}
4674
f9e30088 4675static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4676 struct mlx5e_tc_flow *flow,
226f2ca3 4677 unsigned long flow_flags)
04de7dda
RD		 4678{
4679 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4680 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4681 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4682 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4683 struct mlx5e_tc_flow_parse_attr *parse_attr;
4684 struct mlx5e_rep_priv *peer_urpriv;
4685 struct mlx5e_tc_flow *peer_flow;
4686 struct mlx5_core_dev *in_mdev;
4687 int err = 0;
4688
4689 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4690 if (!peer_esw)
4691 return -ENODEV;
4692
4693 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4694 peer_priv = netdev_priv(peer_urpriv->netdev);
4695
4696 /* in_mdev is assigned of which the packet originated from.
4697 * So packets redirected to uplink use the same mdev of the
4698 * original flow and packets redirected from uplink use the
4699 * peer mdev.
4700 */
c620b772 4701 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4702 in_mdev = peer_priv->mdev;
4703 else
4704 in_mdev = priv->mdev;
4705
c620b772 4706 parse_attr = flow->attr->parse_attr;
95dc1902 4707 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4708 parse_attr->filter_dev,
c620b772 4709 attr->in_rep, in_mdev);
71129676
JG		 4710 if (IS_ERR(peer_flow)) {
4711 err = PTR_ERR(peer_flow);
04de7dda 4712 goto out;
71129676 4713 }
04de7dda
RD		 4714
4715 flow->peer_flow = peer_flow;
226f2ca3 4716 flow_flag_set(flow, DUP);
04de7dda
RD		 4717 mutex_lock(&esw->offloads.peer_mutex);
4718 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4719 mutex_unlock(&esw->offloads.peer_mutex);
4720
4721out:
4722 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4723 return err;
4724}
4725
4726static int
4727mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4728 struct flow_cls_offload *f,
226f2ca3 4729 unsigned long flow_flags,
04de7dda
RD		 4730 struct net_device *filter_dev,
4731 struct mlx5e_tc_flow **__flow)
4732{
4733 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4734 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4735 struct mlx5_core_dev *in_mdev = priv->mdev;
4736 struct mlx5e_tc_flow *flow;
4737 int err;
4738
71129676
JG		 4739 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4740 in_mdev);
4741 if (IS_ERR(flow))
4742 return PTR_ERR(flow);
04de7dda
RD		 4743
4744 if (is_peer_flow_needed(flow)) {
95dc1902 4745 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4746 if (err) {
4747 mlx5e_tc_del_fdb_flow(priv, flow);
4748 goto out;
4749 }
4750 }
4751
4752 *__flow = flow;
4753
4754 return 0;
4755
4756out:
4757 return err;
4758}
4759
a88780a9
RD		 4760static int
4761mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4762 struct flow_cls_offload *f,
226f2ca3 4763 unsigned long flow_flags,
d11afc26 4764 struct net_device *filter_dev,
a88780a9
RD		 4765 struct mlx5e_tc_flow **__flow)
4766{
f9e30088 4767 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4768 struct netlink_ext_ack *extack = f->common.extack;
4769 struct mlx5e_tc_flow_parse_attr *parse_attr;
4770 struct mlx5e_tc_flow *flow;
4771 int attr_size, err;
4772
c7569097
AL		 4773 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4774 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4775 return -EOPNOTSUPP;
4776 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4777 return -EOPNOTSUPP;
c7569097 4778 }
bf07aa73 4779
226f2ca3 4780 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4781 attr_size = sizeof(struct mlx5_nic_flow_attr);
4782 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4783 &parse_attr, &flow);
4784 if (err)
4785 goto out;
4786
d11afc26 4787 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4788 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4789
54c177ca
OS		 4790 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4791 f, filter_dev);
d11afc26
OS		 4792 if (err)
4793 goto err_free;
4794
aedd133d
AL		 4795 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4796 &flow->attr->ct_attr, extack);
4797 if (err)
4798 goto err_free;
4799
73867881 4800 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4801 if (err)
4802 goto err_free;
4803
4804 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4805 if (err)
4806 goto err_free;
4807
226f2ca3 4808 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4809 *__flow = flow;
4810
4811 return 0;
e3a2b7ed 4812
e3a2b7ed 4813err_free:
e68e28b4 4814 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4815 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4816out:
4817 return err;
4818}
4819
4820static int
4821mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4822 struct flow_cls_offload *f,
226f2ca3 4823 unsigned long flags,
d11afc26 4824 struct net_device *filter_dev,
a88780a9
RD		 4825 struct mlx5e_tc_flow **flow)
4826{
4827 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4828 unsigned long flow_flags;
a88780a9
RD		 4829 int err;
4830
4831 get_flags(flags, &flow_flags);
4832
bf07aa73
PB		 4833 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4834 return -EOPNOTSUPP;
4835
f6455de0 4836 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4837 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4838 filter_dev, flow);
a88780a9 4839 else
d11afc26
OS		 4840 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4841 filter_dev, flow);
a88780a9
RD		 4842
4843 return err;
4844}
4845
553f9328
VP		 4846static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4847 struct mlx5e_rep_priv *rpriv)
4848{
4849 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4850 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4851 * function is called from NIC mode.
553f9328 4852 */
2fb15e72 4853 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4854}
4855
71d82d2a 4856int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4857 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4858{
4859 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4860 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4861 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4862 struct mlx5e_tc_flow *flow;
4863 int err = 0;
4864
c5d326b2
VB		 4865 rcu_read_lock();
4866 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4867 if (flow) {
553f9328
VP		 4868 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4869 * just return 0.
4870 */
4871 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4872 goto rcu_unlock;
553f9328 4873
a88780a9
RD		 4874 NL_SET_ERR_MSG_MOD(extack,
4875 "flow cookie already exists, ignoring");
4876 netdev_warn_once(priv->netdev,
4877 "flow cookie %lx already exists, ignoring\n",
4878 f->cookie);
0e1c1a2f 4879 err = -EEXIST;
c1aea9e1 4880 goto rcu_unlock;
a88780a9 4881 }
c1aea9e1
VB		 4882rcu_unlock:
4883 rcu_read_unlock();
4884 if (flow)
4885 goto out;
a88780a9 4886
7a978759 4887 trace_mlx5e_configure_flower(f);
d11afc26 4888 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4889 if (err)
4890 goto out;
4891
553f9328
VP		 4892 /* Flow rule offloaded to non-uplink representor sharing tc block,
4893 * set the flow's owner dev.
4894 */
4895 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4896 flow->orig_dev = dev;
4897
c5d326b2 4898 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4899 if (err)
4900 goto err_free;
4901
4902 return 0;
4903
4904err_free:
5a7e5bcb 4905 mlx5e_flow_put(priv, flow);
a88780a9 4906out:
e3a2b7ed
AV		 4907 return err;
4908}
4909
8f8ae895
OG		 4910static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4911{
226f2ca3
VB		 4912 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4913 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4914
226f2ca3
VB		 4915 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4916 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4917}
4918
71d82d2a 4919int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4920 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4921{
d9ee0491 4922 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4923 struct mlx5e_tc_flow *flow;
c5d326b2 4924 int err;
e3a2b7ed 4925
c5d326b2 4926 rcu_read_lock();
ab818362 4927 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4928 if (!flow || !same_flow_direction(flow, flags)) {
4929 err = -EINVAL;
4930 goto errout;
4931 }
e3a2b7ed 4932
c5d326b2
VB		 4933 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4934 * set.
4935 */
4936 if (flow_flag_test_and_set(flow, DELETED)) {
4937 err = -EINVAL;
4938 goto errout;
4939 }
05866c82 4940 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4941 rcu_read_unlock();
e3a2b7ed 4942
7a978759 4943 trace_mlx5e_delete_flower(f);
5a7e5bcb 4944 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4945
4946 return 0;
c5d326b2
VB		 4947
4948errout:
4949 rcu_read_unlock();
4950 return err;
e3a2b7ed
AV		 4951}
4952
71d82d2a 4953int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4954 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4955{
04de7dda 4956 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4957 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4958 struct mlx5_eswitch *peer_esw;
aad7e08d 4959 struct mlx5e_tc_flow *flow;
aad7e08d 4960 struct mlx5_fc *counter;
316d5f72
RD		 4961 u64 lastuse = 0;
4962 u64 packets = 0;
4963 u64 bytes = 0;
5a7e5bcb 4964 int err = 0;
aad7e08d 4965
c5d326b2
VB		 4966 rcu_read_lock();
4967 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4968 tc_ht_params));
4969 rcu_read_unlock();
5a7e5bcb
VB		 4970 if (IS_ERR(flow))
4971 return PTR_ERR(flow);
4972
4973 if (!same_flow_direction(flow, flags)) {
4974 err = -EINVAL;
4975 goto errout;
4976 }
aad7e08d 4977
4c3844d9 4978 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4979 counter = mlx5e_tc_get_counter(flow);
4980 if (!counter)
5a7e5bcb 4981 goto errout;
aad7e08d 4982
316d5f72
RD		 4983 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4984 }
aad7e08d 4985
316d5f72
RD		 4986 /* Under multipath it's possible for one rule to be currently
4987 * un-offloaded while the other rule is offloaded.
4988 */
04de7dda
RD		 4989 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4990 if (!peer_esw)
4991 goto out;
4992
226f2ca3
VB		 4993 if (flow_flag_test(flow, DUP) &&
4994 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4995 u64 bytes2;
4996 u64 packets2;
4997 u64 lastuse2;
4998
4999 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 5000 if (!counter)
5001 goto no_peer_counter;
04de7dda
RD		 5002 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
5003
5004 bytes += bytes2;
5005 packets += packets2;
5006 lastuse = max_t(u64, lastuse, lastuse2);
5007 }
5008
316d5f72 5009no_peer_counter:
04de7dda 5010 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 5011out:
4b61d3e8 5012 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 5013 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 5014 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 5015errout:
5016 mlx5e_flow_put(priv, flow);
5017 return err;
aad7e08d
AV		 5018}
5019
1fe3e316 5020static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 5021 struct netlink_ext_ack *extack)
5022{
5023 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5024 struct mlx5_eswitch *esw;
1fe3e316 5025 u32 rate_mbps = 0;
fcb64c0f 5026 u16 vport_num;
fcb64c0f
EC		 5027 int err;
5028
e401a184
EC		 5029 vport_num = rpriv->rep->vport;
5030 if (vport_num >= MLX5_VPORT_ECPF) {
5031 NL_SET_ERR_MSG_MOD(extack,
5032 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5033 return -EOPNOTSUPP;
5034 }
5035
fcb64c0f
EC		 5036 esw = priv->mdev->priv.eswitch;
5037 /* rate is given in bytes/sec.
5038 * First convert to bits/sec and then round to the nearest mbit/secs.
5039 * mbit means million bits.
5040 * Moreover, if rate is non zero we choose to configure to a minimum of
5041 * 1 mbit/sec.
5042 */
1fe3e316
PP		 5043 if (rate) {
5044 rate = (rate * BITS_PER_BYTE) + 500000;
5045 rate_mbps = max_t(u32, do_div(rate, 1000000), 1);
5046 }
5047
fcb64c0f
EC		 5048 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
5049 if (err)
5050 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5051
5052 return err;
5053}
5054
5055static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5056 struct flow_action *flow_action,
5057 struct netlink_ext_ack *extack)
5058{
5059 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5060 const struct flow_action_entry *act;
5061 int err;
5062 int i;
5063
5064 if (!flow_action_has_entries(flow_action)) {
5065 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5066 return -EINVAL;
5067 }
5068
5069 if (!flow_offload_has_one_action(flow_action)) {
5070 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5071 return -EOPNOTSUPP;
5072 }
5073
53eca1f3 5074 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 5075 return -EOPNOTSUPP;
5076
fcb64c0f
EC		 5077 flow_action_for_each(i, act, flow_action) {
5078 switch (act->id) {
5079 case FLOW_ACTION_POLICE:
5080 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5081 if (err)
5082 return err;
5083
5084 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
5085 break;
5086 default:
5087 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5088 return -EOPNOTSUPP;
5089 }
5090 }
5091
5092 return 0;
5093}
5094
5095int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5096 struct tc_cls_matchall_offload *ma)
5097{
b5f814cc 5098 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 5099 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 5100
b5f814cc
EC		 5101 if (!mlx5_esw_qos_enabled(esw)) {
5102 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
5103 return -EOPNOTSUPP;
5104 }
5105
7b83355f 5106 if (ma->common.prio != 1) {
fcb64c0f
EC		 5107 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5108 return -EINVAL;
5109 }
5110
5111 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5112}
5113
5114int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5115 struct tc_cls_matchall_offload *ma)
5116{
5117 struct netlink_ext_ack *extack = ma->common.extack;
5118
5119 return apply_police_params(priv, 0, extack);
5120}
5121
5122void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5123 struct tc_cls_matchall_offload *ma)
5124{
5125 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5126 struct rtnl_link_stats64 cur_stats;
5127 u64 dbytes;
5128 u64 dpkts;
5129
5130 cur_stats = priv->stats.vf_vport;
5131 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5132 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5133 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 5134 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 5135 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 5136}
5137
4d8fcf21
AH		 5138static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5139 struct mlx5e_priv *peer_priv)
5140{
5141 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 5142 struct mlx5e_hairpin_entry *hpe, *tmp;
5143 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 5144 u16 peer_vhca_id;
5145 int bkt;
5146
5147 if (!same_hw_devs(priv, peer_priv))
5148 return;
5149
5150 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5151
b32accda 5152 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 5153 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
5154 if (refcount_inc_not_zero(&hpe->refcnt))
5155 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5156 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5157
5158 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5159 wait_for_completion(&hpe->res_ready);
5160 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 5161 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 5162
5163 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 5164 }
5165}
5166
5167static int mlx5e_tc_netdev_event(struct notifier_block *this,
5168 unsigned long event, void *ptr)
5169{
5170 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5171 struct mlx5e_flow_steering *fs;
5172 struct mlx5e_priv *peer_priv;
5173 struct mlx5e_tc_table *tc;
5174 struct mlx5e_priv *priv;
5175
5176 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5177 event != NETDEV_UNREGISTER ||
5178 ndev->reg_state == NETREG_REGISTERED)
5179 return NOTIFY_DONE;
5180
5181 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5182 fs = container_of(tc, struct mlx5e_flow_steering, tc);
5183 priv = container_of(fs, struct mlx5e_priv, fs);
5184 peer_priv = netdev_priv(ndev);
5185 if (priv == peer_priv ||
5186 !(priv->netdev->features & NETIF_F_HW_TC))
5187 return NOTIFY_DONE;
5188
5189 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5190
5191 return NOTIFY_DONE;
5192}
5193
6a064674
AL		 5194static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
5195{
5196 int tc_grp_size, tc_tbl_size;
5197 u32 max_flow_counter;
5198
5199 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
5200 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
5201
5202 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
5203
5204 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
5205 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
5206
5207 return tc_tbl_size;
5208}
5209
655dc3d2 5210int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 5211{
acff797c 5212 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674
AL		 5213 struct mlx5_core_dev *dev = priv->mdev;
5214 struct mlx5_chains_attr attr = {};
4d8fcf21 5215 int err;
e8f887ac 5216
b2fdf3d0 5217 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 5218 mutex_init(&tc->t_lock);
b32accda 5219 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 5220 hash_init(tc->hairpin_tbl);
11c9c548 5221
4d8fcf21
AH		 5222 err = rhashtable_init(&tc->ht, &tc_ht_params);
5223 if (err)
5224 return err;
5225
9ba33339
RD		 5226 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5227
c7569097
AL		 5228 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
5229 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5230 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5231 attr.max_restore_tag = MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5232 }
6a064674
AL		 5233 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5234 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
5235 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5236 attr.default_ft = priv->fs.vlan.ft.t;
5237
5238 tc->chains = mlx5_chains_create(dev, &attr);
5239 if (IS_ERR(tc->chains)) {
5240 err = PTR_ERR(tc->chains);
5241 goto err_chains;
5242 }
5243
aedd133d
AL		 5244 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
5245 MLX5_FLOW_NAMESPACE_KERNEL);
68ec32da
WH		 5246 if (IS_ERR(tc->ct)) {
5247 err = PTR_ERR(tc->ct);
aedd133d 5248 goto err_ct;
68ec32da 5249 }
aedd133d 5250
4d8fcf21 5251 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 5252 err = register_netdevice_notifier_dev_net(priv->netdev,
5253 &tc->netdevice_nb,
5254 &tc->netdevice_nn);
5255 if (err) {
4d8fcf21
AH		 5256 tc->netdevice_nb.notifier_call = NULL;
5257 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 5258 goto err_reg;
4d8fcf21
AH		 5259 }
5260
6a064674
AL		 5261 return 0;
5262
5263err_reg:
aedd133d
AL		 5264 mlx5_tc_ct_clean(tc->ct);
5265err_ct:
6a064674
AL		 5266 mlx5_chains_destroy(tc->chains);
5267err_chains:
5268 rhashtable_destroy(&tc->ht);
4d8fcf21 5269 return err;
e8f887ac
AV		 5270}
5271
5272static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5273{
5274 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5275 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5276
961e8979 5277 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5278 kfree(flow);
5279}
5280
655dc3d2 5281void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5282{
acff797c 5283 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5284
4d8fcf21 5285 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5286 unregister_netdevice_notifier_dev_net(priv->netdev,
5287 &tc->netdevice_nb,
5288 &tc->netdevice_nn);
4d8fcf21 5289
b2fdf3d0 5290 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 5291 mutex_destroy(&tc->hairpin_tbl_lock);
5292
6a064674 5293 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 5294
acff797c 5295 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 5296 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 5297 tc->t = NULL;
e8f887ac 5298 }
b6fac0b4 5299 mutex_destroy(&tc->t_lock);
6a064674 5300
aedd133d 5301 mlx5_tc_ct_clean(tc->ct);
6a064674 5302 mlx5_chains_destroy(tc->chains);
e8f887ac 5303}
655dc3d2
OG		 5304
5305int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5306{
d7a42ad0 5307 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 5308 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 5309 struct mlx5e_rep_priv *rpriv;
0a7fcb78 5310 struct mapping_ctx *mapping;
aedd133d
AL		 5311 struct mlx5_eswitch *esw;
5312 struct mlx5e_priv *priv;
5313 int err = 0;
0a7fcb78
PB		 5314
5315 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5316 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5317 priv = netdev_priv(rpriv->netdev);
5318 esw = priv->mdev->priv.eswitch;
0a7fcb78 5319
aedd133d
AL		 5320 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5321 esw_chains(esw),
5322 &esw->offloads.mod_hdr,
5323 MLX5_FLOW_NAMESPACE_FDB);
5324 if (IS_ERR(uplink_priv->ct_priv))
4c3844d9
PB		 5325 goto err_ct;
5326
0a7fcb78
PB		 5327 mapping = mapping_create(sizeof(struct tunnel_match_key),
5328 TUNNEL_INFO_BITS_MASK, true);
5329 if (IS_ERR(mapping)) {
5330 err = PTR_ERR(mapping);
5331 goto err_tun_mapping;
5332 }
5333 uplink_priv->tunnel_mapping = mapping;
5334
5335 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
5336 if (IS_ERR(mapping)) {
5337 err = PTR_ERR(mapping);
5338 goto err_enc_opts_mapping;
5339 }
5340 uplink_priv->tunnel_enc_opts_mapping = mapping;
5341
5342 err = rhashtable_init(tc_ht, &tc_ht_params);
5343 if (err)
5344 goto err_ht_init;
5345
9ba33339
RD		 5346 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5347
0a7fcb78
PB		 5348 return err;
5349
5350err_ht_init:
5351 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5352err_enc_opts_mapping:
5353 mapping_destroy(uplink_priv->tunnel_mapping);
5354err_tun_mapping:
aedd133d 5355 mlx5_tc_ct_clean(uplink_priv->ct_priv);
4c3844d9 5356err_ct:
0a7fcb78
PB		 5357 netdev_warn(priv->netdev,
5358 "Failed to initialize tc (eswitch), err: %d", err);
5359 return err;
655dc3d2
OG		 5360}
5361
5362void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5363{
0a7fcb78
PB		 5364 struct mlx5_rep_uplink_priv *uplink_priv;
5365
655dc3d2 5366 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 5367
5368 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5369
0a7fcb78
PB		 5370 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5371 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5372
aedd133d 5373 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 5374}
01252a27 5375
226f2ca3 5376int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5377{
d9ee0491 5378 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5379
5380 return atomic_read(&tc_ht->nelems);
5381}
04de7dda
RD		 5382
5383void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5384{
5385 struct mlx5e_tc_flow *flow, *tmp;
5386
5387 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5388 __mlx5e_tc_del_fdb_peer_flow(flow);
5389}
b4a23329
RD		 5390
5391void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5392{
5393 struct mlx5_rep_uplink_priv *rpriv =
5394 container_of(work, struct mlx5_rep_uplink_priv,
5395 reoffload_flows_work);
5396 struct mlx5e_tc_flow *flow, *tmp;
5397
ad86755b 5398 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5399 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5400 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5401 unready_flow_del(flow);
b4a23329 5402 }
ad86755b 5403 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5404}
e2394a61
VB		 5405
5406static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5407 struct flow_cls_offload *cls_flower,
5408 unsigned long flags)
5409{
5410 switch (cls_flower->command) {
5411 case FLOW_CLS_REPLACE:
5412 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5413 flags);
5414 case FLOW_CLS_DESTROY:
5415 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5416 flags);
5417 case FLOW_CLS_STATS:
5418 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5419 flags);
5420 default:
5421 return -EOPNOTSUPP;
5422 }
5423}
5424
5425int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5426 void *cb_priv)
5427{
5428 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
5429 struct mlx5e_priv *priv = cb_priv;
5430
5431 switch (type) {
5432 case TC_SETUP_CLSFLOWER:
5433 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5434 default:
5435 return -EOPNOTSUPP;
5436 }
5437}
c7569097
AL		 5438
5439bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5440 struct sk_buff *skb)
5441{
5442#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5443 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5444 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5445 struct mlx5e_tc_table *tc = &priv->fs.tc;
c7569097
AL		 5446 struct tc_skb_ext *tc_skb_ext;
5447 int err;
5448
5449 reg_b = be32_to_cpu(cqe->ft_metadata);
5450
5451 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5452
5453 err = mlx5_get_chain_for_tag(nic_chains(priv), chain_tag, &chain);
5454 if (err) {
5455 netdev_dbg(priv->netdev,
5456 "Couldn't find chain for chain tag: %d, err: %d\n",
5457 chain_tag, err);
5458 return false;
5459 }
5460
5461 if (chain) {
5462 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
5463 if (WARN_ON(!tc_skb_ext))
5464 return false;
5465
5466 tc_skb_ext->chain = chain;
aedd133d
AL		 5467
5468 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
5469 ZONE_RESTORE_MAX;
5470
5471 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5472 zone_restore_id))
5473 return false;
c7569097
AL		 5474 }
5475#endif /* CONFIG_NET_TC_SKB_EXT */
5476
5477 return true;
5478}
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