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net/mlx5e: TC, Handle sampled packets
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
41c2fd94 50#include <net/psample.h>
f6dfb4c3 51#include <net/arp.h>
3616d08b 52#include <net/ipv6_stubs.h>
f828ca6a 53#include <net/bareudp.h>
d34eb2fc 54#include <net/bonding.h>
e8f887ac 55#include "en.h"
1d447a39 56#include "en_rep.h"
768c3667 57#include "en/rep/tc.h"
e2394a61 58#include "en/rep/neigh.h"
232c0013 59#include "en_tc.h"
03a9d11e 60#include "eswitch.h"
3f6d08d1 61#include "fs_core.h"
2c81bfd5 62#include "en/port.h"
101f4de9 63#include "en/tc_tun.h"
0a7fcb78 64#include "en/mapping.h"
4c3844d9 65#include "en/tc_ct.h"
b2fdf3d0 66#include "en/mod_hdr.h"
0d9f9647
VB		 67#include "en/tc_priv.h"
68#include "en/tc_tun_encap.h"
2a9ab10a 69#include "esw/sample.h"
04de7dda 70#include "lib/devcom.h"
9272e3df 71#include "lib/geneve.h"
ae430332 72#include "lib/fs_chains.h"
7a978759 73#include "diag/en_tc_tracepoint.h"
1fe3e316 74#include <asm/div64.h>
e8f887ac 75
6a064674 76#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 77#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 78
acff797c 79#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 80#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 81
8f1e0b97
PB		 82struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
83 [CHAIN_TO_REG] = {
84 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
85 .moffset = 0,
86 .mlen = 2,
87 },
10742efc
VB		 88 [VPORT_TO_REG] = {
89 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
90 .moffset = 2,
91 .mlen = 2,
92 },
0a7fcb78
PB		 93 [TUNNEL_TO_REG] = {
94 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521 95 .moffset = 1,
48d216e5 96 .mlen = ((ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS) / 8),
0a7fcb78
PB		 97 .soffset = MLX5_BYTE_OFF(fte_match_param,
98 misc_parameters_2.metadata_reg_c_1),
99 },
4c3844d9 100 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 101 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 102 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
103 [MARK_TO_REG] = mark_to_reg_ct,
104 [LABELS_TO_REG] = labels_to_reg_ct,
105 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 106 /* For NIC rules we store the retore metadata directly
107 * into reg_b that is passed to SW since we don't
108 * jump between steering domains.
109 */
110 [NIC_CHAIN_TO_REG] = {
111 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
112 .moffset = 0,
113 .mlen = 2,
114 },
aedd133d 115 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 116};
117
9ba33339
RD		 118/* To avoid false lock dependency warning set the tc_ht lock
119 * class different than the lock class of the ht being used when deleting
120 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
121 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
122 * it's different than the ht->mutex here.
123 */
124static struct lock_class_key tc_ht_lock_key;
125
0a7fcb78
PB		 126static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
127
128void
129mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
130 enum mlx5e_tc_attr_to_reg type,
131 u32 data,
132 u32 mask)
133{
134 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
135 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
136 void *headers_c = spec->match_criteria;
137 void *headers_v = spec->match_value;
138 void *fmask, *fval;
139
140 fmask = headers_c + soffset;
141 fval = headers_v + soffset;
142
58ff18e1
SM		 143 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
144 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 145
146 memcpy(fmask, &mask, match_len);
147 memcpy(fval, &data, match_len);
148
149 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
150}
151
7e36feeb
PB		 152void
153mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
154 enum mlx5e_tc_attr_to_reg type,
155 u32 *data,
156 u32 *mask)
157{
158 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
159 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
160 void *headers_c = spec->match_criteria;
161 void *headers_v = spec->match_value;
162 void *fmask, *fval;
163
164 fmask = headers_c + soffset;
165 fval = headers_v + soffset;
166
167 memcpy(mask, fmask, match_len);
168 memcpy(data, fval, match_len);
169
170 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
171 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
172}
173
0a7fcb78 174int
c7b9038d
VB		 175mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
176 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
177 enum mlx5_flow_namespace_type ns,
178 enum mlx5e_tc_attr_to_reg type,
179 u32 data)
0a7fcb78
PB		 180{
181 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
182 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
183 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
184 char *modact;
185 int err;
186
aedd133d 187 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 188 if (err)
189 return err;
190
191 modact = mod_hdr_acts->actions +
192 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
193
194 /* Firmware has 5bit length field and 0 means 32bits */
195 if (mlen == 4)
196 mlen = 0;
197
198 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
199 MLX5_SET(set_action_in, modact, field, mfield);
200 MLX5_SET(set_action_in, modact, offset, moffset * 8);
201 MLX5_SET(set_action_in, modact, length, mlen * 8);
202 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 203 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 204 mod_hdr_acts->num_actions++;
205
c7b9038d 206 return err;
0a7fcb78
PB		 207}
208
aedd133d
AL		 209static struct mlx5_tc_ct_priv *
210get_ct_priv(struct mlx5e_priv *priv)
211{
212 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
213 struct mlx5_rep_uplink_priv *uplink_priv;
214 struct mlx5e_rep_priv *uplink_rpriv;
215
e8711402 216 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 217 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
218 uplink_priv = &uplink_rpriv->uplink_priv;
219
220 return uplink_priv->ct_priv;
221 }
222
223 return priv->fs.tc.ct;
224}
225
226struct mlx5_flow_handle *
227mlx5_tc_rule_insert(struct mlx5e_priv *priv,
228 struct mlx5_flow_spec *spec,
229 struct mlx5_flow_attr *attr)
230{
231 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232
e8711402 233 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 234 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
235
236 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
237}
238
239void
240mlx5_tc_rule_delete(struct mlx5e_priv *priv,
241 struct mlx5_flow_handle *rule,
242 struct mlx5_flow_attr *attr)
243{
244 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
245
e8711402 246 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 247 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
248
249 return;
250 }
251
252 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
253}
254
c7b9038d
VB		 255int
256mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
257 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
258 enum mlx5_flow_namespace_type ns,
259 enum mlx5e_tc_attr_to_reg type,
260 u32 data)
261{
262 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
263
264 return ret < 0 ? ret : 0;
265}
266
267void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
268 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
269 enum mlx5e_tc_attr_to_reg type,
270 int act_id, u32 data)
271{
272 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
273 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
274 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
275 char *modact;
276
277 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
278
279 /* Firmware has 5bit length field and 0 means 32bits */
280 if (mlen == 4)
281 mlen = 0;
282
283 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
284 MLX5_SET(set_action_in, modact, field, mfield);
285 MLX5_SET(set_action_in, modact, offset, moffset * 8);
286 MLX5_SET(set_action_in, modact, length, mlen * 8);
287 MLX5_SET(set_action_in, modact, data, data);
288}
289
77ab67b7
OG		 290struct mlx5e_hairpin {
291 struct mlx5_hairpin *pair;
292
293 struct mlx5_core_dev *func_mdev;
3f6d08d1 294 struct mlx5e_priv *func_priv;
77ab67b7
OG		 295 u32 tdn;
296 u32 tirn;
3f6d08d1
OG		 297
298 int num_channels;
299 struct mlx5e_rqt indir_rqt;
300 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
301 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 302};
303
5c65c564
OG		 304struct mlx5e_hairpin_entry {
305 /* a node of a hash table which keeps all the hairpin entries */
306 struct hlist_node hairpin_hlist;
307
73edca73
VB		 308 /* protects flows list */
309 spinlock_t flows_lock;
5c65c564
OG		 310 /* flows sharing the same hairpin */
311 struct list_head flows;
db76ca24
VB		 312 /* hpe's that were not fully initialized when dead peer update event
313 * function traversed them.
314 */
315 struct list_head dead_peer_wait_list;
5c65c564 316
d8822868 317 u16 peer_vhca_id;
106be53b 318 u8 prio;
5c65c564 319 struct mlx5e_hairpin *hp;
e4f9abbd 320 refcount_t refcnt;
db76ca24 321 struct completion res_ready;
5c65c564
OG		 322};
323
5a7e5bcb
VB		 324static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
325 struct mlx5e_tc_flow *flow);
326
0d9f9647 327struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 328{
329 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
330 return ERR_PTR(-EINVAL);
331 return flow;
332}
333
0d9f9647 334void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 335{
336 if (refcount_dec_and_test(&flow->refcnt)) {
337 mlx5e_tc_del_flow(priv, flow);
c5d326b2 338 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 339 }
340}
341
aedd133d 342bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 343{
344 return flow_flag_test(flow, ESWITCH);
345}
346
84179981
PB		 347static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
348{
349 return flow_flag_test(flow, FT);
350}
351
0d9f9647 352bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 353{
354 return flow_flag_test(flow, OFFLOADED);
355}
356
b2fdf3d0 357static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 358{
b2fdf3d0
PB		 359 return mlx5e_is_eswitch_flow(flow) ?
360 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 361}
362
dd58edc3 363static struct mod_hdr_tbl *
b2fdf3d0 364get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 365{
366 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
367
b2fdf3d0
PB		 368 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
369 &esw->offloads.mod_hdr :
dd58edc3
VB		 370 &priv->fs.tc.mod_hdr;
371}
372
11c9c548
OG		 373static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
374 struct mlx5e_tc_flow *flow,
375 struct mlx5e_tc_flow_parse_attr *parse_attr)
376{
b2fdf3d0
PB		 377 struct mlx5_modify_hdr *modify_hdr;
378 struct mlx5e_mod_hdr_handle *mh;
11c9c548 379
b2fdf3d0
PB		 380 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
381 get_flow_name_space(flow),
382 &parse_attr->mod_hdr_acts);
383 if (IS_ERR(mh))
384 return PTR_ERR(mh);
11c9c548 385
b2fdf3d0 386 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 387 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 388 flow->mh = mh;
11c9c548
OG		 389
390 return 0;
11c9c548
OG		 391}
392
393static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
394 struct mlx5e_tc_flow *flow)
395{
5a7e5bcb 396 /* flow wasn't fully initialized */
dd58edc3 397 if (!flow->mh)
5a7e5bcb
VB		 398 return;
399
b2fdf3d0
PB		 400 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
401 flow->mh);
dd58edc3 402 flow->mh = NULL;
11c9c548
OG		 403}
404
77ab67b7
OG		 405static
406struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
407{
408 struct net_device *netdev;
409 struct mlx5e_priv *priv;
410
411 netdev = __dev_get_by_index(net, ifindex);
412 priv = netdev_priv(netdev);
413 return priv->mdev;
414}
415
416static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
417{
e0b4b472 418 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 419 void *tirc;
420 int err;
421
422 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
423 if (err)
424 goto alloc_tdn_err;
425
426 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
427
428 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 429 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 430 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
431
e0b4b472 432 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 433 if (err)
434 goto create_tir_err;
435
436 return 0;
437
438create_tir_err:
439 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
440alloc_tdn_err:
441 return err;
442}
443
444static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
445{
446 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
447 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
448}
449
2119bda6 450static int mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
3f6d08d1 451{
3f6d08d1
OG		 452 struct mlx5e_priv *priv = hp->func_priv;
453 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
6def6e47 454 u32 *indirection_rqt, rqn;
3f6d08d1 455
6def6e47 456 indirection_rqt = kcalloc(sz, sizeof(*indirection_rqt), GFP_KERNEL);
2119bda6
AB		 457 if (!indirection_rqt)
458 return -ENOMEM;
459
3f6d08d1
OG		 460 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
461 hp->num_channels);
462
463 for (i = 0; i < sz; i++) {
464 ix = i;
bbeb53b8 465 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 466 ix = mlx5e_bits_invert(i, ilog2(sz));
467 ix = indirection_rqt[ix];
468 rqn = hp->pair->rqn[ix];
469 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
470 }
2119bda6
AB		 471
472 kfree(indirection_rqt);
473 return 0;
3f6d08d1
OG		 474}
475
476static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
477{
478 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
479 struct mlx5e_priv *priv = hp->func_priv;
480 struct mlx5_core_dev *mdev = priv->mdev;
481 void *rqtc;
482 u32 *in;
483
484 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
485 in = kvzalloc(inlen, GFP_KERNEL);
486 if (!in)
487 return -ENOMEM;
488
489 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
490
491 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
492 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
493
2119bda6
AB		 494 err = mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
495 if (err)
496 goto out;
3f6d08d1
OG		 497
498 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
499 if (!err)
500 hp->indir_rqt.enabled = true;
501
2119bda6 502out:
3f6d08d1
OG		 503 kvfree(in);
504 return err;
505}
506
507static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
508{
509 struct mlx5e_priv *priv = hp->func_priv;
510 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
511 int tt, i, err;
512 void *tirc;
513
514 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 515 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
516
3f6d08d1
OG		 517 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
518 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
519
520 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
521 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
522 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 523 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
524
3f6d08d1 525 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 526 &hp->indir_tirn[tt]);
3f6d08d1
OG		 527 if (err) {
528 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
529 goto err_destroy_tirs;
530 }
531 }
532 return 0;
533
534err_destroy_tirs:
535 for (i = 0; i < tt; i++)
536 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
537 return err;
538}
539
540static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
541{
542 int tt;
543
544 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
545 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
546}
547
548static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
549 struct ttc_params *ttc_params)
550{
551 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
552 int tt;
553
554 memset(ttc_params, 0, sizeof(*ttc_params));
555
556 ttc_params->any_tt_tirn = hp->tirn;
557
558 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
559 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
560
6412bb39 561 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 562 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
563 ft_attr->prio = MLX5E_TC_PRIO;
564}
565
566static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
567{
568 struct mlx5e_priv *priv = hp->func_priv;
569 struct ttc_params ttc_params;
570 int err;
571
572 err = mlx5e_hairpin_create_indirect_rqt(hp);
573 if (err)
574 return err;
575
576 err = mlx5e_hairpin_create_indirect_tirs(hp);
577 if (err)
578 goto err_create_indirect_tirs;
579
580 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
581 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
582 if (err)
583 goto err_create_ttc_table;
584
585 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
586 hp->num_channels, hp->ttc.ft.t->id);
587
588 return 0;
589
590err_create_ttc_table:
591 mlx5e_hairpin_destroy_indirect_tirs(hp);
592err_create_indirect_tirs:
593 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
594
595 return err;
596}
597
598static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
599{
600 struct mlx5e_priv *priv = hp->func_priv;
601
602 mlx5e_destroy_ttc_table(priv, &hp->ttc);
603 mlx5e_hairpin_destroy_indirect_tirs(hp);
604 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
605}
606
77ab67b7
OG		 607static struct mlx5e_hairpin *
608mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
609 int peer_ifindex)
610{
611 struct mlx5_core_dev *func_mdev, *peer_mdev;
612 struct mlx5e_hairpin *hp;
613 struct mlx5_hairpin *pair;
614 int err;
615
616 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
617 if (!hp)
618 return ERR_PTR(-ENOMEM);
619
620 func_mdev = priv->mdev;
621 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
622
623 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
624 if (IS_ERR(pair)) {
625 err = PTR_ERR(pair);
626 goto create_pair_err;
627 }
628 hp->pair = pair;
629 hp->func_mdev = func_mdev;
3f6d08d1
OG		 630 hp->func_priv = priv;
631 hp->num_channels = params->num_channels;
77ab67b7
OG		 632
633 err = mlx5e_hairpin_create_transport(hp);
634 if (err)
635 goto create_transport_err;
636
3f6d08d1
OG		 637 if (hp->num_channels > 1) {
638 err = mlx5e_hairpin_rss_init(hp);
639 if (err)
640 goto rss_init_err;
641 }
642
77ab67b7
OG		 643 return hp;
644
3f6d08d1
OG		 645rss_init_err:
646 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 647create_transport_err:
648 mlx5_core_hairpin_destroy(hp->pair);
649create_pair_err:
650 kfree(hp);
651 return ERR_PTR(err);
652}
653
654static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
655{
3f6d08d1
OG		 656 if (hp->num_channels > 1)
657 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 658 mlx5e_hairpin_destroy_transport(hp);
659 mlx5_core_hairpin_destroy(hp->pair);
660 kvfree(hp);
661}
662
106be53b
OG		 663static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
664{
665 return (peer_vhca_id << 16 | prio);
666}
667
5c65c564 668static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 669 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 670{
671 struct mlx5e_hairpin_entry *hpe;
106be53b 672 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 673
674 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 675 hairpin_hlist, hash_key) {
e4f9abbd
VB		 676 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
677 refcount_inc(&hpe->refcnt);
5c65c564 678 return hpe;
e4f9abbd 679 }
5c65c564
OG		 680 }
681
682 return NULL;
683}
684
e4f9abbd
VB		 685static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
686 struct mlx5e_hairpin_entry *hpe)
687{
688 /* no more hairpin flows for us, release the hairpin pair */
b32accda 689 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 690 return;
b32accda
VB		 691 hash_del(&hpe->hairpin_hlist);
692 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 693
db76ca24
VB		 694 if (!IS_ERR_OR_NULL(hpe->hp)) {
695 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
696 dev_name(hpe->hp->pair->peer_mdev->device));
697
698 mlx5e_hairpin_destroy(hpe->hp);
699 }
e4f9abbd
VB		 700
701 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 702 kfree(hpe);
703}
704
106be53b
OG		 705#define UNKNOWN_MATCH_PRIO 8
706
707static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 708 struct mlx5_flow_spec *spec, u8 *match_prio,
709 struct netlink_ext_ack *extack)
106be53b
OG		 710{
711 void *headers_c, *headers_v;
712 u8 prio_val, prio_mask = 0;
713 bool vlan_present;
714
715#ifdef CONFIG_MLX5_CORE_EN_DCB
716 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 717 NL_SET_ERR_MSG_MOD(extack,
718 "only PCP trust state supported for hairpin");
106be53b
OG		 719 return -EOPNOTSUPP;
720 }
721#endif
722 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
723 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
724
725 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
726 if (vlan_present) {
727 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
728 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
729 }
730
731 if (!vlan_present || !prio_mask) {
732 prio_val = UNKNOWN_MATCH_PRIO;
733 } else if (prio_mask != 0x7) {
e98bedf5
EB		 734 NL_SET_ERR_MSG_MOD(extack,
735 "masked priority match not supported for hairpin");
106be53b
OG		 736 return -EOPNOTSUPP;
737 }
738
739 *match_prio = prio_val;
740 return 0;
741}
742
5c65c564
OG		 743static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
744 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 745 struct mlx5e_tc_flow_parse_attr *parse_attr,
746 struct netlink_ext_ack *extack)
5c65c564 747{
98b66cb1 748 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 749 struct mlx5_hairpin_params params;
d8822868 750 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 751 struct mlx5e_hairpin_entry *hpe;
752 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 753 u64 link_speed64;
754 u32 link_speed;
106be53b 755 u8 match_prio;
d8822868 756 u16 peer_id;
5c65c564
OG		 757 int err;
758
d8822868
OG		 759 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
760 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 761 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 762 return -EOPNOTSUPP;
763 }
764
d8822868 765 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 766 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
767 extack);
106be53b
OG		 768 if (err)
769 return err;
b32accda
VB		 770
771 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 772 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 773 if (hpe) {
774 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
775 wait_for_completion(&hpe->res_ready);
776
777 if (IS_ERR(hpe->hp)) {
778 err = -EREMOTEIO;
779 goto out_err;
780 }
5c65c564 781 goto attach_flow;
db76ca24 782 }
5c65c564
OG		 783
784 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 785 if (!hpe) {
db76ca24
VB		 786 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
787 return -ENOMEM;
b32accda 788 }
5c65c564 789
73edca73 790 spin_lock_init(&hpe->flows_lock);
5c65c564 791 INIT_LIST_HEAD(&hpe->flows);
db76ca24 792 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 793 hpe->peer_vhca_id = peer_id;
106be53b 794 hpe->prio = match_prio;
e4f9abbd 795 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 796 init_completion(&hpe->res_ready);
797
798 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
799 hash_hairpin_info(peer_id, match_prio));
800 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 801
802 params.log_data_size = 15;
803 params.log_data_size = min_t(u8, params.log_data_size,
804 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
805 params.log_data_size = max_t(u8, params.log_data_size,
806 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 807
eb9180f7
OG		 808 params.log_num_packets = params.log_data_size -
809 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
810 params.log_num_packets = min_t(u8, params.log_num_packets,
811 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
812
813 params.q_counter = priv->q_counter;
3f6d08d1 814 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 815 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 816 link_speed = max_t(u32, link_speed, 50000);
817 link_speed64 = link_speed;
818 do_div(link_speed64, 50000);
819 params.num_channels = link_speed64;
820
5c65c564 821 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 822 hpe->hp = hp;
823 complete_all(&hpe->res_ready);
5c65c564
OG		 824 if (IS_ERR(hp)) {
825 err = PTR_ERR(hp);
db76ca24 826 goto out_err;
5c65c564
OG		 827 }
828
eb9180f7 829 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 830 hp->tirn, hp->pair->rqn[0],
831 dev_name(hp->pair->peer_mdev->device),
eb9180f7 832 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 833
5c65c564 834attach_flow:
3f6d08d1 835 if (hpe->hp->num_channels > 1) {
226f2ca3 836 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 837 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 838 } else {
c620b772 839 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 840 }
b32accda 841
e4f9abbd 842 flow->hpe = hpe;
73edca73 843 spin_lock(&hpe->flows_lock);
5c65c564 844 list_add(&flow->hairpin, &hpe->flows);
73edca73 845 spin_unlock(&hpe->flows_lock);
3f6d08d1 846
5c65c564
OG		 847 return 0;
848
db76ca24
VB		 849out_err:
850 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 851 return err;
852}
853
854static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
855 struct mlx5e_tc_flow *flow)
856{
5a7e5bcb 857 /* flow wasn't fully initialized */
e4f9abbd 858 if (!flow->hpe)
5a7e5bcb
VB		 859 return;
860
73edca73 861 spin_lock(&flow->hpe->flows_lock);
5c65c564 862 list_del(&flow->hairpin);
73edca73
VB		 863 spin_unlock(&flow->hpe->flows_lock);
864
e4f9abbd
VB		 865 mlx5e_hairpin_put(priv, flow->hpe);
866 flow->hpe = NULL;
5c65c564
OG		 867}
868
08247066
AL		 869struct mlx5_flow_handle *
870mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
871 struct mlx5_flow_spec *spec,
c620b772 872 struct mlx5_flow_attr *attr)
e8f887ac 873{
08247066 874 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 875 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 876 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 877 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 878 struct mlx5_flow_destination dest[2] = {};
66958ed9 879 struct mlx5_flow_act flow_act = {
3bc4b7bf 880 .action = attr->action,
bb0ee7dc 881 .flags = FLOW_ACT_NO_APPEND,
66958ed9 882 };
08247066 883 struct mlx5_flow_handle *rule;
c7569097 884 struct mlx5_flow_table *ft;
08247066 885 int dest_ix = 0;
e8f887ac 886
bb0ee7dc 887 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 888 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 889
aedd133d
AL		 890 if (attr->dest_ft) {
891 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
892 dest[dest_ix].ft = attr->dest_ft;
893 dest_ix++;
894 } else if (nic_attr->hairpin_ft) {
08247066 895 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 896 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 897 dest_ix++;
c620b772 898 } else if (nic_attr->hairpin_tirn) {
08247066 899 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 900 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 901 dest_ix++;
3f6d08d1
OG		 902 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
903 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 904 if (attr->dest_chain) {
905 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
906 attr->dest_chain, 1,
907 MLX5E_TC_FT_LEVEL);
908 if (IS_ERR(dest[dest_ix].ft))
909 return ERR_CAST(dest[dest_ix].ft);
910 } else {
6783f0a2 911 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 912 }
3f6d08d1 913 dest_ix++;
5c65c564 914 }
aad7e08d 915
c7569097
AL		 916 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
917 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
918 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
919
08247066 920 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 921 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 922 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 923 dest_ix++;
aad7e08d
AV		 924 }
925
08247066 926 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 927 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 928
6a064674
AL		 929 mutex_lock(&tc->t_lock);
930 if (IS_ERR_OR_NULL(tc->t)) {
931 /* Create the root table here if doesn't exist yet */
932 tc->t =
c7569097 933 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 934
935 if (IS_ERR(tc->t)) {
936 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 937 netdev_err(priv->netdev,
938 "Failed to create tc offload table\n");
c7569097
AL		 939 rule = ERR_CAST(priv->fs.tc.t);
940 goto err_ft_get;
e8f887ac 941 }
e8f887ac 942 }
08247066 943 mutex_unlock(&tc->t_lock);
e8f887ac 944
aedd133d
AL		 945 if (attr->chain || attr->prio)
946 ft = mlx5_chains_get_table(nic_chains,
947 attr->chain, attr->prio,
948 MLX5E_TC_FT_LEVEL);
949 else
950 ft = attr->ft;
951
c7569097
AL		 952 if (IS_ERR(ft)) {
953 rule = ERR_CAST(ft);
954 goto err_ft_get;
955 }
956
c620b772 957 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 958 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 959
c7569097 960 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 961 &flow_act, dest, dest_ix);
962 if (IS_ERR(rule))
c7569097 963 goto err_rule;
08247066
AL		 964
965 return rule;
c7569097
AL		 966
967err_rule:
aedd133d
AL		 968 if (attr->chain || attr->prio)
969 mlx5_chains_put_table(nic_chains,
970 attr->chain, attr->prio,
971 MLX5E_TC_FT_LEVEL);
c7569097
AL		 972err_ft_get:
973 if (attr->dest_chain)
974 mlx5_chains_put_table(nic_chains,
975 attr->dest_chain, 1,
976 MLX5E_TC_FT_LEVEL);
977
978 return ERR_CAST(rule);
08247066
AL		 979}
980
981static int
982mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
983 struct mlx5e_tc_flow_parse_attr *parse_attr,
984 struct mlx5e_tc_flow *flow,
985 struct netlink_ext_ack *extack)
986{
c620b772 987 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 988 struct mlx5_core_dev *dev = priv->mdev;
989 struct mlx5_fc *counter = NULL;
990 int err;
991
992 if (flow_flag_test(flow, HAIRPIN)) {
993 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
994 if (err)
995 return err;
996 }
997
998 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
999 counter = mlx5_fc_create(dev, true);
1000 if (IS_ERR(counter))
1001 return PTR_ERR(counter);
1002
1003 attr->counter = counter;
1004 }
1005
1006 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1007 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1008 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1009 if (err)
1010 return err;
1011 }
1012
aedd133d
AL		 1013 if (flow_flag_test(flow, CT))
1014 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1015 attr, &parse_attr->mod_hdr_acts);
1016 else
1017 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1018 attr);
aad7e08d 1019
a2b7189b 1020 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1021}
1022
08247066 1023void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1024 struct mlx5_flow_handle *rule,
1025 struct mlx5_flow_attr *attr)
08247066 1026{
c7569097
AL		 1027 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1028
08247066 1029 mlx5_del_flow_rules(rule);
c7569097 1030
aedd133d
AL		 1031 if (attr->chain || attr->prio)
1032 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1033 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1034
1035 if (attr->dest_chain)
1036 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1037 MLX5E_TC_FT_LEVEL);
08247066
AL		 1038}
1039
d85cdccb
OG		 1040static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1041 struct mlx5e_tc_flow *flow)
1042{
c620b772 1043 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1044 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1045
c7569097
AL		 1046 flow_flag_clear(flow, OFFLOADED);
1047
aedd133d
AL		 1048 if (flow_flag_test(flow, CT))
1049 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1050 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1051 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1052
c7569097
AL		 1053 /* Remove root table if no rules are left to avoid
1054 * extra steering hops.
1055 */
b6fac0b4 1056 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1057 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1058 !IS_ERR_OR_NULL(tc->t)) {
1059 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1060 priv->fs.tc.t = NULL;
1061 }
b6fac0b4 1062 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1063
aedd133d
AL		 1064 kvfree(attr->parse_attr);
1065
513f8f7f 1066 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1067 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1068
aedd133d
AL		 1069 mlx5_fc_destroy(priv->mdev, attr->counter);
1070
226f2ca3 1071 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1072 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1073
1074 kfree(flow->attr);
d85cdccb
OG		 1075}
1076
0d9f9647 1077struct mlx5_flow_handle *
6d2a3ed0
OG		 1078mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1079 struct mlx5e_tc_flow *flow,
1080 struct mlx5_flow_spec *spec,
c620b772 1081 struct mlx5_flow_attr *attr)
6d2a3ed0 1082{
1ef3018f 1083 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1084 struct mlx5_flow_handle *rule;
4c3844d9 1085
89e39467
PB		 1086 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1087 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1088
1ef3018f
PB		 1089 if (flow_flag_test(flow, CT)) {
1090 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1091
69e2916e 1092 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1093 flow, spec, attr,
1ef3018f 1094 mod_hdr_acts);
69e2916e
PB		 1095 } else {
1096 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1097 }
6d2a3ed0 1098
6d2a3ed0
OG		 1099 if (IS_ERR(rule))
1100 return rule;
1101
c620b772 1102 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1103 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1104 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1105 if (flow_flag_test(flow, CT))
1106 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1107 else
1108 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1109 return flow->rule[1];
1110 }
1111 }
1112
6d2a3ed0
OG		 1113 return rule;
1114}
1115
0d9f9647
VB		 1116void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1117 struct mlx5e_tc_flow *flow,
1118 struct mlx5_flow_attr *attr)
6d2a3ed0 1119{
226f2ca3 1120 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1121
89e39467
PB		 1122 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1123 goto offload_rule_0;
1124
4c3844d9 1125 if (flow_flag_test(flow, CT)) {
aedd133d 1126 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1127 return;
1128 }
1129
c620b772 1130 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1131 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1132
89e39467 1133offload_rule_0:
6d2a3ed0
OG		 1134 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1135}
1136
0d9f9647 1137struct mlx5_flow_handle *
5dbe906f
PB		 1138mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1139 struct mlx5e_tc_flow *flow,
178f69b4 1140 struct mlx5_flow_spec *spec)
5dbe906f 1141{
c620b772 1142 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1143 struct mlx5_flow_handle *rule;
1144
c620b772
AL		 1145 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1146 if (!slow_attr)
1147 return ERR_PTR(-ENOMEM);
5dbe906f 1148
c620b772
AL		 1149 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1150 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1151 slow_attr->esw_attr->split_count = 0;
1152 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1153
1154 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1155 if (!IS_ERR(rule))
226f2ca3 1156 flow_flag_set(flow, SLOW);
5dbe906f 1157
c620b772
AL		 1158 kfree(slow_attr);
1159
5dbe906f
PB		 1160 return rule;
1161}
1162
0d9f9647
VB		 1163void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1164 struct mlx5e_tc_flow *flow)
5dbe906f 1165{
c620b772 1166 struct mlx5_flow_attr *slow_attr;
178f69b4 1167
c620b772 1168 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1169 if (!slow_attr) {
1170 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1171 return;
1172 }
c620b772
AL		 1173
1174 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1175 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1176 slow_attr->esw_attr->split_count = 0;
1177 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1178 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1179 flow_flag_clear(flow, SLOW);
c620b772 1180 kfree(slow_attr);
5dbe906f
PB		 1181}
1182
ad86755b
VB		 1183/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1184 * function.
1185 */
1186static void unready_flow_add(struct mlx5e_tc_flow *flow,
1187 struct list_head *unready_flows)
1188{
1189 flow_flag_set(flow, NOT_READY);
1190 list_add_tail(&flow->unready, unready_flows);
1191}
1192
1193/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1194 * function.
1195 */
1196static void unready_flow_del(struct mlx5e_tc_flow *flow)
1197{
1198 list_del(&flow->unready);
1199 flow_flag_clear(flow, NOT_READY);
1200}
1201
b4a23329
RD		 1202static void add_unready_flow(struct mlx5e_tc_flow *flow)
1203{
1204 struct mlx5_rep_uplink_priv *uplink_priv;
1205 struct mlx5e_rep_priv *rpriv;
1206 struct mlx5_eswitch *esw;
1207
1208 esw = flow->priv->mdev->priv.eswitch;
1209 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1210 uplink_priv = &rpriv->uplink_priv;
1211
ad86755b
VB		 1212 mutex_lock(&uplink_priv->unready_flows_lock);
1213 unready_flow_add(flow, &uplink_priv->unready_flows);
1214 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1215}
1216
1217static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1218{
ad86755b
VB		 1219 struct mlx5_rep_uplink_priv *uplink_priv;
1220 struct mlx5e_rep_priv *rpriv;
1221 struct mlx5_eswitch *esw;
1222
1223 esw = flow->priv->mdev->priv.eswitch;
1224 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1225 uplink_priv = &rpriv->uplink_priv;
1226
1227 mutex_lock(&uplink_priv->unready_flows_lock);
1228 unready_flow_del(flow);
1229 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1230}
1231
10742efc
VB		 1232static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1233
a508728a 1234bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1235{
1236 struct mlx5_core_dev *out_mdev, *route_mdev;
1237 struct mlx5e_priv *out_priv, *route_priv;
1238
1239 out_priv = netdev_priv(out_dev);
1240 out_mdev = out_priv->mdev;
1241 route_priv = netdev_priv(route_dev);
1242 route_mdev = route_priv->mdev;
1243
1244 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1245 route_mdev->coredev_type != MLX5_COREDEV_VF)
1246 return false;
1247
1248 return same_hw_devs(out_priv, route_priv);
1249}
1250
a508728a 1251int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1252{
1253 struct mlx5e_priv *out_priv, *route_priv;
1254 struct mlx5_core_dev *route_mdev;
1255 struct mlx5_eswitch *esw;
1256 u16 vhca_id;
1257 int err;
1258
1259 out_priv = netdev_priv(out_dev);
1260 esw = out_priv->mdev->priv.eswitch;
1261 route_priv = netdev_priv(route_dev);
1262 route_mdev = route_priv->mdev;
1263
1264 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1265 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1266 return err;
1267}
1268
c7b9038d
VB		 1269int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1270 struct mlx5e_tc_flow_parse_attr *parse_attr,
1271 struct mlx5e_tc_flow *flow)
1272{
1273 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1274 struct mlx5_modify_hdr *mod_hdr;
1275
1276 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1277 get_flow_name_space(flow),
1278 mod_hdr_acts->num_actions,
1279 mod_hdr_acts->actions);
1280 if (IS_ERR(mod_hdr))
1281 return PTR_ERR(mod_hdr);
1282
1283 WARN_ON(flow->attr->modify_hdr);
1284 flow->attr->modify_hdr = mod_hdr;
1285
1286 return 0;
1287}
1288
c83954ab 1289static int
74491de9 1290mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1291 struct mlx5e_tc_flow *flow,
1292 struct netlink_ext_ack *extack)
adb4c123
OG		 1293{
1294 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1295 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1296 struct mlx5e_tc_flow_parse_attr *parse_attr;
1297 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1298 bool vf_tun = false, encap_valid = true;
c620b772 1299 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1300 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1301 struct mlx5e_rep_priv *rpriv;
1302 struct mlx5e_priv *out_priv;
39ac237c 1303 u32 max_prio, max_chain;
0ad060ee 1304 int err = 0;
f493f155 1305 int out_index;
8b32580d 1306
84179981
PB		 1307 /* We check chain range only for tc flows.
1308 * For ft flows, we checked attr->chain was originally 0 and set it to
1309 * FDB_FT_CHAIN which is outside tc range.
1310 * See mlx5e_rep_setup_ft_cb().
1311 */
ae430332 1312 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1313 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1314 NL_SET_ERR_MSG_MOD(extack,
1315 "Requested chain is out of supported range");
8914add2
VB		 1316 err = -EOPNOTSUPP;
1317 goto err_out;
bf07aa73
PB		 1318 }
1319
ae430332 1320 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1321 if (attr->prio > max_prio) {
61644c3d
RD		 1322 NL_SET_ERR_MSG_MOD(extack,
1323 "Requested priority is out of supported range");
8914add2
VB		 1324 err = -EOPNOTSUPP;
1325 goto err_out;
bf07aa73 1326 }
e52c2802 1327
777bb800
VB		 1328 if (flow_flag_test(flow, TUN_RX)) {
1329 err = mlx5e_attach_decap_route(priv, flow);
1330 if (err)
8914add2 1331 goto err_out;
777bb800
VB		 1332 }
1333
14e6b038
EC		 1334 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1335 err = mlx5e_attach_decap(priv, flow, extack);
1336 if (err)
8914add2 1337 goto err_out;
14e6b038
EC		 1338 }
1339
c620b772
AL		 1340 parse_attr = attr->parse_attr;
1341 esw_attr = attr->esw_attr;
1342
f493f155 1343 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1344 int mirred_ifindex;
1345
c620b772 1346 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1347 continue;
1348
7040632d 1349 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1350 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1351 mirred_ifindex);
733d4f36 1352 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1353 extack, &encap_dev, &encap_valid);
1354 if (err)
8914add2 1355 goto err_out;
0ad060ee 1356
8914add2
VB		 1357 if (esw_attr->dests[out_index].flags &
1358 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1359 vf_tun = true;
3c37745e
OG		 1360 out_priv = netdev_priv(encap_dev);
1361 rpriv = out_priv->ppriv;
c620b772
AL		 1362 esw_attr->dests[out_index].rep = rpriv->rep;
1363 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1364 }
1365
8b32580d 1366 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1367 if (err)
8914add2 1368 goto err_out;
adb4c123 1369
d5a3c2b6
RD		 1370 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1371 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1372 if (vf_tun) {
1373 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1374 if (err)
1375 goto err_out;
1376 } else {
1377 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1378 if (err)
1379 goto err_out;
1380 }
d7e75a32
OG		 1381 }
1382
b8aee822 1383 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1384 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1385 if (IS_ERR(counter)) {
1386 err = PTR_ERR(counter);
1387 goto err_out;
1388 }
b8aee822
MB		 1389
1390 attr->counter = counter;
1391 }
1392
0ad060ee
RD		 1393 /* we get here if one of the following takes place:
1394 * (1) there's no error
1395 * (2) there's an encap action and we don't have valid neigh
3c37745e 1396 */
bc1d75fa 1397 if (!encap_valid)
178f69b4 1398 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1399 else
6d2a3ed0 1400 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1401
8914add2
VB		 1402 if (IS_ERR(flow->rule[0])) {
1403 err = PTR_ERR(flow->rule[0]);
1404 goto err_out;
1405 }
1406 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1407
1408 return 0;
8914add2
VB		 1409
1410err_out:
1411 flow_flag_set(flow, FAILED);
1412 return err;
aa0cbbae 1413}
d85cdccb 1414
9272e3df
YK		 1415static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1416{
c620b772 1417 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1418 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1419 spec->match_value,
1420 misc_parameters_3);
1421 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1422 headers_v,
1423 geneve_tlv_option_0_data);
1424
1425 return !!geneve_tlv_opt_0_data;
1426}
1427
d85cdccb
OG		 1428static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1429 struct mlx5e_tc_flow *flow)
1430{
1431 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1432 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1433 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1434 bool vf_tun = false;
f493f155 1435 int out_index;
d85cdccb 1436
777bb800 1437 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1438 mlx5e_put_flow_tunnel_id(flow);
1439
12a240a4 1440 if (flow_flag_test(flow, NOT_READY))
b4a23329 1441 remove_unready_flow(flow);
ef06c9ee 1442
226f2ca3
VB		 1443 if (mlx5e_is_offloaded_flow(flow)) {
1444 if (flow_flag_test(flow, SLOW))
178f69b4 1445 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1446 else
1447 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1448 }
d85cdccb 1449
9272e3df
YK		 1450 if (mlx5_flow_has_geneve_opt(flow))
1451 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1452
513f8f7f 1453 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1454
777bb800
VB		 1455 if (flow->decap_route)
1456 mlx5e_detach_decap_route(priv, flow);
1457
1458 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1459 if (esw_attr->dests[out_index].flags &
1460 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1461 vf_tun = true;
777bb800 1462 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1463 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1464 kfree(attr->parse_attr->tun_info[out_index]);
1465 }
777bb800 1466 }
d7e75a32 1467
aedd133d 1468 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1469
c7b9038d
VB		 1470 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1471 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1472 if (vf_tun && attr->modify_hdr)
1473 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1474 else
1475 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1476 }
8914add2
VB		 1477 kvfree(attr->parse_attr);
1478 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1479
1480 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1481 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1482
1483 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1484 mlx5e_detach_decap(priv, flow);
c620b772 1485
41c2fd94 1486 kfree(flow->attr->esw_attr->sample);
c620b772 1487 kfree(flow->attr);
d85cdccb
OG		 1488}
1489
0d9f9647 1490struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1491{
c620b772 1492 return flow->attr->counter;
b8aee822
MB		 1493}
1494
6a06c2f7 1495/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1496void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1497{
1498 struct mlx5e_tc_flow *flow, *tmp;
1499
1500 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1501 mlx5e_flow_put(priv, flow);
1502}
1503
04de7dda
RD		 1504static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1505{
1506 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1507
226f2ca3
VB		 1508 if (!flow_flag_test(flow, ESWITCH) ||
1509 !flow_flag_test(flow, DUP))
04de7dda
RD		 1510 return;
1511
1512 mutex_lock(&esw->offloads.peer_mutex);
1513 list_del(&flow->peer);
1514 mutex_unlock(&esw->offloads.peer_mutex);
1515
226f2ca3 1516 flow_flag_clear(flow, DUP);
04de7dda 1517
eb252c3a
RD		 1518 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1519 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1520 kfree(flow->peer_flow);
1521 }
1522
04de7dda
RD		 1523 flow->peer_flow = NULL;
1524}
1525
1526static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1527{
1528 struct mlx5_core_dev *dev = flow->priv->mdev;
1529 struct mlx5_devcom *devcom = dev->priv.devcom;
1530 struct mlx5_eswitch *peer_esw;
1531
1532 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1533 if (!peer_esw)
1534 return;
1535
1536 __mlx5e_tc_del_fdb_peer_flow(flow);
1537 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1538}
1539
e8f887ac 1540static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1541 struct mlx5e_tc_flow *flow)
e8f887ac 1542{
226f2ca3 1543 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1544 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1545 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1546 } else {
d85cdccb 1547 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1548 }
e8f887ac
AV		 1549}
1550
0a7fcb78
PB		 1551static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1552{
1553 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1554 struct flow_action *flow_action = &rule->action;
1555 const struct flow_action_entry *act;
1556 int i;
1557
1558 flow_action_for_each(i, act, flow_action) {
1559 switch (act->id) {
1560 case FLOW_ACTION_GOTO:
1561 return true;
1562 default:
1563 continue;
1564 }
1565 }
1566
1567 return false;
1568}
bbd00f7e 1569
0a7fcb78
PB		 1570static int
1571enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1572 struct flow_dissector_key_enc_opts *opts,
1573 struct netlink_ext_ack *extack,
1574 bool *dont_care)
1575{
1576 struct geneve_opt *opt;
1577 int off = 0;
1578
1579 *dont_care = true;
1580
1581 while (opts->len > off) {
1582 opt = (struct geneve_opt *)&opts->data[off];
1583
1584 if (!(*dont_care) || opt->opt_class || opt->type ||
1585 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1586 *dont_care = false;
1587
c51323ee 1588 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1589 opt->type != U8_MAX) {
0a7fcb78
PB		 1590 NL_SET_ERR_MSG(extack,
1591 "Partial match of tunnel options in chain > 0 isn't supported");
1592 netdev_warn(priv->netdev,
1593 "Partial match of tunnel options in chain > 0 isn't supported");
1594 return -EOPNOTSUPP;
1595 }
1596 }
1597
1598 off += sizeof(struct geneve_opt) + opt->length * 4;
1599 }
1600
1601 return 0;
1602}
1603
1604#define COPY_DISSECTOR(rule, diss_key, dst)\
1605({ \
1606 struct flow_rule *__rule = (rule);\
1607 typeof(dst) __dst = dst;\
1608\
1609 memcpy(__dst,\
1610 skb_flow_dissector_target(__rule->match.dissector,\
1611 diss_key,\
1612 __rule->match.key),\
1613 sizeof(*__dst));\
1614})
1615
1616static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1617 struct mlx5e_tc_flow *flow,
1618 struct flow_cls_offload *f,
1619 struct net_device *filter_dev)
bbd00f7e 1620{
f9e30088 1621 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1622 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1623 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1624 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1625 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1626 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1627 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1628 struct mlx5e_rep_priv *uplink_rpriv;
1629 struct tunnel_match_key tunnel_key;
1630 bool enc_opts_is_dont_care = true;
1631 u32 tun_id, enc_opts_id = 0;
1632 struct mlx5_eswitch *esw;
1633 u32 value, mask;
8f256622 1634 int err;
2e72eb43 1635
0a7fcb78
PB		 1636 esw = priv->mdev->priv.eswitch;
1637 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1638 uplink_priv = &uplink_rpriv->uplink_priv;
1639
1640 memset(&tunnel_key, 0, sizeof(tunnel_key));
1641 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1642 &tunnel_key.enc_control);
1643 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1644 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1645 &tunnel_key.enc_ipv4);
1646 else
1647 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1648 &tunnel_key.enc_ipv6);
1649 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1650 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1651 &tunnel_key.enc_tp);
1652 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1653 &tunnel_key.enc_key_id);
1654 tunnel_key.filter_ifindex = filter_dev->ifindex;
1655
1656 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1657 if (err)
101f4de9 1658 return err;
bbd00f7e 1659
0a7fcb78
PB		 1660 flow_rule_match_enc_opts(rule, &enc_opts_match);
1661 err = enc_opts_is_dont_care_or_full_match(priv,
1662 enc_opts_match.mask,
1663 extack,
1664 &enc_opts_is_dont_care);
1665 if (err)
1666 goto err_enc_opts;
fe1587a7 1667
0a7fcb78 1668 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1669 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1670 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1671 sizeof(*enc_opts_match.key));
1672 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1673 sizeof(*enc_opts_match.mask));
1674
0a7fcb78 1675 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1676 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1677 if (err)
1678 goto err_enc_opts;
1679 }
fe1587a7 1680
0a7fcb78
PB		 1681 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1682 mask = enc_opts_id ? TUNNEL_ID_MASK :
1683 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1684
0a7fcb78
PB		 1685 if (attr->chain) {
1686 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1687 TUNNEL_TO_REG, value, mask);
1688 } else {
1689 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1690 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1691 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1692 TUNNEL_TO_REG, value);
1693 if (err)
1694 goto err_set;
fe1587a7 1695
0a7fcb78 1696 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1697 }
bbd00f7e 1698
0a7fcb78
PB		 1699 flow->tunnel_id = value;
1700 return 0;
bcef735c 1701
0a7fcb78
PB		 1702err_set:
1703 if (enc_opts_id)
1704 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1705 enc_opts_id);
1706err_enc_opts:
1707 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1708 return err;
1709}
bcef735c 1710
0a7fcb78
PB		 1711static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1712{
1713 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1714 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1715 struct mlx5_rep_uplink_priv *uplink_priv;
1716 struct mlx5e_rep_priv *uplink_rpriv;
1717 struct mlx5_eswitch *esw;
bcef735c 1718
0a7fcb78
PB		 1719 esw = flow->priv->mdev->priv.eswitch;
1720 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1721 uplink_priv = &uplink_rpriv->uplink_priv;
1722
1723 if (tun_id)
1724 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1725 if (enc_opts_id)
1726 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1727 enc_opts_id);
1728}
e98bedf5 1729
4c3844d9
PB		 1730u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1731{
1732 return flow->tunnel_id;
1733}
1734
fca53304
EB		 1735void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1736 struct flow_match_basic *match, bool outer,
1737 void *headers_c, void *headers_v)
1738{
1739 bool ip_version_cap;
1740
1741 ip_version_cap = outer ?
1742 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1743 ft_field_support.outer_ip_version) :
1744 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1745 ft_field_support.inner_ip_version);
1746
1747 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1748 (match->key->n_proto == htons(ETH_P_IP) ||
1749 match->key->n_proto == htons(ETH_P_IPV6))) {
1750 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1751 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1752 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1753 } else {
1754 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1755 ntohs(match->mask->n_proto));
1756 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1757 ntohs(match->key->n_proto));
1758 }
4a5d5d73
EB		 1759}
1760
0d9f9647 1761u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1762{
1763 void *headers_v;
1764 u16 ethertype;
1765 u8 ip_version;
1766
1767 if (outer)
1768 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1769 else
1770 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1771
1772 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1773 /* Return ip_version converted from ethertype anyway */
1774 if (!ip_version) {
1775 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1776 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1777 ip_version = 4;
1778 else if (ethertype == ETH_P_IPV6)
1779 ip_version = 6;
1780 }
1781 return ip_version;
1782}
1783
bbd00f7e 1784static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1785 struct mlx5e_tc_flow *flow,
bbd00f7e 1786 struct mlx5_flow_spec *spec,
f9e30088 1787 struct flow_cls_offload *f,
0a7fcb78
PB		 1788 struct net_device *filter_dev,
1789 u8 *match_level,
1790 bool *match_inner)
bbd00f7e 1791{
a508728a 1792 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1793 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1794 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1795 bool needs_mapping, sets_mapping;
8f256622 1796 int err;
2e72eb43 1797
0a7fcb78
PB		 1798 if (!mlx5e_is_eswitch_flow(flow))
1799 return -EOPNOTSUPP;
1800
c620b772
AL		 1801 needs_mapping = !!flow->attr->chain;
1802 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 1803 *match_inner = !needs_mapping;
1804
1805 if ((needs_mapping || sets_mapping) &&
636bb968 1806 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1807 NL_SET_ERR_MSG(extack,
636bb968 1808 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1809 netdev_warn(priv->netdev,
636bb968 1810 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1811 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1812 }
1813
c620b772 1814 if (!flow->attr->chain) {
0a7fcb78
PB		 1815 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1816 match_level);
1817 if (err) {
e98bedf5 1818 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1819 "Failed to parse tunnel attributes");
1820 netdev_warn(priv->netdev,
1821 "Failed to parse tunnel attributes");
1822 return err;
e98bedf5
EB		 1823 }
1824
14e6b038
EC		 1825 /* With mpls over udp we decapsulate using packet reformat
1826 * object
1827 */
1828 if (!netif_is_bareudp(filter_dev))
c620b772 1829 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1830 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1831 if (err)
1832 return err;
1833 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1834 struct mlx5_flow_spec *tmp_spec;
1835
1836 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1837 if (!tmp_spec) {
1838 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1839 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1840 return -ENOMEM;
1841 }
1842 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1843
1844 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1845 if (err) {
1846 kvfree(tmp_spec);
1847 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1848 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1849 return err;
1850 }
1851 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1852 kvfree(tmp_spec);
1853 if (err)
1854 return err;
bcef735c
OG		 1855 }
1856
0a7fcb78
PB		 1857 if (!needs_mapping && !sets_mapping)
1858 return 0;
bbd00f7e 1859
0a7fcb78 1860 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1861}
bbd00f7e 1862
0a7fcb78 1863static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1864{
0a7fcb78
PB		 1865 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1866 inner_headers);
bbd00f7e
HHZ		 1867}
1868
0a7fcb78 1869static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1870{
0a7fcb78
PB		 1871 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1872 inner_headers);
1873}
1874
1875static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1876{
1877 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1878 outer_headers);
1879}
1880
1881static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1882{
1883 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1884 outer_headers);
8377629e
EB		 1885}
1886
1887static void *get_match_headers_value(u32 flags,
1888 struct mlx5_flow_spec *spec)
1889{
1890 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1891 get_match_inner_headers_value(spec) :
1892 get_match_outer_headers_value(spec);
1893}
1894
1895static void *get_match_headers_criteria(u32 flags,
1896 struct mlx5_flow_spec *spec)
1897{
1898 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1899 get_match_inner_headers_criteria(spec) :
1900 get_match_outer_headers_criteria(spec);
8377629e
EB		 1901}
1902
6d65bc64 1903static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1904 struct flow_cls_offload *f)
1905{
1906 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1907 struct netlink_ext_ack *extack = f->common.extack;
1908 struct net_device *ingress_dev;
1909 struct flow_match_meta match;
1910
1911 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1912 return 0;
1913
1914 flow_rule_match_meta(rule, &match);
1915 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1916 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 1917 return -EOPNOTSUPP;
6d65bc64 1918 }
1919
1920 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1921 match.key->ingress_ifindex);
1922 if (!ingress_dev) {
1923 NL_SET_ERR_MSG_MOD(extack,
1924 "Can't find the ingress port to match on");
a683012a 1925 return -ENOENT;
6d65bc64 1926 }
1927
1928 if (ingress_dev != filter_dev) {
1929 NL_SET_ERR_MSG_MOD(extack,
1930 "Can't match on the ingress filter port");
a683012a 1931 return -EOPNOTSUPP;
6d65bc64 1932 }
1933
1934 return 0;
1935}
1936
72046a91
EC		 1937static bool skip_key_basic(struct net_device *filter_dev,
1938 struct flow_cls_offload *f)
1939{
1940 /* When doing mpls over udp decap, the user needs to provide
1941 * MPLS_UC as the protocol in order to be able to match on mpls
1942 * label fields. However, the actual ethertype is IP so we want to
1943 * avoid matching on this, otherwise we'll fail the match.
1944 */
1945 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
1946 return true;
1947
1948 return false;
1949}
1950
de0af0bf 1951static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 1952 struct mlx5e_tc_flow *flow,
de0af0bf 1953 struct mlx5_flow_spec *spec,
f9e30088 1954 struct flow_cls_offload *f,
54c177ca 1955 struct net_device *filter_dev,
93b3586e 1956 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 1957{
e98bedf5 1958 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1959 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1960 outer_headers);
1961 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1962 outer_headers);
699e96dd
JL		 1963 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1964 misc_parameters);
1965 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1966 misc_parameters);
a3222a2d
MD		 1967 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1968 misc_parameters_3);
1969 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1970 misc_parameters_3);
f9e30088 1971 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1972 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1973 u16 addr_type = 0;
1974 u8 ip_proto = 0;
93b3586e 1975 u8 *match_level;
6d65bc64 1976 int err;
e3a2b7ed 1977
93b3586e 1978 match_level = outer_match_level;
de0af0bf 1979
8f256622 1980 if (dissector->used_keys &
3d144578
VB		 1981 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1982 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1983 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1984 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1985 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1986 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1987 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1988 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1989 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1990 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1991 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1992 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1993 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1994 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1995 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1996 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 1997 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 1998 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 1999 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2000 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2001 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2002 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2003 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2004 dissector->used_keys);
e3a2b7ed
AV		 2005 return -EOPNOTSUPP;
2006 }
2007
075973c7 2008 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2009 bool match_inner = false;
bbd00f7e 2010
0a7fcb78
PB		 2011 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2012 outer_match_level, &match_inner);
2013 if (err)
2014 return err;
2015
2016 if (match_inner) {
2017 /* header pointers should point to the inner headers
2018 * if the packet was decapsulated already.
2019 * outer headers are set by parse_tunnel_attr.
2020 */
2021 match_level = inner_match_level;
2022 headers_c = get_match_inner_headers_criteria(spec);
2023 headers_v = get_match_inner_headers_value(spec);
2024 }
bbd00f7e
HHZ		 2025 }
2026
6d65bc64 2027 err = mlx5e_flower_parse_meta(filter_dev, f);
2028 if (err)
2029 return err;
2030
72046a91
EC		 2031 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2032 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2033 struct flow_match_basic match;
2034
2035 flow_rule_match_basic(rule, &match);
fca53304
EB		 2036 mlx5e_tc_set_ethertype(priv->mdev, &match,
2037 match_level == outer_match_level,
2038 headers_c, headers_v);
e3a2b7ed 2039
8f256622 2040 if (match.mask->n_proto)
d708f902 2041 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2042 }
35a605db
EB		 2043 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2044 is_vlan_dev(filter_dev)) {
2045 struct flow_dissector_key_vlan filter_dev_mask;
2046 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2047 struct flow_match_vlan match;
2048
35a605db
EB		 2049 if (is_vlan_dev(filter_dev)) {
2050 match.key = &filter_dev_key;
2051 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2052 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2053 match.key->vlan_priority = 0;
2054 match.mask = &filter_dev_mask;
2055 memset(match.mask, 0xff, sizeof(*match.mask));
2056 match.mask->vlan_priority = 0;
2057 } else {
2058 flow_rule_match_vlan(rule, &match);
2059 }
8f256622
PNA		 2060 if (match.mask->vlan_id ||
2061 match.mask->vlan_priority ||
2062 match.mask->vlan_tpid) {
2063 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2064 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2065 svlan_tag, 1);
2066 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2067 svlan_tag, 1);
2068 } else {
2069 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2070 cvlan_tag, 1);
2071 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2072 cvlan_tag, 1);
2073 }
095b6cfd 2074
8f256622
PNA		 2075 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2076 match.mask->vlan_id);
2077 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2078 match.key->vlan_id);
358d79a4 2079
8f256622
PNA		 2080 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2081 match.mask->vlan_priority);
2082 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2083 match.key->vlan_priority);
54782900 2084
d708f902 2085 *match_level = MLX5_MATCH_L2;
54782900 2086 }
d3a80bb5 2087 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2088 /* cvlan_tag enabled in match criteria and
2089 * disabled in match value means both S & C tags
2090 * don't exist (untagged of both)
2091 */
cee26487 2092 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2093 *match_level = MLX5_MATCH_L2;
54782900
OG		 2094 }
2095
8f256622
PNA		 2096 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2097 struct flow_match_vlan match;
2098
12d5cbf8 2099 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2100 if (match.mask->vlan_id ||
2101 match.mask->vlan_priority ||
2102 match.mask->vlan_tpid) {
2103 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2104 MLX5_SET(fte_match_set_misc, misc_c,
2105 outer_second_svlan_tag, 1);
2106 MLX5_SET(fte_match_set_misc, misc_v,
2107 outer_second_svlan_tag, 1);
2108 } else {
2109 MLX5_SET(fte_match_set_misc, misc_c,
2110 outer_second_cvlan_tag, 1);
2111 MLX5_SET(fte_match_set_misc, misc_v,
2112 outer_second_cvlan_tag, 1);
2113 }
2114
2115 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2116 match.mask->vlan_id);
699e96dd 2117 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2118 match.key->vlan_id);
699e96dd 2119 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2120 match.mask->vlan_priority);
699e96dd 2121 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2122 match.key->vlan_priority);
699e96dd
JL		 2123
2124 *match_level = MLX5_MATCH_L2;
0faddfe6 2125 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2126 }
2127 }
2128
8f256622
PNA		 2129 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2130 struct flow_match_eth_addrs match;
54782900 2131
8f256622 2132 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2133 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2134 dmac_47_16),
8f256622 2135 match.mask->dst);
d3a80bb5
OG		 2136 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2137 dmac_47_16),
8f256622 2138 match.key->dst);
d3a80bb5
OG		 2139
2140 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2141 smac_47_16),
8f256622 2142 match.mask->src);
d3a80bb5
OG		 2143 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2144 smac_47_16),
8f256622 2145 match.key->src);
d3a80bb5 2146
8f256622
PNA		 2147 if (!is_zero_ether_addr(match.mask->src) ||
2148 !is_zero_ether_addr(match.mask->dst))
d708f902 2149 *match_level = MLX5_MATCH_L2;
54782900
OG		 2150 }
2151
8f256622
PNA		 2152 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2153 struct flow_match_control match;
54782900 2154
8f256622
PNA		 2155 flow_rule_match_control(rule, &match);
2156 addr_type = match.key->addr_type;
54782900
OG		 2157
2158 /* the HW doesn't support frag first/later */
8f256622 2159 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2160 return -EOPNOTSUPP;
2161
8f256622 2162 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2163 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2164 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2165 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2166
2167 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2168 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2169 *match_level = MLX5_MATCH_L2;
54782900
OG		 2170 /* *** L2 attributes parsing up to here *** */
2171 else
83621b7d 2172 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2173 }
2174 }
2175
8f256622
PNA		 2176 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2177 struct flow_match_basic match;
2178
2179 flow_rule_match_basic(rule, &match);
2180 ip_proto = match.key->ip_proto;
54782900
OG		 2181
2182 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2183 match.mask->ip_proto);
54782900 2184 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2185 match.key->ip_proto);
54782900 2186
8f256622 2187 if (match.mask->ip_proto)
d708f902 2188 *match_level = MLX5_MATCH_L3;
54782900
OG		 2189 }
2190
e3a2b7ed 2191 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2192 struct flow_match_ipv4_addrs match;
e3a2b7ed 2193
8f256622 2194 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2195 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2196 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2197 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2198 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2199 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2200 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2201 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2202 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2203 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2204 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2205 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2206 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2207
8f256622 2208 if (match.mask->src || match.mask->dst)
d708f902 2209 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2210 }
2211
2212 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2213 struct flow_match_ipv6_addrs match;
e3a2b7ed 2214
8f256622 2215 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2216 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2217 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2218 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2219 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2220 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2221 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2222
2223 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2224 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2225 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2226 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2227 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2228 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2229
8f256622
PNA		 2230 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2231 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2232 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2233 }
2234
8f256622
PNA		 2235 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2236 struct flow_match_ip match;
1f97a526 2237
8f256622
PNA		 2238 flow_rule_match_ip(rule, &match);
2239 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2240 match.mask->tos & 0x3);
2241 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2242 match.key->tos & 0x3);
1f97a526 2243
8f256622
PNA		 2244 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2245 match.mask->tos >> 2);
2246 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2247 match.key->tos >> 2);
1f97a526 2248
8f256622
PNA		 2249 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2250 match.mask->ttl);
2251 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2252 match.key->ttl);
1f97a526 2253
8f256622 2254 if (match.mask->ttl &&
a8ade55f 2255 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2256 ft_field_support.outer_ipv4_ttl)) {
2257 NL_SET_ERR_MSG_MOD(extack,
2258 "Matching on TTL is not supported");
1f97a526 2259 return -EOPNOTSUPP;
e98bedf5 2260 }
a8ade55f 2261
8f256622 2262 if (match.mask->tos || match.mask->ttl)
d708f902 2263 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2264 }
2265
54782900
OG		 2266 /* *** L3 attributes parsing up to here *** */
2267
8f256622
PNA		 2268 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2269 struct flow_match_ports match;
2270
2271 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2272 switch (ip_proto) {
2273 case IPPROTO_TCP:
2274 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2275 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2276 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2277 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2278
2279 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2280 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2281 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2282 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2283 break;
2284
2285 case IPPROTO_UDP:
2286 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2287 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2288 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2289 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2290
2291 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2292 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2293 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2294 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2295 break;
2296 default:
e98bedf5
EB		 2297 NL_SET_ERR_MSG_MOD(extack,
2298 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2299 netdev_err(priv->netdev,
2300 "Only UDP and TCP transport are supported\n");
2301 return -EINVAL;
2302 }
de0af0bf 2303
8f256622 2304 if (match.mask->src || match.mask->dst)
d708f902 2305 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2306 }
2307
8f256622
PNA		 2308 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2309 struct flow_match_tcp match;
e77834ec 2310
8f256622 2311 flow_rule_match_tcp(rule, &match);
e77834ec 2312 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2313 ntohs(match.mask->flags));
e77834ec 2314 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2315 ntohs(match.key->flags));
e77834ec 2316
8f256622 2317 if (match.mask->flags)
d708f902 2318 *match_level = MLX5_MATCH_L4;
e77834ec 2319 }
a3222a2d
MD		 2320 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2321 struct flow_match_icmp match;
e77834ec 2322
a3222a2d
MD		 2323 flow_rule_match_icmp(rule, &match);
2324 switch (ip_proto) {
2325 case IPPROTO_ICMP:
2326 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2327 MLX5_FLEX_PROTO_ICMP))
2328 return -EOPNOTSUPP;
2329 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2330 match.mask->type);
2331 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2332 match.key->type);
2333 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2334 match.mask->code);
2335 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2336 match.key->code);
2337 break;
2338 case IPPROTO_ICMPV6:
2339 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2340 MLX5_FLEX_PROTO_ICMPV6))
2341 return -EOPNOTSUPP;
2342 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2343 match.mask->type);
2344 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2345 match.key->type);
2346 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2347 match.mask->code);
2348 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2349 match.key->code);
2350 break;
2351 default:
2352 NL_SET_ERR_MSG_MOD(extack,
2353 "Code and type matching only with ICMP and ICMPv6");
2354 netdev_err(priv->netdev,
2355 "Code and type matching only with ICMP and ICMPv6\n");
2356 return -EINVAL;
2357 }
2358 if (match.mask->code || match.mask->type) {
2359 *match_level = MLX5_MATCH_L4;
2360 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2361 }
2362 }
7d6c86e3
AH		 2363 /* Currenlty supported only for MPLS over UDP */
2364 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2365 !netif_is_bareudp(filter_dev)) {
2366 NL_SET_ERR_MSG_MOD(extack,
2367 "Matching on MPLS is supported only for MPLS over UDP");
2368 netdev_err(priv->netdev,
2369 "Matching on MPLS is supported only for MPLS over UDP\n");
2370 return -EOPNOTSUPP;
2371 }
2372
e3a2b7ed
AV		 2373 return 0;
2374}
2375
de0af0bf 2376static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2377 struct mlx5e_tc_flow *flow,
de0af0bf 2378 struct mlx5_flow_spec *spec,
f9e30088 2379 struct flow_cls_offload *f,
54c177ca 2380 struct net_device *filter_dev)
de0af0bf 2381{
93b3586e 2382 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2383 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2384 struct mlx5_core_dev *dev = priv->mdev;
2385 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2386 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2387 struct mlx5_eswitch_rep *rep;
226f2ca3 2388 bool is_eswitch_flow;
de0af0bf
RD		 2389 int err;
2390
93b3586e
HN		 2391 inner_match_level = MLX5_MATCH_NONE;
2392 outer_match_level = MLX5_MATCH_NONE;
2393
0a7fcb78
PB		 2394 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2395 &inner_match_level, &outer_match_level);
93b3586e
HN		 2396 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2397 outer_match_level : inner_match_level;
de0af0bf 2398
226f2ca3
VB		 2399 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2400 if (!err && is_eswitch_flow) {
1d447a39 2401 rep = rpriv->rep;
b05af6aa 2402 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2403 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2404 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2405 NL_SET_ERR_MSG_MOD(extack,
2406 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2407 netdev_warn(priv->netdev,
2408 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2409 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2410 return -EOPNOTSUPP;
2411 }
2412 }
2413
c620b772
AL		 2414 flow->attr->inner_match_level = inner_match_level;
2415 flow->attr->outer_match_level = outer_match_level;
2416
38aa51c1 2417
de0af0bf
RD		 2418 return err;
2419}
2420
d79b6df6
OG		 2421struct pedit_headers {
2422 struct ethhdr eth;
0eb69bb9 2423 struct vlan_hdr vlan;
d79b6df6
OG		 2424 struct iphdr ip4;
2425 struct ipv6hdr ip6;
2426 struct tcphdr tcp;
2427 struct udphdr udp;
2428};
2429
c500c86b
PNA		 2430struct pedit_headers_action {
2431 struct pedit_headers vals;
2432 struct pedit_headers masks;
2433 u32 pedits;
2434};
2435
d79b6df6 2436static int pedit_header_offsets[] = {
73867881
PNA		 2437 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2438 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2439 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2440 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2441 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2442};
2443
2444#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2445
2446static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2447 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2448{
2449 u32 *curr_pmask, *curr_pval;
2450
c500c86b
PNA		 2451 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2452 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2453
2454 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2455 goto out_err;
2456
2457 *curr_pmask |= mask;
2458 *curr_pval |= (val & mask);
2459
2460 return 0;
2461
2462out_err:
2463 return -EOPNOTSUPP;
2464}
2465
2466struct mlx5_fields {
2467 u8 field;
88f30bbc
DL		 2468 u8 field_bsize;
2469 u32 field_mask;
d79b6df6 2470 u32 offset;
27c11b6b 2471 u32 match_offset;
d79b6df6
OG		 2472};
2473
88f30bbc
DL		 2474#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2475 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2476 offsetof(struct pedit_headers, field) + (off), \
2477 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2478
2ef86872
EB		 2479/* masked values are the same and there are no rewrites that do not have a
2480 * match.
2481 */
2482#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2483 type matchmaskx = *(type *)(matchmaskp); \
2484 type matchvalx = *(type *)(matchvalp); \
2485 type maskx = *(type *)(maskp); \
2486 type valx = *(type *)(valp); \
2487 \
2488 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2489 matchmaskx)); \
2490})
2491
27c11b6b 2492static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2493 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2494{
2495 bool same = false;
2496
88f30bbc
DL		 2497 switch (bsize) {
2498 case 8:
2ef86872 2499 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2500 break;
88f30bbc 2501 case 16:
2ef86872 2502 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2503 break;
88f30bbc 2504 case 32:
2ef86872 2505 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2506 break;
2507 }
2508
2509 return same;
2510}
a8e4f0c4 2511
d79b6df6 2512static struct mlx5_fields fields[] = {
88f30bbc
DL		 2513 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2514 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2515 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2516 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2517 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2518 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2519
ab9341b5 2520 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2521 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2522 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2523 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2524
2525 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2526 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2527 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2528 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2529 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2530 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2531 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2532 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2533 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2534 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2535 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2536 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2537 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2538 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2539 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2540 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2541 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2542 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2543
88f30bbc
DL		 2544 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2545 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2546 /* in linux iphdr tcp_flags is 8 bits long */
2547 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2548
88f30bbc
DL		 2549 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2550 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2551};
2552
82198d8b
MD		 2553static unsigned long mask_to_le(unsigned long mask, int size)
2554{
2555 __be32 mask_be32;
2556 __be16 mask_be16;
2557
2558 if (size == 32) {
2559 mask_be32 = (__force __be32)(mask);
2560 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2561 } else if (size == 16) {
2562 mask_be32 = (__force __be32)(mask);
2563 mask_be16 = *(__be16 *)&mask_be32;
2564 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2565 }
2566
2567 return mask;
2568}
6ae4a6a5
PB		 2569static int offload_pedit_fields(struct mlx5e_priv *priv,
2570 int namespace,
2571 struct pedit_headers_action *hdrs,
e98bedf5 2572 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2573 u32 *action_flags,
e98bedf5 2574 struct netlink_ext_ack *extack)
d79b6df6
OG		 2575{
2576 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2577 int i, action_size, first, last, next_z;
88f30bbc
DL		 2578 void *headers_c, *headers_v, *action, *vals_p;
2579 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2580 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2581 struct mlx5_fields *f;
82198d8b 2582 unsigned long mask, field_mask;
6ae4a6a5 2583 int err;
88f30bbc
DL		 2584 u8 cmd;
2585
6ae4a6a5 2586 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2587 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2588 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2589
73867881
PNA		 2590 set_masks = &hdrs[0].masks;
2591 add_masks = &hdrs[1].masks;
2592 set_vals = &hdrs[0].vals;
2593 add_vals = &hdrs[1].vals;
d79b6df6 2594
d65dbedf 2595 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2596
2597 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2598 bool skip;
2599
d79b6df6
OG		 2600 f = &fields[i];
2601 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2602 s_mask = 0;
2603 a_mask = 0;
d79b6df6
OG		 2604
2605 s_masks_p = (void *)set_masks + f->offset;
2606 a_masks_p = (void *)add_masks + f->offset;
2607
88f30bbc
DL		 2608 s_mask = *s_masks_p & f->field_mask;
2609 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2610
2611 if (!s_mask && !a_mask) /* nothing to offload here */
2612 continue;
2613
2614 if (s_mask && a_mask) {
e98bedf5
EB		 2615 NL_SET_ERR_MSG_MOD(extack,
2616 "can't set and add to the same HW field");
d79b6df6
OG		 2617 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2618 return -EOPNOTSUPP;
2619 }
2620
27c11b6b 2621 skip = false;
d79b6df6 2622 if (s_mask) {
27c11b6b
EB		 2623 void *match_mask = headers_c + f->match_offset;
2624 void *match_val = headers_v + f->match_offset;
2625
d79b6df6
OG		 2626 cmd = MLX5_ACTION_TYPE_SET;
2627 mask = s_mask;
2628 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2629 /* don't rewrite if we have a match on the same value */
2630 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2631 match_mask, f->field_bsize))
27c11b6b 2632 skip = true;
d79b6df6 2633 /* clear to denote we consumed this field */
88f30bbc 2634 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2635 } else {
2636 cmd = MLX5_ACTION_TYPE_ADD;
2637 mask = a_mask;
2638 vals_p = (void *)add_vals + f->offset;
27c11b6b 2639 /* add 0 is no change */
88f30bbc 2640 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2641 skip = true;
d79b6df6 2642 /* clear to denote we consumed this field */
88f30bbc 2643 *a_masks_p &= ~f->field_mask;
d79b6df6 2644 }
27c11b6b
EB		 2645 if (skip)
2646 continue;
d79b6df6 2647
82198d8b 2648 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2649
88f30bbc
DL		 2650 first = find_first_bit(&mask, f->field_bsize);
2651 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2652 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2653 if (first < next_z && next_z < last) {
e98bedf5
EB		 2654 NL_SET_ERR_MSG_MOD(extack,
2655 "rewrite of few sub-fields isn't supported");
2b64beba 2656 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2657 mask);
2658 return -EOPNOTSUPP;
2659 }
2660
6ae4a6a5
PB		 2661 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2662 if (err) {
2663 NL_SET_ERR_MSG_MOD(extack,
2664 "too many pedit actions, can't offload");
2665 mlx5_core_warn(priv->mdev,
2666 "mlx5: parsed %d pedit actions, can't do more\n",
2667 mod_acts->num_actions);
2668 return err;
2669 }
2670
2671 action = mod_acts->actions +
2672 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2673 MLX5_SET(set_action_in, action, action_type, cmd);
2674 MLX5_SET(set_action_in, action, field, f->field);
2675
2676 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2677 int start;
2678
82198d8b
MD		 2679 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2680
88f30bbc 2681 /* if field is bit sized it can start not from first bit */
82198d8b 2682 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2683
2684 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2685 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2686 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2687 }
2688
88f30bbc 2689 if (f->field_bsize == 32)
2b64beba 2690 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2691 else if (f->field_bsize == 16)
2b64beba 2692 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2693 else if (f->field_bsize == 8)
2b64beba 2694 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2695
6ae4a6a5 2696 ++mod_acts->num_actions;
d79b6df6
OG		 2697 }
2698
d79b6df6
OG		 2699 return 0;
2700}
2701
2cc1cb1d
TZ		 2702static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2703 int namespace)
2704{
2705 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2706 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2707 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2708 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2709}
2710
6ae4a6a5
PB		 2711int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2712 int namespace,
2713 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2714{
6ae4a6a5
PB		 2715 int action_size, new_num_actions, max_hw_actions;
2716 size_t new_sz, old_sz;
2717 void *ret;
d79b6df6 2718
6ae4a6a5
PB		 2719 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2720 return 0;
d79b6df6 2721
d65dbedf 2722 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2723
6ae4a6a5
PB		 2724 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2725 namespace);
2726 new_num_actions = min(max_hw_actions,
2727 mod_hdr_acts->actions ?
2728 mod_hdr_acts->max_actions * 2 : 1);
2729 if (mod_hdr_acts->max_actions == new_num_actions)
2730 return -ENOSPC;
2731
2732 new_sz = action_size * new_num_actions;
2733 old_sz = mod_hdr_acts->max_actions * action_size;
2734 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2735 if (!ret)
d79b6df6
OG		 2736 return -ENOMEM;
2737
6ae4a6a5
PB		 2738 memset(ret + old_sz, 0, new_sz - old_sz);
2739 mod_hdr_acts->actions = ret;
2740 mod_hdr_acts->max_actions = new_num_actions;
2741
d79b6df6
OG		 2742 return 0;
2743}
2744
6ae4a6a5
PB		 2745void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2746{
2747 kfree(mod_hdr_acts->actions);
2748 mod_hdr_acts->actions = NULL;
2749 mod_hdr_acts->num_actions = 0;
2750 mod_hdr_acts->max_actions = 0;
2751}
2752
d79b6df6
OG		 2753static const struct pedit_headers zero_masks = {};
2754
582234b4
EC		 2755static int
2756parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2757 const struct flow_action_entry *act, int namespace,
2758 struct mlx5e_tc_flow_parse_attr *parse_attr,
2759 struct pedit_headers_action *hdrs,
2760 struct netlink_ext_ack *extack)
d79b6df6 2761{
73867881
PNA		 2762 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2763 int err = -EOPNOTSUPP;
d79b6df6 2764 u32 mask, val, offset;
73867881 2765 u8 htype;
d79b6df6 2766
73867881
PNA		 2767 htype = act->mangle.htype;
2768 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2769
73867881
PNA		 2770 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2771 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2772 goto out_err;
2773 }
d79b6df6 2774
2cc1cb1d
TZ		 2775 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2776 NL_SET_ERR_MSG_MOD(extack,
2777 "The pedit offload action is not supported");
2778 goto out_err;
2779 }
2780
73867881
PNA		 2781 mask = act->mangle.mask;
2782 val = act->mangle.val;
2783 offset = act->mangle.offset;
d79b6df6 2784
73867881
PNA		 2785 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2786 if (err)
2787 goto out_err;
c500c86b 2788
73867881 2789 hdrs[cmd].pedits++;
d79b6df6 2790
c500c86b
PNA		 2791 return 0;
2792out_err:
2793 return err;
2794}
2795
582234b4
EC		 2796static int
2797parse_pedit_to_reformat(struct mlx5e_priv *priv,
2798 const struct flow_action_entry *act,
2799 struct mlx5e_tc_flow_parse_attr *parse_attr,
2800 struct netlink_ext_ack *extack)
2801{
2802 u32 mask, val, offset;
2803 u32 *p;
2804
2805 if (act->id != FLOW_ACTION_MANGLE)
2806 return -EOPNOTSUPP;
2807
2808 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2809 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2810 return -EOPNOTSUPP;
2811 }
2812
2813 mask = ~act->mangle.mask;
2814 val = act->mangle.val;
2815 offset = act->mangle.offset;
2816 p = (u32 *)&parse_attr->eth;
2817 *(p + (offset >> 2)) |= (val & mask);
2818
2819 return 0;
2820}
2821
2822static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2823 const struct flow_action_entry *act, int namespace,
2824 struct mlx5e_tc_flow_parse_attr *parse_attr,
2825 struct pedit_headers_action *hdrs,
2826 struct mlx5e_tc_flow *flow,
2827 struct netlink_ext_ack *extack)
2828{
2829 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2830 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2831
2832 return parse_pedit_to_modify_hdr(priv, act, namespace,
2833 parse_attr, hdrs, extack);
2834}
2835
c500c86b
PNA		 2836static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2837 struct mlx5e_tc_flow_parse_attr *parse_attr,
2838 struct pedit_headers_action *hdrs,
27c11b6b 2839 u32 *action_flags,
c500c86b
PNA		 2840 struct netlink_ext_ack *extack)
2841{
2842 struct pedit_headers *cmd_masks;
2843 int err;
2844 u8 cmd;
2845
6ae4a6a5
PB		 2846 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2847 action_flags, extack);
d79b6df6
OG		 2848 if (err < 0)
2849 goto out_dealloc_parsed_actions;
2850
2851 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2852 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2853 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2854 NL_SET_ERR_MSG_MOD(extack,
2855 "attempt to offload an unsupported field");
b3a433de 2856 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2857 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2858 16, 1, cmd_masks, sizeof(zero_masks), true);
2859 err = -EOPNOTSUPP;
2860 goto out_dealloc_parsed_actions;
2861 }
2862 }
2863
2864 return 0;
2865
2866out_dealloc_parsed_actions:
6ae4a6a5 2867 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2868 return err;
2869}
2870
e98bedf5
EB		 2871static bool csum_offload_supported(struct mlx5e_priv *priv,
2872 u32 action,
2873 u32 update_flags,
2874 struct netlink_ext_ack *extack)
26c02749
OG		 2875{
2876 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2877 TCA_CSUM_UPDATE_FLAG_UDP;
2878
2879 /* The HW recalcs checksums only if re-writing headers */
2880 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2881 NL_SET_ERR_MSG_MOD(extack,
2882 "TC csum action is only offloaded with pedit");
26c02749
OG		 2883 netdev_warn(priv->netdev,
2884 "TC csum action is only offloaded with pedit\n");
2885 return false;
2886 }
2887
2888 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2889 NL_SET_ERR_MSG_MOD(extack,
2890 "can't offload TC csum action for some header/s");
26c02749
OG		 2891 netdev_warn(priv->netdev,
2892 "can't offload TC csum action for some header/s - flags %#x\n",
2893 update_flags);
2894 return false;
2895 }
2896
2897 return true;
2898}
2899
8998576b
DL		 2900struct ip_ttl_word {
2901 __u8 ttl;
2902 __u8 protocol;
2903 __sum16 check;
2904};
2905
2906struct ipv6_hoplimit_word {
2907 __be16 payload_len;
2908 __u8 nexthdr;
2909 __u8 hop_limit;
2910};
2911
4c3844d9
PB		 2912static int is_action_keys_supported(const struct flow_action_entry *act,
2913 bool ct_flow, bool *modify_ip_header,
7e36feeb 2914 bool *modify_tuple,
4c3844d9 2915 struct netlink_ext_ack *extack)
8998576b
DL		 2916{
2917 u32 mask, offset;
2918 u8 htype;
2919
2920 htype = act->mangle.htype;
2921 offset = act->mangle.offset;
2922 mask = ~act->mangle.mask;
2923 /* For IPv4 & IPv6 header check 4 byte word,
2924 * to determine that modified fields
2925 * are NOT ttl & hop_limit only.
2926 */
2927 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2928 struct ip_ttl_word *ttl_word =
2929 (struct ip_ttl_word *)&mask;
2930
2931 if (offset != offsetof(struct iphdr, ttl) ||
2932 ttl_word->protocol ||
2933 ttl_word->check) {
4c3844d9
PB		 2934 *modify_ip_header = true;
2935 }
2936
7e36feeb
PB		 2937 if (offset >= offsetof(struct iphdr, saddr))
2938 *modify_tuple = true;
2939
2940 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 2941 NL_SET_ERR_MSG_MOD(extack,
2942 "can't offload re-write of ipv4 address with action ct");
2943 return -EOPNOTSUPP;
8998576b
DL		 2944 }
2945 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2946 struct ipv6_hoplimit_word *hoplimit_word =
2947 (struct ipv6_hoplimit_word *)&mask;
2948
2949 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2950 hoplimit_word->payload_len ||
2951 hoplimit_word->nexthdr) {
4c3844d9
PB		 2952 *modify_ip_header = true;
2953 }
2954
7e36feeb
PB		 2955 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
2956 *modify_tuple = true;
2957
2958 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 2959 NL_SET_ERR_MSG_MOD(extack,
2960 "can't offload re-write of ipv6 address with action ct");
2961 return -EOPNOTSUPP;
8998576b 2962 }
7e36feeb
PB		 2963 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2964 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
2965 *modify_tuple = true;
2966 if (ct_flow) {
2967 NL_SET_ERR_MSG_MOD(extack,
2968 "can't offload re-write of transport header ports with action ct");
2969 return -EOPNOTSUPP;
2970 }
8998576b 2971 }
4c3844d9
PB		 2972
2973 return 0;
8998576b
DL		 2974}
2975
96b5b458
DC		 2976static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
2977 bool ct_flow, struct netlink_ext_ack *extack,
2978 struct mlx5e_priv *priv,
2979 struct mlx5_flow_spec *spec)
2980{
2981 if (!modify_tuple || ct_clear)
2982 return true;
2983
2984 if (ct_flow) {
2985 NL_SET_ERR_MSG_MOD(extack,
2986 "can't offload tuple modification with non-clear ct()");
2987 netdev_info(priv->netdev,
2988 "can't offload tuple modification with non-clear ct()");
2989 return false;
2990 }
2991
2992 /* Add ct_state=-trk match so it will be offloaded for non ct flows
2993 * (or after clear action), as otherwise, since the tuple is changed,
2994 * we can't restore ct state
2995 */
2996 if (mlx5_tc_ct_add_no_trk_match(spec)) {
2997 NL_SET_ERR_MSG_MOD(extack,
2998 "can't offload tuple modification with ct matches and no ct(clear) action");
2999 netdev_info(priv->netdev,
3000 "can't offload tuple modification with ct matches and no ct(clear) action");
3001 return false;
3002 }
3003
3004 return true;
3005}
3006
3d486ec4
OS		 3007static bool modify_header_match_supported(struct mlx5e_priv *priv,
3008 struct mlx5_flow_spec *spec,
73867881 3009 struct flow_action *flow_action,
4c3844d9 3010 u32 actions, bool ct_flow,
7e36feeb 3011 bool ct_clear,
e98bedf5 3012 struct netlink_ext_ack *extack)
bdd66ac0 3013{
73867881 3014 const struct flow_action_entry *act;
7e36feeb 3015 bool modify_ip_header, modify_tuple;
fca53304 3016 void *headers_c;
bdd66ac0
OG		 3017 void *headers_v;
3018 u16 ethertype;
8998576b 3019 u8 ip_proto;
4c3844d9 3020 int i, err;
bdd66ac0 3021
fca53304 3022 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3023 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3024 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3025
3026 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3027 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3028 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3029 goto out_ok;
3030
3031 modify_ip_header = false;
7e36feeb 3032 modify_tuple = false;
73867881
PNA		 3033 flow_action_for_each(i, act, flow_action) {
3034 if (act->id != FLOW_ACTION_MANGLE &&
3035 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3036 continue;
3037
4c3844d9 3038 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3039 &modify_ip_header,
3040 &modify_tuple, extack);
4c3844d9
PB		 3041 if (err)
3042 return err;
bdd66ac0
OG		 3043 }
3044
96b5b458
DC		 3045 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3046 priv, spec))
7e36feeb 3047 return false;
7e36feeb 3048
bdd66ac0 3049 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3050 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3051 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3052 NL_SET_ERR_MSG_MOD(extack,
3053 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3054 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3055 ip_proto);
bdd66ac0
OG		 3056 return false;
3057 }
3058
3059out_ok:
3060 return true;
3061}
3062
3063static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3064 struct flow_action *flow_action,
bdd66ac0 3065 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3066 struct mlx5e_tc_flow *flow,
3067 struct netlink_ext_ack *extack)
bdd66ac0 3068{
a7c119bd 3069 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3070 u32 actions;
3071
c620b772
AL		 3072 ct_clear = flow->attr->ct_attr.ct_action &
3073 TCA_CT_ACT_CLEAR;
3074 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3075 actions = flow->attr->action;
3076
4c3844d9 3077 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3078 if (flow->attr->esw_attr->split_count && ct_flow &&
3079 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3080 /* All registers used by ct are cleared when using
3081 * split rules.
3082 */
3083 NL_SET_ERR_MSG_MOD(extack,
3084 "Can't offload mirroring with action ct");
49397b80 3085 return false;
4c3844d9 3086 }
4c3844d9 3087 }
bdd66ac0
OG		 3088
3089 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3090 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3091 flow_action, actions,
7e36feeb
PB		 3092 ct_flow, ct_clear,
3093 extack);
bdd66ac0
OG		 3094
3095 return true;
3096}
3097
32134847
MD		 3098static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3099{
3100 return priv->mdev == peer_priv->mdev;
3101}
3102
5c65c564
OG		 3103static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3104{
3105 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3106 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3107
3108 fmdev = priv->mdev;
3109 pmdev = peer_priv->mdev;
3110
59c9d35e
AH		 3111 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3112 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3113
816f6706 3114 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3115}
3116
bb569657
AL		 3117static bool same_vf_reps(struct mlx5e_priv *priv,
3118 struct net_device *out_dev)
3119{
3120 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3121 priv->netdev == out_dev;
3122}
3123
bdc837ee
EB		 3124static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3125 const struct flow_action_entry *act,
3126 struct mlx5e_tc_flow_parse_attr *parse_attr,
3127 struct pedit_headers_action *hdrs,
3128 u32 *action, struct netlink_ext_ack *extack)
3129{
3130 u16 mask16 = VLAN_VID_MASK;
3131 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3132 const struct flow_action_entry pedit_act = {
3133 .id = FLOW_ACTION_MANGLE,
3134 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3135 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3136 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3137 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3138 };
6fca9d1e 3139 u8 match_prio_mask, match_prio_val;
bf2f3bca 3140 void *headers_c, *headers_v;
bdc837ee
EB		 3141 int err;
3142
bf2f3bca
EB		 3143 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3144 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3145
3146 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3147 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3148 NL_SET_ERR_MSG_MOD(extack,
3149 "VLAN rewrite action must have VLAN protocol match");
3150 return -EOPNOTSUPP;
3151 }
3152
6fca9d1e
EB		 3153 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3154 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3155 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3156 NL_SET_ERR_MSG_MOD(extack,
3157 "Changing VLAN prio is not supported");
bdc837ee
EB		 3158 return -EOPNOTSUPP;
3159 }
3160
582234b4 3161 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3162 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3163
3164 return err;
3165}
3166
0bac1194
EB		 3167static int
3168add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3169 struct mlx5e_tc_flow_parse_attr *parse_attr,
3170 struct pedit_headers_action *hdrs,
3171 u32 *action, struct netlink_ext_ack *extack)
3172{
3173 const struct flow_action_entry prio_tag_act = {
3174 .vlan.vid = 0,
3175 .vlan.prio =
3176 MLX5_GET(fte_match_set_lyr_2_4,
3177 get_match_headers_value(*action,
3178 &parse_attr->spec),
3179 first_prio) &
3180 MLX5_GET(fte_match_set_lyr_2_4,
3181 get_match_headers_criteria(*action,
3182 &parse_attr->spec),
3183 first_prio),
3184 };
3185
3186 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3187 &prio_tag_act, parse_attr, hdrs, action,
3188 extack);
3189}
3190
c7569097
AL		 3191static int validate_goto_chain(struct mlx5e_priv *priv,
3192 struct mlx5e_tc_flow *flow,
3193 const struct flow_action_entry *act,
3194 u32 actions,
3195 struct netlink_ext_ack *extack)
3196{
3197 bool is_esw = mlx5e_is_eswitch_flow(flow);
3198 struct mlx5_flow_attr *attr = flow->attr;
3199 bool ft_flow = mlx5e_is_ft_flow(flow);
3200 u32 dest_chain = act->chain_index;
3201 struct mlx5_fs_chains *chains;
3202 struct mlx5_eswitch *esw;
3203 u32 reformat_and_fwd;
3204 u32 max_chain;
3205
3206 esw = priv->mdev->priv.eswitch;
3207 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3208 max_chain = mlx5_chains_get_chain_range(chains);
3209 reformat_and_fwd = is_esw ?
3210 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3211 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3212
3213 if (ft_flow) {
3214 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3215 return -EOPNOTSUPP;
3216 }
3217
3218 if (!mlx5_chains_backwards_supported(chains) &&
3219 dest_chain <= attr->chain) {
3220 NL_SET_ERR_MSG_MOD(extack,
3221 "Goto lower numbered chain isn't supported");
3222 return -EOPNOTSUPP;
3223 }
3224
3225 if (dest_chain > max_chain) {
3226 NL_SET_ERR_MSG_MOD(extack,
3227 "Requested destination chain is out of supported range");
3228 return -EOPNOTSUPP;
3229 }
3230
3231 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3232 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3233 !reformat_and_fwd) {
3234 NL_SET_ERR_MSG_MOD(extack,
3235 "Goto chain is not allowed if action has reformat or decap");
3236 return -EOPNOTSUPP;
3237 }
3238
3239 return 0;
3240}
3241
73867881
PNA		 3242static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3243 struct flow_action *flow_action,
aa0cbbae 3244 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3245 struct mlx5e_tc_flow *flow,
3246 struct netlink_ext_ack *extack)
e3a2b7ed 3247{
c620b772 3248 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3249 struct pedit_headers_action hdrs[2] = {};
3250 const struct flow_action_entry *act;
c620b772 3251 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3252 u32 action = 0;
244cd96a 3253 int err, i;
e3a2b7ed 3254
73867881 3255 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3256 return -EINVAL;
3257
53eca1f3
JK		 3258 if (!flow_action_hw_stats_check(flow_action, extack,
3259 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3260 return -EOPNOTSUPP;
3261
c620b772
AL		 3262 nic_attr = attr->nic_attr;
3263
3264 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3265
73867881
PNA		 3266 flow_action_for_each(i, act, flow_action) {
3267 switch (act->id) {
15fc92ec
TZ		 3268 case FLOW_ACTION_ACCEPT:
3269 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3270 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3271 break;
73867881 3272 case FLOW_ACTION_DROP:
1cab1cd7 3273 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3274 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3275 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3276 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3277 break;
3278 case FLOW_ACTION_MANGLE:
3279 case FLOW_ACTION_ADD:
3280 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3281 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3282 if (err)
3283 return err;
3284
c7569097 3285 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3286 break;
bdc837ee
EB		 3287 case FLOW_ACTION_VLAN_MANGLE:
3288 err = add_vlan_rewrite_action(priv,
3289 MLX5_FLOW_NAMESPACE_KERNEL,
3290 act, parse_attr, hdrs,
3291 &action, extack);
3292 if (err)
3293 return err;
3294
3295 break;
73867881 3296 case FLOW_ACTION_CSUM:
1cab1cd7 3297 if (csum_offload_supported(priv, action,
73867881 3298 act->csum_flags,
e98bedf5 3299 extack))
73867881 3300 break;
26c02749
OG		 3301
3302 return -EOPNOTSUPP;
73867881
PNA		 3303 case FLOW_ACTION_REDIRECT: {
3304 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3305
3306 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3307 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3308 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3309 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3310 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3311 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3312 } else {
e98bedf5
EB		 3313 NL_SET_ERR_MSG_MOD(extack,
3314 "device is not on same HW, can't offload");
5c65c564
OG		 3315 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3316 peer_dev->name);
3317 return -EINVAL;
3318 }
73867881
PNA		 3319 }
3320 break;
3321 case FLOW_ACTION_MARK: {
3322 u32 mark = act->mark;
e3a2b7ed
AV		 3323
3324 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3325 NL_SET_ERR_MSG_MOD(extack,
3326 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3327 return -EINVAL;
3328 }
3329
c620b772 3330 nic_attr->flow_tag = mark;
1cab1cd7 3331 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3332 }
3333 break;
c7569097
AL		 3334 case FLOW_ACTION_GOTO:
3335 err = validate_goto_chain(priv, flow, act, action,
3336 extack);
3337 if (err)
3338 return err;
3339
3340 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3341 attr->dest_chain = act->chain_index;
3342 break;
aedd133d
AL		 3343 case FLOW_ACTION_CT:
3344 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3345 if (err)
3346 return err;
3347
3348 flow_flag_set(flow, CT);
3349 break;
73867881 3350 default:
2cc1cb1d
TZ		 3351 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3352 return -EOPNOTSUPP;
e3a2b7ed 3353 }
e3a2b7ed
AV		 3354 }
3355
c500c86b
PNA		 3356 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3357 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3358 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3359 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3360 if (err)
3361 return err;
27c11b6b
EB		 3362 /* in case all pedit actions are skipped, remove the MOD_HDR
3363 * flag.
3364 */
6ae4a6a5 3365 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3366 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3367 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3368 }
c500c86b
PNA		 3369 }
3370
1cab1cd7 3371 attr->action = action;
c7569097
AL		 3372
3373 if (attr->dest_chain) {
3374 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3375 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3376 return -EOPNOTSUPP;
3377 }
3378 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3379 }
3380
3381 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3382 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3383
73867881 3384 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3385 return -EOPNOTSUPP;
3386
e3a2b7ed
AV		 3387 return 0;
3388}
3389
32134847 3390static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3391 struct net_device *peer_netdev)
3392{
3393 struct mlx5e_priv *peer_priv;
3394
3395 peer_priv = netdev_priv(peer_netdev);
3396
3397 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3398 mlx5e_eswitch_vf_rep(priv->netdev) &&
3399 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3400 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3401}
3402
1482bd3d 3403static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3404 const struct flow_action_entry *act,
1482bd3d
JL		 3405 struct mlx5_esw_flow_attr *attr,
3406 u32 *action)
3407{
cc495188
JL		 3408 u8 vlan_idx = attr->total_vlan;
3409
3410 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3411 return -EOPNOTSUPP;
3412
73867881
PNA		 3413 switch (act->id) {
3414 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3415 if (vlan_idx) {
3416 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3417 MLX5_FS_VLAN_DEPTH))
3418 return -EOPNOTSUPP;
3419
3420 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3421 } else {
3422 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3423 }
73867881
PNA		 3424 break;
3425 case FLOW_ACTION_VLAN_PUSH:
3426 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3427 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3428 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3429 if (!attr->vlan_proto[vlan_idx])
3430 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3431
3432 if (vlan_idx) {
3433 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3434 MLX5_FS_VLAN_DEPTH))
3435 return -EOPNOTSUPP;
3436
3437 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3438 } else {
3439 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3440 (act->vlan.proto != htons(ETH_P_8021Q) ||
3441 act->vlan.prio))
cc495188
JL		 3442 return -EOPNOTSUPP;
3443
3444 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3445 }
73867881
PNA		 3446 break;
3447 default:
bdc837ee 3448 return -EINVAL;
1482bd3d
JL		 3449 }
3450
cc495188
JL		 3451 attr->total_vlan = vlan_idx + 1;
3452
1482bd3d
JL		 3453 return 0;
3454}
3455
d34eb2fc
OG		 3456static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3457 struct net_device *out_dev)
3458{
3459 struct net_device *fdb_out_dev = out_dev;
3460 struct net_device *uplink_upper;
3461
3462 rcu_read_lock();
3463 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3464 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3465 uplink_upper == out_dev) {
3466 fdb_out_dev = uplink_dev;
3467 } else if (netif_is_lag_master(out_dev)) {
3468 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3469 if (fdb_out_dev &&
3470 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3471 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3472 fdb_out_dev = NULL;
3473 }
3474 rcu_read_unlock();
3475 return fdb_out_dev;
3476}
3477
278748a9 3478static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3479 struct mlx5_flow_attr *attr,
278748a9
EB		 3480 struct net_device **out_dev,
3481 u32 *action)
3482{
3483 struct net_device *vlan_dev = *out_dev;
3484 struct flow_action_entry vlan_act = {
3485 .id = FLOW_ACTION_VLAN_PUSH,
3486 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3487 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3488 .vlan.prio = 0,
3489 };
3490 int err;
3491
c620b772 3492 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3493 if (err)
3494 return err;
3495
3496 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3497 dev_get_iflink(vlan_dev));
3498 if (is_vlan_dev(*out_dev))
3499 err = add_vlan_push_action(priv, attr, out_dev, action);
3500
3501 return err;
3502}
3503
35a605db 3504static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3505 struct mlx5_flow_attr *attr,
35a605db
EB		 3506 u32 *action)
3507{
35a605db
EB		 3508 struct flow_action_entry vlan_act = {
3509 .id = FLOW_ACTION_VLAN_POP,
3510 };
70f478ca 3511 int nest_level, err = 0;
35a605db 3512
70f478ca
DL		 3513 nest_level = attr->parse_attr->filter_dev->lower_level -
3514 priv->netdev->lower_level;
35a605db 3515 while (nest_level--) {
c620b772 3516 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3517 if (err)
3518 return err;
3519 }
3520
3521 return err;
3522}
3523
32134847
MD		 3524static bool same_hw_reps(struct mlx5e_priv *priv,
3525 struct net_device *peer_netdev)
3526{
3527 struct mlx5e_priv *peer_priv;
3528
3529 peer_priv = netdev_priv(peer_netdev);
3530
3531 return mlx5e_eswitch_rep(priv->netdev) &&
3532 mlx5e_eswitch_rep(peer_netdev) &&
3533 same_hw_devs(priv, peer_priv);
3534}
3535
3536static bool is_lag_dev(struct mlx5e_priv *priv,
3537 struct net_device *peer_netdev)
3538{
3539 return ((mlx5_lag_is_sriov(priv->mdev) ||
3540 mlx5_lag_is_multipath(priv->mdev)) &&
3541 same_hw_reps(priv, peer_netdev));
3542}
3543
f6dc1264
PB		 3544bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3545 struct net_device *out_dev)
3546{
32134847
MD		 3547 if (is_merged_eswitch_vfs(priv, out_dev))
3548 return true;
3549
3550 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3551 return true;
3552
3553 return mlx5e_eswitch_rep(out_dev) &&
32134847 3554 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3555}
3556
554fe75c
DL		 3557static bool is_duplicated_output_device(struct net_device *dev,
3558 struct net_device *out_dev,
3559 int *ifindexes, int if_count,
3560 struct netlink_ext_ack *extack)
3561{
3562 int i;
3563
3564 for (i = 0; i < if_count; i++) {
3565 if (ifindexes[i] == out_dev->ifindex) {
3566 NL_SET_ERR_MSG_MOD(extack,
3567 "can't duplicate output to same device");
3568 netdev_err(dev, "can't duplicate output to same device: %s\n",
3569 out_dev->name);
3570 return true;
3571 }
3572 }
3573
3574 return false;
3575}
3576
613f53fe
EC		 3577static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3578 struct mlx5e_tc_flow *flow,
3579 struct net_device *out_dev,
3580 struct netlink_ext_ack *extack)
3581{
c620b772 3582 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3583 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3584 struct mlx5e_rep_priv *rep_priv;
3585
3586 /* Forwarding non encapsulated traffic between
3587 * uplink ports is allowed only if
3588 * termination_table_raw_traffic cap is set.
3589 *
c620b772 3590 * Input vport was stored attr->in_rep.
613f53fe
EC		 3591 * In LAG case, *priv* is the private data of
3592 * uplink which may be not the input vport.
3593 */
3594 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3595
3596 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3597 mlx5e_eswitch_uplink_rep(out_dev)))
3598 return 0;
3599
3600 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3601 termination_table_raw_traffic)) {
3602 NL_SET_ERR_MSG_MOD(extack,
3603 "devices are both uplink, can't offload forwarding");
3604 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3605 priv->netdev->name, out_dev->name);
3606 return -EOPNOTSUPP;
3607 } else if (out_dev != rep_priv->netdev) {
3608 NL_SET_ERR_MSG_MOD(extack,
3609 "devices are not the same uplink, can't offload forwarding");
3610 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3611 priv->netdev->name, out_dev->name);
3612 return -EOPNOTSUPP;
3613 }
3614 return 0;
3615}
3616
73867881
PNA		 3617static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3618 struct flow_action *flow_action,
e98bedf5 3619 struct mlx5e_tc_flow *flow,
14e6b038
EC		 3620 struct netlink_ext_ack *extack,
3621 struct net_device *filter_dev)
03a9d11e 3622{
73867881 3623 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3624 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3625 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3626 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3627 const struct ip_tunnel_info *info = NULL;
c620b772 3628 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3629 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3630 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3631 const struct flow_action_entry *act;
c620b772 3632 struct mlx5_esw_flow_attr *esw_attr;
41c2fd94 3633 struct mlx5_sample_attr sample = {};
0a7fcb78
PB		 3634 bool encap = false, decap = false;
3635 u32 action = attr->action;
554fe75c 3636 int err, i, if_count = 0;
f828ca6a 3637 bool mpls_push = false;
03a9d11e 3638
73867881 3639 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3640 return -EINVAL;
3641
53eca1f3
JK		 3642 if (!flow_action_hw_stats_check(flow_action, extack,
3643 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3644 return -EOPNOTSUPP;
3645
c620b772
AL		 3646 esw_attr = attr->esw_attr;
3647 parse_attr = attr->parse_attr;
3648
73867881
PNA		 3649 flow_action_for_each(i, act, flow_action) {
3650 switch (act->id) {
3651 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3652 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3653 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3654 break;
f0288210
EC		 3655 case FLOW_ACTION_TRAP:
3656 if (!flow_offload_has_one_action(flow_action)) {
3657 NL_SET_ERR_MSG_MOD(extack,
3658 "action trap is supported as a sole action only");
3659 return -EOPNOTSUPP;
3660 }
3661 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3662 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3663 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3664 break;
f828ca6a
EC		 3665 case FLOW_ACTION_MPLS_PUSH:
3666 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3667 reformat_l2_to_l3_tunnel) ||
3668 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3669 NL_SET_ERR_MSG_MOD(extack,
3670 "mpls push is supported only for mpls_uc protocol");
3671 return -EOPNOTSUPP;
3672 }
3673 mpls_push = true;
3674 break;
14e6b038
EC		 3675 case FLOW_ACTION_MPLS_POP:
3676 /* we only support mpls pop if it is the first action
3677 * and the filter net device is bareudp. Subsequent
3678 * actions can be pedit and the last can be mirred
3679 * egress redirect.
3680 */
3681 if (i) {
3682 NL_SET_ERR_MSG_MOD(extack,
3683 "mpls pop supported only as first action");
3684 return -EOPNOTSUPP;
3685 }
3686 if (!netif_is_bareudp(filter_dev)) {
3687 NL_SET_ERR_MSG_MOD(extack,
3688 "mpls pop supported only on bareudp devices");
3689 return -EOPNOTSUPP;
3690 }
3691
3692 parse_attr->eth.h_proto = act->mpls_pop.proto;
3693 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3694 flow_flag_set(flow, L3_TO_L2_DECAP);
3695 break;
73867881
PNA		 3696 case FLOW_ACTION_MANGLE:
3697 case FLOW_ACTION_ADD:
3698 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3699 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3700 if (err)
3701 return err;
3702
582234b4
EC		 3703 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3704 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3705 esw_attr->split_count = esw_attr->out_count;
582234b4 3706 }
73867881
PNA		 3707 break;
3708 case FLOW_ACTION_CSUM:
1cab1cd7 3709 if (csum_offload_supported(priv, action,
73867881
PNA		 3710 act->csum_flags, extack))
3711 break;
26c02749
OG		 3712
3713 return -EOPNOTSUPP;
73867881
PNA		 3714 case FLOW_ACTION_REDIRECT:
3715 case FLOW_ACTION_MIRRED: {
03a9d11e 3716 struct mlx5e_priv *out_priv;
592d3651 3717 struct net_device *out_dev;
03a9d11e 3718
73867881 3719 out_dev = act->dev;
ef381359
OS		 3720 if (!out_dev) {
3721 /* out_dev is NULL when filters with
3722 * non-existing mirred device are replayed to
3723 * the driver.
3724 */
3725 return -EINVAL;
3726 }
03a9d11e 3727
f828ca6a
EC		 3728 if (mpls_push && !netif_is_bareudp(out_dev)) {
3729 NL_SET_ERR_MSG_MOD(extack,
3730 "mpls is supported only through a bareudp device");
3731 return -EOPNOTSUPP;
3732 }
3733
84179981
PB		 3734 if (ft_flow && out_dev == priv->netdev) {
3735 /* Ignore forward to self rules generated
3736 * by adding both mlx5 devs to the flow table
3737 * block on a normal nft offload setup.
3738 */
3739 return -EOPNOTSUPP;
3740 }
3741
c620b772 3742 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3743 NL_SET_ERR_MSG_MOD(extack,
3744 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3745 netdev_warn(priv->netdev,
3746 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3747 esw_attr->out_count);
592d3651
CM		 3748 return -EOPNOTSUPP;
3749 }
3750
f493f155
EB		 3751 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3752 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3753 if (encap) {
c620b772 3754 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3755 out_dev->ifindex;
0d9f9647
VB		 3756 parse_attr->tun_info[esw_attr->out_count] =
3757 mlx5e_dup_tun_info(info);
c620b772 3758 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3759 return -ENOMEM;
3760 encap = false;
c620b772 3761 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3762 MLX5_ESW_DEST_ENCAP;
c620b772 3763 esw_attr->out_count++;
b6a4ac24
VB		 3764 /* attr->dests[].rep is resolved when we
3765 * handle encap
3766 */
3767 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3768 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3769 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3770
554fe75c
DL		 3771 if (is_duplicated_output_device(priv->netdev,
3772 out_dev,
3773 ifindexes,
3774 if_count,
3775 extack))
3776 return -EOPNOTSUPP;
3777
3778 ifindexes[if_count] = out_dev->ifindex;
3779 if_count++;
3780
d34eb2fc
OG		 3781 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3782 if (!out_dev)
3783 return -ENODEV;
7ba58ba7 3784
278748a9
EB		 3785 if (is_vlan_dev(out_dev)) {
3786 err = add_vlan_push_action(priv, attr,
3787 &out_dev,
3788 &action);
3789 if (err)
3790 return err;
3791 }
f6dc1264 3792
35a605db
EB		 3793 if (is_vlan_dev(parse_attr->filter_dev)) {
3794 err = add_vlan_pop_action(priv, attr,
3795 &action);
3796 if (err)
3797 return err;
3798 }
278748a9 3799
613f53fe
EC		 3800 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3801 if (err)
3802 return err;
ffec9702 3803
f6dc1264
PB		 3804 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3805 NL_SET_ERR_MSG_MOD(extack,
3806 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3807 return -EOPNOTSUPP;
f6dc1264 3808 }
a0646c88 3809
bb569657
AL		 3810 if (same_vf_reps(priv, out_dev)) {
3811 NL_SET_ERR_MSG_MOD(extack,
3812 "can't forward from a VF to itself");
3813 return -EOPNOTSUPP;
3814 }
3815
a54e20b4 3816 out_priv = netdev_priv(out_dev);
1d447a39 3817 rpriv = out_priv->ppriv;
c620b772
AL		 3818 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3819 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3820 esw_attr->out_count++;
ef381359
OS		 3821 } else if (parse_attr->filter_dev != priv->netdev) {
3822 /* All mlx5 devices are called to configure
3823 * high level device filters. Therefore, the
3824 * *attempt* to install a filter on invalid
3825 * eswitch should not trigger an explicit error
3826 */
3827 return -EINVAL;
a54e20b4 3828 } else {
e98bedf5
EB		 3829 NL_SET_ERR_MSG_MOD(extack,
3830 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3831 netdev_warn(priv->netdev,
3832 "devices %s %s not on same switch HW, can't offload forwarding\n",
3833 priv->netdev->name,
3834 out_dev->name);
03a9d11e
OG		 3835 return -EINVAL;
3836 }
73867881
PNA		 3837 }
3838 break;
3839 case FLOW_ACTION_TUNNEL_ENCAP:
3840 info = act->tunnel;
a54e20b4
HHZ		 3841 if (info)
3842 encap = true;
3843 else
3844 return -EOPNOTSUPP;
1482bd3d 3845
73867881
PNA		 3846 break;
3847 case FLOW_ACTION_VLAN_PUSH:
3848 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3849 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3850 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3851 /* Replace vlan pop+push with vlan modify */
3852 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3853 err = add_vlan_rewrite_action(priv,
3854 MLX5_FLOW_NAMESPACE_FDB,
3855 act, parse_attr, hdrs,
3856 &action, extack);
3857 } else {
c620b772 3858 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3859 }
1482bd3d
JL		 3860 if (err)
3861 return err;
3862
c620b772 3863 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3864 break;
3865 case FLOW_ACTION_VLAN_MANGLE:
3866 err = add_vlan_rewrite_action(priv,
3867 MLX5_FLOW_NAMESPACE_FDB,
3868 act, parse_attr, hdrs,
3869 &action, extack);
3870 if (err)
3871 return err;
3872
c620b772 3873 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3874 break;
3875 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3876 decap = true;
73867881 3877 break;
2fbbc30d 3878 case FLOW_ACTION_GOTO:
c7569097
AL		 3879 err = validate_goto_chain(priv, flow, act, action,
3880 extack);
2fbbc30d
EC		 3881 if (err)
3882 return err;
bf07aa73 3883
e88afe75 3884 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 3885 attr->dest_chain = act->chain_index;
73867881 3886 break;
4c3844d9 3887 case FLOW_ACTION_CT:
41c2fd94
CM		 3888 if (flow_flag_test(flow, SAMPLE)) {
3889 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
3890 return -EOPNOTSUPP;
3891 }
aedd133d 3892 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 3893 if (err)
3894 return err;
3895
3896 flow_flag_set(flow, CT);
69e2916e 3897 esw_attr->split_count = esw_attr->out_count;
4c3844d9 3898 break;
41c2fd94
CM		 3899 case FLOW_ACTION_SAMPLE:
3900 if (flow_flag_test(flow, CT)) {
3901 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
3902 return -EOPNOTSUPP;
3903 }
3904 sample.rate = act->sample.rate;
3905 sample.group_num = act->sample.psample_group->group_num;
3906 if (act->sample.truncate)
3907 sample.trunc_size = act->sample.trunc_size;
3908 flow_flag_set(flow, SAMPLE);
3909 break;
73867881 3910 default:
2cc1cb1d
TZ		 3911 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3912 return -EOPNOTSUPP;
bf07aa73 3913 }
03a9d11e 3914 }
bdd66ac0 3915
a508728a
VB		 3916 /* always set IP version for indirect table handling */
3917 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3918
0bac1194
EB		 3919 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3920 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3921 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3922 * tag rewrite.
3923 */
3924 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3925 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3926 &action, extack);
3927 if (err)
3928 return err;
3929 }
3930
c500c86b
PNA		 3931 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3932 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3933 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3934 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3935 if (err)
3936 return err;
27c11b6b
EB		 3937 /* in case all pedit actions are skipped, remove the MOD_HDR
3938 * flag. we might have set split_count either by pedit or
3939 * pop/push. if there is no pop/push either, reset it too.
3940 */
6ae4a6a5 3941 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3942 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3943 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 3944 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3945 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 3946 esw_attr->split_count = 0;
27c11b6b 3947 }
c500c86b
PNA		 3948 }
3949
1cab1cd7 3950 attr->action = action;
73867881 3951 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3952 return -EOPNOTSUPP;
3953
e88afe75 3954 if (attr->dest_chain) {
0a7fcb78
PB		 3955 if (decap) {
3956 /* It can be supported if we'll create a mapping for
3957 * the tunnel device only (without tunnel), and set
3958 * this tunnel id with this decap flow.
3959 *
3960 * On restore (miss), we'll just set this saved tunnel
3961 * device.
3962 */
3963
3964 NL_SET_ERR_MSG(extack,
3965 "Decap with goto isn't supported");
3966 netdev_warn(priv->netdev,
3967 "Decap with goto isn't supported");
3968 return -EOPNOTSUPP;
3969 }
3970
e88afe75
OG		 3971 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3972 }
3973
ae2741e2
VB		 3974 if (!(attr->action &
3975 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 3976 NL_SET_ERR_MSG_MOD(extack,
3977 "Rule must have at least one forward/drop action");
ae2741e2
VB		 3978 return -EOPNOTSUPP;
3979 }
3980
c620b772 3981 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3982 NL_SET_ERR_MSG_MOD(extack,
3983 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3984 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3985 return -EOPNOTSUPP;
3986 }
3987
41c2fd94
CM		 3988 /* Allocate sample attribute only when there is a sample action and
3989 * no errors after parsing.
3990 */
3991 if (flow_flag_test(flow, SAMPLE)) {
3992 esw_attr->sample = kzalloc(sizeof(*esw_attr->sample), GFP_KERNEL);
3993 if (!esw_attr->sample)
3994 return -ENOMEM;
3995 *esw_attr->sample = sample;
3996 }
3997
31c8eba5 3998 return 0;
03a9d11e
OG		 3999}
4000
226f2ca3 4001static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4002{
226f2ca3 4003 unsigned long __flow_flags = 0;
60bd4af8 4004
226f2ca3
VB		 4005 if (flags & MLX5_TC_FLAG(INGRESS))
4006 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4007 if (flags & MLX5_TC_FLAG(EGRESS))
4008 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4009
226f2ca3
VB		 4010 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4011 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4012 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4013 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4014 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4015 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4016
60bd4af8
OG		 4017 *flow_flags = __flow_flags;
4018}
4019
05866c82
OG		 4020static const struct rhashtable_params tc_ht_params = {
4021 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4022 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4023 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4024 .automatic_shrinking = true,
4025};
4026
226f2ca3
VB		 4027static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4028 unsigned long flags)
05866c82 4029{
655dc3d2
OG		 4030 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4031 struct mlx5e_rep_priv *uplink_rpriv;
4032
226f2ca3 4033 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4034 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4035 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4036 } else /* NIC offload */
655dc3d2 4037 return &priv->fs.tc.ht;
05866c82
OG		 4038}
4039
04de7dda
RD		 4040static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4041{
c620b772
AL		 4042 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4043 struct mlx5_flow_attr *attr = flow->attr;
4044 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4045 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4046 bool act_is_encap = !!(attr->action &
4047 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4048 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4049 MLX5_DEVCOM_ESW_OFFLOADS);
4050
10fbb1cd
RD		 4051 if (!esw_paired)
4052 return false;
4053
c620b772
AL		 4054 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4055 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4056 (is_rep_ingress || act_is_encap))
4057 return true;
4058
4059 return false;
04de7dda
RD		 4060}
4061
c620b772
AL		 4062struct mlx5_flow_attr *
4063mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4064{
4065 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4066 sizeof(struct mlx5_esw_flow_attr) :
4067 sizeof(struct mlx5_nic_flow_attr);
4068 struct mlx5_flow_attr *attr;
4069
4070 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4071}
4072
a88780a9
RD		 4073static int
4074mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4075 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4076 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4077 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4078{
17091853 4079 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4080 struct mlx5_flow_attr *attr;
3bc4b7bf 4081 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4082 int err = -ENOMEM;
4083 int out_index;
e3a2b7ed 4084
c620b772 4085 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4086 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4087 if (!parse_attr || !flow)
4088 goto err_free;
c620b772
AL		 4089
4090 flow->flags = flow_flags;
4091 flow->cookie = f->cookie;
4092 flow->priv = priv;
4093
4094 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4095 if (!attr)
e3a2b7ed 4096 goto err_free;
ff7ea04a 4097
c620b772 4098 flow->attr = attr;
e3a2b7ed 4099
5a7e5bcb
VB		 4100 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4101 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4102 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4103 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4104 refcount_set(&flow->refcnt, 1);
95435ad7 4105 init_completion(&flow->init_done);
e3a2b7ed 4106
a88780a9
RD		 4107 *__flow = flow;
4108 *__parse_attr = parse_attr;
4109
4110 return 0;
4111
4112err_free:
4113 kfree(flow);
4114 kvfree(parse_attr);
4115 return err;
4116}
4117
c7569097
AL		 4118static void
4119mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4120 struct mlx5e_tc_flow_parse_attr *parse_attr,
4121 struct flow_cls_offload *f)
4122{
4123 attr->parse_attr = parse_attr;
4124 attr->chain = f->common.chain_index;
4125 attr->prio = f->common.prio;
4126}
4127
988ab9c7 4128static void
c620b772 4129mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4130 struct mlx5e_priv *priv,
4131 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4132 struct flow_cls_offload *f,
988ab9c7
TZ		 4133 struct mlx5_eswitch_rep *in_rep,
4134 struct mlx5_core_dev *in_mdev)
4135{
4136 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4137 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4138
c7569097 4139 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4140
4141 esw_attr->in_rep = in_rep;
4142 esw_attr->in_mdev = in_mdev;
4143
4144 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4145 MLX5_COUNTER_SOURCE_ESWITCH)
4146 esw_attr->counter_dev = in_mdev;
4147 else
4148 esw_attr->counter_dev = priv->mdev;
4149}
4150
71129676 4151static struct mlx5e_tc_flow *
04de7dda 4152__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4153 struct flow_cls_offload *f,
226f2ca3 4154 unsigned long flow_flags,
04de7dda
RD		 4155 struct net_device *filter_dev,
4156 struct mlx5_eswitch_rep *in_rep,
71129676 4157 struct mlx5_core_dev *in_mdev)
a88780a9 4158{
f9e30088 4159 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4160 struct netlink_ext_ack *extack = f->common.extack;
4161 struct mlx5e_tc_flow_parse_attr *parse_attr;
4162 struct mlx5e_tc_flow *flow;
4163 int attr_size, err;
e3a2b7ed 4164
226f2ca3 4165 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4166 attr_size = sizeof(struct mlx5_esw_flow_attr);
4167 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4168 &parse_attr, &flow);
4169 if (err)
4170 goto out;
988ab9c7 4171
d11afc26 4172 parse_attr->filter_dev = filter_dev;
c620b772 4173 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4174 priv, parse_attr,
4175 f, in_rep, in_mdev);
4176
54c177ca
OS		 4177 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4178 f, filter_dev);
d11afc26
OS		 4179 if (err)
4180 goto err_free;
a88780a9 4181
7e36feeb 4182 /* actions validation depends on parsing the ct matches first */
aedd133d 4183 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4184 &flow->attr->ct_attr, extack);
a88780a9
RD		 4185 if (err)
4186 goto err_free;
4187
7e36feeb 4188 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4189 if (err)
4190 goto err_free;
4191
7040632d 4192 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4193 complete_all(&flow->init_done);
ef06c9ee
RD		 4194 if (err) {
4195 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4196 goto err_free;
4197
b4a23329 4198 add_unready_flow(flow);
ef06c9ee 4199 }
e3a2b7ed 4200
71129676 4201 return flow;
a88780a9
RD		 4202
4203err_free:
5a7e5bcb 4204 mlx5e_flow_put(priv, flow);
a88780a9 4205out:
71129676 4206 return ERR_PTR(err);
a88780a9
RD		 4207}
4208
f9e30088 4209static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4210 struct mlx5e_tc_flow *flow,
226f2ca3 4211 unsigned long flow_flags)
04de7dda
RD		 4212{
4213 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4214 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4215 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4216 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4217 struct mlx5e_tc_flow_parse_attr *parse_attr;
4218 struct mlx5e_rep_priv *peer_urpriv;
4219 struct mlx5e_tc_flow *peer_flow;
4220 struct mlx5_core_dev *in_mdev;
4221 int err = 0;
4222
4223 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4224 if (!peer_esw)
4225 return -ENODEV;
4226
4227 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4228 peer_priv = netdev_priv(peer_urpriv->netdev);
4229
4230 /* in_mdev is assigned of which the packet originated from.
4231 * So packets redirected to uplink use the same mdev of the
4232 * original flow and packets redirected from uplink use the
4233 * peer mdev.
4234 */
c620b772 4235 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4236 in_mdev = peer_priv->mdev;
4237 else
4238 in_mdev = priv->mdev;
4239
c620b772 4240 parse_attr = flow->attr->parse_attr;
95dc1902 4241 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4242 parse_attr->filter_dev,
c620b772 4243 attr->in_rep, in_mdev);
71129676
JG		 4244 if (IS_ERR(peer_flow)) {
4245 err = PTR_ERR(peer_flow);
04de7dda 4246 goto out;
71129676 4247 }
04de7dda
RD		 4248
4249 flow->peer_flow = peer_flow;
226f2ca3 4250 flow_flag_set(flow, DUP);
04de7dda
RD		 4251 mutex_lock(&esw->offloads.peer_mutex);
4252 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4253 mutex_unlock(&esw->offloads.peer_mutex);
4254
4255out:
4256 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4257 return err;
4258}
4259
4260static int
4261mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4262 struct flow_cls_offload *f,
226f2ca3 4263 unsigned long flow_flags,
04de7dda
RD		 4264 struct net_device *filter_dev,
4265 struct mlx5e_tc_flow **__flow)
4266{
4267 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4268 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4269 struct mlx5_core_dev *in_mdev = priv->mdev;
4270 struct mlx5e_tc_flow *flow;
4271 int err;
4272
71129676
JG		 4273 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4274 in_mdev);
4275 if (IS_ERR(flow))
4276 return PTR_ERR(flow);
04de7dda
RD		 4277
4278 if (is_peer_flow_needed(flow)) {
95dc1902 4279 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4280 if (err) {
4281 mlx5e_tc_del_fdb_flow(priv, flow);
4282 goto out;
4283 }
4284 }
4285
4286 *__flow = flow;
4287
4288 return 0;
4289
4290out:
4291 return err;
4292}
4293
a88780a9
RD		 4294static int
4295mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4296 struct flow_cls_offload *f,
226f2ca3 4297 unsigned long flow_flags,
d11afc26 4298 struct net_device *filter_dev,
a88780a9
RD		 4299 struct mlx5e_tc_flow **__flow)
4300{
f9e30088 4301 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4302 struct netlink_ext_ack *extack = f->common.extack;
4303 struct mlx5e_tc_flow_parse_attr *parse_attr;
4304 struct mlx5e_tc_flow *flow;
4305 int attr_size, err;
4306
c7569097
AL		 4307 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4308 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4309 return -EOPNOTSUPP;
4310 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4311 return -EOPNOTSUPP;
c7569097 4312 }
bf07aa73 4313
226f2ca3 4314 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4315 attr_size = sizeof(struct mlx5_nic_flow_attr);
4316 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4317 &parse_attr, &flow);
4318 if (err)
4319 goto out;
4320
d11afc26 4321 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4322 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4323
54c177ca
OS		 4324 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4325 f, filter_dev);
d11afc26
OS		 4326 if (err)
4327 goto err_free;
4328
aedd133d
AL		 4329 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4330 &flow->attr->ct_attr, extack);
4331 if (err)
4332 goto err_free;
4333
73867881 4334 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4335 if (err)
4336 goto err_free;
4337
4338 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4339 if (err)
4340 goto err_free;
4341
226f2ca3 4342 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4343 *__flow = flow;
4344
4345 return 0;
e3a2b7ed 4346
e3a2b7ed 4347err_free:
8914add2 4348 flow_flag_set(flow, FAILED);
e68e28b4 4349 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4350 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4351out:
4352 return err;
4353}
4354
4355static int
4356mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4357 struct flow_cls_offload *f,
226f2ca3 4358 unsigned long flags,
d11afc26 4359 struct net_device *filter_dev,
a88780a9
RD		 4360 struct mlx5e_tc_flow **flow)
4361{
4362 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4363 unsigned long flow_flags;
a88780a9
RD		 4364 int err;
4365
4366 get_flags(flags, &flow_flags);
4367
bf07aa73
PB		 4368 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4369 return -EOPNOTSUPP;
4370
f6455de0 4371 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4372 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4373 filter_dev, flow);
a88780a9 4374 else
d11afc26
OS		 4375 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4376 filter_dev, flow);
a88780a9
RD		 4377
4378 return err;
4379}
4380
553f9328
VP		 4381static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4382 struct mlx5e_rep_priv *rpriv)
4383{
4384 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4385 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4386 * function is called from NIC mode.
553f9328 4387 */
2fb15e72 4388 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4389}
4390
71d82d2a 4391int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4392 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4393{
4394 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4395 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4396 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4397 struct mlx5e_tc_flow *flow;
4398 int err = 0;
4399
7dc84de9
RD		 4400 if (!mlx5_esw_hold(priv->mdev))
4401 return -EAGAIN;
4402
4403 mlx5_esw_get(priv->mdev);
4404
c5d326b2
VB		 4405 rcu_read_lock();
4406 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4407 if (flow) {
553f9328
VP		 4408 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4409 * just return 0.
4410 */
4411 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4412 goto rcu_unlock;
553f9328 4413
a88780a9
RD		 4414 NL_SET_ERR_MSG_MOD(extack,
4415 "flow cookie already exists, ignoring");
4416 netdev_warn_once(priv->netdev,
4417 "flow cookie %lx already exists, ignoring\n",
4418 f->cookie);
0e1c1a2f 4419 err = -EEXIST;
c1aea9e1 4420 goto rcu_unlock;
a88780a9 4421 }
c1aea9e1
VB		 4422rcu_unlock:
4423 rcu_read_unlock();
4424 if (flow)
4425 goto out;
a88780a9 4426
7a978759 4427 trace_mlx5e_configure_flower(f);
d11afc26 4428 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4429 if (err)
4430 goto out;
4431
553f9328
VP		 4432 /* Flow rule offloaded to non-uplink representor sharing tc block,
4433 * set the flow's owner dev.
4434 */
4435 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4436 flow->orig_dev = dev;
4437
c5d326b2 4438 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4439 if (err)
4440 goto err_free;
4441
7dc84de9 4442 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4443 return 0;
4444
4445err_free:
5a7e5bcb 4446 mlx5e_flow_put(priv, flow);
a88780a9 4447out:
7dc84de9
RD		 4448 mlx5_esw_put(priv->mdev);
4449 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4450 return err;
4451}
4452
8f8ae895
OG		 4453static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4454{
226f2ca3
VB		 4455 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4456 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4457
226f2ca3
VB		 4458 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4459 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4460}
4461
71d82d2a 4462int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4463 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4464{
d9ee0491 4465 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4466 struct mlx5e_tc_flow *flow;
c5d326b2 4467 int err;
e3a2b7ed 4468
c5d326b2 4469 rcu_read_lock();
ab818362 4470 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4471 if (!flow || !same_flow_direction(flow, flags)) {
4472 err = -EINVAL;
4473 goto errout;
4474 }
e3a2b7ed 4475
c5d326b2
VB		 4476 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4477 * set.
4478 */
4479 if (flow_flag_test_and_set(flow, DELETED)) {
4480 err = -EINVAL;
4481 goto errout;
4482 }
05866c82 4483 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4484 rcu_read_unlock();
e3a2b7ed 4485
7a978759 4486 trace_mlx5e_delete_flower(f);
5a7e5bcb 4487 mlx5e_flow_put(priv, flow);
e3a2b7ed 4488
7dc84de9 4489 mlx5_esw_put(priv->mdev);
e3a2b7ed 4490 return 0;
c5d326b2
VB		 4491
4492errout:
4493 rcu_read_unlock();
4494 return err;
e3a2b7ed
AV		 4495}
4496
71d82d2a 4497int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4498 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4499{
04de7dda 4500 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4501 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4502 struct mlx5_eswitch *peer_esw;
aad7e08d 4503 struct mlx5e_tc_flow *flow;
aad7e08d 4504 struct mlx5_fc *counter;
316d5f72
RD		 4505 u64 lastuse = 0;
4506 u64 packets = 0;
4507 u64 bytes = 0;
5a7e5bcb 4508 int err = 0;
aad7e08d 4509
c5d326b2
VB		 4510 rcu_read_lock();
4511 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4512 tc_ht_params));
4513 rcu_read_unlock();
5a7e5bcb
VB		 4514 if (IS_ERR(flow))
4515 return PTR_ERR(flow);
4516
4517 if (!same_flow_direction(flow, flags)) {
4518 err = -EINVAL;
4519 goto errout;
4520 }
aad7e08d 4521
4c3844d9 4522 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4523 counter = mlx5e_tc_get_counter(flow);
4524 if (!counter)
5a7e5bcb 4525 goto errout;
aad7e08d 4526
316d5f72
RD		 4527 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4528 }
aad7e08d 4529
316d5f72
RD		 4530 /* Under multipath it's possible for one rule to be currently
4531 * un-offloaded while the other rule is offloaded.
4532 */
04de7dda
RD		 4533 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4534 if (!peer_esw)
4535 goto out;
4536
226f2ca3
VB		 4537 if (flow_flag_test(flow, DUP) &&
4538 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4539 u64 bytes2;
4540 u64 packets2;
4541 u64 lastuse2;
4542
4543 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4544 if (!counter)
4545 goto no_peer_counter;
04de7dda
RD		 4546 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4547
4548 bytes += bytes2;
4549 packets += packets2;
4550 lastuse = max_t(u64, lastuse, lastuse2);
4551 }
4552
316d5f72 4553no_peer_counter:
04de7dda 4554 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4555out:
4b61d3e8 4556 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4557 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4558 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4559errout:
4560 mlx5e_flow_put(priv, flow);
4561 return err;
aad7e08d
AV		 4562}
4563
1fe3e316 4564static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4565 struct netlink_ext_ack *extack)
4566{
4567 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4568 struct mlx5_eswitch *esw;
1fe3e316 4569 u32 rate_mbps = 0;
fcb64c0f 4570 u16 vport_num;
fcb64c0f
EC		 4571 int err;
4572
e401a184
EC		 4573 vport_num = rpriv->rep->vport;
4574 if (vport_num >= MLX5_VPORT_ECPF) {
4575 NL_SET_ERR_MSG_MOD(extack,
4576 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4577 return -EOPNOTSUPP;
4578 }
4579
fcb64c0f
EC		 4580 esw = priv->mdev->priv.eswitch;
4581 /* rate is given in bytes/sec.
4582 * First convert to bits/sec and then round to the nearest mbit/secs.
4583 * mbit means million bits.
4584 * Moreover, if rate is non zero we choose to configure to a minimum of
4585 * 1 mbit/sec.
4586 */
1fe3e316
PP		 4587 if (rate) {
4588 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4589 do_div(rate, 1000000);
4590 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4591 }
4592
fcb64c0f
EC		 4593 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4594 if (err)
4595 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4596
4597 return err;
4598}
4599
4600static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4601 struct flow_action *flow_action,
4602 struct netlink_ext_ack *extack)
4603{
4604 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4605 const struct flow_action_entry *act;
4606 int err;
4607 int i;
4608
4609 if (!flow_action_has_entries(flow_action)) {
4610 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4611 return -EINVAL;
4612 }
4613
4614 if (!flow_offload_has_one_action(flow_action)) {
4615 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4616 return -EOPNOTSUPP;
4617 }
4618
53eca1f3 4619 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4620 return -EOPNOTSUPP;
4621
fcb64c0f
EC		 4622 flow_action_for_each(i, act, flow_action) {
4623 switch (act->id) {
4624 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4625 if (act->police.rate_pkt_ps) {
4626 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4627 return -EOPNOTSUPP;
4628 }
fcb64c0f
EC		 4629 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4630 if (err)
4631 return err;
4632
4633 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4634 break;
4635 default:
4636 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4637 return -EOPNOTSUPP;
4638 }
4639 }
4640
4641 return 0;
4642}
4643
4644int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4645 struct tc_cls_matchall_offload *ma)
4646{
b5f814cc 4647 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4648 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4649
b5f814cc
EC		 4650 if (!mlx5_esw_qos_enabled(esw)) {
4651 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4652 return -EOPNOTSUPP;
4653 }
4654
7b83355f 4655 if (ma->common.prio != 1) {
fcb64c0f
EC		 4656 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4657 return -EINVAL;
4658 }
4659
4660 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4661}
4662
4663int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4664 struct tc_cls_matchall_offload *ma)
4665{
4666 struct netlink_ext_ack *extack = ma->common.extack;
4667
4668 return apply_police_params(priv, 0, extack);
4669}
4670
4671void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4672 struct tc_cls_matchall_offload *ma)
4673{
4674 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4675 struct rtnl_link_stats64 cur_stats;
4676 u64 dbytes;
4677 u64 dpkts;
4678
4679 cur_stats = priv->stats.vf_vport;
4680 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4681 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4682 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4683 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4684 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4685}
4686
4d8fcf21
AH		 4687static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4688 struct mlx5e_priv *peer_priv)
4689{
4690 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4691 struct mlx5e_hairpin_entry *hpe, *tmp;
4692 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4693 u16 peer_vhca_id;
4694 int bkt;
4695
4696 if (!same_hw_devs(priv, peer_priv))
4697 return;
4698
4699 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4700
b32accda 4701 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4702 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4703 if (refcount_inc_not_zero(&hpe->refcnt))
4704 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4705 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4706
4707 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4708 wait_for_completion(&hpe->res_ready);
4709 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4710 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4711
4712 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4713 }
4714}
4715
4716static int mlx5e_tc_netdev_event(struct notifier_block *this,
4717 unsigned long event, void *ptr)
4718{
4719 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4720 struct mlx5e_flow_steering *fs;
4721 struct mlx5e_priv *peer_priv;
4722 struct mlx5e_tc_table *tc;
4723 struct mlx5e_priv *priv;
4724
4725 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4726 event != NETDEV_UNREGISTER ||
4727 ndev->reg_state == NETREG_REGISTERED)
4728 return NOTIFY_DONE;
4729
4730 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4731 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4732 priv = container_of(fs, struct mlx5e_priv, fs);
4733 peer_priv = netdev_priv(ndev);
4734 if (priv == peer_priv ||
4735 !(priv->netdev->features & NETIF_F_HW_TC))
4736 return NOTIFY_DONE;
4737
4738 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4739
4740 return NOTIFY_DONE;
4741}
4742
6a064674
AL		 4743static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4744{
4745 int tc_grp_size, tc_tbl_size;
4746 u32 max_flow_counter;
4747
4748 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4749 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4750
4751 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4752
4753 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4754 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4755
4756 return tc_tbl_size;
4757}
4758
655dc3d2 4759int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4760{
acff797c 4761 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4762 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4763 struct mapping_ctx *chains_mapping;
6a064674 4764 struct mlx5_chains_attr attr = {};
4d8fcf21 4765 int err;
e8f887ac 4766
b2fdf3d0 4767 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4768 mutex_init(&tc->t_lock);
b32accda 4769 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4770 hash_init(tc->hairpin_tbl);
11c9c548 4771
4d8fcf21
AH		 4772 err = rhashtable_init(&tc->ht, &tc_ht_params);
4773 if (err)
4774 return err;
4775
9ba33339
RD		 4776 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4777
c9355682
CM		 4778 chains_mapping = mapping_create(sizeof(struct mlx5_mapped_obj),
4779 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4780 if (IS_ERR(chains_mapping)) {
4781 err = PTR_ERR(chains_mapping);
4782 goto err_mapping;
4783 }
4784 tc->mapping = chains_mapping;
4785
4786 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4787 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4788 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4789 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4790 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4791 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4792 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4793 attr.mapping = chains_mapping;
6a064674
AL		 4794
4795 tc->chains = mlx5_chains_create(dev, &attr);
4796 if (IS_ERR(tc->chains)) {
4797 err = PTR_ERR(tc->chains);
4798 goto err_chains;
4799 }
4800
aedd133d
AL		 4801 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
4802 MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4803
4d8fcf21 4804 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4805 err = register_netdevice_notifier_dev_net(priv->netdev,
4806 &tc->netdevice_nb,
4807 &tc->netdevice_nn);
4808 if (err) {
4d8fcf21
AH		 4809 tc->netdevice_nb.notifier_call = NULL;
4810 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4811 goto err_reg;
4d8fcf21
AH		 4812 }
4813
6a064674
AL		 4814 return 0;
4815
4816err_reg:
aedd133d 4817 mlx5_tc_ct_clean(tc->ct);
6a064674
AL		 4818 mlx5_chains_destroy(tc->chains);
4819err_chains:
c9355682
CM		 4820 mapping_destroy(chains_mapping);
4821err_mapping:
6a064674 4822 rhashtable_destroy(&tc->ht);
4d8fcf21 4823 return err;
e8f887ac
AV		 4824}
4825
4826static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4827{
4828 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4829 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4830
961e8979 4831 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4832 kfree(flow);
4833}
4834
655dc3d2 4835void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4836{
acff797c 4837 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4838
4d8fcf21 4839 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4840 unregister_netdevice_notifier_dev_net(priv->netdev,
4841 &tc->netdevice_nb,
4842 &tc->netdevice_nn);
4d8fcf21 4843
b2fdf3d0 4844 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4845 mutex_destroy(&tc->hairpin_tbl_lock);
4846
6a064674 4847 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4848
acff797c 4849 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4850 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4851 tc->t = NULL;
e8f887ac 4852 }
b6fac0b4 4853 mutex_destroy(&tc->t_lock);
6a064674 4854
aedd133d 4855 mlx5_tc_ct_clean(tc->ct);
c9355682 4856 mapping_destroy(tc->mapping);
6a064674 4857 mlx5_chains_destroy(tc->chains);
e8f887ac 4858}
655dc3d2
OG		 4859
4860int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4861{
d7a42ad0 4862 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4863 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4864 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4865 struct mapping_ctx *mapping;
aedd133d
AL		 4866 struct mlx5_eswitch *esw;
4867 struct mlx5e_priv *priv;
4868 int err = 0;
0a7fcb78
PB		 4869
4870 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4871 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4872 priv = netdev_priv(rpriv->netdev);
4873 esw = priv->mdev->priv.eswitch;
0a7fcb78 4874
aedd133d
AL		 4875 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4876 esw_chains(esw),
4877 &esw->offloads.mod_hdr,
4878 MLX5_FLOW_NAMESPACE_FDB);
4c3844d9 4879
2a9ab10a
CM		 4880#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4881 uplink_priv->esw_psample = mlx5_esw_sample_init(netdev_priv(priv->netdev));
4882#endif
4883
0a7fcb78
PB		 4884 mapping = mapping_create(sizeof(struct tunnel_match_key),
4885 TUNNEL_INFO_BITS_MASK, true);
4886 if (IS_ERR(mapping)) {
4887 err = PTR_ERR(mapping);
4888 goto err_tun_mapping;
4889 }
4890 uplink_priv->tunnel_mapping = mapping;
4891
8e404fef
VB		 4892 /* 0xFFF is reserved for stack devices slow path table mark */
4893 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 4894 if (IS_ERR(mapping)) {
4895 err = PTR_ERR(mapping);
4896 goto err_enc_opts_mapping;
4897 }
4898 uplink_priv->tunnel_enc_opts_mapping = mapping;
4899
4900 err = rhashtable_init(tc_ht, &tc_ht_params);
4901 if (err)
4902 goto err_ht_init;
4903
9ba33339
RD		 4904 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4905
8914add2 4906 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4907 if (IS_ERR(uplink_priv->encap)) {
4908 err = PTR_ERR(uplink_priv->encap);
8914add2 4909 goto err_register_fib_notifier;
2b6c3c1e 4910 }
8914add2 4911
2b6c3c1e 4912 return 0;
0a7fcb78 4913
8914add2
VB		 4914err_register_fib_notifier:
4915 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 4916err_ht_init:
4917 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4918err_enc_opts_mapping:
4919 mapping_destroy(uplink_priv->tunnel_mapping);
4920err_tun_mapping:
2a9ab10a
CM		 4921#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4922 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
4923#endif
aedd133d 4924 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 4925 netdev_warn(priv->netdev,
4926 "Failed to initialize tc (eswitch), err: %d", err);
4927 return err;
655dc3d2
OG		 4928}
4929
4930void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4931{
0a7fcb78
PB		 4932 struct mlx5_rep_uplink_priv *uplink_priv;
4933
0a7fcb78 4934 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 4935
8914add2
VB		 4936 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4937 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4938
0a7fcb78
PB		 4939 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4940 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 4941
2a9ab10a
CM		 4942#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4943 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
4944#endif
aedd133d 4945 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 4946}
01252a27 4947
226f2ca3 4948int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4949{
d9ee0491 4950 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4951
4952 return atomic_read(&tc_ht->nelems);
4953}
04de7dda
RD		 4954
4955void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4956{
4957 struct mlx5e_tc_flow *flow, *tmp;
4958
4959 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4960 __mlx5e_tc_del_fdb_peer_flow(flow);
4961}
b4a23329
RD		 4962
4963void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4964{
4965 struct mlx5_rep_uplink_priv *rpriv =
4966 container_of(work, struct mlx5_rep_uplink_priv,
4967 reoffload_flows_work);
4968 struct mlx5e_tc_flow *flow, *tmp;
4969
ad86755b 4970 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4971 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4972 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4973 unready_flow_del(flow);
b4a23329 4974 }
ad86755b 4975 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4976}
e2394a61
VB		 4977
4978static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
4979 struct flow_cls_offload *cls_flower,
4980 unsigned long flags)
4981{
4982 switch (cls_flower->command) {
4983 case FLOW_CLS_REPLACE:
4984 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
4985 flags);
4986 case FLOW_CLS_DESTROY:
4987 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
4988 flags);
4989 case FLOW_CLS_STATS:
4990 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
4991 flags);
4992 default:
4993 return -EOPNOTSUPP;
4994 }
4995}
4996
4997int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4998 void *cb_priv)
4999{
ec9457a6 5000 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5001 struct mlx5e_priv *priv = cb_priv;
5002
2ff349c5
RD		 5003 if (!priv->netdev || !netif_device_present(priv->netdev))
5004 return -EOPNOTSUPP;
5005
ec9457a6
RD		 5006 if (mlx5e_is_uplink_rep(priv))
5007 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5008 else
5009 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5010
e2394a61
VB		 5011 switch (type) {
5012 case TC_SETUP_CLSFLOWER:
5013 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5014 default:
5015 return -EOPNOTSUPP;
5016 }
5017}
c7569097
AL		 5018
5019bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5020 struct sk_buff *skb)
5021{
5022#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5023 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5024 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5025 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5026 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5027 struct tc_skb_ext *tc_skb_ext;
5028 int err;
5029
5030 reg_b = be32_to_cpu(cqe->ft_metadata);
5031
5032 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5033
c9355682 5034 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5035 if (err) {
5036 netdev_dbg(priv->netdev,
5037 "Couldn't find chain for chain tag: %d, err: %d\n",
5038 chain_tag, err);
5039 return false;
5040 }
5041
a91d98a0
CM		 5042 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5043 chain = mapped_obj.chain;
c7569097
AL		 5044 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
5045 if (WARN_ON(!tc_skb_ext))
5046 return false;
5047
5048 tc_skb_ext->chain = chain;
aedd133d
AL		 5049
5050 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5051 ESW_ZONE_ID_MASK;
aedd133d
AL		 5052
5053 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5054 zone_restore_id))
5055 return false;
a91d98a0
CM		 5056 } else {
5057 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5058 return false;
c7569097
AL		 5059 }
5060#endif /* CONFIG_NET_TC_SKB_EXT */
5061
5062 return true;
5063}
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