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net/mlx5: E-Switch, Set vhca id valid flag when creating indir fwd group
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
41c2fd94 50#include <net/psample.h>
f6dfb4c3 51#include <net/arp.h>
3616d08b 52#include <net/ipv6_stubs.h>
f828ca6a 53#include <net/bareudp.h>
d34eb2fc 54#include <net/bonding.h>
e8f887ac 55#include "en.h"
1d447a39 56#include "en_rep.h"
768c3667 57#include "en/rep/tc.h"
e2394a61 58#include "en/rep/neigh.h"
232c0013 59#include "en_tc.h"
03a9d11e 60#include "eswitch.h"
3f6d08d1 61#include "fs_core.h"
2c81bfd5 62#include "en/port.h"
101f4de9 63#include "en/tc_tun.h"
0a7fcb78 64#include "en/mapping.h"
4c3844d9 65#include "en/tc_ct.h"
b2fdf3d0 66#include "en/mod_hdr.h"
0d9f9647
VB		 67#include "en/tc_priv.h"
68#include "en/tc_tun_encap.h"
2a9ab10a 69#include "esw/sample.h"
04de7dda 70#include "lib/devcom.h"
9272e3df 71#include "lib/geneve.h"
ae430332 72#include "lib/fs_chains.h"
7a978759 73#include "diag/en_tc_tracepoint.h"
1fe3e316 74#include <asm/div64.h>
e8f887ac 75
6a064674 76#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 77#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 78
acff797c 79#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 80#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 81
8f1e0b97
PB		 82struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
83 [CHAIN_TO_REG] = {
84 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
85 .moffset = 0,
ed2fe7ba 86 .mlen = 16,
8f1e0b97 87 },
10742efc
VB		 88 [VPORT_TO_REG] = {
89 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 90 .moffset = 16,
91 .mlen = 16,
10742efc 92 },
0a7fcb78
PB		 93 [TUNNEL_TO_REG] = {
94 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 95 .moffset = 8,
96 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 97 .soffset = MLX5_BYTE_OFF(fte_match_param,
98 misc_parameters_2.metadata_reg_c_1),
99 },
4c3844d9 100 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 101 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 102 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
103 [MARK_TO_REG] = mark_to_reg_ct,
104 [LABELS_TO_REG] = labels_to_reg_ct,
105 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 106 /* For NIC rules we store the retore metadata directly
107 * into reg_b that is passed to SW since we don't
108 * jump between steering domains.
109 */
110 [NIC_CHAIN_TO_REG] = {
111 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
112 .moffset = 0,
ed2fe7ba 113 .mlen = 16,
c7569097 114 },
aedd133d 115 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 116};
117
9ba33339
RD		 118/* To avoid false lock dependency warning set the tc_ht lock
119 * class different than the lock class of the ht being used when deleting
120 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
121 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
122 * it's different than the ht->mutex here.
123 */
124static struct lock_class_key tc_ht_lock_key;
125
0a7fcb78
PB		 126static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
127
128void
129mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
130 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 131 u32 val,
0a7fcb78
PB		 132 u32 mask)
133{
ed2fe7ba 134 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 135 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 136 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 137 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 138 u32 max_mask = GENMASK(match_len - 1, 0);
139 __be32 curr_mask_be, curr_val_be;
140 u32 curr_mask, curr_val;
0a7fcb78
PB		 141
142 fmask = headers_c + soffset;
143 fval = headers_v + soffset;
144
ed2fe7ba
PB		 145 memcpy(&curr_mask_be, fmask, 4);
146 memcpy(&curr_val_be, fval, 4);
147
148 curr_mask = be32_to_cpu(curr_mask_be);
149 curr_val = be32_to_cpu(curr_val_be);
150
151 //move to correct offset
152 WARN_ON(mask > max_mask);
153 mask <<= moffset;
154 val <<= moffset;
155 max_mask <<= moffset;
156
157 //zero val and mask
158 curr_mask &= ~max_mask;
159 curr_val &= ~max_mask;
0a7fcb78 160
ed2fe7ba
PB		 161 //add current to mask
162 curr_mask |= mask;
163 curr_val |= val;
164
165 //back to be32 and write
166 curr_mask_be = cpu_to_be32(curr_mask);
167 curr_val_be = cpu_to_be32(curr_val);
168
169 memcpy(fmask, &curr_mask_be, 4);
170 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 171
172 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
173}
174
7e36feeb
PB		 175void
176mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
177 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 178 u32 *val,
7e36feeb
PB		 179 u32 *mask)
180{
ed2fe7ba 181 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 182 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 183 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 184 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 185 u32 max_mask = GENMASK(match_len - 1, 0);
186 __be32 curr_mask_be, curr_val_be;
187 u32 curr_mask, curr_val;
7e36feeb
PB		 188
189 fmask = headers_c + soffset;
190 fval = headers_v + soffset;
191
ed2fe7ba
PB		 192 memcpy(&curr_mask_be, fmask, 4);
193 memcpy(&curr_val_be, fval, 4);
194
195 curr_mask = be32_to_cpu(curr_mask_be);
196 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 197
ed2fe7ba
PB		 198 *mask = (curr_mask >> moffset) & max_mask;
199 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 200}
201
0a7fcb78 202int
c7b9038d
VB		 203mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
204 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
205 enum mlx5_flow_namespace_type ns,
206 enum mlx5e_tc_attr_to_reg type,
207 u32 data)
0a7fcb78
PB		 208{
209 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
210 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
211 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
212 char *modact;
213 int err;
214
aedd133d 215 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 216 if (err)
217 return err;
218
219 modact = mod_hdr_acts->actions +
220 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
221
222 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 223 if (mlen == 32)
0a7fcb78
PB		 224 mlen = 0;
225
226 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
227 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 228 MLX5_SET(set_action_in, modact, offset, moffset);
229 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 230 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 231 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 232 mod_hdr_acts->num_actions++;
233
c7b9038d 234 return err;
0a7fcb78
PB		 235}
236
aedd133d
AL		 237static struct mlx5_tc_ct_priv *
238get_ct_priv(struct mlx5e_priv *priv)
239{
240 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
241 struct mlx5_rep_uplink_priv *uplink_priv;
242 struct mlx5e_rep_priv *uplink_rpriv;
243
e8711402 244 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 245 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
246 uplink_priv = &uplink_rpriv->uplink_priv;
247
248 return uplink_priv->ct_priv;
249 }
250
251 return priv->fs.tc.ct;
252}
253
f94d6389
CM		 254#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
255static struct mlx5_esw_psample *
256get_sample_priv(struct mlx5e_priv *priv)
257{
258 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
259 struct mlx5_rep_uplink_priv *uplink_priv;
260 struct mlx5e_rep_priv *uplink_rpriv;
261
262 if (is_mdev_switchdev_mode(priv->mdev)) {
263 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
264 uplink_priv = &uplink_rpriv->uplink_priv;
265
266 return uplink_priv->esw_psample;
267 }
268
269 return NULL;
270}
271#endif
272
aedd133d
AL		 273struct mlx5_flow_handle *
274mlx5_tc_rule_insert(struct mlx5e_priv *priv,
275 struct mlx5_flow_spec *spec,
276 struct mlx5_flow_attr *attr)
277{
278 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
279
e8711402 280 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 281 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
282
283 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
284}
285
286void
287mlx5_tc_rule_delete(struct mlx5e_priv *priv,
288 struct mlx5_flow_handle *rule,
289 struct mlx5_flow_attr *attr)
290{
291 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
292
e8711402 293 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 294 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
295
296 return;
297 }
298
299 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
300}
301
c7b9038d
VB		 302int
303mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
304 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
305 enum mlx5_flow_namespace_type ns,
306 enum mlx5e_tc_attr_to_reg type,
307 u32 data)
308{
309 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
310
311 return ret < 0 ? ret : 0;
312}
313
314void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
315 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
316 enum mlx5e_tc_attr_to_reg type,
317 int act_id, u32 data)
318{
319 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
320 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
321 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
322 char *modact;
323
324 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
325
326 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 327 if (mlen == 32)
c7b9038d
VB		 328 mlen = 0;
329
330 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
331 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 332 MLX5_SET(set_action_in, modact, offset, moffset);
333 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 334 MLX5_SET(set_action_in, modact, data, data);
335}
336
77ab67b7
OG		 337struct mlx5e_hairpin {
338 struct mlx5_hairpin *pair;
339
340 struct mlx5_core_dev *func_mdev;
3f6d08d1 341 struct mlx5e_priv *func_priv;
77ab67b7
OG		 342 u32 tdn;
343 u32 tirn;
3f6d08d1
OG		 344
345 int num_channels;
346 struct mlx5e_rqt indir_rqt;
347 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
348 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 349};
350
5c65c564
OG		 351struct mlx5e_hairpin_entry {
352 /* a node of a hash table which keeps all the hairpin entries */
353 struct hlist_node hairpin_hlist;
354
73edca73
VB		 355 /* protects flows list */
356 spinlock_t flows_lock;
5c65c564
OG		 357 /* flows sharing the same hairpin */
358 struct list_head flows;
db76ca24
VB		 359 /* hpe's that were not fully initialized when dead peer update event
360 * function traversed them.
361 */
362 struct list_head dead_peer_wait_list;
5c65c564 363
d8822868 364 u16 peer_vhca_id;
106be53b 365 u8 prio;
5c65c564 366 struct mlx5e_hairpin *hp;
e4f9abbd 367 refcount_t refcnt;
db76ca24 368 struct completion res_ready;
5c65c564
OG		 369};
370
5a7e5bcb
VB		 371static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
372 struct mlx5e_tc_flow *flow);
373
0d9f9647 374struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 375{
376 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
377 return ERR_PTR(-EINVAL);
378 return flow;
379}
380
0d9f9647 381void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 382{
383 if (refcount_dec_and_test(&flow->refcnt)) {
384 mlx5e_tc_del_flow(priv, flow);
c5d326b2 385 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 386 }
387}
388
aedd133d 389bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 390{
391 return flow_flag_test(flow, ESWITCH);
392}
393
84179981
PB		 394static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
395{
396 return flow_flag_test(flow, FT);
397}
398
0d9f9647 399bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 400{
401 return flow_flag_test(flow, OFFLOADED);
402}
403
b2fdf3d0 404static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 405{
b2fdf3d0
PB		 406 return mlx5e_is_eswitch_flow(flow) ?
407 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 408}
409
dd58edc3 410static struct mod_hdr_tbl *
b2fdf3d0 411get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 412{
413 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
414
b2fdf3d0
PB		 415 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
416 &esw->offloads.mod_hdr :
dd58edc3
VB		 417 &priv->fs.tc.mod_hdr;
418}
419
11c9c548
OG		 420static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
421 struct mlx5e_tc_flow *flow,
422 struct mlx5e_tc_flow_parse_attr *parse_attr)
423{
b2fdf3d0
PB		 424 struct mlx5_modify_hdr *modify_hdr;
425 struct mlx5e_mod_hdr_handle *mh;
11c9c548 426
b2fdf3d0
PB		 427 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
428 get_flow_name_space(flow),
429 &parse_attr->mod_hdr_acts);
430 if (IS_ERR(mh))
431 return PTR_ERR(mh);
11c9c548 432
b2fdf3d0 433 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 434 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 435 flow->mh = mh;
11c9c548
OG		 436
437 return 0;
11c9c548
OG		 438}
439
440static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
441 struct mlx5e_tc_flow *flow)
442{
5a7e5bcb 443 /* flow wasn't fully initialized */
dd58edc3 444 if (!flow->mh)
5a7e5bcb
VB		 445 return;
446
b2fdf3d0
PB		 447 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
448 flow->mh);
dd58edc3 449 flow->mh = NULL;
11c9c548
OG		 450}
451
77ab67b7
OG		 452static
453struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
454{
b1c2f631 455 struct mlx5_core_dev *mdev;
77ab67b7
OG		 456 struct net_device *netdev;
457 struct mlx5e_priv *priv;
458
b1c2f631
DC		 459 netdev = dev_get_by_index(net, ifindex);
460 if (!netdev)
461 return ERR_PTR(-ENODEV);
462
77ab67b7 463 priv = netdev_priv(netdev);
b1c2f631
DC		 464 mdev = priv->mdev;
465 dev_put(netdev);
466
467 /* Mirred tc action holds a refcount on the ifindex net_device (see
468 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
469 * after dev_put(netdev), while we're in the context of adding a tc flow.
470 *
471 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
472 * stored in a hairpin object, which exists until all flows, that refer to it, get
473 * removed.
474 *
475 * On the other hand, after a hairpin object has been created, the peer net_device may
476 * be removed/unbound while there are still some hairpin flows that are using it. This
477 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
478 * NETDEV_UNREGISTER event of the peer net_device.
479 */
480 return mdev;
77ab67b7
OG		 481}
482
483static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
484{
e0b4b472 485 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 486 void *tirc;
487 int err;
488
489 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
490 if (err)
491 goto alloc_tdn_err;
492
493 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
494
495 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 496 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 497 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
498
e0b4b472 499 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 500 if (err)
501 goto create_tir_err;
502
503 return 0;
504
505create_tir_err:
506 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
507alloc_tdn_err:
508 return err;
509}
510
511static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
512{
513 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
514 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
515}
516
2119bda6 517static int mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
3f6d08d1 518{
3f6d08d1
OG		 519 struct mlx5e_priv *priv = hp->func_priv;
520 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
6def6e47 521 u32 *indirection_rqt, rqn;
3f6d08d1 522
6def6e47 523 indirection_rqt = kcalloc(sz, sizeof(*indirection_rqt), GFP_KERNEL);
2119bda6
AB		 524 if (!indirection_rqt)
525 return -ENOMEM;
526
3f6d08d1
OG		 527 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
528 hp->num_channels);
529
530 for (i = 0; i < sz; i++) {
531 ix = i;
bbeb53b8 532 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 533 ix = mlx5e_bits_invert(i, ilog2(sz));
534 ix = indirection_rqt[ix];
535 rqn = hp->pair->rqn[ix];
536 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
537 }
2119bda6
AB		 538
539 kfree(indirection_rqt);
540 return 0;
3f6d08d1
OG		 541}
542
543static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
544{
545 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
546 struct mlx5e_priv *priv = hp->func_priv;
547 struct mlx5_core_dev *mdev = priv->mdev;
548 void *rqtc;
549 u32 *in;
550
551 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
552 in = kvzalloc(inlen, GFP_KERNEL);
553 if (!in)
554 return -ENOMEM;
555
556 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
557
558 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
559 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
560
2119bda6
AB		 561 err = mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
562 if (err)
563 goto out;
3f6d08d1
OG		 564
565 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
566 if (!err)
567 hp->indir_rqt.enabled = true;
568
2119bda6 569out:
3f6d08d1
OG		 570 kvfree(in);
571 return err;
572}
573
574static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
575{
576 struct mlx5e_priv *priv = hp->func_priv;
577 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
578 int tt, i, err;
579 void *tirc;
580
581 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 582 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
583
3f6d08d1
OG		 584 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
585 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
586
587 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
588 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
589 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 590 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
591
3f6d08d1 592 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 593 &hp->indir_tirn[tt]);
3f6d08d1
OG		 594 if (err) {
595 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
596 goto err_destroy_tirs;
597 }
598 }
599 return 0;
600
601err_destroy_tirs:
602 for (i = 0; i < tt; i++)
603 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
604 return err;
605}
606
607static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
608{
609 int tt;
610
611 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
612 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
613}
614
615static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
616 struct ttc_params *ttc_params)
617{
618 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
619 int tt;
620
621 memset(ttc_params, 0, sizeof(*ttc_params));
622
623 ttc_params->any_tt_tirn = hp->tirn;
624
625 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
626 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
627
6412bb39 628 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 629 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
630 ft_attr->prio = MLX5E_TC_PRIO;
631}
632
633static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
634{
635 struct mlx5e_priv *priv = hp->func_priv;
636 struct ttc_params ttc_params;
637 int err;
638
639 err = mlx5e_hairpin_create_indirect_rqt(hp);
640 if (err)
641 return err;
642
643 err = mlx5e_hairpin_create_indirect_tirs(hp);
644 if (err)
645 goto err_create_indirect_tirs;
646
647 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
648 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
649 if (err)
650 goto err_create_ttc_table;
651
652 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
653 hp->num_channels, hp->ttc.ft.t->id);
654
655 return 0;
656
657err_create_ttc_table:
658 mlx5e_hairpin_destroy_indirect_tirs(hp);
659err_create_indirect_tirs:
660 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
661
662 return err;
663}
664
665static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
666{
667 struct mlx5e_priv *priv = hp->func_priv;
668
669 mlx5e_destroy_ttc_table(priv, &hp->ttc);
670 mlx5e_hairpin_destroy_indirect_tirs(hp);
671 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
672}
673
77ab67b7
OG		 674static struct mlx5e_hairpin *
675mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
676 int peer_ifindex)
677{
678 struct mlx5_core_dev *func_mdev, *peer_mdev;
679 struct mlx5e_hairpin *hp;
680 struct mlx5_hairpin *pair;
681 int err;
682
683 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
684 if (!hp)
685 return ERR_PTR(-ENOMEM);
686
687 func_mdev = priv->mdev;
688 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 689 if (IS_ERR(peer_mdev)) {
690 err = PTR_ERR(peer_mdev);
691 goto create_pair_err;
692 }
77ab67b7
OG		 693
694 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
695 if (IS_ERR(pair)) {
696 err = PTR_ERR(pair);
697 goto create_pair_err;
698 }
699 hp->pair = pair;
700 hp->func_mdev = func_mdev;
3f6d08d1
OG		 701 hp->func_priv = priv;
702 hp->num_channels = params->num_channels;
77ab67b7
OG		 703
704 err = mlx5e_hairpin_create_transport(hp);
705 if (err)
706 goto create_transport_err;
707
3f6d08d1
OG		 708 if (hp->num_channels > 1) {
709 err = mlx5e_hairpin_rss_init(hp);
710 if (err)
711 goto rss_init_err;
712 }
713
77ab67b7
OG		 714 return hp;
715
3f6d08d1
OG		 716rss_init_err:
717 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 718create_transport_err:
719 mlx5_core_hairpin_destroy(hp->pair);
720create_pair_err:
721 kfree(hp);
722 return ERR_PTR(err);
723}
724
725static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
726{
3f6d08d1
OG		 727 if (hp->num_channels > 1)
728 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 729 mlx5e_hairpin_destroy_transport(hp);
730 mlx5_core_hairpin_destroy(hp->pair);
731 kvfree(hp);
732}
733
106be53b
OG		 734static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
735{
736 return (peer_vhca_id << 16 | prio);
737}
738
5c65c564 739static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 740 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 741{
742 struct mlx5e_hairpin_entry *hpe;
106be53b 743 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 744
745 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 746 hairpin_hlist, hash_key) {
e4f9abbd
VB		 747 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
748 refcount_inc(&hpe->refcnt);
5c65c564 749 return hpe;
e4f9abbd 750 }
5c65c564
OG		 751 }
752
753 return NULL;
754}
755
e4f9abbd
VB		 756static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
757 struct mlx5e_hairpin_entry *hpe)
758{
759 /* no more hairpin flows for us, release the hairpin pair */
b32accda 760 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 761 return;
b32accda
VB		 762 hash_del(&hpe->hairpin_hlist);
763 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 764
db76ca24
VB		 765 if (!IS_ERR_OR_NULL(hpe->hp)) {
766 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
767 dev_name(hpe->hp->pair->peer_mdev->device));
768
769 mlx5e_hairpin_destroy(hpe->hp);
770 }
e4f9abbd
VB		 771
772 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 773 kfree(hpe);
774}
775
106be53b
OG		 776#define UNKNOWN_MATCH_PRIO 8
777
778static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 779 struct mlx5_flow_spec *spec, u8 *match_prio,
780 struct netlink_ext_ack *extack)
106be53b
OG		 781{
782 void *headers_c, *headers_v;
783 u8 prio_val, prio_mask = 0;
784 bool vlan_present;
785
786#ifdef CONFIG_MLX5_CORE_EN_DCB
787 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 788 NL_SET_ERR_MSG_MOD(extack,
789 "only PCP trust state supported for hairpin");
106be53b
OG		 790 return -EOPNOTSUPP;
791 }
792#endif
793 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
794 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
795
796 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
797 if (vlan_present) {
798 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
799 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
800 }
801
802 if (!vlan_present || !prio_mask) {
803 prio_val = UNKNOWN_MATCH_PRIO;
804 } else if (prio_mask != 0x7) {
e98bedf5
EB		 805 NL_SET_ERR_MSG_MOD(extack,
806 "masked priority match not supported for hairpin");
106be53b
OG		 807 return -EOPNOTSUPP;
808 }
809
810 *match_prio = prio_val;
811 return 0;
812}
813
5c65c564
OG		 814static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
815 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 816 struct mlx5e_tc_flow_parse_attr *parse_attr,
817 struct netlink_ext_ack *extack)
5c65c564 818{
98b66cb1 819 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 820 struct mlx5_hairpin_params params;
d8822868 821 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 822 struct mlx5e_hairpin_entry *hpe;
823 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 824 u64 link_speed64;
825 u32 link_speed;
106be53b 826 u8 match_prio;
d8822868 827 u16 peer_id;
5c65c564
OG		 828 int err;
829
d8822868 830 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 831 if (IS_ERR(peer_mdev)) {
832 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
833 return PTR_ERR(peer_mdev);
834 }
835
d8822868 836 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 837 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 838 return -EOPNOTSUPP;
839 }
840
d8822868 841 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 842 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
843 extack);
106be53b
OG		 844 if (err)
845 return err;
b32accda
VB		 846
847 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 848 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 849 if (hpe) {
850 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
851 wait_for_completion(&hpe->res_ready);
852
853 if (IS_ERR(hpe->hp)) {
854 err = -EREMOTEIO;
855 goto out_err;
856 }
5c65c564 857 goto attach_flow;
db76ca24 858 }
5c65c564
OG		 859
860 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 861 if (!hpe) {
db76ca24
VB		 862 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
863 return -ENOMEM;
b32accda 864 }
5c65c564 865
73edca73 866 spin_lock_init(&hpe->flows_lock);
5c65c564 867 INIT_LIST_HEAD(&hpe->flows);
db76ca24 868 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 869 hpe->peer_vhca_id = peer_id;
106be53b 870 hpe->prio = match_prio;
e4f9abbd 871 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 872 init_completion(&hpe->res_ready);
873
874 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
875 hash_hairpin_info(peer_id, match_prio));
876 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 877
6cdc686a 878 params.log_data_size = 16;
5c65c564
OG		 879 params.log_data_size = min_t(u8, params.log_data_size,
880 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
881 params.log_data_size = max_t(u8, params.log_data_size,
882 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 883
eb9180f7
OG		 884 params.log_num_packets = params.log_data_size -
885 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
886 params.log_num_packets = min_t(u8, params.log_num_packets,
887 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
888
889 params.q_counter = priv->q_counter;
3f6d08d1 890 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 891 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 892 link_speed = max_t(u32, link_speed, 50000);
893 link_speed64 = link_speed;
894 do_div(link_speed64, 50000);
895 params.num_channels = link_speed64;
896
5c65c564 897 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 898 hpe->hp = hp;
899 complete_all(&hpe->res_ready);
5c65c564
OG		 900 if (IS_ERR(hp)) {
901 err = PTR_ERR(hp);
db76ca24 902 goto out_err;
5c65c564
OG		 903 }
904
eb9180f7 905 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 906 hp->tirn, hp->pair->rqn[0],
907 dev_name(hp->pair->peer_mdev->device),
eb9180f7 908 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 909
5c65c564 910attach_flow:
3f6d08d1 911 if (hpe->hp->num_channels > 1) {
226f2ca3 912 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 913 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 914 } else {
c620b772 915 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 916 }
b32accda 917
e4f9abbd 918 flow->hpe = hpe;
73edca73 919 spin_lock(&hpe->flows_lock);
5c65c564 920 list_add(&flow->hairpin, &hpe->flows);
73edca73 921 spin_unlock(&hpe->flows_lock);
3f6d08d1 922
5c65c564
OG		 923 return 0;
924
db76ca24
VB		 925out_err:
926 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 927 return err;
928}
929
930static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
931 struct mlx5e_tc_flow *flow)
932{
5a7e5bcb 933 /* flow wasn't fully initialized */
e4f9abbd 934 if (!flow->hpe)
5a7e5bcb
VB		 935 return;
936
73edca73 937 spin_lock(&flow->hpe->flows_lock);
5c65c564 938 list_del(&flow->hairpin);
73edca73
VB		 939 spin_unlock(&flow->hpe->flows_lock);
940
e4f9abbd
VB		 941 mlx5e_hairpin_put(priv, flow->hpe);
942 flow->hpe = NULL;
5c65c564
OG		 943}
944
08247066
AL		 945struct mlx5_flow_handle *
946mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
947 struct mlx5_flow_spec *spec,
c620b772 948 struct mlx5_flow_attr *attr)
e8f887ac 949{
08247066 950 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 951 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 952 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 953 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 954 struct mlx5_flow_destination dest[2] = {};
66958ed9 955 struct mlx5_flow_act flow_act = {
3bc4b7bf 956 .action = attr->action,
bb0ee7dc 957 .flags = FLOW_ACT_NO_APPEND,
66958ed9 958 };
08247066 959 struct mlx5_flow_handle *rule;
c7569097 960 struct mlx5_flow_table *ft;
08247066 961 int dest_ix = 0;
e8f887ac 962
bb0ee7dc 963 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 964 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 965
aedd133d
AL		 966 if (attr->dest_ft) {
967 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
968 dest[dest_ix].ft = attr->dest_ft;
969 dest_ix++;
970 } else if (nic_attr->hairpin_ft) {
08247066 971 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 972 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 973 dest_ix++;
c620b772 974 } else if (nic_attr->hairpin_tirn) {
08247066 975 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 976 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 977 dest_ix++;
3f6d08d1
OG		 978 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
979 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 980 if (attr->dest_chain) {
981 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
982 attr->dest_chain, 1,
983 MLX5E_TC_FT_LEVEL);
984 if (IS_ERR(dest[dest_ix].ft))
985 return ERR_CAST(dest[dest_ix].ft);
986 } else {
6783f0a2 987 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 988 }
3f6d08d1 989 dest_ix++;
5c65c564 990 }
aad7e08d 991
c7569097
AL		 992 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
993 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
994 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
995
08247066 996 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 997 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 998 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 999 dest_ix++;
aad7e08d
AV		 1000 }
1001
08247066 1002 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 1003 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 1004
6a064674
AL		 1005 mutex_lock(&tc->t_lock);
1006 if (IS_ERR_OR_NULL(tc->t)) {
1007 /* Create the root table here if doesn't exist yet */
1008 tc->t =
c7569097 1009 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 1010
1011 if (IS_ERR(tc->t)) {
1012 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 1013 netdev_err(priv->netdev,
1014 "Failed to create tc offload table\n");
c7569097
AL		 1015 rule = ERR_CAST(priv->fs.tc.t);
1016 goto err_ft_get;
e8f887ac 1017 }
e8f887ac 1018 }
08247066 1019 mutex_unlock(&tc->t_lock);
e8f887ac 1020
aedd133d
AL		 1021 if (attr->chain || attr->prio)
1022 ft = mlx5_chains_get_table(nic_chains,
1023 attr->chain, attr->prio,
1024 MLX5E_TC_FT_LEVEL);
1025 else
1026 ft = attr->ft;
1027
c7569097
AL		 1028 if (IS_ERR(ft)) {
1029 rule = ERR_CAST(ft);
1030 goto err_ft_get;
1031 }
1032
c620b772 1033 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1034 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1035
c7569097 1036 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1037 &flow_act, dest, dest_ix);
1038 if (IS_ERR(rule))
c7569097 1039 goto err_rule;
08247066
AL		 1040
1041 return rule;
c7569097
AL		 1042
1043err_rule:
aedd133d
AL		 1044 if (attr->chain || attr->prio)
1045 mlx5_chains_put_table(nic_chains,
1046 attr->chain, attr->prio,
1047 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1048err_ft_get:
1049 if (attr->dest_chain)
1050 mlx5_chains_put_table(nic_chains,
1051 attr->dest_chain, 1,
1052 MLX5E_TC_FT_LEVEL);
1053
1054 return ERR_CAST(rule);
08247066
AL		 1055}
1056
1057static int
1058mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1059 struct mlx5e_tc_flow_parse_attr *parse_attr,
1060 struct mlx5e_tc_flow *flow,
1061 struct netlink_ext_ack *extack)
1062{
c620b772 1063 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1064 struct mlx5_core_dev *dev = priv->mdev;
1065 struct mlx5_fc *counter = NULL;
1066 int err;
1067
1068 if (flow_flag_test(flow, HAIRPIN)) {
1069 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1070 if (err)
1071 return err;
1072 }
1073
1074 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1075 counter = mlx5_fc_create(dev, true);
1076 if (IS_ERR(counter))
1077 return PTR_ERR(counter);
1078
1079 attr->counter = counter;
1080 }
1081
1082 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1083 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1084 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1085 if (err)
1086 return err;
1087 }
1088
aedd133d
AL		 1089 if (flow_flag_test(flow, CT))
1090 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1091 attr, &parse_attr->mod_hdr_acts);
1092 else
1093 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1094 attr);
aad7e08d 1095
a2b7189b 1096 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1097}
1098
08247066 1099void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1100 struct mlx5_flow_handle *rule,
1101 struct mlx5_flow_attr *attr)
08247066 1102{
c7569097
AL		 1103 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1104
08247066 1105 mlx5_del_flow_rules(rule);
c7569097 1106
aedd133d
AL		 1107 if (attr->chain || attr->prio)
1108 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1109 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1110
1111 if (attr->dest_chain)
1112 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1113 MLX5E_TC_FT_LEVEL);
08247066
AL		 1114}
1115
d85cdccb
OG		 1116static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1117 struct mlx5e_tc_flow *flow)
1118{
c620b772 1119 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1120 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1121
c7569097
AL		 1122 flow_flag_clear(flow, OFFLOADED);
1123
aedd133d
AL		 1124 if (flow_flag_test(flow, CT))
1125 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1126 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1127 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1128
c7569097
AL		 1129 /* Remove root table if no rules are left to avoid
1130 * extra steering hops.
1131 */
b6fac0b4 1132 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1133 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1134 !IS_ERR_OR_NULL(tc->t)) {
1135 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1136 priv->fs.tc.t = NULL;
1137 }
b6fac0b4 1138 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1139
aedd133d
AL		 1140 kvfree(attr->parse_attr);
1141
513f8f7f 1142 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1143 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1144
aedd133d
AL		 1145 mlx5_fc_destroy(priv->mdev, attr->counter);
1146
226f2ca3 1147 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1148 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1149
1150 kfree(flow->attr);
d85cdccb
OG		 1151}
1152
0d9f9647 1153struct mlx5_flow_handle *
6d2a3ed0
OG		 1154mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1155 struct mlx5e_tc_flow *flow,
1156 struct mlx5_flow_spec *spec,
c620b772 1157 struct mlx5_flow_attr *attr)
6d2a3ed0 1158{
1ef3018f 1159 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1160 struct mlx5_flow_handle *rule;
4c3844d9 1161
89e39467
PB		 1162 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1163 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1164
1ef3018f
PB		 1165 if (flow_flag_test(flow, CT)) {
1166 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1167
69e2916e 1168 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1169 flow, spec, attr,
1ef3018f 1170 mod_hdr_acts);
f94d6389
CM		 1171#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1172 } else if (flow_flag_test(flow, SAMPLE)) {
1173 rule = mlx5_esw_sample_offload(get_sample_priv(flow->priv), spec, attr);
1174#endif
69e2916e
PB		 1175 } else {
1176 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1177 }
6d2a3ed0 1178
6d2a3ed0
OG		 1179 if (IS_ERR(rule))
1180 return rule;
1181
c620b772 1182 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1183 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1184 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1185 if (flow_flag_test(flow, CT))
1186 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1187 else
1188 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1189 return flow->rule[1];
1190 }
1191 }
1192
6d2a3ed0
OG		 1193 return rule;
1194}
1195
0d9f9647
VB		 1196void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1197 struct mlx5e_tc_flow *flow,
1198 struct mlx5_flow_attr *attr)
6d2a3ed0 1199{
226f2ca3 1200 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1201
89e39467
PB		 1202 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1203 goto offload_rule_0;
1204
4c3844d9 1205 if (flow_flag_test(flow, CT)) {
aedd133d 1206 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1207 return;
1208 }
1209
f94d6389
CM		 1210#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
1211 if (flow_flag_test(flow, SAMPLE)) {
1212 mlx5_esw_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
1213 return;
1214 }
1215#endif
1216
c620b772 1217 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1218 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1219
89e39467 1220offload_rule_0:
6d2a3ed0
OG		 1221 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1222}
1223
0d9f9647 1224struct mlx5_flow_handle *
5dbe906f
PB		 1225mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1226 struct mlx5e_tc_flow *flow,
178f69b4 1227 struct mlx5_flow_spec *spec)
5dbe906f 1228{
c620b772 1229 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1230 struct mlx5_flow_handle *rule;
1231
c620b772
AL		 1232 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1233 if (!slow_attr)
1234 return ERR_PTR(-ENOMEM);
5dbe906f 1235
c620b772
AL		 1236 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1237 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1238 slow_attr->esw_attr->split_count = 0;
1239 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1240
1241 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1242 if (!IS_ERR(rule))
226f2ca3 1243 flow_flag_set(flow, SLOW);
5dbe906f 1244
c620b772
AL		 1245 kfree(slow_attr);
1246
5dbe906f
PB		 1247 return rule;
1248}
1249
0d9f9647
VB		 1250void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1251 struct mlx5e_tc_flow *flow)
5dbe906f 1252{
c620b772 1253 struct mlx5_flow_attr *slow_attr;
178f69b4 1254
c620b772 1255 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1256 if (!slow_attr) {
1257 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1258 return;
1259 }
c620b772
AL		 1260
1261 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1262 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1263 slow_attr->esw_attr->split_count = 0;
1264 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1265 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1266 flow_flag_clear(flow, SLOW);
c620b772 1267 kfree(slow_attr);
5dbe906f
PB		 1268}
1269
ad86755b
VB		 1270/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1271 * function.
1272 */
1273static void unready_flow_add(struct mlx5e_tc_flow *flow,
1274 struct list_head *unready_flows)
1275{
1276 flow_flag_set(flow, NOT_READY);
1277 list_add_tail(&flow->unready, unready_flows);
1278}
1279
1280/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1281 * function.
1282 */
1283static void unready_flow_del(struct mlx5e_tc_flow *flow)
1284{
1285 list_del(&flow->unready);
1286 flow_flag_clear(flow, NOT_READY);
1287}
1288
b4a23329
RD		 1289static void add_unready_flow(struct mlx5e_tc_flow *flow)
1290{
1291 struct mlx5_rep_uplink_priv *uplink_priv;
1292 struct mlx5e_rep_priv *rpriv;
1293 struct mlx5_eswitch *esw;
1294
1295 esw = flow->priv->mdev->priv.eswitch;
1296 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1297 uplink_priv = &rpriv->uplink_priv;
1298
ad86755b
VB		 1299 mutex_lock(&uplink_priv->unready_flows_lock);
1300 unready_flow_add(flow, &uplink_priv->unready_flows);
1301 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1302}
1303
1304static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1305{
ad86755b
VB		 1306 struct mlx5_rep_uplink_priv *uplink_priv;
1307 struct mlx5e_rep_priv *rpriv;
1308 struct mlx5_eswitch *esw;
1309
1310 esw = flow->priv->mdev->priv.eswitch;
1311 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1312 uplink_priv = &rpriv->uplink_priv;
1313
1314 mutex_lock(&uplink_priv->unready_flows_lock);
1315 unready_flow_del(flow);
1316 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1317}
1318
10742efc
VB		 1319static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1320
a508728a 1321bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1322{
1323 struct mlx5_core_dev *out_mdev, *route_mdev;
1324 struct mlx5e_priv *out_priv, *route_priv;
1325
1326 out_priv = netdev_priv(out_dev);
1327 out_mdev = out_priv->mdev;
1328 route_priv = netdev_priv(route_dev);
1329 route_mdev = route_priv->mdev;
1330
1331 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1332 route_mdev->coredev_type != MLX5_COREDEV_VF)
1333 return false;
1334
1335 return same_hw_devs(out_priv, route_priv);
1336}
1337
a508728a 1338int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1339{
1340 struct mlx5e_priv *out_priv, *route_priv;
1341 struct mlx5_core_dev *route_mdev;
1342 struct mlx5_eswitch *esw;
1343 u16 vhca_id;
1344 int err;
1345
1346 out_priv = netdev_priv(out_dev);
1347 esw = out_priv->mdev->priv.eswitch;
1348 route_priv = netdev_priv(route_dev);
1349 route_mdev = route_priv->mdev;
1350
1351 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1352 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1353 return err;
1354}
1355
c7b9038d
VB		 1356int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1357 struct mlx5e_tc_flow_parse_attr *parse_attr,
1358 struct mlx5e_tc_flow *flow)
1359{
1360 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1361 struct mlx5_modify_hdr *mod_hdr;
1362
1363 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1364 get_flow_name_space(flow),
1365 mod_hdr_acts->num_actions,
1366 mod_hdr_acts->actions);
1367 if (IS_ERR(mod_hdr))
1368 return PTR_ERR(mod_hdr);
1369
1370 WARN_ON(flow->attr->modify_hdr);
1371 flow->attr->modify_hdr = mod_hdr;
1372
1373 return 0;
1374}
1375
c83954ab 1376static int
74491de9 1377mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1378 struct mlx5e_tc_flow *flow,
1379 struct netlink_ext_ack *extack)
adb4c123
OG		 1380{
1381 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1382 struct mlx5e_tc_flow_parse_attr *parse_attr;
1383 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1384 bool vf_tun = false, encap_valid = true;
fe7738eb 1385 struct net_device *encap_dev = NULL;
c620b772 1386 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1387 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1388 struct mlx5e_rep_priv *rpriv;
1389 struct mlx5e_priv *out_priv;
39ac237c 1390 u32 max_prio, max_chain;
0ad060ee 1391 int err = 0;
f493f155 1392 int out_index;
8b32580d 1393
84179981
PB		 1394 /* We check chain range only for tc flows.
1395 * For ft flows, we checked attr->chain was originally 0 and set it to
1396 * FDB_FT_CHAIN which is outside tc range.
1397 * See mlx5e_rep_setup_ft_cb().
1398 */
ae430332 1399 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1400 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1401 NL_SET_ERR_MSG_MOD(extack,
1402 "Requested chain is out of supported range");
8914add2
VB		 1403 err = -EOPNOTSUPP;
1404 goto err_out;
bf07aa73
PB		 1405 }
1406
ae430332 1407 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1408 if (attr->prio > max_prio) {
61644c3d
RD		 1409 NL_SET_ERR_MSG_MOD(extack,
1410 "Requested priority is out of supported range");
8914add2
VB		 1411 err = -EOPNOTSUPP;
1412 goto err_out;
bf07aa73 1413 }
e52c2802 1414
777bb800
VB		 1415 if (flow_flag_test(flow, TUN_RX)) {
1416 err = mlx5e_attach_decap_route(priv, flow);
1417 if (err)
8914add2 1418 goto err_out;
777bb800
VB		 1419 }
1420
14e6b038
EC		 1421 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1422 err = mlx5e_attach_decap(priv, flow, extack);
1423 if (err)
8914add2 1424 goto err_out;
14e6b038
EC		 1425 }
1426
c620b772
AL		 1427 parse_attr = attr->parse_attr;
1428 esw_attr = attr->esw_attr;
1429
f493f155 1430 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1431 struct net_device *out_dev;
8c4dc42b
EB		 1432 int mirred_ifindex;
1433
c620b772 1434 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1435 continue;
1436
7040632d 1437 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1438 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1439 if (!out_dev) {
1440 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1441 err = -ENODEV;
1442 goto err_out;
1443 }
733d4f36 1444 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1445 extack, &encap_dev, &encap_valid);
fe7738eb 1446 dev_put(out_dev);
0ad060ee 1447 if (err)
8914add2 1448 goto err_out;
0ad060ee 1449
8914add2
VB		 1450 if (esw_attr->dests[out_index].flags &
1451 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1452 vf_tun = true;
3c37745e
OG		 1453 out_priv = netdev_priv(encap_dev);
1454 rpriv = out_priv->ppriv;
c620b772
AL		 1455 esw_attr->dests[out_index].rep = rpriv->rep;
1456 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1457 }
1458
7d1a3d08
VB		 1459 if (vf_tun && esw_attr->out_count > 1) {
1460 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1461 err = -EOPNOTSUPP;
1462 goto err_out;
1463 }
1464
8b32580d 1465 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1466 if (err)
8914add2 1467 goto err_out;
adb4c123 1468
d5a3c2b6
RD		 1469 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1470 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1471 if (vf_tun) {
1472 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1473 if (err)
1474 goto err_out;
1475 } else {
1476 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1477 if (err)
1478 goto err_out;
1479 }
d7e75a32
OG		 1480 }
1481
b8aee822 1482 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1483 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1484 if (IS_ERR(counter)) {
1485 err = PTR_ERR(counter);
1486 goto err_out;
1487 }
b8aee822
MB		 1488
1489 attr->counter = counter;
1490 }
1491
0ad060ee
RD		 1492 /* we get here if one of the following takes place:
1493 * (1) there's no error
1494 * (2) there's an encap action and we don't have valid neigh
3c37745e 1495 */
bc1d75fa 1496 if (!encap_valid)
178f69b4 1497 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1498 else
6d2a3ed0 1499 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1500
8914add2
VB		 1501 if (IS_ERR(flow->rule[0])) {
1502 err = PTR_ERR(flow->rule[0]);
1503 goto err_out;
1504 }
1505 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1506
1507 return 0;
8914add2
VB		 1508
1509err_out:
1510 flow_flag_set(flow, FAILED);
1511 return err;
aa0cbbae 1512}
d85cdccb 1513
9272e3df
YK		 1514static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1515{
c620b772 1516 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1517 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1518 spec->match_value,
1519 misc_parameters_3);
1520 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1521 headers_v,
1522 geneve_tlv_option_0_data);
1523
1524 return !!geneve_tlv_opt_0_data;
1525}
1526
d85cdccb
OG		 1527static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1528 struct mlx5e_tc_flow *flow)
1529{
1530 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1531 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1532 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1533 bool vf_tun = false;
f493f155 1534 int out_index;
d85cdccb 1535
777bb800 1536 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1537 mlx5e_put_flow_tunnel_id(flow);
1538
12a240a4 1539 if (flow_flag_test(flow, NOT_READY))
b4a23329 1540 remove_unready_flow(flow);
ef06c9ee 1541
226f2ca3
VB		 1542 if (mlx5e_is_offloaded_flow(flow)) {
1543 if (flow_flag_test(flow, SLOW))
178f69b4 1544 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1545 else
1546 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1547 }
d85cdccb 1548
9272e3df
YK		 1549 if (mlx5_flow_has_geneve_opt(flow))
1550 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1551
513f8f7f 1552 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1553
777bb800
VB		 1554 if (flow->decap_route)
1555 mlx5e_detach_decap_route(priv, flow);
1556
1557 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1558 if (esw_attr->dests[out_index].flags &
1559 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1560 vf_tun = true;
777bb800 1561 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1562 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1563 kfree(attr->parse_attr->tun_info[out_index]);
1564 }
777bb800 1565 }
d7e75a32 1566
aedd133d 1567 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1568
c7b9038d
VB		 1569 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1570 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1571 if (vf_tun && attr->modify_hdr)
1572 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1573 else
1574 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1575 }
8914add2
VB		 1576 kvfree(attr->parse_attr);
1577 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1578
1579 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1580 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1581
1582 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1583 mlx5e_detach_decap(priv, flow);
c620b772 1584
41c2fd94 1585 kfree(flow->attr->esw_attr->sample);
c620b772 1586 kfree(flow->attr);
d85cdccb
OG		 1587}
1588
0d9f9647 1589struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1590{
c620b772 1591 return flow->attr->counter;
b8aee822
MB		 1592}
1593
6a06c2f7 1594/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1595void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1596{
1597 struct mlx5e_tc_flow *flow, *tmp;
1598
1599 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1600 mlx5e_flow_put(priv, flow);
1601}
1602
04de7dda
RD		 1603static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1604{
1605 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1606
226f2ca3
VB		 1607 if (!flow_flag_test(flow, ESWITCH) ||
1608 !flow_flag_test(flow, DUP))
04de7dda
RD		 1609 return;
1610
1611 mutex_lock(&esw->offloads.peer_mutex);
1612 list_del(&flow->peer);
1613 mutex_unlock(&esw->offloads.peer_mutex);
1614
226f2ca3 1615 flow_flag_clear(flow, DUP);
04de7dda 1616
eb252c3a
RD		 1617 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1618 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1619 kfree(flow->peer_flow);
1620 }
1621
04de7dda
RD		 1622 flow->peer_flow = NULL;
1623}
1624
1625static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1626{
1627 struct mlx5_core_dev *dev = flow->priv->mdev;
1628 struct mlx5_devcom *devcom = dev->priv.devcom;
1629 struct mlx5_eswitch *peer_esw;
1630
1631 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1632 if (!peer_esw)
1633 return;
1634
1635 __mlx5e_tc_del_fdb_peer_flow(flow);
1636 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1637}
1638
e8f887ac 1639static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1640 struct mlx5e_tc_flow *flow)
e8f887ac 1641{
226f2ca3 1642 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1643 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1644 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1645 } else {
d85cdccb 1646 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1647 }
e8f887ac
AV		 1648}
1649
0a7fcb78
PB		 1650static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1651{
1652 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1653 struct flow_action *flow_action = &rule->action;
1654 const struct flow_action_entry *act;
1655 int i;
1656
1657 flow_action_for_each(i, act, flow_action) {
1658 switch (act->id) {
1659 case FLOW_ACTION_GOTO:
1660 return true;
1661 default:
1662 continue;
1663 }
1664 }
1665
1666 return false;
1667}
bbd00f7e 1668
0a7fcb78
PB		 1669static int
1670enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1671 struct flow_dissector_key_enc_opts *opts,
1672 struct netlink_ext_ack *extack,
1673 bool *dont_care)
1674{
1675 struct geneve_opt *opt;
1676 int off = 0;
1677
1678 *dont_care = true;
1679
1680 while (opts->len > off) {
1681 opt = (struct geneve_opt *)&opts->data[off];
1682
1683 if (!(*dont_care) || opt->opt_class || opt->type ||
1684 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1685 *dont_care = false;
1686
c51323ee 1687 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1688 opt->type != U8_MAX) {
0a7fcb78
PB		 1689 NL_SET_ERR_MSG(extack,
1690 "Partial match of tunnel options in chain > 0 isn't supported");
1691 netdev_warn(priv->netdev,
1692 "Partial match of tunnel options in chain > 0 isn't supported");
1693 return -EOPNOTSUPP;
1694 }
1695 }
1696
1697 off += sizeof(struct geneve_opt) + opt->length * 4;
1698 }
1699
1700 return 0;
1701}
1702
1703#define COPY_DISSECTOR(rule, diss_key, dst)\
1704({ \
1705 struct flow_rule *__rule = (rule);\
1706 typeof(dst) __dst = dst;\
1707\
1708 memcpy(__dst,\
1709 skb_flow_dissector_target(__rule->match.dissector,\
1710 diss_key,\
1711 __rule->match.key),\
1712 sizeof(*__dst));\
1713})
1714
1715static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1716 struct mlx5e_tc_flow *flow,
1717 struct flow_cls_offload *f,
1718 struct net_device *filter_dev)
bbd00f7e 1719{
f9e30088 1720 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1721 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1722 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1723 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1724 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1725 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1726 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1727 struct mlx5e_rep_priv *uplink_rpriv;
1728 struct tunnel_match_key tunnel_key;
1729 bool enc_opts_is_dont_care = true;
1730 u32 tun_id, enc_opts_id = 0;
1731 struct mlx5_eswitch *esw;
1732 u32 value, mask;
8f256622 1733 int err;
2e72eb43 1734
0a7fcb78
PB		 1735 esw = priv->mdev->priv.eswitch;
1736 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1737 uplink_priv = &uplink_rpriv->uplink_priv;
1738
1739 memset(&tunnel_key, 0, sizeof(tunnel_key));
1740 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1741 &tunnel_key.enc_control);
1742 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1743 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1744 &tunnel_key.enc_ipv4);
1745 else
1746 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1747 &tunnel_key.enc_ipv6);
1748 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1749 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1750 &tunnel_key.enc_tp);
1751 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1752 &tunnel_key.enc_key_id);
1753 tunnel_key.filter_ifindex = filter_dev->ifindex;
1754
1755 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1756 if (err)
101f4de9 1757 return err;
bbd00f7e 1758
0a7fcb78
PB		 1759 flow_rule_match_enc_opts(rule, &enc_opts_match);
1760 err = enc_opts_is_dont_care_or_full_match(priv,
1761 enc_opts_match.mask,
1762 extack,
1763 &enc_opts_is_dont_care);
1764 if (err)
1765 goto err_enc_opts;
fe1587a7 1766
0a7fcb78 1767 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1768 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1769 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1770 sizeof(*enc_opts_match.key));
1771 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1772 sizeof(*enc_opts_match.mask));
1773
0a7fcb78 1774 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1775 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1776 if (err)
1777 goto err_enc_opts;
1778 }
fe1587a7 1779
0a7fcb78
PB		 1780 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1781 mask = enc_opts_id ? TUNNEL_ID_MASK :
1782 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1783
0a7fcb78
PB		 1784 if (attr->chain) {
1785 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1786 TUNNEL_TO_REG, value, mask);
1787 } else {
1788 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1789 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1790 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1791 TUNNEL_TO_REG, value);
1792 if (err)
1793 goto err_set;
fe1587a7 1794
0a7fcb78 1795 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1796 }
bbd00f7e 1797
0a7fcb78
PB		 1798 flow->tunnel_id = value;
1799 return 0;
bcef735c 1800
0a7fcb78
PB		 1801err_set:
1802 if (enc_opts_id)
1803 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1804 enc_opts_id);
1805err_enc_opts:
1806 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1807 return err;
1808}
bcef735c 1809
0a7fcb78
PB		 1810static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1811{
1812 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1813 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1814 struct mlx5_rep_uplink_priv *uplink_priv;
1815 struct mlx5e_rep_priv *uplink_rpriv;
1816 struct mlx5_eswitch *esw;
bcef735c 1817
0a7fcb78
PB		 1818 esw = flow->priv->mdev->priv.eswitch;
1819 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1820 uplink_priv = &uplink_rpriv->uplink_priv;
1821
1822 if (tun_id)
1823 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1824 if (enc_opts_id)
1825 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1826 enc_opts_id);
1827}
e98bedf5 1828
4c3844d9
PB		 1829u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1830{
1831 return flow->tunnel_id;
1832}
1833
fca53304
EB		 1834void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1835 struct flow_match_basic *match, bool outer,
1836 void *headers_c, void *headers_v)
1837{
1838 bool ip_version_cap;
1839
1840 ip_version_cap = outer ?
1841 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1842 ft_field_support.outer_ip_version) :
1843 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1844 ft_field_support.inner_ip_version);
1845
1846 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1847 (match->key->n_proto == htons(ETH_P_IP) ||
1848 match->key->n_proto == htons(ETH_P_IPV6))) {
1849 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1850 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1851 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1852 } else {
1853 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1854 ntohs(match->mask->n_proto));
1855 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1856 ntohs(match->key->n_proto));
1857 }
4a5d5d73
EB		 1858}
1859
0d9f9647 1860u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1861{
1862 void *headers_v;
1863 u16 ethertype;
1864 u8 ip_version;
1865
1866 if (outer)
1867 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1868 else
1869 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1870
1871 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1872 /* Return ip_version converted from ethertype anyway */
1873 if (!ip_version) {
1874 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1875 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1876 ip_version = 4;
1877 else if (ethertype == ETH_P_IPV6)
1878 ip_version = 6;
1879 }
1880 return ip_version;
1881}
1882
bbd00f7e 1883static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1884 struct mlx5e_tc_flow *flow,
bbd00f7e 1885 struct mlx5_flow_spec *spec,
f9e30088 1886 struct flow_cls_offload *f,
0a7fcb78
PB		 1887 struct net_device *filter_dev,
1888 u8 *match_level,
1889 bool *match_inner)
bbd00f7e 1890{
a508728a 1891 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1892 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1893 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1894 bool needs_mapping, sets_mapping;
8f256622 1895 int err;
2e72eb43 1896
0a7fcb78
PB		 1897 if (!mlx5e_is_eswitch_flow(flow))
1898 return -EOPNOTSUPP;
1899
c620b772
AL		 1900 needs_mapping = !!flow->attr->chain;
1901 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 1902 *match_inner = !needs_mapping;
1903
1904 if ((needs_mapping || sets_mapping) &&
636bb968 1905 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1906 NL_SET_ERR_MSG(extack,
636bb968 1907 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1908 netdev_warn(priv->netdev,
636bb968 1909 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1910 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1911 }
1912
c620b772 1913 if (!flow->attr->chain) {
0a7fcb78
PB		 1914 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1915 match_level);
1916 if (err) {
e98bedf5 1917 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1918 "Failed to parse tunnel attributes");
1919 netdev_warn(priv->netdev,
1920 "Failed to parse tunnel attributes");
1921 return err;
e98bedf5
EB		 1922 }
1923
14e6b038
EC		 1924 /* With mpls over udp we decapsulate using packet reformat
1925 * object
1926 */
1927 if (!netif_is_bareudp(filter_dev))
c620b772 1928 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1929 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1930 if (err)
1931 return err;
1932 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1933 struct mlx5_flow_spec *tmp_spec;
1934
1935 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1936 if (!tmp_spec) {
1937 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1938 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1939 return -ENOMEM;
1940 }
1941 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1942
1943 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1944 if (err) {
1945 kvfree(tmp_spec);
1946 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1947 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1948 return err;
1949 }
1950 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1951 kvfree(tmp_spec);
1952 if (err)
1953 return err;
bcef735c
OG		 1954 }
1955
0a7fcb78
PB		 1956 if (!needs_mapping && !sets_mapping)
1957 return 0;
bbd00f7e 1958
0a7fcb78 1959 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1960}
bbd00f7e 1961
0a7fcb78 1962static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1963{
0a7fcb78
PB		 1964 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1965 inner_headers);
bbd00f7e
HHZ		 1966}
1967
0a7fcb78 1968static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1969{
0a7fcb78
PB		 1970 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1971 inner_headers);
1972}
1973
1974static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1975{
1976 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1977 outer_headers);
1978}
1979
1980static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1981{
1982 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1983 outer_headers);
8377629e
EB		 1984}
1985
1986static void *get_match_headers_value(u32 flags,
1987 struct mlx5_flow_spec *spec)
1988{
1989 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1990 get_match_inner_headers_value(spec) :
1991 get_match_outer_headers_value(spec);
1992}
1993
1994static void *get_match_headers_criteria(u32 flags,
1995 struct mlx5_flow_spec *spec)
1996{
1997 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1998 get_match_inner_headers_criteria(spec) :
1999 get_match_outer_headers_criteria(spec);
8377629e
EB		 2000}
2001
6d65bc64 2002static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2003 struct flow_cls_offload *f)
2004{
2005 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2006 struct netlink_ext_ack *extack = f->common.extack;
2007 struct net_device *ingress_dev;
2008 struct flow_match_meta match;
2009
2010 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2011 return 0;
2012
2013 flow_rule_match_meta(rule, &match);
e3e0f9b2 2014 if (!match.mask->ingress_ifindex)
2015 return 0;
2016
6d65bc64 2017 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2018 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2019 return -EOPNOTSUPP;
6d65bc64 2020 }
2021
2022 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2023 match.key->ingress_ifindex);
2024 if (!ingress_dev) {
2025 NL_SET_ERR_MSG_MOD(extack,
2026 "Can't find the ingress port to match on");
a683012a 2027 return -ENOENT;
6d65bc64 2028 }
2029
2030 if (ingress_dev != filter_dev) {
2031 NL_SET_ERR_MSG_MOD(extack,
2032 "Can't match on the ingress filter port");
a683012a 2033 return -EOPNOTSUPP;
6d65bc64 2034 }
2035
2036 return 0;
2037}
2038
72046a91
EC		 2039static bool skip_key_basic(struct net_device *filter_dev,
2040 struct flow_cls_offload *f)
2041{
2042 /* When doing mpls over udp decap, the user needs to provide
2043 * MPLS_UC as the protocol in order to be able to match on mpls
2044 * label fields. However, the actual ethertype is IP so we want to
2045 * avoid matching on this, otherwise we'll fail the match.
2046 */
2047 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2048 return true;
2049
2050 return false;
2051}
2052
de0af0bf 2053static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2054 struct mlx5e_tc_flow *flow,
de0af0bf 2055 struct mlx5_flow_spec *spec,
f9e30088 2056 struct flow_cls_offload *f,
54c177ca 2057 struct net_device *filter_dev,
93b3586e 2058 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2059{
e98bedf5 2060 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2061 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2062 outer_headers);
2063 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2064 outer_headers);
699e96dd
JL		 2065 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2066 misc_parameters);
2067 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2068 misc_parameters);
a3222a2d
MD		 2069 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2070 misc_parameters_3);
2071 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2072 misc_parameters_3);
f9e30088 2073 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2074 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2075 enum fs_flow_table_type fs_type;
e3a2b7ed
AV		 2076 u16 addr_type = 0;
2077 u8 ip_proto = 0;
93b3586e 2078 u8 *match_level;
6d65bc64 2079 int err;
e3a2b7ed 2080
afe93f71 2081 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2082 match_level = outer_match_level;
de0af0bf 2083
8f256622 2084 if (dissector->used_keys &
3d144578
VB		 2085 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2086 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2087 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2088 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2089 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2090 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2091 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2092 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2093 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2094 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2095 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2096 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2097 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2098 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2099 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2100 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2101 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2102 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2103 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2104 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2105 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2106 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2107 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2108 dissector->used_keys);
e3a2b7ed
AV		 2109 return -EOPNOTSUPP;
2110 }
2111
075973c7 2112 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2113 bool match_inner = false;
bbd00f7e 2114
0a7fcb78
PB		 2115 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2116 outer_match_level, &match_inner);
2117 if (err)
2118 return err;
2119
2120 if (match_inner) {
2121 /* header pointers should point to the inner headers
2122 * if the packet was decapsulated already.
2123 * outer headers are set by parse_tunnel_attr.
2124 */
2125 match_level = inner_match_level;
2126 headers_c = get_match_inner_headers_criteria(spec);
2127 headers_v = get_match_inner_headers_value(spec);
2128 }
bbd00f7e
HHZ		 2129 }
2130
6d65bc64 2131 err = mlx5e_flower_parse_meta(filter_dev, f);
2132 if (err)
2133 return err;
2134
72046a91
EC		 2135 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2136 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2137 struct flow_match_basic match;
2138
2139 flow_rule_match_basic(rule, &match);
fca53304
EB		 2140 mlx5e_tc_set_ethertype(priv->mdev, &match,
2141 match_level == outer_match_level,
2142 headers_c, headers_v);
e3a2b7ed 2143
8f256622 2144 if (match.mask->n_proto)
d708f902 2145 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2146 }
35a605db
EB		 2147 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2148 is_vlan_dev(filter_dev)) {
2149 struct flow_dissector_key_vlan filter_dev_mask;
2150 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2151 struct flow_match_vlan match;
2152
35a605db
EB		 2153 if (is_vlan_dev(filter_dev)) {
2154 match.key = &filter_dev_key;
2155 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2156 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2157 match.key->vlan_priority = 0;
2158 match.mask = &filter_dev_mask;
2159 memset(match.mask, 0xff, sizeof(*match.mask));
2160 match.mask->vlan_priority = 0;
2161 } else {
2162 flow_rule_match_vlan(rule, &match);
2163 }
8f256622
PNA		 2164 if (match.mask->vlan_id ||
2165 match.mask->vlan_priority ||
2166 match.mask->vlan_tpid) {
2167 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2168 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2169 svlan_tag, 1);
2170 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2171 svlan_tag, 1);
2172 } else {
2173 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2174 cvlan_tag, 1);
2175 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2176 cvlan_tag, 1);
2177 }
095b6cfd 2178
8f256622
PNA		 2179 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2180 match.mask->vlan_id);
2181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2182 match.key->vlan_id);
358d79a4 2183
8f256622
PNA		 2184 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2185 match.mask->vlan_priority);
2186 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2187 match.key->vlan_priority);
54782900 2188
d708f902 2189 *match_level = MLX5_MATCH_L2;
54782900 2190 }
d3a80bb5 2191 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2192 /* cvlan_tag enabled in match criteria and
2193 * disabled in match value means both S & C tags
2194 * don't exist (untagged of both)
2195 */
cee26487 2196 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2197 *match_level = MLX5_MATCH_L2;
54782900
OG		 2198 }
2199
8f256622
PNA		 2200 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2201 struct flow_match_vlan match;
2202
12d5cbf8 2203 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2204 if (match.mask->vlan_id ||
2205 match.mask->vlan_priority ||
2206 match.mask->vlan_tpid) {
afe93f71
RD		 2207 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2208 fs_type)) {
2209 NL_SET_ERR_MSG_MOD(extack,
2210 "Matching on CVLAN is not supported");
2211 return -EOPNOTSUPP;
2212 }
2213
8f256622 2214 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2215 MLX5_SET(fte_match_set_misc, misc_c,
2216 outer_second_svlan_tag, 1);
2217 MLX5_SET(fte_match_set_misc, misc_v,
2218 outer_second_svlan_tag, 1);
2219 } else {
2220 MLX5_SET(fte_match_set_misc, misc_c,
2221 outer_second_cvlan_tag, 1);
2222 MLX5_SET(fte_match_set_misc, misc_v,
2223 outer_second_cvlan_tag, 1);
2224 }
2225
2226 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2227 match.mask->vlan_id);
699e96dd 2228 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2229 match.key->vlan_id);
699e96dd 2230 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2231 match.mask->vlan_priority);
699e96dd 2232 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2233 match.key->vlan_priority);
699e96dd
JL		 2234
2235 *match_level = MLX5_MATCH_L2;
0faddfe6 2236 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2237 }
2238 }
2239
8f256622
PNA		 2240 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2241 struct flow_match_eth_addrs match;
54782900 2242
8f256622 2243 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2244 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2245 dmac_47_16),
8f256622 2246 match.mask->dst);
d3a80bb5
OG		 2247 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2248 dmac_47_16),
8f256622 2249 match.key->dst);
d3a80bb5
OG		 2250
2251 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2252 smac_47_16),
8f256622 2253 match.mask->src);
d3a80bb5
OG		 2254 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2255 smac_47_16),
8f256622 2256 match.key->src);
d3a80bb5 2257
8f256622
PNA		 2258 if (!is_zero_ether_addr(match.mask->src) ||
2259 !is_zero_ether_addr(match.mask->dst))
d708f902 2260 *match_level = MLX5_MATCH_L2;
54782900
OG		 2261 }
2262
8f256622
PNA		 2263 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2264 struct flow_match_control match;
54782900 2265
8f256622
PNA		 2266 flow_rule_match_control(rule, &match);
2267 addr_type = match.key->addr_type;
54782900
OG		 2268
2269 /* the HW doesn't support frag first/later */
8f256622 2270 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2271 return -EOPNOTSUPP;
2272
8f256622 2273 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2274 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2275 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2276 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2277
2278 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2279 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2280 *match_level = MLX5_MATCH_L2;
54782900
OG		 2281 /* *** L2 attributes parsing up to here *** */
2282 else
83621b7d 2283 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2284 }
2285 }
2286
8f256622
PNA		 2287 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2288 struct flow_match_basic match;
2289
2290 flow_rule_match_basic(rule, &match);
2291 ip_proto = match.key->ip_proto;
54782900
OG		 2292
2293 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2294 match.mask->ip_proto);
54782900 2295 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2296 match.key->ip_proto);
54782900 2297
8f256622 2298 if (match.mask->ip_proto)
d708f902 2299 *match_level = MLX5_MATCH_L3;
54782900
OG		 2300 }
2301
e3a2b7ed 2302 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2303 struct flow_match_ipv4_addrs match;
e3a2b7ed 2304
8f256622 2305 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2306 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2307 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2308 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2309 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2310 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2311 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2312 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2313 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2314 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2315 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2316 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2317 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2318
8f256622 2319 if (match.mask->src || match.mask->dst)
d708f902 2320 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2321 }
2322
2323 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2324 struct flow_match_ipv6_addrs match;
e3a2b7ed 2325
8f256622 2326 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2327 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2328 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2329 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2330 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2331 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2332 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2333
2334 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2335 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2336 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2337 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2338 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2339 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2340
8f256622
PNA		 2341 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2342 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2343 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2344 }
2345
8f256622
PNA		 2346 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2347 struct flow_match_ip match;
1f97a526 2348
8f256622
PNA		 2349 flow_rule_match_ip(rule, &match);
2350 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2351 match.mask->tos & 0x3);
2352 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2353 match.key->tos & 0x3);
1f97a526 2354
8f256622
PNA		 2355 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2356 match.mask->tos >> 2);
2357 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2358 match.key->tos >> 2);
1f97a526 2359
8f256622
PNA		 2360 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2361 match.mask->ttl);
2362 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2363 match.key->ttl);
1f97a526 2364
8f256622 2365 if (match.mask->ttl &&
a8ade55f 2366 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2367 ft_field_support.outer_ipv4_ttl)) {
2368 NL_SET_ERR_MSG_MOD(extack,
2369 "Matching on TTL is not supported");
1f97a526 2370 return -EOPNOTSUPP;
e98bedf5 2371 }
a8ade55f 2372
8f256622 2373 if (match.mask->tos || match.mask->ttl)
d708f902 2374 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2375 }
2376
54782900
OG		 2377 /* *** L3 attributes parsing up to here *** */
2378
8f256622
PNA		 2379 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2380 struct flow_match_ports match;
2381
2382 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2383 switch (ip_proto) {
2384 case IPPROTO_TCP:
2385 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2386 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2387 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2388 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2389
2390 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2391 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2392 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2393 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2394 break;
2395
2396 case IPPROTO_UDP:
2397 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2398 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2399 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2400 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2401
2402 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2403 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2404 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2405 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2406 break;
2407 default:
e98bedf5
EB		 2408 NL_SET_ERR_MSG_MOD(extack,
2409 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2410 netdev_err(priv->netdev,
2411 "Only UDP and TCP transport are supported\n");
2412 return -EINVAL;
2413 }
de0af0bf 2414
8f256622 2415 if (match.mask->src || match.mask->dst)
d708f902 2416 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2417 }
2418
8f256622
PNA		 2419 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2420 struct flow_match_tcp match;
e77834ec 2421
8f256622 2422 flow_rule_match_tcp(rule, &match);
e77834ec 2423 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2424 ntohs(match.mask->flags));
e77834ec 2425 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2426 ntohs(match.key->flags));
e77834ec 2427
8f256622 2428 if (match.mask->flags)
d708f902 2429 *match_level = MLX5_MATCH_L4;
e77834ec 2430 }
a3222a2d
MD		 2431 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2432 struct flow_match_icmp match;
e77834ec 2433
a3222a2d
MD		 2434 flow_rule_match_icmp(rule, &match);
2435 switch (ip_proto) {
2436 case IPPROTO_ICMP:
2437 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2438 MLX5_FLEX_PROTO_ICMP))
2439 return -EOPNOTSUPP;
2440 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2441 match.mask->type);
2442 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2443 match.key->type);
2444 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2445 match.mask->code);
2446 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2447 match.key->code);
2448 break;
2449 case IPPROTO_ICMPV6:
2450 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2451 MLX5_FLEX_PROTO_ICMPV6))
2452 return -EOPNOTSUPP;
2453 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2454 match.mask->type);
2455 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2456 match.key->type);
2457 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2458 match.mask->code);
2459 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2460 match.key->code);
2461 break;
2462 default:
2463 NL_SET_ERR_MSG_MOD(extack,
2464 "Code and type matching only with ICMP and ICMPv6");
2465 netdev_err(priv->netdev,
2466 "Code and type matching only with ICMP and ICMPv6\n");
2467 return -EINVAL;
2468 }
2469 if (match.mask->code || match.mask->type) {
2470 *match_level = MLX5_MATCH_L4;
2471 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2472 }
2473 }
7d6c86e3
AH		 2474 /* Currenlty supported only for MPLS over UDP */
2475 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2476 !netif_is_bareudp(filter_dev)) {
2477 NL_SET_ERR_MSG_MOD(extack,
2478 "Matching on MPLS is supported only for MPLS over UDP");
2479 netdev_err(priv->netdev,
2480 "Matching on MPLS is supported only for MPLS over UDP\n");
2481 return -EOPNOTSUPP;
2482 }
2483
e3a2b7ed
AV		 2484 return 0;
2485}
2486
de0af0bf 2487static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2488 struct mlx5e_tc_flow *flow,
de0af0bf 2489 struct mlx5_flow_spec *spec,
f9e30088 2490 struct flow_cls_offload *f,
54c177ca 2491 struct net_device *filter_dev)
de0af0bf 2492{
93b3586e 2493 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2494 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2495 struct mlx5_core_dev *dev = priv->mdev;
2496 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2497 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2498 struct mlx5_eswitch_rep *rep;
226f2ca3 2499 bool is_eswitch_flow;
de0af0bf
RD		 2500 int err;
2501
93b3586e
HN		 2502 inner_match_level = MLX5_MATCH_NONE;
2503 outer_match_level = MLX5_MATCH_NONE;
2504
0a7fcb78
PB		 2505 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2506 &inner_match_level, &outer_match_level);
93b3586e
HN		 2507 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2508 outer_match_level : inner_match_level;
de0af0bf 2509
226f2ca3
VB		 2510 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2511 if (!err && is_eswitch_flow) {
1d447a39 2512 rep = rpriv->rep;
b05af6aa 2513 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2514 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2515 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2516 NL_SET_ERR_MSG_MOD(extack,
2517 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2518 netdev_warn(priv->netdev,
2519 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2520 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2521 return -EOPNOTSUPP;
2522 }
2523 }
2524
c620b772
AL		 2525 flow->attr->inner_match_level = inner_match_level;
2526 flow->attr->outer_match_level = outer_match_level;
2527
38aa51c1 2528
de0af0bf
RD		 2529 return err;
2530}
2531
d79b6df6
OG		 2532struct pedit_headers {
2533 struct ethhdr eth;
0eb69bb9 2534 struct vlan_hdr vlan;
d79b6df6
OG		 2535 struct iphdr ip4;
2536 struct ipv6hdr ip6;
2537 struct tcphdr tcp;
2538 struct udphdr udp;
2539};
2540
c500c86b
PNA		 2541struct pedit_headers_action {
2542 struct pedit_headers vals;
2543 struct pedit_headers masks;
2544 u32 pedits;
2545};
2546
d79b6df6 2547static int pedit_header_offsets[] = {
73867881
PNA		 2548 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2549 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2550 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2551 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2552 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2553};
2554
2555#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2556
2557static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2558 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2559{
2560 u32 *curr_pmask, *curr_pval;
2561
c500c86b
PNA		 2562 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2563 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2564
2565 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2566 goto out_err;
2567
2568 *curr_pmask |= mask;
2569 *curr_pval |= (val & mask);
2570
2571 return 0;
2572
2573out_err:
2574 return -EOPNOTSUPP;
2575}
2576
2577struct mlx5_fields {
2578 u8 field;
88f30bbc
DL		 2579 u8 field_bsize;
2580 u32 field_mask;
d79b6df6 2581 u32 offset;
27c11b6b 2582 u32 match_offset;
d79b6df6
OG		 2583};
2584
88f30bbc
DL		 2585#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2586 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2587 offsetof(struct pedit_headers, field) + (off), \
2588 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2589
2ef86872
EB		 2590/* masked values are the same and there are no rewrites that do not have a
2591 * match.
2592 */
2593#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2594 type matchmaskx = *(type *)(matchmaskp); \
2595 type matchvalx = *(type *)(matchvalp); \
2596 type maskx = *(type *)(maskp); \
2597 type valx = *(type *)(valp); \
2598 \
2599 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2600 matchmaskx)); \
2601})
2602
27c11b6b 2603static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2604 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2605{
2606 bool same = false;
2607
88f30bbc
DL		 2608 switch (bsize) {
2609 case 8:
2ef86872 2610 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2611 break;
88f30bbc 2612 case 16:
2ef86872 2613 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2614 break;
88f30bbc 2615 case 32:
2ef86872 2616 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2617 break;
2618 }
2619
2620 return same;
2621}
a8e4f0c4 2622
d79b6df6 2623static struct mlx5_fields fields[] = {
88f30bbc
DL		 2624 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2625 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2626 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2627 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2628 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2629 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2630
ab9341b5 2631 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2632 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2633 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2634 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2635
2636 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2637 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2638 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2639 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2640 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2641 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2642 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2643 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2644 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2645 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2646 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2647 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2648 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2649 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2650 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2651 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2652 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2653 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2654
88f30bbc
DL		 2655 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2656 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2657 /* in linux iphdr tcp_flags is 8 bits long */
2658 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2659
88f30bbc
DL		 2660 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2661 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2662};
2663
82198d8b
MD		 2664static unsigned long mask_to_le(unsigned long mask, int size)
2665{
2666 __be32 mask_be32;
2667 __be16 mask_be16;
2668
2669 if (size == 32) {
2670 mask_be32 = (__force __be32)(mask);
2671 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2672 } else if (size == 16) {
2673 mask_be32 = (__force __be32)(mask);
2674 mask_be16 = *(__be16 *)&mask_be32;
2675 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2676 }
2677
2678 return mask;
2679}
6ae4a6a5
PB		 2680static int offload_pedit_fields(struct mlx5e_priv *priv,
2681 int namespace,
2682 struct pedit_headers_action *hdrs,
e98bedf5 2683 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2684 u32 *action_flags,
e98bedf5 2685 struct netlink_ext_ack *extack)
d79b6df6
OG		 2686{
2687 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2688 int i, action_size, first, last, next_z;
88f30bbc
DL		 2689 void *headers_c, *headers_v, *action, *vals_p;
2690 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2691 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2692 struct mlx5_fields *f;
82198d8b 2693 unsigned long mask, field_mask;
6ae4a6a5 2694 int err;
88f30bbc
DL		 2695 u8 cmd;
2696
6ae4a6a5 2697 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2698 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2699 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2700
73867881
PNA		 2701 set_masks = &hdrs[0].masks;
2702 add_masks = &hdrs[1].masks;
2703 set_vals = &hdrs[0].vals;
2704 add_vals = &hdrs[1].vals;
d79b6df6 2705
d65dbedf 2706 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2707
2708 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2709 bool skip;
2710
d79b6df6
OG		 2711 f = &fields[i];
2712 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2713 s_mask = 0;
2714 a_mask = 0;
d79b6df6
OG		 2715
2716 s_masks_p = (void *)set_masks + f->offset;
2717 a_masks_p = (void *)add_masks + f->offset;
2718
88f30bbc
DL		 2719 s_mask = *s_masks_p & f->field_mask;
2720 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2721
2722 if (!s_mask && !a_mask) /* nothing to offload here */
2723 continue;
2724
2725 if (s_mask && a_mask) {
e98bedf5
EB		 2726 NL_SET_ERR_MSG_MOD(extack,
2727 "can't set and add to the same HW field");
d79b6df6
OG		 2728 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2729 return -EOPNOTSUPP;
2730 }
2731
27c11b6b 2732 skip = false;
d79b6df6 2733 if (s_mask) {
27c11b6b
EB		 2734 void *match_mask = headers_c + f->match_offset;
2735 void *match_val = headers_v + f->match_offset;
2736
d79b6df6
OG		 2737 cmd = MLX5_ACTION_TYPE_SET;
2738 mask = s_mask;
2739 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2740 /* don't rewrite if we have a match on the same value */
2741 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2742 match_mask, f->field_bsize))
27c11b6b 2743 skip = true;
d79b6df6 2744 /* clear to denote we consumed this field */
88f30bbc 2745 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2746 } else {
2747 cmd = MLX5_ACTION_TYPE_ADD;
2748 mask = a_mask;
2749 vals_p = (void *)add_vals + f->offset;
27c11b6b 2750 /* add 0 is no change */
88f30bbc 2751 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2752 skip = true;
d79b6df6 2753 /* clear to denote we consumed this field */
88f30bbc 2754 *a_masks_p &= ~f->field_mask;
d79b6df6 2755 }
27c11b6b
EB		 2756 if (skip)
2757 continue;
d79b6df6 2758
82198d8b 2759 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2760
88f30bbc
DL		 2761 first = find_first_bit(&mask, f->field_bsize);
2762 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2763 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2764 if (first < next_z && next_z < last) {
e98bedf5
EB		 2765 NL_SET_ERR_MSG_MOD(extack,
2766 "rewrite of few sub-fields isn't supported");
2b64beba 2767 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2768 mask);
2769 return -EOPNOTSUPP;
2770 }
2771
6ae4a6a5
PB		 2772 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2773 if (err) {
2774 NL_SET_ERR_MSG_MOD(extack,
2775 "too many pedit actions, can't offload");
2776 mlx5_core_warn(priv->mdev,
2777 "mlx5: parsed %d pedit actions, can't do more\n",
2778 mod_acts->num_actions);
2779 return err;
2780 }
2781
2782 action = mod_acts->actions +
2783 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2784 MLX5_SET(set_action_in, action, action_type, cmd);
2785 MLX5_SET(set_action_in, action, field, f->field);
2786
2787 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2788 int start;
2789
82198d8b
MD		 2790 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2791
88f30bbc 2792 /* if field is bit sized it can start not from first bit */
82198d8b 2793 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2794
2795 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2796 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2797 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2798 }
2799
88f30bbc 2800 if (f->field_bsize == 32)
2b64beba 2801 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2802 else if (f->field_bsize == 16)
2b64beba 2803 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2804 else if (f->field_bsize == 8)
2b64beba 2805 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2806
6ae4a6a5 2807 ++mod_acts->num_actions;
d79b6df6
OG		 2808 }
2809
d79b6df6
OG		 2810 return 0;
2811}
2812
2cc1cb1d
TZ		 2813static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2814 int namespace)
2815{
2816 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2817 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2818 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2819 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2820}
2821
6ae4a6a5
PB		 2822int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2823 int namespace,
2824 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2825{
6ae4a6a5
PB		 2826 int action_size, new_num_actions, max_hw_actions;
2827 size_t new_sz, old_sz;
2828 void *ret;
d79b6df6 2829
6ae4a6a5
PB		 2830 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2831 return 0;
d79b6df6 2832
d65dbedf 2833 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2834
6ae4a6a5
PB		 2835 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2836 namespace);
2837 new_num_actions = min(max_hw_actions,
2838 mod_hdr_acts->actions ?
2839 mod_hdr_acts->max_actions * 2 : 1);
2840 if (mod_hdr_acts->max_actions == new_num_actions)
2841 return -ENOSPC;
2842
2843 new_sz = action_size * new_num_actions;
2844 old_sz = mod_hdr_acts->max_actions * action_size;
2845 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2846 if (!ret)
d79b6df6
OG		 2847 return -ENOMEM;
2848
6ae4a6a5
PB		 2849 memset(ret + old_sz, 0, new_sz - old_sz);
2850 mod_hdr_acts->actions = ret;
2851 mod_hdr_acts->max_actions = new_num_actions;
2852
d79b6df6
OG		 2853 return 0;
2854}
2855
6ae4a6a5
PB		 2856void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2857{
2858 kfree(mod_hdr_acts->actions);
2859 mod_hdr_acts->actions = NULL;
2860 mod_hdr_acts->num_actions = 0;
2861 mod_hdr_acts->max_actions = 0;
2862}
2863
d79b6df6
OG		 2864static const struct pedit_headers zero_masks = {};
2865
582234b4
EC		 2866static int
2867parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2868 const struct flow_action_entry *act, int namespace,
2869 struct mlx5e_tc_flow_parse_attr *parse_attr,
2870 struct pedit_headers_action *hdrs,
2871 struct netlink_ext_ack *extack)
d79b6df6 2872{
73867881
PNA		 2873 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2874 int err = -EOPNOTSUPP;
d79b6df6 2875 u32 mask, val, offset;
73867881 2876 u8 htype;
d79b6df6 2877
73867881
PNA		 2878 htype = act->mangle.htype;
2879 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2880
73867881
PNA		 2881 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2882 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2883 goto out_err;
2884 }
d79b6df6 2885
2cc1cb1d
TZ		 2886 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2887 NL_SET_ERR_MSG_MOD(extack,
2888 "The pedit offload action is not supported");
2889 goto out_err;
2890 }
2891
73867881
PNA		 2892 mask = act->mangle.mask;
2893 val = act->mangle.val;
2894 offset = act->mangle.offset;
d79b6df6 2895
73867881
PNA		 2896 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2897 if (err)
2898 goto out_err;
c500c86b 2899
73867881 2900 hdrs[cmd].pedits++;
d79b6df6 2901
c500c86b
PNA		 2902 return 0;
2903out_err:
2904 return err;
2905}
2906
582234b4
EC		 2907static int
2908parse_pedit_to_reformat(struct mlx5e_priv *priv,
2909 const struct flow_action_entry *act,
2910 struct mlx5e_tc_flow_parse_attr *parse_attr,
2911 struct netlink_ext_ack *extack)
2912{
2913 u32 mask, val, offset;
2914 u32 *p;
2915
2916 if (act->id != FLOW_ACTION_MANGLE)
2917 return -EOPNOTSUPP;
2918
2919 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2920 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2921 return -EOPNOTSUPP;
2922 }
2923
2924 mask = ~act->mangle.mask;
2925 val = act->mangle.val;
2926 offset = act->mangle.offset;
2927 p = (u32 *)&parse_attr->eth;
2928 *(p + (offset >> 2)) |= (val & mask);
2929
2930 return 0;
2931}
2932
2933static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2934 const struct flow_action_entry *act, int namespace,
2935 struct mlx5e_tc_flow_parse_attr *parse_attr,
2936 struct pedit_headers_action *hdrs,
2937 struct mlx5e_tc_flow *flow,
2938 struct netlink_ext_ack *extack)
2939{
2940 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2941 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2942
2943 return parse_pedit_to_modify_hdr(priv, act, namespace,
2944 parse_attr, hdrs, extack);
2945}
2946
c500c86b
PNA		 2947static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2948 struct mlx5e_tc_flow_parse_attr *parse_attr,
2949 struct pedit_headers_action *hdrs,
27c11b6b 2950 u32 *action_flags,
c500c86b
PNA		 2951 struct netlink_ext_ack *extack)
2952{
2953 struct pedit_headers *cmd_masks;
2954 int err;
2955 u8 cmd;
2956
6ae4a6a5
PB		 2957 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2958 action_flags, extack);
d79b6df6
OG		 2959 if (err < 0)
2960 goto out_dealloc_parsed_actions;
2961
2962 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2963 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2964 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2965 NL_SET_ERR_MSG_MOD(extack,
2966 "attempt to offload an unsupported field");
b3a433de 2967 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2968 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2969 16, 1, cmd_masks, sizeof(zero_masks), true);
2970 err = -EOPNOTSUPP;
2971 goto out_dealloc_parsed_actions;
2972 }
2973 }
2974
2975 return 0;
2976
2977out_dealloc_parsed_actions:
6ae4a6a5 2978 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2979 return err;
2980}
2981
e98bedf5
EB		 2982static bool csum_offload_supported(struct mlx5e_priv *priv,
2983 u32 action,
2984 u32 update_flags,
2985 struct netlink_ext_ack *extack)
26c02749
OG		 2986{
2987 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2988 TCA_CSUM_UPDATE_FLAG_UDP;
2989
2990 /* The HW recalcs checksums only if re-writing headers */
2991 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2992 NL_SET_ERR_MSG_MOD(extack,
2993 "TC csum action is only offloaded with pedit");
26c02749
OG		 2994 netdev_warn(priv->netdev,
2995 "TC csum action is only offloaded with pedit\n");
2996 return false;
2997 }
2998
2999 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3000 NL_SET_ERR_MSG_MOD(extack,
3001 "can't offload TC csum action for some header/s");
26c02749
OG		 3002 netdev_warn(priv->netdev,
3003 "can't offload TC csum action for some header/s - flags %#x\n",
3004 update_flags);
3005 return false;
3006 }
3007
3008 return true;
3009}
3010
8998576b
DL		 3011struct ip_ttl_word {
3012 __u8 ttl;
3013 __u8 protocol;
3014 __sum16 check;
3015};
3016
3017struct ipv6_hoplimit_word {
3018 __be16 payload_len;
3019 __u8 nexthdr;
3020 __u8 hop_limit;
3021};
3022
4c3844d9
PB		 3023static int is_action_keys_supported(const struct flow_action_entry *act,
3024 bool ct_flow, bool *modify_ip_header,
7e36feeb 3025 bool *modify_tuple,
4c3844d9 3026 struct netlink_ext_ack *extack)
8998576b
DL		 3027{
3028 u32 mask, offset;
3029 u8 htype;
3030
3031 htype = act->mangle.htype;
3032 offset = act->mangle.offset;
3033 mask = ~act->mangle.mask;
3034 /* For IPv4 & IPv6 header check 4 byte word,
3035 * to determine that modified fields
3036 * are NOT ttl & hop_limit only.
3037 */
3038 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3039 struct ip_ttl_word *ttl_word =
3040 (struct ip_ttl_word *)&mask;
3041
3042 if (offset != offsetof(struct iphdr, ttl) ||
3043 ttl_word->protocol ||
3044 ttl_word->check) {
4c3844d9
PB		 3045 *modify_ip_header = true;
3046 }
3047
7e36feeb
PB		 3048 if (offset >= offsetof(struct iphdr, saddr))
3049 *modify_tuple = true;
3050
3051 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3052 NL_SET_ERR_MSG_MOD(extack,
3053 "can't offload re-write of ipv4 address with action ct");
3054 return -EOPNOTSUPP;
8998576b
DL		 3055 }
3056 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3057 struct ipv6_hoplimit_word *hoplimit_word =
3058 (struct ipv6_hoplimit_word *)&mask;
3059
3060 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3061 hoplimit_word->payload_len ||
3062 hoplimit_word->nexthdr) {
4c3844d9
PB		 3063 *modify_ip_header = true;
3064 }
3065
7e36feeb
PB		 3066 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3067 *modify_tuple = true;
3068
3069 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3070 NL_SET_ERR_MSG_MOD(extack,
3071 "can't offload re-write of ipv6 address with action ct");
3072 return -EOPNOTSUPP;
8998576b 3073 }
7e36feeb
PB		 3074 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3075 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3076 *modify_tuple = true;
3077 if (ct_flow) {
3078 NL_SET_ERR_MSG_MOD(extack,
3079 "can't offload re-write of transport header ports with action ct");
3080 return -EOPNOTSUPP;
3081 }
8998576b 3082 }
4c3844d9
PB		 3083
3084 return 0;
8998576b
DL		 3085}
3086
96b5b458
DC		 3087static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3088 bool ct_flow, struct netlink_ext_ack *extack,
3089 struct mlx5e_priv *priv,
3090 struct mlx5_flow_spec *spec)
3091{
3092 if (!modify_tuple || ct_clear)
3093 return true;
3094
3095 if (ct_flow) {
3096 NL_SET_ERR_MSG_MOD(extack,
3097 "can't offload tuple modification with non-clear ct()");
3098 netdev_info(priv->netdev,
3099 "can't offload tuple modification with non-clear ct()");
3100 return false;
3101 }
3102
3103 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3104 * (or after clear action), as otherwise, since the tuple is changed,
3105 * we can't restore ct state
3106 */
3107 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3108 NL_SET_ERR_MSG_MOD(extack,
3109 "can't offload tuple modification with ct matches and no ct(clear) action");
3110 netdev_info(priv->netdev,
3111 "can't offload tuple modification with ct matches and no ct(clear) action");
3112 return false;
3113 }
3114
3115 return true;
3116}
3117
3d486ec4
OS		 3118static bool modify_header_match_supported(struct mlx5e_priv *priv,
3119 struct mlx5_flow_spec *spec,
73867881 3120 struct flow_action *flow_action,
4c3844d9 3121 u32 actions, bool ct_flow,
7e36feeb 3122 bool ct_clear,
e98bedf5 3123 struct netlink_ext_ack *extack)
bdd66ac0 3124{
73867881 3125 const struct flow_action_entry *act;
7e36feeb 3126 bool modify_ip_header, modify_tuple;
fca53304 3127 void *headers_c;
bdd66ac0
OG		 3128 void *headers_v;
3129 u16 ethertype;
8998576b 3130 u8 ip_proto;
4c3844d9 3131 int i, err;
bdd66ac0 3132
fca53304 3133 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3134 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3135 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3136
3137 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3138 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3139 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3140 goto out_ok;
3141
3142 modify_ip_header = false;
7e36feeb 3143 modify_tuple = false;
73867881
PNA		 3144 flow_action_for_each(i, act, flow_action) {
3145 if (act->id != FLOW_ACTION_MANGLE &&
3146 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3147 continue;
3148
4c3844d9 3149 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3150 &modify_ip_header,
3151 &modify_tuple, extack);
4c3844d9
PB		 3152 if (err)
3153 return err;
bdd66ac0
OG		 3154 }
3155
96b5b458
DC		 3156 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3157 priv, spec))
7e36feeb 3158 return false;
7e36feeb 3159
bdd66ac0 3160 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3161 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3162 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3163 NL_SET_ERR_MSG_MOD(extack,
3164 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3165 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3166 ip_proto);
bdd66ac0
OG		 3167 return false;
3168 }
3169
3170out_ok:
3171 return true;
3172}
3173
3174static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3175 struct flow_action *flow_action,
bdd66ac0 3176 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3177 struct mlx5e_tc_flow *flow,
3178 struct netlink_ext_ack *extack)
bdd66ac0 3179{
a7c119bd 3180 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3181 u32 actions;
3182
c620b772
AL		 3183 ct_clear = flow->attr->ct_attr.ct_action &
3184 TCA_CT_ACT_CLEAR;
3185 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3186 actions = flow->attr->action;
3187
4c3844d9 3188 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3189 if (flow->attr->esw_attr->split_count && ct_flow &&
3190 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3191 /* All registers used by ct are cleared when using
3192 * split rules.
3193 */
3194 NL_SET_ERR_MSG_MOD(extack,
3195 "Can't offload mirroring with action ct");
49397b80 3196 return false;
4c3844d9 3197 }
4c3844d9 3198 }
bdd66ac0
OG		 3199
3200 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3201 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3202 flow_action, actions,
7e36feeb
PB		 3203 ct_flow, ct_clear,
3204 extack);
bdd66ac0
OG		 3205
3206 return true;
3207}
3208
32134847
MD		 3209static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3210{
3211 return priv->mdev == peer_priv->mdev;
3212}
3213
5c65c564
OG		 3214static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3215{
3216 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3217 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3218
3219 fmdev = priv->mdev;
3220 pmdev = peer_priv->mdev;
3221
59c9d35e
AH		 3222 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3223 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3224
816f6706 3225 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3226}
3227
bb569657
AL		 3228static bool same_vf_reps(struct mlx5e_priv *priv,
3229 struct net_device *out_dev)
3230{
3231 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3232 priv->netdev == out_dev;
3233}
3234
bdc837ee
EB		 3235static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3236 const struct flow_action_entry *act,
3237 struct mlx5e_tc_flow_parse_attr *parse_attr,
3238 struct pedit_headers_action *hdrs,
3239 u32 *action, struct netlink_ext_ack *extack)
3240{
3241 u16 mask16 = VLAN_VID_MASK;
3242 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3243 const struct flow_action_entry pedit_act = {
3244 .id = FLOW_ACTION_MANGLE,
3245 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3246 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3247 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3248 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3249 };
6fca9d1e 3250 u8 match_prio_mask, match_prio_val;
bf2f3bca 3251 void *headers_c, *headers_v;
bdc837ee
EB		 3252 int err;
3253
bf2f3bca
EB		 3254 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3255 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3256
3257 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3258 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3259 NL_SET_ERR_MSG_MOD(extack,
3260 "VLAN rewrite action must have VLAN protocol match");
3261 return -EOPNOTSUPP;
3262 }
3263
6fca9d1e
EB		 3264 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3265 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3266 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3267 NL_SET_ERR_MSG_MOD(extack,
3268 "Changing VLAN prio is not supported");
bdc837ee
EB		 3269 return -EOPNOTSUPP;
3270 }
3271
582234b4 3272 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3273 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3274
3275 return err;
3276}
3277
0bac1194
EB		 3278static int
3279add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3280 struct mlx5e_tc_flow_parse_attr *parse_attr,
3281 struct pedit_headers_action *hdrs,
3282 u32 *action, struct netlink_ext_ack *extack)
3283{
3284 const struct flow_action_entry prio_tag_act = {
3285 .vlan.vid = 0,
3286 .vlan.prio =
3287 MLX5_GET(fte_match_set_lyr_2_4,
3288 get_match_headers_value(*action,
3289 &parse_attr->spec),
3290 first_prio) &
3291 MLX5_GET(fte_match_set_lyr_2_4,
3292 get_match_headers_criteria(*action,
3293 &parse_attr->spec),
3294 first_prio),
3295 };
3296
3297 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3298 &prio_tag_act, parse_attr, hdrs, action,
3299 extack);
3300}
3301
c7569097
AL		 3302static int validate_goto_chain(struct mlx5e_priv *priv,
3303 struct mlx5e_tc_flow *flow,
3304 const struct flow_action_entry *act,
3305 u32 actions,
3306 struct netlink_ext_ack *extack)
3307{
3308 bool is_esw = mlx5e_is_eswitch_flow(flow);
3309 struct mlx5_flow_attr *attr = flow->attr;
3310 bool ft_flow = mlx5e_is_ft_flow(flow);
3311 u32 dest_chain = act->chain_index;
3312 struct mlx5_fs_chains *chains;
3313 struct mlx5_eswitch *esw;
3314 u32 reformat_and_fwd;
3315 u32 max_chain;
3316
3317 esw = priv->mdev->priv.eswitch;
3318 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3319 max_chain = mlx5_chains_get_chain_range(chains);
3320 reformat_and_fwd = is_esw ?
3321 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3322 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3323
3324 if (ft_flow) {
3325 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3326 return -EOPNOTSUPP;
3327 }
3328
3329 if (!mlx5_chains_backwards_supported(chains) &&
3330 dest_chain <= attr->chain) {
3331 NL_SET_ERR_MSG_MOD(extack,
3332 "Goto lower numbered chain isn't supported");
3333 return -EOPNOTSUPP;
3334 }
3335
3336 if (dest_chain > max_chain) {
3337 NL_SET_ERR_MSG_MOD(extack,
3338 "Requested destination chain is out of supported range");
3339 return -EOPNOTSUPP;
3340 }
3341
3342 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3343 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3344 !reformat_and_fwd) {
3345 NL_SET_ERR_MSG_MOD(extack,
3346 "Goto chain is not allowed if action has reformat or decap");
3347 return -EOPNOTSUPP;
3348 }
3349
3350 return 0;
3351}
3352
73867881
PNA		 3353static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3354 struct flow_action *flow_action,
aa0cbbae 3355 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3356 struct mlx5e_tc_flow *flow,
3357 struct netlink_ext_ack *extack)
e3a2b7ed 3358{
c620b772 3359 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3360 struct pedit_headers_action hdrs[2] = {};
3361 const struct flow_action_entry *act;
c620b772 3362 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3363 u32 action = 0;
244cd96a 3364 int err, i;
e3a2b7ed 3365
73867881 3366 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3367 return -EINVAL;
3368
53eca1f3
JK		 3369 if (!flow_action_hw_stats_check(flow_action, extack,
3370 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3371 return -EOPNOTSUPP;
3372
c620b772
AL		 3373 nic_attr = attr->nic_attr;
3374
3375 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3376
73867881
PNA		 3377 flow_action_for_each(i, act, flow_action) {
3378 switch (act->id) {
15fc92ec
TZ		 3379 case FLOW_ACTION_ACCEPT:
3380 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3381 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3382 break;
73867881 3383 case FLOW_ACTION_DROP:
1cab1cd7 3384 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3385 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3386 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3387 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3388 break;
3389 case FLOW_ACTION_MANGLE:
3390 case FLOW_ACTION_ADD:
3391 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3392 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3393 if (err)
3394 return err;
3395
c7569097 3396 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3397 break;
bdc837ee
EB		 3398 case FLOW_ACTION_VLAN_MANGLE:
3399 err = add_vlan_rewrite_action(priv,
3400 MLX5_FLOW_NAMESPACE_KERNEL,
3401 act, parse_attr, hdrs,
3402 &action, extack);
3403 if (err)
3404 return err;
3405
3406 break;
73867881 3407 case FLOW_ACTION_CSUM:
1cab1cd7 3408 if (csum_offload_supported(priv, action,
73867881 3409 act->csum_flags,
e98bedf5 3410 extack))
73867881 3411 break;
26c02749
OG		 3412
3413 return -EOPNOTSUPP;
73867881
PNA		 3414 case FLOW_ACTION_REDIRECT: {
3415 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3416
3417 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3418 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3419 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3420 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3421 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3422 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3423 } else {
e98bedf5
EB		 3424 NL_SET_ERR_MSG_MOD(extack,
3425 "device is not on same HW, can't offload");
5c65c564
OG		 3426 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3427 peer_dev->name);
3428 return -EINVAL;
3429 }
73867881
PNA		 3430 }
3431 break;
3432 case FLOW_ACTION_MARK: {
3433 u32 mark = act->mark;
e3a2b7ed
AV		 3434
3435 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3436 NL_SET_ERR_MSG_MOD(extack,
3437 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3438 return -EINVAL;
3439 }
3440
c620b772 3441 nic_attr->flow_tag = mark;
1cab1cd7 3442 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3443 }
3444 break;
c7569097
AL		 3445 case FLOW_ACTION_GOTO:
3446 err = validate_goto_chain(priv, flow, act, action,
3447 extack);
3448 if (err)
3449 return err;
3450
3451 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3452 attr->dest_chain = act->chain_index;
3453 break;
aedd133d
AL		 3454 case FLOW_ACTION_CT:
3455 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3456 if (err)
3457 return err;
3458
3459 flow_flag_set(flow, CT);
3460 break;
73867881 3461 default:
2cc1cb1d
TZ		 3462 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3463 return -EOPNOTSUPP;
e3a2b7ed 3464 }
e3a2b7ed
AV		 3465 }
3466
c500c86b
PNA		 3467 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3468 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3469 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3470 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3471 if (err)
3472 return err;
27c11b6b
EB		 3473 /* in case all pedit actions are skipped, remove the MOD_HDR
3474 * flag.
3475 */
6ae4a6a5 3476 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3477 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3478 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3479 }
c500c86b
PNA		 3480 }
3481
1cab1cd7 3482 attr->action = action;
c7569097
AL		 3483
3484 if (attr->dest_chain) {
3485 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3486 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3487 return -EOPNOTSUPP;
3488 }
3489 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3490 }
3491
3492 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3493 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3494
73867881 3495 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3496 return -EOPNOTSUPP;
3497
e3a2b7ed
AV		 3498 return 0;
3499}
3500
32134847 3501static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3502 struct net_device *peer_netdev)
3503{
3504 struct mlx5e_priv *peer_priv;
3505
3506 peer_priv = netdev_priv(peer_netdev);
3507
3508 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3509 mlx5e_eswitch_vf_rep(priv->netdev) &&
3510 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3511 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3512}
3513
1482bd3d 3514static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3515 const struct flow_action_entry *act,
1482bd3d
JL		 3516 struct mlx5_esw_flow_attr *attr,
3517 u32 *action)
3518{
cc495188
JL		 3519 u8 vlan_idx = attr->total_vlan;
3520
3521 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3522 return -EOPNOTSUPP;
3523
73867881
PNA		 3524 switch (act->id) {
3525 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3526 if (vlan_idx) {
3527 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3528 MLX5_FS_VLAN_DEPTH))
3529 return -EOPNOTSUPP;
3530
3531 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3532 } else {
3533 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3534 }
73867881
PNA		 3535 break;
3536 case FLOW_ACTION_VLAN_PUSH:
3537 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3538 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3539 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3540 if (!attr->vlan_proto[vlan_idx])
3541 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3542
3543 if (vlan_idx) {
3544 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3545 MLX5_FS_VLAN_DEPTH))
3546 return -EOPNOTSUPP;
3547
3548 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3549 } else {
3550 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3551 (act->vlan.proto != htons(ETH_P_8021Q) ||
3552 act->vlan.prio))
cc495188
JL		 3553 return -EOPNOTSUPP;
3554
3555 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3556 }
73867881
PNA		 3557 break;
3558 default:
bdc837ee 3559 return -EINVAL;
1482bd3d
JL		 3560 }
3561
cc495188
JL		 3562 attr->total_vlan = vlan_idx + 1;
3563
1482bd3d
JL		 3564 return 0;
3565}
3566
d34eb2fc
OG		 3567static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3568 struct net_device *out_dev)
3569{
3570 struct net_device *fdb_out_dev = out_dev;
3571 struct net_device *uplink_upper;
3572
3573 rcu_read_lock();
3574 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3575 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3576 uplink_upper == out_dev) {
3577 fdb_out_dev = uplink_dev;
3578 } else if (netif_is_lag_master(out_dev)) {
3579 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3580 if (fdb_out_dev &&
3581 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3582 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3583 fdb_out_dev = NULL;
3584 }
3585 rcu_read_unlock();
3586 return fdb_out_dev;
3587}
3588
278748a9 3589static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3590 struct mlx5_flow_attr *attr,
278748a9
EB		 3591 struct net_device **out_dev,
3592 u32 *action)
3593{
3594 struct net_device *vlan_dev = *out_dev;
3595 struct flow_action_entry vlan_act = {
3596 .id = FLOW_ACTION_VLAN_PUSH,
3597 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3598 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3599 .vlan.prio = 0,
3600 };
3601 int err;
3602
c620b772 3603 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3604 if (err)
3605 return err;
3606
dca59f4a
DC		 3607 rcu_read_lock();
3608 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3609 rcu_read_unlock();
3610 if (!*out_dev)
3611 return -ENODEV;
3612
278748a9
EB		 3613 if (is_vlan_dev(*out_dev))
3614 err = add_vlan_push_action(priv, attr, out_dev, action);
3615
3616 return err;
3617}
3618
35a605db 3619static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3620 struct mlx5_flow_attr *attr,
35a605db
EB		 3621 u32 *action)
3622{
35a605db
EB		 3623 struct flow_action_entry vlan_act = {
3624 .id = FLOW_ACTION_VLAN_POP,
3625 };
70f478ca 3626 int nest_level, err = 0;
35a605db 3627
70f478ca
DL		 3628 nest_level = attr->parse_attr->filter_dev->lower_level -
3629 priv->netdev->lower_level;
35a605db 3630 while (nest_level--) {
c620b772 3631 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3632 if (err)
3633 return err;
3634 }
3635
3636 return err;
3637}
3638
32134847
MD		 3639static bool same_hw_reps(struct mlx5e_priv *priv,
3640 struct net_device *peer_netdev)
3641{
3642 struct mlx5e_priv *peer_priv;
3643
3644 peer_priv = netdev_priv(peer_netdev);
3645
3646 return mlx5e_eswitch_rep(priv->netdev) &&
3647 mlx5e_eswitch_rep(peer_netdev) &&
3648 same_hw_devs(priv, peer_priv);
3649}
3650
3651static bool is_lag_dev(struct mlx5e_priv *priv,
3652 struct net_device *peer_netdev)
3653{
3654 return ((mlx5_lag_is_sriov(priv->mdev) ||
3655 mlx5_lag_is_multipath(priv->mdev)) &&
3656 same_hw_reps(priv, peer_netdev));
3657}
3658
f6dc1264
PB		 3659bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3660 struct net_device *out_dev)
3661{
32134847
MD		 3662 if (is_merged_eswitch_vfs(priv, out_dev))
3663 return true;
3664
3665 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3666 return true;
3667
3668 return mlx5e_eswitch_rep(out_dev) &&
32134847 3669 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3670}
3671
554fe75c
DL		 3672static bool is_duplicated_output_device(struct net_device *dev,
3673 struct net_device *out_dev,
3674 int *ifindexes, int if_count,
3675 struct netlink_ext_ack *extack)
3676{
3677 int i;
3678
3679 for (i = 0; i < if_count; i++) {
3680 if (ifindexes[i] == out_dev->ifindex) {
3681 NL_SET_ERR_MSG_MOD(extack,
3682 "can't duplicate output to same device");
3683 netdev_err(dev, "can't duplicate output to same device: %s\n",
3684 out_dev->name);
3685 return true;
3686 }
3687 }
3688
3689 return false;
3690}
3691
613f53fe
EC		 3692static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3693 struct mlx5e_tc_flow *flow,
3694 struct net_device *out_dev,
3695 struct netlink_ext_ack *extack)
3696{
c620b772 3697 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3698 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3699 struct mlx5e_rep_priv *rep_priv;
3700
3701 /* Forwarding non encapsulated traffic between
3702 * uplink ports is allowed only if
3703 * termination_table_raw_traffic cap is set.
3704 *
c620b772 3705 * Input vport was stored attr->in_rep.
613f53fe
EC		 3706 * In LAG case, *priv* is the private data of
3707 * uplink which may be not the input vport.
3708 */
3709 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3710
3711 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3712 mlx5e_eswitch_uplink_rep(out_dev)))
3713 return 0;
3714
3715 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3716 termination_table_raw_traffic)) {
3717 NL_SET_ERR_MSG_MOD(extack,
3718 "devices are both uplink, can't offload forwarding");
3719 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3720 priv->netdev->name, out_dev->name);
3721 return -EOPNOTSUPP;
3722 } else if (out_dev != rep_priv->netdev) {
3723 NL_SET_ERR_MSG_MOD(extack,
3724 "devices are not the same uplink, can't offload forwarding");
3725 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3726 priv->netdev->name, out_dev->name);
3727 return -EOPNOTSUPP;
3728 }
3729 return 0;
3730}
3731
73867881
PNA		 3732static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3733 struct flow_action *flow_action,
e98bedf5 3734 struct mlx5e_tc_flow *flow,
14e6b038
EC		 3735 struct netlink_ext_ack *extack,
3736 struct net_device *filter_dev)
03a9d11e 3737{
73867881 3738 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3739 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3740 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3741 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3742 const struct ip_tunnel_info *info = NULL;
c620b772 3743 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3744 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3745 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3746 const struct flow_action_entry *act;
c620b772 3747 struct mlx5_esw_flow_attr *esw_attr;
41c2fd94 3748 struct mlx5_sample_attr sample = {};
0a7fcb78
PB		 3749 bool encap = false, decap = false;
3750 u32 action = attr->action;
554fe75c 3751 int err, i, if_count = 0;
f828ca6a 3752 bool mpls_push = false;
03a9d11e 3753
73867881 3754 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3755 return -EINVAL;
3756
53eca1f3
JK		 3757 if (!flow_action_hw_stats_check(flow_action, extack,
3758 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3759 return -EOPNOTSUPP;
3760
c620b772
AL		 3761 esw_attr = attr->esw_attr;
3762 parse_attr = attr->parse_attr;
3763
73867881
PNA		 3764 flow_action_for_each(i, act, flow_action) {
3765 switch (act->id) {
3766 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3767 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3768 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3769 break;
f0288210
EC		 3770 case FLOW_ACTION_TRAP:
3771 if (!flow_offload_has_one_action(flow_action)) {
3772 NL_SET_ERR_MSG_MOD(extack,
3773 "action trap is supported as a sole action only");
3774 return -EOPNOTSUPP;
3775 }
3776 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3777 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3778 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3779 break;
f828ca6a
EC		 3780 case FLOW_ACTION_MPLS_PUSH:
3781 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3782 reformat_l2_to_l3_tunnel) ||
3783 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3784 NL_SET_ERR_MSG_MOD(extack,
3785 "mpls push is supported only for mpls_uc protocol");
3786 return -EOPNOTSUPP;
3787 }
3788 mpls_push = true;
3789 break;
14e6b038
EC		 3790 case FLOW_ACTION_MPLS_POP:
3791 /* we only support mpls pop if it is the first action
3792 * and the filter net device is bareudp. Subsequent
3793 * actions can be pedit and the last can be mirred
3794 * egress redirect.
3795 */
3796 if (i) {
3797 NL_SET_ERR_MSG_MOD(extack,
3798 "mpls pop supported only as first action");
3799 return -EOPNOTSUPP;
3800 }
3801 if (!netif_is_bareudp(filter_dev)) {
3802 NL_SET_ERR_MSG_MOD(extack,
3803 "mpls pop supported only on bareudp devices");
3804 return -EOPNOTSUPP;
3805 }
3806
3807 parse_attr->eth.h_proto = act->mpls_pop.proto;
3808 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3809 flow_flag_set(flow, L3_TO_L2_DECAP);
3810 break;
73867881
PNA		 3811 case FLOW_ACTION_MANGLE:
3812 case FLOW_ACTION_ADD:
3813 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3814 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3815 if (err)
3816 return err;
3817
582234b4
EC		 3818 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3819 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3820 esw_attr->split_count = esw_attr->out_count;
582234b4 3821 }
73867881
PNA		 3822 break;
3823 case FLOW_ACTION_CSUM:
1cab1cd7 3824 if (csum_offload_supported(priv, action,
73867881
PNA		 3825 act->csum_flags, extack))
3826 break;
26c02749
OG		 3827
3828 return -EOPNOTSUPP;
73867881
PNA		 3829 case FLOW_ACTION_REDIRECT:
3830 case FLOW_ACTION_MIRRED: {
03a9d11e 3831 struct mlx5e_priv *out_priv;
592d3651 3832 struct net_device *out_dev;
03a9d11e 3833
73867881 3834 out_dev = act->dev;
ef381359
OS		 3835 if (!out_dev) {
3836 /* out_dev is NULL when filters with
3837 * non-existing mirred device are replayed to
3838 * the driver.
3839 */
3840 return -EINVAL;
3841 }
03a9d11e 3842
f828ca6a
EC		 3843 if (mpls_push && !netif_is_bareudp(out_dev)) {
3844 NL_SET_ERR_MSG_MOD(extack,
3845 "mpls is supported only through a bareudp device");
3846 return -EOPNOTSUPP;
3847 }
3848
84179981
PB		 3849 if (ft_flow && out_dev == priv->netdev) {
3850 /* Ignore forward to self rules generated
3851 * by adding both mlx5 devs to the flow table
3852 * block on a normal nft offload setup.
3853 */
3854 return -EOPNOTSUPP;
3855 }
3856
c620b772 3857 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3858 NL_SET_ERR_MSG_MOD(extack,
3859 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3860 netdev_warn(priv->netdev,
3861 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3862 esw_attr->out_count);
592d3651
CM		 3863 return -EOPNOTSUPP;
3864 }
3865
f493f155
EB		 3866 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3867 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3868 if (encap) {
c620b772 3869 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3870 out_dev->ifindex;
0d9f9647
VB		 3871 parse_attr->tun_info[esw_attr->out_count] =
3872 mlx5e_dup_tun_info(info);
c620b772 3873 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3874 return -ENOMEM;
3875 encap = false;
c620b772 3876 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3877 MLX5_ESW_DEST_ENCAP;
c620b772 3878 esw_attr->out_count++;
b6a4ac24
VB		 3879 /* attr->dests[].rep is resolved when we
3880 * handle encap
3881 */
3882 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3883 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3884 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3885
554fe75c
DL		 3886 if (is_duplicated_output_device(priv->netdev,
3887 out_dev,
3888 ifindexes,
3889 if_count,
3890 extack))
3891 return -EOPNOTSUPP;
3892
3893 ifindexes[if_count] = out_dev->ifindex;
3894 if_count++;
3895
d34eb2fc
OG		 3896 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3897 if (!out_dev)
3898 return -ENODEV;
7ba58ba7 3899
278748a9
EB		 3900 if (is_vlan_dev(out_dev)) {
3901 err = add_vlan_push_action(priv, attr,
3902 &out_dev,
3903 &action);
3904 if (err)
3905 return err;
3906 }
f6dc1264 3907
35a605db
EB		 3908 if (is_vlan_dev(parse_attr->filter_dev)) {
3909 err = add_vlan_pop_action(priv, attr,
3910 &action);
3911 if (err)
3912 return err;
3913 }
278748a9 3914
613f53fe
EC		 3915 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3916 if (err)
3917 return err;
ffec9702 3918
f6dc1264
PB		 3919 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3920 NL_SET_ERR_MSG_MOD(extack,
3921 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3922 return -EOPNOTSUPP;
f6dc1264 3923 }
a0646c88 3924
bb569657
AL		 3925 if (same_vf_reps(priv, out_dev)) {
3926 NL_SET_ERR_MSG_MOD(extack,
3927 "can't forward from a VF to itself");
3928 return -EOPNOTSUPP;
3929 }
3930
a54e20b4 3931 out_priv = netdev_priv(out_dev);
1d447a39 3932 rpriv = out_priv->ppriv;
c620b772
AL		 3933 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3934 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3935 esw_attr->out_count++;
ef381359
OS		 3936 } else if (parse_attr->filter_dev != priv->netdev) {
3937 /* All mlx5 devices are called to configure
3938 * high level device filters. Therefore, the
3939 * *attempt* to install a filter on invalid
3940 * eswitch should not trigger an explicit error
3941 */
3942 return -EINVAL;
a54e20b4 3943 } else {
e98bedf5
EB		 3944 NL_SET_ERR_MSG_MOD(extack,
3945 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3946 netdev_warn(priv->netdev,
3947 "devices %s %s not on same switch HW, can't offload forwarding\n",
3948 priv->netdev->name,
3949 out_dev->name);
03a9d11e
OG		 3950 return -EINVAL;
3951 }
73867881
PNA		 3952 }
3953 break;
3954 case FLOW_ACTION_TUNNEL_ENCAP:
3955 info = act->tunnel;
a54e20b4
HHZ		 3956 if (info)
3957 encap = true;
3958 else
3959 return -EOPNOTSUPP;
1482bd3d 3960
73867881
PNA		 3961 break;
3962 case FLOW_ACTION_VLAN_PUSH:
3963 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3964 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3965 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3966 /* Replace vlan pop+push with vlan modify */
3967 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3968 err = add_vlan_rewrite_action(priv,
3969 MLX5_FLOW_NAMESPACE_FDB,
3970 act, parse_attr, hdrs,
3971 &action, extack);
3972 } else {
c620b772 3973 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3974 }
1482bd3d
JL		 3975 if (err)
3976 return err;
3977
c620b772 3978 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3979 break;
3980 case FLOW_ACTION_VLAN_MANGLE:
3981 err = add_vlan_rewrite_action(priv,
3982 MLX5_FLOW_NAMESPACE_FDB,
3983 act, parse_attr, hdrs,
3984 &action, extack);
3985 if (err)
3986 return err;
3987
c620b772 3988 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3989 break;
3990 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3991 decap = true;
73867881 3992 break;
2fbbc30d 3993 case FLOW_ACTION_GOTO:
c7569097
AL		 3994 err = validate_goto_chain(priv, flow, act, action,
3995 extack);
2fbbc30d
EC		 3996 if (err)
3997 return err;
bf07aa73 3998
e88afe75 3999 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4000 attr->dest_chain = act->chain_index;
73867881 4001 break;
4c3844d9 4002 case FLOW_ACTION_CT:
41c2fd94
CM		 4003 if (flow_flag_test(flow, SAMPLE)) {
4004 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4005 return -EOPNOTSUPP;
4006 }
aedd133d 4007 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4008 if (err)
4009 return err;
4010
4011 flow_flag_set(flow, CT);
69e2916e 4012 esw_attr->split_count = esw_attr->out_count;
4c3844d9 4013 break;
41c2fd94
CM		 4014 case FLOW_ACTION_SAMPLE:
4015 if (flow_flag_test(flow, CT)) {
4016 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4017 return -EOPNOTSUPP;
4018 }
4019 sample.rate = act->sample.rate;
4020 sample.group_num = act->sample.psample_group->group_num;
4021 if (act->sample.truncate)
4022 sample.trunc_size = act->sample.trunc_size;
4023 flow_flag_set(flow, SAMPLE);
4024 break;
73867881 4025 default:
2cc1cb1d
TZ		 4026 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4027 return -EOPNOTSUPP;
bf07aa73 4028 }
03a9d11e 4029 }
bdd66ac0 4030
a508728a
VB		 4031 /* always set IP version for indirect table handling */
4032 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4033
0bac1194
EB		 4034 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4035 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4036 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4037 * tag rewrite.
4038 */
4039 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4040 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4041 &action, extack);
4042 if (err)
4043 return err;
4044 }
4045
c500c86b
PNA		 4046 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4047 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4048 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4049 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4050 if (err)
4051 return err;
27c11b6b
EB		 4052 /* in case all pedit actions are skipped, remove the MOD_HDR
4053 * flag. we might have set split_count either by pedit or
4054 * pop/push. if there is no pop/push either, reset it too.
4055 */
6ae4a6a5 4056 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4057 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4058 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4059 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4060 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4061 esw_attr->split_count = 0;
27c11b6b 4062 }
c500c86b
PNA		 4063 }
4064
1cab1cd7 4065 attr->action = action;
73867881 4066 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4067 return -EOPNOTSUPP;
4068
e88afe75 4069 if (attr->dest_chain) {
0a7fcb78
PB		 4070 if (decap) {
4071 /* It can be supported if we'll create a mapping for
4072 * the tunnel device only (without tunnel), and set
4073 * this tunnel id with this decap flow.
4074 *
4075 * On restore (miss), we'll just set this saved tunnel
4076 * device.
4077 */
4078
4079 NL_SET_ERR_MSG(extack,
4080 "Decap with goto isn't supported");
4081 netdev_warn(priv->netdev,
4082 "Decap with goto isn't supported");
4083 return -EOPNOTSUPP;
4084 }
4085
e88afe75
OG		 4086 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4087 }
4088
ae2741e2
VB		 4089 if (!(attr->action &
4090 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4091 NL_SET_ERR_MSG_MOD(extack,
4092 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4093 return -EOPNOTSUPP;
4094 }
4095
c620b772 4096 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4097 NL_SET_ERR_MSG_MOD(extack,
4098 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4099 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4100 return -EOPNOTSUPP;
4101 }
4102
41c2fd94
CM		 4103 /* Allocate sample attribute only when there is a sample action and
4104 * no errors after parsing.
4105 */
4106 if (flow_flag_test(flow, SAMPLE)) {
4107 esw_attr->sample = kzalloc(sizeof(*esw_attr->sample), GFP_KERNEL);
4108 if (!esw_attr->sample)
4109 return -ENOMEM;
4110 *esw_attr->sample = sample;
4111 }
4112
31c8eba5 4113 return 0;
03a9d11e
OG		 4114}
4115
226f2ca3 4116static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4117{
226f2ca3 4118 unsigned long __flow_flags = 0;
60bd4af8 4119
226f2ca3
VB		 4120 if (flags & MLX5_TC_FLAG(INGRESS))
4121 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4122 if (flags & MLX5_TC_FLAG(EGRESS))
4123 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4124
226f2ca3
VB		 4125 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4126 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4127 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4128 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4129 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4130 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4131
60bd4af8
OG		 4132 *flow_flags = __flow_flags;
4133}
4134
05866c82
OG		 4135static const struct rhashtable_params tc_ht_params = {
4136 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4137 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4138 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4139 .automatic_shrinking = true,
4140};
4141
226f2ca3
VB		 4142static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4143 unsigned long flags)
05866c82 4144{
655dc3d2
OG		 4145 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4146 struct mlx5e_rep_priv *uplink_rpriv;
4147
226f2ca3 4148 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4149 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4150 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4151 } else /* NIC offload */
655dc3d2 4152 return &priv->fs.tc.ht;
05866c82
OG		 4153}
4154
04de7dda
RD		 4155static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4156{
c620b772
AL		 4157 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4158 struct mlx5_flow_attr *attr = flow->attr;
4159 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4160 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4161 bool act_is_encap = !!(attr->action &
4162 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4163 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4164 MLX5_DEVCOM_ESW_OFFLOADS);
4165
10fbb1cd
RD		 4166 if (!esw_paired)
4167 return false;
4168
c620b772
AL		 4169 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4170 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4171 (is_rep_ingress || act_is_encap))
4172 return true;
4173
4174 return false;
04de7dda
RD		 4175}
4176
c620b772
AL		 4177struct mlx5_flow_attr *
4178mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4179{
4180 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4181 sizeof(struct mlx5_esw_flow_attr) :
4182 sizeof(struct mlx5_nic_flow_attr);
4183 struct mlx5_flow_attr *attr;
4184
4185 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4186}
4187
a88780a9
RD		 4188static int
4189mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4190 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4191 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4192 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4193{
17091853 4194 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4195 struct mlx5_flow_attr *attr;
3bc4b7bf 4196 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4197 int err = -ENOMEM;
4198 int out_index;
e3a2b7ed 4199
c620b772 4200 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4201 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4202 if (!parse_attr || !flow)
4203 goto err_free;
c620b772
AL		 4204
4205 flow->flags = flow_flags;
4206 flow->cookie = f->cookie;
4207 flow->priv = priv;
4208
4209 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4210 if (!attr)
e3a2b7ed 4211 goto err_free;
ff7ea04a 4212
c620b772 4213 flow->attr = attr;
e3a2b7ed 4214
5a7e5bcb
VB		 4215 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4216 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4217 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4218 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4219 refcount_set(&flow->refcnt, 1);
95435ad7 4220 init_completion(&flow->init_done);
e3a2b7ed 4221
a88780a9
RD		 4222 *__flow = flow;
4223 *__parse_attr = parse_attr;
4224
4225 return 0;
4226
4227err_free:
4228 kfree(flow);
4229 kvfree(parse_attr);
4230 return err;
4231}
4232
c7569097
AL		 4233static void
4234mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4235 struct mlx5e_tc_flow_parse_attr *parse_attr,
4236 struct flow_cls_offload *f)
4237{
4238 attr->parse_attr = parse_attr;
4239 attr->chain = f->common.chain_index;
4240 attr->prio = f->common.prio;
4241}
4242
988ab9c7 4243static void
c620b772 4244mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4245 struct mlx5e_priv *priv,
4246 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4247 struct flow_cls_offload *f,
988ab9c7
TZ		 4248 struct mlx5_eswitch_rep *in_rep,
4249 struct mlx5_core_dev *in_mdev)
4250{
4251 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4252 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4253
c7569097 4254 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4255
4256 esw_attr->in_rep = in_rep;
4257 esw_attr->in_mdev = in_mdev;
4258
4259 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4260 MLX5_COUNTER_SOURCE_ESWITCH)
4261 esw_attr->counter_dev = in_mdev;
4262 else
4263 esw_attr->counter_dev = priv->mdev;
4264}
4265
71129676 4266static struct mlx5e_tc_flow *
04de7dda 4267__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4268 struct flow_cls_offload *f,
226f2ca3 4269 unsigned long flow_flags,
04de7dda
RD		 4270 struct net_device *filter_dev,
4271 struct mlx5_eswitch_rep *in_rep,
71129676 4272 struct mlx5_core_dev *in_mdev)
a88780a9 4273{
f9e30088 4274 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4275 struct netlink_ext_ack *extack = f->common.extack;
4276 struct mlx5e_tc_flow_parse_attr *parse_attr;
4277 struct mlx5e_tc_flow *flow;
4278 int attr_size, err;
e3a2b7ed 4279
226f2ca3 4280 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4281 attr_size = sizeof(struct mlx5_esw_flow_attr);
4282 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4283 &parse_attr, &flow);
4284 if (err)
4285 goto out;
988ab9c7 4286
d11afc26 4287 parse_attr->filter_dev = filter_dev;
c620b772 4288 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4289 priv, parse_attr,
4290 f, in_rep, in_mdev);
4291
54c177ca
OS		 4292 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4293 f, filter_dev);
d11afc26
OS		 4294 if (err)
4295 goto err_free;
a88780a9 4296
7e36feeb 4297 /* actions validation depends on parsing the ct matches first */
aedd133d 4298 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4299 &flow->attr->ct_attr, extack);
a88780a9
RD		 4300 if (err)
4301 goto err_free;
4302
7e36feeb 4303 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4304 if (err)
4305 goto err_free;
4306
7040632d 4307 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4308 complete_all(&flow->init_done);
ef06c9ee
RD		 4309 if (err) {
4310 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4311 goto err_free;
4312
b4a23329 4313 add_unready_flow(flow);
ef06c9ee 4314 }
e3a2b7ed 4315
71129676 4316 return flow;
a88780a9
RD		 4317
4318err_free:
5a7e5bcb 4319 mlx5e_flow_put(priv, flow);
a88780a9 4320out:
71129676 4321 return ERR_PTR(err);
a88780a9
RD		 4322}
4323
f9e30088 4324static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4325 struct mlx5e_tc_flow *flow,
226f2ca3 4326 unsigned long flow_flags)
04de7dda
RD		 4327{
4328 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4329 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4330 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4331 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4332 struct mlx5e_tc_flow_parse_attr *parse_attr;
4333 struct mlx5e_rep_priv *peer_urpriv;
4334 struct mlx5e_tc_flow *peer_flow;
4335 struct mlx5_core_dev *in_mdev;
4336 int err = 0;
4337
4338 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4339 if (!peer_esw)
4340 return -ENODEV;
4341
4342 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4343 peer_priv = netdev_priv(peer_urpriv->netdev);
4344
4345 /* in_mdev is assigned of which the packet originated from.
4346 * So packets redirected to uplink use the same mdev of the
4347 * original flow and packets redirected from uplink use the
4348 * peer mdev.
4349 */
c620b772 4350 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4351 in_mdev = peer_priv->mdev;
4352 else
4353 in_mdev = priv->mdev;
4354
c620b772 4355 parse_attr = flow->attr->parse_attr;
95dc1902 4356 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4357 parse_attr->filter_dev,
c620b772 4358 attr->in_rep, in_mdev);
71129676
JG		 4359 if (IS_ERR(peer_flow)) {
4360 err = PTR_ERR(peer_flow);
04de7dda 4361 goto out;
71129676 4362 }
04de7dda
RD		 4363
4364 flow->peer_flow = peer_flow;
226f2ca3 4365 flow_flag_set(flow, DUP);
04de7dda
RD		 4366 mutex_lock(&esw->offloads.peer_mutex);
4367 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4368 mutex_unlock(&esw->offloads.peer_mutex);
4369
4370out:
4371 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4372 return err;
4373}
4374
4375static int
4376mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4377 struct flow_cls_offload *f,
226f2ca3 4378 unsigned long flow_flags,
04de7dda
RD		 4379 struct net_device *filter_dev,
4380 struct mlx5e_tc_flow **__flow)
4381{
4382 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4383 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4384 struct mlx5_core_dev *in_mdev = priv->mdev;
4385 struct mlx5e_tc_flow *flow;
4386 int err;
4387
71129676
JG		 4388 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4389 in_mdev);
4390 if (IS_ERR(flow))
4391 return PTR_ERR(flow);
04de7dda
RD		 4392
4393 if (is_peer_flow_needed(flow)) {
95dc1902 4394 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4395 if (err) {
4396 mlx5e_tc_del_fdb_flow(priv, flow);
4397 goto out;
4398 }
4399 }
4400
4401 *__flow = flow;
4402
4403 return 0;
4404
4405out:
4406 return err;
4407}
4408
a88780a9
RD		 4409static int
4410mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4411 struct flow_cls_offload *f,
226f2ca3 4412 unsigned long flow_flags,
d11afc26 4413 struct net_device *filter_dev,
a88780a9
RD		 4414 struct mlx5e_tc_flow **__flow)
4415{
f9e30088 4416 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4417 struct netlink_ext_ack *extack = f->common.extack;
4418 struct mlx5e_tc_flow_parse_attr *parse_attr;
4419 struct mlx5e_tc_flow *flow;
4420 int attr_size, err;
4421
c7569097
AL		 4422 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4423 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4424 return -EOPNOTSUPP;
4425 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4426 return -EOPNOTSUPP;
c7569097 4427 }
bf07aa73 4428
226f2ca3 4429 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4430 attr_size = sizeof(struct mlx5_nic_flow_attr);
4431 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4432 &parse_attr, &flow);
4433 if (err)
4434 goto out;
4435
d11afc26 4436 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4437 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4438
54c177ca
OS		 4439 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4440 f, filter_dev);
d11afc26
OS		 4441 if (err)
4442 goto err_free;
4443
aedd133d
AL		 4444 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4445 &flow->attr->ct_attr, extack);
4446 if (err)
4447 goto err_free;
4448
73867881 4449 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4450 if (err)
4451 goto err_free;
4452
4453 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4454 if (err)
4455 goto err_free;
4456
226f2ca3 4457 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4458 *__flow = flow;
4459
4460 return 0;
e3a2b7ed 4461
e3a2b7ed 4462err_free:
8914add2 4463 flow_flag_set(flow, FAILED);
e68e28b4 4464 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4465 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4466out:
4467 return err;
4468}
4469
4470static int
4471mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4472 struct flow_cls_offload *f,
226f2ca3 4473 unsigned long flags,
d11afc26 4474 struct net_device *filter_dev,
a88780a9
RD		 4475 struct mlx5e_tc_flow **flow)
4476{
4477 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4478 unsigned long flow_flags;
a88780a9
RD		 4479 int err;
4480
4481 get_flags(flags, &flow_flags);
4482
bf07aa73
PB		 4483 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4484 return -EOPNOTSUPP;
4485
f6455de0 4486 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4487 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4488 filter_dev, flow);
a88780a9 4489 else
d11afc26
OS		 4490 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4491 filter_dev, flow);
a88780a9
RD		 4492
4493 return err;
4494}
4495
553f9328
VP		 4496static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4497 struct mlx5e_rep_priv *rpriv)
4498{
4499 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4500 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4501 * function is called from NIC mode.
553f9328 4502 */
2fb15e72 4503 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4504}
4505
71d82d2a 4506int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4507 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4508{
4509 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4510 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4511 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4512 struct mlx5e_tc_flow *flow;
4513 int err = 0;
4514
7dc84de9
RD		 4515 if (!mlx5_esw_hold(priv->mdev))
4516 return -EAGAIN;
4517
4518 mlx5_esw_get(priv->mdev);
4519
c5d326b2
VB		 4520 rcu_read_lock();
4521 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4522 if (flow) {
553f9328
VP		 4523 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4524 * just return 0.
4525 */
4526 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4527 goto rcu_unlock;
553f9328 4528
a88780a9
RD		 4529 NL_SET_ERR_MSG_MOD(extack,
4530 "flow cookie already exists, ignoring");
4531 netdev_warn_once(priv->netdev,
4532 "flow cookie %lx already exists, ignoring\n",
4533 f->cookie);
0e1c1a2f 4534 err = -EEXIST;
c1aea9e1 4535 goto rcu_unlock;
a88780a9 4536 }
c1aea9e1
VB		 4537rcu_unlock:
4538 rcu_read_unlock();
4539 if (flow)
4540 goto out;
a88780a9 4541
7a978759 4542 trace_mlx5e_configure_flower(f);
d11afc26 4543 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4544 if (err)
4545 goto out;
4546
553f9328
VP		 4547 /* Flow rule offloaded to non-uplink representor sharing tc block,
4548 * set the flow's owner dev.
4549 */
4550 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4551 flow->orig_dev = dev;
4552
c5d326b2 4553 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4554 if (err)
4555 goto err_free;
4556
7dc84de9 4557 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4558 return 0;
4559
4560err_free:
5a7e5bcb 4561 mlx5e_flow_put(priv, flow);
a88780a9 4562out:
7dc84de9
RD		 4563 mlx5_esw_put(priv->mdev);
4564 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4565 return err;
4566}
4567
8f8ae895
OG		 4568static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4569{
226f2ca3
VB		 4570 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4571 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4572
226f2ca3
VB		 4573 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4574 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4575}
4576
71d82d2a 4577int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4578 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4579{
d9ee0491 4580 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4581 struct mlx5e_tc_flow *flow;
c5d326b2 4582 int err;
e3a2b7ed 4583
c5d326b2 4584 rcu_read_lock();
ab818362 4585 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4586 if (!flow || !same_flow_direction(flow, flags)) {
4587 err = -EINVAL;
4588 goto errout;
4589 }
e3a2b7ed 4590
c5d326b2
VB		 4591 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4592 * set.
4593 */
4594 if (flow_flag_test_and_set(flow, DELETED)) {
4595 err = -EINVAL;
4596 goto errout;
4597 }
05866c82 4598 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4599 rcu_read_unlock();
e3a2b7ed 4600
7a978759 4601 trace_mlx5e_delete_flower(f);
5a7e5bcb 4602 mlx5e_flow_put(priv, flow);
e3a2b7ed 4603
7dc84de9 4604 mlx5_esw_put(priv->mdev);
e3a2b7ed 4605 return 0;
c5d326b2
VB		 4606
4607errout:
4608 rcu_read_unlock();
4609 return err;
e3a2b7ed
AV		 4610}
4611
71d82d2a 4612int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4613 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4614{
04de7dda 4615 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4616 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4617 struct mlx5_eswitch *peer_esw;
aad7e08d 4618 struct mlx5e_tc_flow *flow;
aad7e08d 4619 struct mlx5_fc *counter;
316d5f72
RD		 4620 u64 lastuse = 0;
4621 u64 packets = 0;
4622 u64 bytes = 0;
5a7e5bcb 4623 int err = 0;
aad7e08d 4624
c5d326b2
VB		 4625 rcu_read_lock();
4626 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4627 tc_ht_params));
4628 rcu_read_unlock();
5a7e5bcb
VB		 4629 if (IS_ERR(flow))
4630 return PTR_ERR(flow);
4631
4632 if (!same_flow_direction(flow, flags)) {
4633 err = -EINVAL;
4634 goto errout;
4635 }
aad7e08d 4636
4c3844d9 4637 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4638 counter = mlx5e_tc_get_counter(flow);
4639 if (!counter)
5a7e5bcb 4640 goto errout;
aad7e08d 4641
316d5f72
RD		 4642 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4643 }
aad7e08d 4644
316d5f72
RD		 4645 /* Under multipath it's possible for one rule to be currently
4646 * un-offloaded while the other rule is offloaded.
4647 */
04de7dda
RD		 4648 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4649 if (!peer_esw)
4650 goto out;
4651
226f2ca3
VB		 4652 if (flow_flag_test(flow, DUP) &&
4653 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4654 u64 bytes2;
4655 u64 packets2;
4656 u64 lastuse2;
4657
4658 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4659 if (!counter)
4660 goto no_peer_counter;
04de7dda
RD		 4661 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4662
4663 bytes += bytes2;
4664 packets += packets2;
4665 lastuse = max_t(u64, lastuse, lastuse2);
4666 }
4667
316d5f72 4668no_peer_counter:
04de7dda 4669 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4670out:
4b61d3e8 4671 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4672 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4673 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4674errout:
4675 mlx5e_flow_put(priv, flow);
4676 return err;
aad7e08d
AV		 4677}
4678
1fe3e316 4679static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4680 struct netlink_ext_ack *extack)
4681{
4682 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4683 struct mlx5_eswitch *esw;
1fe3e316 4684 u32 rate_mbps = 0;
fcb64c0f 4685 u16 vport_num;
fcb64c0f
EC		 4686 int err;
4687
e401a184
EC		 4688 vport_num = rpriv->rep->vport;
4689 if (vport_num >= MLX5_VPORT_ECPF) {
4690 NL_SET_ERR_MSG_MOD(extack,
4691 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4692 return -EOPNOTSUPP;
4693 }
4694
fcb64c0f
EC		 4695 esw = priv->mdev->priv.eswitch;
4696 /* rate is given in bytes/sec.
4697 * First convert to bits/sec and then round to the nearest mbit/secs.
4698 * mbit means million bits.
4699 * Moreover, if rate is non zero we choose to configure to a minimum of
4700 * 1 mbit/sec.
4701 */
1fe3e316
PP		 4702 if (rate) {
4703 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4704 do_div(rate, 1000000);
4705 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4706 }
4707
fcb64c0f
EC		 4708 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4709 if (err)
4710 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4711
4712 return err;
4713}
4714
4715static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4716 struct flow_action *flow_action,
4717 struct netlink_ext_ack *extack)
4718{
4719 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4720 const struct flow_action_entry *act;
4721 int err;
4722 int i;
4723
4724 if (!flow_action_has_entries(flow_action)) {
4725 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4726 return -EINVAL;
4727 }
4728
4729 if (!flow_offload_has_one_action(flow_action)) {
4730 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4731 return -EOPNOTSUPP;
4732 }
4733
53eca1f3 4734 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4735 return -EOPNOTSUPP;
4736
fcb64c0f
EC		 4737 flow_action_for_each(i, act, flow_action) {
4738 switch (act->id) {
4739 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4740 if (act->police.rate_pkt_ps) {
4741 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4742 return -EOPNOTSUPP;
4743 }
fcb64c0f
EC		 4744 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4745 if (err)
4746 return err;
4747
4748 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4749 break;
4750 default:
4751 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4752 return -EOPNOTSUPP;
4753 }
4754 }
4755
4756 return 0;
4757}
4758
4759int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4760 struct tc_cls_matchall_offload *ma)
4761{
b5f814cc 4762 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4763 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4764
b5f814cc
EC		 4765 if (!mlx5_esw_qos_enabled(esw)) {
4766 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4767 return -EOPNOTSUPP;
4768 }
4769
7b83355f 4770 if (ma->common.prio != 1) {
fcb64c0f
EC		 4771 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4772 return -EINVAL;
4773 }
4774
4775 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4776}
4777
4778int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4779 struct tc_cls_matchall_offload *ma)
4780{
4781 struct netlink_ext_ack *extack = ma->common.extack;
4782
4783 return apply_police_params(priv, 0, extack);
4784}
4785
4786void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4787 struct tc_cls_matchall_offload *ma)
4788{
4789 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4790 struct rtnl_link_stats64 cur_stats;
4791 u64 dbytes;
4792 u64 dpkts;
4793
4794 cur_stats = priv->stats.vf_vport;
4795 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4796 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4797 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4798 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4799 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4800}
4801
4d8fcf21
AH		 4802static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4803 struct mlx5e_priv *peer_priv)
4804{
4805 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4806 struct mlx5e_hairpin_entry *hpe, *tmp;
4807 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4808 u16 peer_vhca_id;
4809 int bkt;
4810
4811 if (!same_hw_devs(priv, peer_priv))
4812 return;
4813
4814 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4815
b32accda 4816 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4817 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4818 if (refcount_inc_not_zero(&hpe->refcnt))
4819 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4820 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4821
4822 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4823 wait_for_completion(&hpe->res_ready);
4824 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4825 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4826
4827 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4828 }
4829}
4830
4831static int mlx5e_tc_netdev_event(struct notifier_block *this,
4832 unsigned long event, void *ptr)
4833{
4834 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4835 struct mlx5e_flow_steering *fs;
4836 struct mlx5e_priv *peer_priv;
4837 struct mlx5e_tc_table *tc;
4838 struct mlx5e_priv *priv;
4839
4840 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4841 event != NETDEV_UNREGISTER ||
4842 ndev->reg_state == NETREG_REGISTERED)
4843 return NOTIFY_DONE;
4844
4845 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4846 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4847 priv = container_of(fs, struct mlx5e_priv, fs);
4848 peer_priv = netdev_priv(ndev);
4849 if (priv == peer_priv ||
4850 !(priv->netdev->features & NETIF_F_HW_TC))
4851 return NOTIFY_DONE;
4852
4853 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4854
4855 return NOTIFY_DONE;
4856}
4857
6a064674
AL		 4858static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4859{
4860 int tc_grp_size, tc_tbl_size;
4861 u32 max_flow_counter;
4862
4863 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4864 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4865
4866 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4867
4868 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4869 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4870
4871 return tc_tbl_size;
4872}
4873
655dc3d2 4874int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4875{
acff797c 4876 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4877 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4878 struct mapping_ctx *chains_mapping;
6a064674 4879 struct mlx5_chains_attr attr = {};
4d8fcf21 4880 int err;
e8f887ac 4881
b2fdf3d0 4882 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4883 mutex_init(&tc->t_lock);
b32accda 4884 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4885 hash_init(tc->hairpin_tbl);
11c9c548 4886
4d8fcf21
AH		 4887 err = rhashtable_init(&tc->ht, &tc_ht_params);
4888 if (err)
4889 return err;
4890
9ba33339
RD		 4891 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4892
c9355682
CM		 4893 chains_mapping = mapping_create(sizeof(struct mlx5_mapped_obj),
4894 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4895 if (IS_ERR(chains_mapping)) {
4896 err = PTR_ERR(chains_mapping);
4897 goto err_mapping;
4898 }
4899 tc->mapping = chains_mapping;
4900
4901 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4902 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4903 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4904 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4905 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4906 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4907 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4908 attr.mapping = chains_mapping;
6a064674
AL		 4909
4910 tc->chains = mlx5_chains_create(dev, &attr);
4911 if (IS_ERR(tc->chains)) {
4912 err = PTR_ERR(tc->chains);
4913 goto err_chains;
4914 }
4915
aedd133d
AL		 4916 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
4917 MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4918
4d8fcf21 4919 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4920 err = register_netdevice_notifier_dev_net(priv->netdev,
4921 &tc->netdevice_nb,
4922 &tc->netdevice_nn);
4923 if (err) {
4d8fcf21
AH		 4924 tc->netdevice_nb.notifier_call = NULL;
4925 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4926 goto err_reg;
4d8fcf21
AH		 4927 }
4928
6a064674
AL		 4929 return 0;
4930
4931err_reg:
aedd133d 4932 mlx5_tc_ct_clean(tc->ct);
6a064674
AL		 4933 mlx5_chains_destroy(tc->chains);
4934err_chains:
c9355682
CM		 4935 mapping_destroy(chains_mapping);
4936err_mapping:
6a064674 4937 rhashtable_destroy(&tc->ht);
4d8fcf21 4938 return err;
e8f887ac
AV		 4939}
4940
4941static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4942{
4943 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4944 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4945
961e8979 4946 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4947 kfree(flow);
4948}
4949
655dc3d2 4950void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4951{
acff797c 4952 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4953
4d8fcf21 4954 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4955 unregister_netdevice_notifier_dev_net(priv->netdev,
4956 &tc->netdevice_nb,
4957 &tc->netdevice_nn);
4d8fcf21 4958
b2fdf3d0 4959 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4960 mutex_destroy(&tc->hairpin_tbl_lock);
4961
6a064674 4962 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4963
acff797c 4964 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4965 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4966 tc->t = NULL;
e8f887ac 4967 }
b6fac0b4 4968 mutex_destroy(&tc->t_lock);
6a064674 4969
aedd133d 4970 mlx5_tc_ct_clean(tc->ct);
c9355682 4971 mapping_destroy(tc->mapping);
6a064674 4972 mlx5_chains_destroy(tc->chains);
e8f887ac 4973}
655dc3d2
OG		 4974
4975int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4976{
d7a42ad0 4977 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4978 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4979 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4980 struct mapping_ctx *mapping;
aedd133d
AL		 4981 struct mlx5_eswitch *esw;
4982 struct mlx5e_priv *priv;
4983 int err = 0;
0a7fcb78
PB		 4984
4985 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4986 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4987 priv = netdev_priv(rpriv->netdev);
4988 esw = priv->mdev->priv.eswitch;
0a7fcb78 4989
aedd133d
AL		 4990 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4991 esw_chains(esw),
4992 &esw->offloads.mod_hdr,
4993 MLX5_FLOW_NAMESPACE_FDB);
4c3844d9 4994
2a9ab10a
CM		 4995#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
4996 uplink_priv->esw_psample = mlx5_esw_sample_init(netdev_priv(priv->netdev));
4997#endif
4998
0a7fcb78
PB		 4999 mapping = mapping_create(sizeof(struct tunnel_match_key),
5000 TUNNEL_INFO_BITS_MASK, true);
5001 if (IS_ERR(mapping)) {
5002 err = PTR_ERR(mapping);
5003 goto err_tun_mapping;
5004 }
5005 uplink_priv->tunnel_mapping = mapping;
5006
8e404fef
VB		 5007 /* 0xFFF is reserved for stack devices slow path table mark */
5008 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 5009 if (IS_ERR(mapping)) {
5010 err = PTR_ERR(mapping);
5011 goto err_enc_opts_mapping;
5012 }
5013 uplink_priv->tunnel_enc_opts_mapping = mapping;
5014
5015 err = rhashtable_init(tc_ht, &tc_ht_params);
5016 if (err)
5017 goto err_ht_init;
5018
9ba33339
RD		 5019 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5020
8914add2 5021 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 5022 if (IS_ERR(uplink_priv->encap)) {
5023 err = PTR_ERR(uplink_priv->encap);
8914add2 5024 goto err_register_fib_notifier;
2b6c3c1e 5025 }
8914add2 5026
2b6c3c1e 5027 return 0;
0a7fcb78 5028
8914add2
VB		 5029err_register_fib_notifier:
5030 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5031err_ht_init:
5032 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5033err_enc_opts_mapping:
5034 mapping_destroy(uplink_priv->tunnel_mapping);
5035err_tun_mapping:
2a9ab10a
CM		 5036#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
5037 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
5038#endif
aedd133d 5039 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5040 netdev_warn(priv->netdev,
5041 "Failed to initialize tc (eswitch), err: %d", err);
5042 return err;
655dc3d2
OG		 5043}
5044
5045void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5046{
0a7fcb78
PB		 5047 struct mlx5_rep_uplink_priv *uplink_priv;
5048
0a7fcb78 5049 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5050
8914add2
VB		 5051 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5052 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5053
0a7fcb78
PB		 5054 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5055 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5056
2a9ab10a
CM		 5057#if IS_ENABLED(CONFIG_MLX5_TC_SAMPLE)
5058 mlx5_esw_sample_cleanup(uplink_priv->esw_psample);
5059#endif
aedd133d 5060 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 5061}
01252a27 5062
226f2ca3 5063int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5064{
d9ee0491 5065 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5066
5067 return atomic_read(&tc_ht->nelems);
5068}
04de7dda
RD		 5069
5070void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5071{
5072 struct mlx5e_tc_flow *flow, *tmp;
5073
5074 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5075 __mlx5e_tc_del_fdb_peer_flow(flow);
5076}
b4a23329
RD		 5077
5078void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5079{
5080 struct mlx5_rep_uplink_priv *rpriv =
5081 container_of(work, struct mlx5_rep_uplink_priv,
5082 reoffload_flows_work);
5083 struct mlx5e_tc_flow *flow, *tmp;
5084
ad86755b 5085 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5086 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5087 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5088 unready_flow_del(flow);
b4a23329 5089 }
ad86755b 5090 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5091}
e2394a61
VB		 5092
5093static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5094 struct flow_cls_offload *cls_flower,
5095 unsigned long flags)
5096{
5097 switch (cls_flower->command) {
5098 case FLOW_CLS_REPLACE:
5099 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5100 flags);
5101 case FLOW_CLS_DESTROY:
5102 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5103 flags);
5104 case FLOW_CLS_STATS:
5105 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5106 flags);
5107 default:
5108 return -EOPNOTSUPP;
5109 }
5110}
5111
5112int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5113 void *cb_priv)
5114{
ec9457a6 5115 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5116 struct mlx5e_priv *priv = cb_priv;
5117
2ff349c5
RD		 5118 if (!priv->netdev || !netif_device_present(priv->netdev))
5119 return -EOPNOTSUPP;
5120
ec9457a6
RD		 5121 if (mlx5e_is_uplink_rep(priv))
5122 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5123 else
5124 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5125
e2394a61
VB		 5126 switch (type) {
5127 case TC_SETUP_CLSFLOWER:
5128 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5129 default:
5130 return -EOPNOTSUPP;
5131 }
5132}
c7569097
AL		 5133
5134bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5135 struct sk_buff *skb)
5136{
5137#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5138 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5139 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5140 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5141 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5142 struct tc_skb_ext *tc_skb_ext;
5143 int err;
5144
5145 reg_b = be32_to_cpu(cqe->ft_metadata);
5146
5147 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5148
c9355682 5149 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5150 if (err) {
5151 netdev_dbg(priv->netdev,
5152 "Couldn't find chain for chain tag: %d, err: %d\n",
5153 chain_tag, err);
5154 return false;
5155 }
5156
a91d98a0
CM		 5157 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5158 chain = mapped_obj.chain;
9453d45e 5159 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5160 if (WARN_ON(!tc_skb_ext))
5161 return false;
5162
5163 tc_skb_ext->chain = chain;
aedd133d 5164
ed2fe7ba 5165 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5166 ESW_ZONE_ID_MASK;
aedd133d
AL		 5167
5168 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5169 zone_restore_id))
5170 return false;
a91d98a0
CM		 5171 } else {
5172 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5173 return false;
c7569097
AL		 5174 }
5175#endif /* CONFIG_NET_TC_SKB_EXT */
5176
5177 return true;
5178}
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