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net/mlx5e: Use tc sample stubs instead of ifdefs in source file
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
d79b6df6 42#include <net/tc_act/tc_pedit.h>
26c02749 43#include <net/tc_act/tc_csum.h>
41c2fd94 44#include <net/psample.h>
f6dfb4c3 45#include <net/arp.h>
3616d08b 46#include <net/ipv6_stubs.h>
f828ca6a 47#include <net/bareudp.h>
d34eb2fc 48#include <net/bonding.h>
e8f887ac 49#include "en.h"
f0da4daa 50#include "en/tc/post_act.h"
1d447a39 51#include "en_rep.h"
768c3667 52#include "en/rep/tc.h"
e2394a61 53#include "en/rep/neigh.h"
232c0013 54#include "en_tc.h"
03a9d11e 55#include "eswitch.h"
3f6d08d1 56#include "fs_core.h"
2c81bfd5 57#include "en/port.h"
101f4de9 58#include "en/tc_tun.h"
0a7fcb78 59#include "en/mapping.h"
4c3844d9 60#include "en/tc_ct.h"
b2fdf3d0 61#include "en/mod_hdr.h"
0d9f9647
VB		 62#include "en/tc_priv.h"
63#include "en/tc_tun_encap.h"
0027d70c 64#include "en/tc/sample.h"
04de7dda 65#include "lib/devcom.h"
9272e3df 66#include "lib/geneve.h"
ae430332 67#include "lib/fs_chains.h"
7a978759 68#include "diag/en_tc_tracepoint.h"
1fe3e316 69#include <asm/div64.h>
14fe2471
MD		 70#include "lag.h"
71#include "lag_mp.h"
e8f887ac 72
6a064674 73#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 74#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 75
acff797c 76#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 77#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 78
8f1e0b97
PB		 79struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
80 [CHAIN_TO_REG] = {
81 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
82 .moffset = 0,
ed2fe7ba 83 .mlen = 16,
8f1e0b97 84 },
10742efc
VB		 85 [VPORT_TO_REG] = {
86 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 87 .moffset = 16,
88 .mlen = 16,
10742efc 89 },
0a7fcb78
PB		 90 [TUNNEL_TO_REG] = {
91 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 92 .moffset = 8,
93 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 94 .soffset = MLX5_BYTE_OFF(fte_match_param,
95 misc_parameters_2.metadata_reg_c_1),
96 },
4c3844d9 97 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 98 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 99 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
100 [MARK_TO_REG] = mark_to_reg_ct,
101 [LABELS_TO_REG] = labels_to_reg_ct,
102 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 103 /* For NIC rules we store the restore metadata directly
c7569097
AL		 104 * into reg_b that is passed to SW since we don't
105 * jump between steering domains.
106 */
107 [NIC_CHAIN_TO_REG] = {
108 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
109 .moffset = 0,
ed2fe7ba 110 .mlen = 16,
c7569097 111 },
aedd133d 112 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 113};
114
9ba33339
RD		 115/* To avoid false lock dependency warning set the tc_ht lock
116 * class different than the lock class of the ht being used when deleting
117 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
118 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
119 * it's different than the ht->mutex here.
120 */
121static struct lock_class_key tc_ht_lock_key;
122
0a7fcb78
PB		 123static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
124
125void
126mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
127 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 128 u32 val,
0a7fcb78
PB		 129 u32 mask)
130{
ed2fe7ba 131 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 132 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 133 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 134 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 135 u32 max_mask = GENMASK(match_len - 1, 0);
136 __be32 curr_mask_be, curr_val_be;
137 u32 curr_mask, curr_val;
0a7fcb78
PB		 138
139 fmask = headers_c + soffset;
140 fval = headers_v + soffset;
141
ed2fe7ba
PB		 142 memcpy(&curr_mask_be, fmask, 4);
143 memcpy(&curr_val_be, fval, 4);
144
145 curr_mask = be32_to_cpu(curr_mask_be);
146 curr_val = be32_to_cpu(curr_val_be);
147
148 //move to correct offset
149 WARN_ON(mask > max_mask);
150 mask <<= moffset;
151 val <<= moffset;
152 max_mask <<= moffset;
153
154 //zero val and mask
155 curr_mask &= ~max_mask;
156 curr_val &= ~max_mask;
0a7fcb78 157
ed2fe7ba
PB		 158 //add current to mask
159 curr_mask |= mask;
160 curr_val |= val;
161
162 //back to be32 and write
163 curr_mask_be = cpu_to_be32(curr_mask);
164 curr_val_be = cpu_to_be32(curr_val);
165
166 memcpy(fmask, &curr_mask_be, 4);
167 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 168
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
170}
171
7e36feeb
PB		 172void
173mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
174 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 175 u32 *val,
7e36feeb
PB		 176 u32 *mask)
177{
ed2fe7ba 178 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 179 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 180 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 181 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 182 u32 max_mask = GENMASK(match_len - 1, 0);
183 __be32 curr_mask_be, curr_val_be;
184 u32 curr_mask, curr_val;
7e36feeb
PB		 185
186 fmask = headers_c + soffset;
187 fval = headers_v + soffset;
188
ed2fe7ba
PB		 189 memcpy(&curr_mask_be, fmask, 4);
190 memcpy(&curr_val_be, fval, 4);
191
192 curr_mask = be32_to_cpu(curr_mask_be);
193 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 194
ed2fe7ba
PB		 195 *mask = (curr_mask >> moffset) & max_mask;
196 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 197}
198
0a7fcb78 199int
c7b9038d
VB		 200mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
201 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
202 enum mlx5_flow_namespace_type ns,
203 enum mlx5e_tc_attr_to_reg type,
204 u32 data)
0a7fcb78
PB		 205{
206 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
207 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
208 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
209 char *modact;
210 int err;
211
aedd133d 212 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 213 if (err)
214 return err;
215
216 modact = mod_hdr_acts->actions +
217 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
218
219 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 220 if (mlen == 32)
0a7fcb78
PB		 221 mlen = 0;
222
223 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
224 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 225 MLX5_SET(set_action_in, modact, offset, moffset);
226 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 227 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 228 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 229 mod_hdr_acts->num_actions++;
230
c7b9038d 231 return err;
0a7fcb78
PB		 232}
233
aedd133d
AL		 234static struct mlx5_tc_ct_priv *
235get_ct_priv(struct mlx5e_priv *priv)
236{
237 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
238 struct mlx5_rep_uplink_priv *uplink_priv;
239 struct mlx5e_rep_priv *uplink_rpriv;
240
e8711402 241 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 242 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
243 uplink_priv = &uplink_rpriv->uplink_priv;
244
245 return uplink_priv->ct_priv;
246 }
247
248 return priv->fs.tc.ct;
249}
250
0027d70c 251static struct mlx5e_tc_psample *
f94d6389
CM		 252get_sample_priv(struct mlx5e_priv *priv)
253{
254 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
255 struct mlx5_rep_uplink_priv *uplink_priv;
256 struct mlx5e_rep_priv *uplink_rpriv;
257
258 if (is_mdev_switchdev_mode(priv->mdev)) {
259 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
260 uplink_priv = &uplink_rpriv->uplink_priv;
261
0027d70c 262 return uplink_priv->tc_psample;
f94d6389
CM		 263 }
264
265 return NULL;
266}
f94d6389 267
aedd133d
AL		 268struct mlx5_flow_handle *
269mlx5_tc_rule_insert(struct mlx5e_priv *priv,
270 struct mlx5_flow_spec *spec,
271 struct mlx5_flow_attr *attr)
272{
273 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
274
e8711402 275 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 276 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
277
278 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
279}
280
281void
282mlx5_tc_rule_delete(struct mlx5e_priv *priv,
283 struct mlx5_flow_handle *rule,
284 struct mlx5_flow_attr *attr)
285{
286 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
287
e8711402 288 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 289 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
290
291 return;
292 }
293
294 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
295}
296
c7b9038d
VB		 297int
298mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
299 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
300 enum mlx5_flow_namespace_type ns,
301 enum mlx5e_tc_attr_to_reg type,
302 u32 data)
303{
304 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
305
306 return ret < 0 ? ret : 0;
307}
308
309void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
310 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
311 enum mlx5e_tc_attr_to_reg type,
312 int act_id, u32 data)
313{
314 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
315 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
316 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
317 char *modact;
318
319 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
320
321 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 322 if (mlen == 32)
c7b9038d
VB		 323 mlen = 0;
324
325 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
326 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 327 MLX5_SET(set_action_in, modact, offset, moffset);
328 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 329 MLX5_SET(set_action_in, modact, data, data);
330}
331
77ab67b7
OG		 332struct mlx5e_hairpin {
333 struct mlx5_hairpin *pair;
334
335 struct mlx5_core_dev *func_mdev;
3f6d08d1 336 struct mlx5e_priv *func_priv;
77ab67b7 337 u32 tdn;
a6696735 338 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 339
340 int num_channels;
341 struct mlx5e_rqt indir_rqt;
a6696735 342 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 343 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 344};
345
5c65c564
OG		 346struct mlx5e_hairpin_entry {
347 /* a node of a hash table which keeps all the hairpin entries */
348 struct hlist_node hairpin_hlist;
349
73edca73
VB		 350 /* protects flows list */
351 spinlock_t flows_lock;
5c65c564
OG		 352 /* flows sharing the same hairpin */
353 struct list_head flows;
db76ca24
VB		 354 /* hpe's that were not fully initialized when dead peer update event
355 * function traversed them.
356 */
357 struct list_head dead_peer_wait_list;
5c65c564 358
d8822868 359 u16 peer_vhca_id;
106be53b 360 u8 prio;
5c65c564 361 struct mlx5e_hairpin *hp;
e4f9abbd 362 refcount_t refcnt;
db76ca24 363 struct completion res_ready;
5c65c564
OG		 364};
365
5a7e5bcb
VB		 366static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
367 struct mlx5e_tc_flow *flow);
368
0d9f9647 369struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 370{
371 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
372 return ERR_PTR(-EINVAL);
373 return flow;
374}
375
0d9f9647 376void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 377{
378 if (refcount_dec_and_test(&flow->refcnt)) {
379 mlx5e_tc_del_flow(priv, flow);
c5d326b2 380 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 381 }
382}
383
aedd133d 384bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 385{
386 return flow_flag_test(flow, ESWITCH);
387}
388
84179981
PB		 389static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390{
391 return flow_flag_test(flow, FT);
392}
393
0d9f9647 394bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 395{
396 return flow_flag_test(flow, OFFLOADED);
397}
398
b2fdf3d0 399static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 400{
b2fdf3d0
PB		 401 return mlx5e_is_eswitch_flow(flow) ?
402 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 403}
404
dd58edc3 405static struct mod_hdr_tbl *
b2fdf3d0 406get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 407{
408 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
409
b2fdf3d0
PB		 410 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
411 &esw->offloads.mod_hdr :
dd58edc3
VB		 412 &priv->fs.tc.mod_hdr;
413}
414
11c9c548
OG		 415static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
416 struct mlx5e_tc_flow *flow,
417 struct mlx5e_tc_flow_parse_attr *parse_attr)
418{
b2fdf3d0
PB		 419 struct mlx5_modify_hdr *modify_hdr;
420 struct mlx5e_mod_hdr_handle *mh;
11c9c548 421
b2fdf3d0
PB		 422 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
423 get_flow_name_space(flow),
424 &parse_attr->mod_hdr_acts);
425 if (IS_ERR(mh))
426 return PTR_ERR(mh);
11c9c548 427
b2fdf3d0 428 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 429 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 430 flow->mh = mh;
11c9c548
OG		 431
432 return 0;
11c9c548
OG		 433}
434
435static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
436 struct mlx5e_tc_flow *flow)
437{
5a7e5bcb 438 /* flow wasn't fully initialized */
dd58edc3 439 if (!flow->mh)
5a7e5bcb
VB		 440 return;
441
b2fdf3d0
PB		 442 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
443 flow->mh);
dd58edc3 444 flow->mh = NULL;
11c9c548
OG		 445}
446
77ab67b7
OG		 447static
448struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
449{
b1c2f631 450 struct mlx5_core_dev *mdev;
77ab67b7
OG		 451 struct net_device *netdev;
452 struct mlx5e_priv *priv;
453
b1c2f631
DC		 454 netdev = dev_get_by_index(net, ifindex);
455 if (!netdev)
456 return ERR_PTR(-ENODEV);
457
77ab67b7 458 priv = netdev_priv(netdev);
b1c2f631
DC		 459 mdev = priv->mdev;
460 dev_put(netdev);
461
462 /* Mirred tc action holds a refcount on the ifindex net_device (see
463 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
464 * after dev_put(netdev), while we're in the context of adding a tc flow.
465 *
466 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
467 * stored in a hairpin object, which exists until all flows, that refer to it, get
468 * removed.
469 *
470 * On the other hand, after a hairpin object has been created, the peer net_device may
471 * be removed/unbound while there are still some hairpin flows that are using it. This
472 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
473 * NETDEV_UNREGISTER event of the peer net_device.
474 */
475 return mdev;
77ab67b7
OG		 476}
477
478static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
479{
a6696735 480 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 481 int err;
482
a6696735
MM		 483 builder = mlx5e_tir_builder_alloc(false);
484 if (!builder)
485 return -ENOMEM;
486
77ab67b7
OG		 487 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
488 if (err)
a6696735 489 goto out;
77ab67b7 490
a6696735
MM		 491 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
492 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 493 if (err)
494 goto create_tir_err;
495
a6696735
MM		 496out:
497 mlx5e_tir_builder_free(builder);
498 return err;
77ab67b7
OG		 499
500create_tir_err:
501 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 502
503 goto out;
77ab67b7
OG		 504}
505
506static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
507{
a6696735 508 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 509 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
510}
511
3f6d08d1
OG		 512static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
513{
3f6d08d1
OG		 514 struct mlx5e_priv *priv = hp->func_priv;
515 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 516 struct mlx5e_rss_params_indir *indir;
517 int err;
3f6d08d1 518
06e9f13a
MM		 519 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
520 if (!indir)
3f6d08d1
OG		 521 return -ENOMEM;
522
43befe99 523 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 524 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 525 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
526 indir);
3f6d08d1 527
06e9f13a 528 kvfree(indir);
3f6d08d1
OG		 529 return err;
530}
531
532static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
533{
534 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 535 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 536 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 537 struct mlx5e_tir_builder *builder;
538 int err = 0;
539
540 builder = mlx5e_tir_builder_alloc(false);
541 if (!builder)
542 return -ENOMEM;
543
43ec0f41 544 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 545
546 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 547 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 548
65d6b6e5 549 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 550
a6696735
MM		 551 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
552 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
553 false);
43ec0f41 554 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 555
a6696735 556 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 557 if (err) {
558 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
559 goto err_destroy_tirs;
560 }
a6696735
MM		 561
562 mlx5e_tir_builder_clear(builder);
3f6d08d1 563 }
3f6d08d1 564
a6696735
MM		 565out:
566 mlx5e_tir_builder_free(builder);
3f6d08d1 567 return err;
a6696735
MM		 568
569err_destroy_tirs:
570 max_tt = tt;
571 for (tt = 0; tt < max_tt; tt++)
572 mlx5e_tir_destroy(&hp->indir_tir[tt]);
573
574 goto out;
3f6d08d1
OG		 575}
576
577static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
578{
579 int tt;
580
581 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 582 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 583}
584
585static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
586 struct ttc_params *ttc_params)
587{
588 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
589 int tt;
590
591 memset(ttc_params, 0, sizeof(*ttc_params));
592
bc29764e
MG		 593 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
594 MLX5_FLOW_NAMESPACE_KERNEL);
595 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
596 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
597 ttc_params->dests[tt].tir_num =
598 tt == MLX5_TT_ANY ?
599 mlx5e_tir_get_tirn(&hp->direct_tir) :
600 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
601 }
3f6d08d1 602
3f6d08d1
OG		 603 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
604 ft_attr->prio = MLX5E_TC_PRIO;
605}
606
607static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
608{
609 struct mlx5e_priv *priv = hp->func_priv;
610 struct ttc_params ttc_params;
611 int err;
612
613 err = mlx5e_hairpin_create_indirect_rqt(hp);
614 if (err)
615 return err;
616
617 err = mlx5e_hairpin_create_indirect_tirs(hp);
618 if (err)
619 goto err_create_indirect_tirs;
620
621 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 622 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
623 if (IS_ERR(hp->ttc)) {
624 err = PTR_ERR(hp->ttc);
3f6d08d1 625 goto err_create_ttc_table;
f4b45940 626 }
3f6d08d1
OG		 627
628 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 629 hp->num_channels,
630 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 631
632 return 0;
633
634err_create_ttc_table:
635 mlx5e_hairpin_destroy_indirect_tirs(hp);
636err_create_indirect_tirs:
06e9f13a 637 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 638
639 return err;
640}
641
642static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
643{
f4b45940 644 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 645 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 646 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 647}
648
77ab67b7
OG		 649static struct mlx5e_hairpin *
650mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
651 int peer_ifindex)
652{
653 struct mlx5_core_dev *func_mdev, *peer_mdev;
654 struct mlx5e_hairpin *hp;
655 struct mlx5_hairpin *pair;
656 int err;
657
658 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
659 if (!hp)
660 return ERR_PTR(-ENOMEM);
661
662 func_mdev = priv->mdev;
663 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 664 if (IS_ERR(peer_mdev)) {
665 err = PTR_ERR(peer_mdev);
666 goto create_pair_err;
667 }
77ab67b7
OG		 668
669 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
670 if (IS_ERR(pair)) {
671 err = PTR_ERR(pair);
672 goto create_pair_err;
673 }
674 hp->pair = pair;
675 hp->func_mdev = func_mdev;
3f6d08d1
OG		 676 hp->func_priv = priv;
677 hp->num_channels = params->num_channels;
77ab67b7
OG		 678
679 err = mlx5e_hairpin_create_transport(hp);
680 if (err)
681 goto create_transport_err;
682
3f6d08d1
OG		 683 if (hp->num_channels > 1) {
684 err = mlx5e_hairpin_rss_init(hp);
685 if (err)
686 goto rss_init_err;
687 }
688
77ab67b7
OG		 689 return hp;
690
3f6d08d1
OG		 691rss_init_err:
692 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 693create_transport_err:
694 mlx5_core_hairpin_destroy(hp->pair);
695create_pair_err:
696 kfree(hp);
697 return ERR_PTR(err);
698}
699
700static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
701{
3f6d08d1
OG		 702 if (hp->num_channels > 1)
703 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 704 mlx5e_hairpin_destroy_transport(hp);
705 mlx5_core_hairpin_destroy(hp->pair);
706 kvfree(hp);
707}
708
106be53b
OG		 709static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
710{
711 return (peer_vhca_id << 16 | prio);
712}
713
5c65c564 714static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 715 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 716{
717 struct mlx5e_hairpin_entry *hpe;
106be53b 718 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 719
720 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 721 hairpin_hlist, hash_key) {
e4f9abbd
VB		 722 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
723 refcount_inc(&hpe->refcnt);
5c65c564 724 return hpe;
e4f9abbd 725 }
5c65c564
OG		 726 }
727
728 return NULL;
729}
730
e4f9abbd
VB		 731static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
732 struct mlx5e_hairpin_entry *hpe)
733{
734 /* no more hairpin flows for us, release the hairpin pair */
b32accda 735 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 736 return;
b32accda
VB		 737 hash_del(&hpe->hairpin_hlist);
738 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 739
db76ca24
VB		 740 if (!IS_ERR_OR_NULL(hpe->hp)) {
741 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
742 dev_name(hpe->hp->pair->peer_mdev->device));
743
744 mlx5e_hairpin_destroy(hpe->hp);
745 }
e4f9abbd
VB		 746
747 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 748 kfree(hpe);
749}
750
106be53b
OG		 751#define UNKNOWN_MATCH_PRIO 8
752
753static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 754 struct mlx5_flow_spec *spec, u8 *match_prio,
755 struct netlink_ext_ack *extack)
106be53b
OG		 756{
757 void *headers_c, *headers_v;
758 u8 prio_val, prio_mask = 0;
759 bool vlan_present;
760
761#ifdef CONFIG_MLX5_CORE_EN_DCB
762 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 763 NL_SET_ERR_MSG_MOD(extack,
764 "only PCP trust state supported for hairpin");
106be53b
OG		 765 return -EOPNOTSUPP;
766 }
767#endif
768 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
769 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
770
771 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
772 if (vlan_present) {
773 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
774 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
775 }
776
777 if (!vlan_present || !prio_mask) {
778 prio_val = UNKNOWN_MATCH_PRIO;
779 } else if (prio_mask != 0x7) {
e98bedf5
EB		 780 NL_SET_ERR_MSG_MOD(extack,
781 "masked priority match not supported for hairpin");
106be53b
OG		 782 return -EOPNOTSUPP;
783 }
784
785 *match_prio = prio_val;
786 return 0;
787}
788
5c65c564
OG		 789static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
790 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 791 struct mlx5e_tc_flow_parse_attr *parse_attr,
792 struct netlink_ext_ack *extack)
5c65c564 793{
98b66cb1 794 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 795 struct mlx5_hairpin_params params;
d8822868 796 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 797 struct mlx5e_hairpin_entry *hpe;
798 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 799 u64 link_speed64;
800 u32 link_speed;
106be53b 801 u8 match_prio;
d8822868 802 u16 peer_id;
5c65c564
OG		 803 int err;
804
d8822868 805 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 806 if (IS_ERR(peer_mdev)) {
807 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
808 return PTR_ERR(peer_mdev);
809 }
810
d8822868 811 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 812 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 813 return -EOPNOTSUPP;
814 }
815
d8822868 816 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 817 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
818 extack);
106be53b
OG		 819 if (err)
820 return err;
b32accda
VB		 821
822 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 823 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 824 if (hpe) {
825 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
826 wait_for_completion(&hpe->res_ready);
827
828 if (IS_ERR(hpe->hp)) {
829 err = -EREMOTEIO;
830 goto out_err;
831 }
5c65c564 832 goto attach_flow;
db76ca24 833 }
5c65c564
OG		 834
835 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 836 if (!hpe) {
db76ca24
VB		 837 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
838 return -ENOMEM;
b32accda 839 }
5c65c564 840
73edca73 841 spin_lock_init(&hpe->flows_lock);
5c65c564 842 INIT_LIST_HEAD(&hpe->flows);
db76ca24 843 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 844 hpe->peer_vhca_id = peer_id;
106be53b 845 hpe->prio = match_prio;
e4f9abbd 846 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 847 init_completion(&hpe->res_ready);
848
849 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
850 hash_hairpin_info(peer_id, match_prio));
851 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 852
6cdc686a 853 params.log_data_size = 16;
5c65c564
OG		 854 params.log_data_size = min_t(u8, params.log_data_size,
855 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
856 params.log_data_size = max_t(u8, params.log_data_size,
857 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 858
eb9180f7
OG		 859 params.log_num_packets = params.log_data_size -
860 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
861 params.log_num_packets = min_t(u8, params.log_num_packets,
862 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
863
864 params.q_counter = priv->q_counter;
3f6d08d1 865 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 866 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 867 link_speed = max_t(u32, link_speed, 50000);
868 link_speed64 = link_speed;
869 do_div(link_speed64, 50000);
870 params.num_channels = link_speed64;
871
5c65c564 872 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 873 hpe->hp = hp;
874 complete_all(&hpe->res_ready);
5c65c564
OG		 875 if (IS_ERR(hp)) {
876 err = PTR_ERR(hp);
db76ca24 877 goto out_err;
5c65c564
OG		 878 }
879
eb9180f7 880 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 881 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 882 dev_name(hp->pair->peer_mdev->device),
eb9180f7 883 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 884
5c65c564 885attach_flow:
3f6d08d1 886 if (hpe->hp->num_channels > 1) {
226f2ca3 887 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 888 flow->attr->nic_attr->hairpin_ft =
889 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 890 } else {
a6696735 891 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 892 }
b32accda 893
e4f9abbd 894 flow->hpe = hpe;
73edca73 895 spin_lock(&hpe->flows_lock);
5c65c564 896 list_add(&flow->hairpin, &hpe->flows);
73edca73 897 spin_unlock(&hpe->flows_lock);
3f6d08d1 898
5c65c564
OG		 899 return 0;
900
db76ca24
VB		 901out_err:
902 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 903 return err;
904}
905
906static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
907 struct mlx5e_tc_flow *flow)
908{
5a7e5bcb 909 /* flow wasn't fully initialized */
e4f9abbd 910 if (!flow->hpe)
5a7e5bcb
VB		 911 return;
912
73edca73 913 spin_lock(&flow->hpe->flows_lock);
5c65c564 914 list_del(&flow->hairpin);
73edca73
VB		 915 spin_unlock(&flow->hpe->flows_lock);
916
e4f9abbd
VB		 917 mlx5e_hairpin_put(priv, flow->hpe);
918 flow->hpe = NULL;
5c65c564
OG		 919}
920
08247066
AL		 921struct mlx5_flow_handle *
922mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
923 struct mlx5_flow_spec *spec,
c620b772 924 struct mlx5_flow_attr *attr)
e8f887ac 925{
08247066 926 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 927 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 928 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 929 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 930 struct mlx5_flow_destination dest[2] = {};
66958ed9 931 struct mlx5_flow_act flow_act = {
3bc4b7bf 932 .action = attr->action,
bb0ee7dc 933 .flags = FLOW_ACT_NO_APPEND,
66958ed9 934 };
08247066 935 struct mlx5_flow_handle *rule;
c7569097 936 struct mlx5_flow_table *ft;
08247066 937 int dest_ix = 0;
e8f887ac 938
bb0ee7dc 939 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 940 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 941
aedd133d
AL		 942 if (attr->dest_ft) {
943 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
944 dest[dest_ix].ft = attr->dest_ft;
945 dest_ix++;
946 } else if (nic_attr->hairpin_ft) {
08247066 947 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 948 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 949 dest_ix++;
c620b772 950 } else if (nic_attr->hairpin_tirn) {
08247066 951 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 952 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 953 dest_ix++;
3f6d08d1
OG		 954 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 956 if (attr->dest_chain) {
957 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
958 attr->dest_chain, 1,
959 MLX5E_TC_FT_LEVEL);
960 if (IS_ERR(dest[dest_ix].ft))
961 return ERR_CAST(dest[dest_ix].ft);
962 } else {
6783f0a2 963 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 964 }
3f6d08d1 965 dest_ix++;
5c65c564 966 }
aad7e08d 967
c7569097
AL		 968 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
969 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
970 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
971
08247066 972 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 973 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 974 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 975 dest_ix++;
aad7e08d
AV		 976 }
977
08247066 978 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 979 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 980
6a064674
AL		 981 mutex_lock(&tc->t_lock);
982 if (IS_ERR_OR_NULL(tc->t)) {
983 /* Create the root table here if doesn't exist yet */
984 tc->t =
c7569097 985 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 986
987 if (IS_ERR(tc->t)) {
988 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 989 netdev_err(priv->netdev,
990 "Failed to create tc offload table\n");
c7569097
AL		 991 rule = ERR_CAST(priv->fs.tc.t);
992 goto err_ft_get;
e8f887ac 993 }
e8f887ac 994 }
08247066 995 mutex_unlock(&tc->t_lock);
e8f887ac 996
aedd133d
AL		 997 if (attr->chain || attr->prio)
998 ft = mlx5_chains_get_table(nic_chains,
999 attr->chain, attr->prio,
1000 MLX5E_TC_FT_LEVEL);
1001 else
1002 ft = attr->ft;
1003
c7569097
AL		 1004 if (IS_ERR(ft)) {
1005 rule = ERR_CAST(ft);
1006 goto err_ft_get;
1007 }
1008
c620b772 1009 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1010 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1011
c7569097 1012 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1013 &flow_act, dest, dest_ix);
1014 if (IS_ERR(rule))
c7569097 1015 goto err_rule;
08247066
AL		 1016
1017 return rule;
c7569097
AL		 1018
1019err_rule:
aedd133d
AL		 1020 if (attr->chain || attr->prio)
1021 mlx5_chains_put_table(nic_chains,
1022 attr->chain, attr->prio,
1023 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1024err_ft_get:
1025 if (attr->dest_chain)
1026 mlx5_chains_put_table(nic_chains,
1027 attr->dest_chain, 1,
1028 MLX5E_TC_FT_LEVEL);
1029
1030 return ERR_CAST(rule);
08247066
AL		 1031}
1032
1033static int
1034mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1035 struct mlx5e_tc_flow *flow,
1036 struct netlink_ext_ack *extack)
1037{
c6cfe113 1038 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1039 struct mlx5_flow_attr *attr = flow->attr;
08247066 1040 struct mlx5_core_dev *dev = priv->mdev;
97a8d29a 1041 struct mlx5_fc *counter;
08247066
AL		 1042 int err;
1043
c6cfe113
RD		 1044 parse_attr = attr->parse_attr;
1045
08247066
AL		 1046 if (flow_flag_test(flow, HAIRPIN)) {
1047 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1048 if (err)
1049 return err;
1050 }
1051
1052 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1053 counter = mlx5_fc_create(dev, true);
1054 if (IS_ERR(counter))
1055 return PTR_ERR(counter);
1056
1057 attr->counter = counter;
1058 }
1059
1060 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1061 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1062 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1063 if (err)
1064 return err;
1065 }
1066
aedd133d
AL		 1067 if (flow_flag_test(flow, CT))
1068 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1069 attr, &parse_attr->mod_hdr_acts);
1070 else
1071 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1072 attr);
aad7e08d 1073
a2b7189b 1074 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1075}
1076
08247066 1077void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1078 struct mlx5_flow_handle *rule,
1079 struct mlx5_flow_attr *attr)
08247066 1080{
c7569097
AL		 1081 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1082
08247066 1083 mlx5_del_flow_rules(rule);
c7569097 1084
aedd133d
AL		 1085 if (attr->chain || attr->prio)
1086 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1087 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1088
1089 if (attr->dest_chain)
1090 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1091 MLX5E_TC_FT_LEVEL);
08247066
AL		 1092}
1093
d85cdccb
OG		 1094static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1095 struct mlx5e_tc_flow *flow)
1096{
c620b772 1097 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1098 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1099
c7569097
AL		 1100 flow_flag_clear(flow, OFFLOADED);
1101
aedd133d
AL		 1102 if (flow_flag_test(flow, CT))
1103 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1104 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1105 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1106
c7569097
AL		 1107 /* Remove root table if no rules are left to avoid
1108 * extra steering hops.
1109 */
b6fac0b4 1110 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1111 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1112 !IS_ERR_OR_NULL(tc->t)) {
1113 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1114 priv->fs.tc.t = NULL;
1115 }
b6fac0b4 1116 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1117
aedd133d
AL		 1118 kvfree(attr->parse_attr);
1119
513f8f7f 1120 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1121 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1122
aedd133d
AL		 1123 mlx5_fc_destroy(priv->mdev, attr->counter);
1124
226f2ca3 1125 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1126 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1127
1128 kfree(flow->attr);
d85cdccb
OG		 1129}
1130
0d9f9647 1131struct mlx5_flow_handle *
6d2a3ed0
OG		 1132mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1133 struct mlx5e_tc_flow *flow,
1134 struct mlx5_flow_spec *spec,
c620b772 1135 struct mlx5_flow_attr *attr)
6d2a3ed0 1136{
1ef3018f 1137 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1138 struct mlx5_flow_handle *rule;
4c3844d9 1139
89e39467
PB		 1140 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1141 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1142
1ef3018f
PB		 1143 if (flow_flag_test(flow, CT)) {
1144 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1145
69e2916e 1146 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1147 flow, spec, attr,
1ef3018f 1148 mod_hdr_acts);
f94d6389 1149 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1150 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1151 mlx5e_tc_get_flow_tun_id(flow));
69e2916e
PB		 1152 } else {
1153 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1154 }
6d2a3ed0 1155
6d2a3ed0
OG		 1156 if (IS_ERR(rule))
1157 return rule;
1158
c620b772 1159 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1160 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1161 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1162 if (flow_flag_test(flow, CT))
1163 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1164 else
1165 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1166 return flow->rule[1];
1167 }
1168 }
1169
6d2a3ed0
OG		 1170 return rule;
1171}
1172
0d9f9647
VB		 1173void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1174 struct mlx5e_tc_flow *flow,
1175 struct mlx5_flow_attr *attr)
6d2a3ed0 1176{
226f2ca3 1177 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1178
89e39467
PB		 1179 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1180 goto offload_rule_0;
1181
4c3844d9 1182 if (flow_flag_test(flow, CT)) {
aedd133d 1183 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1184 return;
1185 }
1186
f94d6389 1187 if (flow_flag_test(flow, SAMPLE)) {
0027d70c 1188 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
f94d6389
CM		 1189 return;
1190 }
f94d6389 1191
c620b772 1192 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1193 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1194
89e39467 1195offload_rule_0:
6d2a3ed0
OG		 1196 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1197}
1198
0d9f9647 1199struct mlx5_flow_handle *
5dbe906f
PB		 1200mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1201 struct mlx5e_tc_flow *flow,
178f69b4 1202 struct mlx5_flow_spec *spec)
5dbe906f 1203{
c620b772 1204 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1205 struct mlx5_flow_handle *rule;
1206
c620b772
AL		 1207 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1208 if (!slow_attr)
1209 return ERR_PTR(-ENOMEM);
5dbe906f 1210
c620b772
AL		 1211 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1212 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1213 slow_attr->esw_attr->split_count = 0;
1214 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1215
1216 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1217 if (!IS_ERR(rule))
226f2ca3 1218 flow_flag_set(flow, SLOW);
5dbe906f 1219
c620b772
AL		 1220 kfree(slow_attr);
1221
5dbe906f
PB		 1222 return rule;
1223}
1224
0d9f9647
VB		 1225void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1226 struct mlx5e_tc_flow *flow)
5dbe906f 1227{
c620b772 1228 struct mlx5_flow_attr *slow_attr;
178f69b4 1229
c620b772 1230 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1231 if (!slow_attr) {
1232 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1233 return;
1234 }
c620b772
AL		 1235
1236 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1237 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1238 slow_attr->esw_attr->split_count = 0;
1239 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1240 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1241 flow_flag_clear(flow, SLOW);
c620b772 1242 kfree(slow_attr);
5dbe906f
PB		 1243}
1244
ad86755b
VB		 1245/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1246 * function.
1247 */
1248static void unready_flow_add(struct mlx5e_tc_flow *flow,
1249 struct list_head *unready_flows)
1250{
1251 flow_flag_set(flow, NOT_READY);
1252 list_add_tail(&flow->unready, unready_flows);
1253}
1254
1255/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1256 * function.
1257 */
1258static void unready_flow_del(struct mlx5e_tc_flow *flow)
1259{
1260 list_del(&flow->unready);
1261 flow_flag_clear(flow, NOT_READY);
1262}
1263
b4a23329
RD		 1264static void add_unready_flow(struct mlx5e_tc_flow *flow)
1265{
1266 struct mlx5_rep_uplink_priv *uplink_priv;
1267 struct mlx5e_rep_priv *rpriv;
1268 struct mlx5_eswitch *esw;
1269
1270 esw = flow->priv->mdev->priv.eswitch;
1271 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1272 uplink_priv = &rpriv->uplink_priv;
1273
ad86755b
VB		 1274 mutex_lock(&uplink_priv->unready_flows_lock);
1275 unready_flow_add(flow, &uplink_priv->unready_flows);
1276 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1277}
1278
1279static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1280{
ad86755b
VB		 1281 struct mlx5_rep_uplink_priv *uplink_priv;
1282 struct mlx5e_rep_priv *rpriv;
1283 struct mlx5_eswitch *esw;
1284
1285 esw = flow->priv->mdev->priv.eswitch;
1286 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1287 uplink_priv = &rpriv->uplink_priv;
1288
1289 mutex_lock(&uplink_priv->unready_flows_lock);
1290 unready_flow_del(flow);
1291 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1292}
1293
10742efc
VB		 1294static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1295
a508728a 1296bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1297{
1298 struct mlx5_core_dev *out_mdev, *route_mdev;
1299 struct mlx5e_priv *out_priv, *route_priv;
1300
1301 out_priv = netdev_priv(out_dev);
1302 out_mdev = out_priv->mdev;
1303 route_priv = netdev_priv(route_dev);
1304 route_mdev = route_priv->mdev;
1305
1306 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1307 route_mdev->coredev_type != MLX5_COREDEV_VF)
1308 return false;
1309
1310 return same_hw_devs(out_priv, route_priv);
1311}
1312
a508728a 1313int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1314{
1315 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1316 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1317 struct mlx5_core_dev *route_mdev;
1318 struct mlx5_eswitch *esw;
1319 u16 vhca_id;
1320 int err;
1321
1322 out_priv = netdev_priv(out_dev);
1323 esw = out_priv->mdev->priv.eswitch;
1324 route_priv = netdev_priv(route_dev);
1325 route_mdev = route_priv->mdev;
1326
1327 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1328 if (mlx5_lag_is_active(out_priv->mdev)) {
1329 /* In lag case we may get devices from different eswitch instances.
1330 * If we failed to get vport num, it means, mostly, that we on the wrong
1331 * eswitch.
1332 */
1333 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1334 if (err != -ENOENT)
1335 return err;
1336
1337 devcom = out_priv->mdev->priv.devcom;
1338 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1339 if (!esw)
1340 return -ENODEV;
1341 }
1342
10742efc 1343 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1344 if (devcom)
1345 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1346 return err;
1347}
1348
c7b9038d
VB		 1349int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1350 struct mlx5e_tc_flow_parse_attr *parse_attr,
1351 struct mlx5e_tc_flow *flow)
1352{
1353 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1354 struct mlx5_modify_hdr *mod_hdr;
1355
1356 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1357 get_flow_name_space(flow),
1358 mod_hdr_acts->num_actions,
1359 mod_hdr_acts->actions);
1360 if (IS_ERR(mod_hdr))
1361 return PTR_ERR(mod_hdr);
1362
1363 WARN_ON(flow->attr->modify_hdr);
1364 flow->attr->modify_hdr = mod_hdr;
1365
1366 return 0;
1367}
1368
c83954ab 1369static int
74491de9 1370mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1371 struct mlx5e_tc_flow *flow,
1372 struct netlink_ext_ack *extack)
adb4c123
OG		 1373{
1374 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1375 struct mlx5e_tc_flow_parse_attr *parse_attr;
1376 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1377 bool vf_tun = false, encap_valid = true;
fe7738eb 1378 struct net_device *encap_dev = NULL;
c620b772 1379 struct mlx5_esw_flow_attr *esw_attr;
3c37745e
OG		 1380 struct mlx5e_rep_priv *rpriv;
1381 struct mlx5e_priv *out_priv;
97a8d29a 1382 struct mlx5_fc *counter;
39ac237c 1383 u32 max_prio, max_chain;
0ad060ee 1384 int err = 0;
f493f155 1385 int out_index;
8b32580d 1386
84179981
PB		 1387 /* We check chain range only for tc flows.
1388 * For ft flows, we checked attr->chain was originally 0 and set it to
1389 * FDB_FT_CHAIN which is outside tc range.
1390 * See mlx5e_rep_setup_ft_cb().
1391 */
ae430332 1392 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1393 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1394 NL_SET_ERR_MSG_MOD(extack,
1395 "Requested chain is out of supported range");
8914add2
VB		 1396 err = -EOPNOTSUPP;
1397 goto err_out;
bf07aa73
PB		 1398 }
1399
ae430332 1400 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1401 if (attr->prio > max_prio) {
61644c3d
RD		 1402 NL_SET_ERR_MSG_MOD(extack,
1403 "Requested priority is out of supported range");
8914add2
VB		 1404 err = -EOPNOTSUPP;
1405 goto err_out;
bf07aa73 1406 }
e52c2802 1407
777bb800
VB		 1408 if (flow_flag_test(flow, TUN_RX)) {
1409 err = mlx5e_attach_decap_route(priv, flow);
1410 if (err)
8914add2 1411 goto err_out;
777bb800
VB		 1412 }
1413
14e6b038
EC		 1414 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1415 err = mlx5e_attach_decap(priv, flow, extack);
1416 if (err)
8914add2 1417 goto err_out;
14e6b038
EC		 1418 }
1419
c620b772
AL		 1420 parse_attr = attr->parse_attr;
1421 esw_attr = attr->esw_attr;
1422
f493f155 1423 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1424 struct net_device *out_dev;
8c4dc42b
EB		 1425 int mirred_ifindex;
1426
c620b772 1427 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1428 continue;
1429
7040632d 1430 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1431 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1432 if (!out_dev) {
1433 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1434 err = -ENODEV;
1435 goto err_out;
1436 }
733d4f36 1437 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1438 extack, &encap_dev, &encap_valid);
fe7738eb 1439 dev_put(out_dev);
0ad060ee 1440 if (err)
8914add2 1441 goto err_out;
0ad060ee 1442
8914add2
VB		 1443 if (esw_attr->dests[out_index].flags &
1444 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1445 vf_tun = true;
3c37745e
OG		 1446 out_priv = netdev_priv(encap_dev);
1447 rpriv = out_priv->ppriv;
c620b772
AL		 1448 esw_attr->dests[out_index].rep = rpriv->rep;
1449 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1450 }
1451
7d1a3d08
VB		 1452 if (vf_tun && esw_attr->out_count > 1) {
1453 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1454 err = -EOPNOTSUPP;
1455 goto err_out;
1456 }
1457
8b32580d 1458 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1459 if (err)
8914add2 1460 goto err_out;
adb4c123 1461
d5a3c2b6
RD		 1462 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1463 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1464 if (vf_tun) {
1465 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1466 if (err)
1467 goto err_out;
1468 } else {
1469 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1470 if (err)
1471 goto err_out;
1472 }
d7e75a32
OG		 1473 }
1474
b8aee822 1475 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1476 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1477 if (IS_ERR(counter)) {
1478 err = PTR_ERR(counter);
1479 goto err_out;
1480 }
b8aee822
MB		 1481
1482 attr->counter = counter;
1483 }
1484
0ad060ee
RD		 1485 /* we get here if one of the following takes place:
1486 * (1) there's no error
1487 * (2) there's an encap action and we don't have valid neigh
3c37745e 1488 */
bc1d75fa 1489 if (!encap_valid)
178f69b4 1490 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1491 else
6d2a3ed0 1492 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1493
8914add2
VB		 1494 if (IS_ERR(flow->rule[0])) {
1495 err = PTR_ERR(flow->rule[0]);
1496 goto err_out;
1497 }
1498 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1499
1500 return 0;
8914add2
VB		 1501
1502err_out:
1503 flow_flag_set(flow, FAILED);
1504 return err;
aa0cbbae 1505}
d85cdccb 1506
9272e3df
YK		 1507static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1508{
c620b772 1509 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1510 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1511 spec->match_value,
1512 misc_parameters_3);
1513 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1514 headers_v,
1515 geneve_tlv_option_0_data);
1516
1517 return !!geneve_tlv_opt_0_data;
1518}
1519
d85cdccb
OG		 1520static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1521 struct mlx5e_tc_flow *flow)
1522{
1523 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1524 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1525 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1526 bool vf_tun = false;
f493f155 1527 int out_index;
d85cdccb 1528
777bb800 1529 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1530 mlx5e_put_flow_tunnel_id(flow);
1531
12a240a4 1532 if (flow_flag_test(flow, NOT_READY))
b4a23329 1533 remove_unready_flow(flow);
ef06c9ee 1534
226f2ca3
VB		 1535 if (mlx5e_is_offloaded_flow(flow)) {
1536 if (flow_flag_test(flow, SLOW))
178f69b4 1537 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1538 else
1539 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1540 }
909e615d 1541 complete_all(&flow->del_hw_done);
d85cdccb 1542
9272e3df
YK		 1543 if (mlx5_flow_has_geneve_opt(flow))
1544 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1545
513f8f7f 1546 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1547
777bb800
VB		 1548 if (flow->decap_route)
1549 mlx5e_detach_decap_route(priv, flow);
1550
1551 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1552 if (esw_attr->dests[out_index].flags &
1553 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1554 vf_tun = true;
777bb800 1555 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1556 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1557 kfree(attr->parse_attr->tun_info[out_index]);
1558 }
777bb800 1559 }
d7e75a32 1560
aedd133d 1561 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1562
c7b9038d
VB		 1563 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1564 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1565 if (vf_tun && attr->modify_hdr)
1566 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1567 else
1568 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1569 }
bcd6740c 1570 kfree(attr->sample_attr);
8914add2
VB		 1571 kvfree(attr->parse_attr);
1572 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1573
1574 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1575 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1576
1577 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1578 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1579
1580 kfree(flow->attr);
d85cdccb
OG		 1581}
1582
0d9f9647 1583struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1584{
c620b772 1585 return flow->attr->counter;
b8aee822
MB		 1586}
1587
6a06c2f7 1588/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1589void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1590{
1591 struct mlx5e_tc_flow *flow, *tmp;
1592
1593 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1594 mlx5e_flow_put(priv, flow);
1595}
1596
04de7dda
RD		 1597static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1598{
1599 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1600
226f2ca3
VB		 1601 if (!flow_flag_test(flow, ESWITCH) ||
1602 !flow_flag_test(flow, DUP))
04de7dda
RD		 1603 return;
1604
1605 mutex_lock(&esw->offloads.peer_mutex);
1606 list_del(&flow->peer);
1607 mutex_unlock(&esw->offloads.peer_mutex);
1608
226f2ca3 1609 flow_flag_clear(flow, DUP);
04de7dda 1610
eb252c3a
RD		 1611 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1612 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1613 kfree(flow->peer_flow);
1614 }
1615
04de7dda
RD		 1616 flow->peer_flow = NULL;
1617}
1618
1619static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1620{
1621 struct mlx5_core_dev *dev = flow->priv->mdev;
1622 struct mlx5_devcom *devcom = dev->priv.devcom;
1623 struct mlx5_eswitch *peer_esw;
1624
1625 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1626 if (!peer_esw)
1627 return;
1628
1629 __mlx5e_tc_del_fdb_peer_flow(flow);
1630 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1631}
1632
e8f887ac 1633static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1634 struct mlx5e_tc_flow *flow)
e8f887ac 1635{
226f2ca3 1636 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1637 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1638 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1639 } else {
d85cdccb 1640 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1641 }
e8f887ac
AV		 1642}
1643
ee950e5d 1644static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1645{
1646 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1647 struct flow_action *flow_action = &rule->action;
1648 const struct flow_action_entry *act;
1649 int i;
1650
ee950e5d
CM		 1651 if (chain)
1652 return false;
1653
0a7fcb78
PB		 1654 flow_action_for_each(i, act, flow_action) {
1655 switch (act->id) {
1656 case FLOW_ACTION_GOTO:
1657 return true;
ee950e5d
CM		 1658 case FLOW_ACTION_SAMPLE:
1659 return true;
0a7fcb78
PB		 1660 default:
1661 continue;
1662 }
1663 }
1664
1665 return false;
1666}
bbd00f7e 1667
0a7fcb78
PB		 1668static int
1669enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1670 struct flow_dissector_key_enc_opts *opts,
1671 struct netlink_ext_ack *extack,
1672 bool *dont_care)
1673{
1674 struct geneve_opt *opt;
1675 int off = 0;
1676
1677 *dont_care = true;
1678
1679 while (opts->len > off) {
1680 opt = (struct geneve_opt *)&opts->data[off];
1681
1682 if (!(*dont_care) || opt->opt_class || opt->type ||
1683 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1684 *dont_care = false;
1685
c51323ee 1686 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1687 opt->type != U8_MAX) {
0a7fcb78
PB		 1688 NL_SET_ERR_MSG(extack,
1689 "Partial match of tunnel options in chain > 0 isn't supported");
1690 netdev_warn(priv->netdev,
1691 "Partial match of tunnel options in chain > 0 isn't supported");
1692 return -EOPNOTSUPP;
1693 }
1694 }
1695
1696 off += sizeof(struct geneve_opt) + opt->length * 4;
1697 }
1698
1699 return 0;
1700}
1701
1702#define COPY_DISSECTOR(rule, diss_key, dst)\
1703({ \
1704 struct flow_rule *__rule = (rule);\
1705 typeof(dst) __dst = dst;\
1706\
1707 memcpy(__dst,\
1708 skb_flow_dissector_target(__rule->match.dissector,\
1709 diss_key,\
1710 __rule->match.key),\
1711 sizeof(*__dst));\
1712})
1713
1714static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1715 struct mlx5e_tc_flow *flow,
1716 struct flow_cls_offload *f,
1717 struct net_device *filter_dev)
bbd00f7e 1718{
f9e30088 1719 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1720 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1721 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1722 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1723 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1724 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1725 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1726 struct mlx5e_rep_priv *uplink_rpriv;
1727 struct tunnel_match_key tunnel_key;
1728 bool enc_opts_is_dont_care = true;
1729 u32 tun_id, enc_opts_id = 0;
1730 struct mlx5_eswitch *esw;
1731 u32 value, mask;
8f256622 1732 int err;
2e72eb43 1733
0a7fcb78
PB		 1734 esw = priv->mdev->priv.eswitch;
1735 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1736 uplink_priv = &uplink_rpriv->uplink_priv;
1737
1738 memset(&tunnel_key, 0, sizeof(tunnel_key));
1739 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1740 &tunnel_key.enc_control);
1741 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1742 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1743 &tunnel_key.enc_ipv4);
1744 else
1745 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1746 &tunnel_key.enc_ipv6);
1747 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1748 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1749 &tunnel_key.enc_tp);
1750 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1751 &tunnel_key.enc_key_id);
1752 tunnel_key.filter_ifindex = filter_dev->ifindex;
1753
1754 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1755 if (err)
101f4de9 1756 return err;
bbd00f7e 1757
0a7fcb78
PB		 1758 flow_rule_match_enc_opts(rule, &enc_opts_match);
1759 err = enc_opts_is_dont_care_or_full_match(priv,
1760 enc_opts_match.mask,
1761 extack,
1762 &enc_opts_is_dont_care);
1763 if (err)
1764 goto err_enc_opts;
fe1587a7 1765
0a7fcb78 1766 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1767 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1768 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1769 sizeof(*enc_opts_match.key));
1770 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1771 sizeof(*enc_opts_match.mask));
1772
0a7fcb78 1773 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1774 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1775 if (err)
1776 goto err_enc_opts;
1777 }
fe1587a7 1778
0a7fcb78
PB		 1779 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1780 mask = enc_opts_id ? TUNNEL_ID_MASK :
1781 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1782
0a7fcb78
PB		 1783 if (attr->chain) {
1784 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1785 TUNNEL_TO_REG, value, mask);
1786 } else {
1787 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1788 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1789 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1790 TUNNEL_TO_REG, value);
1791 if (err)
1792 goto err_set;
fe1587a7 1793
0a7fcb78 1794 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1795 }
bbd00f7e 1796
0a7fcb78
PB		 1797 flow->tunnel_id = value;
1798 return 0;
bcef735c 1799
0a7fcb78
PB		 1800err_set:
1801 if (enc_opts_id)
1802 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1803 enc_opts_id);
1804err_enc_opts:
1805 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1806 return err;
1807}
bcef735c 1808
0a7fcb78
PB		 1809static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1810{
1811 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1812 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1813 struct mlx5_rep_uplink_priv *uplink_priv;
1814 struct mlx5e_rep_priv *uplink_rpriv;
1815 struct mlx5_eswitch *esw;
bcef735c 1816
0a7fcb78
PB		 1817 esw = flow->priv->mdev->priv.eswitch;
1818 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1819 uplink_priv = &uplink_rpriv->uplink_priv;
1820
1821 if (tun_id)
1822 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1823 if (enc_opts_id)
1824 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1825 enc_opts_id);
1826}
e98bedf5 1827
4c3844d9
PB		 1828u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1829{
1830 return flow->tunnel_id;
1831}
1832
fca53304
EB		 1833void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1834 struct flow_match_basic *match, bool outer,
1835 void *headers_c, void *headers_v)
1836{
1837 bool ip_version_cap;
1838
1839 ip_version_cap = outer ?
1840 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1841 ft_field_support.outer_ip_version) :
1842 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1843 ft_field_support.inner_ip_version);
1844
1845 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1846 (match->key->n_proto == htons(ETH_P_IP) ||
1847 match->key->n_proto == htons(ETH_P_IPV6))) {
1848 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1849 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1850 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1851 } else {
1852 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1853 ntohs(match->mask->n_proto));
1854 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1855 ntohs(match->key->n_proto));
1856 }
4a5d5d73
EB		 1857}
1858
0d9f9647 1859u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1860{
1861 void *headers_v;
1862 u16 ethertype;
1863 u8 ip_version;
1864
1865 if (outer)
1866 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1867 else
1868 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1869
1870 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1871 /* Return ip_version converted from ethertype anyway */
1872 if (!ip_version) {
1873 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1874 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1875 ip_version = 4;
1876 else if (ethertype == ETH_P_IPV6)
1877 ip_version = 6;
1878 }
1879 return ip_version;
1880}
1881
bbd00f7e 1882static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1883 struct mlx5e_tc_flow *flow,
bbd00f7e 1884 struct mlx5_flow_spec *spec,
f9e30088 1885 struct flow_cls_offload *f,
0a7fcb78
PB		 1886 struct net_device *filter_dev,
1887 u8 *match_level,
1888 bool *match_inner)
bbd00f7e 1889{
a508728a 1890 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1891 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1892 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1893 bool needs_mapping, sets_mapping;
8f256622 1894 int err;
2e72eb43 1895
0a7fcb78
PB		 1896 if (!mlx5e_is_eswitch_flow(flow))
1897 return -EOPNOTSUPP;
1898
c620b772 1899 needs_mapping = !!flow->attr->chain;
ee950e5d 1900 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 1901 *match_inner = !needs_mapping;
1902
1903 if ((needs_mapping || sets_mapping) &&
636bb968 1904 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 1905 NL_SET_ERR_MSG(extack,
636bb968 1906 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1907 netdev_warn(priv->netdev,
636bb968 1908 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1909 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1910 }
1911
c620b772 1912 if (!flow->attr->chain) {
0a7fcb78
PB		 1913 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1914 match_level);
1915 if (err) {
e98bedf5 1916 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1917 "Failed to parse tunnel attributes");
1918 netdev_warn(priv->netdev,
1919 "Failed to parse tunnel attributes");
1920 return err;
e98bedf5
EB		 1921 }
1922
14e6b038
EC		 1923 /* With mpls over udp we decapsulate using packet reformat
1924 * object
1925 */
1926 if (!netif_is_bareudp(filter_dev))
c620b772 1927 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1928 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1929 if (err)
1930 return err;
1931 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1932 struct mlx5_flow_spec *tmp_spec;
1933
1934 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1935 if (!tmp_spec) {
1936 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1937 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1938 return -ENOMEM;
1939 }
1940 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1941
1942 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1943 if (err) {
1944 kvfree(tmp_spec);
1945 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1946 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1947 return err;
1948 }
1949 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1950 kvfree(tmp_spec);
1951 if (err)
1952 return err;
bcef735c
OG		 1953 }
1954
0a7fcb78
PB		 1955 if (!needs_mapping && !sets_mapping)
1956 return 0;
bbd00f7e 1957
0a7fcb78 1958 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1959}
bbd00f7e 1960
0a7fcb78 1961static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1962{
0a7fcb78
PB		 1963 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1964 inner_headers);
bbd00f7e
HHZ		 1965}
1966
0a7fcb78 1967static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1968{
0a7fcb78
PB		 1969 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1970 inner_headers);
1971}
1972
1973static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1974{
1975 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1976 outer_headers);
1977}
1978
1979static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1980{
1981 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1982 outer_headers);
8377629e
EB		 1983}
1984
1985static void *get_match_headers_value(u32 flags,
1986 struct mlx5_flow_spec *spec)
1987{
1988 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1989 get_match_inner_headers_value(spec) :
1990 get_match_outer_headers_value(spec);
1991}
1992
1993static void *get_match_headers_criteria(u32 flags,
1994 struct mlx5_flow_spec *spec)
1995{
1996 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1997 get_match_inner_headers_criteria(spec) :
1998 get_match_outer_headers_criteria(spec);
8377629e
EB		 1999}
2000
6d65bc64 2001static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2002 struct flow_cls_offload *f)
2003{
2004 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2005 struct netlink_ext_ack *extack = f->common.extack;
2006 struct net_device *ingress_dev;
2007 struct flow_match_meta match;
2008
2009 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2010 return 0;
2011
2012 flow_rule_match_meta(rule, &match);
e3e0f9b2 2013 if (!match.mask->ingress_ifindex)
2014 return 0;
2015
6d65bc64 2016 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2017 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2018 return -EOPNOTSUPP;
6d65bc64 2019 }
2020
2021 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2022 match.key->ingress_ifindex);
2023 if (!ingress_dev) {
2024 NL_SET_ERR_MSG_MOD(extack,
2025 "Can't find the ingress port to match on");
a683012a 2026 return -ENOENT;
6d65bc64 2027 }
2028
2029 if (ingress_dev != filter_dev) {
2030 NL_SET_ERR_MSG_MOD(extack,
2031 "Can't match on the ingress filter port");
a683012a 2032 return -EOPNOTSUPP;
6d65bc64 2033 }
2034
2035 return 0;
2036}
2037
72046a91
EC		 2038static bool skip_key_basic(struct net_device *filter_dev,
2039 struct flow_cls_offload *f)
2040{
2041 /* When doing mpls over udp decap, the user needs to provide
2042 * MPLS_UC as the protocol in order to be able to match on mpls
2043 * label fields. However, the actual ethertype is IP so we want to
2044 * avoid matching on this, otherwise we'll fail the match.
2045 */
2046 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2047 return true;
2048
2049 return false;
2050}
2051
de0af0bf 2052static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2053 struct mlx5e_tc_flow *flow,
de0af0bf 2054 struct mlx5_flow_spec *spec,
f9e30088 2055 struct flow_cls_offload *f,
54c177ca 2056 struct net_device *filter_dev,
93b3586e 2057 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2058{
e98bedf5 2059 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2060 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2061 outer_headers);
2062 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2063 outer_headers);
699e96dd
JL		 2064 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2065 misc_parameters);
2066 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2067 misc_parameters);
a3222a2d
MD		 2068 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2069 misc_parameters_3);
2070 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2071 misc_parameters_3);
f9e30088 2072 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2073 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2074 enum fs_flow_table_type fs_type;
e3a2b7ed
AV		 2075 u16 addr_type = 0;
2076 u8 ip_proto = 0;
93b3586e 2077 u8 *match_level;
6d65bc64 2078 int err;
e3a2b7ed 2079
afe93f71 2080 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2081 match_level = outer_match_level;
de0af0bf 2082
8f256622 2083 if (dissector->used_keys &
3d144578
VB		 2084 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2085 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2086 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2087 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2088 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2089 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2090 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2091 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2092 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2093 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2094 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2095 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2096 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2097 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2098 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2099 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2100 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2101 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2102 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2103 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2104 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2105 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2106 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2107 dissector->used_keys);
e3a2b7ed
AV		 2108 return -EOPNOTSUPP;
2109 }
2110
075973c7 2111 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2112 bool match_inner = false;
bbd00f7e 2113
0a7fcb78
PB		 2114 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2115 outer_match_level, &match_inner);
2116 if (err)
2117 return err;
2118
2119 if (match_inner) {
2120 /* header pointers should point to the inner headers
2121 * if the packet was decapsulated already.
2122 * outer headers are set by parse_tunnel_attr.
2123 */
2124 match_level = inner_match_level;
2125 headers_c = get_match_inner_headers_criteria(spec);
2126 headers_v = get_match_inner_headers_value(spec);
2127 }
bbd00f7e
HHZ		 2128 }
2129
6d65bc64 2130 err = mlx5e_flower_parse_meta(filter_dev, f);
2131 if (err)
2132 return err;
2133
72046a91
EC		 2134 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2135 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2136 struct flow_match_basic match;
2137
2138 flow_rule_match_basic(rule, &match);
fca53304
EB		 2139 mlx5e_tc_set_ethertype(priv->mdev, &match,
2140 match_level == outer_match_level,
2141 headers_c, headers_v);
e3a2b7ed 2142
8f256622 2143 if (match.mask->n_proto)
d708f902 2144 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2145 }
35a605db
EB		 2146 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2147 is_vlan_dev(filter_dev)) {
2148 struct flow_dissector_key_vlan filter_dev_mask;
2149 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2150 struct flow_match_vlan match;
2151
35a605db
EB		 2152 if (is_vlan_dev(filter_dev)) {
2153 match.key = &filter_dev_key;
2154 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2155 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2156 match.key->vlan_priority = 0;
2157 match.mask = &filter_dev_mask;
2158 memset(match.mask, 0xff, sizeof(*match.mask));
2159 match.mask->vlan_priority = 0;
2160 } else {
2161 flow_rule_match_vlan(rule, &match);
2162 }
8f256622
PNA		 2163 if (match.mask->vlan_id ||
2164 match.mask->vlan_priority ||
2165 match.mask->vlan_tpid) {
2166 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2167 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2168 svlan_tag, 1);
2169 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2170 svlan_tag, 1);
2171 } else {
2172 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2173 cvlan_tag, 1);
2174 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2175 cvlan_tag, 1);
2176 }
095b6cfd 2177
8f256622
PNA		 2178 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2179 match.mask->vlan_id);
2180 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2181 match.key->vlan_id);
358d79a4 2182
8f256622
PNA		 2183 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2184 match.mask->vlan_priority);
2185 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2186 match.key->vlan_priority);
54782900 2187
d708f902 2188 *match_level = MLX5_MATCH_L2;
54782900 2189 }
d3a80bb5 2190 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2191 /* cvlan_tag enabled in match criteria and
2192 * disabled in match value means both S & C tags
2193 * don't exist (untagged of both)
2194 */
cee26487 2195 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2196 *match_level = MLX5_MATCH_L2;
54782900
OG		 2197 }
2198
8f256622
PNA		 2199 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2200 struct flow_match_vlan match;
2201
12d5cbf8 2202 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2203 if (match.mask->vlan_id ||
2204 match.mask->vlan_priority ||
2205 match.mask->vlan_tpid) {
afe93f71
RD		 2206 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2207 fs_type)) {
2208 NL_SET_ERR_MSG_MOD(extack,
2209 "Matching on CVLAN is not supported");
2210 return -EOPNOTSUPP;
2211 }
2212
8f256622 2213 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2214 MLX5_SET(fte_match_set_misc, misc_c,
2215 outer_second_svlan_tag, 1);
2216 MLX5_SET(fte_match_set_misc, misc_v,
2217 outer_second_svlan_tag, 1);
2218 } else {
2219 MLX5_SET(fte_match_set_misc, misc_c,
2220 outer_second_cvlan_tag, 1);
2221 MLX5_SET(fte_match_set_misc, misc_v,
2222 outer_second_cvlan_tag, 1);
2223 }
2224
2225 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2226 match.mask->vlan_id);
699e96dd 2227 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2228 match.key->vlan_id);
699e96dd 2229 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2230 match.mask->vlan_priority);
699e96dd 2231 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2232 match.key->vlan_priority);
699e96dd
JL		 2233
2234 *match_level = MLX5_MATCH_L2;
0faddfe6 2235 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2236 }
2237 }
2238
8f256622
PNA		 2239 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2240 struct flow_match_eth_addrs match;
54782900 2241
8f256622 2242 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2243 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2244 dmac_47_16),
8f256622 2245 match.mask->dst);
d3a80bb5
OG		 2246 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2247 dmac_47_16),
8f256622 2248 match.key->dst);
d3a80bb5
OG		 2249
2250 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2251 smac_47_16),
8f256622 2252 match.mask->src);
d3a80bb5
OG		 2253 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2254 smac_47_16),
8f256622 2255 match.key->src);
d3a80bb5 2256
8f256622
PNA		 2257 if (!is_zero_ether_addr(match.mask->src) ||
2258 !is_zero_ether_addr(match.mask->dst))
d708f902 2259 *match_level = MLX5_MATCH_L2;
54782900
OG		 2260 }
2261
8f256622
PNA		 2262 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2263 struct flow_match_control match;
54782900 2264
8f256622
PNA		 2265 flow_rule_match_control(rule, &match);
2266 addr_type = match.key->addr_type;
54782900
OG		 2267
2268 /* the HW doesn't support frag first/later */
8f256622 2269 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2270 return -EOPNOTSUPP;
2271
8f256622 2272 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2273 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2275 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2276
2277 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2278 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2279 *match_level = MLX5_MATCH_L2;
54782900
OG		 2280 /* *** L2 attributes parsing up to here *** */
2281 else
83621b7d 2282 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2283 }
2284 }
2285
8f256622
PNA		 2286 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2287 struct flow_match_basic match;
2288
2289 flow_rule_match_basic(rule, &match);
2290 ip_proto = match.key->ip_proto;
54782900
OG		 2291
2292 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2293 match.mask->ip_proto);
54782900 2294 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2295 match.key->ip_proto);
54782900 2296
8f256622 2297 if (match.mask->ip_proto)
d708f902 2298 *match_level = MLX5_MATCH_L3;
54782900
OG		 2299 }
2300
e3a2b7ed 2301 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2302 struct flow_match_ipv4_addrs match;
e3a2b7ed 2303
8f256622 2304 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2305 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2306 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2307 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2308 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2309 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2310 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2311 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2312 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2313 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2314 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2315 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2316 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2317
8f256622 2318 if (match.mask->src || match.mask->dst)
d708f902 2319 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2320 }
2321
2322 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2323 struct flow_match_ipv6_addrs match;
e3a2b7ed 2324
8f256622 2325 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2326 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2327 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2328 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2329 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2330 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2331 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2332
2333 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2334 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2335 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2336 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2337 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2338 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2339
8f256622
PNA		 2340 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2341 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2342 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2343 }
2344
8f256622
PNA		 2345 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2346 struct flow_match_ip match;
1f97a526 2347
8f256622
PNA		 2348 flow_rule_match_ip(rule, &match);
2349 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2350 match.mask->tos & 0x3);
2351 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2352 match.key->tos & 0x3);
1f97a526 2353
8f256622
PNA		 2354 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2355 match.mask->tos >> 2);
2356 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2357 match.key->tos >> 2);
1f97a526 2358
8f256622
PNA		 2359 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2360 match.mask->ttl);
2361 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2362 match.key->ttl);
1f97a526 2363
8f256622 2364 if (match.mask->ttl &&
a8ade55f 2365 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2366 ft_field_support.outer_ipv4_ttl)) {
2367 NL_SET_ERR_MSG_MOD(extack,
2368 "Matching on TTL is not supported");
1f97a526 2369 return -EOPNOTSUPP;
e98bedf5 2370 }
a8ade55f 2371
8f256622 2372 if (match.mask->tos || match.mask->ttl)
d708f902 2373 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2374 }
2375
54782900
OG		 2376 /* *** L3 attributes parsing up to here *** */
2377
8f256622
PNA		 2378 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2379 struct flow_match_ports match;
2380
2381 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2382 switch (ip_proto) {
2383 case IPPROTO_TCP:
2384 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2385 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2386 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2387 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2388
2389 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2390 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2391 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2392 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2393 break;
2394
2395 case IPPROTO_UDP:
2396 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2397 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2398 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2399 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2400
2401 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2402 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2403 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2404 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2405 break;
2406 default:
e98bedf5
EB		 2407 NL_SET_ERR_MSG_MOD(extack,
2408 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2409 netdev_err(priv->netdev,
2410 "Only UDP and TCP transport are supported\n");
2411 return -EINVAL;
2412 }
de0af0bf 2413
8f256622 2414 if (match.mask->src || match.mask->dst)
d708f902 2415 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2416 }
2417
8f256622
PNA		 2418 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2419 struct flow_match_tcp match;
e77834ec 2420
8f256622 2421 flow_rule_match_tcp(rule, &match);
e77834ec 2422 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2423 ntohs(match.mask->flags));
e77834ec 2424 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2425 ntohs(match.key->flags));
e77834ec 2426
8f256622 2427 if (match.mask->flags)
d708f902 2428 *match_level = MLX5_MATCH_L4;
e77834ec 2429 }
a3222a2d
MD		 2430 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2431 struct flow_match_icmp match;
e77834ec 2432
a3222a2d
MD		 2433 flow_rule_match_icmp(rule, &match);
2434 switch (ip_proto) {
2435 case IPPROTO_ICMP:
2436 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2437 MLX5_FLEX_PROTO_ICMP))
2438 return -EOPNOTSUPP;
2439 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2440 match.mask->type);
2441 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2442 match.key->type);
2443 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2444 match.mask->code);
2445 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2446 match.key->code);
2447 break;
2448 case IPPROTO_ICMPV6:
2449 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2450 MLX5_FLEX_PROTO_ICMPV6))
2451 return -EOPNOTSUPP;
2452 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2453 match.mask->type);
2454 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2455 match.key->type);
2456 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2457 match.mask->code);
2458 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2459 match.key->code);
2460 break;
2461 default:
2462 NL_SET_ERR_MSG_MOD(extack,
2463 "Code and type matching only with ICMP and ICMPv6");
2464 netdev_err(priv->netdev,
2465 "Code and type matching only with ICMP and ICMPv6\n");
2466 return -EINVAL;
2467 }
2468 if (match.mask->code || match.mask->type) {
2469 *match_level = MLX5_MATCH_L4;
2470 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2471 }
2472 }
39c538d6 2473 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2474 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2475 !netif_is_bareudp(filter_dev)) {
2476 NL_SET_ERR_MSG_MOD(extack,
2477 "Matching on MPLS is supported only for MPLS over UDP");
2478 netdev_err(priv->netdev,
2479 "Matching on MPLS is supported only for MPLS over UDP\n");
2480 return -EOPNOTSUPP;
2481 }
2482
e3a2b7ed
AV		 2483 return 0;
2484}
2485
de0af0bf 2486static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2487 struct mlx5e_tc_flow *flow,
de0af0bf 2488 struct mlx5_flow_spec *spec,
f9e30088 2489 struct flow_cls_offload *f,
54c177ca 2490 struct net_device *filter_dev)
de0af0bf 2491{
93b3586e 2492 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2493 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2494 struct mlx5_core_dev *dev = priv->mdev;
2495 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2496 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2497 struct mlx5_eswitch_rep *rep;
226f2ca3 2498 bool is_eswitch_flow;
de0af0bf
RD		 2499 int err;
2500
93b3586e
HN		 2501 inner_match_level = MLX5_MATCH_NONE;
2502 outer_match_level = MLX5_MATCH_NONE;
2503
0a7fcb78
PB		 2504 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2505 &inner_match_level, &outer_match_level);
93b3586e
HN		 2506 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2507 outer_match_level : inner_match_level;
de0af0bf 2508
226f2ca3
VB		 2509 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2510 if (!err && is_eswitch_flow) {
1d447a39 2511 rep = rpriv->rep;
b05af6aa 2512 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2513 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2514 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2515 NL_SET_ERR_MSG_MOD(extack,
2516 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2517 netdev_warn(priv->netdev,
2518 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2519 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2520 return -EOPNOTSUPP;
2521 }
2522 }
2523
c620b772
AL		 2524 flow->attr->inner_match_level = inner_match_level;
2525 flow->attr->outer_match_level = outer_match_level;
2526
38aa51c1 2527
de0af0bf
RD		 2528 return err;
2529}
2530
d79b6df6
OG		 2531struct pedit_headers {
2532 struct ethhdr eth;
0eb69bb9 2533 struct vlan_hdr vlan;
d79b6df6
OG		 2534 struct iphdr ip4;
2535 struct ipv6hdr ip6;
2536 struct tcphdr tcp;
2537 struct udphdr udp;
2538};
2539
c500c86b
PNA		 2540struct pedit_headers_action {
2541 struct pedit_headers vals;
2542 struct pedit_headers masks;
2543 u32 pedits;
2544};
2545
d79b6df6 2546static int pedit_header_offsets[] = {
73867881
PNA		 2547 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2548 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2549 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2550 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2551 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2552};
2553
2554#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2555
2556static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2557 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2558{
2559 u32 *curr_pmask, *curr_pval;
2560
c500c86b
PNA		 2561 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2562 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2563
2564 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2565 goto out_err;
2566
2567 *curr_pmask |= mask;
2568 *curr_pval |= (val & mask);
2569
2570 return 0;
2571
2572out_err:
2573 return -EOPNOTSUPP;
2574}
2575
2576struct mlx5_fields {
2577 u8 field;
88f30bbc
DL		 2578 u8 field_bsize;
2579 u32 field_mask;
d79b6df6 2580 u32 offset;
27c11b6b 2581 u32 match_offset;
d79b6df6
OG		 2582};
2583
88f30bbc
DL		 2584#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2585 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2586 offsetof(struct pedit_headers, field) + (off), \
2587 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2588
2ef86872
EB		 2589/* masked values are the same and there are no rewrites that do not have a
2590 * match.
2591 */
2592#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2593 type matchmaskx = *(type *)(matchmaskp); \
2594 type matchvalx = *(type *)(matchvalp); \
2595 type maskx = *(type *)(maskp); \
2596 type valx = *(type *)(valp); \
2597 \
2598 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2599 matchmaskx)); \
2600})
2601
27c11b6b 2602static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2603 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2604{
2605 bool same = false;
2606
88f30bbc
DL		 2607 switch (bsize) {
2608 case 8:
2ef86872 2609 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2610 break;
88f30bbc 2611 case 16:
2ef86872 2612 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2613 break;
88f30bbc 2614 case 32:
2ef86872 2615 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2616 break;
2617 }
2618
2619 return same;
2620}
a8e4f0c4 2621
d79b6df6 2622static struct mlx5_fields fields[] = {
88f30bbc
DL		 2623 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2624 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2625 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2626 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2627 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2628 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2629
ab9341b5 2630 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2631 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2632 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2633 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2634
2635 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2636 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2637 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2638 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2639 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2640 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2641 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2642 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2643 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2644 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2645 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2646 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2647 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2648 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2649 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2650 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2651 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2652 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2653
88f30bbc
DL		 2654 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2655 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2656 /* in linux iphdr tcp_flags is 8 bits long */
2657 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2658
88f30bbc
DL		 2659 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2660 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2661};
2662
82198d8b
MD		 2663static unsigned long mask_to_le(unsigned long mask, int size)
2664{
2665 __be32 mask_be32;
2666 __be16 mask_be16;
2667
2668 if (size == 32) {
2669 mask_be32 = (__force __be32)(mask);
2670 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2671 } else if (size == 16) {
2672 mask_be32 = (__force __be32)(mask);
2673 mask_be16 = *(__be16 *)&mask_be32;
2674 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2675 }
2676
2677 return mask;
2678}
6ae4a6a5
PB		 2679static int offload_pedit_fields(struct mlx5e_priv *priv,
2680 int namespace,
2681 struct pedit_headers_action *hdrs,
e98bedf5 2682 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2683 u32 *action_flags,
e98bedf5 2684 struct netlink_ext_ack *extack)
d79b6df6
OG		 2685{
2686 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2687 int i, action_size, first, last, next_z;
88f30bbc
DL		 2688 void *headers_c, *headers_v, *action, *vals_p;
2689 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2690 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2691 struct mlx5_fields *f;
82198d8b 2692 unsigned long mask, field_mask;
6ae4a6a5 2693 int err;
88f30bbc
DL		 2694 u8 cmd;
2695
6ae4a6a5 2696 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2697 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2698 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2699
73867881
PNA		 2700 set_masks = &hdrs[0].masks;
2701 add_masks = &hdrs[1].masks;
2702 set_vals = &hdrs[0].vals;
2703 add_vals = &hdrs[1].vals;
d79b6df6 2704
d65dbedf 2705 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2706
2707 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2708 bool skip;
2709
d79b6df6
OG		 2710 f = &fields[i];
2711 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2712 s_mask = 0;
2713 a_mask = 0;
d79b6df6
OG		 2714
2715 s_masks_p = (void *)set_masks + f->offset;
2716 a_masks_p = (void *)add_masks + f->offset;
2717
88f30bbc
DL		 2718 s_mask = *s_masks_p & f->field_mask;
2719 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2720
2721 if (!s_mask && !a_mask) /* nothing to offload here */
2722 continue;
2723
2724 if (s_mask && a_mask) {
e98bedf5
EB		 2725 NL_SET_ERR_MSG_MOD(extack,
2726 "can't set and add to the same HW field");
61b6a6c3
CH		 2727 netdev_warn(priv->netdev,
2728 "mlx5: can't set and add to the same HW field (%x)\n",
2729 f->field);
d79b6df6
OG		 2730 return -EOPNOTSUPP;
2731 }
2732
27c11b6b 2733 skip = false;
d79b6df6 2734 if (s_mask) {
27c11b6b
EB		 2735 void *match_mask = headers_c + f->match_offset;
2736 void *match_val = headers_v + f->match_offset;
2737
d79b6df6
OG		 2738 cmd = MLX5_ACTION_TYPE_SET;
2739 mask = s_mask;
2740 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2741 /* don't rewrite if we have a match on the same value */
2742 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2743 match_mask, f->field_bsize))
27c11b6b 2744 skip = true;
d79b6df6 2745 /* clear to denote we consumed this field */
88f30bbc 2746 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2747 } else {
2748 cmd = MLX5_ACTION_TYPE_ADD;
2749 mask = a_mask;
2750 vals_p = (void *)add_vals + f->offset;
27c11b6b 2751 /* add 0 is no change */
88f30bbc 2752 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2753 skip = true;
d79b6df6 2754 /* clear to denote we consumed this field */
88f30bbc 2755 *a_masks_p &= ~f->field_mask;
d79b6df6 2756 }
27c11b6b
EB		 2757 if (skip)
2758 continue;
d79b6df6 2759
82198d8b 2760 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2761
88f30bbc
DL		 2762 first = find_first_bit(&mask, f->field_bsize);
2763 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2764 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2765 if (first < next_z && next_z < last) {
e98bedf5
EB		 2766 NL_SET_ERR_MSG_MOD(extack,
2767 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2768 netdev_warn(priv->netdev,
2769 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2770 mask);
d79b6df6
OG		 2771 return -EOPNOTSUPP;
2772 }
2773
6ae4a6a5
PB		 2774 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2775 if (err) {
2776 NL_SET_ERR_MSG_MOD(extack,
2777 "too many pedit actions, can't offload");
2778 mlx5_core_warn(priv->mdev,
2779 "mlx5: parsed %d pedit actions, can't do more\n",
2780 mod_acts->num_actions);
2781 return err;
2782 }
2783
2784 action = mod_acts->actions +
2785 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2786 MLX5_SET(set_action_in, action, action_type, cmd);
2787 MLX5_SET(set_action_in, action, field, f->field);
2788
2789 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2790 int start;
2791
82198d8b
MD		 2792 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2793
88f30bbc 2794 /* if field is bit sized it can start not from first bit */
82198d8b 2795 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2796
2797 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2798 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2799 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2800 }
2801
88f30bbc 2802 if (f->field_bsize == 32)
2b64beba 2803 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2804 else if (f->field_bsize == 16)
2b64beba 2805 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2806 else if (f->field_bsize == 8)
2b64beba 2807 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2808
6ae4a6a5 2809 ++mod_acts->num_actions;
d79b6df6
OG		 2810 }
2811
d79b6df6
OG		 2812 return 0;
2813}
2814
2cc1cb1d
TZ		 2815static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2816 int namespace)
2817{
2818 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2819 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2820 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2821 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2822}
2823
6ae4a6a5
PB		 2824int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2825 int namespace,
2826 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2827{
6ae4a6a5
PB		 2828 int action_size, new_num_actions, max_hw_actions;
2829 size_t new_sz, old_sz;
2830 void *ret;
d79b6df6 2831
6ae4a6a5
PB		 2832 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2833 return 0;
d79b6df6 2834
d65dbedf 2835 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2836
6ae4a6a5
PB		 2837 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2838 namespace);
2839 new_num_actions = min(max_hw_actions,
2840 mod_hdr_acts->actions ?
2841 mod_hdr_acts->max_actions * 2 : 1);
2842 if (mod_hdr_acts->max_actions == new_num_actions)
2843 return -ENOSPC;
2844
2845 new_sz = action_size * new_num_actions;
2846 old_sz = mod_hdr_acts->max_actions * action_size;
2847 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2848 if (!ret)
d79b6df6
OG		 2849 return -ENOMEM;
2850
6ae4a6a5
PB		 2851 memset(ret + old_sz, 0, new_sz - old_sz);
2852 mod_hdr_acts->actions = ret;
2853 mod_hdr_acts->max_actions = new_num_actions;
2854
d79b6df6
OG		 2855 return 0;
2856}
2857
6ae4a6a5
PB		 2858void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2859{
2860 kfree(mod_hdr_acts->actions);
2861 mod_hdr_acts->actions = NULL;
2862 mod_hdr_acts->num_actions = 0;
2863 mod_hdr_acts->max_actions = 0;
2864}
2865
d79b6df6
OG		 2866static const struct pedit_headers zero_masks = {};
2867
582234b4
EC		 2868static int
2869parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2870 const struct flow_action_entry *act, int namespace,
2871 struct mlx5e_tc_flow_parse_attr *parse_attr,
2872 struct pedit_headers_action *hdrs,
2873 struct netlink_ext_ack *extack)
d79b6df6 2874{
73867881
PNA		 2875 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2876 int err = -EOPNOTSUPP;
d79b6df6 2877 u32 mask, val, offset;
73867881 2878 u8 htype;
d79b6df6 2879
73867881
PNA		 2880 htype = act->mangle.htype;
2881 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2882
73867881
PNA		 2883 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2884 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2885 goto out_err;
2886 }
d79b6df6 2887
2cc1cb1d
TZ		 2888 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2889 NL_SET_ERR_MSG_MOD(extack,
2890 "The pedit offload action is not supported");
2891 goto out_err;
2892 }
2893
73867881
PNA		 2894 mask = act->mangle.mask;
2895 val = act->mangle.val;
2896 offset = act->mangle.offset;
d79b6df6 2897
73867881
PNA		 2898 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2899 if (err)
2900 goto out_err;
c500c86b 2901
73867881 2902 hdrs[cmd].pedits++;
d79b6df6 2903
c500c86b
PNA		 2904 return 0;
2905out_err:
2906 return err;
2907}
2908
582234b4
EC		 2909static int
2910parse_pedit_to_reformat(struct mlx5e_priv *priv,
2911 const struct flow_action_entry *act,
2912 struct mlx5e_tc_flow_parse_attr *parse_attr,
2913 struct netlink_ext_ack *extack)
2914{
2915 u32 mask, val, offset;
2916 u32 *p;
2917
2918 if (act->id != FLOW_ACTION_MANGLE)
2919 return -EOPNOTSUPP;
2920
2921 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2922 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2923 return -EOPNOTSUPP;
2924 }
2925
2926 mask = ~act->mangle.mask;
2927 val = act->mangle.val;
2928 offset = act->mangle.offset;
2929 p = (u32 *)&parse_attr->eth;
2930 *(p + (offset >> 2)) |= (val & mask);
2931
2932 return 0;
2933}
2934
2935static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2936 const struct flow_action_entry *act, int namespace,
2937 struct mlx5e_tc_flow_parse_attr *parse_attr,
2938 struct pedit_headers_action *hdrs,
2939 struct mlx5e_tc_flow *flow,
2940 struct netlink_ext_ack *extack)
2941{
2942 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2943 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2944
2945 return parse_pedit_to_modify_hdr(priv, act, namespace,
2946 parse_attr, hdrs, extack);
2947}
2948
c500c86b
PNA		 2949static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2950 struct mlx5e_tc_flow_parse_attr *parse_attr,
2951 struct pedit_headers_action *hdrs,
27c11b6b 2952 u32 *action_flags,
c500c86b
PNA		 2953 struct netlink_ext_ack *extack)
2954{
2955 struct pedit_headers *cmd_masks;
2956 int err;
2957 u8 cmd;
2958
6ae4a6a5
PB		 2959 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2960 action_flags, extack);
d79b6df6
OG		 2961 if (err < 0)
2962 goto out_dealloc_parsed_actions;
2963
2964 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2965 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2966 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2967 NL_SET_ERR_MSG_MOD(extack,
2968 "attempt to offload an unsupported field");
b3a433de 2969 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2970 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2971 16, 1, cmd_masks, sizeof(zero_masks), true);
2972 err = -EOPNOTSUPP;
2973 goto out_dealloc_parsed_actions;
2974 }
2975 }
2976
2977 return 0;
2978
2979out_dealloc_parsed_actions:
6ae4a6a5 2980 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2981 return err;
2982}
2983
e98bedf5
EB		 2984static bool csum_offload_supported(struct mlx5e_priv *priv,
2985 u32 action,
2986 u32 update_flags,
2987 struct netlink_ext_ack *extack)
26c02749
OG		 2988{
2989 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2990 TCA_CSUM_UPDATE_FLAG_UDP;
2991
2992 /* The HW recalcs checksums only if re-writing headers */
2993 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2994 NL_SET_ERR_MSG_MOD(extack,
2995 "TC csum action is only offloaded with pedit");
26c02749
OG		 2996 netdev_warn(priv->netdev,
2997 "TC csum action is only offloaded with pedit\n");
2998 return false;
2999 }
3000
3001 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3002 NL_SET_ERR_MSG_MOD(extack,
3003 "can't offload TC csum action for some header/s");
26c02749
OG		 3004 netdev_warn(priv->netdev,
3005 "can't offload TC csum action for some header/s - flags %#x\n",
3006 update_flags);
3007 return false;
3008 }
3009
3010 return true;
3011}
3012
8998576b
DL		 3013struct ip_ttl_word {
3014 __u8 ttl;
3015 __u8 protocol;
3016 __sum16 check;
3017};
3018
3019struct ipv6_hoplimit_word {
3020 __be16 payload_len;
3021 __u8 nexthdr;
3022 __u8 hop_limit;
3023};
3024
4c3844d9
PB		 3025static int is_action_keys_supported(const struct flow_action_entry *act,
3026 bool ct_flow, bool *modify_ip_header,
7e36feeb 3027 bool *modify_tuple,
4c3844d9 3028 struct netlink_ext_ack *extack)
8998576b
DL		 3029{
3030 u32 mask, offset;
3031 u8 htype;
3032
3033 htype = act->mangle.htype;
3034 offset = act->mangle.offset;
3035 mask = ~act->mangle.mask;
3036 /* For IPv4 & IPv6 header check 4 byte word,
3037 * to determine that modified fields
3038 * are NOT ttl & hop_limit only.
3039 */
3040 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3041 struct ip_ttl_word *ttl_word =
3042 (struct ip_ttl_word *)&mask;
3043
3044 if (offset != offsetof(struct iphdr, ttl) ||
3045 ttl_word->protocol ||
3046 ttl_word->check) {
4c3844d9
PB		 3047 *modify_ip_header = true;
3048 }
3049
7e36feeb
PB		 3050 if (offset >= offsetof(struct iphdr, saddr))
3051 *modify_tuple = true;
3052
3053 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3054 NL_SET_ERR_MSG_MOD(extack,
3055 "can't offload re-write of ipv4 address with action ct");
3056 return -EOPNOTSUPP;
8998576b
DL		 3057 }
3058 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3059 struct ipv6_hoplimit_word *hoplimit_word =
3060 (struct ipv6_hoplimit_word *)&mask;
3061
3062 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3063 hoplimit_word->payload_len ||
3064 hoplimit_word->nexthdr) {
4c3844d9
PB		 3065 *modify_ip_header = true;
3066 }
3067
7e36feeb
PB		 3068 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3069 *modify_tuple = true;
3070
3071 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3072 NL_SET_ERR_MSG_MOD(extack,
3073 "can't offload re-write of ipv6 address with action ct");
3074 return -EOPNOTSUPP;
8998576b 3075 }
7e36feeb
PB		 3076 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3077 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3078 *modify_tuple = true;
3079 if (ct_flow) {
3080 NL_SET_ERR_MSG_MOD(extack,
3081 "can't offload re-write of transport header ports with action ct");
3082 return -EOPNOTSUPP;
3083 }
8998576b 3084 }
4c3844d9
PB		 3085
3086 return 0;
8998576b
DL		 3087}
3088
96b5b458
DC		 3089static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3090 bool ct_flow, struct netlink_ext_ack *extack,
3091 struct mlx5e_priv *priv,
3092 struct mlx5_flow_spec *spec)
3093{
3094 if (!modify_tuple || ct_clear)
3095 return true;
3096
3097 if (ct_flow) {
3098 NL_SET_ERR_MSG_MOD(extack,
3099 "can't offload tuple modification with non-clear ct()");
3100 netdev_info(priv->netdev,
3101 "can't offload tuple modification with non-clear ct()");
3102 return false;
3103 }
3104
3105 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3106 * (or after clear action), as otherwise, since the tuple is changed,
3107 * we can't restore ct state
3108 */
3109 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3110 NL_SET_ERR_MSG_MOD(extack,
3111 "can't offload tuple modification with ct matches and no ct(clear) action");
3112 netdev_info(priv->netdev,
3113 "can't offload tuple modification with ct matches and no ct(clear) action");
3114 return false;
3115 }
3116
3117 return true;
3118}
3119
3d486ec4
OS		 3120static bool modify_header_match_supported(struct mlx5e_priv *priv,
3121 struct mlx5_flow_spec *spec,
73867881 3122 struct flow_action *flow_action,
4c3844d9 3123 u32 actions, bool ct_flow,
7e36feeb 3124 bool ct_clear,
e98bedf5 3125 struct netlink_ext_ack *extack)
bdd66ac0 3126{
73867881 3127 const struct flow_action_entry *act;
7e36feeb 3128 bool modify_ip_header, modify_tuple;
fca53304 3129 void *headers_c;
bdd66ac0
OG		 3130 void *headers_v;
3131 u16 ethertype;
8998576b 3132 u8 ip_proto;
4c3844d9 3133 int i, err;
bdd66ac0 3134
fca53304 3135 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3136 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3137 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3138
3139 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3140 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3141 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3142 goto out_ok;
3143
3144 modify_ip_header = false;
7e36feeb 3145 modify_tuple = false;
73867881
PNA		 3146 flow_action_for_each(i, act, flow_action) {
3147 if (act->id != FLOW_ACTION_MANGLE &&
3148 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3149 continue;
3150
4c3844d9 3151 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3152 &modify_ip_header,
3153 &modify_tuple, extack);
4c3844d9
PB		 3154 if (err)
3155 return err;
bdd66ac0
OG		 3156 }
3157
96b5b458
DC		 3158 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3159 priv, spec))
7e36feeb 3160 return false;
7e36feeb 3161
bdd66ac0 3162 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3163 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3164 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3165 NL_SET_ERR_MSG_MOD(extack,
3166 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3167 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3168 ip_proto);
bdd66ac0
OG		 3169 return false;
3170 }
3171
3172out_ok:
3173 return true;
3174}
3175
3176static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3177 struct flow_action *flow_action,
bdd66ac0 3178 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3179 struct mlx5e_tc_flow *flow,
3180 struct netlink_ext_ack *extack)
bdd66ac0 3181{
a7c119bd 3182 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3183 u32 actions;
3184
c620b772
AL		 3185 ct_clear = flow->attr->ct_attr.ct_action &
3186 TCA_CT_ACT_CLEAR;
3187 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3188 actions = flow->attr->action;
3189
4c3844d9 3190 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3191 if (flow->attr->esw_attr->split_count && ct_flow &&
3192 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3193 /* All registers used by ct are cleared when using
3194 * split rules.
3195 */
3196 NL_SET_ERR_MSG_MOD(extack,
3197 "Can't offload mirroring with action ct");
49397b80 3198 return false;
4c3844d9 3199 }
4c3844d9 3200 }
bdd66ac0
OG		 3201
3202 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3203 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3204 flow_action, actions,
7e36feeb
PB		 3205 ct_flow, ct_clear,
3206 extack);
bdd66ac0
OG		 3207
3208 return true;
3209}
3210
32134847
MD		 3211static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3212{
3213 return priv->mdev == peer_priv->mdev;
3214}
3215
5c65c564
OG		 3216static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3217{
3218 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3219 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3220
3221 fmdev = priv->mdev;
3222 pmdev = peer_priv->mdev;
3223
59c9d35e
AH		 3224 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3225 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3226
816f6706 3227 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3228}
3229
bb569657
AL		 3230static bool same_vf_reps(struct mlx5e_priv *priv,
3231 struct net_device *out_dev)
3232{
3233 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3234 priv->netdev == out_dev;
3235}
3236
bdc837ee
EB		 3237static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3238 const struct flow_action_entry *act,
3239 struct mlx5e_tc_flow_parse_attr *parse_attr,
3240 struct pedit_headers_action *hdrs,
3241 u32 *action, struct netlink_ext_ack *extack)
3242{
3243 u16 mask16 = VLAN_VID_MASK;
3244 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3245 const struct flow_action_entry pedit_act = {
3246 .id = FLOW_ACTION_MANGLE,
3247 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3248 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3249 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3250 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3251 };
6fca9d1e 3252 u8 match_prio_mask, match_prio_val;
bf2f3bca 3253 void *headers_c, *headers_v;
bdc837ee
EB		 3254 int err;
3255
bf2f3bca
EB		 3256 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3257 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3258
3259 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3260 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3261 NL_SET_ERR_MSG_MOD(extack,
3262 "VLAN rewrite action must have VLAN protocol match");
3263 return -EOPNOTSUPP;
3264 }
3265
6fca9d1e
EB		 3266 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3267 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3268 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3269 NL_SET_ERR_MSG_MOD(extack,
3270 "Changing VLAN prio is not supported");
bdc837ee
EB		 3271 return -EOPNOTSUPP;
3272 }
3273
582234b4 3274 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3275 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3276
3277 return err;
3278}
3279
0bac1194
EB		 3280static int
3281add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3282 struct mlx5e_tc_flow_parse_attr *parse_attr,
3283 struct pedit_headers_action *hdrs,
3284 u32 *action, struct netlink_ext_ack *extack)
3285{
3286 const struct flow_action_entry prio_tag_act = {
3287 .vlan.vid = 0,
3288 .vlan.prio =
3289 MLX5_GET(fte_match_set_lyr_2_4,
3290 get_match_headers_value(*action,
3291 &parse_attr->spec),
3292 first_prio) &
3293 MLX5_GET(fte_match_set_lyr_2_4,
3294 get_match_headers_criteria(*action,
3295 &parse_attr->spec),
3296 first_prio),
3297 };
3298
3299 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3300 &prio_tag_act, parse_attr, hdrs, action,
3301 extack);
3302}
3303
c7569097
AL		 3304static int validate_goto_chain(struct mlx5e_priv *priv,
3305 struct mlx5e_tc_flow *flow,
3306 const struct flow_action_entry *act,
3307 u32 actions,
3308 struct netlink_ext_ack *extack)
3309{
3310 bool is_esw = mlx5e_is_eswitch_flow(flow);
3311 struct mlx5_flow_attr *attr = flow->attr;
3312 bool ft_flow = mlx5e_is_ft_flow(flow);
3313 u32 dest_chain = act->chain_index;
3314 struct mlx5_fs_chains *chains;
3315 struct mlx5_eswitch *esw;
3316 u32 reformat_and_fwd;
3317 u32 max_chain;
3318
3319 esw = priv->mdev->priv.eswitch;
3320 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3321 max_chain = mlx5_chains_get_chain_range(chains);
3322 reformat_and_fwd = is_esw ?
3323 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3324 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3325
3326 if (ft_flow) {
3327 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3328 return -EOPNOTSUPP;
3329 }
3330
3331 if (!mlx5_chains_backwards_supported(chains) &&
3332 dest_chain <= attr->chain) {
3333 NL_SET_ERR_MSG_MOD(extack,
3334 "Goto lower numbered chain isn't supported");
3335 return -EOPNOTSUPP;
3336 }
3337
3338 if (dest_chain > max_chain) {
3339 NL_SET_ERR_MSG_MOD(extack,
3340 "Requested destination chain is out of supported range");
3341 return -EOPNOTSUPP;
3342 }
3343
3344 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3345 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3346 !reformat_and_fwd) {
3347 NL_SET_ERR_MSG_MOD(extack,
3348 "Goto chain is not allowed if action has reformat or decap");
3349 return -EOPNOTSUPP;
3350 }
3351
3352 return 0;
3353}
3354
73867881
PNA		 3355static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3356 struct flow_action *flow_action,
e98bedf5
EB		 3357 struct mlx5e_tc_flow *flow,
3358 struct netlink_ext_ack *extack)
e3a2b7ed 3359{
c6cfe113 3360 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3361 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3362 struct pedit_headers_action hdrs[2] = {};
3363 const struct flow_action_entry *act;
c620b772 3364 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3365 u32 action = 0;
244cd96a 3366 int err, i;
e3a2b7ed 3367
73867881 3368 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3369 return -EINVAL;
3370
53eca1f3
JK		 3371 if (!flow_action_hw_stats_check(flow_action, extack,
3372 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3373 return -EOPNOTSUPP;
3374
c620b772 3375 nic_attr = attr->nic_attr;
c620b772 3376 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3377 parse_attr = attr->parse_attr;
e3a2b7ed 3378
73867881
PNA		 3379 flow_action_for_each(i, act, flow_action) {
3380 switch (act->id) {
15fc92ec
TZ		 3381 case FLOW_ACTION_ACCEPT:
3382 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3383 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3384 break;
73867881 3385 case FLOW_ACTION_DROP:
950b4df9
RD		 3386 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3387 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3388 break;
3389 case FLOW_ACTION_MANGLE:
3390 case FLOW_ACTION_ADD:
3391 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3392 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3393 if (err)
3394 return err;
3395
c7569097 3396 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3397 break;
bdc837ee
EB		 3398 case FLOW_ACTION_VLAN_MANGLE:
3399 err = add_vlan_rewrite_action(priv,
3400 MLX5_FLOW_NAMESPACE_KERNEL,
3401 act, parse_attr, hdrs,
3402 &action, extack);
3403 if (err)
3404 return err;
3405
3406 break;
73867881 3407 case FLOW_ACTION_CSUM:
1cab1cd7 3408 if (csum_offload_supported(priv, action,
73867881 3409 act->csum_flags,
e98bedf5 3410 extack))
73867881 3411 break;
26c02749
OG		 3412
3413 return -EOPNOTSUPP;
73867881
PNA		 3414 case FLOW_ACTION_REDIRECT: {
3415 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3416
3417 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3418 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3419 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3420 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3421 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3422 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3423 } else {
e98bedf5
EB		 3424 NL_SET_ERR_MSG_MOD(extack,
3425 "device is not on same HW, can't offload");
5c65c564
OG		 3426 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3427 peer_dev->name);
25f150f4 3428 return -EOPNOTSUPP;
5c65c564 3429 }
73867881
PNA		 3430 }
3431 break;
3432 case FLOW_ACTION_MARK: {
3433 u32 mark = act->mark;
e3a2b7ed
AV		 3434
3435 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3436 NL_SET_ERR_MSG_MOD(extack,
3437 "Bad flow mark - only 16 bit is supported");
25f150f4 3438 return -EOPNOTSUPP;
e3a2b7ed
AV		 3439 }
3440
c620b772 3441 nic_attr->flow_tag = mark;
1cab1cd7 3442 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3443 }
3444 break;
c7569097
AL		 3445 case FLOW_ACTION_GOTO:
3446 err = validate_goto_chain(priv, flow, act, action,
3447 extack);
3448 if (err)
3449 return err;
3450
3451 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3452 attr->dest_chain = act->chain_index;
3453 break;
aedd133d 3454 case FLOW_ACTION_CT:
3cfe4267
RD		 3455 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr,
3456 &parse_attr->mod_hdr_acts,
3457 act, extack);
aedd133d
AL		 3458 if (err)
3459 return err;
3460
3461 flow_flag_set(flow, CT);
3462 break;
73867881 3463 default:
2cc1cb1d
TZ		 3464 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3465 return -EOPNOTSUPP;
e3a2b7ed 3466 }
e3a2b7ed
AV		 3467 }
3468
c500c86b
PNA		 3469 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3470 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3471 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3472 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3473 if (err)
3474 return err;
27c11b6b
EB		 3475 /* in case all pedit actions are skipped, remove the MOD_HDR
3476 * flag.
3477 */
6ae4a6a5 3478 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3479 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3480 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3481 }
c500c86b
PNA		 3482 }
3483
1cab1cd7 3484 attr->action = action;
c7569097
AL		 3485
3486 if (attr->dest_chain) {
3487 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3488 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3489 return -EOPNOTSUPP;
3490 }
3491 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3492 }
3493
3494 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3495 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3496
73867881 3497 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3498 return -EOPNOTSUPP;
3499
e3a2b7ed
AV		 3500 return 0;
3501}
3502
32134847 3503static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3504 struct net_device *peer_netdev)
3505{
3506 struct mlx5e_priv *peer_priv;
3507
3508 peer_priv = netdev_priv(peer_netdev);
3509
3510 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3511 mlx5e_eswitch_vf_rep(priv->netdev) &&
3512 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3513 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3514}
3515
1482bd3d 3516static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3517 const struct flow_action_entry *act,
1482bd3d
JL		 3518 struct mlx5_esw_flow_attr *attr,
3519 u32 *action)
3520{
cc495188
JL		 3521 u8 vlan_idx = attr->total_vlan;
3522
3523 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3524 return -EOPNOTSUPP;
3525
73867881
PNA		 3526 switch (act->id) {
3527 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3528 if (vlan_idx) {
3529 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3530 MLX5_FS_VLAN_DEPTH))
3531 return -EOPNOTSUPP;
3532
3533 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3534 } else {
3535 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3536 }
73867881
PNA		 3537 break;
3538 case FLOW_ACTION_VLAN_PUSH:
3539 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3540 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3541 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3542 if (!attr->vlan_proto[vlan_idx])
3543 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3544
3545 if (vlan_idx) {
3546 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3547 MLX5_FS_VLAN_DEPTH))
3548 return -EOPNOTSUPP;
3549
3550 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3551 } else {
3552 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3553 (act->vlan.proto != htons(ETH_P_8021Q) ||
3554 act->vlan.prio))
cc495188
JL		 3555 return -EOPNOTSUPP;
3556
3557 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3558 }
73867881
PNA		 3559 break;
3560 default:
bdc837ee 3561 return -EINVAL;
1482bd3d
JL		 3562 }
3563
cc495188
JL		 3564 attr->total_vlan = vlan_idx + 1;
3565
1482bd3d
JL		 3566 return 0;
3567}
3568
d34eb2fc
OG		 3569static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3570 struct net_device *out_dev)
3571{
3572 struct net_device *fdb_out_dev = out_dev;
3573 struct net_device *uplink_upper;
3574
3575 rcu_read_lock();
3576 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3577 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3578 uplink_upper == out_dev) {
3579 fdb_out_dev = uplink_dev;
3580 } else if (netif_is_lag_master(out_dev)) {
3581 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3582 if (fdb_out_dev &&
3583 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3584 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3585 fdb_out_dev = NULL;
3586 }
3587 rcu_read_unlock();
3588 return fdb_out_dev;
3589}
3590
278748a9 3591static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3592 struct mlx5_flow_attr *attr,
278748a9
EB		 3593 struct net_device **out_dev,
3594 u32 *action)
3595{
3596 struct net_device *vlan_dev = *out_dev;
3597 struct flow_action_entry vlan_act = {
3598 .id = FLOW_ACTION_VLAN_PUSH,
3599 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3600 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3601 .vlan.prio = 0,
3602 };
3603 int err;
3604
c620b772 3605 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3606 if (err)
3607 return err;
3608
dca59f4a
DC		 3609 rcu_read_lock();
3610 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3611 rcu_read_unlock();
3612 if (!*out_dev)
3613 return -ENODEV;
3614
278748a9
EB		 3615 if (is_vlan_dev(*out_dev))
3616 err = add_vlan_push_action(priv, attr, out_dev, action);
3617
3618 return err;
3619}
3620
35a605db 3621static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3622 struct mlx5_flow_attr *attr,
35a605db
EB		 3623 u32 *action)
3624{
35a605db
EB		 3625 struct flow_action_entry vlan_act = {
3626 .id = FLOW_ACTION_VLAN_POP,
3627 };
70f478ca 3628 int nest_level, err = 0;
35a605db 3629
70f478ca
DL		 3630 nest_level = attr->parse_attr->filter_dev->lower_level -
3631 priv->netdev->lower_level;
35a605db 3632 while (nest_level--) {
c620b772 3633 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3634 if (err)
3635 return err;
3636 }
3637
3638 return err;
3639}
3640
32134847
MD		 3641static bool same_hw_reps(struct mlx5e_priv *priv,
3642 struct net_device *peer_netdev)
3643{
3644 struct mlx5e_priv *peer_priv;
3645
3646 peer_priv = netdev_priv(peer_netdev);
3647
3648 return mlx5e_eswitch_rep(priv->netdev) &&
3649 mlx5e_eswitch_rep(peer_netdev) &&
3650 same_hw_devs(priv, peer_priv);
3651}
3652
3653static bool is_lag_dev(struct mlx5e_priv *priv,
3654 struct net_device *peer_netdev)
3655{
3656 return ((mlx5_lag_is_sriov(priv->mdev) ||
3657 mlx5_lag_is_multipath(priv->mdev)) &&
3658 same_hw_reps(priv, peer_netdev));
3659}
3660
f6dc1264
PB		 3661bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3662 struct net_device *out_dev)
3663{
32134847
MD		 3664 if (is_merged_eswitch_vfs(priv, out_dev))
3665 return true;
3666
3667 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3668 return true;
3669
3670 return mlx5e_eswitch_rep(out_dev) &&
32134847 3671 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3672}
3673
554fe75c
DL		 3674static bool is_duplicated_output_device(struct net_device *dev,
3675 struct net_device *out_dev,
3676 int *ifindexes, int if_count,
3677 struct netlink_ext_ack *extack)
3678{
3679 int i;
3680
3681 for (i = 0; i < if_count; i++) {
3682 if (ifindexes[i] == out_dev->ifindex) {
3683 NL_SET_ERR_MSG_MOD(extack,
3684 "can't duplicate output to same device");
3685 netdev_err(dev, "can't duplicate output to same device: %s\n",
3686 out_dev->name);
3687 return true;
3688 }
3689 }
3690
3691 return false;
3692}
3693
613f53fe
EC		 3694static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3695 struct mlx5e_tc_flow *flow,
3696 struct net_device *out_dev,
3697 struct netlink_ext_ack *extack)
3698{
c620b772 3699 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3700 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3701 struct mlx5e_rep_priv *rep_priv;
3702
3703 /* Forwarding non encapsulated traffic between
3704 * uplink ports is allowed only if
3705 * termination_table_raw_traffic cap is set.
3706 *
c620b772 3707 * Input vport was stored attr->in_rep.
613f53fe
EC		 3708 * In LAG case, *priv* is the private data of
3709 * uplink which may be not the input vport.
3710 */
3711 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3712
3713 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3714 mlx5e_eswitch_uplink_rep(out_dev)))
3715 return 0;
3716
3717 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3718 termination_table_raw_traffic)) {
3719 NL_SET_ERR_MSG_MOD(extack,
3720 "devices are both uplink, can't offload forwarding");
3721 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3722 priv->netdev->name, out_dev->name);
3723 return -EOPNOTSUPP;
3724 } else if (out_dev != rep_priv->netdev) {
3725 NL_SET_ERR_MSG_MOD(extack,
3726 "devices are not the same uplink, can't offload forwarding");
3727 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3728 priv->netdev->name, out_dev->name);
3729 return -EOPNOTSUPP;
3730 }
3731 return 0;
3732}
3733
73867881
PNA		 3734static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3735 struct flow_action *flow_action,
e98bedf5 3736 struct mlx5e_tc_flow *flow,
70f8019e 3737 struct netlink_ext_ack *extack)
03a9d11e 3738{
73867881 3739 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3740 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3741 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3742 struct mlx5e_rep_priv *rpriv = priv->ppriv;
bcd6740c 3743 struct mlx5e_sample_attr sample_attr = {};
73867881 3744 const struct ip_tunnel_info *info = NULL;
c620b772 3745 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3746 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3747 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3748 const struct flow_action_entry *act;
c620b772 3749 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 3750 bool encap = false, decap = false;
3751 u32 action = attr->action;
554fe75c 3752 int err, i, if_count = 0;
f828ca6a 3753 bool mpls_push = false;
03a9d11e 3754
73867881 3755 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3756 return -EINVAL;
3757
53eca1f3
JK		 3758 if (!flow_action_hw_stats_check(flow_action, extack,
3759 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3760 return -EOPNOTSUPP;
3761
c620b772
AL		 3762 esw_attr = attr->esw_attr;
3763 parse_attr = attr->parse_attr;
3764
73867881
PNA		 3765 flow_action_for_each(i, act, flow_action) {
3766 switch (act->id) {
3767 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3768 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3769 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3770 break;
f0288210
EC		 3771 case FLOW_ACTION_TRAP:
3772 if (!flow_offload_has_one_action(flow_action)) {
3773 NL_SET_ERR_MSG_MOD(extack,
3774 "action trap is supported as a sole action only");
3775 return -EOPNOTSUPP;
3776 }
3777 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3778 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3779 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3780 break;
f828ca6a
EC		 3781 case FLOW_ACTION_MPLS_PUSH:
3782 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3783 reformat_l2_to_l3_tunnel) ||
3784 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3785 NL_SET_ERR_MSG_MOD(extack,
3786 "mpls push is supported only for mpls_uc protocol");
3787 return -EOPNOTSUPP;
3788 }
3789 mpls_push = true;
3790 break;
14e6b038
EC		 3791 case FLOW_ACTION_MPLS_POP:
3792 /* we only support mpls pop if it is the first action
3793 * and the filter net device is bareudp. Subsequent
3794 * actions can be pedit and the last can be mirred
3795 * egress redirect.
3796 */
3797 if (i) {
3798 NL_SET_ERR_MSG_MOD(extack,
3799 "mpls pop supported only as first action");
3800 return -EOPNOTSUPP;
3801 }
70f8019e 3802 if (!netif_is_bareudp(parse_attr->filter_dev)) {
14e6b038
EC		 3803 NL_SET_ERR_MSG_MOD(extack,
3804 "mpls pop supported only on bareudp devices");
3805 return -EOPNOTSUPP;
3806 }
3807
3808 parse_attr->eth.h_proto = act->mpls_pop.proto;
3809 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3810 flow_flag_set(flow, L3_TO_L2_DECAP);
3811 break;
73867881
PNA		 3812 case FLOW_ACTION_MANGLE:
3813 case FLOW_ACTION_ADD:
3814 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3815 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3816 if (err)
3817 return err;
3818
582234b4
EC		 3819 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3820 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3821 esw_attr->split_count = esw_attr->out_count;
582234b4 3822 }
73867881
PNA		 3823 break;
3824 case FLOW_ACTION_CSUM:
1cab1cd7 3825 if (csum_offload_supported(priv, action,
73867881
PNA		 3826 act->csum_flags, extack))
3827 break;
26c02749
OG		 3828
3829 return -EOPNOTSUPP;
73867881
PNA		 3830 case FLOW_ACTION_REDIRECT:
3831 case FLOW_ACTION_MIRRED: {
03a9d11e 3832 struct mlx5e_priv *out_priv;
592d3651 3833 struct net_device *out_dev;
03a9d11e 3834
73867881 3835 out_dev = act->dev;
ef381359
OS		 3836 if (!out_dev) {
3837 /* out_dev is NULL when filters with
3838 * non-existing mirred device are replayed to
3839 * the driver.
3840 */
3841 return -EINVAL;
3842 }
03a9d11e 3843
f828ca6a
EC		 3844 if (mpls_push && !netif_is_bareudp(out_dev)) {
3845 NL_SET_ERR_MSG_MOD(extack,
3846 "mpls is supported only through a bareudp device");
3847 return -EOPNOTSUPP;
3848 }
3849
84179981
PB		 3850 if (ft_flow && out_dev == priv->netdev) {
3851 /* Ignore forward to self rules generated
3852 * by adding both mlx5 devs to the flow table
3853 * block on a normal nft offload setup.
3854 */
3855 return -EOPNOTSUPP;
3856 }
3857
c620b772 3858 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3859 NL_SET_ERR_MSG_MOD(extack,
3860 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3861 netdev_warn(priv->netdev,
3862 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3863 esw_attr->out_count);
592d3651
CM		 3864 return -EOPNOTSUPP;
3865 }
3866
f493f155
EB		 3867 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3868 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3869 if (encap) {
c620b772 3870 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3871 out_dev->ifindex;
0d9f9647
VB		 3872 parse_attr->tun_info[esw_attr->out_count] =
3873 mlx5e_dup_tun_info(info);
c620b772 3874 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3875 return -ENOMEM;
3876 encap = false;
c620b772 3877 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3878 MLX5_ESW_DEST_ENCAP;
c620b772 3879 esw_attr->out_count++;
b6a4ac24
VB		 3880 /* attr->dests[].rep is resolved when we
3881 * handle encap
3882 */
3883 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3884 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3885 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3886
554fe75c
DL		 3887 if (is_duplicated_output_device(priv->netdev,
3888 out_dev,
3889 ifindexes,
3890 if_count,
3891 extack))
3892 return -EOPNOTSUPP;
3893
3894 ifindexes[if_count] = out_dev->ifindex;
3895 if_count++;
3896
d34eb2fc
OG		 3897 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3898 if (!out_dev)
3899 return -ENODEV;
7ba58ba7 3900
278748a9
EB		 3901 if (is_vlan_dev(out_dev)) {
3902 err = add_vlan_push_action(priv, attr,
3903 &out_dev,
3904 &action);
3905 if (err)
3906 return err;
3907 }
f6dc1264 3908
35a605db
EB		 3909 if (is_vlan_dev(parse_attr->filter_dev)) {
3910 err = add_vlan_pop_action(priv, attr,
3911 &action);
3912 if (err)
3913 return err;
3914 }
278748a9 3915
613f53fe
EC		 3916 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3917 if (err)
3918 return err;
ffec9702 3919
f6dc1264
PB		 3920 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3921 NL_SET_ERR_MSG_MOD(extack,
3922 "devices are not on same switch HW, can't offload forwarding");
a0646c88 3923 return -EOPNOTSUPP;
f6dc1264 3924 }
a0646c88 3925
bb569657
AL		 3926 if (same_vf_reps(priv, out_dev)) {
3927 NL_SET_ERR_MSG_MOD(extack,
3928 "can't forward from a VF to itself");
3929 return -EOPNOTSUPP;
3930 }
3931
a54e20b4 3932 out_priv = netdev_priv(out_dev);
1d447a39 3933 rpriv = out_priv->ppriv;
c620b772
AL		 3934 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3935 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3936 esw_attr->out_count++;
ef381359
OS		 3937 } else if (parse_attr->filter_dev != priv->netdev) {
3938 /* All mlx5 devices are called to configure
3939 * high level device filters. Therefore, the
3940 * *attempt* to install a filter on invalid
3941 * eswitch should not trigger an explicit error
3942 */
3943 return -EINVAL;
a54e20b4 3944 } else {
e98bedf5
EB		 3945 NL_SET_ERR_MSG_MOD(extack,
3946 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3947 netdev_warn(priv->netdev,
3948 "devices %s %s not on same switch HW, can't offload forwarding\n",
3949 priv->netdev->name,
3950 out_dev->name);
25f150f4 3951 return -EOPNOTSUPP;
03a9d11e 3952 }
73867881
PNA		 3953 }
3954 break;
3955 case FLOW_ACTION_TUNNEL_ENCAP:
3956 info = act->tunnel;
a54e20b4
HHZ		 3957 if (info)
3958 encap = true;
3959 else
3960 return -EOPNOTSUPP;
1482bd3d 3961
73867881
PNA		 3962 break;
3963 case FLOW_ACTION_VLAN_PUSH:
3964 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3965 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3966 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3967 /* Replace vlan pop+push with vlan modify */
3968 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3969 err = add_vlan_rewrite_action(priv,
3970 MLX5_FLOW_NAMESPACE_FDB,
3971 act, parse_attr, hdrs,
3972 &action, extack);
3973 } else {
c620b772 3974 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 3975 }
1482bd3d
JL		 3976 if (err)
3977 return err;
3978
c620b772 3979 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 3980 break;
3981 case FLOW_ACTION_VLAN_MANGLE:
3982 err = add_vlan_rewrite_action(priv,
3983 MLX5_FLOW_NAMESPACE_FDB,
3984 act, parse_attr, hdrs,
3985 &action, extack);
3986 if (err)
3987 return err;
3988
c620b772 3989 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 3990 break;
3991 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3992 decap = true;
73867881 3993 break;
2fbbc30d 3994 case FLOW_ACTION_GOTO:
c7569097
AL		 3995 err = validate_goto_chain(priv, flow, act, action,
3996 extack);
2fbbc30d
EC		 3997 if (err)
3998 return err;
bf07aa73 3999
e88afe75 4000 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4001 attr->dest_chain = act->chain_index;
73867881 4002 break;
4c3844d9 4003 case FLOW_ACTION_CT:
41c2fd94
CM		 4004 if (flow_flag_test(flow, SAMPLE)) {
4005 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4006 return -EOPNOTSUPP;
4007 }
3cfe4267
RD		 4008 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr,
4009 &parse_attr->mod_hdr_acts,
4010 act, extack);
4c3844d9
PB		 4011 if (err)
4012 return err;
4013
4014 flow_flag_set(flow, CT);
69e2916e 4015 esw_attr->split_count = esw_attr->out_count;
4c3844d9 4016 break;
41c2fd94
CM		 4017 case FLOW_ACTION_SAMPLE:
4018 if (flow_flag_test(flow, CT)) {
4019 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4020 return -EOPNOTSUPP;
4021 }
bcd6740c
CM		 4022 sample_attr.rate = act->sample.rate;
4023 sample_attr.group_num = act->sample.psample_group->group_num;
41c2fd94 4024 if (act->sample.truncate)
bcd6740c 4025 sample_attr.trunc_size = act->sample.trunc_size;
41c2fd94
CM		 4026 flow_flag_set(flow, SAMPLE);
4027 break;
73867881 4028 default:
2cc1cb1d
TZ		 4029 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4030 return -EOPNOTSUPP;
bf07aa73 4031 }
03a9d11e 4032 }
bdd66ac0 4033
a508728a
VB		 4034 /* always set IP version for indirect table handling */
4035 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4036
0bac1194
EB		 4037 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4038 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4039 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4040 * tag rewrite.
4041 */
4042 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4043 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4044 &action, extack);
4045 if (err)
4046 return err;
4047 }
4048
c500c86b
PNA		 4049 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4050 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4051 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4052 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4053 if (err)
4054 return err;
27c11b6b
EB		 4055 /* in case all pedit actions are skipped, remove the MOD_HDR
4056 * flag. we might have set split_count either by pedit or
4057 * pop/push. if there is no pop/push either, reset it too.
4058 */
6ae4a6a5 4059 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4060 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4061 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4062 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4063 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4064 esw_attr->split_count = 0;
27c11b6b 4065 }
c500c86b
PNA		 4066 }
4067
1cab1cd7 4068 attr->action = action;
73867881 4069 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4070 return -EOPNOTSUPP;
4071
e88afe75 4072 if (attr->dest_chain) {
0a7fcb78
PB		 4073 if (decap) {
4074 /* It can be supported if we'll create a mapping for
4075 * the tunnel device only (without tunnel), and set
4076 * this tunnel id with this decap flow.
4077 *
4078 * On restore (miss), we'll just set this saved tunnel
4079 * device.
4080 */
4081
4082 NL_SET_ERR_MSG(extack,
4083 "Decap with goto isn't supported");
4084 netdev_warn(priv->netdev,
4085 "Decap with goto isn't supported");
4086 return -EOPNOTSUPP;
4087 }
4088
e88afe75
OG		 4089 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4090 }
4091
ae2741e2
VB		 4092 if (!(attr->action &
4093 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4094 NL_SET_ERR_MSG_MOD(extack,
4095 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4096 return -EOPNOTSUPP;
4097 }
4098
c620b772 4099 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4100 NL_SET_ERR_MSG_MOD(extack,
4101 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4102 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4103 return -EOPNOTSUPP;
4104 }
4105
41c2fd94
CM		 4106 /* Allocate sample attribute only when there is a sample action and
4107 * no errors after parsing.
4108 */
4109 if (flow_flag_test(flow, SAMPLE)) {
bcd6740c
CM		 4110 attr->sample_attr = kzalloc(sizeof(*attr->sample_attr), GFP_KERNEL);
4111 if (!attr->sample_attr)
41c2fd94 4112 return -ENOMEM;
bcd6740c 4113 *attr->sample_attr = sample_attr;
41c2fd94
CM		 4114 }
4115
31c8eba5 4116 return 0;
03a9d11e
OG		 4117}
4118
226f2ca3 4119static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4120{
226f2ca3 4121 unsigned long __flow_flags = 0;
60bd4af8 4122
226f2ca3
VB		 4123 if (flags & MLX5_TC_FLAG(INGRESS))
4124 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4125 if (flags & MLX5_TC_FLAG(EGRESS))
4126 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4127
226f2ca3
VB		 4128 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4129 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4130 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4131 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4132 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4133 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4134
60bd4af8
OG		 4135 *flow_flags = __flow_flags;
4136}
4137
05866c82
OG		 4138static const struct rhashtable_params tc_ht_params = {
4139 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4140 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4141 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4142 .automatic_shrinking = true,
4143};
4144
226f2ca3
VB		 4145static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4146 unsigned long flags)
05866c82 4147{
655dc3d2
OG		 4148 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4149 struct mlx5e_rep_priv *uplink_rpriv;
4150
226f2ca3 4151 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4152 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4153 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4154 } else /* NIC offload */
655dc3d2 4155 return &priv->fs.tc.ht;
05866c82
OG		 4156}
4157
04de7dda
RD		 4158static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4159{
c620b772
AL		 4160 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4161 struct mlx5_flow_attr *attr = flow->attr;
4162 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4163 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4164 bool act_is_encap = !!(attr->action &
4165 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4166 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4167 MLX5_DEVCOM_ESW_OFFLOADS);
4168
10fbb1cd
RD		 4169 if (!esw_paired)
4170 return false;
4171
c620b772
AL		 4172 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4173 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4174 (is_rep_ingress || act_is_encap))
4175 return true;
4176
4177 return false;
04de7dda
RD		 4178}
4179
c620b772
AL		 4180struct mlx5_flow_attr *
4181mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4182{
4183 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4184 sizeof(struct mlx5_esw_flow_attr) :
4185 sizeof(struct mlx5_nic_flow_attr);
4186 struct mlx5_flow_attr *attr;
4187
4188 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4189}
4190
a88780a9
RD		 4191static int
4192mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4193 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4194 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4195 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4196{
17091853 4197 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4198 struct mlx5_flow_attr *attr;
3bc4b7bf 4199 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4200 int err = -ENOMEM;
4201 int out_index;
e3a2b7ed 4202
c620b772 4203 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4204 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4205 if (!parse_attr || !flow)
4206 goto err_free;
c620b772
AL		 4207
4208 flow->flags = flow_flags;
4209 flow->cookie = f->cookie;
4210 flow->priv = priv;
4211
4212 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4213 if (!attr)
e3a2b7ed 4214 goto err_free;
ff7ea04a 4215
c620b772 4216 flow->attr = attr;
e3a2b7ed 4217
5a7e5bcb
VB		 4218 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4219 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4220 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4221 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4222 refcount_set(&flow->refcnt, 1);
95435ad7 4223 init_completion(&flow->init_done);
909e615d 4224 init_completion(&flow->del_hw_done);
e3a2b7ed 4225
a88780a9
RD		 4226 *__flow = flow;
4227 *__parse_attr = parse_attr;
4228
4229 return 0;
4230
4231err_free:
4232 kfree(flow);
4233 kvfree(parse_attr);
4234 return err;
4235}
4236
c7569097
AL		 4237static void
4238mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4239 struct mlx5e_tc_flow_parse_attr *parse_attr,
4240 struct flow_cls_offload *f)
4241{
4242 attr->parse_attr = parse_attr;
4243 attr->chain = f->common.chain_index;
4244 attr->prio = f->common.prio;
4245}
4246
988ab9c7 4247static void
c620b772 4248mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4249 struct mlx5e_priv *priv,
4250 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4251 struct flow_cls_offload *f,
988ab9c7
TZ		 4252 struct mlx5_eswitch_rep *in_rep,
4253 struct mlx5_core_dev *in_mdev)
4254{
4255 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4256 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4257
c7569097 4258 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4259
4260 esw_attr->in_rep = in_rep;
4261 esw_attr->in_mdev = in_mdev;
4262
4263 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4264 MLX5_COUNTER_SOURCE_ESWITCH)
4265 esw_attr->counter_dev = in_mdev;
4266 else
4267 esw_attr->counter_dev = priv->mdev;
4268}
4269
71129676 4270static struct mlx5e_tc_flow *
04de7dda 4271__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4272 struct flow_cls_offload *f,
226f2ca3 4273 unsigned long flow_flags,
04de7dda
RD		 4274 struct net_device *filter_dev,
4275 struct mlx5_eswitch_rep *in_rep,
71129676 4276 struct mlx5_core_dev *in_mdev)
a88780a9 4277{
f9e30088 4278 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4279 struct netlink_ext_ack *extack = f->common.extack;
4280 struct mlx5e_tc_flow_parse_attr *parse_attr;
4281 struct mlx5e_tc_flow *flow;
4282 int attr_size, err;
e3a2b7ed 4283
226f2ca3 4284 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4285 attr_size = sizeof(struct mlx5_esw_flow_attr);
4286 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4287 &parse_attr, &flow);
4288 if (err)
4289 goto out;
988ab9c7 4290
d11afc26 4291 parse_attr->filter_dev = filter_dev;
c620b772 4292 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4293 priv, parse_attr,
4294 f, in_rep, in_mdev);
4295
54c177ca
OS		 4296 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4297 f, filter_dev);
d11afc26
OS		 4298 if (err)
4299 goto err_free;
a88780a9 4300
7e36feeb 4301 /* actions validation depends on parsing the ct matches first */
aedd133d 4302 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4303 &flow->attr->ct_attr, extack);
a88780a9
RD		 4304 if (err)
4305 goto err_free;
4306
70f8019e 4307 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 4308 if (err)
4309 goto err_free;
4310
7040632d 4311 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4312 complete_all(&flow->init_done);
ef06c9ee
RD		 4313 if (err) {
4314 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4315 goto err_free;
4316
b4a23329 4317 add_unready_flow(flow);
ef06c9ee 4318 }
e3a2b7ed 4319
71129676 4320 return flow;
a88780a9
RD		 4321
4322err_free:
5a7e5bcb 4323 mlx5e_flow_put(priv, flow);
a88780a9 4324out:
71129676 4325 return ERR_PTR(err);
a88780a9
RD		 4326}
4327
f9e30088 4328static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4329 struct mlx5e_tc_flow *flow,
226f2ca3 4330 unsigned long flow_flags)
04de7dda
RD		 4331{
4332 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4333 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4334 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4335 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4336 struct mlx5e_tc_flow_parse_attr *parse_attr;
4337 struct mlx5e_rep_priv *peer_urpriv;
4338 struct mlx5e_tc_flow *peer_flow;
4339 struct mlx5_core_dev *in_mdev;
4340 int err = 0;
4341
4342 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4343 if (!peer_esw)
4344 return -ENODEV;
4345
4346 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4347 peer_priv = netdev_priv(peer_urpriv->netdev);
4348
4349 /* in_mdev is assigned of which the packet originated from.
4350 * So packets redirected to uplink use the same mdev of the
4351 * original flow and packets redirected from uplink use the
4352 * peer mdev.
4353 */
c620b772 4354 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4355 in_mdev = peer_priv->mdev;
4356 else
4357 in_mdev = priv->mdev;
4358
c620b772 4359 parse_attr = flow->attr->parse_attr;
95dc1902 4360 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4361 parse_attr->filter_dev,
c620b772 4362 attr->in_rep, in_mdev);
71129676
JG		 4363 if (IS_ERR(peer_flow)) {
4364 err = PTR_ERR(peer_flow);
04de7dda 4365 goto out;
71129676 4366 }
04de7dda
RD		 4367
4368 flow->peer_flow = peer_flow;
226f2ca3 4369 flow_flag_set(flow, DUP);
04de7dda
RD		 4370 mutex_lock(&esw->offloads.peer_mutex);
4371 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4372 mutex_unlock(&esw->offloads.peer_mutex);
4373
4374out:
4375 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4376 return err;
4377}
4378
4379static int
4380mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4381 struct flow_cls_offload *f,
226f2ca3 4382 unsigned long flow_flags,
04de7dda
RD		 4383 struct net_device *filter_dev,
4384 struct mlx5e_tc_flow **__flow)
4385{
4386 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4387 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4388 struct mlx5_core_dev *in_mdev = priv->mdev;
4389 struct mlx5e_tc_flow *flow;
4390 int err;
4391
71129676
JG		 4392 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4393 in_mdev);
4394 if (IS_ERR(flow))
4395 return PTR_ERR(flow);
04de7dda
RD		 4396
4397 if (is_peer_flow_needed(flow)) {
95dc1902 4398 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4399 if (err) {
4400 mlx5e_tc_del_fdb_flow(priv, flow);
4401 goto out;
4402 }
4403 }
4404
4405 *__flow = flow;
4406
4407 return 0;
4408
4409out:
4410 return err;
4411}
4412
a88780a9
RD		 4413static int
4414mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4415 struct flow_cls_offload *f,
226f2ca3 4416 unsigned long flow_flags,
d11afc26 4417 struct net_device *filter_dev,
a88780a9
RD		 4418 struct mlx5e_tc_flow **__flow)
4419{
f9e30088 4420 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4421 struct netlink_ext_ack *extack = f->common.extack;
4422 struct mlx5e_tc_flow_parse_attr *parse_attr;
4423 struct mlx5e_tc_flow *flow;
4424 int attr_size, err;
4425
c7569097
AL		 4426 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4427 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4428 return -EOPNOTSUPP;
4429 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4430 return -EOPNOTSUPP;
c7569097 4431 }
bf07aa73 4432
226f2ca3 4433 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4434 attr_size = sizeof(struct mlx5_nic_flow_attr);
4435 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4436 &parse_attr, &flow);
4437 if (err)
4438 goto out;
4439
d11afc26 4440 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4441 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4442
54c177ca
OS		 4443 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4444 f, filter_dev);
d11afc26
OS		 4445 if (err)
4446 goto err_free;
4447
aedd133d
AL		 4448 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4449 &flow->attr->ct_attr, extack);
4450 if (err)
4451 goto err_free;
4452
c6cfe113 4453 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4454 if (err)
4455 goto err_free;
4456
c6cfe113 4457 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 4458 if (err)
4459 goto err_free;
4460
226f2ca3 4461 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4462 *__flow = flow;
4463
4464 return 0;
e3a2b7ed 4465
e3a2b7ed 4466err_free:
8914add2 4467 flow_flag_set(flow, FAILED);
e68e28b4 4468 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4469 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4470out:
4471 return err;
4472}
4473
4474static int
4475mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4476 struct flow_cls_offload *f,
226f2ca3 4477 unsigned long flags,
d11afc26 4478 struct net_device *filter_dev,
a88780a9
RD		 4479 struct mlx5e_tc_flow **flow)
4480{
4481 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4482 unsigned long flow_flags;
a88780a9
RD		 4483 int err;
4484
4485 get_flags(flags, &flow_flags);
4486
bf07aa73
PB		 4487 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4488 return -EOPNOTSUPP;
4489
f6455de0 4490 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4491 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4492 filter_dev, flow);
a88780a9 4493 else
d11afc26
OS		 4494 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4495 filter_dev, flow);
a88780a9
RD		 4496
4497 return err;
4498}
4499
553f9328
VP		 4500static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4501 struct mlx5e_rep_priv *rpriv)
4502{
4503 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4504 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4505 * function is called from NIC mode.
553f9328 4506 */
2fb15e72 4507 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4508}
4509
71d82d2a 4510int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4511 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4512{
4513 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4514 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4515 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4516 struct mlx5e_tc_flow *flow;
4517 int err = 0;
4518
7dc84de9
RD		 4519 if (!mlx5_esw_hold(priv->mdev))
4520 return -EAGAIN;
4521
4522 mlx5_esw_get(priv->mdev);
4523
c5d326b2
VB		 4524 rcu_read_lock();
4525 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4526 if (flow) {
553f9328
VP		 4527 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4528 * just return 0.
4529 */
4530 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4531 goto rcu_unlock;
553f9328 4532
a88780a9
RD		 4533 NL_SET_ERR_MSG_MOD(extack,
4534 "flow cookie already exists, ignoring");
4535 netdev_warn_once(priv->netdev,
4536 "flow cookie %lx already exists, ignoring\n",
4537 f->cookie);
0e1c1a2f 4538 err = -EEXIST;
c1aea9e1 4539 goto rcu_unlock;
a88780a9 4540 }
c1aea9e1
VB		 4541rcu_unlock:
4542 rcu_read_unlock();
4543 if (flow)
4544 goto out;
a88780a9 4545
7a978759 4546 trace_mlx5e_configure_flower(f);
d11afc26 4547 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4548 if (err)
4549 goto out;
4550
553f9328
VP		 4551 /* Flow rule offloaded to non-uplink representor sharing tc block,
4552 * set the flow's owner dev.
4553 */
4554 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4555 flow->orig_dev = dev;
4556
c5d326b2 4557 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4558 if (err)
4559 goto err_free;
4560
7dc84de9 4561 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4562 return 0;
4563
4564err_free:
5a7e5bcb 4565 mlx5e_flow_put(priv, flow);
a88780a9 4566out:
7dc84de9
RD		 4567 mlx5_esw_put(priv->mdev);
4568 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4569 return err;
4570}
4571
8f8ae895
OG		 4572static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4573{
226f2ca3
VB		 4574 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4575 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4576
226f2ca3
VB		 4577 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4578 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4579}
4580
71d82d2a 4581int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4582 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4583{
d9ee0491 4584 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4585 struct mlx5e_tc_flow *flow;
c5d326b2 4586 int err;
e3a2b7ed 4587
c5d326b2 4588 rcu_read_lock();
ab818362 4589 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4590 if (!flow || !same_flow_direction(flow, flags)) {
4591 err = -EINVAL;
4592 goto errout;
4593 }
e3a2b7ed 4594
c5d326b2
VB		 4595 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4596 * set.
4597 */
4598 if (flow_flag_test_and_set(flow, DELETED)) {
4599 err = -EINVAL;
4600 goto errout;
4601 }
05866c82 4602 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4603 rcu_read_unlock();
e3a2b7ed 4604
7a978759 4605 trace_mlx5e_delete_flower(f);
5a7e5bcb 4606 mlx5e_flow_put(priv, flow);
e3a2b7ed 4607
7dc84de9 4608 mlx5_esw_put(priv->mdev);
e3a2b7ed 4609 return 0;
c5d326b2
VB		 4610
4611errout:
4612 rcu_read_unlock();
4613 return err;
e3a2b7ed
AV		 4614}
4615
71d82d2a 4616int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4617 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4618{
04de7dda 4619 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4620 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4621 struct mlx5_eswitch *peer_esw;
aad7e08d 4622 struct mlx5e_tc_flow *flow;
aad7e08d 4623 struct mlx5_fc *counter;
316d5f72
RD		 4624 u64 lastuse = 0;
4625 u64 packets = 0;
4626 u64 bytes = 0;
5a7e5bcb 4627 int err = 0;
aad7e08d 4628
c5d326b2
VB		 4629 rcu_read_lock();
4630 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4631 tc_ht_params));
4632 rcu_read_unlock();
5a7e5bcb
VB		 4633 if (IS_ERR(flow))
4634 return PTR_ERR(flow);
4635
4636 if (!same_flow_direction(flow, flags)) {
4637 err = -EINVAL;
4638 goto errout;
4639 }
aad7e08d 4640
4c3844d9 4641 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4642 counter = mlx5e_tc_get_counter(flow);
4643 if (!counter)
5a7e5bcb 4644 goto errout;
aad7e08d 4645
316d5f72
RD		 4646 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4647 }
aad7e08d 4648
316d5f72
RD		 4649 /* Under multipath it's possible for one rule to be currently
4650 * un-offloaded while the other rule is offloaded.
4651 */
04de7dda
RD		 4652 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4653 if (!peer_esw)
4654 goto out;
4655
226f2ca3
VB		 4656 if (flow_flag_test(flow, DUP) &&
4657 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4658 u64 bytes2;
4659 u64 packets2;
4660 u64 lastuse2;
4661
4662 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4663 if (!counter)
4664 goto no_peer_counter;
04de7dda
RD		 4665 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4666
4667 bytes += bytes2;
4668 packets += packets2;
4669 lastuse = max_t(u64, lastuse, lastuse2);
4670 }
4671
316d5f72 4672no_peer_counter:
04de7dda 4673 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4674out:
4b61d3e8 4675 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4676 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4677 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4678errout:
4679 mlx5e_flow_put(priv, flow);
4680 return err;
aad7e08d
AV		 4681}
4682
1fe3e316 4683static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4684 struct netlink_ext_ack *extack)
4685{
4686 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4687 struct mlx5_eswitch *esw;
1fe3e316 4688 u32 rate_mbps = 0;
fcb64c0f 4689 u16 vport_num;
fcb64c0f
EC		 4690 int err;
4691
e401a184
EC		 4692 vport_num = rpriv->rep->vport;
4693 if (vport_num >= MLX5_VPORT_ECPF) {
4694 NL_SET_ERR_MSG_MOD(extack,
4695 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4696 return -EOPNOTSUPP;
4697 }
4698
fcb64c0f
EC		 4699 esw = priv->mdev->priv.eswitch;
4700 /* rate is given in bytes/sec.
4701 * First convert to bits/sec and then round to the nearest mbit/secs.
4702 * mbit means million bits.
4703 * Moreover, if rate is non zero we choose to configure to a minimum of
4704 * 1 mbit/sec.
4705 */
1fe3e316
PP		 4706 if (rate) {
4707 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4708 do_div(rate, 1000000);
4709 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4710 }
4711
2d116e3e 4712 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4713 if (err)
4714 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4715
4716 return err;
4717}
4718
4719static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4720 struct flow_action *flow_action,
4721 struct netlink_ext_ack *extack)
4722{
4723 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4724 const struct flow_action_entry *act;
4725 int err;
4726 int i;
4727
4728 if (!flow_action_has_entries(flow_action)) {
4729 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4730 return -EINVAL;
4731 }
4732
4733 if (!flow_offload_has_one_action(flow_action)) {
4734 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4735 return -EOPNOTSUPP;
4736 }
4737
53eca1f3 4738 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4739 return -EOPNOTSUPP;
4740
fcb64c0f
EC		 4741 flow_action_for_each(i, act, flow_action) {
4742 switch (act->id) {
4743 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4744 if (act->police.rate_pkt_ps) {
4745 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4746 return -EOPNOTSUPP;
4747 }
fcb64c0f
EC		 4748 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4749 if (err)
4750 return err;
4751
4752 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4753 break;
4754 default:
4755 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4756 return -EOPNOTSUPP;
4757 }
4758 }
4759
4760 return 0;
4761}
4762
4763int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4764 struct tc_cls_matchall_offload *ma)
4765{
b5f814cc 4766 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4767 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4768
b5f814cc
EC		 4769 if (!mlx5_esw_qos_enabled(esw)) {
4770 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4771 return -EOPNOTSUPP;
4772 }
4773
7b83355f 4774 if (ma->common.prio != 1) {
fcb64c0f
EC		 4775 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4776 return -EINVAL;
4777 }
4778
4779 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4780}
4781
4782int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4783 struct tc_cls_matchall_offload *ma)
4784{
4785 struct netlink_ext_ack *extack = ma->common.extack;
4786
4787 return apply_police_params(priv, 0, extack);
4788}
4789
4790void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4791 struct tc_cls_matchall_offload *ma)
4792{
4793 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4794 struct rtnl_link_stats64 cur_stats;
4795 u64 dbytes;
4796 u64 dpkts;
4797
4798 cur_stats = priv->stats.vf_vport;
4799 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4800 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4801 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4802 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4803 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4804}
4805
4d8fcf21
AH		 4806static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4807 struct mlx5e_priv *peer_priv)
4808{
4809 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4810 struct mlx5e_hairpin_entry *hpe, *tmp;
4811 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4812 u16 peer_vhca_id;
4813 int bkt;
4814
4815 if (!same_hw_devs(priv, peer_priv))
4816 return;
4817
4818 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4819
b32accda 4820 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4821 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4822 if (refcount_inc_not_zero(&hpe->refcnt))
4823 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4824 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4825
4826 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4827 wait_for_completion(&hpe->res_ready);
4828 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4829 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4830
4831 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4832 }
4833}
4834
4835static int mlx5e_tc_netdev_event(struct notifier_block *this,
4836 unsigned long event, void *ptr)
4837{
4838 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4839 struct mlx5e_flow_steering *fs;
4840 struct mlx5e_priv *peer_priv;
4841 struct mlx5e_tc_table *tc;
4842 struct mlx5e_priv *priv;
4843
4844 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4845 event != NETDEV_UNREGISTER ||
4846 ndev->reg_state == NETREG_REGISTERED)
4847 return NOTIFY_DONE;
4848
4849 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4850 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4851 priv = container_of(fs, struct mlx5e_priv, fs);
4852 peer_priv = netdev_priv(ndev);
4853 if (priv == peer_priv ||
4854 !(priv->netdev->features & NETIF_F_HW_TC))
4855 return NOTIFY_DONE;
4856
4857 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4858
4859 return NOTIFY_DONE;
4860}
4861
6a064674
AL		 4862static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4863{
4864 int tc_grp_size, tc_tbl_size;
4865 u32 max_flow_counter;
4866
4867 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4868 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4869
4870 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4871
4872 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4873 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4874
4875 return tc_tbl_size;
4876}
4877
655dc3d2 4878int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4879{
acff797c 4880 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4881 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4882 struct mapping_ctx *chains_mapping;
6a064674 4883 struct mlx5_chains_attr attr = {};
2198b932 4884 u64 mapping_id;
4d8fcf21 4885 int err;
e8f887ac 4886
b2fdf3d0 4887 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4888 mutex_init(&tc->t_lock);
b32accda 4889 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4890 hash_init(tc->hairpin_tbl);
11c9c548 4891
4d8fcf21
AH		 4892 err = rhashtable_init(&tc->ht, &tc_ht_params);
4893 if (err)
4894 return err;
4895
9ba33339
RD		 4896 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4897
2198b932
RD		 4898 mapping_id = mlx5_query_nic_system_image_guid(dev);
4899
4900 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4901 sizeof(struct mlx5_mapped_obj),
4902 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4903
c9355682
CM		 4904 if (IS_ERR(chains_mapping)) {
4905 err = PTR_ERR(chains_mapping);
4906 goto err_mapping;
4907 }
4908 tc->mapping = chains_mapping;
4909
4910 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4911 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4912 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4913 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4914 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4915 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4916 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4917 attr.mapping = chains_mapping;
6a064674
AL		 4918
4919 tc->chains = mlx5_chains_create(dev, &attr);
4920 if (IS_ERR(tc->chains)) {
4921 err = PTR_ERR(tc->chains);
4922 goto err_chains;
4923 }
4924
f0da4daa 4925 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4926 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4927 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4928
4d8fcf21 4929 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4930 err = register_netdevice_notifier_dev_net(priv->netdev,
4931 &tc->netdevice_nb,
4932 &tc->netdevice_nn);
4933 if (err) {
4d8fcf21
AH		 4934 tc->netdevice_nb.notifier_call = NULL;
4935 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4936 goto err_reg;
4d8fcf21
AH		 4937 }
4938
6a064674
AL		 4939 return 0;
4940
4941err_reg:
aedd133d 4942 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4943 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 4944 mlx5_chains_destroy(tc->chains);
4945err_chains:
c9355682
CM		 4946 mapping_destroy(chains_mapping);
4947err_mapping:
6a064674 4948 rhashtable_destroy(&tc->ht);
4d8fcf21 4949 return err;
e8f887ac
AV		 4950}
4951
4952static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4953{
4954 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4955 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4956
961e8979 4957 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4958 kfree(flow);
4959}
4960
655dc3d2 4961void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4962{
acff797c 4963 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4964
4d8fcf21 4965 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4966 unregister_netdevice_notifier_dev_net(priv->netdev,
4967 &tc->netdevice_nb,
4968 &tc->netdevice_nn);
4d8fcf21 4969
b2fdf3d0 4970 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4971 mutex_destroy(&tc->hairpin_tbl_lock);
4972
6a064674 4973 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4974
acff797c 4975 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4976 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4977 tc->t = NULL;
e8f887ac 4978 }
b6fac0b4 4979 mutex_destroy(&tc->t_lock);
6a064674 4980
aedd133d 4981 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4982 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 4983 mapping_destroy(tc->mapping);
6a064674 4984 mlx5_chains_destroy(tc->chains);
e8f887ac 4985}
655dc3d2
OG		 4986
4987int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4988{
d7a42ad0 4989 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4990 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4991 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4992 struct mapping_ctx *mapping;
aedd133d
AL		 4993 struct mlx5_eswitch *esw;
4994 struct mlx5e_priv *priv;
2198b932 4995 u64 mapping_id;
aedd133d 4996 int err = 0;
0a7fcb78
PB		 4997
4998 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4999 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5000 priv = netdev_priv(rpriv->netdev);
5001 esw = priv->mdev->priv.eswitch;
0a7fcb78 5002
f0da4daa
CM		 5003 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5004 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 5005 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5006 esw_chains(esw),
5007 &esw->offloads.mod_hdr,
f0da4daa
CM		 5008 MLX5_FLOW_NAMESPACE_FDB,
5009 uplink_priv->post_act);
4c3844d9 5010
2741f223 5011 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a 5012
2198b932
RD		 5013 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5014
5015 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5016 sizeof(struct tunnel_match_key),
5017 TUNNEL_INFO_BITS_MASK, true);
5018
0a7fcb78
PB		 5019 if (IS_ERR(mapping)) {
5020 err = PTR_ERR(mapping);
5021 goto err_tun_mapping;
5022 }
5023 uplink_priv->tunnel_mapping = mapping;
5024
8e404fef 5025 /* 0xFFF is reserved for stack devices slow path table mark */
2198b932
RD		 5026 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5027 sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 5028 if (IS_ERR(mapping)) {
5029 err = PTR_ERR(mapping);
5030 goto err_enc_opts_mapping;
5031 }
5032 uplink_priv->tunnel_enc_opts_mapping = mapping;
5033
5034 err = rhashtable_init(tc_ht, &tc_ht_params);
5035 if (err)
5036 goto err_ht_init;
5037
9ba33339
RD		 5038 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5039
8914add2 5040 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 5041 if (IS_ERR(uplink_priv->encap)) {
5042 err = PTR_ERR(uplink_priv->encap);
8914add2 5043 goto err_register_fib_notifier;
2b6c3c1e 5044 }
8914add2 5045
2b6c3c1e 5046 return 0;
0a7fcb78 5047
8914add2
VB		 5048err_register_fib_notifier:
5049 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5050err_ht_init:
5051 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5052err_enc_opts_mapping:
5053 mapping_destroy(uplink_priv->tunnel_mapping);
5054err_tun_mapping:
0027d70c 5055 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
aedd133d 5056 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5057 netdev_warn(priv->netdev,
5058 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 5059 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 5060 return err;
655dc3d2
OG		 5061}
5062
5063void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5064{
0a7fcb78
PB		 5065 struct mlx5_rep_uplink_priv *uplink_priv;
5066
0a7fcb78 5067 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5068
8914add2
VB		 5069 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5070 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5071
0a7fcb78
PB		 5072 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5073 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5074
0027d70c 5075 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
aedd133d 5076 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 5077 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 5078}
01252a27 5079
226f2ca3 5080int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5081{
d9ee0491 5082 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5083
5084 return atomic_read(&tc_ht->nelems);
5085}
04de7dda
RD		 5086
5087void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5088{
5089 struct mlx5e_tc_flow *flow, *tmp;
5090
5091 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5092 __mlx5e_tc_del_fdb_peer_flow(flow);
5093}
b4a23329
RD		 5094
5095void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5096{
5097 struct mlx5_rep_uplink_priv *rpriv =
5098 container_of(work, struct mlx5_rep_uplink_priv,
5099 reoffload_flows_work);
5100 struct mlx5e_tc_flow *flow, *tmp;
5101
ad86755b 5102 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5103 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5104 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5105 unready_flow_del(flow);
b4a23329 5106 }
ad86755b 5107 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5108}
e2394a61
VB		 5109
5110static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5111 struct flow_cls_offload *cls_flower,
5112 unsigned long flags)
5113{
5114 switch (cls_flower->command) {
5115 case FLOW_CLS_REPLACE:
5116 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5117 flags);
5118 case FLOW_CLS_DESTROY:
5119 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5120 flags);
5121 case FLOW_CLS_STATS:
5122 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5123 flags);
5124 default:
5125 return -EOPNOTSUPP;
5126 }
5127}
5128
5129int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5130 void *cb_priv)
5131{
ec9457a6 5132 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5133 struct mlx5e_priv *priv = cb_priv;
5134
2ff349c5
RD		 5135 if (!priv->netdev || !netif_device_present(priv->netdev))
5136 return -EOPNOTSUPP;
5137
ec9457a6
RD		 5138 if (mlx5e_is_uplink_rep(priv))
5139 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5140 else
5141 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5142
e2394a61
VB		 5143 switch (type) {
5144 case TC_SETUP_CLSFLOWER:
5145 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5146 default:
5147 return -EOPNOTSUPP;
5148 }
5149}
c7569097
AL		 5150
5151bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5152 struct sk_buff *skb)
5153{
5154#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5155 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5156 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5157 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5158 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5159 struct tc_skb_ext *tc_skb_ext;
5160 int err;
5161
5162 reg_b = be32_to_cpu(cqe->ft_metadata);
5163
5164 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5165
c9355682 5166 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5167 if (err) {
5168 netdev_dbg(priv->netdev,
5169 "Couldn't find chain for chain tag: %d, err: %d\n",
5170 chain_tag, err);
5171 return false;
5172 }
5173
a91d98a0
CM		 5174 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5175 chain = mapped_obj.chain;
9453d45e 5176 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5177 if (WARN_ON(!tc_skb_ext))
5178 return false;
5179
5180 tc_skb_ext->chain = chain;
aedd133d 5181
ed2fe7ba 5182 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5183 ESW_ZONE_ID_MASK;
aedd133d
AL		 5184
5185 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5186 zone_restore_id))
5187 return false;
a91d98a0
CM		 5188 } else {
5189 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5190 return false;
c7569097
AL		 5191 }
5192#endif /* CONFIG_NET_TC_SKB_EXT */
5193
5194 return true;
5195}
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