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UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
db76ca24 42#include <linux/completion.h>
03a9d11e 43#include <net/tc_act/tc_mirred.h>
776b12b6 44#include <net/tc_act/tc_vlan.h>
bbd00f7e 45#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 46#include <net/tc_act/tc_pedit.h>
26c02749 47#include <net/tc_act/tc_csum.h>
f6dfb4c3 48#include <net/arp.h>
3616d08b 49#include <net/ipv6_stubs.h>
e8f887ac 50#include "en.h"
1d447a39 51#include "en_rep.h"
232c0013 52#include "en_tc.h"
03a9d11e 53#include "eswitch.h"
3f6d08d1 54#include "fs_core.h"
2c81bfd5 55#include "en/port.h"
101f4de9 56#include "en/tc_tun.h"
04de7dda 57#include "lib/devcom.h"
9272e3df 58#include "lib/geneve.h"
7a978759 59#include "diag/en_tc_tracepoint.h"
d82e406f 60#include <asm/div64.h>
e8f887ac 61
3bc4b7bf
OG		 62struct mlx5_nic_flow_attr {
63 u32 action;
64 u32 flow_tag;
2b688ea5 65 struct mlx5_modify_hdr *modify_hdr;
5c65c564 66 u32 hairpin_tirn;
38aa51c1 67 u8 match_level;
3f6d08d1 68 struct mlx5_flow_table *hairpin_ft;
b8aee822 69 struct mlx5_fc *counter;
3bc4b7bf
OG		 70};
71
226f2ca3 72#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 73
65ba8fb7 74enum {
226f2ca3
VB		 75 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
76 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
77 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
78 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
79 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
80 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
81 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
82 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
83 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
84 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 85 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
65ba8fb7
OG		 86};
87
e4ad91f2
CM		 88#define MLX5E_TC_MAX_SPLITS 1
89
79baaec7
EB		 90/* Helper struct for accessing a struct containing list_head array.
91 * Containing struct
92 * |- Helper array
93 * [0] Helper item 0
94 * |- list_head item 0
95 * |- index (0)
96 * [1] Helper item 1
97 * |- list_head item 1
98 * |- index (1)
99 * To access the containing struct from one of the list_head items:
100 * 1. Get the helper item from the list_head item using
101 * helper item =
102 * container_of(list_head item, helper struct type, list_head field)
103 * 2. Get the contining struct from the helper item and its index in the array:
104 * containing struct =
105 * container_of(helper item, containing struct type, helper field[index])
106 */
107struct encap_flow_item {
948993f2 108 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 109 struct list_head list;
110 int index;
111};
112
e8f887ac
AV		 113struct mlx5e_tc_flow {
114 struct rhash_head node;
655dc3d2 115 struct mlx5e_priv *priv;
e8f887ac 116 u64 cookie;
226f2ca3 117 unsigned long flags;
e4ad91f2 118 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 119 /* Flow can be associated with multiple encap IDs.
120 * The number of encaps is bounded by the number of supported
121 * destinations.
122 */
123 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 124 struct mlx5e_tc_flow *peer_flow;
dd58edc3 125 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 126 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 127 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 128 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 129 struct list_head peer; /* flows with peer flow */
b4a23329 130 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
2a1f1768 131 int tmp_efi_index;
6a06c2f7 132 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 133 refcount_t refcnt;
c5d326b2 134 struct rcu_head rcu_head;
95435ad7 135 struct completion init_done;
3bc4b7bf
OG		 136 union {
137 struct mlx5_esw_flow_attr esw_attr[0];
138 struct mlx5_nic_flow_attr nic_attr[0];
139 };
e8f887ac
AV		 140};
141
17091853 142struct mlx5e_tc_flow_parse_attr {
1f6da306 143 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 144 struct net_device *filter_dev;
17091853 145 struct mlx5_flow_spec spec;
d79b6df6 146 int num_mod_hdr_actions;
218d05ce 147 int max_mod_hdr_actions;
d79b6df6 148 void *mod_hdr_actions;
98b66cb1 149 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 150};
151
acff797c 152#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 153#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 154
77ab67b7
OG		 155struct mlx5e_hairpin {
156 struct mlx5_hairpin *pair;
157
158 struct mlx5_core_dev *func_mdev;
3f6d08d1 159 struct mlx5e_priv *func_priv;
77ab67b7
OG		 160 u32 tdn;
161 u32 tirn;
3f6d08d1
OG		 162
163 int num_channels;
164 struct mlx5e_rqt indir_rqt;
165 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
166 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 167};
168
5c65c564
OG		 169struct mlx5e_hairpin_entry {
170 /* a node of a hash table which keeps all the hairpin entries */
171 struct hlist_node hairpin_hlist;
172
73edca73
VB		 173 /* protects flows list */
174 spinlock_t flows_lock;
5c65c564
OG		 175 /* flows sharing the same hairpin */
176 struct list_head flows;
db76ca24
VB		 177 /* hpe's that were not fully initialized when dead peer update event
178 * function traversed them.
179 */
180 struct list_head dead_peer_wait_list;
5c65c564 181
d8822868 182 u16 peer_vhca_id;
106be53b 183 u8 prio;
5c65c564 184 struct mlx5e_hairpin *hp;
e4f9abbd 185 refcount_t refcnt;
db76ca24 186 struct completion res_ready;
5c65c564
OG		 187};
188
11c9c548
OG		 189struct mod_hdr_key {
190 int num_actions;
191 void *actions;
192};
193
194struct mlx5e_mod_hdr_entry {
195 /* a node of a hash table which keeps all the mod_hdr entries */
196 struct hlist_node mod_hdr_hlist;
197
83a52f0d
VB		 198 /* protects flows list */
199 spinlock_t flows_lock;
11c9c548
OG		 200 /* flows sharing the same mod_hdr entry */
201 struct list_head flows;
202
203 struct mod_hdr_key key;
204
2b688ea5 205 struct mlx5_modify_hdr *modify_hdr;
dd58edc3
VB		 206
207 refcount_t refcnt;
a734d007
VB		 208 struct completion res_ready;
209 int compl_result;
11c9c548
OG		 210};
211
212#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
213
5a7e5bcb
VB		 214static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
215 struct mlx5e_tc_flow *flow);
216
217static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
218{
219 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
220 return ERR_PTR(-EINVAL);
221 return flow;
222}
223
224static void mlx5e_flow_put(struct mlx5e_priv *priv,
225 struct mlx5e_tc_flow *flow)
226{
227 if (refcount_dec_and_test(&flow->refcnt)) {
228 mlx5e_tc_del_flow(priv, flow);
c5d326b2 229 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 230 }
231}
232
226f2ca3
VB		 233static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
234{
235 /* Complete all memory stores before setting bit. */
236 smp_mb__before_atomic();
237 set_bit(flag, &flow->flags);
238}
239
240#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
241
c5d326b2
VB		 242static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
243 unsigned long flag)
244{
245 /* test_and_set_bit() provides all necessary barriers */
246 return test_and_set_bit(flag, &flow->flags);
247}
248
249#define flow_flag_test_and_set(flow, flag) \
250 __flow_flag_test_and_set(flow, \
251 MLX5E_TC_FLOW_FLAG_##flag)
252
226f2ca3
VB		 253static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
254{
255 /* Complete all memory stores before clearing bit. */
256 smp_mb__before_atomic();
257 clear_bit(flag, &flow->flags);
258}
259
260#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
261 MLX5E_TC_FLOW_FLAG_##flag)
262
263static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
264{
265 bool ret = test_bit(flag, &flow->flags);
266
267 /* Read fields of flow structure only after checking flags. */
268 smp_mb__after_atomic();
269 return ret;
270}
271
272#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
273 MLX5E_TC_FLOW_FLAG_##flag)
274
275static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
276{
277 return flow_flag_test(flow, ESWITCH);
278}
279
280static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
281{
282 return flow_flag_test(flow, OFFLOADED);
283}
284
11c9c548
OG		 285static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
286{
287 return jhash(key->actions,
288 key->num_actions * MLX5_MH_ACT_SZ, 0);
289}
290
291static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
292 struct mod_hdr_key *b)
293{
294 if (a->num_actions != b->num_actions)
295 return 1;
296
297 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
298}
299
dd58edc3
VB		 300static struct mod_hdr_tbl *
301get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
302{
303 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
304
305 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
306 &priv->fs.tc.mod_hdr;
307}
308
309static struct mlx5e_mod_hdr_entry *
310mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
311{
312 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
313
314 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
315 if (!cmp_mod_hdr_info(&mh->key, key)) {
316 refcount_inc(&mh->refcnt);
317 found = mh;
318 break;
319 }
320 }
321
322 return found;
323}
324
325static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
d2faae25
VB		 326 struct mlx5e_mod_hdr_entry *mh,
327 int namespace)
dd58edc3 328{
d2faae25
VB		 329 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
330
331 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
dd58edc3 332 return;
d2faae25
VB		 333 hash_del(&mh->mod_hdr_hlist);
334 mutex_unlock(&tbl->lock);
dd58edc3
VB		 335
336 WARN_ON(!list_empty(&mh->flows));
a734d007 337 if (mh->compl_result > 0)
2b688ea5 338 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
d2faae25 339
dd58edc3
VB		 340 kfree(mh);
341}
342
d2faae25
VB		 343static int get_flow_name_space(struct mlx5e_tc_flow *flow)
344{
345 return mlx5e_is_eswitch_flow(flow) ?
346 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
347}
11c9c548
OG		 348static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
349 struct mlx5e_tc_flow *flow,
350 struct mlx5e_tc_flow_parse_attr *parse_attr)
351{
11c9c548
OG		 352 int num_actions, actions_size, namespace, err;
353 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 354 struct mod_hdr_tbl *tbl;
11c9c548 355 struct mod_hdr_key key;
11c9c548
OG		 356 u32 hash_key;
357
358 num_actions = parse_attr->num_mod_hdr_actions;
359 actions_size = MLX5_MH_ACT_SZ * num_actions;
360
361 key.actions = parse_attr->mod_hdr_actions;
362 key.num_actions = num_actions;
363
364 hash_key = hash_mod_hdr_info(&key);
365
d2faae25 366 namespace = get_flow_name_space(flow);
dd58edc3 367 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 368
d2faae25 369 mutex_lock(&tbl->lock);
dd58edc3 370 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
a734d007
VB		 371 if (mh) {
372 mutex_unlock(&tbl->lock);
373 wait_for_completion(&mh->res_ready);
374
375 if (mh->compl_result < 0) {
376 err = -EREMOTEIO;
377 goto attach_header_err;
378 }
11c9c548 379 goto attach_flow;
a734d007 380 }
11c9c548
OG		 381
382 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
d2faae25 383 if (!mh) {
a734d007
VB		 384 mutex_unlock(&tbl->lock);
385 return -ENOMEM;
d2faae25 386 }
11c9c548
OG		 387
388 mh->key.actions = (void *)mh + sizeof(*mh);
389 memcpy(mh->key.actions, key.actions, actions_size);
390 mh->key.num_actions = num_actions;
83a52f0d 391 spin_lock_init(&mh->flows_lock);
11c9c548 392 INIT_LIST_HEAD(&mh->flows);
dd58edc3 393 refcount_set(&mh->refcnt, 1);
a734d007
VB		 394 init_completion(&mh->res_ready);
395
396 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
397 mutex_unlock(&tbl->lock);
11c9c548 398
2b688ea5
MG		 399 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
400 mh->key.num_actions,
401 mh->key.actions);
402 if (IS_ERR(mh->modify_hdr)) {
403 err = PTR_ERR(mh->modify_hdr);
a734d007
VB		 404 mh->compl_result = err;
405 goto alloc_header_err;
406 }
407 mh->compl_result = 1;
408 complete_all(&mh->res_ready);
11c9c548
OG		 409
410attach_flow:
dd58edc3 411 flow->mh = mh;
83a52f0d 412 spin_lock(&mh->flows_lock);
11c9c548 413 list_add(&flow->mod_hdr, &mh->flows);
83a52f0d 414 spin_unlock(&mh->flows_lock);
d2faae25 415 if (mlx5e_is_eswitch_flow(flow))
2b688ea5 416 flow->esw_attr->modify_hdr = mh->modify_hdr;
11c9c548 417 else
2b688ea5 418 flow->nic_attr->modify_hdr = mh->modify_hdr;
11c9c548
OG		 419
420 return 0;
421
a734d007
VB		 422alloc_header_err:
423 complete_all(&mh->res_ready);
424attach_header_err:
425 mlx5e_mod_hdr_put(priv, mh, namespace);
11c9c548
OG		 426 return err;
427}
428
429static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
430 struct mlx5e_tc_flow *flow)
431{
5a7e5bcb 432 /* flow wasn't fully initialized */
dd58edc3 433 if (!flow->mh)
5a7e5bcb
VB		 434 return;
435
83a52f0d 436 spin_lock(&flow->mh->flows_lock);
11c9c548 437 list_del(&flow->mod_hdr);
83a52f0d 438 spin_unlock(&flow->mh->flows_lock);
11c9c548 439
d2faae25 440 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
dd58edc3 441 flow->mh = NULL;
11c9c548
OG		 442}
443
77ab67b7
OG		 444static
445struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
446{
dd52b9f7 447 struct mlx5_core_dev *mdev;
77ab67b7
OG		 448 struct net_device *netdev;
449 struct mlx5e_priv *priv;
450
dd52b9f7
DC		 451 netdev = dev_get_by_index(net, ifindex);
452 if (!netdev)
453 return ERR_PTR(-ENODEV);
454
77ab67b7 455 priv = netdev_priv(netdev);
dd52b9f7
DC		 456 mdev = priv->mdev;
457 dev_put(netdev);
458
459 /* Mirred tc action holds a refcount on the ifindex net_device (see
460 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
461 * after dev_put(netdev), while we're in the context of adding a tc flow.
462 *
463 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
464 * stored in a hairpin object, which exists until all flows, that refer to it, get
465 * removed.
466 *
467 * On the other hand, after a hairpin object has been created, the peer net_device may
468 * be removed/unbound while there are still some hairpin flows that are using it. This
469 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
470 * NETDEV_UNREGISTER event of the peer net_device.
471 */
472 return mdev;
77ab67b7
OG		 473}
474
475static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
476{
477 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
478 void *tirc;
479 int err;
480
481 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
482 if (err)
483 goto alloc_tdn_err;
484
485 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
486
487 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 488 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 489 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
490
491 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
492 if (err)
493 goto create_tir_err;
494
495 return 0;
496
497create_tir_err:
498 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
499alloc_tdn_err:
500 return err;
501}
502
503static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
504{
505 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
506 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
507}
508
3f6d08d1
OG		 509static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
510{
511 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
512 struct mlx5e_priv *priv = hp->func_priv;
513 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
514
515 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
516 hp->num_channels);
517
518 for (i = 0; i < sz; i++) {
519 ix = i;
bbeb53b8 520 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 521 ix = mlx5e_bits_invert(i, ilog2(sz));
522 ix = indirection_rqt[ix];
523 rqn = hp->pair->rqn[ix];
524 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
525 }
526}
527
528static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
529{
530 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
531 struct mlx5e_priv *priv = hp->func_priv;
532 struct mlx5_core_dev *mdev = priv->mdev;
533 void *rqtc;
534 u32 *in;
535
536 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
537 in = kvzalloc(inlen, GFP_KERNEL);
538 if (!in)
539 return -ENOMEM;
540
541 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
542
543 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
544 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
545
546 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
547
548 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
549 if (!err)
550 hp->indir_rqt.enabled = true;
551
552 kvfree(in);
553 return err;
554}
555
556static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
557{
558 struct mlx5e_priv *priv = hp->func_priv;
559 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
560 int tt, i, err;
561 void *tirc;
562
563 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 564 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
565
3f6d08d1
OG		 566 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
567 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
568
569 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
570 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
571 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 572 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
573
3f6d08d1
OG		 574 err = mlx5_core_create_tir(hp->func_mdev, in,
575 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
576 if (err) {
577 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
578 goto err_destroy_tirs;
579 }
580 }
581 return 0;
582
583err_destroy_tirs:
584 for (i = 0; i < tt; i++)
585 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
586 return err;
587}
588
589static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
590{
591 int tt;
592
593 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
594 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
595}
596
597static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
598 struct ttc_params *ttc_params)
599{
600 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
601 int tt;
602
603 memset(ttc_params, 0, sizeof(*ttc_params));
604
605 ttc_params->any_tt_tirn = hp->tirn;
606
607 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
608 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
609
d75ccaa8 610 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 611 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
612 ft_attr->prio = MLX5E_TC_PRIO;
613}
614
615static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
616{
617 struct mlx5e_priv *priv = hp->func_priv;
618 struct ttc_params ttc_params;
619 int err;
620
621 err = mlx5e_hairpin_create_indirect_rqt(hp);
622 if (err)
623 return err;
624
625 err = mlx5e_hairpin_create_indirect_tirs(hp);
626 if (err)
627 goto err_create_indirect_tirs;
628
629 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
630 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
631 if (err)
632 goto err_create_ttc_table;
633
634 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
635 hp->num_channels, hp->ttc.ft.t->id);
636
637 return 0;
638
639err_create_ttc_table:
640 mlx5e_hairpin_destroy_indirect_tirs(hp);
641err_create_indirect_tirs:
642 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
643
644 return err;
645}
646
647static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
648{
649 struct mlx5e_priv *priv = hp->func_priv;
650
651 mlx5e_destroy_ttc_table(priv, &hp->ttc);
652 mlx5e_hairpin_destroy_indirect_tirs(hp);
653 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
654}
655
77ab67b7
OG		 656static struct mlx5e_hairpin *
657mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
658 int peer_ifindex)
659{
660 struct mlx5_core_dev *func_mdev, *peer_mdev;
661 struct mlx5e_hairpin *hp;
662 struct mlx5_hairpin *pair;
663 int err;
664
665 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
666 if (!hp)
667 return ERR_PTR(-ENOMEM);
668
669 func_mdev = priv->mdev;
670 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
dd52b9f7
DC		 671 if (IS_ERR(peer_mdev)) {
672 err = PTR_ERR(peer_mdev);
673 goto create_pair_err;
674 }
77ab67b7
OG		 675
676 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
677 if (IS_ERR(pair)) {
678 err = PTR_ERR(pair);
679 goto create_pair_err;
680 }
681 hp->pair = pair;
682 hp->func_mdev = func_mdev;
3f6d08d1
OG		 683 hp->func_priv = priv;
684 hp->num_channels = params->num_channels;
77ab67b7
OG		 685
686 err = mlx5e_hairpin_create_transport(hp);
687 if (err)
688 goto create_transport_err;
689
3f6d08d1
OG		 690 if (hp->num_channels > 1) {
691 err = mlx5e_hairpin_rss_init(hp);
692 if (err)
693 goto rss_init_err;
694 }
695
77ab67b7
OG		 696 return hp;
697
3f6d08d1
OG		 698rss_init_err:
699 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 700create_transport_err:
701 mlx5_core_hairpin_destroy(hp->pair);
702create_pair_err:
703 kfree(hp);
704 return ERR_PTR(err);
705}
706
707static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
708{
3f6d08d1
OG		 709 if (hp->num_channels > 1)
710 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 711 mlx5e_hairpin_destroy_transport(hp);
712 mlx5_core_hairpin_destroy(hp->pair);
713 kvfree(hp);
714}
715
106be53b
OG		 716static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
717{
718 return (peer_vhca_id << 16 | prio);
719}
720
5c65c564 721static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 722 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 723{
724 struct mlx5e_hairpin_entry *hpe;
106be53b 725 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 726
727 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 728 hairpin_hlist, hash_key) {
e4f9abbd
VB		 729 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
730 refcount_inc(&hpe->refcnt);
5c65c564 731 return hpe;
e4f9abbd 732 }
5c65c564
OG		 733 }
734
735 return NULL;
736}
737
e4f9abbd
VB		 738static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
739 struct mlx5e_hairpin_entry *hpe)
740{
741 /* no more hairpin flows for us, release the hairpin pair */
b32accda 742 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 743 return;
b32accda
VB		 744 hash_del(&hpe->hairpin_hlist);
745 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 746
db76ca24
VB		 747 if (!IS_ERR_OR_NULL(hpe->hp)) {
748 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
749 dev_name(hpe->hp->pair->peer_mdev->device));
750
751 mlx5e_hairpin_destroy(hpe->hp);
752 }
e4f9abbd
VB		 753
754 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 755 kfree(hpe);
756}
757
106be53b
OG		 758#define UNKNOWN_MATCH_PRIO 8
759
760static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 761 struct mlx5_flow_spec *spec, u8 *match_prio,
762 struct netlink_ext_ack *extack)
106be53b
OG		 763{
764 void *headers_c, *headers_v;
765 u8 prio_val, prio_mask = 0;
766 bool vlan_present;
767
768#ifdef CONFIG_MLX5_CORE_EN_DCB
769 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 770 NL_SET_ERR_MSG_MOD(extack,
771 "only PCP trust state supported for hairpin");
106be53b
OG		 772 return -EOPNOTSUPP;
773 }
774#endif
775 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
776 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
777
778 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
779 if (vlan_present) {
780 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
781 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
782 }
783
784 if (!vlan_present || !prio_mask) {
785 prio_val = UNKNOWN_MATCH_PRIO;
786 } else if (prio_mask != 0x7) {
e98bedf5
EB		 787 NL_SET_ERR_MSG_MOD(extack,
788 "masked priority match not supported for hairpin");
106be53b
OG		 789 return -EOPNOTSUPP;
790 }
791
792 *match_prio = prio_val;
793 return 0;
794}
795
5c65c564
OG		 796static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
797 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 798 struct mlx5e_tc_flow_parse_attr *parse_attr,
799 struct netlink_ext_ack *extack)
5c65c564 800{
98b66cb1 801 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 802 struct mlx5_hairpin_params params;
d8822868 803 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 804 struct mlx5e_hairpin_entry *hpe;
805 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 806 u64 link_speed64;
807 u32 link_speed;
106be53b 808 u8 match_prio;
d8822868 809 u16 peer_id;
5c65c564
OG		 810 int err;
811
d8822868 812 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
dd52b9f7
DC		 813 if (IS_ERR(peer_mdev)) {
814 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
815 return PTR_ERR(peer_mdev);
816 }
817
d8822868 818 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 819 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 820 return -EOPNOTSUPP;
821 }
822
d8822868 823 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 824 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
825 extack);
106be53b
OG		 826 if (err)
827 return err;
b32accda
VB		 828
829 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 830 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 831 if (hpe) {
832 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
833 wait_for_completion(&hpe->res_ready);
834
835 if (IS_ERR(hpe->hp)) {
836 err = -EREMOTEIO;
837 goto out_err;
838 }
5c65c564 839 goto attach_flow;
db76ca24 840 }
5c65c564
OG		 841
842 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 843 if (!hpe) {
db76ca24
VB		 844 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
845 return -ENOMEM;
b32accda 846 }
5c65c564 847
73edca73 848 spin_lock_init(&hpe->flows_lock);
5c65c564 849 INIT_LIST_HEAD(&hpe->flows);
db76ca24 850 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 851 hpe->peer_vhca_id = peer_id;
106be53b 852 hpe->prio = match_prio;
e4f9abbd 853 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 854 init_completion(&hpe->res_ready);
855
856 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
857 hash_hairpin_info(peer_id, match_prio));
858 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 859
860 params.log_data_size = 15;
861 params.log_data_size = min_t(u8, params.log_data_size,
862 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
863 params.log_data_size = max_t(u8, params.log_data_size,
864 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 865
eb9180f7
OG		 866 params.log_num_packets = params.log_data_size -
867 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
868 params.log_num_packets = min_t(u8, params.log_num_packets,
869 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
870
871 params.q_counter = priv->q_counter;
3f6d08d1 872 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 873 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 874 link_speed = max_t(u32, link_speed, 50000);
875 link_speed64 = link_speed;
876 do_div(link_speed64, 50000);
877 params.num_channels = link_speed64;
878
5c65c564 879 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 880 hpe->hp = hp;
881 complete_all(&hpe->res_ready);
5c65c564
OG		 882 if (IS_ERR(hp)) {
883 err = PTR_ERR(hp);
db76ca24 884 goto out_err;
5c65c564
OG		 885 }
886
eb9180f7 887 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 888 hp->tirn, hp->pair->rqn[0],
889 dev_name(hp->pair->peer_mdev->device),
eb9180f7 890 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 891
5c65c564 892attach_flow:
3f6d08d1 893 if (hpe->hp->num_channels > 1) {
226f2ca3 894 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 895 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
896 } else {
897 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
898 }
b32accda 899
e4f9abbd 900 flow->hpe = hpe;
73edca73 901 spin_lock(&hpe->flows_lock);
5c65c564 902 list_add(&flow->hairpin, &hpe->flows);
73edca73 903 spin_unlock(&hpe->flows_lock);
3f6d08d1 904
5c65c564
OG		 905 return 0;
906
db76ca24
VB		 907out_err:
908 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 909 return err;
910}
911
912static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
913 struct mlx5e_tc_flow *flow)
914{
5a7e5bcb 915 /* flow wasn't fully initialized */
e4f9abbd 916 if (!flow->hpe)
5a7e5bcb
VB		 917 return;
918
73edca73 919 spin_lock(&flow->hpe->flows_lock);
5c65c564 920 list_del(&flow->hairpin);
73edca73
VB		 921 spin_unlock(&flow->hpe->flows_lock);
922
e4f9abbd
VB		 923 mlx5e_hairpin_put(priv, flow->hpe);
924 flow->hpe = NULL;
5c65c564
OG		 925}
926
c83954ab 927static int
74491de9 928mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 929 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 930 struct mlx5e_tc_flow *flow,
931 struct netlink_ext_ack *extack)
e8f887ac 932{
bb0ee7dc 933 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 934 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 935 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 936 struct mlx5_flow_destination dest[2] = {};
66958ed9 937 struct mlx5_flow_act flow_act = {
3bc4b7bf 938 .action = attr->action,
bb0ee7dc 939 .flags = FLOW_ACT_NO_APPEND,
66958ed9 940 };
aad7e08d 941 struct mlx5_fc *counter = NULL;
5c65c564 942 int err, dest_ix = 0;
e8f887ac 943
bb0ee7dc
JL		 944 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
945 flow_context->flow_tag = attr->flow_tag;
946
226f2ca3 947 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 948 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 949 if (err)
950 return err;
951
226f2ca3 952 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 953 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
954 dest[dest_ix].ft = attr->hairpin_ft;
955 } else {
5c65c564
OG		 956 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
957 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 958 }
959 dest_ix++;
3f6d08d1
OG		 960 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
961 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
962 dest[dest_ix].ft = priv->fs.vlan.ft.t;
963 dest_ix++;
5c65c564 964 }
aad7e08d 965
5c65c564
OG		 966 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
967 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 968 if (IS_ERR(counter))
969 return PTR_ERR(counter);
970
5c65c564 971 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 972 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 973 dest_ix++;
b8aee822 974 attr->counter = counter;
aad7e08d
AV		 975 }
976
2f4fe4ca 977 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 978 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 979 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 980 kfree(parse_attr->mod_hdr_actions);
c83954ab 981 if (err)
5a7e5bcb 982 return err;
2f4fe4ca
OG		 983 }
984
b6fac0b4 985 mutex_lock(&priv->fs.tc.t_lock);
acff797c 986 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 987 int tc_grp_size, tc_tbl_size;
988 u32 max_flow_counter;
989
990 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
991 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
992
993 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
994
995 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
996 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
997
acff797c
MG		 998 priv->fs.tc.t =
999 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
1000 MLX5E_TC_PRIO,
21b9c144 1001 tc_tbl_size,
acff797c 1002 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 1003 MLX5E_TC_FT_LEVEL, 0);
acff797c 1004 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 1005 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 1006 NL_SET_ERR_MSG_MOD(extack,
1007 "Failed to create tc offload table\n");
e8f887ac
AV		 1008 netdev_err(priv->netdev,
1009 "Failed to create tc offload table\n");
5a7e5bcb 1010 return PTR_ERR(priv->fs.tc.t);
e8f887ac 1011 }
e8f887ac
AV		 1012 }
1013
38aa51c1 1014 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 1015 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1016
c83954ab
RL		 1017 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
1018 &flow_act, dest, dest_ix);
b6fac0b4 1019 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 1020
a2b7189b 1021 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1022}
1023
d85cdccb
OG		 1024static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1025 struct mlx5e_tc_flow *flow)
1026{
513f8f7f 1027 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 1028 struct mlx5_fc *counter = NULL;
1029
b8aee822 1030 counter = attr->counter;
5a7e5bcb
VB		 1031 if (!IS_ERR_OR_NULL(flow->rule[0]))
1032 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1033 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1034
b6fac0b4 1035 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1036 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1037 mlx5_destroy_flow_table(priv->fs.tc.t);
1038 priv->fs.tc.t = NULL;
1039 }
b6fac0b4 1040 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1041
513f8f7f 1042 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1043 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1044
226f2ca3 1045 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1046 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1047}
1048
aa0cbbae 1049static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1050 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1051
3c37745e 1052static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1053 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1054 struct net_device *mirred_dev,
1055 int out_index,
8c4dc42b 1056 struct netlink_ext_ack *extack,
0ad060ee
RD		 1057 struct net_device **encap_dev,
1058 bool *encap_valid);
3c37745e 1059
6d2a3ed0
OG		 1060static struct mlx5_flow_handle *
1061mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1062 struct mlx5e_tc_flow *flow,
1063 struct mlx5_flow_spec *spec,
1064 struct mlx5_esw_flow_attr *attr)
1065{
1066 struct mlx5_flow_handle *rule;
1067
1068 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1069 if (IS_ERR(rule))
1070 return rule;
1071
e85e02ba 1072 if (attr->split_count) {
6d2a3ed0
OG		 1073 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1074 if (IS_ERR(flow->rule[1])) {
1075 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1076 return flow->rule[1];
1077 }
1078 }
1079
6d2a3ed0
OG		 1080 return rule;
1081}
1082
1083static void
1084mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1085 struct mlx5e_tc_flow *flow,
1086 struct mlx5_esw_flow_attr *attr)
1087{
226f2ca3 1088 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1089
e85e02ba 1090 if (attr->split_count)
6d2a3ed0
OG		 1091 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1092
1093 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1094}
1095
5dbe906f
PB		 1096static struct mlx5_flow_handle *
1097mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1098 struct mlx5e_tc_flow *flow,
1099 struct mlx5_flow_spec *spec,
1100 struct mlx5_esw_flow_attr *slow_attr)
1101{
1102 struct mlx5_flow_handle *rule;
1103
1104 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1105 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1106 slow_attr->split_count = 0;
154e62ab 1107 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 1108
1109 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1110 if (!IS_ERR(rule))
226f2ca3 1111 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1112
1113 return rule;
1114}
1115
1116static void
1117mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1118 struct mlx5e_tc_flow *flow,
1119 struct mlx5_esw_flow_attr *slow_attr)
1120{
1121 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1122 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1123 slow_attr->split_count = 0;
154e62ab 1124 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f 1125 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1126 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1127}
1128
ad86755b
VB		 1129/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1130 * function.
1131 */
1132static void unready_flow_add(struct mlx5e_tc_flow *flow,
1133 struct list_head *unready_flows)
1134{
1135 flow_flag_set(flow, NOT_READY);
1136 list_add_tail(&flow->unready, unready_flows);
1137}
1138
1139/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1140 * function.
1141 */
1142static void unready_flow_del(struct mlx5e_tc_flow *flow)
1143{
1144 list_del(&flow->unready);
1145 flow_flag_clear(flow, NOT_READY);
1146}
1147
b4a23329
RD		 1148static void add_unready_flow(struct mlx5e_tc_flow *flow)
1149{
1150 struct mlx5_rep_uplink_priv *uplink_priv;
1151 struct mlx5e_rep_priv *rpriv;
1152 struct mlx5_eswitch *esw;
1153
1154 esw = flow->priv->mdev->priv.eswitch;
1155 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1156 uplink_priv = &rpriv->uplink_priv;
1157
ad86755b
VB		 1158 mutex_lock(&uplink_priv->unready_flows_lock);
1159 unready_flow_add(flow, &uplink_priv->unready_flows);
1160 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1161}
1162
1163static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1164{
ad86755b
VB		 1165 struct mlx5_rep_uplink_priv *uplink_priv;
1166 struct mlx5e_rep_priv *rpriv;
1167 struct mlx5_eswitch *esw;
1168
1169 esw = flow->priv->mdev->priv.eswitch;
1170 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1171 uplink_priv = &rpriv->uplink_priv;
1172
1173 mutex_lock(&uplink_priv->unready_flows_lock);
1174 unready_flow_del(flow);
1175 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1176}
1177
c83954ab 1178static int
74491de9 1179mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1180 struct mlx5e_tc_flow *flow,
1181 struct netlink_ext_ack *extack)
adb4c123
OG		 1182{
1183 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 1184 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 1185 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1186 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 1187 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 1188 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1189 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1190 struct mlx5e_rep_priv *rpriv;
1191 struct mlx5e_priv *out_priv;
0ad060ee
RD		 1192 bool encap_valid = true;
1193 int err = 0;
f493f155 1194 int out_index;
8b32580d 1195
d14f6f2a
OG		 1196 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1197 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1198 return -EOPNOTSUPP;
1199 }
bf07aa73
PB		 1200
1201 if (attr->chain > max_chain) {
1202 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
5a7e5bcb 1203 return -EOPNOTSUPP;
bf07aa73
PB		 1204 }
1205
1206 if (attr->prio > max_prio) {
1207 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
5a7e5bcb 1208 return -EOPNOTSUPP;
bf07aa73 1209 }
e52c2802 1210
f493f155 1211 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1212 int mirred_ifindex;
1213
f493f155
EB		 1214 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1215 continue;
1216
7040632d 1217 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1218 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1219 mirred_ifindex);
733d4f36 1220 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1221 extack, &encap_dev, &encap_valid);
1222 if (err)
5a7e5bcb 1223 return err;
0ad060ee 1224
3c37745e
OG		 1225 out_priv = netdev_priv(encap_dev);
1226 rpriv = out_priv->ppriv;
1cc26d74
EB		 1227 attr->dests[out_index].rep = rpriv->rep;
1228 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1229 }
1230
8b32580d 1231 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1232 if (err)
5a7e5bcb 1233 return err;
adb4c123 1234
d7e75a32 1235 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1236 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1237 kfree(parse_attr->mod_hdr_actions);
c83954ab 1238 if (err)
5a7e5bcb 1239 return err;
d7e75a32
OG		 1240 }
1241
b8aee822 1242 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1243 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1244 if (IS_ERR(counter))
1245 return PTR_ERR(counter);
b8aee822
MB		 1246
1247 attr->counter = counter;
1248 }
1249
0ad060ee
RD		 1250 /* we get here if one of the following takes place:
1251 * (1) there's no error
1252 * (2) there's an encap action and we don't have valid neigh
3c37745e 1253 */
0ad060ee 1254 if (!encap_valid) {
5dbe906f
PB		 1255 /* continue with goto slow path rule instead */
1256 struct mlx5_esw_flow_attr slow_attr;
1257
1258 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1259 } else {
6d2a3ed0 1260 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1261 }
c83954ab 1262
5a7e5bcb
VB		 1263 if (IS_ERR(flow->rule[0]))
1264 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1265 else
1266 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1267
1268 return 0;
aa0cbbae 1269}
d85cdccb 1270
9272e3df
YK		 1271static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1272{
1273 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1274 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1275 spec->match_value,
1276 misc_parameters_3);
1277 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1278 headers_v,
1279 geneve_tlv_option_0_data);
1280
1281 return !!geneve_tlv_opt_0_data;
1282}
1283
d85cdccb
OG		 1284static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1285 struct mlx5e_tc_flow *flow)
1286{
1287 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1288 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1289 struct mlx5_esw_flow_attr slow_attr;
f493f155 1290 int out_index;
d85cdccb 1291
226f2ca3 1292 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1293 remove_unready_flow(flow);
ef06c9ee
RD		 1294 kvfree(attr->parse_attr);
1295 return;
1296 }
1297
226f2ca3
VB		 1298 if (mlx5e_is_offloaded_flow(flow)) {
1299 if (flow_flag_test(flow, SLOW))
5dbe906f
PB		 1300 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1301 else
1302 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1303 }
d85cdccb 1304
9272e3df
YK		 1305 if (mlx5_flow_has_geneve_opt(flow))
1306 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1307
513f8f7f 1308 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1309
f493f155 1310 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1311 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1312 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1313 kfree(attr->parse_attr->tun_info[out_index]);
1314 }
f493f155 1315 kvfree(attr->parse_attr);
d7e75a32 1316
513f8f7f 1317 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1318 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1319
1320 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1321 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1322}
1323
232c0013 1324void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1325 struct mlx5e_encap_entry *e,
1326 struct list_head *flow_list)
232c0013 1327{
3c37745e 1328 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1329 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1330 struct mlx5_flow_handle *rule;
1331 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1332 struct mlx5e_tc_flow *flow;
1333 int err;
1334
2b688ea5
MG		 1335 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1336 e->reformat_type,
1337 e->encap_size, e->encap_header,
1338 MLX5_FLOW_NAMESPACE_FDB);
1339 if (IS_ERR(e->pkt_reformat)) {
1340 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1341 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1342 return;
1343 }
1344 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1345 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1346
2a1f1768 1347 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1348 bool all_flow_encaps_valid = true;
1349 int i;
1350
95435ad7
VB		 1351 if (!mlx5e_is_offloaded_flow(flow))
1352 continue;
3c37745e 1353 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1354 spec = &esw_attr->parse_attr->spec;
1355
2b688ea5 1356 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1357 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1358 /* Flow can be associated with multiple encap entries.
1359 * Before offloading the flow verify that all of them have
1360 * a valid neighbour.
1361 */
1362 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1363 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1364 continue;
1365 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1366 all_flow_encaps_valid = false;
1367 break;
1368 }
1369 }
1370 /* Do not offload flows with unresolved neighbors */
1371 if (!all_flow_encaps_valid)
2a1f1768 1372 continue;
5dbe906f 1373 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1374 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1375 if (IS_ERR(rule)) {
1376 err = PTR_ERR(rule);
232c0013
HHZ		 1377 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1378 err);
2a1f1768 1379 continue;
232c0013 1380 }
5dbe906f
PB		 1381
1382 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
6d2a3ed0 1383 flow->rule[0] = rule;
226f2ca3
VB		 1384 /* was unset when slow path rule removed */
1385 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1386 }
1387}
1388
1389void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1390 struct mlx5e_encap_entry *e,
1391 struct list_head *flow_list)
232c0013 1392{
3c37745e 1393 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1394 struct mlx5_esw_flow_attr slow_attr;
1395 struct mlx5_flow_handle *rule;
1396 struct mlx5_flow_spec *spec;
232c0013 1397 struct mlx5e_tc_flow *flow;
5dbe906f 1398 int err;
232c0013 1399
2a1f1768 1400 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1401 if (!mlx5e_is_offloaded_flow(flow))
1402 continue;
5dbe906f
PB		 1403 spec = &flow->esw_attr->parse_attr->spec;
1404
1405 /* update from encap rule to slow path rule */
1406 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b 1407 /* mark the flow's encap dest as non-valid */
2a1f1768 1408 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1409
1410 if (IS_ERR(rule)) {
1411 err = PTR_ERR(rule);
1412 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1413 err);
2a1f1768 1414 continue;
5dbe906f
PB		 1415 }
1416
1417 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1418 flow->rule[0] = rule;
226f2ca3
VB		 1419 /* was unset when fast path rule removed */
1420 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1421 }
1422
61c806da
OG		 1423 /* we know that the encap is valid */
1424 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1425 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1426}
1427
b8aee822
MB		 1428static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1429{
226f2ca3 1430 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1431 return flow->esw_attr->counter;
1432 else
1433 return flow->nic_attr->counter;
1434}
1435
2a1f1768
VB		 1436/* Takes reference to all flows attached to encap and adds the flows to
1437 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1438 */
1439void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1440{
1441 struct encap_flow_item *efi;
1442 struct mlx5e_tc_flow *flow;
1443
1444 list_for_each_entry(efi, &e->flows, list) {
1445 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1446 if (IS_ERR(mlx5e_flow_get(flow)))
1447 continue;
95435ad7 1448 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1449
1450 flow->tmp_efi_index = efi->index;
1451 list_add(&flow->tmp_list, flow_list);
1452 }
1453}
1454
6a06c2f7 1455/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1456void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1457{
1458 struct mlx5e_tc_flow *flow, *tmp;
1459
1460 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1461 mlx5e_flow_put(priv, flow);
1462}
1463
ac0d9176
VB		 1464static struct mlx5e_encap_entry *
1465mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1466 struct mlx5e_encap_entry *e)
1467{
1468 struct mlx5e_encap_entry *next = NULL;
1469
1470retry:
1471 rcu_read_lock();
1472
1473 /* find encap with non-zero reference counter value */
1474 for (next = e ?
1475 list_next_or_null_rcu(&nhe->encap_list,
1476 &e->encap_list,
1477 struct mlx5e_encap_entry,
1478 encap_list) :
1479 list_first_or_null_rcu(&nhe->encap_list,
1480 struct mlx5e_encap_entry,
1481 encap_list);
1482 next;
1483 next = list_next_or_null_rcu(&nhe->encap_list,
1484 &next->encap_list,
1485 struct mlx5e_encap_entry,
1486 encap_list))
1487 if (mlx5e_encap_take(next))
1488 break;
1489
1490 rcu_read_unlock();
1491
1492 /* release starting encap */
1493 if (e)
1494 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1495 if (!next)
1496 return next;
1497
1498 /* wait for encap to be fully initialized */
1499 wait_for_completion(&next->res_ready);
1500 /* continue searching if encap entry is not in valid state after completion */
1501 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1502 e = next;
1503 goto retry;
1504 }
1505
1506 return next;
1507}
1508
f6dfb4c3
HHZ		 1509void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1510{
1511 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1512 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1513 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1514 struct mlx5_fc *counter;
1515 struct neigh_table *tbl;
1516 bool neigh_used = false;
1517 struct neighbour *n;
90bb7692 1518 u64 lastuse;
f6dfb4c3
HHZ		 1519
1520 if (m_neigh->family == AF_INET)
1521 tbl = &arp_tbl;
1522#if IS_ENABLED(CONFIG_IPV6)
1523 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1524 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1525#endif
1526 else
1527 return;
1528
ac0d9176
VB		 1529 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1530 * next one.
1531 */
1532 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1533 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1534 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1535 struct mlx5_eswitch *esw;
1536 LIST_HEAD(flow_list);
948993f2 1537
6a06c2f7
VB		 1538 esw = priv->mdev->priv.eswitch;
1539 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1540 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1541 flow = container_of(efi, struct mlx5e_tc_flow,
1542 encaps[efi->index]);
5a7e5bcb
VB		 1543 if (IS_ERR(mlx5e_flow_get(flow)))
1544 continue;
6a06c2f7 1545 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1546
226f2ca3 1547 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1548 counter = mlx5e_tc_get_counter(flow);
90bb7692 1549 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1550 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1551 neigh_used = true;
1552 break;
1553 }
1554 }
1555 }
6a06c2f7 1556 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1557
6a06c2f7 1558 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1559 if (neigh_used) {
1560 /* release current encap before breaking the loop */
6a06c2f7 1561 mlx5e_encap_put(priv, e);
e36d4810 1562 break;
ac0d9176 1563 }
f6dfb4c3
HHZ		 1564 }
1565
c786fe59
VB		 1566 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1567
f6dfb4c3
HHZ		 1568 if (neigh_used) {
1569 nhe->reported_lastuse = jiffies;
1570
1571 /* find the relevant neigh according to the cached device and
1572 * dst ip pair
1573 */
1574 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1575 if (!n)
f6dfb4c3 1576 return;
f6dfb4c3
HHZ		 1577
1578 neigh_event_send(n, NULL);
1579 neigh_release(n);
1580 }
1581}
1582
61086f39 1583static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1584{
948993f2 1585 WARN_ON(!list_empty(&e->flows));
948993f2 1586
3c140dd5
VB		 1587 if (e->compl_result > 0) {
1588 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1589
1590 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1591 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1592 }
948993f2 1593
2a4b6526 1594 kfree(e->tun_info);
948993f2 1595 kfree(e->encap_header);
ac0d9176 1596 kfree_rcu(e, rcu);
948993f2
VB		 1597}
1598
61086f39
VB		 1599void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1600{
1601 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1602
1603 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1604 return;
1605 hash_del_rcu(&e->encap_hlist);
1606 mutex_unlock(&esw->offloads.encap_tbl_lock);
1607
1608 mlx5e_encap_dealloc(priv, e);
1609}
1610
d85cdccb 1611static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1612 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1613{
61086f39
VB		 1614 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1615 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1616
5a7e5bcb 1617 /* flow wasn't fully initialized */
61086f39 1618 if (!e)
5a7e5bcb
VB		 1619 return;
1620
61086f39 1621 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1622 list_del(&flow->encaps[out_index].list);
948993f2 1623 flow->encaps[out_index].e = NULL;
61086f39
VB		 1624 if (!refcount_dec_and_test(&e->refcnt)) {
1625 mutex_unlock(&esw->offloads.encap_tbl_lock);
1626 return;
1627 }
1628 hash_del_rcu(&e->encap_hlist);
1629 mutex_unlock(&esw->offloads.encap_tbl_lock);
1630
1631 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1632}
1633
04de7dda
RD		 1634static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1635{
1636 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1637
226f2ca3
VB		 1638 if (!flow_flag_test(flow, ESWITCH) ||
1639 !flow_flag_test(flow, DUP))
04de7dda
RD		 1640 return;
1641
1642 mutex_lock(&esw->offloads.peer_mutex);
1643 list_del(&flow->peer);
1644 mutex_unlock(&esw->offloads.peer_mutex);
1645
226f2ca3 1646 flow_flag_clear(flow, DUP);
04de7dda 1647
ab869cc1
RD		 1648 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1649 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1650 kfree(flow->peer_flow);
1651 }
1652
04de7dda
RD		 1653 flow->peer_flow = NULL;
1654}
1655
1656static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1657{
1658 struct mlx5_core_dev *dev = flow->priv->mdev;
1659 struct mlx5_devcom *devcom = dev->priv.devcom;
1660 struct mlx5_eswitch *peer_esw;
1661
1662 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1663 if (!peer_esw)
1664 return;
1665
1666 __mlx5e_tc_del_fdb_peer_flow(flow);
1667 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1668}
1669
e8f887ac 1670static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1671 struct mlx5e_tc_flow *flow)
e8f887ac 1672{
226f2ca3 1673 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1674 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1675 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1676 } else {
d85cdccb 1677 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1678 }
e8f887ac
AV		 1679}
1680
bbd00f7e
HHZ		 1681
1682static int parse_tunnel_attr(struct mlx5e_priv *priv,
1683 struct mlx5_flow_spec *spec,
f9e30088 1684 struct flow_cls_offload *f,
6363651d 1685 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1686{
e98bedf5 1687 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1688 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1689 outer_headers);
1690 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1691 outer_headers);
f9e30088 1692 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1693 int err;
2e72eb43 1694
101f4de9 1695 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1696 headers_c, headers_v, match_level);
54c177ca
OS		 1697 if (err) {
1698 NL_SET_ERR_MSG_MOD(extack,
1699 "failed to parse tunnel attributes");
101f4de9 1700 return err;
bbd00f7e
HHZ		 1701 }
1702
fe1587a7
DL		 1703 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1704 struct flow_match_control match;
1705 u16 addr_type;
1706
1707 flow_rule_match_enc_control(rule, &match);
1708 addr_type = match.key->addr_type;
1709
1710 /* For tunnel addr_type used same key id`s as for non-tunnel */
1711 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1712 struct flow_match_ipv4_addrs match;
1713
1714 flow_rule_match_enc_ipv4_addrs(rule, &match);
1715 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1716 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1717 ntohl(match.mask->src));
1718 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1719 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1720 ntohl(match.key->src));
1721
1722 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1723 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1724 ntohl(match.mask->dst));
1725 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1726 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1727 ntohl(match.key->dst));
1728
1729 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1730 ethertype);
1731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1732 ETH_P_IP);
1733 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1734 struct flow_match_ipv6_addrs match;
1735
1736 flow_rule_match_enc_ipv6_addrs(rule, &match);
1737 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1738 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1739 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1740 ipv6));
1741 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1742 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1743 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1744 ipv6));
1745
1746 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1747 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1748 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1749 ipv6));
1750 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1751 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1752 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1753 ipv6));
1754
1755 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1756 ethertype);
1757 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1758 ETH_P_IPV6);
1759 }
2e72eb43 1760 }
bbd00f7e 1761
8f256622
PNA		 1762 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1763 struct flow_match_ip match;
bcef735c 1764
8f256622
PNA		 1765 flow_rule_match_enc_ip(rule, &match);
1766 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1767 match.mask->tos & 0x3);
1768 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1769 match.key->tos & 0x3);
bcef735c 1770
8f256622
PNA		 1771 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1772 match.mask->tos >> 2);
1773 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1774 match.key->tos >> 2);
bcef735c 1775
8f256622
PNA		 1776 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1777 match.mask->ttl);
1778 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1779 match.key->ttl);
e98bedf5 1780
8f256622 1781 if (match.mask->ttl &&
e98bedf5
EB		 1782 !MLX5_CAP_ESW_FLOWTABLE_FDB
1783 (priv->mdev,
1784 ft_field_support.outer_ipv4_ttl)) {
1785 NL_SET_ERR_MSG_MOD(extack,
1786 "Matching on TTL is not supported");
1787 return -EOPNOTSUPP;
1788 }
1789
bcef735c
OG		 1790 }
1791
bbd00f7e
HHZ		 1792 /* Enforce DMAC when offloading incoming tunneled flows.
1793 * Flow counters require a match on the DMAC.
1794 */
1795 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1796 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1797 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1798 dmac_47_16), priv->netdev->dev_addr);
1799
1800 /* let software handle IP fragments */
1801 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1802 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1803
1804 return 0;
1805}
1806
8377629e
EB		 1807static void *get_match_headers_criteria(u32 flags,
1808 struct mlx5_flow_spec *spec)
1809{
1810 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1811 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1812 inner_headers) :
1813 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1814 outer_headers);
1815}
1816
1817static void *get_match_headers_value(u32 flags,
1818 struct mlx5_flow_spec *spec)
1819{
1820 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1821 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1822 inner_headers) :
1823 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1824 outer_headers);
1825}
1826
de0af0bf
RD		 1827static int __parse_cls_flower(struct mlx5e_priv *priv,
1828 struct mlx5_flow_spec *spec,
f9e30088 1829 struct flow_cls_offload *f,
54c177ca 1830 struct net_device *filter_dev,
93b3586e 1831 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 1832{
e98bedf5 1833 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1834 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1835 outer_headers);
1836 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1837 outer_headers);
699e96dd
JL		 1838 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1839 misc_parameters);
1840 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1841 misc_parameters);
f9e30088 1842 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1843 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1844 u16 addr_type = 0;
1845 u8 ip_proto = 0;
93b3586e 1846 u8 *match_level;
e3a2b7ed 1847
93b3586e 1848 match_level = outer_match_level;
de0af0bf 1849
8f256622 1850 if (dissector->used_keys &
3d144578
VB		 1851 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1852 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1853 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1854 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1855 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1856 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1857 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1858 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1859 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1860 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1861 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1862 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1863 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1864 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1865 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1866 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1867 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1868 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1869 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
952c54df
MD		 1870 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
1871 dissector->used_keys);
e3a2b7ed
AV		 1872 return -EOPNOTSUPP;
1873 }
1874
075973c7 1875 if (mlx5e_get_tc_tun(filter_dev)) {
93b3586e
HN		 1876 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1877 outer_match_level))
bbd00f7e 1878 return -EOPNOTSUPP;
bbd00f7e 1879
93b3586e 1880 /* At this point, header pointers should point to the inner
bbd00f7e
HHZ		 1881 * headers, outer header were already set by parse_tunnel_attr
1882 */
93b3586e 1883 match_level = inner_match_level;
8377629e
EB		 1884 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1885 spec);
1886 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1887 spec);
bbd00f7e
HHZ		 1888 }
1889
8f256622
PNA		 1890 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1891 struct flow_match_basic match;
1892
1893 flow_rule_match_basic(rule, &match);
d3a80bb5 1894 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1895 ntohs(match.mask->n_proto));
d3a80bb5 1896 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1897 ntohs(match.key->n_proto));
e3a2b7ed 1898
8f256622 1899 if (match.mask->n_proto)
d708f902 1900 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1901 }
35a605db
EB		 1902 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1903 is_vlan_dev(filter_dev)) {
1904 struct flow_dissector_key_vlan filter_dev_mask;
1905 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1906 struct flow_match_vlan match;
1907
35a605db
EB		 1908 if (is_vlan_dev(filter_dev)) {
1909 match.key = &filter_dev_key;
1910 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1911 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1912 match.key->vlan_priority = 0;
1913 match.mask = &filter_dev_mask;
1914 memset(match.mask, 0xff, sizeof(*match.mask));
1915 match.mask->vlan_priority = 0;
1916 } else {
1917 flow_rule_match_vlan(rule, &match);
1918 }
8f256622
PNA		 1919 if (match.mask->vlan_id ||
1920 match.mask->vlan_priority ||
1921 match.mask->vlan_tpid) {
1922 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1923 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1924 svlan_tag, 1);
1925 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1926 svlan_tag, 1);
1927 } else {
1928 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1929 cvlan_tag, 1);
1930 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1931 cvlan_tag, 1);
1932 }
095b6cfd 1933
8f256622
PNA		 1934 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1935 match.mask->vlan_id);
1936 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1937 match.key->vlan_id);
358d79a4 1938
8f256622
PNA		 1939 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1940 match.mask->vlan_priority);
1941 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1942 match.key->vlan_priority);
54782900 1943
d708f902 1944 *match_level = MLX5_MATCH_L2;
54782900 1945 }
d3a80bb5 1946 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 1947 /* cvlan_tag enabled in match criteria and
1948 * disabled in match value means both S & C tags
1949 * don't exist (untagged of both)
1950 */
cee26487 1951 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1952 *match_level = MLX5_MATCH_L2;
54782900
OG		 1953 }
1954
8f256622
PNA		 1955 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1956 struct flow_match_vlan match;
1957
12d5cbf8 1958 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1959 if (match.mask->vlan_id ||
1960 match.mask->vlan_priority ||
1961 match.mask->vlan_tpid) {
1962 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1963 MLX5_SET(fte_match_set_misc, misc_c,
1964 outer_second_svlan_tag, 1);
1965 MLX5_SET(fte_match_set_misc, misc_v,
1966 outer_second_svlan_tag, 1);
1967 } else {
1968 MLX5_SET(fte_match_set_misc, misc_c,
1969 outer_second_cvlan_tag, 1);
1970 MLX5_SET(fte_match_set_misc, misc_v,
1971 outer_second_cvlan_tag, 1);
1972 }
1973
1974 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1975 match.mask->vlan_id);
699e96dd 1976 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1977 match.key->vlan_id);
699e96dd 1978 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1979 match.mask->vlan_priority);
699e96dd 1980 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1981 match.key->vlan_priority);
699e96dd
JL		 1982
1983 *match_level = MLX5_MATCH_L2;
1984 }
1985 }
1986
8f256622
PNA		 1987 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1988 struct flow_match_eth_addrs match;
54782900 1989
8f256622 1990 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1991 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1992 dmac_47_16),
8f256622 1993 match.mask->dst);
d3a80bb5
OG		 1994 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1995 dmac_47_16),
8f256622 1996 match.key->dst);
d3a80bb5
OG		 1997
1998 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1999 smac_47_16),
8f256622 2000 match.mask->src);
d3a80bb5
OG		 2001 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2002 smac_47_16),
8f256622 2003 match.key->src);
d3a80bb5 2004
8f256622
PNA		 2005 if (!is_zero_ether_addr(match.mask->src) ||
2006 !is_zero_ether_addr(match.mask->dst))
d708f902 2007 *match_level = MLX5_MATCH_L2;
54782900
OG		 2008 }
2009
8f256622
PNA		 2010 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2011 struct flow_match_control match;
54782900 2012
8f256622
PNA		 2013 flow_rule_match_control(rule, &match);
2014 addr_type = match.key->addr_type;
54782900
OG		 2015
2016 /* the HW doesn't support frag first/later */
8f256622 2017 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2018 return -EOPNOTSUPP;
2019
8f256622 2020 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2021 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2022 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2023 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2024
2025 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2026 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2027 *match_level = MLX5_MATCH_L2;
54782900
OG		 2028 /* *** L2 attributes parsing up to here *** */
2029 else
83621b7d 2030 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2031 }
2032 }
2033
8f256622
PNA		 2034 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2035 struct flow_match_basic match;
2036
2037 flow_rule_match_basic(rule, &match);
2038 ip_proto = match.key->ip_proto;
54782900
OG		 2039
2040 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2041 match.mask->ip_proto);
54782900 2042 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2043 match.key->ip_proto);
54782900 2044
8f256622 2045 if (match.mask->ip_proto)
d708f902 2046 *match_level = MLX5_MATCH_L3;
54782900
OG		 2047 }
2048
e3a2b7ed 2049 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2050 struct flow_match_ipv4_addrs match;
e3a2b7ed 2051
8f256622 2052 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2053 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2054 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2055 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2056 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2057 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2058 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2059 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2060 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2061 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2062 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2063 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2064 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2065
8f256622 2066 if (match.mask->src || match.mask->dst)
d708f902 2067 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2068 }
2069
2070 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2071 struct flow_match_ipv6_addrs match;
e3a2b7ed 2072
8f256622 2073 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2074 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2075 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2076 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2077 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2078 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2079 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2080
2081 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2082 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2083 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2084 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2085 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2086 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2087
8f256622
PNA		 2088 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2089 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2090 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2091 }
2092
8f256622
PNA		 2093 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2094 struct flow_match_ip match;
1f97a526 2095
8f256622
PNA		 2096 flow_rule_match_ip(rule, &match);
2097 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2098 match.mask->tos & 0x3);
2099 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2100 match.key->tos & 0x3);
1f97a526 2101
8f256622
PNA		 2102 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2103 match.mask->tos >> 2);
2104 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2105 match.key->tos >> 2);
1f97a526 2106
8f256622
PNA		 2107 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2108 match.mask->ttl);
2109 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2110 match.key->ttl);
1f97a526 2111
8f256622 2112 if (match.mask->ttl &&
a8ade55f 2113 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2114 ft_field_support.outer_ipv4_ttl)) {
2115 NL_SET_ERR_MSG_MOD(extack,
2116 "Matching on TTL is not supported");
1f97a526 2117 return -EOPNOTSUPP;
e98bedf5 2118 }
a8ade55f 2119
8f256622 2120 if (match.mask->tos || match.mask->ttl)
d708f902 2121 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2122 }
2123
54782900
OG		 2124 /* *** L3 attributes parsing up to here *** */
2125
8f256622
PNA		 2126 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2127 struct flow_match_ports match;
2128
2129 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2130 switch (ip_proto) {
2131 case IPPROTO_TCP:
2132 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2133 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2134 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2135 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2136
2137 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2138 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2139 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2140 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2141 break;
2142
2143 case IPPROTO_UDP:
2144 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2145 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2146 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2147 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2148
2149 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2150 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2151 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2152 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2153 break;
2154 default:
e98bedf5
EB		 2155 NL_SET_ERR_MSG_MOD(extack,
2156 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2157 netdev_err(priv->netdev,
2158 "Only UDP and TCP transport are supported\n");
2159 return -EINVAL;
2160 }
de0af0bf 2161
8f256622 2162 if (match.mask->src || match.mask->dst)
d708f902 2163 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2164 }
2165
8f256622
PNA		 2166 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2167 struct flow_match_tcp match;
e77834ec 2168
8f256622 2169 flow_rule_match_tcp(rule, &match);
e77834ec 2170 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2171 ntohs(match.mask->flags));
e77834ec 2172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2173 ntohs(match.key->flags));
e77834ec 2174
8f256622 2175 if (match.mask->flags)
d708f902 2176 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2177 }
2178
e3a2b7ed
AV		 2179 return 0;
2180}
2181
de0af0bf 2182static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2183 struct mlx5e_tc_flow *flow,
de0af0bf 2184 struct mlx5_flow_spec *spec,
f9e30088 2185 struct flow_cls_offload *f,
54c177ca 2186 struct net_device *filter_dev)
de0af0bf 2187{
93b3586e 2188 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2189 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2190 struct mlx5_core_dev *dev = priv->mdev;
2191 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2192 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2193 struct mlx5_eswitch_rep *rep;
226f2ca3 2194 bool is_eswitch_flow;
de0af0bf
RD		 2195 int err;
2196
93b3586e
HN		 2197 inner_match_level = MLX5_MATCH_NONE;
2198 outer_match_level = MLX5_MATCH_NONE;
2199
2200 err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2201 &outer_match_level);
2202 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2203 outer_match_level : inner_match_level;
de0af0bf 2204
226f2ca3
VB		 2205 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2206 if (!err && is_eswitch_flow) {
1d447a39 2207 rep = rpriv->rep;
b05af6aa 2208 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2209 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2210 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2211 NL_SET_ERR_MSG_MOD(extack,
2212 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2213 netdev_warn(priv->netdev,
2214 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2215 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2216 return -EOPNOTSUPP;
2217 }
2218 }
2219
226f2ca3 2220 if (is_eswitch_flow) {
93b3586e
HN		 2221 flow->esw_attr->inner_match_level = inner_match_level;
2222 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2223 } else {
93b3586e 2224 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2225 }
38aa51c1 2226
de0af0bf
RD		 2227 return err;
2228}
2229
d79b6df6
OG		 2230struct pedit_headers {
2231 struct ethhdr eth;
0eb69bb9 2232 struct vlan_hdr vlan;
d79b6df6
OG		 2233 struct iphdr ip4;
2234 struct ipv6hdr ip6;
2235 struct tcphdr tcp;
2236 struct udphdr udp;
2237};
2238
c500c86b
PNA		 2239struct pedit_headers_action {
2240 struct pedit_headers vals;
2241 struct pedit_headers masks;
2242 u32 pedits;
2243};
2244
d79b6df6 2245static int pedit_header_offsets[] = {
73867881
PNA		 2246 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2247 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2248 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2249 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2250 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2251};
2252
2253#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2254
2255static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2256 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2257{
2258 u32 *curr_pmask, *curr_pval;
2259
c500c86b
PNA		 2260 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2261 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2262
2263 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2264 goto out_err;
2265
2266 *curr_pmask |= mask;
2267 *curr_pval |= (val & mask);
2268
2269 return 0;
2270
2271out_err:
2272 return -EOPNOTSUPP;
2273}
2274
2275struct mlx5_fields {
2276 u8 field;
2277 u8 size;
2278 u32 offset;
27c11b6b 2279 u32 match_offset;
d79b6df6
OG		 2280};
2281
27c11b6b
EB		 2282#define OFFLOAD(fw_field, size, field, off, match_field) \
2283 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2284 offsetof(struct pedit_headers, field) + (off), \
2285 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2286
2ef86872
EB		 2287/* masked values are the same and there are no rewrites that do not have a
2288 * match.
2289 */
2290#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2291 type matchmaskx = *(type *)(matchmaskp); \
2292 type matchvalx = *(type *)(matchvalp); \
2293 type maskx = *(type *)(maskp); \
2294 type valx = *(type *)(valp); \
2295 \
2296 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2297 matchmaskx)); \
2298})
2299
27c11b6b
EB		 2300static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2301 void *matchmaskp, int size)
2302{
2303 bool same = false;
2304
2305 switch (size) {
2306 case sizeof(u8):
2ef86872 2307 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2308 break;
2309 case sizeof(u16):
2ef86872 2310 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2311 break;
2312 case sizeof(u32):
2ef86872 2313 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2314 break;
2315 }
2316
2317 return same;
2318}
a8e4f0c4 2319
d79b6df6 2320static struct mlx5_fields fields[] = {
27c11b6b
EB		 2321 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2322 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
2323 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2324 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
2325 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
2326 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
2327
2328 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
2329 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2330 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2331
2332 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2333 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2334 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
2335 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2336 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
2337 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2338 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
2339 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2340 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2341 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2342 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
2343 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2344 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
2345 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2346 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
2347 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2348 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2349
2350 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
2351 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
2352 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2353
2354 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2355 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
d79b6df6
OG		 2356};
2357
218d05ce
TZ		 2358/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2359 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2360 * says how many HW actions were actually parsed.
d79b6df6 2361 */
c500c86b 2362static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2363 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2364 u32 *action_flags,
e98bedf5 2365 struct netlink_ext_ack *extack)
d79b6df6
OG		 2366{
2367 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
27c11b6b
EB		 2368 void *headers_c = get_match_headers_criteria(*action_flags,
2369 &parse_attr->spec);
2370 void *headers_v = get_match_headers_value(*action_flags,
2371 &parse_attr->spec);
2b64beba 2372 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 2373 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 2374 struct mlx5_fields *f;
2375 u8 cmd, field_bsize;
e3ca4e05 2376 u32 s_mask, a_mask;
d79b6df6 2377 unsigned long mask;
2b64beba
OG		 2378 __be32 mask_be32;
2379 __be16 mask_be16;
d79b6df6
OG		 2380 void *action;
2381
73867881
PNA		 2382 set_masks = &hdrs[0].masks;
2383 add_masks = &hdrs[1].masks;
2384 set_vals = &hdrs[0].vals;
2385 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2386
2387 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2388 action = parse_attr->mod_hdr_actions +
2389 parse_attr->num_mod_hdr_actions * action_size;
2390
2391 max_actions = parse_attr->max_mod_hdr_actions;
2392 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2393
2394 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2395 bool skip;
2396
d79b6df6
OG		 2397 f = &fields[i];
2398 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2399 s_mask = 0;
2400 a_mask = 0;
d79b6df6
OG		 2401
2402 s_masks_p = (void *)set_masks + f->offset;
2403 a_masks_p = (void *)add_masks + f->offset;
2404
2405 memcpy(&s_mask, s_masks_p, f->size);
2406 memcpy(&a_mask, a_masks_p, f->size);
2407
2408 if (!s_mask && !a_mask) /* nothing to offload here */
2409 continue;
2410
2411 if (s_mask && a_mask) {
e98bedf5
EB		 2412 NL_SET_ERR_MSG_MOD(extack,
2413 "can't set and add to the same HW field");
d79b6df6
OG		 2414 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2415 return -EOPNOTSUPP;
2416 }
2417
2418 if (nactions == max_actions) {
e98bedf5
EB		 2419 NL_SET_ERR_MSG_MOD(extack,
2420 "too many pedit actions, can't offload");
d79b6df6
OG		 2421 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2422 return -EOPNOTSUPP;
2423 }
2424
27c11b6b 2425 skip = false;
d79b6df6 2426 if (s_mask) {
27c11b6b
EB		 2427 void *match_mask = headers_c + f->match_offset;
2428 void *match_val = headers_v + f->match_offset;
2429
d79b6df6
OG		 2430 cmd = MLX5_ACTION_TYPE_SET;
2431 mask = s_mask;
2432 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2433 /* don't rewrite if we have a match on the same value */
2434 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2435 match_mask, f->size))
2436 skip = true;
d79b6df6
OG		 2437 /* clear to denote we consumed this field */
2438 memset(s_masks_p, 0, f->size);
2439 } else {
27c11b6b
EB		 2440 u32 zero = 0;
2441
d79b6df6
OG		 2442 cmd = MLX5_ACTION_TYPE_ADD;
2443 mask = a_mask;
2444 vals_p = (void *)add_vals + f->offset;
27c11b6b
EB		 2445 /* add 0 is no change */
2446 if (!memcmp(vals_p, &zero, f->size))
2447 skip = true;
d79b6df6
OG		 2448 /* clear to denote we consumed this field */
2449 memset(a_masks_p, 0, f->size);
2450 }
27c11b6b
EB		 2451 if (skip)
2452 continue;
d79b6df6 2453
d79b6df6 2454 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2455
2b64beba 2456 if (field_bsize == 32) {
b917e37e 2457 mask_be32 = (__be32)mask;
2b64beba
OG		 2458 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2459 } else if (field_bsize == 16) {
b917e37e
SH		 2460 mask_be32 = (__be32)mask;
2461 mask_be16 = *(__be16 *)&mask_be32;
2b64beba
OG		 2462 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2463 }
2464
d79b6df6 2465 first = find_first_bit(&mask, field_bsize);
2b64beba 2466 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2467 last = find_last_bit(&mask, field_bsize);
2b64beba 2468 if (first < next_z && next_z < last) {
e98bedf5
EB		 2469 NL_SET_ERR_MSG_MOD(extack,
2470 "rewrite of few sub-fields isn't supported");
2b64beba 2471 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2472 mask);
2473 return -EOPNOTSUPP;
2474 }
2475
2476 MLX5_SET(set_action_in, action, action_type, cmd);
2477 MLX5_SET(set_action_in, action, field, f->field);
2478
2479 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2480 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2481 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2482 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2483 }
2484
2485 if (field_bsize == 32)
2b64beba 2486 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2487 else if (field_bsize == 16)
2b64beba 2488 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2489 else if (field_bsize == 8)
2b64beba 2490 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2491
2492 action += action_size;
2493 nactions++;
2494 }
2495
2496 parse_attr->num_mod_hdr_actions = nactions;
2497 return 0;
2498}
2499
2cc1cb1d
TZ		 2500static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2501 int namespace)
2502{
2503 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2504 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2505 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2506 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2507}
2508
d79b6df6 2509static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2510 struct pedit_headers_action *hdrs,
2511 int namespace,
d79b6df6
OG		 2512 struct mlx5e_tc_flow_parse_attr *parse_attr)
2513{
2514 int nkeys, action_size, max_actions;
2515
c500c86b
PNA		 2516 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2517 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2518 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2519
2cc1cb1d 2520 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2521 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2522 max_actions = min(max_actions, nkeys * 16);
2523
2524 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2525 if (!parse_attr->mod_hdr_actions)
2526 return -ENOMEM;
2527
218d05ce 2528 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2529 return 0;
2530}
2531
2532static const struct pedit_headers zero_masks = {};
2533
2534static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2535 const struct flow_action_entry *act, int namespace,
e98bedf5 2536 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2537 struct pedit_headers_action *hdrs,
e98bedf5 2538 struct netlink_ext_ack *extack)
d79b6df6 2539{
73867881
PNA		 2540 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2541 int err = -EOPNOTSUPP;
d79b6df6 2542 u32 mask, val, offset;
73867881 2543 u8 htype;
d79b6df6 2544
73867881
PNA		 2545 htype = act->mangle.htype;
2546 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2547
73867881
PNA		 2548 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2549 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2550 goto out_err;
2551 }
d79b6df6 2552
2cc1cb1d
TZ		 2553 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2554 NL_SET_ERR_MSG_MOD(extack,
2555 "The pedit offload action is not supported");
2556 goto out_err;
2557 }
2558
73867881
PNA		 2559 mask = act->mangle.mask;
2560 val = act->mangle.val;
2561 offset = act->mangle.offset;
d79b6df6 2562
73867881
PNA		 2563 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2564 if (err)
2565 goto out_err;
c500c86b 2566
73867881 2567 hdrs[cmd].pedits++;
d79b6df6 2568
c500c86b
PNA		 2569 return 0;
2570out_err:
2571 return err;
2572}
2573
2574static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2575 struct mlx5e_tc_flow_parse_attr *parse_attr,
2576 struct pedit_headers_action *hdrs,
27c11b6b 2577 u32 *action_flags,
c500c86b
PNA		 2578 struct netlink_ext_ack *extack)
2579{
2580 struct pedit_headers *cmd_masks;
2581 int err;
2582 u8 cmd;
2583
218d05ce 2584 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2585 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2586 if (err)
2587 goto out_err;
2588 }
d79b6df6 2589
27c11b6b 2590 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2591 if (err < 0)
2592 goto out_dealloc_parsed_actions;
2593
2594 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2595 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2596 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2597 NL_SET_ERR_MSG_MOD(extack,
2598 "attempt to offload an unsupported field");
b3a433de 2599 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2600 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2601 16, 1, cmd_masks, sizeof(zero_masks), true);
2602 err = -EOPNOTSUPP;
2603 goto out_dealloc_parsed_actions;
2604 }
2605 }
2606
2607 return 0;
2608
2609out_dealloc_parsed_actions:
2610 kfree(parse_attr->mod_hdr_actions);
2611out_err:
2612 return err;
2613}
2614
e98bedf5
EB		 2615static bool csum_offload_supported(struct mlx5e_priv *priv,
2616 u32 action,
2617 u32 update_flags,
2618 struct netlink_ext_ack *extack)
26c02749
OG		 2619{
2620 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2621 TCA_CSUM_UPDATE_FLAG_UDP;
2622
2623 /* The HW recalcs checksums only if re-writing headers */
2624 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2625 NL_SET_ERR_MSG_MOD(extack,
2626 "TC csum action is only offloaded with pedit");
26c02749
OG		 2627 netdev_warn(priv->netdev,
2628 "TC csum action is only offloaded with pedit\n");
2629 return false;
2630 }
2631
2632 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2633 NL_SET_ERR_MSG_MOD(extack,
2634 "can't offload TC csum action for some header/s");
26c02749
OG		 2635 netdev_warn(priv->netdev,
2636 "can't offload TC csum action for some header/s - flags %#x\n",
2637 update_flags);
2638 return false;
2639 }
2640
2641 return true;
2642}
2643
8998576b
DL		 2644struct ip_ttl_word {
2645 __u8 ttl;
2646 __u8 protocol;
2647 __sum16 check;
2648};
2649
2650struct ipv6_hoplimit_word {
2651 __be16 payload_len;
2652 __u8 nexthdr;
2653 __u8 hop_limit;
2654};
2655
2656static bool is_action_keys_supported(const struct flow_action_entry *act)
2657{
2658 u32 mask, offset;
2659 u8 htype;
2660
2661 htype = act->mangle.htype;
2662 offset = act->mangle.offset;
2663 mask = ~act->mangle.mask;
2664 /* For IPv4 & IPv6 header check 4 byte word,
2665 * to determine that modified fields
2666 * are NOT ttl & hop_limit only.
2667 */
2668 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2669 struct ip_ttl_word *ttl_word =
2670 (struct ip_ttl_word *)&mask;
2671
2672 if (offset != offsetof(struct iphdr, ttl) ||
2673 ttl_word->protocol ||
2674 ttl_word->check) {
2675 return true;
2676 }
2677 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2678 struct ipv6_hoplimit_word *hoplimit_word =
2679 (struct ipv6_hoplimit_word *)&mask;
2680
2681 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2682 hoplimit_word->payload_len ||
2683 hoplimit_word->nexthdr) {
2684 return true;
2685 }
2686 }
2687 return false;
2688}
2689
bdd66ac0 2690static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2691 struct flow_action *flow_action,
1651925d 2692 u32 actions,
e98bedf5 2693 struct netlink_ext_ack *extack)
bdd66ac0 2694{
73867881 2695 const struct flow_action_entry *act;
bdd66ac0 2696 bool modify_ip_header;
bdd66ac0
OG		 2697 void *headers_v;
2698 u16 ethertype;
8998576b 2699 u8 ip_proto;
73867881 2700 int i;
bdd66ac0 2701
8377629e 2702 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2703 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2704
2705 /* for non-IP we only re-write MACs, so we're okay */
2706 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2707 goto out_ok;
2708
2709 modify_ip_header = false;
73867881
PNA		 2710 flow_action_for_each(i, act, flow_action) {
2711 if (act->id != FLOW_ACTION_MANGLE &&
2712 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2713 continue;
2714
8998576b 2715 if (is_action_keys_supported(act)) {
73867881
PNA		 2716 modify_ip_header = true;
2717 break;
bdd66ac0
OG		 2718 }
2719 }
2720
2721 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2722 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2723 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2724 NL_SET_ERR_MSG_MOD(extack,
2725 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2726 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2727 return false;
2728 }
2729
2730out_ok:
2731 return true;
2732}
2733
2734static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2735 struct flow_action *flow_action,
bdd66ac0 2736 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2737 struct mlx5e_tc_flow *flow,
2738 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2739{
2740 u32 actions;
2741
226f2ca3 2742 if (mlx5e_is_eswitch_flow(flow))
bdd66ac0
OG		 2743 actions = flow->esw_attr->action;
2744 else
2745 actions = flow->nic_attr->action;
2746
226f2ca3 2747 if (flow_flag_test(flow, EGRESS) &&
35a605db 2748 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
6830b468
TZ		 2749 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2750 (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
7e29392e
RD		 2751 return false;
2752
bdd66ac0 2753 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2754 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2755 flow_action, actions,
e98bedf5 2756 extack);
bdd66ac0
OG		 2757
2758 return true;
2759}
2760
5c65c564
OG		 2761static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2762{
2763 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2764 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2765
2766 fmdev = priv->mdev;
2767 pmdev = peer_priv->mdev;
2768
59c9d35e
AH		 2769 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2770 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2771
816f6706 2772 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2773}
2774
bdc837ee
EB		 2775static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2776 const struct flow_action_entry *act,
2777 struct mlx5e_tc_flow_parse_attr *parse_attr,
2778 struct pedit_headers_action *hdrs,
2779 u32 *action, struct netlink_ext_ack *extack)
2780{
2781 u16 mask16 = VLAN_VID_MASK;
2782 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2783 const struct flow_action_entry pedit_act = {
2784 .id = FLOW_ACTION_MANGLE,
2785 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2786 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2787 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2788 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2789 };
6fca9d1e 2790 u8 match_prio_mask, match_prio_val;
bf2f3bca 2791 void *headers_c, *headers_v;
bdc837ee
EB		 2792 int err;
2793
bf2f3bca
EB		 2794 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2795 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2796
2797 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2798 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2799 NL_SET_ERR_MSG_MOD(extack,
2800 "VLAN rewrite action must have VLAN protocol match");
2801 return -EOPNOTSUPP;
2802 }
2803
6fca9d1e
EB		 2804 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2805 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2806 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2807 NL_SET_ERR_MSG_MOD(extack,
2808 "Changing VLAN prio is not supported");
bdc837ee
EB		 2809 return -EOPNOTSUPP;
2810 }
2811
2812 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2813 hdrs, NULL);
2814 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2815
2816 return err;
2817}
2818
0bac1194
EB		 2819static int
2820add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2821 struct mlx5e_tc_flow_parse_attr *parse_attr,
2822 struct pedit_headers_action *hdrs,
2823 u32 *action, struct netlink_ext_ack *extack)
2824{
2825 const struct flow_action_entry prio_tag_act = {
2826 .vlan.vid = 0,
2827 .vlan.prio =
2828 MLX5_GET(fte_match_set_lyr_2_4,
2829 get_match_headers_value(*action,
2830 &parse_attr->spec),
2831 first_prio) &
2832 MLX5_GET(fte_match_set_lyr_2_4,
2833 get_match_headers_criteria(*action,
2834 &parse_attr->spec),
2835 first_prio),
2836 };
2837
2838 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2839 &prio_tag_act, parse_attr, hdrs, action,
2840 extack);
2841}
2842
73867881
PNA		 2843static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2844 struct flow_action *flow_action,
aa0cbbae 2845 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2846 struct mlx5e_tc_flow *flow,
2847 struct netlink_ext_ack *extack)
e3a2b7ed 2848{
aa0cbbae 2849 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2850 struct pedit_headers_action hdrs[2] = {};
2851 const struct flow_action_entry *act;
1cab1cd7 2852 u32 action = 0;
244cd96a 2853 int err, i;
e3a2b7ed 2854
73867881 2855 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2856 return -EINVAL;
2857
3bc4b7bf 2858 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2859
73867881
PNA		 2860 flow_action_for_each(i, act, flow_action) {
2861 switch (act->id) {
2862 case FLOW_ACTION_DROP:
1cab1cd7 2863 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2864 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2865 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2866 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2867 break;
2868 case FLOW_ACTION_MANGLE:
2869 case FLOW_ACTION_ADD:
2870 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2871 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2872 if (err)
2873 return err;
2874
1cab1cd7
OG		 2875 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2876 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2877 break;
bdc837ee
EB		 2878 case FLOW_ACTION_VLAN_MANGLE:
2879 err = add_vlan_rewrite_action(priv,
2880 MLX5_FLOW_NAMESPACE_KERNEL,
2881 act, parse_attr, hdrs,
2882 &action, extack);
2883 if (err)
2884 return err;
2885
2886 break;
73867881 2887 case FLOW_ACTION_CSUM:
1cab1cd7 2888 if (csum_offload_supported(priv, action,
73867881 2889 act->csum_flags,
e98bedf5 2890 extack))
73867881 2891 break;
26c02749
OG		 2892
2893 return -EOPNOTSUPP;
73867881
PNA		 2894 case FLOW_ACTION_REDIRECT: {
2895 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2896
2897 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2898 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2899 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 2900 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 2901 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2902 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2903 } else {
e98bedf5
EB		 2904 NL_SET_ERR_MSG_MOD(extack,
2905 "device is not on same HW, can't offload");
5c65c564
OG		 2906 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2907 peer_dev->name);
2908 return -EINVAL;
2909 }
73867881
PNA		 2910 }
2911 break;
2912 case FLOW_ACTION_MARK: {
2913 u32 mark = act->mark;
e3a2b7ed
AV		 2914
2915 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2916 NL_SET_ERR_MSG_MOD(extack,
2917 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2918 return -EINVAL;
2919 }
2920
3bc4b7bf 2921 attr->flow_tag = mark;
1cab1cd7 2922 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2923 }
2924 break;
2925 default:
2cc1cb1d
TZ		 2926 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2927 return -EOPNOTSUPP;
e3a2b7ed 2928 }
e3a2b7ed
AV		 2929 }
2930
c500c86b
PNA		 2931 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2932 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2933 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2934 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2935 if (err)
2936 return err;
27c11b6b
EB		 2937 /* in case all pedit actions are skipped, remove the MOD_HDR
2938 * flag.
2939 */
e7739a60 2940 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2941 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2942 kfree(parse_attr->mod_hdr_actions);
2943 }
c500c86b
PNA		 2944 }
2945
1cab1cd7 2946 attr->action = action;
73867881 2947 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2948 return -EOPNOTSUPP;
2949
e3a2b7ed
AV		 2950 return 0;
2951}
2952
7f1a546e 2953struct encap_key {
1f6da306 2954 const struct ip_tunnel_key *ip_tun_key;
d386939a 2955 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2956};
2957
2958static inline int cmp_encap_info(struct encap_key *a,
2959 struct encap_key *b)
a54e20b4 2960{
7f1a546e 2961 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2962 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2963}
2964
7f1a546e 2965static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2966{
7f1a546e 2967 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2968 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 2969}
2970
a54e20b4 2971
b1d90e6b
RL		 2972static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2973 struct net_device *peer_netdev)
2974{
2975 struct mlx5e_priv *peer_priv;
2976
2977 peer_priv = netdev_priv(peer_netdev);
2978
2979 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2980 mlx5e_eswitch_rep(priv->netdev) &&
2981 mlx5e_eswitch_rep(peer_netdev) &&
2982 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2983}
2984
32f3671f 2985
f5bc2c5d 2986
948993f2
VB		 2987bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
2988{
2989 return refcount_inc_not_zero(&e->refcnt);
2990}
2991
2992static struct mlx5e_encap_entry *
2993mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
2994 uintptr_t hash_key)
2995{
2996 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2997 struct mlx5e_encap_entry *e;
2998 struct encap_key e_key;
2999
3000 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3001 encap_hlist, hash_key) {
3002 e_key.ip_tun_key = &e->tun_info->key;
3003 e_key.tc_tunnel = e->tunnel;
3004 if (!cmp_encap_info(&e_key, key) &&
3005 mlx5e_encap_take(e))
3006 return e;
3007 }
3008
3009 return NULL;
3010}
3011
2a4b6526
VB		 3012static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3013{
3014 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3015
3016 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3017}
3018
a54e20b4 3019static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3020 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3021 struct net_device *mirred_dev,
3022 int out_index,
8c4dc42b 3023 struct netlink_ext_ack *extack,
0ad060ee
RD		 3024 struct net_device **encap_dev,
3025 bool *encap_valid)
a54e20b4
HHZ		 3026{
3027 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3028 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3029 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3030 const struct ip_tunnel_info *tun_info;
948993f2 3031 struct encap_key key;
c1ae1152 3032 struct mlx5e_encap_entry *e;
733d4f36 3033 unsigned short family;
a54e20b4 3034 uintptr_t hash_key;
54c177ca 3035 int err = 0;
a54e20b4 3036
733d4f36 3037 parse_attr = attr->parse_attr;
1f6da306 3038 tun_info = parse_attr->tun_info[out_index];
733d4f36 3039 family = ip_tunnel_info_af(tun_info);
7f1a546e 3040 key.ip_tun_key = &tun_info->key;
d386939a 3041 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3042 if (!key.tc_tunnel) {
3043 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3044 return -EOPNOTSUPP;
3045 }
733d4f36 3046
7f1a546e 3047 hash_key = hash_encap_info(&key);
a54e20b4 3048
61086f39 3049 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3050 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3051
b2812089 3052 /* must verify if encap is valid or not */
d589e785
VB		 3053 if (e) {
3054 mutex_unlock(&esw->offloads.encap_tbl_lock);
3055 wait_for_completion(&e->res_ready);
3056
3057 /* Protect against concurrent neigh update. */
3058 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3059 if (e->compl_result < 0) {
d589e785
VB		 3060 err = -EREMOTEIO;
3061 goto out_err;
3062 }
45247bf2 3063 goto attach_flow;
d589e785 3064 }
a54e20b4
HHZ		 3065
3066 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3067 if (!e) {
3068 err = -ENOMEM;
3069 goto out_err;
3070 }
a54e20b4 3071
948993f2 3072 refcount_set(&e->refcnt, 1);
d589e785
VB		 3073 init_completion(&e->res_ready);
3074
2a4b6526
VB		 3075 tun_info = dup_tun_info(tun_info);
3076 if (!tun_info) {
3077 err = -ENOMEM;
3078 goto out_err_init;
3079 }
1f6da306 3080 e->tun_info = tun_info;
101f4de9 3081 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3082 if (err)
3083 goto out_err_init;
54c177ca 3084
a54e20b4 3085 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3086 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3087 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3088
ce99f6b9 3089 if (family == AF_INET)
101f4de9 3090 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3091 else if (family == AF_INET6)
101f4de9 3092 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3093
d589e785
VB		 3094 /* Protect against concurrent neigh update. */
3095 mutex_lock(&esw->offloads.encap_tbl_lock);
3096 complete_all(&e->res_ready);
3097 if (err) {
3098 e->compl_result = err;
a54e20b4 3099 goto out_err;
d589e785 3100 }
3c140dd5 3101 e->compl_result = 1;
a54e20b4 3102
45247bf2 3103attach_flow:
948993f2 3104 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3105 list_add(&flow->encaps[out_index].list, &e->flows);
3106 flow->encaps[out_index].index = out_index;
45247bf2 3107 *encap_dev = e->out_dev;
8c4dc42b 3108 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3109 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3110 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3111 *encap_valid = true;
8c4dc42b 3112 } else {
0ad060ee 3113 *encap_valid = false;
8c4dc42b 3114 }
61086f39 3115 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3116
232c0013 3117 return err;
a54e20b4
HHZ		 3118
3119out_err:
61086f39 3120 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3121 if (e)
3122 mlx5e_encap_put(priv, e);
a54e20b4 3123 return err;
2a4b6526
VB		 3124
3125out_err_init:
3126 mutex_unlock(&esw->offloads.encap_tbl_lock);
3127 kfree(tun_info);
3128 kfree(e);
3129 return err;
a54e20b4
HHZ		 3130}
3131
1482bd3d 3132static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3133 const struct flow_action_entry *act,
1482bd3d
JL		 3134 struct mlx5_esw_flow_attr *attr,
3135 u32 *action)
3136{
cc495188
JL		 3137 u8 vlan_idx = attr->total_vlan;
3138
3139 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3140 return -EOPNOTSUPP;
3141
73867881
PNA		 3142 switch (act->id) {
3143 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3144 if (vlan_idx) {
3145 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3146 MLX5_FS_VLAN_DEPTH))
3147 return -EOPNOTSUPP;
3148
3149 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3150 } else {
3151 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3152 }
73867881
PNA		 3153 break;
3154 case FLOW_ACTION_VLAN_PUSH:
3155 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3156 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3157 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3158 if (!attr->vlan_proto[vlan_idx])
3159 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3160
3161 if (vlan_idx) {
3162 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3163 MLX5_FS_VLAN_DEPTH))
3164 return -EOPNOTSUPP;
3165
3166 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3167 } else {
3168 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3169 (act->vlan.proto != htons(ETH_P_8021Q) ||
3170 act->vlan.prio))
cc495188
JL		 3171 return -EOPNOTSUPP;
3172
3173 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3174 }
73867881
PNA		 3175 break;
3176 default:
bdc837ee 3177 return -EINVAL;
1482bd3d
JL		 3178 }
3179
cc495188
JL		 3180 attr->total_vlan = vlan_idx + 1;
3181
1482bd3d
JL		 3182 return 0;
3183}
3184
278748a9
EB		 3185static int add_vlan_push_action(struct mlx5e_priv *priv,
3186 struct mlx5_esw_flow_attr *attr,
3187 struct net_device **out_dev,
3188 u32 *action)
3189{
3190 struct net_device *vlan_dev = *out_dev;
3191 struct flow_action_entry vlan_act = {
3192 .id = FLOW_ACTION_VLAN_PUSH,
3193 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3194 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3195 .vlan.prio = 0,
3196 };
3197 int err;
3198
3199 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3200 if (err)
3201 return err;
3202
a2b17b79
DC		 3203 rcu_read_lock();
3204 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3205 rcu_read_unlock();
3206 if (!*out_dev)
3207 return -ENODEV;
3208
278748a9
EB		 3209 if (is_vlan_dev(*out_dev))
3210 err = add_vlan_push_action(priv, attr, out_dev, action);
3211
3212 return err;
3213}
3214
35a605db
EB		 3215static int add_vlan_pop_action(struct mlx5e_priv *priv,
3216 struct mlx5_esw_flow_attr *attr,
3217 u32 *action)
3218{
35a605db
EB		 3219 struct flow_action_entry vlan_act = {
3220 .id = FLOW_ACTION_VLAN_POP,
3221 };
3d4d370c 3222 int nest_level, err = 0;
35a605db 3223
3d4d370c
DL		 3224 nest_level = attr->parse_attr->filter_dev->lower_level -
3225 priv->netdev->lower_level;
35a605db
EB		 3226 while (nest_level--) {
3227 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3228 if (err)
3229 return err;
3230 }
3231
3232 return err;
3233}
3234
f6dc1264
PB		 3235bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3236 struct net_device *out_dev)
3237{
3238 if (is_merged_eswitch_dev(priv, out_dev))
3239 return true;
3240
3241 return mlx5e_eswitch_rep(out_dev) &&
3242 same_hw_devs(priv, netdev_priv(out_dev));
3243}
3244
73867881
PNA		 3245static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3246 struct flow_action *flow_action,
e98bedf5
EB		 3247 struct mlx5e_tc_flow *flow,
3248 struct netlink_ext_ack *extack)
03a9d11e 3249{
73867881 3250 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3251 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3252 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3253 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3254 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 3255 const struct ip_tunnel_info *info = NULL;
3256 const struct flow_action_entry *act;
a54e20b4 3257 bool encap = false;
1cab1cd7 3258 u32 action = 0;
244cd96a 3259 int err, i;
03a9d11e 3260
73867881 3261 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3262 return -EINVAL;
3263
73867881
PNA		 3264 flow_action_for_each(i, act, flow_action) {
3265 switch (act->id) {
3266 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3267 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3268 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3269 break;
3270 case FLOW_ACTION_MANGLE:
3271 case FLOW_ACTION_ADD:
3272 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 3273 parse_attr, hdrs, extack);
d7e75a32
OG		 3274 if (err)
3275 return err;
3276
1cab1cd7 3277 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 3278 attr->split_count = attr->out_count;
73867881
PNA		 3279 break;
3280 case FLOW_ACTION_CSUM:
1cab1cd7 3281 if (csum_offload_supported(priv, action,
73867881
PNA		 3282 act->csum_flags, extack))
3283 break;
26c02749
OG		 3284
3285 return -EOPNOTSUPP;
73867881
PNA		 3286 case FLOW_ACTION_REDIRECT:
3287 case FLOW_ACTION_MIRRED: {
03a9d11e 3288 struct mlx5e_priv *out_priv;
592d3651 3289 struct net_device *out_dev;
03a9d11e 3290
73867881 3291 out_dev = act->dev;
ef381359
OS		 3292 if (!out_dev) {
3293 /* out_dev is NULL when filters with
3294 * non-existing mirred device are replayed to
3295 * the driver.
3296 */
3297 return -EINVAL;
3298 }
03a9d11e 3299
592d3651 3300 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3301 NL_SET_ERR_MSG_MOD(extack,
3302 "can't support more output ports, can't offload forwarding");
592d3651
CM		 3303 pr_err("can't support more than %d output ports, can't offload forwarding\n",
3304 attr->out_count);
3305 return -EOPNOTSUPP;
3306 }
3307
f493f155
EB		 3308 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3309 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 3310 if (encap) {
3311 parse_attr->mirred_ifindex[attr->out_count] =
3312 out_dev->ifindex;
3313 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3314 if (!parse_attr->tun_info[attr->out_count])
3315 return -ENOMEM;
3316 encap = false;
3317 attr->dests[attr->out_count].flags |=
3318 MLX5_ESW_DEST_ENCAP;
3319 attr->out_count++;
3320 /* attr->dests[].rep is resolved when we
3321 * handle encap
3322 */
3323 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3324 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3325 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3326 struct net_device *uplink_upper;
7ba58ba7 3327
fa833bd5
VB		 3328 rcu_read_lock();
3329 uplink_upper =
3330 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3331 if (uplink_upper &&
3332 netif_is_lag_master(uplink_upper) &&
3333 uplink_upper == out_dev)
3334 out_dev = uplink_dev;
fa833bd5 3335 rcu_read_unlock();
7ba58ba7 3336
278748a9
EB		 3337 if (is_vlan_dev(out_dev)) {
3338 err = add_vlan_push_action(priv, attr,
3339 &out_dev,
3340 &action);
3341 if (err)
3342 return err;
3343 }
f6dc1264 3344
35a605db
EB		 3345 if (is_vlan_dev(parse_attr->filter_dev)) {
3346 err = add_vlan_pop_action(priv, attr,
3347 &action);
3348 if (err)
3349 return err;
3350 }
278748a9 3351
f6dc1264
PB		 3352 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3353 NL_SET_ERR_MSG_MOD(extack,
3354 "devices are not on same switch HW, can't offload forwarding");
3355 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3356 priv->netdev->name, out_dev->name);
a0646c88 3357 return -EOPNOTSUPP;
f6dc1264 3358 }
a0646c88 3359
a54e20b4 3360 out_priv = netdev_priv(out_dev);
1d447a39 3361 rpriv = out_priv->ppriv;
df65a573
EB		 3362 attr->dests[attr->out_count].rep = rpriv->rep;
3363 attr->dests[attr->out_count].mdev = out_priv->mdev;
3364 attr->out_count++;
ef381359
OS		 3365 } else if (parse_attr->filter_dev != priv->netdev) {
3366 /* All mlx5 devices are called to configure
3367 * high level device filters. Therefore, the
3368 * *attempt* to install a filter on invalid
3369 * eswitch should not trigger an explicit error
3370 */
3371 return -EINVAL;
a54e20b4 3372 } else {
e98bedf5
EB		 3373 NL_SET_ERR_MSG_MOD(extack,
3374 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 3375 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3376 priv->netdev->name, out_dev->name);
3377 return -EINVAL;
3378 }
73867881
PNA		 3379 }
3380 break;
3381 case FLOW_ACTION_TUNNEL_ENCAP:
3382 info = act->tunnel;
a54e20b4
HHZ		 3383 if (info)
3384 encap = true;
3385 else
3386 return -EOPNOTSUPP;
1482bd3d 3387
73867881
PNA		 3388 break;
3389 case FLOW_ACTION_VLAN_PUSH:
3390 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3391 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3392 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3393 /* Replace vlan pop+push with vlan modify */
3394 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3395 err = add_vlan_rewrite_action(priv,
3396 MLX5_FLOW_NAMESPACE_FDB,
3397 act, parse_attr, hdrs,
3398 &action, extack);
3399 } else {
3400 err = parse_tc_vlan_action(priv, act, attr, &action);
3401 }
1482bd3d
JL		 3402 if (err)
3403 return err;
3404
bdc837ee
EB		 3405 attr->split_count = attr->out_count;
3406 break;
3407 case FLOW_ACTION_VLAN_MANGLE:
3408 err = add_vlan_rewrite_action(priv,
3409 MLX5_FLOW_NAMESPACE_FDB,
3410 act, parse_attr, hdrs,
3411 &action, extack);
3412 if (err)
3413 return err;
3414
e85e02ba 3415 attr->split_count = attr->out_count;
73867881
PNA		 3416 break;
3417 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 3418 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 3419 break;
3420 case FLOW_ACTION_GOTO: {
3421 u32 dest_chain = act->chain_index;
bf07aa73
PB		 3422 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3423
3424 if (dest_chain <= attr->chain) {
3425 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3426 return -EOPNOTSUPP;
3427 }
3428 if (dest_chain > max_chain) {
3429 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3430 return -EOPNOTSUPP;
3431 }
e88afe75 3432 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 3433 attr->dest_chain = dest_chain;
73867881
PNA		 3434 break;
3435 }
3436 default:
2cc1cb1d
TZ		 3437 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3438 return -EOPNOTSUPP;
bf07aa73 3439 }
03a9d11e 3440 }
bdd66ac0 3441
0bac1194
EB		 3442 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3443 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3444 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3445 * tag rewrite.
3446 */
3447 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3448 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3449 &action, extack);
3450 if (err)
3451 return err;
3452 }
3453
c500c86b
PNA		 3454 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3455 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3456 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3457 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3458 if (err)
3459 return err;
27c11b6b
EB		 3460 /* in case all pedit actions are skipped, remove the MOD_HDR
3461 * flag. we might have set split_count either by pedit or
3462 * pop/push. if there is no pop/push either, reset it too.
3463 */
3464 if (parse_attr->num_mod_hdr_actions == 0) {
3465 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3466 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3467 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3468 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3469 attr->split_count = 0;
3470 }
c500c86b
PNA		 3471 }
3472
1cab1cd7 3473 attr->action = action;
73867881 3474 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3475 return -EOPNOTSUPP;
3476
e88afe75
OG		 3477 if (attr->dest_chain) {
3478 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3479 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3480 return -EOPNOTSUPP;
3481 }
3482 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3483 }
3484
8c5bb25f
VB		 3485 if (!(attr->action &
3486 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3487 NL_SET_ERR_MSG(extack, "Rule must have at least one forward/drop action");
3488 return -EOPNOTSUPP;
3489 }
3490
e85e02ba 3491 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3492 NL_SET_ERR_MSG_MOD(extack,
3493 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3494 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3495 return -EOPNOTSUPP;
3496 }
3497
31c8eba5 3498 return 0;
03a9d11e
OG		 3499}
3500
226f2ca3 3501static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3502{
226f2ca3 3503 unsigned long __flow_flags = 0;
60bd4af8 3504
226f2ca3
VB		 3505 if (flags & MLX5_TC_FLAG(INGRESS))
3506 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3507 if (flags & MLX5_TC_FLAG(EGRESS))
3508 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3509
226f2ca3
VB		 3510 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3511 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3512 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3513 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
d9ee0491 3514
60bd4af8
OG		 3515 *flow_flags = __flow_flags;
3516}
3517
05866c82
OG		 3518static const struct rhashtable_params tc_ht_params = {
3519 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3520 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3521 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3522 .automatic_shrinking = true,
3523};
3524
226f2ca3
VB		 3525static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3526 unsigned long flags)
05866c82 3527{
655dc3d2
OG		 3528 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3529 struct mlx5e_rep_priv *uplink_rpriv;
3530
226f2ca3 3531 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3532 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3533 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3534 } else /* NIC offload */
655dc3d2 3535 return &priv->fs.tc.ht;
05866c82
OG		 3536}
3537
04de7dda
RD		 3538static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3539{
1418ddd9 3540 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3541 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3542 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3543 bool act_is_encap = !!(attr->action &
3544 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3545 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3546 MLX5_DEVCOM_ESW_OFFLOADS);
3547
10fbb1cd
RD		 3548 if (!esw_paired)
3549 return false;
3550
3551 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3552 mlx5_lag_is_multipath(attr->in_mdev)) &&
3553 (is_rep_ingress || act_is_encap))
3554 return true;
3555
3556 return false;
04de7dda
RD		 3557}
3558
a88780a9
RD		 3559static int
3560mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3561 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3562 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3563 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3564{
17091853 3565 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3566 struct mlx5e_tc_flow *flow;
5a7e5bcb 3567 int out_index, err;
e3a2b7ed 3568
65ba8fb7 3569 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3570 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3571 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3572 err = -ENOMEM;
3573 goto err_free;
3574 }
3575
3576 flow->cookie = f->cookie;
65ba8fb7 3577 flow->flags = flow_flags;
655dc3d2 3578 flow->priv = priv;
5a7e5bcb
VB		 3579 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3580 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3581 INIT_LIST_HEAD(&flow->mod_hdr);
3582 INIT_LIST_HEAD(&flow->hairpin);
3583 refcount_set(&flow->refcnt, 1);
95435ad7 3584 init_completion(&flow->init_done);
e3a2b7ed 3585
a88780a9
RD		 3586 *__flow = flow;
3587 *__parse_attr = parse_attr;
3588
3589 return 0;
3590
3591err_free:
3592 kfree(flow);
3593 kvfree(parse_attr);
3594 return err;
3595}
3596
988ab9c7
TZ		 3597static void
3598mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3599 struct mlx5e_priv *priv,
3600 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3601 struct flow_cls_offload *f,
988ab9c7
TZ		 3602 struct mlx5_eswitch_rep *in_rep,
3603 struct mlx5_core_dev *in_mdev)
3604{
3605 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3606
3607 esw_attr->parse_attr = parse_attr;
3608 esw_attr->chain = f->common.chain_index;
ef01adae 3609 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 3610
3611 esw_attr->in_rep = in_rep;
3612 esw_attr->in_mdev = in_mdev;
3613
3614 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3615 MLX5_COUNTER_SOURCE_ESWITCH)
3616 esw_attr->counter_dev = in_mdev;
3617 else
3618 esw_attr->counter_dev = priv->mdev;
3619}
3620
71129676 3621static struct mlx5e_tc_flow *
04de7dda 3622__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3623 struct flow_cls_offload *f,
226f2ca3 3624 unsigned long flow_flags,
04de7dda
RD		 3625 struct net_device *filter_dev,
3626 struct mlx5_eswitch_rep *in_rep,
71129676 3627 struct mlx5_core_dev *in_mdev)
a88780a9 3628{
f9e30088 3629 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3630 struct netlink_ext_ack *extack = f->common.extack;
3631 struct mlx5e_tc_flow_parse_attr *parse_attr;
3632 struct mlx5e_tc_flow *flow;
3633 int attr_size, err;
e3a2b7ed 3634
226f2ca3 3635 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3636 attr_size = sizeof(struct mlx5_esw_flow_attr);
3637 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3638 &parse_attr, &flow);
3639 if (err)
3640 goto out;
988ab9c7 3641
d11afc26 3642 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3643 mlx5e_flow_esw_attr_init(flow->esw_attr,
3644 priv, parse_attr,
3645 f, in_rep, in_mdev);
3646
54c177ca
OS		 3647 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3648 f, filter_dev);
d11afc26
OS		 3649 if (err)
3650 goto err_free;
a88780a9 3651
6f9af8ff 3652 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3653 if (err)
3654 goto err_free;
3655
7040632d 3656 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 3657 complete_all(&flow->init_done);
ef06c9ee
RD		 3658 if (err) {
3659 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3660 goto err_free;
3661
b4a23329 3662 add_unready_flow(flow);
ef06c9ee 3663 }
e3a2b7ed 3664
71129676 3665 return flow;
a88780a9
RD		 3666
3667err_free:
5a7e5bcb 3668 mlx5e_flow_put(priv, flow);
a88780a9 3669out:
71129676 3670 return ERR_PTR(err);
a88780a9
RD		 3671}
3672
f9e30088 3673static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3674 struct mlx5e_tc_flow *flow,
226f2ca3 3675 unsigned long flow_flags)
04de7dda
RD		 3676{
3677 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3678 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3679 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3680 struct mlx5e_tc_flow_parse_attr *parse_attr;
3681 struct mlx5e_rep_priv *peer_urpriv;
3682 struct mlx5e_tc_flow *peer_flow;
3683 struct mlx5_core_dev *in_mdev;
3684 int err = 0;
3685
3686 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3687 if (!peer_esw)
3688 return -ENODEV;
3689
3690 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3691 peer_priv = netdev_priv(peer_urpriv->netdev);
3692
3693 /* in_mdev is assigned of which the packet originated from.
3694 * So packets redirected to uplink use the same mdev of the
3695 * original flow and packets redirected from uplink use the
3696 * peer mdev.
3697 */
b05af6aa 3698 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3699 in_mdev = peer_priv->mdev;
3700 else
3701 in_mdev = priv->mdev;
3702
3703 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3704 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3705 parse_attr->filter_dev,
3706 flow->esw_attr->in_rep, in_mdev);
3707 if (IS_ERR(peer_flow)) {
3708 err = PTR_ERR(peer_flow);
04de7dda 3709 goto out;
71129676 3710 }
04de7dda
RD		 3711
3712 flow->peer_flow = peer_flow;
226f2ca3 3713 flow_flag_set(flow, DUP);
04de7dda
RD		 3714 mutex_lock(&esw->offloads.peer_mutex);
3715 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3716 mutex_unlock(&esw->offloads.peer_mutex);
3717
3718out:
3719 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3720 return err;
3721}
3722
3723static int
3724mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3725 struct flow_cls_offload *f,
226f2ca3 3726 unsigned long flow_flags,
04de7dda
RD		 3727 struct net_device *filter_dev,
3728 struct mlx5e_tc_flow **__flow)
3729{
3730 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3731 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3732 struct mlx5_core_dev *in_mdev = priv->mdev;
3733 struct mlx5e_tc_flow *flow;
3734 int err;
3735
71129676
JG		 3736 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3737 in_mdev);
3738 if (IS_ERR(flow))
3739 return PTR_ERR(flow);
04de7dda
RD		 3740
3741 if (is_peer_flow_needed(flow)) {
95dc1902 3742 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3743 if (err) {
3744 mlx5e_tc_del_fdb_flow(priv, flow);
3745 goto out;
3746 }
3747 }
3748
3749 *__flow = flow;
3750
3751 return 0;
3752
3753out:
3754 return err;
3755}
3756
a88780a9
RD		 3757static int
3758mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3759 struct flow_cls_offload *f,
226f2ca3 3760 unsigned long flow_flags,
d11afc26 3761 struct net_device *filter_dev,
a88780a9
RD		 3762 struct mlx5e_tc_flow **__flow)
3763{
f9e30088 3764 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3765 struct netlink_ext_ack *extack = f->common.extack;
3766 struct mlx5e_tc_flow_parse_attr *parse_attr;
3767 struct mlx5e_tc_flow *flow;
3768 int attr_size, err;
3769
bf07aa73
PB		 3770 /* multi-chain not supported for NIC rules */
3771 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3772 return -EOPNOTSUPP;
3773
226f2ca3 3774 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3775 attr_size = sizeof(struct mlx5_nic_flow_attr);
3776 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3777 &parse_attr, &flow);
3778 if (err)
3779 goto out;
3780
d11afc26 3781 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3782 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3783 f, filter_dev);
d11afc26
OS		 3784 if (err)
3785 goto err_free;
3786
73867881 3787 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3788 if (err)
3789 goto err_free;
3790
3791 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3792 if (err)
3793 goto err_free;
3794
226f2ca3 3795 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3796 kvfree(parse_attr);
3797 *__flow = flow;
3798
3799 return 0;
e3a2b7ed 3800
e3a2b7ed 3801err_free:
5a7e5bcb 3802 mlx5e_flow_put(priv, flow);
17091853 3803 kvfree(parse_attr);
a88780a9
RD		 3804out:
3805 return err;
3806}
3807
3808static int
3809mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3810 struct flow_cls_offload *f,
226f2ca3 3811 unsigned long flags,
d11afc26 3812 struct net_device *filter_dev,
a88780a9
RD		 3813 struct mlx5e_tc_flow **flow)
3814{
3815 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3816 unsigned long flow_flags;
a88780a9
RD		 3817 int err;
3818
3819 get_flags(flags, &flow_flags);
3820
bf07aa73
PB		 3821 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3822 return -EOPNOTSUPP;
3823
f6455de0 3824 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3825 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3826 filter_dev, flow);
a88780a9 3827 else
d11afc26
OS		 3828 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3829 filter_dev, flow);
a88780a9
RD		 3830
3831 return err;
3832}
3833
71d82d2a 3834int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3835 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3836{
3837 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3838 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3839 struct mlx5e_tc_flow *flow;
3840 int err = 0;
3841
c5d326b2
VB		 3842 rcu_read_lock();
3843 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3844 rcu_read_unlock();
a88780a9
RD		 3845 if (flow) {
3846 NL_SET_ERR_MSG_MOD(extack,
3847 "flow cookie already exists, ignoring");
3848 netdev_warn_once(priv->netdev,
3849 "flow cookie %lx already exists, ignoring\n",
3850 f->cookie);
0e1c1a2f 3851 err = -EEXIST;
a88780a9
RD		 3852 goto out;
3853 }
3854
7a978759 3855 trace_mlx5e_configure_flower(f);
d11afc26 3856 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3857 if (err)
3858 goto out;
3859
c5d326b2 3860 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3861 if (err)
3862 goto err_free;
3863
3864 return 0;
3865
3866err_free:
5a7e5bcb 3867 mlx5e_flow_put(priv, flow);
a88780a9 3868out:
e3a2b7ed
AV		 3869 return err;
3870}
3871
8f8ae895
OG		 3872static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3873{
226f2ca3
VB		 3874 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3875 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 3876
226f2ca3
VB		 3877 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3878 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 3879}
3880
71d82d2a 3881int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3882 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 3883{
d9ee0491 3884 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3885 struct mlx5e_tc_flow *flow;
c5d326b2 3886 int err;
e3a2b7ed 3887
c5d326b2 3888 rcu_read_lock();
05866c82 3889 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 3890 if (!flow || !same_flow_direction(flow, flags)) {
3891 err = -EINVAL;
3892 goto errout;
3893 }
e3a2b7ed 3894
c5d326b2
VB		 3895 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3896 * set.
3897 */
3898 if (flow_flag_test_and_set(flow, DELETED)) {
3899 err = -EINVAL;
3900 goto errout;
3901 }
05866c82 3902 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 3903 rcu_read_unlock();
e3a2b7ed 3904
7a978759 3905 trace_mlx5e_delete_flower(f);
5a7e5bcb 3906 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 3907
3908 return 0;
c5d326b2
VB		 3909
3910errout:
3911 rcu_read_unlock();
3912 return err;
e3a2b7ed
AV		 3913}
3914
71d82d2a 3915int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3916 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 3917{
04de7dda 3918 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3919 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3920 struct mlx5_eswitch *peer_esw;
aad7e08d 3921 struct mlx5e_tc_flow *flow;
aad7e08d 3922 struct mlx5_fc *counter;
316d5f72
RD		 3923 u64 lastuse = 0;
3924 u64 packets = 0;
3925 u64 bytes = 0;
5a7e5bcb 3926 int err = 0;
aad7e08d 3927
c5d326b2
VB		 3928 rcu_read_lock();
3929 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3930 tc_ht_params));
3931 rcu_read_unlock();
5a7e5bcb
VB		 3932 if (IS_ERR(flow))
3933 return PTR_ERR(flow);
3934
3935 if (!same_flow_direction(flow, flags)) {
3936 err = -EINVAL;
3937 goto errout;
3938 }
aad7e08d 3939
226f2ca3 3940 if (mlx5e_is_offloaded_flow(flow)) {
316d5f72
RD		 3941 counter = mlx5e_tc_get_counter(flow);
3942 if (!counter)
5a7e5bcb 3943 goto errout;
aad7e08d 3944
316d5f72
RD		 3945 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3946 }
aad7e08d 3947
316d5f72
RD		 3948 /* Under multipath it's possible for one rule to be currently
3949 * un-offloaded while the other rule is offloaded.
3950 */
04de7dda
RD		 3951 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3952 if (!peer_esw)
3953 goto out;
3954
226f2ca3
VB		 3955 if (flow_flag_test(flow, DUP) &&
3956 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 3957 u64 bytes2;
3958 u64 packets2;
3959 u64 lastuse2;
3960
3961 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3962 if (!counter)
3963 goto no_peer_counter;
04de7dda
RD		 3964 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3965
3966 bytes += bytes2;
3967 packets += packets2;
3968 lastuse = max_t(u64, lastuse, lastuse2);
3969 }
3970
316d5f72 3971no_peer_counter:
04de7dda 3972 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3973out:
3b1903ef 3974 flow_stats_update(&f->stats, bytes, packets, lastuse);
7a978759 3975 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 3976errout:
3977 mlx5e_flow_put(priv, flow);
3978 return err;
aad7e08d
AV		 3979}
3980
d82e406f 3981static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 3982 struct netlink_ext_ack *extack)
3983{
3984 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3985 struct mlx5_eswitch *esw;
d82e406f 3986 u32 rate_mbps = 0;
fcb64c0f 3987 u16 vport_num;
fcb64c0f
EC		 3988 int err;
3989
aab7b3cb
EC		 3990 vport_num = rpriv->rep->vport;
3991 if (vport_num >= MLX5_VPORT_ECPF) {
3992 NL_SET_ERR_MSG_MOD(extack,
3993 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
3994 return -EOPNOTSUPP;
3995 }
3996
fcb64c0f
EC		 3997 esw = priv->mdev->priv.eswitch;
3998 /* rate is given in bytes/sec.
3999 * First convert to bits/sec and then round to the nearest mbit/secs.
4000 * mbit means million bits.
4001 * Moreover, if rate is non zero we choose to configure to a minimum of
4002 * 1 mbit/sec.
4003 */
d82e406f
PP		 4004 if (rate) {
4005 rate = (rate * BITS_PER_BYTE) + 500000;
4006 rate_mbps = max_t(u32, do_div(rate, 1000000), 1);
4007 }
4008
fcb64c0f
EC		 4009 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4010 if (err)
4011 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4012
4013 return err;
4014}
4015
4016static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4017 struct flow_action *flow_action,
4018 struct netlink_ext_ack *extack)
4019{
4020 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4021 const struct flow_action_entry *act;
4022 int err;
4023 int i;
4024
4025 if (!flow_action_has_entries(flow_action)) {
4026 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4027 return -EINVAL;
4028 }
4029
4030 if (!flow_offload_has_one_action(flow_action)) {
4031 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4032 return -EOPNOTSUPP;
4033 }
4034
4035 flow_action_for_each(i, act, flow_action) {
4036 switch (act->id) {
4037 case FLOW_ACTION_POLICE:
4038 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4039 if (err)
4040 return err;
4041
4042 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4043 break;
4044 default:
4045 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4046 return -EOPNOTSUPP;
4047 }
4048 }
4049
4050 return 0;
4051}
4052
4053int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4054 struct tc_cls_matchall_offload *ma)
4055{
4056 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4057
7b83355f 4058 if (ma->common.prio != 1) {
fcb64c0f
EC		 4059 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4060 return -EINVAL;
4061 }
4062
4063 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4064}
4065
4066int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4067 struct tc_cls_matchall_offload *ma)
4068{
4069 struct netlink_ext_ack *extack = ma->common.extack;
4070
4071 return apply_police_params(priv, 0, extack);
4072}
4073
4074void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4075 struct tc_cls_matchall_offload *ma)
4076{
4077 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4078 struct rtnl_link_stats64 cur_stats;
4079 u64 dbytes;
4080 u64 dpkts;
4081
4082 cur_stats = priv->stats.vf_vport;
4083 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4084 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4085 rpriv->prev_vf_vport_stats = cur_stats;
4086 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4087}
4088
4d8fcf21
AH		 4089static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4090 struct mlx5e_priv *peer_priv)
4091{
4092 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4093 struct mlx5e_hairpin_entry *hpe, *tmp;
4094 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4095 u16 peer_vhca_id;
4096 int bkt;
4097
4098 if (!same_hw_devs(priv, peer_priv))
4099 return;
4100
4101 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4102
b32accda 4103 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4104 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4105 if (refcount_inc_not_zero(&hpe->refcnt))
4106 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4107 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4108
4109 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4110 wait_for_completion(&hpe->res_ready);
4111 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
d2c8663b 4112 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4113
4114 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4115 }
4116}
4117
4118static int mlx5e_tc_netdev_event(struct notifier_block *this,
4119 unsigned long event, void *ptr)
4120{
4121 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4122 struct mlx5e_flow_steering *fs;
4123 struct mlx5e_priv *peer_priv;
4124 struct mlx5e_tc_table *tc;
4125 struct mlx5e_priv *priv;
4126
4127 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4128 event != NETDEV_UNREGISTER ||
4129 ndev->reg_state == NETREG_REGISTERED)
4130 return NOTIFY_DONE;
4131
4132 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4133 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4134 priv = container_of(fs, struct mlx5e_priv, fs);
4135 peer_priv = netdev_priv(ndev);
4136 if (priv == peer_priv ||
4137 !(priv->netdev->features & NETIF_F_HW_TC))
4138 return NOTIFY_DONE;
4139
4140 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4141
4142 return NOTIFY_DONE;
4143}
4144
655dc3d2 4145int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4146{
acff797c 4147 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4148 int err;
e8f887ac 4149
b6fac0b4 4150 mutex_init(&tc->t_lock);
d2faae25 4151 mutex_init(&tc->mod_hdr.lock);
dd58edc3 4152 hash_init(tc->mod_hdr.hlist);
b32accda 4153 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4154 hash_init(tc->hairpin_tbl);
11c9c548 4155
4d8fcf21
AH		 4156 err = rhashtable_init(&tc->ht, &tc_ht_params);
4157 if (err)
4158 return err;
4159
4160 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4161 if (register_netdevice_notifier(&tc->netdevice_nb)) {
4162 tc->netdevice_nb.notifier_call = NULL;
4163 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4164 }
4165
4166 return err;
e8f887ac
AV		 4167}
4168
4169static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4170{
4171 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4172 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4173
961e8979 4174 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4175 kfree(flow);
4176}
4177
655dc3d2 4178void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4179{
acff797c 4180 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4181
4d8fcf21
AH		 4182 if (tc->netdevice_nb.notifier_call)
4183 unregister_netdevice_notifier(&tc->netdevice_nb);
4184
d2faae25 4185 mutex_destroy(&tc->mod_hdr.lock);
b32accda
VB		 4186 mutex_destroy(&tc->hairpin_tbl_lock);
4187
d9ee0491 4188 rhashtable_destroy(&tc->ht);
e8f887ac 4189
acff797c
MG		 4190 if (!IS_ERR_OR_NULL(tc->t)) {
4191 mlx5_destroy_flow_table(tc->t);
4192 tc->t = NULL;
e8f887ac 4193 }
b6fac0b4 4194 mutex_destroy(&tc->t_lock);
e8f887ac 4195}
655dc3d2
OG		 4196
4197int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4198{
4199 return rhashtable_init(tc_ht, &tc_ht_params);
4200}
4201
4202void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4203{
4204 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4205}
01252a27 4206
226f2ca3 4207int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4208{
d9ee0491 4209 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4210
4211 return atomic_read(&tc_ht->nelems);
4212}
04de7dda
RD		 4213
4214void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4215{
4216 struct mlx5e_tc_flow *flow, *tmp;
4217
4218 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4219 __mlx5e_tc_del_fdb_peer_flow(flow);
4220}
b4a23329
RD		 4221
4222void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4223{
4224 struct mlx5_rep_uplink_priv *rpriv =
4225 container_of(work, struct mlx5_rep_uplink_priv,
4226 reoffload_flows_work);
4227 struct mlx5e_tc_flow *flow, *tmp;
4228
ad86755b 4229 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4230 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4231 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4232 unready_flow_del(flow);
b4a23329 4233 }
ad86755b 4234 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4235}
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