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UBUNTU: Ubuntu-5.15.0-39.42
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
d79b6df6 42#include <net/tc_act/tc_pedit.h>
26c02749 43#include <net/tc_act/tc_csum.h>
41c2fd94 44#include <net/psample.h>
f6dfb4c3 45#include <net/arp.h>
3616d08b 46#include <net/ipv6_stubs.h>
f828ca6a 47#include <net/bareudp.h>
d34eb2fc 48#include <net/bonding.h>
e8f887ac 49#include "en.h"
f0da4daa 50#include "en/tc/post_act.h"
1d447a39 51#include "en_rep.h"
768c3667 52#include "en/rep/tc.h"
e2394a61 53#include "en/rep/neigh.h"
232c0013 54#include "en_tc.h"
03a9d11e 55#include "eswitch.h"
3f6d08d1 56#include "fs_core.h"
2c81bfd5 57#include "en/port.h"
101f4de9 58#include "en/tc_tun.h"
0a7fcb78 59#include "en/mapping.h"
4c3844d9 60#include "en/tc_ct.h"
b2fdf3d0 61#include "en/mod_hdr.h"
0d9f9647
VB		 62#include "en/tc_priv.h"
63#include "en/tc_tun_encap.h"
0027d70c 64#include "en/tc/sample.h"
04de7dda 65#include "lib/devcom.h"
9272e3df 66#include "lib/geneve.h"
ae430332 67#include "lib/fs_chains.h"
7a978759 68#include "diag/en_tc_tracepoint.h"
1fe3e316 69#include <asm/div64.h>
14fe2471
MD		 70#include "lag.h"
71#include "lag_mp.h"
e8f887ac 72
6a064674 73#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 74#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 75
acff797c 76#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 77#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 78
8f1e0b97
PB		 79struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
80 [CHAIN_TO_REG] = {
81 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
82 .moffset = 0,
ed2fe7ba 83 .mlen = 16,
8f1e0b97 84 },
10742efc
VB		 85 [VPORT_TO_REG] = {
86 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 87 .moffset = 16,
88 .mlen = 16,
10742efc 89 },
0a7fcb78
PB		 90 [TUNNEL_TO_REG] = {
91 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 92 .moffset = 8,
93 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 94 .soffset = MLX5_BYTE_OFF(fte_match_param,
95 misc_parameters_2.metadata_reg_c_1),
96 },
4c3844d9 97 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 98 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 99 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
100 [MARK_TO_REG] = mark_to_reg_ct,
101 [LABELS_TO_REG] = labels_to_reg_ct,
102 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 103 /* For NIC rules we store the restore metadata directly
c7569097
AL		 104 * into reg_b that is passed to SW since we don't
105 * jump between steering domains.
106 */
107 [NIC_CHAIN_TO_REG] = {
108 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
109 .moffset = 0,
ed2fe7ba 110 .mlen = 16,
c7569097 111 },
aedd133d 112 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 113};
114
9ba33339
RD		 115/* To avoid false lock dependency warning set the tc_ht lock
116 * class different than the lock class of the ht being used when deleting
117 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
118 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
119 * it's different than the ht->mutex here.
120 */
121static struct lock_class_key tc_ht_lock_key;
122
0a7fcb78
PB		 123static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
124
125void
126mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
127 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 128 u32 val,
0a7fcb78
PB		 129 u32 mask)
130{
ed2fe7ba 131 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 132 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 133 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 134 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 135 u32 max_mask = GENMASK(match_len - 1, 0);
136 __be32 curr_mask_be, curr_val_be;
137 u32 curr_mask, curr_val;
0a7fcb78
PB		 138
139 fmask = headers_c + soffset;
140 fval = headers_v + soffset;
141
ed2fe7ba
PB		 142 memcpy(&curr_mask_be, fmask, 4);
143 memcpy(&curr_val_be, fval, 4);
144
145 curr_mask = be32_to_cpu(curr_mask_be);
146 curr_val = be32_to_cpu(curr_val_be);
147
148 //move to correct offset
149 WARN_ON(mask > max_mask);
150 mask <<= moffset;
151 val <<= moffset;
152 max_mask <<= moffset;
153
154 //zero val and mask
155 curr_mask &= ~max_mask;
156 curr_val &= ~max_mask;
0a7fcb78 157
ed2fe7ba
PB		 158 //add current to mask
159 curr_mask |= mask;
160 curr_val |= val;
161
162 //back to be32 and write
163 curr_mask_be = cpu_to_be32(curr_mask);
164 curr_val_be = cpu_to_be32(curr_val);
165
166 memcpy(fmask, &curr_mask_be, 4);
167 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 168
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
170}
171
7e36feeb
PB		 172void
173mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
174 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 175 u32 *val,
7e36feeb
PB		 176 u32 *mask)
177{
ed2fe7ba 178 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 179 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 180 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 181 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 182 u32 max_mask = GENMASK(match_len - 1, 0);
183 __be32 curr_mask_be, curr_val_be;
184 u32 curr_mask, curr_val;
7e36feeb
PB		 185
186 fmask = headers_c + soffset;
187 fval = headers_v + soffset;
188
ed2fe7ba
PB		 189 memcpy(&curr_mask_be, fmask, 4);
190 memcpy(&curr_val_be, fval, 4);
191
192 curr_mask = be32_to_cpu(curr_mask_be);
193 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 194
ed2fe7ba
PB		 195 *mask = (curr_mask >> moffset) & max_mask;
196 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 197}
198
0a7fcb78 199int
c7b9038d
VB		 200mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
201 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
202 enum mlx5_flow_namespace_type ns,
203 enum mlx5e_tc_attr_to_reg type,
204 u32 data)
0a7fcb78
PB		 205{
206 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
207 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
208 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
209 char *modact;
210 int err;
211
aedd133d 212 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 213 if (err)
214 return err;
215
216 modact = mod_hdr_acts->actions +
217 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
218
219 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 220 if (mlen == 32)
0a7fcb78
PB		 221 mlen = 0;
222
223 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
224 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 225 MLX5_SET(set_action_in, modact, offset, moffset);
226 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 227 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 228 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 229 mod_hdr_acts->num_actions++;
230
c7b9038d 231 return err;
0a7fcb78
PB		 232}
233
aedd133d
AL		 234static struct mlx5_tc_ct_priv *
235get_ct_priv(struct mlx5e_priv *priv)
236{
237 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
238 struct mlx5_rep_uplink_priv *uplink_priv;
239 struct mlx5e_rep_priv *uplink_rpriv;
240
e8711402 241 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 242 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
243 uplink_priv = &uplink_rpriv->uplink_priv;
244
245 return uplink_priv->ct_priv;
246 }
247
248 return priv->fs.tc.ct;
249}
250
0027d70c 251static struct mlx5e_tc_psample *
f94d6389
CM		 252get_sample_priv(struct mlx5e_priv *priv)
253{
254 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
255 struct mlx5_rep_uplink_priv *uplink_priv;
256 struct mlx5e_rep_priv *uplink_rpriv;
257
258 if (is_mdev_switchdev_mode(priv->mdev)) {
259 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
260 uplink_priv = &uplink_rpriv->uplink_priv;
261
0027d70c 262 return uplink_priv->tc_psample;
f94d6389
CM		 263 }
264
265 return NULL;
266}
f94d6389 267
aedd133d
AL		 268struct mlx5_flow_handle *
269mlx5_tc_rule_insert(struct mlx5e_priv *priv,
270 struct mlx5_flow_spec *spec,
271 struct mlx5_flow_attr *attr)
272{
273 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
274
e8711402 275 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 276 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
277
278 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
279}
280
281void
282mlx5_tc_rule_delete(struct mlx5e_priv *priv,
283 struct mlx5_flow_handle *rule,
284 struct mlx5_flow_attr *attr)
285{
286 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
287
e8711402 288 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 289 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
290
291 return;
292 }
293
294 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
295}
296
c7b9038d
VB		 297int
298mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
299 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
300 enum mlx5_flow_namespace_type ns,
301 enum mlx5e_tc_attr_to_reg type,
302 u32 data)
303{
304 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
305
306 return ret < 0 ? ret : 0;
307}
308
309void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
310 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
311 enum mlx5e_tc_attr_to_reg type,
312 int act_id, u32 data)
313{
314 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
315 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
316 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
317 char *modact;
318
319 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
320
321 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 322 if (mlen == 32)
c7b9038d
VB		 323 mlen = 0;
324
325 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
326 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 327 MLX5_SET(set_action_in, modact, offset, moffset);
328 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 329 MLX5_SET(set_action_in, modact, data, data);
330}
331
77ab67b7
OG		 332struct mlx5e_hairpin {
333 struct mlx5_hairpin *pair;
334
335 struct mlx5_core_dev *func_mdev;
3f6d08d1 336 struct mlx5e_priv *func_priv;
77ab67b7 337 u32 tdn;
a6696735 338 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 339
340 int num_channels;
341 struct mlx5e_rqt indir_rqt;
a6696735 342 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 343 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 344};
345
5c65c564
OG		 346struct mlx5e_hairpin_entry {
347 /* a node of a hash table which keeps all the hairpin entries */
348 struct hlist_node hairpin_hlist;
349
73edca73
VB		 350 /* protects flows list */
351 spinlock_t flows_lock;
5c65c564
OG		 352 /* flows sharing the same hairpin */
353 struct list_head flows;
db76ca24
VB		 354 /* hpe's that were not fully initialized when dead peer update event
355 * function traversed them.
356 */
357 struct list_head dead_peer_wait_list;
5c65c564 358
d8822868 359 u16 peer_vhca_id;
106be53b 360 u8 prio;
5c65c564 361 struct mlx5e_hairpin *hp;
e4f9abbd 362 refcount_t refcnt;
db76ca24 363 struct completion res_ready;
5c65c564
OG		 364};
365
5a7e5bcb
VB		 366static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
367 struct mlx5e_tc_flow *flow);
368
0d9f9647 369struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 370{
371 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
372 return ERR_PTR(-EINVAL);
373 return flow;
374}
375
0d9f9647 376void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 377{
378 if (refcount_dec_and_test(&flow->refcnt)) {
379 mlx5e_tc_del_flow(priv, flow);
c5d326b2 380 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 381 }
382}
383
aedd133d 384bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 385{
386 return flow_flag_test(flow, ESWITCH);
387}
388
84179981
PB		 389static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390{
391 return flow_flag_test(flow, FT);
392}
393
0d9f9647 394bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 395{
396 return flow_flag_test(flow, OFFLOADED);
397}
398
b2fdf3d0 399static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 400{
b2fdf3d0
PB		 401 return mlx5e_is_eswitch_flow(flow) ?
402 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 403}
404
dd58edc3 405static struct mod_hdr_tbl *
b2fdf3d0 406get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 407{
408 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
409
b2fdf3d0
PB		 410 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
411 &esw->offloads.mod_hdr :
dd58edc3
VB		 412 &priv->fs.tc.mod_hdr;
413}
414
11c9c548
OG		 415static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
416 struct mlx5e_tc_flow *flow,
417 struct mlx5e_tc_flow_parse_attr *parse_attr)
418{
b2fdf3d0
PB		 419 struct mlx5_modify_hdr *modify_hdr;
420 struct mlx5e_mod_hdr_handle *mh;
11c9c548 421
b2fdf3d0
PB		 422 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
423 get_flow_name_space(flow),
424 &parse_attr->mod_hdr_acts);
425 if (IS_ERR(mh))
426 return PTR_ERR(mh);
11c9c548 427
b2fdf3d0 428 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 429 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 430 flow->mh = mh;
11c9c548
OG		 431
432 return 0;
11c9c548
OG		 433}
434
435static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
436 struct mlx5e_tc_flow *flow)
437{
5a7e5bcb 438 /* flow wasn't fully initialized */
dd58edc3 439 if (!flow->mh)
5a7e5bcb
VB		 440 return;
441
b2fdf3d0
PB		 442 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
443 flow->mh);
dd58edc3 444 flow->mh = NULL;
11c9c548
OG		 445}
446
77ab67b7
OG		 447static
448struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
449{
b1c2f631 450 struct mlx5_core_dev *mdev;
77ab67b7
OG		 451 struct net_device *netdev;
452 struct mlx5e_priv *priv;
453
b1c2f631
DC		 454 netdev = dev_get_by_index(net, ifindex);
455 if (!netdev)
456 return ERR_PTR(-ENODEV);
457
77ab67b7 458 priv = netdev_priv(netdev);
b1c2f631
DC		 459 mdev = priv->mdev;
460 dev_put(netdev);
461
462 /* Mirred tc action holds a refcount on the ifindex net_device (see
463 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
464 * after dev_put(netdev), while we're in the context of adding a tc flow.
465 *
466 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
467 * stored in a hairpin object, which exists until all flows, that refer to it, get
468 * removed.
469 *
470 * On the other hand, after a hairpin object has been created, the peer net_device may
471 * be removed/unbound while there are still some hairpin flows that are using it. This
472 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
473 * NETDEV_UNREGISTER event of the peer net_device.
474 */
475 return mdev;
77ab67b7
OG		 476}
477
478static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
479{
a6696735 480 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 481 int err;
482
a6696735
MM		 483 builder = mlx5e_tir_builder_alloc(false);
484 if (!builder)
485 return -ENOMEM;
486
77ab67b7
OG		 487 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
488 if (err)
a6696735 489 goto out;
77ab67b7 490
a6696735
MM		 491 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
492 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 493 if (err)
494 goto create_tir_err;
495
a6696735
MM		 496out:
497 mlx5e_tir_builder_free(builder);
498 return err;
77ab67b7
OG		 499
500create_tir_err:
501 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 502
503 goto out;
77ab67b7
OG		 504}
505
506static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
507{
a6696735 508 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 509 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
510}
511
3f6d08d1
OG		 512static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
513{
3f6d08d1
OG		 514 struct mlx5e_priv *priv = hp->func_priv;
515 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 516 struct mlx5e_rss_params_indir *indir;
517 int err;
3f6d08d1 518
06e9f13a
MM		 519 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
520 if (!indir)
3f6d08d1
OG		 521 return -ENOMEM;
522
43befe99 523 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 524 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 525 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
526 indir);
3f6d08d1 527
06e9f13a 528 kvfree(indir);
3f6d08d1
OG		 529 return err;
530}
531
532static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
533{
534 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 535 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 536 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 537 struct mlx5e_tir_builder *builder;
538 int err = 0;
539
540 builder = mlx5e_tir_builder_alloc(false);
541 if (!builder)
542 return -ENOMEM;
543
43ec0f41 544 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 545
546 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 547 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 548
65d6b6e5 549 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 550
a6696735
MM		 551 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
552 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
553 false);
43ec0f41 554 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 555
a6696735 556 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 557 if (err) {
558 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
559 goto err_destroy_tirs;
560 }
a6696735
MM		 561
562 mlx5e_tir_builder_clear(builder);
3f6d08d1 563 }
3f6d08d1 564
a6696735
MM		 565out:
566 mlx5e_tir_builder_free(builder);
3f6d08d1 567 return err;
a6696735
MM		 568
569err_destroy_tirs:
570 max_tt = tt;
571 for (tt = 0; tt < max_tt; tt++)
572 mlx5e_tir_destroy(&hp->indir_tir[tt]);
573
574 goto out;
3f6d08d1
OG		 575}
576
577static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
578{
579 int tt;
580
581 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 582 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 583}
584
585static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
586 struct ttc_params *ttc_params)
587{
588 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
589 int tt;
590
591 memset(ttc_params, 0, sizeof(*ttc_params));
592
bc29764e
MG		 593 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
594 MLX5_FLOW_NAMESPACE_KERNEL);
595 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
596 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
597 ttc_params->dests[tt].tir_num =
598 tt == MLX5_TT_ANY ?
599 mlx5e_tir_get_tirn(&hp->direct_tir) :
600 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
601 }
3f6d08d1 602
3f6d08d1
OG		 603 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
604 ft_attr->prio = MLX5E_TC_PRIO;
605}
606
607static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
608{
609 struct mlx5e_priv *priv = hp->func_priv;
610 struct ttc_params ttc_params;
611 int err;
612
613 err = mlx5e_hairpin_create_indirect_rqt(hp);
614 if (err)
615 return err;
616
617 err = mlx5e_hairpin_create_indirect_tirs(hp);
618 if (err)
619 goto err_create_indirect_tirs;
620
621 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 622 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
623 if (IS_ERR(hp->ttc)) {
624 err = PTR_ERR(hp->ttc);
3f6d08d1 625 goto err_create_ttc_table;
f4b45940 626 }
3f6d08d1
OG		 627
628 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 629 hp->num_channels,
630 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 631
632 return 0;
633
634err_create_ttc_table:
635 mlx5e_hairpin_destroy_indirect_tirs(hp);
636err_create_indirect_tirs:
06e9f13a 637 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 638
639 return err;
640}
641
642static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
643{
f4b45940 644 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 645 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 646 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 647}
648
77ab67b7
OG		 649static struct mlx5e_hairpin *
650mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
651 int peer_ifindex)
652{
653 struct mlx5_core_dev *func_mdev, *peer_mdev;
654 struct mlx5e_hairpin *hp;
655 struct mlx5_hairpin *pair;
656 int err;
657
658 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
659 if (!hp)
660 return ERR_PTR(-ENOMEM);
661
662 func_mdev = priv->mdev;
663 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 664 if (IS_ERR(peer_mdev)) {
665 err = PTR_ERR(peer_mdev);
666 goto create_pair_err;
667 }
77ab67b7
OG		 668
669 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
670 if (IS_ERR(pair)) {
671 err = PTR_ERR(pair);
672 goto create_pair_err;
673 }
674 hp->pair = pair;
675 hp->func_mdev = func_mdev;
3f6d08d1
OG		 676 hp->func_priv = priv;
677 hp->num_channels = params->num_channels;
77ab67b7
OG		 678
679 err = mlx5e_hairpin_create_transport(hp);
680 if (err)
681 goto create_transport_err;
682
3f6d08d1
OG		 683 if (hp->num_channels > 1) {
684 err = mlx5e_hairpin_rss_init(hp);
685 if (err)
686 goto rss_init_err;
687 }
688
77ab67b7
OG		 689 return hp;
690
3f6d08d1
OG		 691rss_init_err:
692 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 693create_transport_err:
694 mlx5_core_hairpin_destroy(hp->pair);
695create_pair_err:
696 kfree(hp);
697 return ERR_PTR(err);
698}
699
700static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
701{
3f6d08d1
OG		 702 if (hp->num_channels > 1)
703 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 704 mlx5e_hairpin_destroy_transport(hp);
705 mlx5_core_hairpin_destroy(hp->pair);
706 kvfree(hp);
707}
708
106be53b
OG		 709static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
710{
711 return (peer_vhca_id << 16 | prio);
712}
713
5c65c564 714static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 715 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 716{
717 struct mlx5e_hairpin_entry *hpe;
106be53b 718 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 719
720 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 721 hairpin_hlist, hash_key) {
e4f9abbd
VB		 722 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
723 refcount_inc(&hpe->refcnt);
5c65c564 724 return hpe;
e4f9abbd 725 }
5c65c564
OG		 726 }
727
728 return NULL;
729}
730
e4f9abbd
VB		 731static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
732 struct mlx5e_hairpin_entry *hpe)
733{
734 /* no more hairpin flows for us, release the hairpin pair */
b32accda 735 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 736 return;
b32accda
VB		 737 hash_del(&hpe->hairpin_hlist);
738 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 739
db76ca24
VB		 740 if (!IS_ERR_OR_NULL(hpe->hp)) {
741 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
742 dev_name(hpe->hp->pair->peer_mdev->device));
743
744 mlx5e_hairpin_destroy(hpe->hp);
745 }
e4f9abbd
VB		 746
747 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 748 kfree(hpe);
749}
750
106be53b
OG		 751#define UNKNOWN_MATCH_PRIO 8
752
753static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 754 struct mlx5_flow_spec *spec, u8 *match_prio,
755 struct netlink_ext_ack *extack)
106be53b
OG		 756{
757 void *headers_c, *headers_v;
758 u8 prio_val, prio_mask = 0;
759 bool vlan_present;
760
761#ifdef CONFIG_MLX5_CORE_EN_DCB
762 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 763 NL_SET_ERR_MSG_MOD(extack,
764 "only PCP trust state supported for hairpin");
106be53b
OG		 765 return -EOPNOTSUPP;
766 }
767#endif
768 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
769 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
770
771 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
772 if (vlan_present) {
773 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
774 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
775 }
776
777 if (!vlan_present || !prio_mask) {
778 prio_val = UNKNOWN_MATCH_PRIO;
779 } else if (prio_mask != 0x7) {
e98bedf5
EB		 780 NL_SET_ERR_MSG_MOD(extack,
781 "masked priority match not supported for hairpin");
106be53b
OG		 782 return -EOPNOTSUPP;
783 }
784
785 *match_prio = prio_val;
786 return 0;
787}
788
5c65c564
OG		 789static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
790 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 791 struct mlx5e_tc_flow_parse_attr *parse_attr,
792 struct netlink_ext_ack *extack)
5c65c564 793{
98b66cb1 794 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 795 struct mlx5_hairpin_params params;
d8822868 796 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 797 struct mlx5e_hairpin_entry *hpe;
798 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 799 u64 link_speed64;
800 u32 link_speed;
106be53b 801 u8 match_prio;
d8822868 802 u16 peer_id;
5c65c564
OG		 803 int err;
804
d8822868 805 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 806 if (IS_ERR(peer_mdev)) {
807 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
808 return PTR_ERR(peer_mdev);
809 }
810
d8822868 811 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 812 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 813 return -EOPNOTSUPP;
814 }
815
d8822868 816 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 817 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
818 extack);
106be53b
OG		 819 if (err)
820 return err;
b32accda
VB		 821
822 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 823 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 824 if (hpe) {
825 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
826 wait_for_completion(&hpe->res_ready);
827
828 if (IS_ERR(hpe->hp)) {
829 err = -EREMOTEIO;
830 goto out_err;
831 }
5c65c564 832 goto attach_flow;
db76ca24 833 }
5c65c564
OG		 834
835 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 836 if (!hpe) {
db76ca24
VB		 837 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
838 return -ENOMEM;
b32accda 839 }
5c65c564 840
73edca73 841 spin_lock_init(&hpe->flows_lock);
5c65c564 842 INIT_LIST_HEAD(&hpe->flows);
db76ca24 843 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 844 hpe->peer_vhca_id = peer_id;
106be53b 845 hpe->prio = match_prio;
e4f9abbd 846 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 847 init_completion(&hpe->res_ready);
848
849 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
850 hash_hairpin_info(peer_id, match_prio));
851 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 852
6cdc686a 853 params.log_data_size = 16;
5c65c564
OG		 854 params.log_data_size = min_t(u8, params.log_data_size,
855 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
856 params.log_data_size = max_t(u8, params.log_data_size,
857 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 858
eb9180f7
OG		 859 params.log_num_packets = params.log_data_size -
860 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
861 params.log_num_packets = min_t(u8, params.log_num_packets,
862 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
863
864 params.q_counter = priv->q_counter;
3f6d08d1 865 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 866 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 867 link_speed = max_t(u32, link_speed, 50000);
868 link_speed64 = link_speed;
869 do_div(link_speed64, 50000);
870 params.num_channels = link_speed64;
871
5c65c564 872 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 873 hpe->hp = hp;
874 complete_all(&hpe->res_ready);
5c65c564
OG		 875 if (IS_ERR(hp)) {
876 err = PTR_ERR(hp);
db76ca24 877 goto out_err;
5c65c564
OG		 878 }
879
eb9180f7 880 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 881 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 882 dev_name(hp->pair->peer_mdev->device),
eb9180f7 883 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 884
5c65c564 885attach_flow:
3f6d08d1 886 if (hpe->hp->num_channels > 1) {
226f2ca3 887 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 888 flow->attr->nic_attr->hairpin_ft =
889 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 890 } else {
a6696735 891 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 892 }
b32accda 893
e4f9abbd 894 flow->hpe = hpe;
73edca73 895 spin_lock(&hpe->flows_lock);
5c65c564 896 list_add(&flow->hairpin, &hpe->flows);
73edca73 897 spin_unlock(&hpe->flows_lock);
3f6d08d1 898
5c65c564
OG		 899 return 0;
900
db76ca24
VB		 901out_err:
902 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 903 return err;
904}
905
906static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
907 struct mlx5e_tc_flow *flow)
908{
5a7e5bcb 909 /* flow wasn't fully initialized */
e4f9abbd 910 if (!flow->hpe)
5a7e5bcb
VB		 911 return;
912
73edca73 913 spin_lock(&flow->hpe->flows_lock);
5c65c564 914 list_del(&flow->hairpin);
73edca73
VB		 915 spin_unlock(&flow->hpe->flows_lock);
916
e4f9abbd
VB		 917 mlx5e_hairpin_put(priv, flow->hpe);
918 flow->hpe = NULL;
5c65c564
OG		 919}
920
08247066
AL		 921struct mlx5_flow_handle *
922mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
923 struct mlx5_flow_spec *spec,
c620b772 924 struct mlx5_flow_attr *attr)
e8f887ac 925{
08247066 926 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 927 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 928 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 929 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 930 struct mlx5_flow_destination dest[2] = {};
66958ed9 931 struct mlx5_flow_act flow_act = {
3bc4b7bf 932 .action = attr->action,
bb0ee7dc 933 .flags = FLOW_ACT_NO_APPEND,
66958ed9 934 };
08247066 935 struct mlx5_flow_handle *rule;
c7569097 936 struct mlx5_flow_table *ft;
08247066 937 int dest_ix = 0;
e8f887ac 938
bb0ee7dc 939 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 940 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 941
aedd133d
AL		 942 if (attr->dest_ft) {
943 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
944 dest[dest_ix].ft = attr->dest_ft;
945 dest_ix++;
946 } else if (nic_attr->hairpin_ft) {
08247066 947 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 948 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 949 dest_ix++;
c620b772 950 } else if (nic_attr->hairpin_tirn) {
08247066 951 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 952 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 953 dest_ix++;
3f6d08d1
OG		 954 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 956 if (attr->dest_chain) {
957 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
958 attr->dest_chain, 1,
959 MLX5E_TC_FT_LEVEL);
960 if (IS_ERR(dest[dest_ix].ft))
961 return ERR_CAST(dest[dest_ix].ft);
962 } else {
6783f0a2 963 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 964 }
3f6d08d1 965 dest_ix++;
5c65c564 966 }
aad7e08d 967
c7569097
AL		 968 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
969 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
970 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
971
08247066 972 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 973 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 974 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 975 dest_ix++;
aad7e08d
AV		 976 }
977
08247066 978 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 979 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 980
6a064674
AL		 981 mutex_lock(&tc->t_lock);
982 if (IS_ERR_OR_NULL(tc->t)) {
983 /* Create the root table here if doesn't exist yet */
984 tc->t =
c7569097 985 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 986
987 if (IS_ERR(tc->t)) {
988 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 989 netdev_err(priv->netdev,
990 "Failed to create tc offload table\n");
c7569097
AL		 991 rule = ERR_CAST(priv->fs.tc.t);
992 goto err_ft_get;
e8f887ac 993 }
e8f887ac 994 }
08247066 995 mutex_unlock(&tc->t_lock);
e8f887ac 996
aedd133d
AL		 997 if (attr->chain || attr->prio)
998 ft = mlx5_chains_get_table(nic_chains,
999 attr->chain, attr->prio,
1000 MLX5E_TC_FT_LEVEL);
1001 else
1002 ft = attr->ft;
1003
c7569097
AL		 1004 if (IS_ERR(ft)) {
1005 rule = ERR_CAST(ft);
1006 goto err_ft_get;
1007 }
1008
c620b772 1009 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1010 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1011
c7569097 1012 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1013 &flow_act, dest, dest_ix);
1014 if (IS_ERR(rule))
c7569097 1015 goto err_rule;
08247066
AL		 1016
1017 return rule;
c7569097
AL		 1018
1019err_rule:
aedd133d
AL		 1020 if (attr->chain || attr->prio)
1021 mlx5_chains_put_table(nic_chains,
1022 attr->chain, attr->prio,
1023 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1024err_ft_get:
1025 if (attr->dest_chain)
1026 mlx5_chains_put_table(nic_chains,
1027 attr->dest_chain, 1,
1028 MLX5E_TC_FT_LEVEL);
1029
1030 return ERR_CAST(rule);
08247066
AL		 1031}
1032
1033static int
1034mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1035 struct mlx5e_tc_flow *flow,
1036 struct netlink_ext_ack *extack)
1037{
c6cfe113 1038 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1039 struct mlx5_flow_attr *attr = flow->attr;
08247066 1040 struct mlx5_core_dev *dev = priv->mdev;
97a8d29a 1041 struct mlx5_fc *counter;
08247066
AL		 1042 int err;
1043
c6cfe113
RD		 1044 parse_attr = attr->parse_attr;
1045
08247066
AL		 1046 if (flow_flag_test(flow, HAIRPIN)) {
1047 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1048 if (err)
1049 return err;
1050 }
1051
1052 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1053 counter = mlx5_fc_create(dev, true);
1054 if (IS_ERR(counter))
1055 return PTR_ERR(counter);
1056
1057 attr->counter = counter;
1058 }
1059
1060 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1061 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1062 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1063 if (err)
1064 return err;
1065 }
1066
aedd133d
AL		 1067 if (flow_flag_test(flow, CT))
1068 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1069 attr, &parse_attr->mod_hdr_acts);
1070 else
1071 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1072 attr);
aad7e08d 1073
a2b7189b 1074 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1075}
1076
08247066 1077void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1078 struct mlx5_flow_handle *rule,
1079 struct mlx5_flow_attr *attr)
08247066 1080{
c7569097
AL		 1081 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1082
08247066 1083 mlx5_del_flow_rules(rule);
c7569097 1084
aedd133d
AL		 1085 if (attr->chain || attr->prio)
1086 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1087 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1088
1089 if (attr->dest_chain)
1090 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1091 MLX5E_TC_FT_LEVEL);
08247066
AL		 1092}
1093
d85cdccb
OG		 1094static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1095 struct mlx5e_tc_flow *flow)
1096{
c620b772 1097 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1098 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1099
c7569097
AL		 1100 flow_flag_clear(flow, OFFLOADED);
1101
aedd133d
AL		 1102 if (flow_flag_test(flow, CT))
1103 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1104 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1105 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1106
c7569097
AL		 1107 /* Remove root table if no rules are left to avoid
1108 * extra steering hops.
1109 */
b6fac0b4 1110 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1111 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1112 !IS_ERR_OR_NULL(tc->t)) {
1113 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1114 priv->fs.tc.t = NULL;
1115 }
b6fac0b4 1116 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1117
aedd133d
AL		 1118 kvfree(attr->parse_attr);
1119
513f8f7f 1120 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1121 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1122
aedd133d
AL		 1123 mlx5_fc_destroy(priv->mdev, attr->counter);
1124
226f2ca3 1125 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1126 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1127
1128 kfree(flow->attr);
d85cdccb
OG		 1129}
1130
0d9f9647 1131struct mlx5_flow_handle *
6d2a3ed0
OG		 1132mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1133 struct mlx5e_tc_flow *flow,
1134 struct mlx5_flow_spec *spec,
c620b772 1135 struct mlx5_flow_attr *attr)
6d2a3ed0 1136{
1ef3018f 1137 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1138 struct mlx5_flow_handle *rule;
4c3844d9 1139
89e39467
PB		 1140 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1141 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1142
1ef3018f
PB		 1143 if (flow_flag_test(flow, CT)) {
1144 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1145
69e2916e 1146 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1147 flow, spec, attr,
1ef3018f 1148 mod_hdr_acts);
f94d6389 1149 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1150 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1151 mlx5e_tc_get_flow_tun_id(flow));
69e2916e
PB		 1152 } else {
1153 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1154 }
6d2a3ed0 1155
6d2a3ed0
OG		 1156 if (IS_ERR(rule))
1157 return rule;
1158
c620b772 1159 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1160 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1161 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1162 if (flow_flag_test(flow, CT))
1163 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1164 else
1165 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1166 return flow->rule[1];
1167 }
1168 }
1169
6d2a3ed0
OG		 1170 return rule;
1171}
1172
0d9f9647
VB		 1173void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1174 struct mlx5e_tc_flow *flow,
1175 struct mlx5_flow_attr *attr)
6d2a3ed0 1176{
226f2ca3 1177 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1178
89e39467
PB		 1179 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1180 goto offload_rule_0;
1181
c620b772 1182 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1183 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1184
f7a6ab77
CM		 1185 if (flow_flag_test(flow, CT))
1186 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1187 else if (flow_flag_test(flow, SAMPLE))
1188 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
1189 else
89e39467 1190offload_rule_0:
f7a6ab77 1191 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
6d2a3ed0
OG		 1192}
1193
0d9f9647 1194struct mlx5_flow_handle *
5dbe906f
PB		 1195mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1196 struct mlx5e_tc_flow *flow,
178f69b4 1197 struct mlx5_flow_spec *spec)
5dbe906f 1198{
c620b772 1199 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1200 struct mlx5_flow_handle *rule;
1201
c620b772
AL		 1202 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1203 if (!slow_attr)
1204 return ERR_PTR(-ENOMEM);
5dbe906f 1205
c620b772
AL		 1206 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1207 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1208 slow_attr->esw_attr->split_count = 0;
1209 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1210
1211 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1212 if (!IS_ERR(rule))
226f2ca3 1213 flow_flag_set(flow, SLOW);
5dbe906f 1214
c620b772
AL		 1215 kfree(slow_attr);
1216
5dbe906f
PB		 1217 return rule;
1218}
1219
0d9f9647
VB		 1220void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1221 struct mlx5e_tc_flow *flow)
5dbe906f 1222{
c620b772 1223 struct mlx5_flow_attr *slow_attr;
178f69b4 1224
c620b772 1225 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1226 if (!slow_attr) {
1227 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1228 return;
1229 }
c620b772
AL		 1230
1231 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1232 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1233 slow_attr->esw_attr->split_count = 0;
1234 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1235 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1236 flow_flag_clear(flow, SLOW);
c620b772 1237 kfree(slow_attr);
5dbe906f
PB		 1238}
1239
ad86755b
VB		 1240/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1241 * function.
1242 */
1243static void unready_flow_add(struct mlx5e_tc_flow *flow,
1244 struct list_head *unready_flows)
1245{
1246 flow_flag_set(flow, NOT_READY);
1247 list_add_tail(&flow->unready, unready_flows);
1248}
1249
1250/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1251 * function.
1252 */
1253static void unready_flow_del(struct mlx5e_tc_flow *flow)
1254{
1255 list_del(&flow->unready);
1256 flow_flag_clear(flow, NOT_READY);
1257}
1258
b4a23329
RD		 1259static void add_unready_flow(struct mlx5e_tc_flow *flow)
1260{
1261 struct mlx5_rep_uplink_priv *uplink_priv;
1262 struct mlx5e_rep_priv *rpriv;
1263 struct mlx5_eswitch *esw;
1264
1265 esw = flow->priv->mdev->priv.eswitch;
1266 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1267 uplink_priv = &rpriv->uplink_priv;
1268
ad86755b
VB		 1269 mutex_lock(&uplink_priv->unready_flows_lock);
1270 unready_flow_add(flow, &uplink_priv->unready_flows);
1271 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1272}
1273
1274static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1275{
ad86755b
VB		 1276 struct mlx5_rep_uplink_priv *uplink_priv;
1277 struct mlx5e_rep_priv *rpriv;
1278 struct mlx5_eswitch *esw;
1279
1280 esw = flow->priv->mdev->priv.eswitch;
1281 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1282 uplink_priv = &rpriv->uplink_priv;
1283
1284 mutex_lock(&uplink_priv->unready_flows_lock);
1285 unready_flow_del(flow);
1286 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1287}
1288
10742efc
VB		 1289static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1290
a508728a 1291bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1292{
1293 struct mlx5_core_dev *out_mdev, *route_mdev;
1294 struct mlx5e_priv *out_priv, *route_priv;
1295
1296 out_priv = netdev_priv(out_dev);
1297 out_mdev = out_priv->mdev;
1298 route_priv = netdev_priv(route_dev);
1299 route_mdev = route_priv->mdev;
1300
1301 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1302 route_mdev->coredev_type != MLX5_COREDEV_VF)
1303 return false;
1304
1305 return same_hw_devs(out_priv, route_priv);
1306}
1307
a508728a 1308int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1309{
1310 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1311 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1312 struct mlx5_core_dev *route_mdev;
1313 struct mlx5_eswitch *esw;
1314 u16 vhca_id;
1315 int err;
1316
1317 out_priv = netdev_priv(out_dev);
1318 esw = out_priv->mdev->priv.eswitch;
1319 route_priv = netdev_priv(route_dev);
1320 route_mdev = route_priv->mdev;
1321
1322 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1323 if (mlx5_lag_is_active(out_priv->mdev)) {
1324 /* In lag case we may get devices from different eswitch instances.
1325 * If we failed to get vport num, it means, mostly, that we on the wrong
1326 * eswitch.
1327 */
1328 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1329 if (err != -ENOENT)
1330 return err;
1331
1332 devcom = out_priv->mdev->priv.devcom;
1333 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1334 if (!esw)
1335 return -ENODEV;
1336 }
1337
10742efc 1338 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1339 if (devcom)
1340 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1341 return err;
1342}
1343
c7b9038d
VB		 1344int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1345 struct mlx5e_tc_flow_parse_attr *parse_attr,
1346 struct mlx5e_tc_flow *flow)
1347{
1348 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1349 struct mlx5_modify_hdr *mod_hdr;
1350
1351 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1352 get_flow_name_space(flow),
1353 mod_hdr_acts->num_actions,
1354 mod_hdr_acts->actions);
1355 if (IS_ERR(mod_hdr))
1356 return PTR_ERR(mod_hdr);
1357
1358 WARN_ON(flow->attr->modify_hdr);
1359 flow->attr->modify_hdr = mod_hdr;
1360
1361 return 0;
1362}
1363
c83954ab 1364static int
74491de9 1365mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1366 struct mlx5e_tc_flow *flow,
1367 struct netlink_ext_ack *extack)
adb4c123
OG		 1368{
1369 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1370 struct mlx5e_tc_flow_parse_attr *parse_attr;
1371 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1372 bool vf_tun = false, encap_valid = true;
fe7738eb 1373 struct net_device *encap_dev = NULL;
c620b772 1374 struct mlx5_esw_flow_attr *esw_attr;
3c37745e
OG		 1375 struct mlx5e_rep_priv *rpriv;
1376 struct mlx5e_priv *out_priv;
97a8d29a 1377 struct mlx5_fc *counter;
39ac237c 1378 u32 max_prio, max_chain;
0ad060ee 1379 int err = 0;
f493f155 1380 int out_index;
8b32580d 1381
84179981
PB		 1382 /* We check chain range only for tc flows.
1383 * For ft flows, we checked attr->chain was originally 0 and set it to
1384 * FDB_FT_CHAIN which is outside tc range.
1385 * See mlx5e_rep_setup_ft_cb().
1386 */
ae430332 1387 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1388 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1389 NL_SET_ERR_MSG_MOD(extack,
1390 "Requested chain is out of supported range");
8914add2
VB		 1391 err = -EOPNOTSUPP;
1392 goto err_out;
bf07aa73
PB		 1393 }
1394
ae430332 1395 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1396 if (attr->prio > max_prio) {
61644c3d
RD		 1397 NL_SET_ERR_MSG_MOD(extack,
1398 "Requested priority is out of supported range");
8914add2
VB		 1399 err = -EOPNOTSUPP;
1400 goto err_out;
bf07aa73 1401 }
e52c2802 1402
777bb800
VB		 1403 if (flow_flag_test(flow, TUN_RX)) {
1404 err = mlx5e_attach_decap_route(priv, flow);
1405 if (err)
8914add2 1406 goto err_out;
777bb800
VB		 1407 }
1408
14e6b038
EC		 1409 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1410 err = mlx5e_attach_decap(priv, flow, extack);
1411 if (err)
8914add2 1412 goto err_out;
14e6b038
EC		 1413 }
1414
c620b772
AL		 1415 parse_attr = attr->parse_attr;
1416 esw_attr = attr->esw_attr;
1417
f493f155 1418 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1419 struct net_device *out_dev;
8c4dc42b
EB		 1420 int mirred_ifindex;
1421
c620b772 1422 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1423 continue;
1424
7040632d 1425 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1426 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1427 if (!out_dev) {
1428 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1429 err = -ENODEV;
1430 goto err_out;
1431 }
733d4f36 1432 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1433 extack, &encap_dev, &encap_valid);
fe7738eb 1434 dev_put(out_dev);
0ad060ee 1435 if (err)
8914add2 1436 goto err_out;
0ad060ee 1437
8914add2
VB		 1438 if (esw_attr->dests[out_index].flags &
1439 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1440 vf_tun = true;
3c37745e
OG		 1441 out_priv = netdev_priv(encap_dev);
1442 rpriv = out_priv->ppriv;
c620b772
AL		 1443 esw_attr->dests[out_index].rep = rpriv->rep;
1444 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1445 }
1446
7d1a3d08
VB		 1447 if (vf_tun && esw_attr->out_count > 1) {
1448 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1449 err = -EOPNOTSUPP;
1450 goto err_out;
1451 }
1452
8b32580d 1453 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1454 if (err)
8914add2 1455 goto err_out;
adb4c123 1456
d5a3c2b6
RD		 1457 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1458 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1459 if (vf_tun) {
1460 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1461 if (err)
1462 goto err_out;
1463 } else {
1464 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1465 if (err)
1466 goto err_out;
1467 }
d7e75a32
OG		 1468 }
1469
b8aee822 1470 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1471 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1472 if (IS_ERR(counter)) {
1473 err = PTR_ERR(counter);
1474 goto err_out;
1475 }
b8aee822
MB		 1476
1477 attr->counter = counter;
1478 }
1479
0ad060ee
RD		 1480 /* we get here if one of the following takes place:
1481 * (1) there's no error
1482 * (2) there's an encap action and we don't have valid neigh
3c37745e 1483 */
bc1d75fa 1484 if (!encap_valid)
178f69b4 1485 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1486 else
6d2a3ed0 1487 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1488
8914add2
VB		 1489 if (IS_ERR(flow->rule[0])) {
1490 err = PTR_ERR(flow->rule[0]);
1491 goto err_out;
1492 }
1493 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1494
1495 return 0;
8914add2
VB		 1496
1497err_out:
1498 flow_flag_set(flow, FAILED);
1499 return err;
aa0cbbae 1500}
d85cdccb 1501
9272e3df
YK		 1502static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1503{
c620b772 1504 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1505 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1506 spec->match_value,
1507 misc_parameters_3);
1508 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1509 headers_v,
1510 geneve_tlv_option_0_data);
1511
1512 return !!geneve_tlv_opt_0_data;
1513}
1514
d85cdccb
OG		 1515static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1516 struct mlx5e_tc_flow *flow)
1517{
1518 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1519 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1520 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1521 bool vf_tun = false;
f493f155 1522 int out_index;
d85cdccb 1523
777bb800 1524 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1525 mlx5e_put_flow_tunnel_id(flow);
1526
12a240a4 1527 if (flow_flag_test(flow, NOT_READY))
b4a23329 1528 remove_unready_flow(flow);
ef06c9ee 1529
226f2ca3
VB		 1530 if (mlx5e_is_offloaded_flow(flow)) {
1531 if (flow_flag_test(flow, SLOW))
178f69b4 1532 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1533 else
1534 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1535 }
909e615d 1536 complete_all(&flow->del_hw_done);
d85cdccb 1537
9272e3df
YK		 1538 if (mlx5_flow_has_geneve_opt(flow))
1539 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1540
513f8f7f 1541 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1542
777bb800
VB		 1543 if (flow->decap_route)
1544 mlx5e_detach_decap_route(priv, flow);
1545
1546 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1547 if (esw_attr->dests[out_index].flags &
1548 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1549 vf_tun = true;
777bb800 1550 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1551 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1552 kfree(attr->parse_attr->tun_info[out_index]);
1553 }
777bb800 1554 }
d7e75a32 1555
aedd133d 1556 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1557
c7b9038d
VB		 1558 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1559 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1560 if (vf_tun && attr->modify_hdr)
1561 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1562 else
1563 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1564 }
bcd6740c 1565 kfree(attr->sample_attr);
8914add2
VB		 1566 kvfree(attr->parse_attr);
1567 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1568
1569 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1570 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1571
1572 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1573 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1574
1575 kfree(flow->attr);
d85cdccb
OG		 1576}
1577
0d9f9647 1578struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1579{
c620b772 1580 return flow->attr->counter;
b8aee822
MB		 1581}
1582
6a06c2f7 1583/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1584void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1585{
1586 struct mlx5e_tc_flow *flow, *tmp;
1587
1588 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1589 mlx5e_flow_put(priv, flow);
1590}
1591
04de7dda
RD		 1592static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1593{
1594 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1595
226f2ca3
VB		 1596 if (!flow_flag_test(flow, ESWITCH) ||
1597 !flow_flag_test(flow, DUP))
04de7dda
RD		 1598 return;
1599
1600 mutex_lock(&esw->offloads.peer_mutex);
1601 list_del(&flow->peer);
1602 mutex_unlock(&esw->offloads.peer_mutex);
1603
226f2ca3 1604 flow_flag_clear(flow, DUP);
04de7dda 1605
eb252c3a
RD		 1606 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1607 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1608 kfree(flow->peer_flow);
1609 }
1610
04de7dda
RD		 1611 flow->peer_flow = NULL;
1612}
1613
1614static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1615{
1616 struct mlx5_core_dev *dev = flow->priv->mdev;
1617 struct mlx5_devcom *devcom = dev->priv.devcom;
1618 struct mlx5_eswitch *peer_esw;
1619
1620 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1621 if (!peer_esw)
1622 return;
1623
1624 __mlx5e_tc_del_fdb_peer_flow(flow);
1625 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1626}
1627
e8f887ac 1628static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1629 struct mlx5e_tc_flow *flow)
e8f887ac 1630{
226f2ca3 1631 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1632 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1633 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1634 } else {
d85cdccb 1635 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1636 }
e8f887ac
AV		 1637}
1638
ee950e5d 1639static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1640{
1641 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1642 struct flow_action *flow_action = &rule->action;
1643 const struct flow_action_entry *act;
1644 int i;
1645
ee950e5d
CM		 1646 if (chain)
1647 return false;
1648
0a7fcb78
PB		 1649 flow_action_for_each(i, act, flow_action) {
1650 switch (act->id) {
1651 case FLOW_ACTION_GOTO:
1652 return true;
ee950e5d
CM		 1653 case FLOW_ACTION_SAMPLE:
1654 return true;
0a7fcb78
PB		 1655 default:
1656 continue;
1657 }
1658 }
1659
1660 return false;
1661}
bbd00f7e 1662
0a7fcb78
PB		 1663static int
1664enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1665 struct flow_dissector_key_enc_opts *opts,
1666 struct netlink_ext_ack *extack,
1667 bool *dont_care)
1668{
1669 struct geneve_opt *opt;
1670 int off = 0;
1671
1672 *dont_care = true;
1673
1674 while (opts->len > off) {
1675 opt = (struct geneve_opt *)&opts->data[off];
1676
1677 if (!(*dont_care) || opt->opt_class || opt->type ||
1678 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1679 *dont_care = false;
1680
c51323ee 1681 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1682 opt->type != U8_MAX) {
0a7fcb78
PB		 1683 NL_SET_ERR_MSG(extack,
1684 "Partial match of tunnel options in chain > 0 isn't supported");
1685 netdev_warn(priv->netdev,
1686 "Partial match of tunnel options in chain > 0 isn't supported");
1687 return -EOPNOTSUPP;
1688 }
1689 }
1690
1691 off += sizeof(struct geneve_opt) + opt->length * 4;
1692 }
1693
1694 return 0;
1695}
1696
1697#define COPY_DISSECTOR(rule, diss_key, dst)\
1698({ \
1699 struct flow_rule *__rule = (rule);\
1700 typeof(dst) __dst = dst;\
1701\
1702 memcpy(__dst,\
1703 skb_flow_dissector_target(__rule->match.dissector,\
1704 diss_key,\
1705 __rule->match.key),\
1706 sizeof(*__dst));\
1707})
1708
1709static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1710 struct mlx5e_tc_flow *flow,
1711 struct flow_cls_offload *f,
1712 struct net_device *filter_dev)
bbd00f7e 1713{
f9e30088 1714 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1715 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1716 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1717 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1718 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1719 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1720 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1721 struct mlx5e_rep_priv *uplink_rpriv;
1722 struct tunnel_match_key tunnel_key;
1723 bool enc_opts_is_dont_care = true;
1724 u32 tun_id, enc_opts_id = 0;
1725 struct mlx5_eswitch *esw;
1726 u32 value, mask;
8f256622 1727 int err;
2e72eb43 1728
0a7fcb78
PB		 1729 esw = priv->mdev->priv.eswitch;
1730 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1731 uplink_priv = &uplink_rpriv->uplink_priv;
1732
1733 memset(&tunnel_key, 0, sizeof(tunnel_key));
1734 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1735 &tunnel_key.enc_control);
1736 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1737 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1738 &tunnel_key.enc_ipv4);
1739 else
1740 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1741 &tunnel_key.enc_ipv6);
1742 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1743 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1744 &tunnel_key.enc_tp);
1745 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1746 &tunnel_key.enc_key_id);
1747 tunnel_key.filter_ifindex = filter_dev->ifindex;
1748
1749 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1750 if (err)
101f4de9 1751 return err;
bbd00f7e 1752
0a7fcb78
PB		 1753 flow_rule_match_enc_opts(rule, &enc_opts_match);
1754 err = enc_opts_is_dont_care_or_full_match(priv,
1755 enc_opts_match.mask,
1756 extack,
1757 &enc_opts_is_dont_care);
1758 if (err)
1759 goto err_enc_opts;
fe1587a7 1760
0a7fcb78 1761 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1762 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1763 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1764 sizeof(*enc_opts_match.key));
1765 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1766 sizeof(*enc_opts_match.mask));
1767
0a7fcb78 1768 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1769 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1770 if (err)
1771 goto err_enc_opts;
1772 }
fe1587a7 1773
0a7fcb78
PB		 1774 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1775 mask = enc_opts_id ? TUNNEL_ID_MASK :
1776 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1777
0a7fcb78
PB		 1778 if (attr->chain) {
1779 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1780 TUNNEL_TO_REG, value, mask);
1781 } else {
1782 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1783 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1784 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1785 TUNNEL_TO_REG, value);
1786 if (err)
1787 goto err_set;
fe1587a7 1788
0a7fcb78 1789 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1790 }
bbd00f7e 1791
0a7fcb78
PB		 1792 flow->tunnel_id = value;
1793 return 0;
bcef735c 1794
0a7fcb78
PB		 1795err_set:
1796 if (enc_opts_id)
1797 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1798 enc_opts_id);
1799err_enc_opts:
1800 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1801 return err;
1802}
bcef735c 1803
0a7fcb78
PB		 1804static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1805{
1806 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1807 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1808 struct mlx5_rep_uplink_priv *uplink_priv;
1809 struct mlx5e_rep_priv *uplink_rpriv;
1810 struct mlx5_eswitch *esw;
bcef735c 1811
0a7fcb78
PB		 1812 esw = flow->priv->mdev->priv.eswitch;
1813 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1814 uplink_priv = &uplink_rpriv->uplink_priv;
1815
1816 if (tun_id)
1817 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1818 if (enc_opts_id)
1819 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1820 enc_opts_id);
1821}
e98bedf5 1822
4c3844d9
PB		 1823u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1824{
1825 return flow->tunnel_id;
1826}
1827
fca53304
EB		 1828void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1829 struct flow_match_basic *match, bool outer,
1830 void *headers_c, void *headers_v)
1831{
1832 bool ip_version_cap;
1833
1834 ip_version_cap = outer ?
1835 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1836 ft_field_support.outer_ip_version) :
1837 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1838 ft_field_support.inner_ip_version);
1839
1840 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1841 (match->key->n_proto == htons(ETH_P_IP) ||
1842 match->key->n_proto == htons(ETH_P_IPV6))) {
1843 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1844 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1845 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1846 } else {
1847 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1848 ntohs(match->mask->n_proto));
1849 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1850 ntohs(match->key->n_proto));
1851 }
4a5d5d73
EB		 1852}
1853
0d9f9647 1854u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1855{
1856 void *headers_v;
1857 u16 ethertype;
1858 u8 ip_version;
1859
1860 if (outer)
1861 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1862 else
1863 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1864
1865 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1866 /* Return ip_version converted from ethertype anyway */
1867 if (!ip_version) {
1868 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1869 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1870 ip_version = 4;
1871 else if (ethertype == ETH_P_IPV6)
1872 ip_version = 6;
1873 }
1874 return ip_version;
1875}
1876
9bef4eea
PB		 1877/* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
1878 * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
1879 * +---------+----------------------------------------+
1880 * |Arriving | Arriving Outer Header |
1881 * | Inner +---------+---------+---------+----------+
1882 * | Header | Not-ECT | ECT(0) | ECT(1) | CE |
1883 * +---------+---------+---------+---------+----------+
1884 * | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop> |
1885 * | ECT(0) | ECT(0) | ECT(0) | ECT(1) | CE* |
1886 * | ECT(1) | ECT(1) | ECT(1) | ECT(1)* | CE* |
1887 * | CE | CE | CE | CE | CE |
1888 * +---------+---------+---------+---------+----------+
1889 *
1890 * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
1891 * the inner ip_ecn value before hardware decap action.
1892 *
1893 * Cells marked are changed from original inner packet ip_ecn value during decap, and
1894 * so matching those values on inner ip_ecn before decap will fail.
1895 *
1896 * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
1897 * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
1898 * and such we can drop the inner ip_ecn=CE match.
1899 */
1900
1901static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
1902 struct flow_cls_offload *f,
1903 bool *match_inner_ecn)
1904{
1905 u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
1906 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1907 struct netlink_ext_ack *extack = f->common.extack;
1908 struct flow_match_ip match;
1909
1910 *match_inner_ecn = true;
1911
1912 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1913 flow_rule_match_enc_ip(rule, &match);
1914 outer_ecn_key = match.key->tos & INET_ECN_MASK;
1915 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
1916 }
1917
1918 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1919 flow_rule_match_ip(rule, &match);
1920 inner_ecn_key = match.key->tos & INET_ECN_MASK;
1921 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
1922 }
1923
1924 if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
1925 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
1926 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
1927 return -EOPNOTSUPP;
1928 }
1929
1930 if (!outer_ecn_mask) {
1931 if (!inner_ecn_mask)
1932 return 0;
1933
1934 NL_SET_ERR_MSG_MOD(extack,
1935 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
1936 netdev_warn(priv->netdev,
1937 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
1938 return -EOPNOTSUPP;
1939 }
1940
1941 if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
1942 NL_SET_ERR_MSG_MOD(extack,
1943 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
1944 netdev_warn(priv->netdev,
1945 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
1946 return -EOPNOTSUPP;
1947 }
1948
1949 if (!inner_ecn_mask)
1950 return 0;
1951
1952 /* Both inner and outer have full mask on ecn */
1953
1954 if (outer_ecn_key == INET_ECN_ECT_1) {
1955 /* inner ecn might change by DECAP action */
1956
1957 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
1958 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
1959 return -EOPNOTSUPP;
1960 }
1961
1962 if (outer_ecn_key != INET_ECN_CE)
1963 return 0;
1964
1965 if (inner_ecn_key != INET_ECN_CE) {
1966 /* Can't happen in software, as packet ecn will be changed to CE after decap */
1967 NL_SET_ERR_MSG_MOD(extack,
1968 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
1969 netdev_warn(priv->netdev,
1970 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
1971 return -EOPNOTSUPP;
1972 }
1973
1974 /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
1975 * drop match on inner ecn
1976 */
1977 *match_inner_ecn = false;
1978
1979 return 0;
1980}
1981
bbd00f7e 1982static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1983 struct mlx5e_tc_flow *flow,
bbd00f7e 1984 struct mlx5_flow_spec *spec,
f9e30088 1985 struct flow_cls_offload *f,
0a7fcb78
PB		 1986 struct net_device *filter_dev,
1987 u8 *match_level,
1988 bool *match_inner)
bbd00f7e 1989{
a508728a 1990 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1991 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1992 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1993 bool needs_mapping, sets_mapping;
8f256622 1994 int err;
2e72eb43 1995
0a7fcb78
PB		 1996 if (!mlx5e_is_eswitch_flow(flow))
1997 return -EOPNOTSUPP;
1998
c620b772 1999 needs_mapping = !!flow->attr->chain;
ee950e5d 2000 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 2001 *match_inner = !needs_mapping;
2002
2003 if ((needs_mapping || sets_mapping) &&
636bb968 2004 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 2005 NL_SET_ERR_MSG(extack,
636bb968 2006 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2007 netdev_warn(priv->netdev,
636bb968 2008 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2009 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2010 }
2011
c620b772 2012 if (!flow->attr->chain) {
0a7fcb78
PB		 2013 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2014 match_level);
2015 if (err) {
e98bedf5 2016 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2017 "Failed to parse tunnel attributes");
2018 netdev_warn(priv->netdev,
2019 "Failed to parse tunnel attributes");
2020 return err;
e98bedf5
EB		 2021 }
2022
14e6b038
EC		 2023 /* With mpls over udp we decapsulate using packet reformat
2024 * object
2025 */
2026 if (!netif_is_bareudp(filter_dev))
c620b772 2027 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 2028 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2029 if (err)
2030 return err;
2031 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
2032 struct mlx5_flow_spec *tmp_spec;
2033
2034 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2035 if (!tmp_spec) {
2036 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
2037 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
2038 return -ENOMEM;
2039 }
2040 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2041
2042 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2043 if (err) {
2044 kvfree(tmp_spec);
2045 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2046 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2047 return err;
2048 }
2049 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2050 kvfree(tmp_spec);
2051 if (err)
2052 return err;
bcef735c
OG		 2053 }
2054
0a7fcb78
PB		 2055 if (!needs_mapping && !sets_mapping)
2056 return 0;
bbd00f7e 2057
0a7fcb78 2058 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2059}
bbd00f7e 2060
0a7fcb78 2061static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2062{
0a7fcb78
PB		 2063 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2064 inner_headers);
bbd00f7e
HHZ		 2065}
2066
0a7fcb78 2067static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2068{
0a7fcb78
PB		 2069 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2070 inner_headers);
2071}
2072
2073static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2074{
2075 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2076 outer_headers);
2077}
2078
2079static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2080{
2081 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2082 outer_headers);
8377629e
EB		 2083}
2084
2085static void *get_match_headers_value(u32 flags,
2086 struct mlx5_flow_spec *spec)
2087{
2088 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2089 get_match_inner_headers_value(spec) :
2090 get_match_outer_headers_value(spec);
2091}
2092
2093static void *get_match_headers_criteria(u32 flags,
2094 struct mlx5_flow_spec *spec)
2095{
2096 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2097 get_match_inner_headers_criteria(spec) :
2098 get_match_outer_headers_criteria(spec);
8377629e
EB		 2099}
2100
6d65bc64 2101static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2102 struct flow_cls_offload *f)
2103{
2104 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2105 struct netlink_ext_ack *extack = f->common.extack;
2106 struct net_device *ingress_dev;
2107 struct flow_match_meta match;
2108
2109 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2110 return 0;
2111
2112 flow_rule_match_meta(rule, &match);
e3e0f9b2 2113 if (!match.mask->ingress_ifindex)
2114 return 0;
2115
6d65bc64 2116 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2117 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2118 return -EOPNOTSUPP;
6d65bc64 2119 }
2120
2121 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2122 match.key->ingress_ifindex);
2123 if (!ingress_dev) {
2124 NL_SET_ERR_MSG_MOD(extack,
2125 "Can't find the ingress port to match on");
a683012a 2126 return -ENOENT;
6d65bc64 2127 }
2128
2129 if (ingress_dev != filter_dev) {
2130 NL_SET_ERR_MSG_MOD(extack,
2131 "Can't match on the ingress filter port");
a683012a 2132 return -EOPNOTSUPP;
6d65bc64 2133 }
2134
2135 return 0;
2136}
2137
72046a91
EC		 2138static bool skip_key_basic(struct net_device *filter_dev,
2139 struct flow_cls_offload *f)
2140{
2141 /* When doing mpls over udp decap, the user needs to provide
2142 * MPLS_UC as the protocol in order to be able to match on mpls
2143 * label fields. However, the actual ethertype is IP so we want to
2144 * avoid matching on this, otherwise we'll fail the match.
2145 */
2146 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2147 return true;
2148
2149 return false;
2150}
2151
de0af0bf 2152static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2153 struct mlx5e_tc_flow *flow,
de0af0bf 2154 struct mlx5_flow_spec *spec,
f9e30088 2155 struct flow_cls_offload *f,
54c177ca 2156 struct net_device *filter_dev,
93b3586e 2157 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2158{
e98bedf5 2159 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2160 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2161 outer_headers);
2162 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2163 outer_headers);
699e96dd
JL		 2164 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2165 misc_parameters);
2166 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2167 misc_parameters);
a3222a2d
MD		 2168 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2169 misc_parameters_3);
2170 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2171 misc_parameters_3);
f9e30088 2172 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2173 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2174 enum fs_flow_table_type fs_type;
9bef4eea 2175 bool match_inner_ecn = true;
e3a2b7ed
AV		 2176 u16 addr_type = 0;
2177 u8 ip_proto = 0;
93b3586e 2178 u8 *match_level;
6d65bc64 2179 int err;
e3a2b7ed 2180
afe93f71 2181 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2182 match_level = outer_match_level;
de0af0bf 2183
8f256622 2184 if (dissector->used_keys &
3d144578
VB		 2185 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2186 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2187 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2188 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2189 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2190 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2191 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2192 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2193 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2194 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2195 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2196 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2197 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2198 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2199 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2200 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2201 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2202 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2203 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2204 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2205 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2206 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2207 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2208 dissector->used_keys);
e3a2b7ed
AV		 2209 return -EOPNOTSUPP;
2210 }
2211
075973c7 2212 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2213 bool match_inner = false;
bbd00f7e 2214
0a7fcb78
PB		 2215 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2216 outer_match_level, &match_inner);
2217 if (err)
2218 return err;
2219
2220 if (match_inner) {
2221 /* header pointers should point to the inner headers
2222 * if the packet was decapsulated already.
2223 * outer headers are set by parse_tunnel_attr.
2224 */
2225 match_level = inner_match_level;
2226 headers_c = get_match_inner_headers_criteria(spec);
2227 headers_v = get_match_inner_headers_value(spec);
2228 }
9bef4eea
PB		 2229
2230 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2231 if (err)
2232 return err;
bbd00f7e
HHZ		 2233 }
2234
6d65bc64 2235 err = mlx5e_flower_parse_meta(filter_dev, f);
2236 if (err)
2237 return err;
2238
72046a91
EC		 2239 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2240 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2241 struct flow_match_basic match;
2242
2243 flow_rule_match_basic(rule, &match);
fca53304
EB		 2244 mlx5e_tc_set_ethertype(priv->mdev, &match,
2245 match_level == outer_match_level,
2246 headers_c, headers_v);
e3a2b7ed 2247
8f256622 2248 if (match.mask->n_proto)
d708f902 2249 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2250 }
35a605db
EB		 2251 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2252 is_vlan_dev(filter_dev)) {
2253 struct flow_dissector_key_vlan filter_dev_mask;
2254 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2255 struct flow_match_vlan match;
2256
35a605db
EB		 2257 if (is_vlan_dev(filter_dev)) {
2258 match.key = &filter_dev_key;
2259 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2260 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2261 match.key->vlan_priority = 0;
2262 match.mask = &filter_dev_mask;
2263 memset(match.mask, 0xff, sizeof(*match.mask));
2264 match.mask->vlan_priority = 0;
2265 } else {
2266 flow_rule_match_vlan(rule, &match);
2267 }
8f256622
PNA		 2268 if (match.mask->vlan_id ||
2269 match.mask->vlan_priority ||
2270 match.mask->vlan_tpid) {
2271 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2272 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2273 svlan_tag, 1);
2274 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2275 svlan_tag, 1);
2276 } else {
2277 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2278 cvlan_tag, 1);
2279 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2280 cvlan_tag, 1);
2281 }
095b6cfd 2282
8f256622
PNA		 2283 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2284 match.mask->vlan_id);
2285 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2286 match.key->vlan_id);
358d79a4 2287
8f256622
PNA		 2288 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2289 match.mask->vlan_priority);
2290 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2291 match.key->vlan_priority);
54782900 2292
d708f902 2293 *match_level = MLX5_MATCH_L2;
54782900 2294 }
d3a80bb5 2295 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2296 /* cvlan_tag enabled in match criteria and
2297 * disabled in match value means both S & C tags
2298 * don't exist (untagged of both)
2299 */
cee26487 2300 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2301 *match_level = MLX5_MATCH_L2;
54782900
OG		 2302 }
2303
8f256622
PNA		 2304 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2305 struct flow_match_vlan match;
2306
12d5cbf8 2307 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2308 if (match.mask->vlan_id ||
2309 match.mask->vlan_priority ||
2310 match.mask->vlan_tpid) {
afe93f71
RD		 2311 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2312 fs_type)) {
2313 NL_SET_ERR_MSG_MOD(extack,
2314 "Matching on CVLAN is not supported");
2315 return -EOPNOTSUPP;
2316 }
2317
8f256622 2318 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2319 MLX5_SET(fte_match_set_misc, misc_c,
2320 outer_second_svlan_tag, 1);
2321 MLX5_SET(fte_match_set_misc, misc_v,
2322 outer_second_svlan_tag, 1);
2323 } else {
2324 MLX5_SET(fte_match_set_misc, misc_c,
2325 outer_second_cvlan_tag, 1);
2326 MLX5_SET(fte_match_set_misc, misc_v,
2327 outer_second_cvlan_tag, 1);
2328 }
2329
2330 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2331 match.mask->vlan_id);
699e96dd 2332 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2333 match.key->vlan_id);
699e96dd 2334 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2335 match.mask->vlan_priority);
699e96dd 2336 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2337 match.key->vlan_priority);
699e96dd
JL		 2338
2339 *match_level = MLX5_MATCH_L2;
0faddfe6 2340 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2341 }
2342 }
2343
8f256622
PNA		 2344 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2345 struct flow_match_eth_addrs match;
54782900 2346
8f256622 2347 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2348 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2349 dmac_47_16),
8f256622 2350 match.mask->dst);
d3a80bb5
OG		 2351 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2352 dmac_47_16),
8f256622 2353 match.key->dst);
d3a80bb5
OG		 2354
2355 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2356 smac_47_16),
8f256622 2357 match.mask->src);
d3a80bb5
OG		 2358 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2359 smac_47_16),
8f256622 2360 match.key->src);
d3a80bb5 2361
8f256622
PNA		 2362 if (!is_zero_ether_addr(match.mask->src) ||
2363 !is_zero_ether_addr(match.mask->dst))
d708f902 2364 *match_level = MLX5_MATCH_L2;
54782900
OG		 2365 }
2366
8f256622
PNA		 2367 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2368 struct flow_match_control match;
54782900 2369
8f256622
PNA		 2370 flow_rule_match_control(rule, &match);
2371 addr_type = match.key->addr_type;
54782900
OG		 2372
2373 /* the HW doesn't support frag first/later */
8f256622 2374 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2375 return -EOPNOTSUPP;
2376
8f256622 2377 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2378 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2380 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2381
2382 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2383 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2384 *match_level = MLX5_MATCH_L2;
54782900
OG		 2385 /* *** L2 attributes parsing up to here *** */
2386 else
83621b7d 2387 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2388 }
2389 }
2390
8f256622
PNA		 2391 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2392 struct flow_match_basic match;
2393
2394 flow_rule_match_basic(rule, &match);
2395 ip_proto = match.key->ip_proto;
54782900
OG		 2396
2397 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2398 match.mask->ip_proto);
54782900 2399 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2400 match.key->ip_proto);
54782900 2401
8f256622 2402 if (match.mask->ip_proto)
d708f902 2403 *match_level = MLX5_MATCH_L3;
54782900
OG		 2404 }
2405
e3a2b7ed 2406 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2407 struct flow_match_ipv4_addrs match;
e3a2b7ed 2408
8f256622 2409 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2410 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2411 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2412 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2413 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2414 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2415 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2416 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2417 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2418 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2419 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2420 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2421 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2422
8f256622 2423 if (match.mask->src || match.mask->dst)
d708f902 2424 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2425 }
2426
2427 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2428 struct flow_match_ipv6_addrs match;
e3a2b7ed 2429
8f256622 2430 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2431 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2432 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2433 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2434 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2435 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2436 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2437
2438 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2439 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2440 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2441 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2442 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2443 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2444
8f256622
PNA		 2445 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2446 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2447 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2448 }
2449
8f256622
PNA		 2450 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2451 struct flow_match_ip match;
1f97a526 2452
8f256622 2453 flow_rule_match_ip(rule, &match);
9bef4eea
PB		 2454 if (match_inner_ecn) {
2455 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2456 match.mask->tos & 0x3);
2457 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2458 match.key->tos & 0x3);
2459 }
1f97a526 2460
8f256622
PNA		 2461 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2462 match.mask->tos >> 2);
2463 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2464 match.key->tos >> 2);
1f97a526 2465
8f256622
PNA		 2466 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2467 match.mask->ttl);
2468 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2469 match.key->ttl);
1f97a526 2470
8f256622 2471 if (match.mask->ttl &&
a8ade55f 2472 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2473 ft_field_support.outer_ipv4_ttl)) {
2474 NL_SET_ERR_MSG_MOD(extack,
2475 "Matching on TTL is not supported");
1f97a526 2476 return -EOPNOTSUPP;
e98bedf5 2477 }
a8ade55f 2478
8f256622 2479 if (match.mask->tos || match.mask->ttl)
d708f902 2480 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2481 }
2482
54782900
OG		 2483 /* *** L3 attributes parsing up to here *** */
2484
8f256622
PNA		 2485 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2486 struct flow_match_ports match;
2487
2488 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2489 switch (ip_proto) {
2490 case IPPROTO_TCP:
2491 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2492 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2493 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2494 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2495
2496 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2497 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2498 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2499 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2500 break;
2501
2502 case IPPROTO_UDP:
2503 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2504 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2505 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2506 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2507
2508 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2509 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2510 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2511 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2512 break;
2513 default:
e98bedf5
EB		 2514 NL_SET_ERR_MSG_MOD(extack,
2515 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2516 netdev_err(priv->netdev,
2517 "Only UDP and TCP transport are supported\n");
2518 return -EINVAL;
2519 }
de0af0bf 2520
8f256622 2521 if (match.mask->src || match.mask->dst)
d708f902 2522 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2523 }
2524
8f256622
PNA		 2525 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2526 struct flow_match_tcp match;
e77834ec 2527
8f256622 2528 flow_rule_match_tcp(rule, &match);
e77834ec 2529 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2530 ntohs(match.mask->flags));
e77834ec 2531 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2532 ntohs(match.key->flags));
e77834ec 2533
8f256622 2534 if (match.mask->flags)
d708f902 2535 *match_level = MLX5_MATCH_L4;
e77834ec 2536 }
a3222a2d
MD		 2537 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2538 struct flow_match_icmp match;
e77834ec 2539
a3222a2d
MD		 2540 flow_rule_match_icmp(rule, &match);
2541 switch (ip_proto) {
2542 case IPPROTO_ICMP:
2543 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2544 MLX5_FLEX_PROTO_ICMP))
2545 return -EOPNOTSUPP;
2546 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2547 match.mask->type);
2548 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2549 match.key->type);
2550 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2551 match.mask->code);
2552 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2553 match.key->code);
2554 break;
2555 case IPPROTO_ICMPV6:
2556 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2557 MLX5_FLEX_PROTO_ICMPV6))
2558 return -EOPNOTSUPP;
2559 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2560 match.mask->type);
2561 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2562 match.key->type);
2563 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2564 match.mask->code);
2565 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2566 match.key->code);
2567 break;
2568 default:
2569 NL_SET_ERR_MSG_MOD(extack,
2570 "Code and type matching only with ICMP and ICMPv6");
2571 netdev_err(priv->netdev,
2572 "Code and type matching only with ICMP and ICMPv6\n");
2573 return -EINVAL;
2574 }
2575 if (match.mask->code || match.mask->type) {
2576 *match_level = MLX5_MATCH_L4;
2577 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2578 }
2579 }
39c538d6 2580 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2581 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2582 !netif_is_bareudp(filter_dev)) {
2583 NL_SET_ERR_MSG_MOD(extack,
2584 "Matching on MPLS is supported only for MPLS over UDP");
2585 netdev_err(priv->netdev,
2586 "Matching on MPLS is supported only for MPLS over UDP\n");
2587 return -EOPNOTSUPP;
2588 }
2589
e3a2b7ed
AV		 2590 return 0;
2591}
2592
de0af0bf 2593static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2594 struct mlx5e_tc_flow *flow,
de0af0bf 2595 struct mlx5_flow_spec *spec,
f9e30088 2596 struct flow_cls_offload *f,
54c177ca 2597 struct net_device *filter_dev)
de0af0bf 2598{
93b3586e 2599 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2600 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2601 struct mlx5_core_dev *dev = priv->mdev;
2602 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2603 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2604 struct mlx5_eswitch_rep *rep;
226f2ca3 2605 bool is_eswitch_flow;
de0af0bf
RD		 2606 int err;
2607
93b3586e
HN		 2608 inner_match_level = MLX5_MATCH_NONE;
2609 outer_match_level = MLX5_MATCH_NONE;
2610
0a7fcb78
PB		 2611 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2612 &inner_match_level, &outer_match_level);
93b3586e
HN		 2613 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2614 outer_match_level : inner_match_level;
de0af0bf 2615
226f2ca3
VB		 2616 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2617 if (!err && is_eswitch_flow) {
1d447a39 2618 rep = rpriv->rep;
b05af6aa 2619 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2620 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2621 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2622 NL_SET_ERR_MSG_MOD(extack,
2623 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2624 netdev_warn(priv->netdev,
2625 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2626 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2627 return -EOPNOTSUPP;
2628 }
2629 }
2630
c620b772
AL		 2631 flow->attr->inner_match_level = inner_match_level;
2632 flow->attr->outer_match_level = outer_match_level;
2633
38aa51c1 2634
de0af0bf
RD		 2635 return err;
2636}
2637
d79b6df6
OG		 2638struct pedit_headers {
2639 struct ethhdr eth;
0eb69bb9 2640 struct vlan_hdr vlan;
d79b6df6
OG		 2641 struct iphdr ip4;
2642 struct ipv6hdr ip6;
2643 struct tcphdr tcp;
2644 struct udphdr udp;
2645};
2646
c500c86b
PNA		 2647struct pedit_headers_action {
2648 struct pedit_headers vals;
2649 struct pedit_headers masks;
2650 u32 pedits;
2651};
2652
d79b6df6 2653static int pedit_header_offsets[] = {
73867881
PNA		 2654 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2655 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2656 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2657 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2658 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2659};
2660
2661#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2662
2663static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2664 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2665{
2666 u32 *curr_pmask, *curr_pval;
2667
c500c86b
PNA		 2668 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2669 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2670
2671 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2672 goto out_err;
2673
2674 *curr_pmask |= mask;
2675 *curr_pval |= (val & mask);
2676
2677 return 0;
2678
2679out_err:
2680 return -EOPNOTSUPP;
2681}
2682
2683struct mlx5_fields {
2684 u8 field;
88f30bbc
DL		 2685 u8 field_bsize;
2686 u32 field_mask;
d79b6df6 2687 u32 offset;
27c11b6b 2688 u32 match_offset;
d79b6df6
OG		 2689};
2690
88f30bbc
DL		 2691#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2692 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2693 offsetof(struct pedit_headers, field) + (off), \
2694 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2695
2ef86872
EB		 2696/* masked values are the same and there are no rewrites that do not have a
2697 * match.
2698 */
2699#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2700 type matchmaskx = *(type *)(matchmaskp); \
2701 type matchvalx = *(type *)(matchvalp); \
2702 type maskx = *(type *)(maskp); \
2703 type valx = *(type *)(valp); \
2704 \
2705 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2706 matchmaskx)); \
2707})
2708
27c11b6b 2709static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2710 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2711{
2712 bool same = false;
2713
88f30bbc
DL		 2714 switch (bsize) {
2715 case 8:
2ef86872 2716 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2717 break;
88f30bbc 2718 case 16:
2ef86872 2719 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2720 break;
88f30bbc 2721 case 32:
2ef86872 2722 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2723 break;
2724 }
2725
2726 return same;
2727}
a8e4f0c4 2728
d79b6df6 2729static struct mlx5_fields fields[] = {
88f30bbc
DL		 2730 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2731 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2732 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2733 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2734 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2735 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2736
ab9341b5 2737 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2738 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2739 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2740 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2741
2742 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2743 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2744 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2745 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2746 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2747 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2748 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2749 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2750 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2751 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2752 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2753 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2754 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2755 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2756 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2757 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2758 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2759 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2760
88f30bbc
DL		 2761 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2762 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2763 /* in linux iphdr tcp_flags is 8 bits long */
2764 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2765
88f30bbc
DL		 2766 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2767 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2768};
2769
82198d8b
MD		 2770static unsigned long mask_to_le(unsigned long mask, int size)
2771{
2772 __be32 mask_be32;
2773 __be16 mask_be16;
2774
2775 if (size == 32) {
2776 mask_be32 = (__force __be32)(mask);
2777 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2778 } else if (size == 16) {
2779 mask_be32 = (__force __be32)(mask);
2780 mask_be16 = *(__be16 *)&mask_be32;
2781 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2782 }
2783
2784 return mask;
2785}
6ae4a6a5
PB		 2786static int offload_pedit_fields(struct mlx5e_priv *priv,
2787 int namespace,
2788 struct pedit_headers_action *hdrs,
e98bedf5 2789 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2790 u32 *action_flags,
e98bedf5 2791 struct netlink_ext_ack *extack)
d79b6df6
OG		 2792{
2793 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2794 int i, action_size, first, last, next_z;
88f30bbc
DL		 2795 void *headers_c, *headers_v, *action, *vals_p;
2796 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2797 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2798 struct mlx5_fields *f;
82198d8b 2799 unsigned long mask, field_mask;
6ae4a6a5 2800 int err;
88f30bbc
DL		 2801 u8 cmd;
2802
6ae4a6a5 2803 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2804 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2805 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2806
73867881
PNA		 2807 set_masks = &hdrs[0].masks;
2808 add_masks = &hdrs[1].masks;
2809 set_vals = &hdrs[0].vals;
2810 add_vals = &hdrs[1].vals;
d79b6df6 2811
d65dbedf 2812 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2813
2814 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2815 bool skip;
2816
d79b6df6
OG		 2817 f = &fields[i];
2818 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2819 s_mask = 0;
2820 a_mask = 0;
d79b6df6
OG		 2821
2822 s_masks_p = (void *)set_masks + f->offset;
2823 a_masks_p = (void *)add_masks + f->offset;
2824
88f30bbc
DL		 2825 s_mask = *s_masks_p & f->field_mask;
2826 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2827
2828 if (!s_mask && !a_mask) /* nothing to offload here */
2829 continue;
2830
2831 if (s_mask && a_mask) {
e98bedf5
EB		 2832 NL_SET_ERR_MSG_MOD(extack,
2833 "can't set and add to the same HW field");
61b6a6c3
CH		 2834 netdev_warn(priv->netdev,
2835 "mlx5: can't set and add to the same HW field (%x)\n",
2836 f->field);
d79b6df6
OG		 2837 return -EOPNOTSUPP;
2838 }
2839
27c11b6b 2840 skip = false;
d79b6df6 2841 if (s_mask) {
27c11b6b
EB		 2842 void *match_mask = headers_c + f->match_offset;
2843 void *match_val = headers_v + f->match_offset;
2844
d79b6df6
OG		 2845 cmd = MLX5_ACTION_TYPE_SET;
2846 mask = s_mask;
2847 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2848 /* don't rewrite if we have a match on the same value */
2849 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2850 match_mask, f->field_bsize))
27c11b6b 2851 skip = true;
d79b6df6 2852 /* clear to denote we consumed this field */
88f30bbc 2853 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2854 } else {
2855 cmd = MLX5_ACTION_TYPE_ADD;
2856 mask = a_mask;
2857 vals_p = (void *)add_vals + f->offset;
27c11b6b 2858 /* add 0 is no change */
88f30bbc 2859 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2860 skip = true;
d79b6df6 2861 /* clear to denote we consumed this field */
88f30bbc 2862 *a_masks_p &= ~f->field_mask;
d79b6df6 2863 }
27c11b6b
EB		 2864 if (skip)
2865 continue;
d79b6df6 2866
82198d8b 2867 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2868
88f30bbc
DL		 2869 first = find_first_bit(&mask, f->field_bsize);
2870 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2871 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2872 if (first < next_z && next_z < last) {
e98bedf5
EB		 2873 NL_SET_ERR_MSG_MOD(extack,
2874 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2875 netdev_warn(priv->netdev,
2876 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2877 mask);
d79b6df6
OG		 2878 return -EOPNOTSUPP;
2879 }
2880
6ae4a6a5
PB		 2881 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2882 if (err) {
2883 NL_SET_ERR_MSG_MOD(extack,
2884 "too many pedit actions, can't offload");
2885 mlx5_core_warn(priv->mdev,
2886 "mlx5: parsed %d pedit actions, can't do more\n",
2887 mod_acts->num_actions);
2888 return err;
2889 }
2890
2891 action = mod_acts->actions +
2892 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2893 MLX5_SET(set_action_in, action, action_type, cmd);
2894 MLX5_SET(set_action_in, action, field, f->field);
2895
2896 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2897 int start;
2898
82198d8b
MD		 2899 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2900
88f30bbc 2901 /* if field is bit sized it can start not from first bit */
82198d8b 2902 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2903
2904 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2905 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2906 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2907 }
2908
88f30bbc 2909 if (f->field_bsize == 32)
2b64beba 2910 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2911 else if (f->field_bsize == 16)
2b64beba 2912 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2913 else if (f->field_bsize == 8)
2b64beba 2914 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2915
6ae4a6a5 2916 ++mod_acts->num_actions;
d79b6df6
OG		 2917 }
2918
d79b6df6
OG		 2919 return 0;
2920}
2921
2cc1cb1d
TZ		 2922static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2923 int namespace)
2924{
2925 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2926 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2927 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2928 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2929}
2930
6ae4a6a5
PB		 2931int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2932 int namespace,
2933 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2934{
6ae4a6a5
PB		 2935 int action_size, new_num_actions, max_hw_actions;
2936 size_t new_sz, old_sz;
2937 void *ret;
d79b6df6 2938
6ae4a6a5
PB		 2939 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2940 return 0;
d79b6df6 2941
d65dbedf 2942 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2943
6ae4a6a5
PB		 2944 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2945 namespace);
2946 new_num_actions = min(max_hw_actions,
2947 mod_hdr_acts->actions ?
2948 mod_hdr_acts->max_actions * 2 : 1);
2949 if (mod_hdr_acts->max_actions == new_num_actions)
2950 return -ENOSPC;
2951
2952 new_sz = action_size * new_num_actions;
2953 old_sz = mod_hdr_acts->max_actions * action_size;
2954 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2955 if (!ret)
d79b6df6
OG		 2956 return -ENOMEM;
2957
6ae4a6a5
PB		 2958 memset(ret + old_sz, 0, new_sz - old_sz);
2959 mod_hdr_acts->actions = ret;
2960 mod_hdr_acts->max_actions = new_num_actions;
2961
d79b6df6
OG		 2962 return 0;
2963}
2964
6ae4a6a5
PB		 2965void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2966{
2967 kfree(mod_hdr_acts->actions);
2968 mod_hdr_acts->actions = NULL;
2969 mod_hdr_acts->num_actions = 0;
2970 mod_hdr_acts->max_actions = 0;
2971}
2972
d79b6df6
OG		 2973static const struct pedit_headers zero_masks = {};
2974
582234b4
EC		 2975static int
2976parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2977 const struct flow_action_entry *act, int namespace,
2978 struct mlx5e_tc_flow_parse_attr *parse_attr,
2979 struct pedit_headers_action *hdrs,
2980 struct netlink_ext_ack *extack)
d79b6df6 2981{
73867881
PNA		 2982 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2983 int err = -EOPNOTSUPP;
d79b6df6 2984 u32 mask, val, offset;
73867881 2985 u8 htype;
d79b6df6 2986
73867881
PNA		 2987 htype = act->mangle.htype;
2988 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2989
73867881
PNA		 2990 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2991 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2992 goto out_err;
2993 }
d79b6df6 2994
2cc1cb1d
TZ		 2995 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2996 NL_SET_ERR_MSG_MOD(extack,
2997 "The pedit offload action is not supported");
2998 goto out_err;
2999 }
3000
73867881
PNA		 3001 mask = act->mangle.mask;
3002 val = act->mangle.val;
3003 offset = act->mangle.offset;
d79b6df6 3004
73867881
PNA		 3005 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
3006 if (err)
3007 goto out_err;
c500c86b 3008
73867881 3009 hdrs[cmd].pedits++;
d79b6df6 3010
c500c86b
PNA		 3011 return 0;
3012out_err:
3013 return err;
3014}
3015
582234b4
EC		 3016static int
3017parse_pedit_to_reformat(struct mlx5e_priv *priv,
3018 const struct flow_action_entry *act,
3019 struct mlx5e_tc_flow_parse_attr *parse_attr,
3020 struct netlink_ext_ack *extack)
3021{
3022 u32 mask, val, offset;
3023 u32 *p;
3024
3025 if (act->id != FLOW_ACTION_MANGLE)
3026 return -EOPNOTSUPP;
3027
3028 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
3029 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
3030 return -EOPNOTSUPP;
3031 }
3032
3033 mask = ~act->mangle.mask;
3034 val = act->mangle.val;
3035 offset = act->mangle.offset;
3036 p = (u32 *)&parse_attr->eth;
3037 *(p + (offset >> 2)) |= (val & mask);
3038
3039 return 0;
3040}
3041
3042static int parse_tc_pedit_action(struct mlx5e_priv *priv,
3043 const struct flow_action_entry *act, int namespace,
3044 struct mlx5e_tc_flow_parse_attr *parse_attr,
3045 struct pedit_headers_action *hdrs,
3046 struct mlx5e_tc_flow *flow,
3047 struct netlink_ext_ack *extack)
3048{
3049 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
3050 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
3051
3052 return parse_pedit_to_modify_hdr(priv, act, namespace,
3053 parse_attr, hdrs, extack);
3054}
3055
c500c86b
PNA		 3056static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3057 struct mlx5e_tc_flow_parse_attr *parse_attr,
3058 struct pedit_headers_action *hdrs,
27c11b6b 3059 u32 *action_flags,
c500c86b
PNA		 3060 struct netlink_ext_ack *extack)
3061{
3062 struct pedit_headers *cmd_masks;
3063 int err;
3064 u8 cmd;
3065
6ae4a6a5
PB		 3066 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
3067 action_flags, extack);
d79b6df6
OG		 3068 if (err < 0)
3069 goto out_dealloc_parsed_actions;
3070
3071 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 3072 cmd_masks = &hdrs[cmd].masks;
d79b6df6 3073 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 3074 NL_SET_ERR_MSG_MOD(extack,
3075 "attempt to offload an unsupported field");
b3a433de 3076 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3077 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3078 16, 1, cmd_masks, sizeof(zero_masks), true);
3079 err = -EOPNOTSUPP;
3080 goto out_dealloc_parsed_actions;
3081 }
3082 }
3083
3084 return 0;
3085
3086out_dealloc_parsed_actions:
6ae4a6a5 3087 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3088 return err;
3089}
3090
e98bedf5
EB		 3091static bool csum_offload_supported(struct mlx5e_priv *priv,
3092 u32 action,
3093 u32 update_flags,
3094 struct netlink_ext_ack *extack)
26c02749
OG		 3095{
3096 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3097 TCA_CSUM_UPDATE_FLAG_UDP;
3098
3099 /* The HW recalcs checksums only if re-writing headers */
3100 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3101 NL_SET_ERR_MSG_MOD(extack,
3102 "TC csum action is only offloaded with pedit");
26c02749
OG		 3103 netdev_warn(priv->netdev,
3104 "TC csum action is only offloaded with pedit\n");
3105 return false;
3106 }
3107
3108 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3109 NL_SET_ERR_MSG_MOD(extack,
3110 "can't offload TC csum action for some header/s");
26c02749
OG		 3111 netdev_warn(priv->netdev,
3112 "can't offload TC csum action for some header/s - flags %#x\n",
3113 update_flags);
3114 return false;
3115 }
3116
3117 return true;
3118}
3119
8998576b
DL		 3120struct ip_ttl_word {
3121 __u8 ttl;
3122 __u8 protocol;
3123 __sum16 check;
3124};
3125
3126struct ipv6_hoplimit_word {
3127 __be16 payload_len;
3128 __u8 nexthdr;
3129 __u8 hop_limit;
3130};
3131
4c3844d9
PB		 3132static int is_action_keys_supported(const struct flow_action_entry *act,
3133 bool ct_flow, bool *modify_ip_header,
7e36feeb 3134 bool *modify_tuple,
4c3844d9 3135 struct netlink_ext_ack *extack)
8998576b
DL		 3136{
3137 u32 mask, offset;
3138 u8 htype;
3139
3140 htype = act->mangle.htype;
3141 offset = act->mangle.offset;
3142 mask = ~act->mangle.mask;
3143 /* For IPv4 & IPv6 header check 4 byte word,
3144 * to determine that modified fields
3145 * are NOT ttl & hop_limit only.
3146 */
3147 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3148 struct ip_ttl_word *ttl_word =
3149 (struct ip_ttl_word *)&mask;
3150
3151 if (offset != offsetof(struct iphdr, ttl) ||
3152 ttl_word->protocol ||
3153 ttl_word->check) {
4c3844d9
PB		 3154 *modify_ip_header = true;
3155 }
3156
7e36feeb
PB		 3157 if (offset >= offsetof(struct iphdr, saddr))
3158 *modify_tuple = true;
3159
3160 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3161 NL_SET_ERR_MSG_MOD(extack,
3162 "can't offload re-write of ipv4 address with action ct");
3163 return -EOPNOTSUPP;
8998576b
DL		 3164 }
3165 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3166 struct ipv6_hoplimit_word *hoplimit_word =
3167 (struct ipv6_hoplimit_word *)&mask;
3168
3169 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3170 hoplimit_word->payload_len ||
3171 hoplimit_word->nexthdr) {
4c3844d9
PB		 3172 *modify_ip_header = true;
3173 }
3174
7e36feeb
PB		 3175 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3176 *modify_tuple = true;
3177
3178 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3179 NL_SET_ERR_MSG_MOD(extack,
3180 "can't offload re-write of ipv6 address with action ct");
3181 return -EOPNOTSUPP;
8998576b 3182 }
7e36feeb
PB		 3183 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3184 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3185 *modify_tuple = true;
3186 if (ct_flow) {
3187 NL_SET_ERR_MSG_MOD(extack,
3188 "can't offload re-write of transport header ports with action ct");
3189 return -EOPNOTSUPP;
3190 }
8998576b 3191 }
4c3844d9
PB		 3192
3193 return 0;
8998576b
DL		 3194}
3195
96b5b458
DC		 3196static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3197 bool ct_flow, struct netlink_ext_ack *extack,
3198 struct mlx5e_priv *priv,
3199 struct mlx5_flow_spec *spec)
3200{
3201 if (!modify_tuple || ct_clear)
3202 return true;
3203
3204 if (ct_flow) {
3205 NL_SET_ERR_MSG_MOD(extack,
3206 "can't offload tuple modification with non-clear ct()");
3207 netdev_info(priv->netdev,
3208 "can't offload tuple modification with non-clear ct()");
3209 return false;
3210 }
3211
3212 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3213 * (or after clear action), as otherwise, since the tuple is changed,
3214 * we can't restore ct state
3215 */
3216 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3217 NL_SET_ERR_MSG_MOD(extack,
3218 "can't offload tuple modification with ct matches and no ct(clear) action");
3219 netdev_info(priv->netdev,
3220 "can't offload tuple modification with ct matches and no ct(clear) action");
3221 return false;
3222 }
3223
3224 return true;
3225}
3226
3d486ec4
OS		 3227static bool modify_header_match_supported(struct mlx5e_priv *priv,
3228 struct mlx5_flow_spec *spec,
73867881 3229 struct flow_action *flow_action,
4c3844d9 3230 u32 actions, bool ct_flow,
7e36feeb 3231 bool ct_clear,
e98bedf5 3232 struct netlink_ext_ack *extack)
bdd66ac0 3233{
73867881 3234 const struct flow_action_entry *act;
7e36feeb 3235 bool modify_ip_header, modify_tuple;
fca53304 3236 void *headers_c;
bdd66ac0
OG		 3237 void *headers_v;
3238 u16 ethertype;
8998576b 3239 u8 ip_proto;
4c3844d9 3240 int i, err;
bdd66ac0 3241
fca53304 3242 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3243 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3244 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3245
3246 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3247 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3248 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3249 goto out_ok;
3250
3251 modify_ip_header = false;
7e36feeb 3252 modify_tuple = false;
73867881
PNA		 3253 flow_action_for_each(i, act, flow_action) {
3254 if (act->id != FLOW_ACTION_MANGLE &&
3255 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3256 continue;
3257
4c3844d9 3258 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3259 &modify_ip_header,
3260 &modify_tuple, extack);
4c3844d9
PB		 3261 if (err)
3262 return err;
bdd66ac0
OG		 3263 }
3264
96b5b458
DC		 3265 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3266 priv, spec))
7e36feeb 3267 return false;
7e36feeb 3268
bdd66ac0 3269 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3270 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3271 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3272 NL_SET_ERR_MSG_MOD(extack,
3273 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3274 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3275 ip_proto);
bdd66ac0
OG		 3276 return false;
3277 }
3278
3279out_ok:
3280 return true;
3281}
3282
3283static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3284 struct flow_action *flow_action,
bdd66ac0 3285 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3286 struct mlx5e_tc_flow *flow,
3287 struct netlink_ext_ack *extack)
bdd66ac0 3288{
a7c119bd 3289 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3290 u32 actions;
3291
c620b772
AL		 3292 ct_clear = flow->attr->ct_attr.ct_action &
3293 TCA_CT_ACT_CLEAR;
3294 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3295 actions = flow->attr->action;
3296
4c3844d9 3297 if (mlx5e_is_eswitch_flow(flow)) {
69e2916e
PB		 3298 if (flow->attr->esw_attr->split_count && ct_flow &&
3299 !MLX5_CAP_GEN(flow->attr->esw_attr->in_mdev, reg_c_preserve)) {
4c3844d9
PB		 3300 /* All registers used by ct are cleared when using
3301 * split rules.
3302 */
3303 NL_SET_ERR_MSG_MOD(extack,
3304 "Can't offload mirroring with action ct");
49397b80 3305 return false;
4c3844d9 3306 }
4c3844d9 3307 }
bdd66ac0
OG		 3308
3309 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3310 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3311 flow_action, actions,
7e36feeb
PB		 3312 ct_flow, ct_clear,
3313 extack);
bdd66ac0
OG		 3314
3315 return true;
3316}
3317
32134847
MD		 3318static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3319{
3320 return priv->mdev == peer_priv->mdev;
3321}
3322
5c65c564
OG		 3323static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3324{
3325 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3326 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3327
3328 fmdev = priv->mdev;
3329 pmdev = peer_priv->mdev;
3330
59c9d35e
AH		 3331 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3332 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3333
816f6706 3334 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3335}
3336
bb569657
AL		 3337static bool same_vf_reps(struct mlx5e_priv *priv,
3338 struct net_device *out_dev)
3339{
3340 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3341 priv->netdev == out_dev;
3342}
3343
bdc837ee
EB		 3344static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3345 const struct flow_action_entry *act,
3346 struct mlx5e_tc_flow_parse_attr *parse_attr,
3347 struct pedit_headers_action *hdrs,
3348 u32 *action, struct netlink_ext_ack *extack)
3349{
3350 u16 mask16 = VLAN_VID_MASK;
3351 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3352 const struct flow_action_entry pedit_act = {
3353 .id = FLOW_ACTION_MANGLE,
3354 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3355 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3356 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3357 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3358 };
6fca9d1e 3359 u8 match_prio_mask, match_prio_val;
bf2f3bca 3360 void *headers_c, *headers_v;
bdc837ee
EB		 3361 int err;
3362
bf2f3bca
EB		 3363 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3364 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3365
3366 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3367 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3368 NL_SET_ERR_MSG_MOD(extack,
3369 "VLAN rewrite action must have VLAN protocol match");
3370 return -EOPNOTSUPP;
3371 }
3372
6fca9d1e
EB		 3373 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3374 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3375 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3376 NL_SET_ERR_MSG_MOD(extack,
3377 "Changing VLAN prio is not supported");
bdc837ee
EB		 3378 return -EOPNOTSUPP;
3379 }
3380
582234b4 3381 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3382 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3383
3384 return err;
3385}
3386
0bac1194
EB		 3387static int
3388add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3389 struct mlx5e_tc_flow_parse_attr *parse_attr,
3390 struct pedit_headers_action *hdrs,
3391 u32 *action, struct netlink_ext_ack *extack)
3392{
3393 const struct flow_action_entry prio_tag_act = {
3394 .vlan.vid = 0,
3395 .vlan.prio =
3396 MLX5_GET(fte_match_set_lyr_2_4,
3397 get_match_headers_value(*action,
3398 &parse_attr->spec),
3399 first_prio) &
3400 MLX5_GET(fte_match_set_lyr_2_4,
3401 get_match_headers_criteria(*action,
3402 &parse_attr->spec),
3403 first_prio),
3404 };
3405
3406 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3407 &prio_tag_act, parse_attr, hdrs, action,
3408 extack);
3409}
3410
c7569097
AL		 3411static int validate_goto_chain(struct mlx5e_priv *priv,
3412 struct mlx5e_tc_flow *flow,
3413 const struct flow_action_entry *act,
3414 u32 actions,
3415 struct netlink_ext_ack *extack)
3416{
3417 bool is_esw = mlx5e_is_eswitch_flow(flow);
3418 struct mlx5_flow_attr *attr = flow->attr;
3419 bool ft_flow = mlx5e_is_ft_flow(flow);
3420 u32 dest_chain = act->chain_index;
3421 struct mlx5_fs_chains *chains;
3422 struct mlx5_eswitch *esw;
3423 u32 reformat_and_fwd;
3424 u32 max_chain;
3425
3426 esw = priv->mdev->priv.eswitch;
3427 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3428 max_chain = mlx5_chains_get_chain_range(chains);
3429 reformat_and_fwd = is_esw ?
3430 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3431 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3432
3433 if (ft_flow) {
3434 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3435 return -EOPNOTSUPP;
3436 }
3437
3438 if (!mlx5_chains_backwards_supported(chains) &&
3439 dest_chain <= attr->chain) {
3440 NL_SET_ERR_MSG_MOD(extack,
3441 "Goto lower numbered chain isn't supported");
3442 return -EOPNOTSUPP;
3443 }
3444
3445 if (dest_chain > max_chain) {
3446 NL_SET_ERR_MSG_MOD(extack,
3447 "Requested destination chain is out of supported range");
3448 return -EOPNOTSUPP;
3449 }
3450
3451 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3452 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3453 !reformat_and_fwd) {
3454 NL_SET_ERR_MSG_MOD(extack,
3455 "Goto chain is not allowed if action has reformat or decap");
3456 return -EOPNOTSUPP;
3457 }
3458
3459 return 0;
3460}
3461
73867881
PNA		 3462static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3463 struct flow_action *flow_action,
e98bedf5
EB		 3464 struct mlx5e_tc_flow *flow,
3465 struct netlink_ext_ack *extack)
e3a2b7ed 3466{
c6cfe113 3467 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3468 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3469 struct pedit_headers_action hdrs[2] = {};
3470 const struct flow_action_entry *act;
c620b772 3471 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3472 u32 action = 0;
244cd96a 3473 int err, i;
e3a2b7ed 3474
73867881 3475 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3476 return -EINVAL;
3477
53eca1f3
JK		 3478 if (!flow_action_hw_stats_check(flow_action, extack,
3479 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3480 return -EOPNOTSUPP;
3481
c620b772 3482 nic_attr = attr->nic_attr;
c620b772 3483 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3484 parse_attr = attr->parse_attr;
e3a2b7ed 3485
73867881
PNA		 3486 flow_action_for_each(i, act, flow_action) {
3487 switch (act->id) {
15fc92ec
TZ		 3488 case FLOW_ACTION_ACCEPT:
3489 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3490 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3491 break;
73867881 3492 case FLOW_ACTION_DROP:
950b4df9
RD		 3493 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3494 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3495 break;
3496 case FLOW_ACTION_MANGLE:
3497 case FLOW_ACTION_ADD:
3498 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3499 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3500 if (err)
3501 return err;
3502
c7569097 3503 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3504 break;
bdc837ee
EB		 3505 case FLOW_ACTION_VLAN_MANGLE:
3506 err = add_vlan_rewrite_action(priv,
3507 MLX5_FLOW_NAMESPACE_KERNEL,
3508 act, parse_attr, hdrs,
3509 &action, extack);
3510 if (err)
3511 return err;
3512
3513 break;
73867881 3514 case FLOW_ACTION_CSUM:
1cab1cd7 3515 if (csum_offload_supported(priv, action,
73867881 3516 act->csum_flags,
e98bedf5 3517 extack))
73867881 3518 break;
26c02749
OG		 3519
3520 return -EOPNOTSUPP;
73867881
PNA		 3521 case FLOW_ACTION_REDIRECT: {
3522 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3523
3524 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3525 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3526 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3527 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3528 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3529 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3530 } else {
e98bedf5
EB		 3531 NL_SET_ERR_MSG_MOD(extack,
3532 "device is not on same HW, can't offload");
5c65c564
OG		 3533 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3534 peer_dev->name);
25f150f4 3535 return -EOPNOTSUPP;
5c65c564 3536 }
73867881
PNA		 3537 }
3538 break;
3539 case FLOW_ACTION_MARK: {
3540 u32 mark = act->mark;
e3a2b7ed
AV		 3541
3542 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3543 NL_SET_ERR_MSG_MOD(extack,
3544 "Bad flow mark - only 16 bit is supported");
25f150f4 3545 return -EOPNOTSUPP;
e3a2b7ed
AV		 3546 }
3547
c620b772 3548 nic_attr->flow_tag = mark;
1cab1cd7 3549 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3550 }
3551 break;
c7569097
AL		 3552 case FLOW_ACTION_GOTO:
3553 err = validate_goto_chain(priv, flow, act, action,
3554 extack);
3555 if (err)
3556 return err;
3557
3558 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3559 attr->dest_chain = act->chain_index;
3560 break;
aedd133d 3561 case FLOW_ACTION_CT:
3cfe4267
RD		 3562 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr,
3563 &parse_attr->mod_hdr_acts,
3564 act, extack);
aedd133d
AL		 3565 if (err)
3566 return err;
3567
3568 flow_flag_set(flow, CT);
3569 break;
73867881 3570 default:
2cc1cb1d
TZ		 3571 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3572 return -EOPNOTSUPP;
e3a2b7ed 3573 }
e3a2b7ed
AV		 3574 }
3575
c500c86b
PNA		 3576 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3577 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3578 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3579 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3580 if (err)
3581 return err;
27c11b6b
EB		 3582 /* in case all pedit actions are skipped, remove the MOD_HDR
3583 * flag.
3584 */
6ae4a6a5 3585 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3586 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3587 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3588 }
c500c86b
PNA		 3589 }
3590
1cab1cd7 3591 attr->action = action;
c7569097
AL		 3592
3593 if (attr->dest_chain) {
3594 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3595 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3596 return -EOPNOTSUPP;
3597 }
3598 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3599 }
3600
3601 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3602 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3603
73867881 3604 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3605 return -EOPNOTSUPP;
3606
e3a2b7ed
AV		 3607 return 0;
3608}
3609
32134847 3610static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3611 struct net_device *peer_netdev)
3612{
3613 struct mlx5e_priv *peer_priv;
3614
3615 peer_priv = netdev_priv(peer_netdev);
3616
3617 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3618 mlx5e_eswitch_vf_rep(priv->netdev) &&
3619 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3620 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3621}
3622
1482bd3d 3623static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3624 const struct flow_action_entry *act,
1482bd3d
JL		 3625 struct mlx5_esw_flow_attr *attr,
3626 u32 *action)
3627{
cc495188
JL		 3628 u8 vlan_idx = attr->total_vlan;
3629
3630 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3631 return -EOPNOTSUPP;
3632
73867881
PNA		 3633 switch (act->id) {
3634 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3635 if (vlan_idx) {
3636 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3637 MLX5_FS_VLAN_DEPTH))
3638 return -EOPNOTSUPP;
3639
3640 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3641 } else {
3642 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3643 }
73867881
PNA		 3644 break;
3645 case FLOW_ACTION_VLAN_PUSH:
3646 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3647 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3648 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3649 if (!attr->vlan_proto[vlan_idx])
3650 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3651
3652 if (vlan_idx) {
3653 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3654 MLX5_FS_VLAN_DEPTH))
3655 return -EOPNOTSUPP;
3656
3657 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3658 } else {
3659 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3660 (act->vlan.proto != htons(ETH_P_8021Q) ||
3661 act->vlan.prio))
cc495188
JL		 3662 return -EOPNOTSUPP;
3663
3664 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3665 }
73867881
PNA		 3666 break;
3667 default:
bdc837ee 3668 return -EINVAL;
1482bd3d
JL		 3669 }
3670
cc495188
JL		 3671 attr->total_vlan = vlan_idx + 1;
3672
1482bd3d
JL		 3673 return 0;
3674}
3675
d34eb2fc
OG		 3676static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3677 struct net_device *out_dev)
3678{
3679 struct net_device *fdb_out_dev = out_dev;
3680 struct net_device *uplink_upper;
3681
3682 rcu_read_lock();
3683 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3684 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3685 uplink_upper == out_dev) {
3686 fdb_out_dev = uplink_dev;
3687 } else if (netif_is_lag_master(out_dev)) {
3688 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3689 if (fdb_out_dev &&
3690 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3691 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3692 fdb_out_dev = NULL;
3693 }
3694 rcu_read_unlock();
3695 return fdb_out_dev;
3696}
3697
278748a9 3698static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3699 struct mlx5_flow_attr *attr,
278748a9
EB		 3700 struct net_device **out_dev,
3701 u32 *action)
3702{
3703 struct net_device *vlan_dev = *out_dev;
3704 struct flow_action_entry vlan_act = {
3705 .id = FLOW_ACTION_VLAN_PUSH,
3706 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3707 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3708 .vlan.prio = 0,
3709 };
3710 int err;
3711
c620b772 3712 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 3713 if (err)
3714 return err;
3715
dca59f4a
DC		 3716 rcu_read_lock();
3717 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3718 rcu_read_unlock();
3719 if (!*out_dev)
3720 return -ENODEV;
3721
278748a9
EB		 3722 if (is_vlan_dev(*out_dev))
3723 err = add_vlan_push_action(priv, attr, out_dev, action);
3724
3725 return err;
3726}
3727
35a605db 3728static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3729 struct mlx5_flow_attr *attr,
35a605db
EB		 3730 u32 *action)
3731{
35a605db
EB		 3732 struct flow_action_entry vlan_act = {
3733 .id = FLOW_ACTION_VLAN_POP,
3734 };
70f478ca 3735 int nest_level, err = 0;
35a605db 3736
70f478ca
DL		 3737 nest_level = attr->parse_attr->filter_dev->lower_level -
3738 priv->netdev->lower_level;
35a605db 3739 while (nest_level--) {
c620b772 3740 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 3741 if (err)
3742 return err;
3743 }
3744
3745 return err;
3746}
3747
32134847
MD		 3748static bool same_hw_reps(struct mlx5e_priv *priv,
3749 struct net_device *peer_netdev)
3750{
3751 struct mlx5e_priv *peer_priv;
3752
3753 peer_priv = netdev_priv(peer_netdev);
3754
3755 return mlx5e_eswitch_rep(priv->netdev) &&
3756 mlx5e_eswitch_rep(peer_netdev) &&
3757 same_hw_devs(priv, peer_priv);
3758}
3759
3760static bool is_lag_dev(struct mlx5e_priv *priv,
3761 struct net_device *peer_netdev)
3762{
3763 return ((mlx5_lag_is_sriov(priv->mdev) ||
3764 mlx5_lag_is_multipath(priv->mdev)) &&
3765 same_hw_reps(priv, peer_netdev));
3766}
3767
f6dc1264
PB		 3768bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3769 struct net_device *out_dev)
3770{
32134847
MD		 3771 if (is_merged_eswitch_vfs(priv, out_dev))
3772 return true;
3773
3774 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3775 return true;
3776
3777 return mlx5e_eswitch_rep(out_dev) &&
32134847 3778 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3779}
3780
554fe75c
DL		 3781static bool is_duplicated_output_device(struct net_device *dev,
3782 struct net_device *out_dev,
3783 int *ifindexes, int if_count,
3784 struct netlink_ext_ack *extack)
3785{
3786 int i;
3787
3788 for (i = 0; i < if_count; i++) {
3789 if (ifindexes[i] == out_dev->ifindex) {
3790 NL_SET_ERR_MSG_MOD(extack,
3791 "can't duplicate output to same device");
3792 netdev_err(dev, "can't duplicate output to same device: %s\n",
3793 out_dev->name);
3794 return true;
3795 }
3796 }
3797
3798 return false;
3799}
3800
613f53fe
EC		 3801static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3802 struct mlx5e_tc_flow *flow,
3803 struct net_device *out_dev,
3804 struct netlink_ext_ack *extack)
3805{
c620b772 3806 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3807 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3808 struct mlx5e_rep_priv *rep_priv;
3809
3810 /* Forwarding non encapsulated traffic between
3811 * uplink ports is allowed only if
3812 * termination_table_raw_traffic cap is set.
3813 *
c620b772 3814 * Input vport was stored attr->in_rep.
613f53fe
EC		 3815 * In LAG case, *priv* is the private data of
3816 * uplink which may be not the input vport.
3817 */
3818 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3819
3820 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3821 mlx5e_eswitch_uplink_rep(out_dev)))
3822 return 0;
3823
3824 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3825 termination_table_raw_traffic)) {
3826 NL_SET_ERR_MSG_MOD(extack,
3827 "devices are both uplink, can't offload forwarding");
3828 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3829 priv->netdev->name, out_dev->name);
3830 return -EOPNOTSUPP;
3831 } else if (out_dev != rep_priv->netdev) {
3832 NL_SET_ERR_MSG_MOD(extack,
3833 "devices are not the same uplink, can't offload forwarding");
3834 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3835 priv->netdev->name, out_dev->name);
3836 return -EOPNOTSUPP;
3837 }
3838 return 0;
3839}
3840
73867881
PNA		 3841static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3842 struct flow_action *flow_action,
e98bedf5 3843 struct mlx5e_tc_flow *flow,
70f8019e 3844 struct netlink_ext_ack *extack)
03a9d11e 3845{
73867881 3846 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3847 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3848 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3849 struct mlx5e_rep_priv *rpriv = priv->ppriv;
bcd6740c 3850 struct mlx5e_sample_attr sample_attr = {};
73867881 3851 const struct ip_tunnel_info *info = NULL;
c620b772 3852 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3853 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3854 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3855 const struct flow_action_entry *act;
c620b772 3856 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 3857 bool encap = false, decap = false;
3858 u32 action = attr->action;
554fe75c 3859 int err, i, if_count = 0;
f828ca6a 3860 bool mpls_push = false;
03a9d11e 3861
73867881 3862 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3863 return -EINVAL;
3864
53eca1f3
JK		 3865 if (!flow_action_hw_stats_check(flow_action, extack,
3866 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3867 return -EOPNOTSUPP;
3868
c620b772
AL		 3869 esw_attr = attr->esw_attr;
3870 parse_attr = attr->parse_attr;
3871
73867881
PNA		 3872 flow_action_for_each(i, act, flow_action) {
3873 switch (act->id) {
3874 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3875 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3876 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3877 break;
f0288210
EC		 3878 case FLOW_ACTION_TRAP:
3879 if (!flow_offload_has_one_action(flow_action)) {
3880 NL_SET_ERR_MSG_MOD(extack,
3881 "action trap is supported as a sole action only");
3882 return -EOPNOTSUPP;
3883 }
3884 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3885 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3886 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3887 break;
f828ca6a
EC		 3888 case FLOW_ACTION_MPLS_PUSH:
3889 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3890 reformat_l2_to_l3_tunnel) ||
3891 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3892 NL_SET_ERR_MSG_MOD(extack,
3893 "mpls push is supported only for mpls_uc protocol");
3894 return -EOPNOTSUPP;
3895 }
3896 mpls_push = true;
3897 break;
14e6b038
EC		 3898 case FLOW_ACTION_MPLS_POP:
3899 /* we only support mpls pop if it is the first action
3900 * and the filter net device is bareudp. Subsequent
3901 * actions can be pedit and the last can be mirred
3902 * egress redirect.
3903 */
3904 if (i) {
3905 NL_SET_ERR_MSG_MOD(extack,
3906 "mpls pop supported only as first action");
3907 return -EOPNOTSUPP;
3908 }
70f8019e 3909 if (!netif_is_bareudp(parse_attr->filter_dev)) {
14e6b038
EC		 3910 NL_SET_ERR_MSG_MOD(extack,
3911 "mpls pop supported only on bareudp devices");
3912 return -EOPNOTSUPP;
3913 }
3914
3915 parse_attr->eth.h_proto = act->mpls_pop.proto;
3916 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3917 flow_flag_set(flow, L3_TO_L2_DECAP);
3918 break;
73867881
PNA		 3919 case FLOW_ACTION_MANGLE:
3920 case FLOW_ACTION_ADD:
3921 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3922 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3923 if (err)
3924 return err;
3925
582234b4
EC		 3926 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3927 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3928 esw_attr->split_count = esw_attr->out_count;
582234b4 3929 }
73867881
PNA		 3930 break;
3931 case FLOW_ACTION_CSUM:
1cab1cd7 3932 if (csum_offload_supported(priv, action,
73867881
PNA		 3933 act->csum_flags, extack))
3934 break;
26c02749
OG		 3935
3936 return -EOPNOTSUPP;
73867881
PNA		 3937 case FLOW_ACTION_REDIRECT:
3938 case FLOW_ACTION_MIRRED: {
03a9d11e 3939 struct mlx5e_priv *out_priv;
592d3651 3940 struct net_device *out_dev;
03a9d11e 3941
73867881 3942 out_dev = act->dev;
ef381359
OS		 3943 if (!out_dev) {
3944 /* out_dev is NULL when filters with
3945 * non-existing mirred device are replayed to
3946 * the driver.
3947 */
3948 return -EINVAL;
3949 }
03a9d11e 3950
f828ca6a
EC		 3951 if (mpls_push && !netif_is_bareudp(out_dev)) {
3952 NL_SET_ERR_MSG_MOD(extack,
3953 "mpls is supported only through a bareudp device");
3954 return -EOPNOTSUPP;
3955 }
3956
84179981
PB		 3957 if (ft_flow && out_dev == priv->netdev) {
3958 /* Ignore forward to self rules generated
3959 * by adding both mlx5 devs to the flow table
3960 * block on a normal nft offload setup.
3961 */
3962 return -EOPNOTSUPP;
3963 }
3964
c620b772 3965 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3966 NL_SET_ERR_MSG_MOD(extack,
3967 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3968 netdev_warn(priv->netdev,
3969 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3970 esw_attr->out_count);
592d3651
CM		 3971 return -EOPNOTSUPP;
3972 }
3973
f493f155
EB		 3974 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3975 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3976 if (encap) {
c620b772 3977 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3978 out_dev->ifindex;
0d9f9647
VB		 3979 parse_attr->tun_info[esw_attr->out_count] =
3980 mlx5e_dup_tun_info(info);
c620b772 3981 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3982 return -ENOMEM;
3983 encap = false;
c620b772 3984 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3985 MLX5_ESW_DEST_ENCAP;
c620b772 3986 esw_attr->out_count++;
b6a4ac24
VB		 3987 /* attr->dests[].rep is resolved when we
3988 * handle encap
3989 */
3990 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3991 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3992 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3993
554fe75c
DL		 3994 if (is_duplicated_output_device(priv->netdev,
3995 out_dev,
3996 ifindexes,
3997 if_count,
3998 extack))
3999 return -EOPNOTSUPP;
4000
4001 ifindexes[if_count] = out_dev->ifindex;
4002 if_count++;
4003
d34eb2fc
OG		 4004 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4005 if (!out_dev)
4006 return -ENODEV;
7ba58ba7 4007
278748a9
EB		 4008 if (is_vlan_dev(out_dev)) {
4009 err = add_vlan_push_action(priv, attr,
4010 &out_dev,
4011 &action);
4012 if (err)
4013 return err;
4014 }
f6dc1264 4015
35a605db
EB		 4016 if (is_vlan_dev(parse_attr->filter_dev)) {
4017 err = add_vlan_pop_action(priv, attr,
4018 &action);
4019 if (err)
4020 return err;
4021 }
278748a9 4022
613f53fe
EC		 4023 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4024 if (err)
4025 return err;
ffec9702 4026
f6dc1264
PB		 4027 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4028 NL_SET_ERR_MSG_MOD(extack,
4029 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4030 return -EOPNOTSUPP;
f6dc1264 4031 }
a0646c88 4032
bb569657
AL		 4033 if (same_vf_reps(priv, out_dev)) {
4034 NL_SET_ERR_MSG_MOD(extack,
4035 "can't forward from a VF to itself");
4036 return -EOPNOTSUPP;
4037 }
4038
a54e20b4 4039 out_priv = netdev_priv(out_dev);
1d447a39 4040 rpriv = out_priv->ppriv;
c620b772
AL		 4041 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
4042 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
4043 esw_attr->out_count++;
ef381359
OS		 4044 } else if (parse_attr->filter_dev != priv->netdev) {
4045 /* All mlx5 devices are called to configure
4046 * high level device filters. Therefore, the
4047 * *attempt* to install a filter on invalid
4048 * eswitch should not trigger an explicit error
4049 */
4050 return -EINVAL;
a54e20b4 4051 } else {
e98bedf5
EB		 4052 NL_SET_ERR_MSG_MOD(extack,
4053 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4054 netdev_warn(priv->netdev,
4055 "devices %s %s not on same switch HW, can't offload forwarding\n",
4056 priv->netdev->name,
4057 out_dev->name);
25f150f4 4058 return -EOPNOTSUPP;
03a9d11e 4059 }
73867881
PNA		 4060 }
4061 break;
4062 case FLOW_ACTION_TUNNEL_ENCAP:
4063 info = act->tunnel;
a54e20b4
HHZ		 4064 if (info)
4065 encap = true;
4066 else
4067 return -EOPNOTSUPP;
1482bd3d 4068
73867881
PNA		 4069 break;
4070 case FLOW_ACTION_VLAN_PUSH:
4071 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4072 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4073 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4074 /* Replace vlan pop+push with vlan modify */
4075 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4076 err = add_vlan_rewrite_action(priv,
4077 MLX5_FLOW_NAMESPACE_FDB,
4078 act, parse_attr, hdrs,
4079 &action, extack);
4080 } else {
c620b772 4081 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 4082 }
1482bd3d
JL		 4083 if (err)
4084 return err;
4085
c620b772 4086 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 4087 break;
4088 case FLOW_ACTION_VLAN_MANGLE:
4089 err = add_vlan_rewrite_action(priv,
4090 MLX5_FLOW_NAMESPACE_FDB,
4091 act, parse_attr, hdrs,
4092 &action, extack);
4093 if (err)
4094 return err;
4095
c620b772 4096 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 4097 break;
4098 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4099 decap = true;
73867881 4100 break;
2fbbc30d 4101 case FLOW_ACTION_GOTO:
c7569097
AL		 4102 err = validate_goto_chain(priv, flow, act, action,
4103 extack);
2fbbc30d
EC		 4104 if (err)
4105 return err;
bf07aa73 4106
e88afe75 4107 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4108 attr->dest_chain = act->chain_index;
73867881 4109 break;
4c3844d9 4110 case FLOW_ACTION_CT:
41c2fd94
CM		 4111 if (flow_flag_test(flow, SAMPLE)) {
4112 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4113 return -EOPNOTSUPP;
4114 }
3cfe4267
RD		 4115 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr,
4116 &parse_attr->mod_hdr_acts,
4117 act, extack);
4c3844d9
PB		 4118 if (err)
4119 return err;
4120
4121 flow_flag_set(flow, CT);
69e2916e 4122 esw_attr->split_count = esw_attr->out_count;
4c3844d9 4123 break;
41c2fd94
CM		 4124 case FLOW_ACTION_SAMPLE:
4125 if (flow_flag_test(flow, CT)) {
4126 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4127 return -EOPNOTSUPP;
4128 }
bcd6740c
CM		 4129 sample_attr.rate = act->sample.rate;
4130 sample_attr.group_num = act->sample.psample_group->group_num;
41c2fd94 4131 if (act->sample.truncate)
bcd6740c 4132 sample_attr.trunc_size = act->sample.trunc_size;
41c2fd94
CM		 4133 flow_flag_set(flow, SAMPLE);
4134 break;
73867881 4135 default:
2cc1cb1d
TZ		 4136 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4137 return -EOPNOTSUPP;
bf07aa73 4138 }
03a9d11e 4139 }
bdd66ac0 4140
a508728a
VB		 4141 /* always set IP version for indirect table handling */
4142 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4143
0bac1194
EB		 4144 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4145 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4146 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4147 * tag rewrite.
4148 */
4149 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4150 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4151 &action, extack);
4152 if (err)
4153 return err;
4154 }
4155
c500c86b
PNA		 4156 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4157 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4158 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4159 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4160 if (err)
4161 return err;
27c11b6b
EB		 4162 /* in case all pedit actions are skipped, remove the MOD_HDR
4163 * flag. we might have set split_count either by pedit or
4164 * pop/push. if there is no pop/push either, reset it too.
4165 */
6ae4a6a5 4166 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4167 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4168 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4169 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4170 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4171 esw_attr->split_count = 0;
27c11b6b 4172 }
c500c86b
PNA		 4173 }
4174
1cab1cd7 4175 attr->action = action;
73867881 4176 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4177 return -EOPNOTSUPP;
4178
e88afe75 4179 if (attr->dest_chain) {
0a7fcb78
PB		 4180 if (decap) {
4181 /* It can be supported if we'll create a mapping for
4182 * the tunnel device only (without tunnel), and set
4183 * this tunnel id with this decap flow.
4184 *
4185 * On restore (miss), we'll just set this saved tunnel
4186 * device.
4187 */
4188
4189 NL_SET_ERR_MSG(extack,
4190 "Decap with goto isn't supported");
4191 netdev_warn(priv->netdev,
4192 "Decap with goto isn't supported");
4193 return -EOPNOTSUPP;
4194 }
4195
e88afe75
OG		 4196 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4197 }
4198
ae2741e2
VB		 4199 if (!(attr->action &
4200 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4201 NL_SET_ERR_MSG_MOD(extack,
4202 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4203 return -EOPNOTSUPP;
4204 }
4205
c620b772 4206 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4207 NL_SET_ERR_MSG_MOD(extack,
4208 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4209 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4210 return -EOPNOTSUPP;
4211 }
4212
41c2fd94
CM		 4213 /* Allocate sample attribute only when there is a sample action and
4214 * no errors after parsing.
4215 */
4216 if (flow_flag_test(flow, SAMPLE)) {
bcd6740c
CM		 4217 attr->sample_attr = kzalloc(sizeof(*attr->sample_attr), GFP_KERNEL);
4218 if (!attr->sample_attr)
41c2fd94 4219 return -ENOMEM;
bcd6740c 4220 *attr->sample_attr = sample_attr;
41c2fd94
CM		 4221 }
4222
31c8eba5 4223 return 0;
03a9d11e
OG		 4224}
4225
226f2ca3 4226static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4227{
226f2ca3 4228 unsigned long __flow_flags = 0;
60bd4af8 4229
226f2ca3
VB		 4230 if (flags & MLX5_TC_FLAG(INGRESS))
4231 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4232 if (flags & MLX5_TC_FLAG(EGRESS))
4233 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4234
226f2ca3
VB		 4235 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4236 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4237 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4238 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4239 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4240 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4241
60bd4af8
OG		 4242 *flow_flags = __flow_flags;
4243}
4244
05866c82
OG		 4245static const struct rhashtable_params tc_ht_params = {
4246 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4247 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4248 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4249 .automatic_shrinking = true,
4250};
4251
226f2ca3
VB		 4252static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4253 unsigned long flags)
05866c82 4254{
655dc3d2
OG		 4255 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4256 struct mlx5e_rep_priv *uplink_rpriv;
4257
226f2ca3 4258 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4259 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4260 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4261 } else /* NIC offload */
655dc3d2 4262 return &priv->fs.tc.ht;
05866c82
OG		 4263}
4264
04de7dda
RD		 4265static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4266{
c620b772
AL		 4267 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4268 struct mlx5_flow_attr *attr = flow->attr;
4269 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4270 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4271 bool act_is_encap = !!(attr->action &
4272 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4273 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4274 MLX5_DEVCOM_ESW_OFFLOADS);
4275
10fbb1cd
RD		 4276 if (!esw_paired)
4277 return false;
4278
c620b772
AL		 4279 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4280 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4281 (is_rep_ingress || act_is_encap))
4282 return true;
4283
4284 return false;
04de7dda
RD		 4285}
4286
c620b772
AL		 4287struct mlx5_flow_attr *
4288mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4289{
4290 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4291 sizeof(struct mlx5_esw_flow_attr) :
4292 sizeof(struct mlx5_nic_flow_attr);
4293 struct mlx5_flow_attr *attr;
4294
4295 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4296}
4297
a88780a9
RD		 4298static int
4299mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4300 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4301 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4302 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4303{
17091853 4304 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4305 struct mlx5_flow_attr *attr;
3bc4b7bf 4306 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4307 int err = -ENOMEM;
4308 int out_index;
e3a2b7ed 4309
c620b772 4310 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4311 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4312 if (!parse_attr || !flow)
4313 goto err_free;
c620b772
AL		 4314
4315 flow->flags = flow_flags;
4316 flow->cookie = f->cookie;
4317 flow->priv = priv;
4318
4319 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4320 if (!attr)
e3a2b7ed 4321 goto err_free;
ff7ea04a 4322
c620b772 4323 flow->attr = attr;
e3a2b7ed 4324
5a7e5bcb
VB		 4325 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4326 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4327 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4328 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4329 refcount_set(&flow->refcnt, 1);
95435ad7 4330 init_completion(&flow->init_done);
909e615d 4331 init_completion(&flow->del_hw_done);
e3a2b7ed 4332
a88780a9
RD		 4333 *__flow = flow;
4334 *__parse_attr = parse_attr;
4335
4336 return 0;
4337
4338err_free:
4339 kfree(flow);
4340 kvfree(parse_attr);
4341 return err;
4342}
4343
c7569097
AL		 4344static void
4345mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4346 struct mlx5e_tc_flow_parse_attr *parse_attr,
4347 struct flow_cls_offload *f)
4348{
4349 attr->parse_attr = parse_attr;
4350 attr->chain = f->common.chain_index;
4351 attr->prio = f->common.prio;
4352}
4353
988ab9c7 4354static void
c620b772 4355mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4356 struct mlx5e_priv *priv,
4357 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4358 struct flow_cls_offload *f,
988ab9c7
TZ		 4359 struct mlx5_eswitch_rep *in_rep,
4360 struct mlx5_core_dev *in_mdev)
4361{
4362 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4363 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4364
c7569097 4365 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4366
4367 esw_attr->in_rep = in_rep;
4368 esw_attr->in_mdev = in_mdev;
4369
4370 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4371 MLX5_COUNTER_SOURCE_ESWITCH)
4372 esw_attr->counter_dev = in_mdev;
4373 else
4374 esw_attr->counter_dev = priv->mdev;
4375}
4376
71129676 4377static struct mlx5e_tc_flow *
04de7dda 4378__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4379 struct flow_cls_offload *f,
226f2ca3 4380 unsigned long flow_flags,
04de7dda
RD		 4381 struct net_device *filter_dev,
4382 struct mlx5_eswitch_rep *in_rep,
71129676 4383 struct mlx5_core_dev *in_mdev)
a88780a9 4384{
f9e30088 4385 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4386 struct netlink_ext_ack *extack = f->common.extack;
4387 struct mlx5e_tc_flow_parse_attr *parse_attr;
4388 struct mlx5e_tc_flow *flow;
4389 int attr_size, err;
e3a2b7ed 4390
226f2ca3 4391 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4392 attr_size = sizeof(struct mlx5_esw_flow_attr);
4393 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4394 &parse_attr, &flow);
4395 if (err)
4396 goto out;
988ab9c7 4397
d11afc26 4398 parse_attr->filter_dev = filter_dev;
c620b772 4399 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4400 priv, parse_attr,
4401 f, in_rep, in_mdev);
4402
54c177ca
OS		 4403 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4404 f, filter_dev);
d11afc26
OS		 4405 if (err)
4406 goto err_free;
a88780a9 4407
7e36feeb 4408 /* actions validation depends on parsing the ct matches first */
aedd133d 4409 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4410 &flow->attr->ct_attr, extack);
a88780a9
RD		 4411 if (err)
4412 goto err_free;
4413
70f8019e 4414 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 4415 if (err)
4416 goto err_free;
4417
7040632d 4418 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4419 complete_all(&flow->init_done);
ef06c9ee
RD		 4420 if (err) {
4421 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4422 goto err_free;
4423
b4a23329 4424 add_unready_flow(flow);
ef06c9ee 4425 }
e3a2b7ed 4426
71129676 4427 return flow;
a88780a9
RD		 4428
4429err_free:
5a7e5bcb 4430 mlx5e_flow_put(priv, flow);
a88780a9 4431out:
71129676 4432 return ERR_PTR(err);
a88780a9
RD		 4433}
4434
f9e30088 4435static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4436 struct mlx5e_tc_flow *flow,
226f2ca3 4437 unsigned long flow_flags)
04de7dda
RD		 4438{
4439 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4440 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4441 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4442 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4443 struct mlx5e_tc_flow_parse_attr *parse_attr;
4444 struct mlx5e_rep_priv *peer_urpriv;
4445 struct mlx5e_tc_flow *peer_flow;
4446 struct mlx5_core_dev *in_mdev;
4447 int err = 0;
4448
4449 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4450 if (!peer_esw)
4451 return -ENODEV;
4452
4453 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4454 peer_priv = netdev_priv(peer_urpriv->netdev);
4455
4456 /* in_mdev is assigned of which the packet originated from.
4457 * So packets redirected to uplink use the same mdev of the
4458 * original flow and packets redirected from uplink use the
4459 * peer mdev.
4460 */
c620b772 4461 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4462 in_mdev = peer_priv->mdev;
4463 else
4464 in_mdev = priv->mdev;
4465
c620b772 4466 parse_attr = flow->attr->parse_attr;
95dc1902 4467 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4468 parse_attr->filter_dev,
c620b772 4469 attr->in_rep, in_mdev);
71129676
JG		 4470 if (IS_ERR(peer_flow)) {
4471 err = PTR_ERR(peer_flow);
04de7dda 4472 goto out;
71129676 4473 }
04de7dda
RD		 4474
4475 flow->peer_flow = peer_flow;
226f2ca3 4476 flow_flag_set(flow, DUP);
04de7dda
RD		 4477 mutex_lock(&esw->offloads.peer_mutex);
4478 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4479 mutex_unlock(&esw->offloads.peer_mutex);
4480
4481out:
4482 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4483 return err;
4484}
4485
4486static int
4487mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4488 struct flow_cls_offload *f,
226f2ca3 4489 unsigned long flow_flags,
04de7dda
RD		 4490 struct net_device *filter_dev,
4491 struct mlx5e_tc_flow **__flow)
4492{
4493 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4494 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4495 struct mlx5_core_dev *in_mdev = priv->mdev;
4496 struct mlx5e_tc_flow *flow;
4497 int err;
4498
71129676
JG		 4499 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4500 in_mdev);
4501 if (IS_ERR(flow))
4502 return PTR_ERR(flow);
04de7dda
RD		 4503
4504 if (is_peer_flow_needed(flow)) {
95dc1902 4505 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4506 if (err) {
4507 mlx5e_tc_del_fdb_flow(priv, flow);
4508 goto out;
4509 }
4510 }
4511
4512 *__flow = flow;
4513
4514 return 0;
4515
4516out:
4517 return err;
4518}
4519
a88780a9
RD		 4520static int
4521mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4522 struct flow_cls_offload *f,
226f2ca3 4523 unsigned long flow_flags,
d11afc26 4524 struct net_device *filter_dev,
a88780a9
RD		 4525 struct mlx5e_tc_flow **__flow)
4526{
f9e30088 4527 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4528 struct netlink_ext_ack *extack = f->common.extack;
4529 struct mlx5e_tc_flow_parse_attr *parse_attr;
4530 struct mlx5e_tc_flow *flow;
4531 int attr_size, err;
4532
c7569097
AL		 4533 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4534 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4535 return -EOPNOTSUPP;
4536 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4537 return -EOPNOTSUPP;
c7569097 4538 }
bf07aa73 4539
226f2ca3 4540 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4541 attr_size = sizeof(struct mlx5_nic_flow_attr);
4542 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4543 &parse_attr, &flow);
4544 if (err)
4545 goto out;
4546
d11afc26 4547 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4548 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4549
54c177ca
OS		 4550 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4551 f, filter_dev);
d11afc26
OS		 4552 if (err)
4553 goto err_free;
4554
aedd133d
AL		 4555 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4556 &flow->attr->ct_attr, extack);
4557 if (err)
4558 goto err_free;
4559
c6cfe113 4560 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4561 if (err)
4562 goto err_free;
4563
c6cfe113 4564 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 4565 if (err)
4566 goto err_free;
4567
226f2ca3 4568 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4569 *__flow = flow;
4570
4571 return 0;
e3a2b7ed 4572
e3a2b7ed 4573err_free:
8914add2 4574 flow_flag_set(flow, FAILED);
e68e28b4 4575 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4576 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4577out:
4578 return err;
4579}
4580
4581static int
4582mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4583 struct flow_cls_offload *f,
226f2ca3 4584 unsigned long flags,
d11afc26 4585 struct net_device *filter_dev,
a88780a9
RD		 4586 struct mlx5e_tc_flow **flow)
4587{
4588 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4589 unsigned long flow_flags;
a88780a9
RD		 4590 int err;
4591
4592 get_flags(flags, &flow_flags);
4593
bf07aa73
PB		 4594 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4595 return -EOPNOTSUPP;
4596
f6455de0 4597 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4598 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4599 filter_dev, flow);
a88780a9 4600 else
d11afc26
OS		 4601 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4602 filter_dev, flow);
a88780a9
RD		 4603
4604 return err;
4605}
4606
553f9328
VP		 4607static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4608 struct mlx5e_rep_priv *rpriv)
4609{
4610 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4611 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4612 * function is called from NIC mode.
553f9328 4613 */
2fb15e72 4614 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4615}
4616
71d82d2a 4617int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4618 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4619{
4620 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4621 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4622 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4623 struct mlx5e_tc_flow *flow;
4624 int err = 0;
4625
7dc84de9
RD		 4626 if (!mlx5_esw_hold(priv->mdev))
4627 return -EAGAIN;
4628
4629 mlx5_esw_get(priv->mdev);
4630
c5d326b2
VB		 4631 rcu_read_lock();
4632 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4633 if (flow) {
553f9328
VP		 4634 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4635 * just return 0.
4636 */
4637 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4638 goto rcu_unlock;
553f9328 4639
a88780a9
RD		 4640 NL_SET_ERR_MSG_MOD(extack,
4641 "flow cookie already exists, ignoring");
4642 netdev_warn_once(priv->netdev,
4643 "flow cookie %lx already exists, ignoring\n",
4644 f->cookie);
0e1c1a2f 4645 err = -EEXIST;
c1aea9e1 4646 goto rcu_unlock;
a88780a9 4647 }
c1aea9e1
VB		 4648rcu_unlock:
4649 rcu_read_unlock();
4650 if (flow)
4651 goto out;
a88780a9 4652
7a978759 4653 trace_mlx5e_configure_flower(f);
d11afc26 4654 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4655 if (err)
4656 goto out;
4657
553f9328
VP		 4658 /* Flow rule offloaded to non-uplink representor sharing tc block,
4659 * set the flow's owner dev.
4660 */
4661 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4662 flow->orig_dev = dev;
4663
c5d326b2 4664 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4665 if (err)
4666 goto err_free;
4667
7dc84de9 4668 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4669 return 0;
4670
4671err_free:
5a7e5bcb 4672 mlx5e_flow_put(priv, flow);
a88780a9 4673out:
7dc84de9
RD		 4674 mlx5_esw_put(priv->mdev);
4675 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4676 return err;
4677}
4678
8f8ae895
OG		 4679static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4680{
226f2ca3
VB		 4681 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4682 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4683
226f2ca3
VB		 4684 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4685 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4686}
4687
71d82d2a 4688int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4689 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4690{
d9ee0491 4691 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4692 struct mlx5e_tc_flow *flow;
c5d326b2 4693 int err;
e3a2b7ed 4694
c5d326b2 4695 rcu_read_lock();
ab818362 4696 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4697 if (!flow || !same_flow_direction(flow, flags)) {
4698 err = -EINVAL;
4699 goto errout;
4700 }
e3a2b7ed 4701
c5d326b2
VB		 4702 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4703 * set.
4704 */
4705 if (flow_flag_test_and_set(flow, DELETED)) {
4706 err = -EINVAL;
4707 goto errout;
4708 }
05866c82 4709 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4710 rcu_read_unlock();
e3a2b7ed 4711
7a978759 4712 trace_mlx5e_delete_flower(f);
5a7e5bcb 4713 mlx5e_flow_put(priv, flow);
e3a2b7ed 4714
7dc84de9 4715 mlx5_esw_put(priv->mdev);
e3a2b7ed 4716 return 0;
c5d326b2
VB		 4717
4718errout:
4719 rcu_read_unlock();
4720 return err;
e3a2b7ed
AV		 4721}
4722
71d82d2a 4723int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4724 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4725{
04de7dda 4726 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4727 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4728 struct mlx5_eswitch *peer_esw;
aad7e08d 4729 struct mlx5e_tc_flow *flow;
aad7e08d 4730 struct mlx5_fc *counter;
316d5f72
RD		 4731 u64 lastuse = 0;
4732 u64 packets = 0;
4733 u64 bytes = 0;
5a7e5bcb 4734 int err = 0;
aad7e08d 4735
c5d326b2
VB		 4736 rcu_read_lock();
4737 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4738 tc_ht_params));
4739 rcu_read_unlock();
5a7e5bcb
VB		 4740 if (IS_ERR(flow))
4741 return PTR_ERR(flow);
4742
4743 if (!same_flow_direction(flow, flags)) {
4744 err = -EINVAL;
4745 goto errout;
4746 }
aad7e08d 4747
4c3844d9 4748 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4749 counter = mlx5e_tc_get_counter(flow);
4750 if (!counter)
5a7e5bcb 4751 goto errout;
aad7e08d 4752
316d5f72
RD		 4753 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4754 }
aad7e08d 4755
316d5f72
RD		 4756 /* Under multipath it's possible for one rule to be currently
4757 * un-offloaded while the other rule is offloaded.
4758 */
04de7dda
RD		 4759 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4760 if (!peer_esw)
4761 goto out;
4762
226f2ca3
VB		 4763 if (flow_flag_test(flow, DUP) &&
4764 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4765 u64 bytes2;
4766 u64 packets2;
4767 u64 lastuse2;
4768
4769 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4770 if (!counter)
4771 goto no_peer_counter;
04de7dda
RD		 4772 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4773
4774 bytes += bytes2;
4775 packets += packets2;
4776 lastuse = max_t(u64, lastuse, lastuse2);
4777 }
4778
316d5f72 4779no_peer_counter:
04de7dda 4780 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4781out:
4b61d3e8 4782 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4783 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4784 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4785errout:
4786 mlx5e_flow_put(priv, flow);
4787 return err;
aad7e08d
AV		 4788}
4789
1fe3e316 4790static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4791 struct netlink_ext_ack *extack)
4792{
4793 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4794 struct mlx5_eswitch *esw;
1fe3e316 4795 u32 rate_mbps = 0;
fcb64c0f 4796 u16 vport_num;
fcb64c0f
EC		 4797 int err;
4798
e401a184
EC		 4799 vport_num = rpriv->rep->vport;
4800 if (vport_num >= MLX5_VPORT_ECPF) {
4801 NL_SET_ERR_MSG_MOD(extack,
4802 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4803 return -EOPNOTSUPP;
4804 }
4805
fcb64c0f
EC		 4806 esw = priv->mdev->priv.eswitch;
4807 /* rate is given in bytes/sec.
4808 * First convert to bits/sec and then round to the nearest mbit/secs.
4809 * mbit means million bits.
4810 * Moreover, if rate is non zero we choose to configure to a minimum of
4811 * 1 mbit/sec.
4812 */
1fe3e316
PP		 4813 if (rate) {
4814 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4815 do_div(rate, 1000000);
4816 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4817 }
4818
2d116e3e 4819 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4820 if (err)
4821 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4822
4823 return err;
4824}
4825
4826static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4827 struct flow_action *flow_action,
4828 struct netlink_ext_ack *extack)
4829{
4830 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4831 const struct flow_action_entry *act;
4832 int err;
4833 int i;
4834
4835 if (!flow_action_has_entries(flow_action)) {
4836 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4837 return -EINVAL;
4838 }
4839
4840 if (!flow_offload_has_one_action(flow_action)) {
4841 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4842 return -EOPNOTSUPP;
4843 }
4844
53eca1f3 4845 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 4846 return -EOPNOTSUPP;
4847
fcb64c0f
EC		 4848 flow_action_for_each(i, act, flow_action) {
4849 switch (act->id) {
4850 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4851 if (act->police.rate_pkt_ps) {
4852 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4853 return -EOPNOTSUPP;
4854 }
fcb64c0f
EC		 4855 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4856 if (err)
4857 return err;
4858
4859 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4860 break;
4861 default:
4862 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4863 return -EOPNOTSUPP;
4864 }
4865 }
4866
4867 return 0;
4868}
4869
4870int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4871 struct tc_cls_matchall_offload *ma)
4872{
b5f814cc 4873 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4874 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4875
b5f814cc
EC		 4876 if (!mlx5_esw_qos_enabled(esw)) {
4877 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4878 return -EOPNOTSUPP;
4879 }
4880
7b83355f 4881 if (ma->common.prio != 1) {
fcb64c0f
EC		 4882 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4883 return -EINVAL;
4884 }
4885
4886 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4887}
4888
4889int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4890 struct tc_cls_matchall_offload *ma)
4891{
4892 struct netlink_ext_ack *extack = ma->common.extack;
4893
4894 return apply_police_params(priv, 0, extack);
4895}
4896
4897void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4898 struct tc_cls_matchall_offload *ma)
4899{
4900 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4901 struct rtnl_link_stats64 cur_stats;
4902 u64 dbytes;
4903 u64 dpkts;
4904
4905 cur_stats = priv->stats.vf_vport;
4906 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4907 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4908 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4909 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4910 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4911}
4912
4d8fcf21
AH		 4913static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4914 struct mlx5e_priv *peer_priv)
4915{
4916 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4917 struct mlx5e_hairpin_entry *hpe, *tmp;
4918 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4919 u16 peer_vhca_id;
4920 int bkt;
4921
4922 if (!same_hw_devs(priv, peer_priv))
4923 return;
4924
4925 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4926
b32accda 4927 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4928 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4929 if (refcount_inc_not_zero(&hpe->refcnt))
4930 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4931 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4932
4933 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4934 wait_for_completion(&hpe->res_ready);
4935 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4936 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4937
4938 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4939 }
4940}
4941
4942static int mlx5e_tc_netdev_event(struct notifier_block *this,
4943 unsigned long event, void *ptr)
4944{
4945 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4946 struct mlx5e_flow_steering *fs;
4947 struct mlx5e_priv *peer_priv;
4948 struct mlx5e_tc_table *tc;
4949 struct mlx5e_priv *priv;
4950
4951 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4952 event != NETDEV_UNREGISTER ||
4953 ndev->reg_state == NETREG_REGISTERED)
4954 return NOTIFY_DONE;
4955
4956 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4957 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4958 priv = container_of(fs, struct mlx5e_priv, fs);
4959 peer_priv = netdev_priv(ndev);
4960 if (priv == peer_priv ||
4961 !(priv->netdev->features & NETIF_F_HW_TC))
4962 return NOTIFY_DONE;
4963
4964 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4965
4966 return NOTIFY_DONE;
4967}
4968
6a064674
AL		 4969static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4970{
4971 int tc_grp_size, tc_tbl_size;
4972 u32 max_flow_counter;
4973
4974 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4975 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4976
4977 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4978
4979 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4980 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4981
4982 return tc_tbl_size;
4983}
4984
655dc3d2 4985int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4986{
acff797c 4987 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4988 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4989 struct mapping_ctx *chains_mapping;
6a064674 4990 struct mlx5_chains_attr attr = {};
2198b932 4991 u64 mapping_id;
4d8fcf21 4992 int err;
e8f887ac 4993
b2fdf3d0 4994 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4995 mutex_init(&tc->t_lock);
b32accda 4996 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4997 hash_init(tc->hairpin_tbl);
11c9c548 4998
4d8fcf21
AH		 4999 err = rhashtable_init(&tc->ht, &tc_ht_params);
5000 if (err)
5001 return err;
5002
9ba33339
RD		 5003 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5004
2198b932
RD		 5005 mapping_id = mlx5_query_nic_system_image_guid(dev);
5006
5007 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5008 sizeof(struct mlx5_mapped_obj),
5009 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5010
c9355682
CM		 5011 if (IS_ERR(chains_mapping)) {
5012 err = PTR_ERR(chains_mapping);
5013 goto err_mapping;
5014 }
5015 tc->mapping = chains_mapping;
5016
5017 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 5018 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5019 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 5020 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5021 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
5022 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 5023 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 5024 attr.mapping = chains_mapping;
6a064674
AL		 5025
5026 tc->chains = mlx5_chains_create(dev, &attr);
5027 if (IS_ERR(tc->chains)) {
5028 err = PTR_ERR(tc->chains);
5029 goto err_chains;
5030 }
5031
f0da4daa 5032 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 5033 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 5034 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 5035
4d8fcf21 5036 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 5037 err = register_netdevice_notifier_dev_net(priv->netdev,
5038 &tc->netdevice_nb,
5039 &tc->netdevice_nn);
5040 if (err) {
4d8fcf21
AH		 5041 tc->netdevice_nb.notifier_call = NULL;
5042 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 5043 goto err_reg;
4d8fcf21
AH		 5044 }
5045
6a064674
AL		 5046 return 0;
5047
5048err_reg:
aedd133d 5049 mlx5_tc_ct_clean(tc->ct);
f0da4daa 5050 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 5051 mlx5_chains_destroy(tc->chains);
5052err_chains:
c9355682
CM		 5053 mapping_destroy(chains_mapping);
5054err_mapping:
6a064674 5055 rhashtable_destroy(&tc->ht);
4d8fcf21 5056 return err;
e8f887ac
AV		 5057}
5058
5059static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5060{
5061 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5062 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5063
961e8979 5064 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5065 kfree(flow);
5066}
5067
655dc3d2 5068void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5069{
acff797c 5070 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5071
4d8fcf21 5072 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5073 unregister_netdevice_notifier_dev_net(priv->netdev,
5074 &tc->netdevice_nb,
5075 &tc->netdevice_nn);
4d8fcf21 5076
b2fdf3d0 5077 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 5078 mutex_destroy(&tc->hairpin_tbl_lock);
5079
6a064674 5080 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 5081
acff797c 5082 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 5083 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 5084 tc->t = NULL;
e8f887ac 5085 }
b6fac0b4 5086 mutex_destroy(&tc->t_lock);
6a064674 5087
aedd133d 5088 mlx5_tc_ct_clean(tc->ct);
f0da4daa 5089 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 5090 mapping_destroy(tc->mapping);
6a064674 5091 mlx5_chains_destroy(tc->chains);
e8f887ac 5092}
655dc3d2
OG		 5093
5094int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5095{
d7a42ad0 5096 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 5097 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 5098 struct mlx5e_rep_priv *rpriv;
0a7fcb78 5099 struct mapping_ctx *mapping;
aedd133d
AL		 5100 struct mlx5_eswitch *esw;
5101 struct mlx5e_priv *priv;
2198b932 5102 u64 mapping_id;
aedd133d 5103 int err = 0;
0a7fcb78
PB		 5104
5105 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5106 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5107 priv = netdev_priv(rpriv->netdev);
5108 esw = priv->mdev->priv.eswitch;
0a7fcb78 5109
f0da4daa
CM		 5110 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5111 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 5112 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5113 esw_chains(esw),
5114 &esw->offloads.mod_hdr,
f0da4daa
CM		 5115 MLX5_FLOW_NAMESPACE_FDB,
5116 uplink_priv->post_act);
4c3844d9 5117
2741f223 5118 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a 5119
2198b932
RD		 5120 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5121
5122 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5123 sizeof(struct tunnel_match_key),
5124 TUNNEL_INFO_BITS_MASK, true);
5125
0a7fcb78
PB		 5126 if (IS_ERR(mapping)) {
5127 err = PTR_ERR(mapping);
5128 goto err_tun_mapping;
5129 }
5130 uplink_priv->tunnel_mapping = mapping;
5131
8e404fef 5132 /* 0xFFF is reserved for stack devices slow path table mark */
2198b932
RD		 5133 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5134 sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
0a7fcb78
PB		 5135 if (IS_ERR(mapping)) {
5136 err = PTR_ERR(mapping);
5137 goto err_enc_opts_mapping;
5138 }
5139 uplink_priv->tunnel_enc_opts_mapping = mapping;
5140
5141 err = rhashtable_init(tc_ht, &tc_ht_params);
5142 if (err)
5143 goto err_ht_init;
5144
9ba33339
RD		 5145 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5146
8914add2 5147 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 5148 if (IS_ERR(uplink_priv->encap)) {
5149 err = PTR_ERR(uplink_priv->encap);
8914add2 5150 goto err_register_fib_notifier;
2b6c3c1e 5151 }
8914add2 5152
2b6c3c1e 5153 return 0;
0a7fcb78 5154
8914add2
VB		 5155err_register_fib_notifier:
5156 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5157err_ht_init:
5158 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5159err_enc_opts_mapping:
5160 mapping_destroy(uplink_priv->tunnel_mapping);
5161err_tun_mapping:
0027d70c 5162 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
aedd133d 5163 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5164 netdev_warn(priv->netdev,
5165 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 5166 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 5167 return err;
655dc3d2
OG		 5168}
5169
5170void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5171{
0a7fcb78
PB		 5172 struct mlx5_rep_uplink_priv *uplink_priv;
5173
0a7fcb78 5174 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5175
8914add2
VB		 5176 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5177 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5178
0a7fcb78
PB		 5179 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5180 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5181
0027d70c 5182 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
aedd133d 5183 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 5184 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 5185}
01252a27 5186
226f2ca3 5187int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5188{
d9ee0491 5189 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5190
5191 return atomic_read(&tc_ht->nelems);
5192}
04de7dda
RD		 5193
5194void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5195{
5196 struct mlx5e_tc_flow *flow, *tmp;
5197
5198 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5199 __mlx5e_tc_del_fdb_peer_flow(flow);
5200}
b4a23329
RD		 5201
5202void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5203{
5204 struct mlx5_rep_uplink_priv *rpriv =
5205 container_of(work, struct mlx5_rep_uplink_priv,
5206 reoffload_flows_work);
5207 struct mlx5e_tc_flow *flow, *tmp;
5208
ad86755b 5209 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5210 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5211 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5212 unready_flow_del(flow);
b4a23329 5213 }
ad86755b 5214 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5215}
e2394a61
VB		 5216
5217static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5218 struct flow_cls_offload *cls_flower,
5219 unsigned long flags)
5220{
5221 switch (cls_flower->command) {
5222 case FLOW_CLS_REPLACE:
5223 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5224 flags);
5225 case FLOW_CLS_DESTROY:
5226 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5227 flags);
5228 case FLOW_CLS_STATS:
5229 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5230 flags);
5231 default:
5232 return -EOPNOTSUPP;
5233 }
5234}
5235
5236int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5237 void *cb_priv)
5238{
ec9457a6 5239 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5240 struct mlx5e_priv *priv = cb_priv;
5241
2ff349c5
RD		 5242 if (!priv->netdev || !netif_device_present(priv->netdev))
5243 return -EOPNOTSUPP;
5244
ec9457a6
RD		 5245 if (mlx5e_is_uplink_rep(priv))
5246 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5247 else
5248 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5249
e2394a61
VB		 5250 switch (type) {
5251 case TC_SETUP_CLSFLOWER:
5252 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5253 default:
5254 return -EOPNOTSUPP;
5255 }
5256}
c7569097
AL		 5257
5258bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5259 struct sk_buff *skb)
5260{
5261#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5262 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5263 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5264 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5265 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5266 struct tc_skb_ext *tc_skb_ext;
5267 int err;
5268
5269 reg_b = be32_to_cpu(cqe->ft_metadata);
5270
5271 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5272
c9355682 5273 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5274 if (err) {
5275 netdev_dbg(priv->netdev,
5276 "Couldn't find chain for chain tag: %d, err: %d\n",
5277 chain_tag, err);
5278 return false;
5279 }
5280
a91d98a0
CM		 5281 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5282 chain = mapped_obj.chain;
9453d45e 5283 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5284 if (WARN_ON(!tc_skb_ext))
5285 return false;
5286
5287 tc_skb_ext->chain = chain;
aedd133d 5288
ed2fe7ba 5289 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5290 ESW_ZONE_ID_MASK;
aedd133d
AL		 5291
5292 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5293 zone_restore_id))
5294 return false;
a91d98a0
CM		 5295 } else {
5296 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5297 return false;
c7569097
AL		 5298 }
5299#endif /* CONFIG_NET_TC_SKB_EXT */
5300
5301 return true;
5302}
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