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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.c
CommitLineData
073bb189
SM		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
86d722ad 37#include <linux/mlx5/fs.h>
073bb189
SM		 38#include "mlx5_core.h"
39#include "eswitch.h"
40
81848731
SM		 41#define UPLINK_VPORT 0xFFFF
42
073bb189
SM		 43enum {
44 MLX5_ACTION_NONE = 0,
45 MLX5_ACTION_ADD = 1,
46 MLX5_ACTION_DEL = 2,
47};
48
81848731
SM		 49/* E-Switch UC L2 table hash node */
50struct esw_uc_addr {
073bb189 51 struct l2addr_node node;
073bb189
SM		 52 u32 table_index;
53 u32 vport;
54};
55
81848731
SM		 56/* E-Switch MC FDB table hash node */
57struct esw_mc_addr { /* SRIOV only */
58 struct l2addr_node node;
59 struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
60 u32 refcnt;
61};
62
63/* Vport UC/MC hash node */
64struct vport_addr {
65 struct l2addr_node node;
66 u8 action;
67 u32 vport;
68 struct mlx5_flow_rule *flow_rule; /* SRIOV only */
a35f71f2
MHY		 69 /* A flag indicating that mac was added due to mc promiscuous vport */
70 bool mc_promisc;
073bb189
SM		 71};
72
73enum {
74 UC_ADDR_CHANGE = BIT(0),
75 MC_ADDR_CHANGE = BIT(1),
a35f71f2 76 PROMISC_CHANGE = BIT(3),
073bb189
SM		 77};
78
81848731
SM		 79/* Vport context events */
80#define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
a35f71f2
MHY		 81 MC_ADDR_CHANGE | \
82 PROMISC_CHANGE)
81848731 83
c930a3ad
OG		 84int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
85void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
69697b6e 86
81848731 87static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
073bb189
SM		 88 u32 events_mask)
89{
90 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)];
91 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)];
92 void *nic_vport_ctx;
93 int err;
94
95 memset(out, 0, sizeof(out));
96 memset(in, 0, sizeof(in));
97
98 MLX5_SET(modify_nic_vport_context_in, in,
99 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
100 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
101 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
102 if (vport)
103 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
104 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
105 in, nic_vport_context);
106
107 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
108
109 if (events_mask & UC_ADDR_CHANGE)
110 MLX5_SET(nic_vport_context, nic_vport_ctx,
111 event_on_uc_address_change, 1);
112 if (events_mask & MC_ADDR_CHANGE)
113 MLX5_SET(nic_vport_context, nic_vport_ctx,
114 event_on_mc_address_change, 1);
a35f71f2
MHY		 115 if (events_mask & PROMISC_CHANGE)
116 MLX5_SET(nic_vport_context, nic_vport_ctx,
117 event_on_promisc_change, 1);
073bb189
SM		 118
119 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
120 if (err)
121 goto ex;
122 err = mlx5_cmd_status_to_err_v2(out);
123 if (err)
124 goto ex;
125 return 0;
126ex:
127 return err;
128}
129
9e7ea352
SM		 130/* E-Switch vport context HW commands */
131static int query_esw_vport_context_cmd(struct mlx5_core_dev *mdev, u32 vport,
132 u32 *out, int outlen)
133{
134 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)];
135
136 memset(in, 0, sizeof(in));
137
138 MLX5_SET(query_nic_vport_context_in, in, opcode,
139 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
140
141 MLX5_SET(query_esw_vport_context_in, in, vport_number, vport);
142 if (vport)
143 MLX5_SET(query_esw_vport_context_in, in, other_vport, 1);
144
145 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in), out, outlen);
146}
147
148static int query_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
149 u16 *vlan, u8 *qos)
150{
151 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)];
152 int err;
153 bool cvlan_strip;
154 bool cvlan_insert;
155
156 memset(out, 0, sizeof(out));
157
158 *vlan = 0;
159 *qos = 0;
160
161 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
162 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
163 return -ENOTSUPP;
164
165 err = query_esw_vport_context_cmd(dev, vport, out, sizeof(out));
166 if (err)
167 goto out;
168
169 cvlan_strip = MLX5_GET(query_esw_vport_context_out, out,
170 esw_vport_context.vport_cvlan_strip);
171
172 cvlan_insert = MLX5_GET(query_esw_vport_context_out, out,
173 esw_vport_context.vport_cvlan_insert);
174
175 if (cvlan_strip || cvlan_insert) {
176 *vlan = MLX5_GET(query_esw_vport_context_out, out,
177 esw_vport_context.cvlan_id);
178 *qos = MLX5_GET(query_esw_vport_context_out, out,
179 esw_vport_context.cvlan_pcp);
180 }
181
182 esw_debug(dev, "Query Vport[%d] cvlan: VLAN %d qos=%d\n",
183 vport, *vlan, *qos);
184out:
185 return err;
186}
187
188static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
189 void *in, int inlen)
190{
191 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)];
192
193 memset(out, 0, sizeof(out));
194
195 MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
196 if (vport)
197 MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
198
199 MLX5_SET(modify_esw_vport_context_in, in, opcode,
200 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
201
202 return mlx5_cmd_exec_check_status(dev, in, inlen,
203 out, sizeof(out));
204}
205
206static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
207 u16 vlan, u8 qos, bool set)
208{
209 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)];
210
211 memset(in, 0, sizeof(in));
212
213 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
214 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
215 return -ENOTSUPP;
216
217 esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%d\n",
218 vport, vlan, qos, set);
219
220 if (set) {
221 MLX5_SET(modify_esw_vport_context_in, in,
222 esw_vport_context.vport_cvlan_strip, 1);
223 /* insert only if no vlan in packet */
224 MLX5_SET(modify_esw_vport_context_in, in,
225 esw_vport_context.vport_cvlan_insert, 1);
226 MLX5_SET(modify_esw_vport_context_in, in,
227 esw_vport_context.cvlan_pcp, qos);
228 MLX5_SET(modify_esw_vport_context_in, in,
229 esw_vport_context.cvlan_id, vlan);
230 }
231
232 MLX5_SET(modify_esw_vport_context_in, in,
233 field_select.vport_cvlan_strip, 1);
234 MLX5_SET(modify_esw_vport_context_in, in,
235 field_select.vport_cvlan_insert, 1);
236
237 return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
238}
239
073bb189
SM		 240/* HW L2 Table (MPFS) management */
241static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
242 u8 *mac, u8 vlan_valid, u16 vlan)
243{
244 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)];
245 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)];
246 u8 *in_mac_addr;
247
248 memset(in, 0, sizeof(in));
249 memset(out, 0, sizeof(out));
250
251 MLX5_SET(set_l2_table_entry_in, in, opcode,
252 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
253 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
254 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
255 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
256
257 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
258 ether_addr_copy(&in_mac_addr[2], mac);
259
260 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
261 out, sizeof(out));
262}
263
264static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
265{
266 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)];
267 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)];
268
269 memset(in, 0, sizeof(in));
270 memset(out, 0, sizeof(out));
271
272 MLX5_SET(delete_l2_table_entry_in, in, opcode,
273 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
274 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
275 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
276 out, sizeof(out));
277}
278
279static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
280{
281 int err = 0;
282
283 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
284 if (*ix >= l2_table->size)
285 err = -ENOSPC;
286 else
287 __set_bit(*ix, l2_table->bitmap);
288
289 return err;
290}
291
292static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
293{
294 __clear_bit(ix, l2_table->bitmap);
295}
296
297static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
298 u8 vlan_valid, u16 vlan,
299 u32 *index)
300{
301 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
302 int err;
303
304 err = alloc_l2_table_index(l2_table, index);
305 if (err)
306 return err;
307
308 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
309 if (err)
310 free_l2_table_index(l2_table, *index);
311
312 return err;
313}
314
315static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
316{
317 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
318
319 del_l2_table_entry_cmd(dev, index);
320 free_l2_table_index(l2_table, index);
321}
322
81848731
SM		 323/* E-Switch FDB */
324static struct mlx5_flow_rule *
a35f71f2 325__esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
78a9199b 326 u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
81848731 327{
78a9199b
MHY		 328 int match_header = (is_zero_ether_addr(mac_c) ? 0 :
329 MLX5_MATCH_OUTER_HEADERS);
81848731 330 struct mlx5_flow_rule *flow_rule = NULL;
78a9199b 331 struct mlx5_flow_destination dest;
c5bb1730 332 struct mlx5_flow_spec *spec;
a35f71f2
MHY		 333 void *mv_misc = NULL;
334 void *mc_misc = NULL;
78a9199b
MHY		 335 u8 *dmac_v = NULL;
336 u8 *dmac_c = NULL;
81848731 337
a35f71f2
MHY		 338 if (rx_rule)
339 match_header |= MLX5_MATCH_MISC_PARAMETERS;
c5bb1730
MG		 340
341 spec = mlx5_vzalloc(sizeof(*spec));
342 if (!spec) {
81848731 343 pr_warn("FDB: Failed to alloc match parameters\n");
c5bb1730 344 return NULL;
81848731 345 }
c5bb1730 346 dmac_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
81848731 347 outer_headers.dmac_47_16);
c5bb1730 348 dmac_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
81848731
SM		 349 outer_headers.dmac_47_16);
350
a35f71f2 351 if (match_header & MLX5_MATCH_OUTER_HEADERS) {
78a9199b
MHY		 352 ether_addr_copy(dmac_v, mac_v);
353 ether_addr_copy(dmac_c, mac_c);
354 }
81848731 355
a35f71f2 356 if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
c5bb1730
MG		 357 mv_misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
358 misc_parameters);
359 mc_misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
360 misc_parameters);
a35f71f2
MHY		 361 MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
362 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
363 }
364
81848731
SM		 365 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
366 dest.vport_num = vport;
367
368 esw_debug(esw->dev,
369 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
370 dmac_v, dmac_c, vport);
c5bb1730 371 spec->match_criteria_enable = match_header;
81848731 372 flow_rule =
c5bb1730 373 mlx5_add_flow_rule(esw->fdb_table.fdb, spec,
81848731
SM		 374 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
375 0, &dest);
3f42ac66 376 if (IS_ERR(flow_rule)) {
81848731
SM		 377 pr_warn(
378 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
379 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
380 flow_rule = NULL;
381 }
c5bb1730
MG		 382
383 kvfree(spec);
81848731
SM		 384 return flow_rule;
385}
386
78a9199b
MHY		 387static struct mlx5_flow_rule *
388esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
389{
390 u8 mac_c[ETH_ALEN];
391
392 eth_broadcast_addr(mac_c);
a35f71f2
MHY		 393 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
394}
395
396static struct mlx5_flow_rule *
397esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
398{
399 u8 mac_c[ETH_ALEN];
400 u8 mac_v[ETH_ALEN];
401
402 eth_zero_addr(mac_c);
403 eth_zero_addr(mac_v);
404 mac_c[0] = 0x01;
405 mac_v[0] = 0x01;
406 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
407}
408
409static struct mlx5_flow_rule *
410esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
411{
412 u8 mac_c[ETH_ALEN];
413 u8 mac_v[ETH_ALEN];
414
415 eth_zero_addr(mac_c);
416 eth_zero_addr(mac_v);
417 return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
78a9199b
MHY		 418}
419
6ab36e35 420static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports)
81848731 421{
86d722ad 422 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
81848731 423 struct mlx5_core_dev *dev = esw->dev;
86d722ad 424 struct mlx5_flow_namespace *root_ns;
81848731 425 struct mlx5_flow_table *fdb;
86d722ad
MG		 426 struct mlx5_flow_group *g;
427 void *match_criteria;
428 int table_size;
429 u32 *flow_group_in;
81848731 430 u8 *dmac;
86d722ad 431 int err = 0;
81848731
SM		 432
433 esw_debug(dev, "Create FDB log_max_size(%d)\n",
434 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
435
86d722ad
MG		 436 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
437 if (!root_ns) {
438 esw_warn(dev, "Failed to get FDB flow namespace\n");
439 return -ENOMEM;
440 }
81848731 441
86d722ad
MG		 442 flow_group_in = mlx5_vzalloc(inlen);
443 if (!flow_group_in)
444 return -ENOMEM;
445 memset(flow_group_in, 0, inlen);
446
447 table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
d63cd286 448 fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0);
3f42ac66 449 if (IS_ERR(fdb)) {
86d722ad
MG		 450 err = PTR_ERR(fdb);
451 esw_warn(dev, "Failed to create FDB Table err %d\n", err);
452 goto out;
453 }
78a9199b 454 esw->fdb_table.fdb = fdb;
81848731 455
78a9199b 456 /* Addresses group : Full match unicast/multicast addresses */
86d722ad
MG		 457 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
458 MLX5_MATCH_OUTER_HEADERS);
459 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
460 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
461 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
78a9199b
MHY		 462 /* Preserve 2 entries for allmulti and promisc rules*/
463 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
86d722ad 464 eth_broadcast_addr(dmac);
86d722ad 465 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 466 if (IS_ERR(g)) {
86d722ad
MG		 467 err = PTR_ERR(g);
468 esw_warn(dev, "Failed to create flow group err(%d)\n", err);
469 goto out;
470 }
6ab36e35 471 esw->fdb_table.legacy.addr_grp = g;
78a9199b
MHY		 472
473 /* Allmulti group : One rule that forwards any mcast traffic */
474 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
475 MLX5_MATCH_OUTER_HEADERS);
476 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
477 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
478 eth_zero_addr(dmac);
479 dmac[0] = 0x01;
480 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 481 if (IS_ERR(g)) {
78a9199b
MHY		 482 err = PTR_ERR(g);
483 esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
484 goto out;
485 }
6ab36e35 486 esw->fdb_table.legacy.allmulti_grp = g;
78a9199b
MHY		 487
488 /* Promiscuous group :
489 * One rule that forward all unmatched traffic from previous groups
490 */
491 eth_zero_addr(dmac);
492 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
493 MLX5_MATCH_MISC_PARAMETERS);
494 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
495 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
496 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
497 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 498 if (IS_ERR(g)) {
78a9199b
MHY		 499 err = PTR_ERR(g);
500 esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
501 goto out;
502 }
6ab36e35 503 esw->fdb_table.legacy.promisc_grp = g;
78a9199b 504
86d722ad 505out:
78a9199b 506 if (err) {
6ab36e35
OG		 507 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) {
508 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
509 esw->fdb_table.legacy.allmulti_grp = NULL;
78a9199b 510 }
6ab36e35
OG		 511 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) {
512 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
513 esw->fdb_table.legacy.addr_grp = NULL;
78a9199b
MHY		 514 }
515 if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
516 mlx5_destroy_flow_table(esw->fdb_table.fdb);
517 esw->fdb_table.fdb = NULL;
518 }
519 }
520
3fe3d819 521 kvfree(flow_group_in);
86d722ad 522 return err;
81848731
SM		 523}
524
6ab36e35 525static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw)
81848731
SM		 526{
527 if (!esw->fdb_table.fdb)
528 return;
529
86d722ad 530 esw_debug(esw->dev, "Destroy FDB Table\n");
6ab36e35
OG		 531 mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp);
532 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
533 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
81848731
SM		 534 mlx5_destroy_flow_table(esw->fdb_table.fdb);
535 esw->fdb_table.fdb = NULL;
6ab36e35
OG		 536 esw->fdb_table.legacy.addr_grp = NULL;
537 esw->fdb_table.legacy.allmulti_grp = NULL;
538 esw->fdb_table.legacy.promisc_grp = NULL;
81848731
SM		 539}
540
541/* E-Switch vport UC/MC lists management */
542typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
543 struct vport_addr *vaddr);
544
545static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
546{
547 struct hlist_head *hash = esw->l2_table.l2_hash;
548 struct esw_uc_addr *esw_uc;
549 u8 *mac = vaddr->node.addr;
550 u32 vport = vaddr->vport;
551 int err;
552
553 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
554 if (esw_uc) {
073bb189
SM		 555 esw_warn(esw->dev,
556 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
81848731 557 mac, vport, esw_uc->vport);
073bb189
SM		 558 return -EEXIST;
559 }
560
81848731
SM		 561 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
562 if (!esw_uc)
073bb189 563 return -ENOMEM;
81848731 564 esw_uc->vport = vport;
073bb189 565
81848731 566 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
073bb189 567 if (err)
81848731
SM		 568 goto abort;
569
69697b6e
OG		 570 /* SRIOV is enabled: Forward UC MAC to vport */
571 if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY)
81848731
SM		 572 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
573
574 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
575 vport, mac, esw_uc->table_index, vaddr->flow_rule);
576 return err;
577abort:
578 l2addr_hash_del(esw_uc);
073bb189
SM		 579 return err;
580}
581
81848731 582static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
073bb189 583{
81848731
SM		 584 struct hlist_head *hash = esw->l2_table.l2_hash;
585 struct esw_uc_addr *esw_uc;
586 u8 *mac = vaddr->node.addr;
587 u32 vport = vaddr->vport;
588
589 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
590 if (!esw_uc || esw_uc->vport != vport) {
591 esw_debug(esw->dev,
592 "MAC(%pM) doesn't belong to vport (%d)\n",
593 mac, vport);
594 return -EINVAL;
595 }
596 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
597 vport, mac, esw_uc->table_index, vaddr->flow_rule);
598
599 del_l2_table_entry(esw->dev, esw_uc->table_index);
600
601 if (vaddr->flow_rule)
86d722ad 602 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 603 vaddr->flow_rule = NULL;
604
605 l2addr_hash_del(esw_uc);
606 return 0;
607}
608
a35f71f2
MHY		 609static void update_allmulti_vports(struct mlx5_eswitch *esw,
610 struct vport_addr *vaddr,
611 struct esw_mc_addr *esw_mc)
612{
613 u8 *mac = vaddr->node.addr;
614 u32 vport_idx = 0;
615
616 for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
617 struct mlx5_vport *vport = &esw->vports[vport_idx];
618 struct hlist_head *vport_hash = vport->mc_list;
619 struct vport_addr *iter_vaddr =
620 l2addr_hash_find(vport_hash,
621 mac,
622 struct vport_addr);
623 if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
624 vaddr->vport == vport_idx)
625 continue;
626 switch (vaddr->action) {
627 case MLX5_ACTION_ADD:
628 if (iter_vaddr)
629 continue;
630 iter_vaddr = l2addr_hash_add(vport_hash, mac,
631 struct vport_addr,
632 GFP_KERNEL);
633 if (!iter_vaddr) {
634 esw_warn(esw->dev,
635 "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
636 mac, vport_idx);
637 continue;
638 }
639 iter_vaddr->vport = vport_idx;
640 iter_vaddr->flow_rule =
641 esw_fdb_set_vport_rule(esw,
642 mac,
643 vport_idx);
62e3c24a 644 iter_vaddr->mc_promisc = true;
a35f71f2
MHY		 645 break;
646 case MLX5_ACTION_DEL:
647 if (!iter_vaddr)
648 continue;
649 mlx5_del_flow_rule(iter_vaddr->flow_rule);
650 l2addr_hash_del(iter_vaddr);
651 break;
652 }
653 }
654}
655
81848731
SM		 656static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
657{
658 struct hlist_head *hash = esw->mc_table;
659 struct esw_mc_addr *esw_mc;
660 u8 *mac = vaddr->node.addr;
661 u32 vport = vaddr->vport;
662
663 if (!esw->fdb_table.fdb)
664 return 0;
665
666 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
667 if (esw_mc)
668 goto add;
669
670 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
671 if (!esw_mc)
672 return -ENOMEM;
673
674 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
675 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
a35f71f2
MHY		 676
677 /* Add this multicast mac to all the mc promiscuous vports */
678 update_allmulti_vports(esw, vaddr, esw_mc);
679
81848731 680add:
a35f71f2
MHY		 681 /* If the multicast mac is added as a result of mc promiscuous vport,
682 * don't increment the multicast ref count
683 */
684 if (!vaddr->mc_promisc)
685 esw_mc->refcnt++;
686
81848731
SM		 687 /* Forward MC MAC to vport */
688 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
689 esw_debug(esw->dev,
690 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
691 vport, mac, vaddr->flow_rule,
692 esw_mc->refcnt, esw_mc->uplink_rule);
693 return 0;
694}
695
696static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
697{
698 struct hlist_head *hash = esw->mc_table;
699 struct esw_mc_addr *esw_mc;
700 u8 *mac = vaddr->node.addr;
701 u32 vport = vaddr->vport;
073bb189 702
81848731
SM		 703 if (!esw->fdb_table.fdb)
704 return 0;
705
706 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
707 if (!esw_mc) {
708 esw_warn(esw->dev,
709 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
073bb189
SM		 710 mac, vport);
711 return -EINVAL;
712 }
81848731
SM		 713 esw_debug(esw->dev,
714 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
715 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
716 esw_mc->uplink_rule);
717
718 if (vaddr->flow_rule)
86d722ad 719 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 720 vaddr->flow_rule = NULL;
721
a35f71f2
MHY		 722 /* If the multicast mac is added as a result of mc promiscuous vport,
723 * don't decrement the multicast ref count.
724 */
725 if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
81848731 726 return 0;
073bb189 727
a35f71f2
MHY		 728 /* Remove this multicast mac from all the mc promiscuous vports */
729 update_allmulti_vports(esw, vaddr, esw_mc);
730
81848731 731 if (esw_mc->uplink_rule)
86d722ad 732 mlx5_del_flow_rule(esw_mc->uplink_rule);
81848731
SM		 733
734 l2addr_hash_del(esw_mc);
073bb189
SM		 735 return 0;
736}
737
81848731
SM		 738/* Apply vport UC/MC list to HW l2 table and FDB table */
739static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
740 u32 vport_num, int list_type)
073bb189
SM		 741{
742 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731
SM		 743 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
744 vport_addr_action vport_addr_add;
745 vport_addr_action vport_addr_del;
746 struct vport_addr *addr;
073bb189
SM		 747 struct l2addr_node *node;
748 struct hlist_head *hash;
749 struct hlist_node *tmp;
750 int hi;
751
81848731
SM		 752 vport_addr_add = is_uc ? esw_add_uc_addr :
753 esw_add_mc_addr;
754 vport_addr_del = is_uc ? esw_del_uc_addr :
755 esw_del_mc_addr;
756
757 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189 758 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 759 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 760 switch (addr->action) {
761 case MLX5_ACTION_ADD:
81848731 762 vport_addr_add(esw, addr);
073bb189
SM		 763 addr->action = MLX5_ACTION_NONE;
764 break;
765 case MLX5_ACTION_DEL:
81848731 766 vport_addr_del(esw, addr);
073bb189
SM		 767 l2addr_hash_del(addr);
768 break;
769 }
770 }
771}
772
81848731
SM		 773/* Sync vport UC/MC list from vport context */
774static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
775 u32 vport_num, int list_type)
073bb189
SM		 776{
777 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731 778 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
073bb189 779 u8 (*mac_list)[ETH_ALEN];
81848731
SM		 780 struct l2addr_node *node;
781 struct vport_addr *addr;
073bb189
SM		 782 struct hlist_head *hash;
783 struct hlist_node *tmp;
784 int size;
785 int err;
786 int hi;
787 int i;
788
81848731
SM		 789 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
790 MLX5_MAX_MC_PER_VPORT(esw->dev);
073bb189
SM		 791
792 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
793 if (!mac_list)
794 return;
795
81848731 796 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189
SM		 797
798 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 799 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 800 addr->action = MLX5_ACTION_DEL;
801 }
802
586cfa7f
MHY		 803 if (!vport->enabled)
804 goto out;
805
81848731 806 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
073bb189
SM		 807 mac_list, &size);
808 if (err)
761e205b 809 goto out;
81848731
SM		 810 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
811 vport_num, is_uc ? "UC" : "MC", size);
073bb189
SM		 812
813 for (i = 0; i < size; i++) {
81848731 814 if (is_uc && !is_valid_ether_addr(mac_list[i]))
073bb189
SM		 815 continue;
816
81848731
SM		 817 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
818 continue;
819
820 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
073bb189
SM		 821 if (addr) {
822 addr->action = MLX5_ACTION_NONE;
a35f71f2
MHY		 823 /* If this mac was previously added because of allmulti
824 * promiscuous rx mode, its now converted to be original
825 * vport mac.
826 */
827 if (addr->mc_promisc) {
828 struct esw_mc_addr *esw_mc =
829 l2addr_hash_find(esw->mc_table,
830 mac_list[i],
831 struct esw_mc_addr);
832 if (!esw_mc) {
833 esw_warn(esw->dev,
834 "Failed to MAC(%pM) in mcast DB\n",
835 mac_list[i]);
836 continue;
837 }
838 esw_mc->refcnt++;
839 addr->mc_promisc = false;
840 }
073bb189
SM		 841 continue;
842 }
843
81848731 844 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
073bb189
SM		 845 GFP_KERNEL);
846 if (!addr) {
847 esw_warn(esw->dev,
848 "Failed to add MAC(%pM) to vport[%d] DB\n",
849 mac_list[i], vport_num);
850 continue;
851 }
81848731 852 addr->vport = vport_num;
073bb189
SM		 853 addr->action = MLX5_ACTION_ADD;
854 }
761e205b 855out:
073bb189
SM		 856 kfree(mac_list);
857}
858
a35f71f2
MHY		 859/* Sync vport UC/MC list from vport context
860 * Must be called after esw_update_vport_addr_list
861 */
862static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
863{
864 struct mlx5_vport *vport = &esw->vports[vport_num];
865 struct l2addr_node *node;
866 struct vport_addr *addr;
867 struct hlist_head *hash;
868 struct hlist_node *tmp;
869 int hi;
870
871 hash = vport->mc_list;
872
873 for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
874 u8 *mac = node->addr;
875
876 addr = l2addr_hash_find(hash, mac, struct vport_addr);
877 if (addr) {
878 if (addr->action == MLX5_ACTION_DEL)
879 addr->action = MLX5_ACTION_NONE;
880 continue;
881 }
882 addr = l2addr_hash_add(hash, mac, struct vport_addr,
883 GFP_KERNEL);
884 if (!addr) {
885 esw_warn(esw->dev,
886 "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
887 mac, vport_num);
888 continue;
889 }
890 addr->vport = vport_num;
891 addr->action = MLX5_ACTION_ADD;
892 addr->mc_promisc = true;
893 }
894}
895
896/* Apply vport rx mode to HW FDB table */
897static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
898 bool promisc, bool mc_promisc)
899{
900 struct esw_mc_addr *allmulti_addr = esw->mc_promisc;
901 struct mlx5_vport *vport = &esw->vports[vport_num];
902
903 if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
904 goto promisc;
905
906 if (mc_promisc) {
907 vport->allmulti_rule =
908 esw_fdb_set_vport_allmulti_rule(esw, vport_num);
909 if (!allmulti_addr->uplink_rule)
910 allmulti_addr->uplink_rule =
911 esw_fdb_set_vport_allmulti_rule(esw,
912 UPLINK_VPORT);
913 allmulti_addr->refcnt++;
914 } else if (vport->allmulti_rule) {
915 mlx5_del_flow_rule(vport->allmulti_rule);
916 vport->allmulti_rule = NULL;
917
918 if (--allmulti_addr->refcnt > 0)
919 goto promisc;
920
921 if (allmulti_addr->uplink_rule)
922 mlx5_del_flow_rule(allmulti_addr->uplink_rule);
923 allmulti_addr->uplink_rule = NULL;
924 }
925
926promisc:
927 if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
928 return;
929
930 if (promisc) {
931 vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
932 vport_num);
933 } else if (vport->promisc_rule) {
934 mlx5_del_flow_rule(vport->promisc_rule);
935 vport->promisc_rule = NULL;
936 }
937}
938
939/* Sync vport rx mode from vport context */
940static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
941{
942 struct mlx5_vport *vport = &esw->vports[vport_num];
943 int promisc_all = 0;
944 int promisc_uc = 0;
945 int promisc_mc = 0;
946 int err;
947
948 err = mlx5_query_nic_vport_promisc(esw->dev,
949 vport_num,
950 &promisc_uc,
951 &promisc_mc,
952 &promisc_all);
953 if (err)
954 return;
955 esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
956 vport_num, promisc_all, promisc_mc);
957
958 if (!vport->trusted || !vport->enabled) {
959 promisc_uc = 0;
960 promisc_mc = 0;
961 promisc_all = 0;
962 }
963
964 esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
965 (promisc_all || promisc_mc));
966}
967
1edc57e2 968static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
073bb189 969{
073bb189 970 struct mlx5_core_dev *dev = vport->dev;
81848731 971 struct mlx5_eswitch *esw = dev->priv.eswitch;
073bb189
SM		 972 u8 mac[ETH_ALEN];
973
974 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
81848731
SM		 975 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
976 vport->vport, mac);
977
978 if (vport->enabled_events & UC_ADDR_CHANGE) {
979 esw_update_vport_addr_list(esw, vport->vport,
980 MLX5_NVPRT_LIST_TYPE_UC);
981 esw_apply_vport_addr_list(esw, vport->vport,
982 MLX5_NVPRT_LIST_TYPE_UC);
983 }
073bb189 984
81848731
SM		 985 if (vport->enabled_events & MC_ADDR_CHANGE) {
986 esw_update_vport_addr_list(esw, vport->vport,
987 MLX5_NVPRT_LIST_TYPE_MC);
a35f71f2
MHY		 988 }
989
990 if (vport->enabled_events & PROMISC_CHANGE) {
991 esw_update_vport_rx_mode(esw, vport->vport);
992 if (!IS_ERR_OR_NULL(vport->allmulti_rule))
993 esw_update_vport_mc_promisc(esw, vport->vport);
994 }
995
996 if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
81848731
SM		 997 esw_apply_vport_addr_list(esw, vport->vport,
998 MLX5_NVPRT_LIST_TYPE_MC);
999 }
073bb189 1000
81848731 1001 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
073bb189
SM		 1002 if (vport->enabled)
1003 arm_vport_context_events_cmd(dev, vport->vport,
81848731 1004 vport->enabled_events);
073bb189
SM		 1005}
1006
1edc57e2
MHY		 1007static void esw_vport_change_handler(struct work_struct *work)
1008{
1009 struct mlx5_vport *vport =
1010 container_of(work, struct mlx5_vport, vport_change_handler);
1011 struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
1012
1013 mutex_lock(&esw->state_lock);
1014 esw_vport_change_handle_locked(vport);
1015 mutex_unlock(&esw->state_lock);
1016}
1017
5742df0f
MHY		 1018static void esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
1019 struct mlx5_vport *vport)
1020{
1021 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1022 struct mlx5_flow_group *vlan_grp = NULL;
1023 struct mlx5_flow_group *drop_grp = NULL;
1024 struct mlx5_core_dev *dev = esw->dev;
1025 struct mlx5_flow_namespace *root_ns;
1026 struct mlx5_flow_table *acl;
1027 void *match_criteria;
1028 u32 *flow_group_in;
1029 /* The egress acl table contains 2 rules:
1030 * 1)Allow traffic with vlan_tag=vst_vlan_id
1031 * 2)Drop all other traffic.
1032 */
1033 int table_size = 2;
1034 int err = 0;
1035
01f51f22
MHY		 1036 if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support) ||
1037 !IS_ERR_OR_NULL(vport->egress.acl))
5742df0f
MHY		 1038 return;
1039
1040 esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
1041 vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
1042
1043 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
1044 if (!root_ns) {
1045 esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
1046 return;
1047 }
1048
1049 flow_group_in = mlx5_vzalloc(inlen);
1050 if (!flow_group_in)
1051 return;
1052
1053 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1054 if (IS_ERR(acl)) {
5742df0f
MHY		 1055 err = PTR_ERR(acl);
1056 esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
1057 vport->vport, err);
1058 goto out;
1059 }
1060
1061 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1062 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1063 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1064 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
1065 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1066 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1067
1068 vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1069 if (IS_ERR(vlan_grp)) {
5742df0f
MHY		 1070 err = PTR_ERR(vlan_grp);
1071 esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
1072 vport->vport, err);
1073 goto out;
1074 }
1075
1076 memset(flow_group_in, 0, inlen);
1077 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1078 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1079 drop_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1080 if (IS_ERR(drop_grp)) {
5742df0f
MHY		 1081 err = PTR_ERR(drop_grp);
1082 esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
1083 vport->vport, err);
1084 goto out;
1085 }
1086
1087 vport->egress.acl = acl;
1088 vport->egress.drop_grp = drop_grp;
1089 vport->egress.allowed_vlans_grp = vlan_grp;
1090out:
3fe3d819 1091 kvfree(flow_group_in);
5742df0f
MHY		 1092 if (err && !IS_ERR_OR_NULL(vlan_grp))
1093 mlx5_destroy_flow_group(vlan_grp);
1094 if (err && !IS_ERR_OR_NULL(acl))
1095 mlx5_destroy_flow_table(acl);
1096}
1097
dfcb1ed3
MHY		 1098static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
1099 struct mlx5_vport *vport)
1100{
1101 if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
1102 mlx5_del_flow_rule(vport->egress.allowed_vlan);
1103
1104 if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
1105 mlx5_del_flow_rule(vport->egress.drop_rule);
1106
1107 vport->egress.allowed_vlan = NULL;
1108 vport->egress.drop_rule = NULL;
1109}
1110
5742df0f
MHY		 1111static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
1112 struct mlx5_vport *vport)
1113{
1114 if (IS_ERR_OR_NULL(vport->egress.acl))
1115 return;
1116
1117 esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
1118
dfcb1ed3 1119 esw_vport_cleanup_egress_rules(esw, vport);
5742df0f
MHY		 1120 mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
1121 mlx5_destroy_flow_group(vport->egress.drop_grp);
1122 mlx5_destroy_flow_table(vport->egress.acl);
1123 vport->egress.allowed_vlans_grp = NULL;
1124 vport->egress.drop_grp = NULL;
1125 vport->egress.acl = NULL;
1126}
1127
1128static void esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
1129 struct mlx5_vport *vport)
1130{
1131 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1132 struct mlx5_core_dev *dev = esw->dev;
1133 struct mlx5_flow_namespace *root_ns;
1134 struct mlx5_flow_table *acl;
1135 struct mlx5_flow_group *g;
1136 void *match_criteria;
1137 u32 *flow_group_in;
1138 /* The ingress acl table contains 4 groups
1139 * (2 active rules at the same time -
1140 * 1 allow rule from one of the first 3 groups.
1141 * 1 drop rule from the last group):
1142 * 1)Allow untagged traffic with smac=original mac.
1143 * 2)Allow untagged traffic.
1144 * 3)Allow traffic with smac=original mac.
1145 * 4)Drop all other traffic.
1146 */
1147 int table_size = 4;
1148 int err = 0;
1149
01f51f22
MHY		 1150 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support) ||
1151 !IS_ERR_OR_NULL(vport->ingress.acl))
5742df0f
MHY		 1152 return;
1153
1154 esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
1155 vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
1156
1157 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
1158 if (!root_ns) {
1159 esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
1160 return;
1161 }
1162
1163 flow_group_in = mlx5_vzalloc(inlen);
1164 if (!flow_group_in)
1165 return;
1166
1167 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1168 if (IS_ERR(acl)) {
5742df0f
MHY		 1169 err = PTR_ERR(acl);
1170 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
1171 vport->vport, err);
1172 goto out;
1173 }
1174 vport->ingress.acl = acl;
1175
1176 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1177
1178 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1179 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1180 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1181 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1182 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1183 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1184
1185 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1186 if (IS_ERR(g)) {
5742df0f
MHY		 1187 err = PTR_ERR(g);
1188 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
1189 vport->vport, err);
1190 goto out;
1191 }
1192 vport->ingress.allow_untagged_spoofchk_grp = g;
1193
1194 memset(flow_group_in, 0, inlen);
1195 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1196 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1197 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1198 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1199
1200 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1201 if (IS_ERR(g)) {
5742df0f
MHY		 1202 err = PTR_ERR(g);
1203 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
1204 vport->vport, err);
1205 goto out;
1206 }
1207 vport->ingress.allow_untagged_only_grp = g;
1208
1209 memset(flow_group_in, 0, inlen);
1210 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1211 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1212 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1213 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
1214 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
1215
1216 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1217 if (IS_ERR(g)) {
5742df0f
MHY		 1218 err = PTR_ERR(g);
1219 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
1220 vport->vport, err);
1221 goto out;
1222 }
1223 vport->ingress.allow_spoofchk_only_grp = g;
1224
1225 memset(flow_group_in, 0, inlen);
1226 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
1227 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
1228
1229 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1230 if (IS_ERR(g)) {
5742df0f
MHY		 1231 err = PTR_ERR(g);
1232 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
1233 vport->vport, err);
1234 goto out;
1235 }
1236 vport->ingress.drop_grp = g;
1237
1238out:
1239 if (err) {
1240 if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
1241 mlx5_destroy_flow_group(
1242 vport->ingress.allow_spoofchk_only_grp);
1243 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
1244 mlx5_destroy_flow_group(
1245 vport->ingress.allow_untagged_only_grp);
1246 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
1247 mlx5_destroy_flow_group(
1248 vport->ingress.allow_untagged_spoofchk_grp);
1249 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1250 mlx5_destroy_flow_table(vport->ingress.acl);
1251 }
1252
3fe3d819 1253 kvfree(flow_group_in);
5742df0f
MHY		 1254}
1255
dfcb1ed3
MHY		 1256static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
1257 struct mlx5_vport *vport)
1258{
1259 if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
1260 mlx5_del_flow_rule(vport->ingress.drop_rule);
f942380c
MHY		 1261
1262 if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
1263 mlx5_del_flow_rule(vport->ingress.allow_rule);
1264
dfcb1ed3 1265 vport->ingress.drop_rule = NULL;
f942380c 1266 vport->ingress.allow_rule = NULL;
dfcb1ed3
MHY		 1267}
1268
5742df0f
MHY		 1269static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
1270 struct mlx5_vport *vport)
1271{
1272 if (IS_ERR_OR_NULL(vport->ingress.acl))
1273 return;
1274
1275 esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
1276
dfcb1ed3 1277 esw_vport_cleanup_ingress_rules(esw, vport);
5742df0f
MHY		 1278 mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
1279 mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
1280 mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
1281 mlx5_destroy_flow_group(vport->ingress.drop_grp);
1282 mlx5_destroy_flow_table(vport->ingress.acl);
1283 vport->ingress.acl = NULL;
1284 vport->ingress.drop_grp = NULL;
1285 vport->ingress.allow_spoofchk_only_grp = NULL;
1286 vport->ingress.allow_untagged_only_grp = NULL;
1287 vport->ingress.allow_untagged_spoofchk_grp = NULL;
1288}
1289
dfcb1ed3
MHY		 1290static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1291 struct mlx5_vport *vport)
1292{
c5bb1730 1293 struct mlx5_flow_spec *spec;
f942380c 1294 u8 smac[ETH_ALEN];
dfcb1ed3 1295 int err = 0;
f942380c 1296 u8 *smac_v;
dfcb1ed3 1297
f942380c
MHY		 1298 if (vport->spoofchk) {
1299 err = mlx5_query_nic_vport_mac_address(esw->dev, vport->vport, smac);
1300 if (err) {
1301 esw_warn(esw->dev,
1302 "vport[%d] configure ingress rules failed, query smac failed, err(%d)\n",
1303 vport->vport, err);
1304 return err;
1305 }
1306
1307 if (!is_valid_ether_addr(smac)) {
1308 mlx5_core_warn(esw->dev,
1309 "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
1310 vport->vport);
1311 return -EPERM;
1312 }
1313 }
1314
dfcb1ed3
MHY		 1315 esw_vport_cleanup_ingress_rules(esw, vport);
1316
01f51f22
MHY		 1317 if (!vport->vlan && !vport->qos && !vport->spoofchk) {
1318 esw_vport_disable_ingress_acl(esw, vport);
dfcb1ed3 1319 return 0;
01f51f22
MHY		 1320 }
1321
1322 esw_vport_enable_ingress_acl(esw, vport);
dfcb1ed3
MHY		 1323
1324 esw_debug(esw->dev,
1325 "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
1326 vport->vport, vport->vlan, vport->qos);
1327
c5bb1730
MG		 1328 spec = mlx5_vzalloc(sizeof(*spec));
1329 if (!spec) {
dfcb1ed3
MHY		 1330 err = -ENOMEM;
1331 esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n",
1332 vport->vport, err);
1333 goto out;
1334 }
dfcb1ed3 1335
f942380c 1336 if (vport->vlan || vport->qos)
c5bb1730 1337 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
f942380c
MHY		 1338
1339 if (vport->spoofchk) {
c5bb1730
MG		 1340 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16);
1341 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_15_0);
f942380c 1342 smac_v = MLX5_ADDR_OF(fte_match_param,
c5bb1730 1343 spec->match_value,
f942380c
MHY		 1344 outer_headers.smac_47_16);
1345 ether_addr_copy(smac_v, smac);
1346 }
1347
c5bb1730 1348 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
f942380c 1349 vport->ingress.allow_rule =
c5bb1730 1350 mlx5_add_flow_rule(vport->ingress.acl, spec,
f942380c
MHY		 1351 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1352 0, NULL);
3f42ac66 1353 if (IS_ERR(vport->ingress.allow_rule)) {
f942380c
MHY		 1354 err = PTR_ERR(vport->ingress.allow_rule);
1355 pr_warn("vport[%d] configure ingress allow rule, err(%d)\n",
1356 vport->vport, err);
1357 vport->ingress.allow_rule = NULL;
1358 goto out;
1359 }
1360
c5bb1730 1361 memset(spec, 0, sizeof(*spec));
f942380c 1362 vport->ingress.drop_rule =
c5bb1730 1363 mlx5_add_flow_rule(vport->ingress.acl, spec,
dfcb1ed3
MHY		 1364 MLX5_FLOW_CONTEXT_ACTION_DROP,
1365 0, NULL);
3f42ac66 1366 if (IS_ERR(vport->ingress.drop_rule)) {
dfcb1ed3 1367 err = PTR_ERR(vport->ingress.drop_rule);
f942380c 1368 pr_warn("vport[%d] configure ingress drop rule, err(%d)\n",
dfcb1ed3
MHY		 1369 vport->vport, err);
1370 vport->ingress.drop_rule = NULL;
f942380c 1371 goto out;
dfcb1ed3 1372 }
f942380c 1373
dfcb1ed3 1374out:
f942380c
MHY		 1375 if (err)
1376 esw_vport_cleanup_ingress_rules(esw, vport);
c5bb1730 1377 kvfree(spec);
dfcb1ed3
MHY		 1378 return err;
1379}
1380
1381static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1382 struct mlx5_vport *vport)
1383{
c5bb1730 1384 struct mlx5_flow_spec *spec;
dfcb1ed3
MHY		 1385 int err = 0;
1386
dfcb1ed3
MHY		 1387 esw_vport_cleanup_egress_rules(esw, vport);
1388
01f51f22
MHY		 1389 if (!vport->vlan && !vport->qos) {
1390 esw_vport_disable_egress_acl(esw, vport);
dfcb1ed3 1391 return 0;
01f51f22
MHY		 1392 }
1393
1394 esw_vport_enable_egress_acl(esw, vport);
dfcb1ed3
MHY		 1395
1396 esw_debug(esw->dev,
1397 "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
1398 vport->vport, vport->vlan, vport->qos);
1399
c5bb1730
MG		 1400 spec = mlx5_vzalloc(sizeof(*spec));
1401 if (!spec) {
dfcb1ed3
MHY		 1402 err = -ENOMEM;
1403 esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n",
1404 vport->vport, err);
1405 goto out;
1406 }
1407
1408 /* Allowed vlan rule */
c5bb1730
MG		 1409 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
1410 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.vlan_tag);
1411 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1412 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->vlan);
dfcb1ed3 1413
c5bb1730 1414 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
dfcb1ed3 1415 vport->egress.allowed_vlan =
c5bb1730 1416 mlx5_add_flow_rule(vport->egress.acl, spec,
dfcb1ed3
MHY		 1417 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1418 0, NULL);
3f42ac66 1419 if (IS_ERR(vport->egress.allowed_vlan)) {
dfcb1ed3
MHY		 1420 err = PTR_ERR(vport->egress.allowed_vlan);
1421 pr_warn("vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
1422 vport->vport, err);
1423 vport->egress.allowed_vlan = NULL;
1424 goto out;
1425 }
1426
1427 /* Drop others rule (star rule) */
c5bb1730 1428 memset(spec, 0, sizeof(*spec));
dfcb1ed3 1429 vport->egress.drop_rule =
c5bb1730 1430 mlx5_add_flow_rule(vport->egress.acl, spec,
dfcb1ed3
MHY		 1431 MLX5_FLOW_CONTEXT_ACTION_DROP,
1432 0, NULL);
3f42ac66 1433 if (IS_ERR(vport->egress.drop_rule)) {
dfcb1ed3
MHY		 1434 err = PTR_ERR(vport->egress.drop_rule);
1435 pr_warn("vport[%d] configure egress drop rule failed, err(%d)\n",
1436 vport->vport, err);
1437 vport->egress.drop_rule = NULL;
1438 }
1439out:
c5bb1730 1440 kvfree(spec);
dfcb1ed3
MHY		 1441 return err;
1442}
1443
81848731
SM		 1444static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
1445 int enable_events)
073bb189
SM		 1446{
1447 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189 1448
dfcb1ed3 1449 mutex_lock(&esw->state_lock);
81848731
SM		 1450 WARN_ON(vport->enabled);
1451
1452 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
5742df0f 1453
f96750f8
OG		 1454 /* Only VFs need ACLs for VST and spoofchk filtering */
1455 if (vport_num && esw->mode == SRIOV_LEGACY) {
dfcb1ed3
MHY		 1456 esw_vport_ingress_config(esw, vport);
1457 esw_vport_egress_config(esw, vport);
5742df0f
MHY		 1458 }
1459
81848731
SM		 1460 mlx5_modify_vport_admin_state(esw->dev,
1461 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1462 vport_num,
1463 MLX5_ESW_VPORT_ADMIN_STATE_AUTO);
1464
1465 /* Sync with current vport context */
1466 vport->enabled_events = enable_events;
073bb189 1467 vport->enabled = true;
073bb189 1468
a35f71f2
MHY		 1469 /* only PF is trusted by default */
1470 vport->trusted = (vport_num) ? false : true;
25fff58c 1471 esw_vport_change_handle_locked(vport);
81848731
SM		 1472
1473 esw->enabled_vports++;
1474 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
dfcb1ed3 1475 mutex_unlock(&esw->state_lock);
81848731
SM		 1476}
1477
073bb189
SM		 1478static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
1479{
1480 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189
SM		 1481
1482 if (!vport->enabled)
1483 return;
1484
81848731 1485 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
073bb189 1486 /* Mark this vport as disabled to discard new events */
073bb189 1487 vport->enabled = false;
831cae1d
MHY		 1488
1489 synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
073bb189 1490
81848731
SM		 1491 mlx5_modify_vport_admin_state(esw->dev,
1492 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1493 vport_num,
1494 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
073bb189
SM		 1495 /* Wait for current already scheduled events to complete */
1496 flush_workqueue(esw->work_queue);
073bb189
SM		 1497 /* Disable events from this vport */
1498 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
dfcb1ed3 1499 mutex_lock(&esw->state_lock);
586cfa7f
MHY		 1500 /* We don't assume VFs will cleanup after themselves.
1501 * Calling vport change handler while vport is disabled will cleanup
1502 * the vport resources.
1503 */
1edc57e2 1504 esw_vport_change_handle_locked(vport);
586cfa7f 1505 vport->enabled_events = 0;
f96750f8 1506 if (vport_num && esw->mode == SRIOV_LEGACY) {
5742df0f
MHY		 1507 esw_vport_disable_egress_acl(esw, vport);
1508 esw_vport_disable_ingress_acl(esw, vport);
1509 }
81848731 1510 esw->enabled_vports--;
dfcb1ed3 1511 mutex_unlock(&esw->state_lock);
073bb189
SM		 1512}
1513
1514/* Public E-Switch API */
6ab36e35 1515int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode)
81848731
SM		 1516{
1517 int err;
69697b6e 1518 int i, enabled_events;
81848731
SM		 1519
1520 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1521 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1522 return 0;
1523
1524 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
1525 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
1526 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
1527 return -ENOTSUPP;
1528 }
1529
5742df0f
MHY		 1530 if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
1531 esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
1532
1533 if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
1534 esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
1535
6ab36e35 1536 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode);
6ab36e35 1537 esw->mode = mode;
81848731
SM		 1538 esw_disable_vport(esw, 0);
1539
69697b6e
OG		 1540 if (mode == SRIOV_LEGACY)
1541 err = esw_create_legacy_fdb_table(esw, nvfs + 1);
1542 else
c930a3ad 1543 err = esw_offloads_init(esw, nvfs + 1);
81848731
SM		 1544 if (err)
1545 goto abort;
1546
69697b6e 1547 enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE;
81848731 1548 for (i = 0; i <= nvfs; i++)
69697b6e 1549 esw_enable_vport(esw, i, enabled_events);
81848731
SM		 1550
1551 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
1552 esw->enabled_vports);
1553 return 0;
1554
1555abort:
1556 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
4eea37d7 1557 esw->mode = SRIOV_NONE;
81848731
SM		 1558 return err;
1559}
1560
1561void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
1562{
a35f71f2 1563 struct esw_mc_addr *mc_promisc;
c930a3ad 1564 int nvports;
81848731
SM		 1565 int i;
1566
1567 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1568 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1569 return;
1570
6ab36e35
OG		 1571 esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
1572 esw->enabled_vports, esw->mode);
81848731 1573
a35f71f2 1574 mc_promisc = esw->mc_promisc;
c930a3ad 1575 nvports = esw->enabled_vports;
a35f71f2 1576
81848731
SM		 1577 for (i = 0; i < esw->total_vports; i++)
1578 esw_disable_vport(esw, i);
1579
a35f71f2
MHY		 1580 if (mc_promisc && mc_promisc->uplink_rule)
1581 mlx5_del_flow_rule(mc_promisc->uplink_rule);
1582
69697b6e
OG		 1583 if (esw->mode == SRIOV_LEGACY)
1584 esw_destroy_legacy_fdb_table(esw);
c930a3ad
OG		 1585 else if (esw->mode == SRIOV_OFFLOADS)
1586 esw_offloads_cleanup(esw, nvports);
81848731 1587
6ab36e35 1588 esw->mode = SRIOV_NONE;
81848731
SM		 1589 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
1590 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1591}
1592
073bb189
SM		 1593int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1594{
1595 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
efdc810b 1596 int total_vports = MLX5_TOTAL_VPORTS(dev);
a35f71f2 1597 struct esw_mc_addr *mc_promisc;
073bb189
SM		 1598 struct mlx5_eswitch *esw;
1599 int vport_num;
1600 int err;
1601
1602 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
1603 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1604 return 0;
1605
1606 esw_info(dev,
1607 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
1608 total_vports, l2_table_size,
1609 MLX5_MAX_UC_PER_VPORT(dev),
1610 MLX5_MAX_MC_PER_VPORT(dev));
1611
1612 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
1613 if (!esw)
1614 return -ENOMEM;
1615
1616 esw->dev = dev;
1617
1618 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
1619 sizeof(uintptr_t), GFP_KERNEL);
1620 if (!esw->l2_table.bitmap) {
1621 err = -ENOMEM;
1622 goto abort;
1623 }
1624 esw->l2_table.size = l2_table_size;
1625
a35f71f2
MHY		 1626 mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL);
1627 if (!mc_promisc) {
1628 err = -ENOMEM;
1629 goto abort;
1630 }
1631 esw->mc_promisc = mc_promisc;
1632
073bb189
SM		 1633 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
1634 if (!esw->work_queue) {
1635 err = -ENOMEM;
1636 goto abort;
1637 }
1638
1639 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
1640 GFP_KERNEL);
1641 if (!esw->vports) {
1642 err = -ENOMEM;
1643 goto abort;
1644 }
1645
127ea380
HHZ		 1646 esw->offloads.vport_reps =
1647 kzalloc(total_vports * sizeof(struct mlx5_eswitch_rep),
1648 GFP_KERNEL);
1649 if (!esw->offloads.vport_reps) {
1650 err = -ENOMEM;
1651 goto abort;
1652 }
1653
dfcb1ed3
MHY		 1654 mutex_init(&esw->state_lock);
1655
073bb189
SM		 1656 for (vport_num = 0; vport_num < total_vports; vport_num++) {
1657 struct mlx5_vport *vport = &esw->vports[vport_num];
1658
1659 vport->vport = vport_num;
1660 vport->dev = dev;
1661 INIT_WORK(&vport->vport_change_handler,
1662 esw_vport_change_handler);
073bb189
SM		 1663 }
1664
81848731
SM		 1665 esw->total_vports = total_vports;
1666 esw->enabled_vports = 0;
6ab36e35 1667 esw->mode = SRIOV_NONE;
073bb189 1668
81848731
SM		 1669 dev->priv.eswitch = esw;
1670 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
073bb189
SM		 1671 /* VF Vports will be enabled when SRIOV is enabled */
1672 return 0;
1673abort:
1674 if (esw->work_queue)
1675 destroy_workqueue(esw->work_queue);
1676 kfree(esw->l2_table.bitmap);
1677 kfree(esw->vports);
127ea380 1678 kfree(esw->offloads.vport_reps);
073bb189
SM		 1679 kfree(esw);
1680 return err;
1681}
1682
1683void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
1684{
1685 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1686 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1687 return;
1688
1689 esw_info(esw->dev, "cleanup\n");
1690 esw_disable_vport(esw, 0);
1691
1692 esw->dev->priv.eswitch = NULL;
1693 destroy_workqueue(esw->work_queue);
1694 kfree(esw->l2_table.bitmap);
a35f71f2 1695 kfree(esw->mc_promisc);
127ea380 1696 kfree(esw->offloads.vport_reps);
073bb189
SM		 1697 kfree(esw->vports);
1698 kfree(esw);
1699}
1700
1701void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1702{
1703 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1704 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1705 struct mlx5_vport *vport;
1706
1707 if (!esw) {
1708 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1709 vport_num);
1710 return;
1711 }
1712
1713 vport = &esw->vports[vport_num];
073bb189
SM		 1714 if (vport->enabled)
1715 queue_work(esw->work_queue, &vport->vport_change_handler);
073bb189 1716}
77256579
SM		 1717
1718/* Vport Administration */
1719#define ESW_ALLOWED(esw) \
1720 (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
1721#define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
1722
23898c76
NO		 1723static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
1724{
1725 ((u8 *)node_guid)[7] = mac[0];
1726 ((u8 *)node_guid)[6] = mac[1];
1727 ((u8 *)node_guid)[5] = mac[2];
1728 ((u8 *)node_guid)[4] = 0xff;
1729 ((u8 *)node_guid)[3] = 0xfe;
1730 ((u8 *)node_guid)[2] = mac[3];
1731 ((u8 *)node_guid)[1] = mac[4];
1732 ((u8 *)node_guid)[0] = mac[5];
1733}
1734
77256579
SM		 1735int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
1736 int vport, u8 mac[ETH_ALEN])
1737{
f942380c 1738 struct mlx5_vport *evport;
23898c76
NO		 1739 u64 node_guid;
1740 int err = 0;
77256579
SM		 1741
1742 if (!ESW_ALLOWED(esw))
1743 return -EPERM;
1744 if (!LEGAL_VPORT(esw, vport))
1745 return -EINVAL;
1746
f942380c
MHY		 1747 evport = &esw->vports[vport];
1748
1749 if (evport->spoofchk && !is_valid_ether_addr(mac)) {
1750 mlx5_core_warn(esw->dev,
1751 "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
1752 vport);
1753 return -EPERM;
1754 }
1755
77256579
SM		 1756 err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
1757 if (err) {
1758 mlx5_core_warn(esw->dev,
1759 "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
1760 vport, err);
1761 return err;
1762 }
1763
23898c76
NO		 1764 node_guid_gen_from_mac(&node_guid, mac);
1765 err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
1766 if (err)
1767 mlx5_core_warn(esw->dev,
1768 "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
1769 vport, err);
1770
f942380c 1771 mutex_lock(&esw->state_lock);
f96750f8 1772 if (evport->enabled && esw->mode == SRIOV_LEGACY)
f942380c
MHY		 1773 err = esw_vport_ingress_config(esw, evport);
1774 mutex_unlock(&esw->state_lock);
77256579
SM		 1775 return err;
1776}
1777
1778int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
1779 int vport, int link_state)
1780{
1781 if (!ESW_ALLOWED(esw))
1782 return -EPERM;
1783 if (!LEGAL_VPORT(esw, vport))
1784 return -EINVAL;
1785
1786 return mlx5_modify_vport_admin_state(esw->dev,
1787 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1788 vport, link_state);
1789}
1790
1791int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
1792 int vport, struct ifla_vf_info *ivi)
1793{
f942380c 1794 struct mlx5_vport *evport;
9e7ea352
SM		 1795 u16 vlan;
1796 u8 qos;
1797
77256579
SM		 1798 if (!ESW_ALLOWED(esw))
1799 return -EPERM;
1800 if (!LEGAL_VPORT(esw, vport))
1801 return -EINVAL;
1802
f942380c
MHY		 1803 evport = &esw->vports[vport];
1804
77256579
SM		 1805 memset(ivi, 0, sizeof(*ivi));
1806 ivi->vf = vport - 1;
1807
1808 mlx5_query_nic_vport_mac_address(esw->dev, vport, ivi->mac);
1809 ivi->linkstate = mlx5_query_vport_admin_state(esw->dev,
1810 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1811 vport);
9e7ea352
SM		 1812 query_esw_vport_cvlan(esw->dev, vport, &vlan, &qos);
1813 ivi->vlan = vlan;
1814 ivi->qos = qos;
f942380c 1815 ivi->spoofchk = evport->spoofchk;
77256579
SM		 1816
1817 return 0;
1818}
9e7ea352
SM		 1819
1820int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1821 int vport, u16 vlan, u8 qos)
1822{
dfcb1ed3
MHY		 1823 struct mlx5_vport *evport;
1824 int err = 0;
9e7ea352
SM		 1825 int set = 0;
1826
1827 if (!ESW_ALLOWED(esw))
1828 return -EPERM;
1829 if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
1830 return -EINVAL;
1831
1832 if (vlan || qos)
1833 set = 1;
1834
dfcb1ed3
MHY		 1835 evport = &esw->vports[vport];
1836
1837 err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set);
1838 if (err)
1839 return err;
1840
1841 mutex_lock(&esw->state_lock);
1842 evport->vlan = vlan;
1843 evport->qos = qos;
f96750f8 1844 if (evport->enabled && esw->mode == SRIOV_LEGACY) {
dfcb1ed3
MHY		 1845 err = esw_vport_ingress_config(esw, evport);
1846 if (err)
1847 goto out;
1848 err = esw_vport_egress_config(esw, evport);
1849 }
1850
1851out:
1852 mutex_unlock(&esw->state_lock);
1853 return err;
9e7ea352 1854}
3b751a2a 1855
f942380c
MHY		 1856int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
1857 int vport, bool spoofchk)
1858{
1859 struct mlx5_vport *evport;
1860 bool pschk;
1861 int err = 0;
1862
1863 if (!ESW_ALLOWED(esw))
1864 return -EPERM;
1865 if (!LEGAL_VPORT(esw, vport))
1866 return -EINVAL;
1867
1868 evport = &esw->vports[vport];
1869
1870 mutex_lock(&esw->state_lock);
1871 pschk = evport->spoofchk;
1872 evport->spoofchk = spoofchk;
f96750f8 1873 if (evport->enabled && esw->mode == SRIOV_LEGACY) {
f942380c 1874 err = esw_vport_ingress_config(esw, evport);
f96750f8
OG		 1875 if (err)
1876 evport->spoofchk = pschk;
1877 }
f942380c
MHY		 1878 mutex_unlock(&esw->state_lock);
1879
1880 return err;
1881}
1882
1edc57e2
MHY		 1883int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1884 int vport, bool setting)
1885{
1886 struct mlx5_vport *evport;
1887
1888 if (!ESW_ALLOWED(esw))
1889 return -EPERM;
1890 if (!LEGAL_VPORT(esw, vport))
1891 return -EINVAL;
1892
1893 evport = &esw->vports[vport];
1894
1895 mutex_lock(&esw->state_lock);
1896 evport->trusted = setting;
1897 if (evport->enabled)
1898 esw_vport_change_handle_locked(evport);
1899 mutex_unlock(&esw->state_lock);
1900
1901 return 0;
1902}
1903
3b751a2a
SM		 1904int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
1905 int vport,
1906 struct ifla_vf_stats *vf_stats)
1907{
1908 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
1909 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
1910 int err = 0;
1911 u32 *out;
1912
1913 if (!ESW_ALLOWED(esw))
1914 return -EPERM;
1915 if (!LEGAL_VPORT(esw, vport))
1916 return -EINVAL;
1917
1918 out = mlx5_vzalloc(outlen);
1919 if (!out)
1920 return -ENOMEM;
1921
1922 memset(in, 0, sizeof(in));
1923
1924 MLX5_SET(query_vport_counter_in, in, opcode,
1925 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
1926 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
1927 MLX5_SET(query_vport_counter_in, in, vport_number, vport);
1928 if (vport)
1929 MLX5_SET(query_vport_counter_in, in, other_vport, 1);
1930
1931 memset(out, 0, outlen);
1932 err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
1933 if (err)
1934 goto free_out;
1935
1936 #define MLX5_GET_CTR(p, x) \
1937 MLX5_GET64(query_vport_counter_out, p, x)
1938
1939 memset(vf_stats, 0, sizeof(*vf_stats));
1940 vf_stats->rx_packets =
1941 MLX5_GET_CTR(out, received_eth_unicast.packets) +
1942 MLX5_GET_CTR(out, received_eth_multicast.packets) +
1943 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1944
1945 vf_stats->rx_bytes =
1946 MLX5_GET_CTR(out, received_eth_unicast.octets) +
1947 MLX5_GET_CTR(out, received_eth_multicast.octets) +
1948 MLX5_GET_CTR(out, received_eth_broadcast.octets);
1949
1950 vf_stats->tx_packets =
1951 MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
1952 MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
1953 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
1954
1955 vf_stats->tx_bytes =
1956 MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
1957 MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
1958 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
1959
1960 vf_stats->multicast =
1961 MLX5_GET_CTR(out, received_eth_multicast.packets);
1962
1963 vf_stats->broadcast =
1964 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1965
1966free_out:
1967 kvfree(out);
1968 return err;
1969}
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