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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/mlx5/driver.h> | |
35 | #include <linux/mlx5/mlx5_ifc.h> | |
36 | #include <linux/mlx5/vport.h> | |
86d722ad | 37 | #include <linux/mlx5/fs.h> |
073bb189 SM |
38 | #include "mlx5_core.h" |
39 | #include "eswitch.h" | |
40 | ||
81848731 SM |
41 | #define UPLINK_VPORT 0xFFFF |
42 | ||
073bb189 SM |
43 | enum { |
44 | MLX5_ACTION_NONE = 0, | |
45 | MLX5_ACTION_ADD = 1, | |
46 | MLX5_ACTION_DEL = 2, | |
47 | }; | |
48 | ||
81848731 SM |
49 | /* E-Switch UC L2 table hash node */ |
50 | struct esw_uc_addr { | |
073bb189 | 51 | struct l2addr_node node; |
073bb189 SM |
52 | u32 table_index; |
53 | u32 vport; | |
54 | }; | |
55 | ||
81848731 SM |
56 | /* E-Switch MC FDB table hash node */ |
57 | struct esw_mc_addr { /* SRIOV only */ | |
58 | struct l2addr_node node; | |
74491de9 | 59 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ |
81848731 SM |
60 | u32 refcnt; |
61 | }; | |
62 | ||
63 | /* Vport UC/MC hash node */ | |
64 | struct vport_addr { | |
65 | struct l2addr_node node; | |
66 | u8 action; | |
67 | u32 vport; | |
74491de9 | 68 | struct mlx5_flow_handle *flow_rule; /* SRIOV only */ |
a35f71f2 MHY |
69 | /* A flag indicating that mac was added due to mc promiscuous vport */ |
70 | bool mc_promisc; | |
073bb189 SM |
71 | }; |
72 | ||
73 | enum { | |
74 | UC_ADDR_CHANGE = BIT(0), | |
75 | MC_ADDR_CHANGE = BIT(1), | |
a35f71f2 | 76 | PROMISC_CHANGE = BIT(3), |
073bb189 SM |
77 | }; |
78 | ||
81848731 SM |
79 | /* Vport context events */ |
80 | #define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \ | |
a35f71f2 MHY |
81 | MC_ADDR_CHANGE | \ |
82 | PROMISC_CHANGE) | |
81848731 SM |
83 | |
84 | static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport, | |
073bb189 SM |
85 | u32 events_mask) |
86 | { | |
c4f287c4 SM |
87 | int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0}; |
88 | int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0}; | |
073bb189 | 89 | void *nic_vport_ctx; |
073bb189 SM |
90 | |
91 | MLX5_SET(modify_nic_vport_context_in, in, | |
92 | opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT); | |
93 | MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1); | |
94 | MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport); | |
95 | if (vport) | |
96 | MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1); | |
97 | nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in, | |
98 | in, nic_vport_context); | |
99 | ||
100 | MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1); | |
101 | ||
102 | if (events_mask & UC_ADDR_CHANGE) | |
103 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
104 | event_on_uc_address_change, 1); | |
105 | if (events_mask & MC_ADDR_CHANGE) | |
106 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
107 | event_on_mc_address_change, 1); | |
a35f71f2 MHY |
108 | if (events_mask & PROMISC_CHANGE) |
109 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
110 | event_on_promisc_change, 1); | |
073bb189 | 111 | |
c4f287c4 | 112 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
073bb189 SM |
113 | } |
114 | ||
9e7ea352 | 115 | /* E-Switch vport context HW commands */ |
9e7ea352 SM |
116 | static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport, |
117 | void *in, int inlen) | |
118 | { | |
c4f287c4 | 119 | u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0}; |
9e7ea352 | 120 | |
c4f287c4 SM |
121 | MLX5_SET(modify_esw_vport_context_in, in, opcode, |
122 | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT); | |
9e7ea352 SM |
123 | MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport); |
124 | if (vport) | |
125 | MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1); | |
c4f287c4 | 126 | return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); |
9e7ea352 SM |
127 | } |
128 | ||
129 | static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport, | |
e33dfe31 | 130 | u16 vlan, u8 qos, u8 set_flags) |
9e7ea352 | 131 | { |
c4f287c4 | 132 | u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0}; |
9e7ea352 SM |
133 | |
134 | if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) || | |
135 | !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist)) | |
9eb78923 | 136 | return -EOPNOTSUPP; |
9e7ea352 | 137 | |
e33dfe31 OG |
138 | esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%x\n", |
139 | vport, vlan, qos, set_flags); | |
140 | ||
141 | if (set_flags & SET_VLAN_STRIP) | |
9e7ea352 SM |
142 | MLX5_SET(modify_esw_vport_context_in, in, |
143 | esw_vport_context.vport_cvlan_strip, 1); | |
e33dfe31 OG |
144 | |
145 | if (set_flags & SET_VLAN_INSERT) { | |
9e7ea352 SM |
146 | /* insert only if no vlan in packet */ |
147 | MLX5_SET(modify_esw_vport_context_in, in, | |
148 | esw_vport_context.vport_cvlan_insert, 1); | |
e33dfe31 | 149 | |
9e7ea352 SM |
150 | MLX5_SET(modify_esw_vport_context_in, in, |
151 | esw_vport_context.cvlan_pcp, qos); | |
152 | MLX5_SET(modify_esw_vport_context_in, in, | |
153 | esw_vport_context.cvlan_id, vlan); | |
154 | } | |
155 | ||
156 | MLX5_SET(modify_esw_vport_context_in, in, | |
157 | field_select.vport_cvlan_strip, 1); | |
158 | MLX5_SET(modify_esw_vport_context_in, in, | |
159 | field_select.vport_cvlan_insert, 1); | |
160 | ||
161 | return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in)); | |
162 | } | |
163 | ||
073bb189 SM |
164 | /* HW L2 Table (MPFS) management */ |
165 | static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index, | |
166 | u8 *mac, u8 vlan_valid, u16 vlan) | |
167 | { | |
c4f287c4 SM |
168 | u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0}; |
169 | u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0}; | |
073bb189 SM |
170 | u8 *in_mac_addr; |
171 | ||
073bb189 SM |
172 | MLX5_SET(set_l2_table_entry_in, in, opcode, |
173 | MLX5_CMD_OP_SET_L2_TABLE_ENTRY); | |
174 | MLX5_SET(set_l2_table_entry_in, in, table_index, index); | |
175 | MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid); | |
176 | MLX5_SET(set_l2_table_entry_in, in, vlan, vlan); | |
177 | ||
178 | in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address); | |
179 | ether_addr_copy(&in_mac_addr[2], mac); | |
180 | ||
c4f287c4 | 181 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
073bb189 SM |
182 | } |
183 | ||
184 | static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index) | |
185 | { | |
c4f287c4 SM |
186 | u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0}; |
187 | u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0}; | |
073bb189 SM |
188 | |
189 | MLX5_SET(delete_l2_table_entry_in, in, opcode, | |
190 | MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY); | |
191 | MLX5_SET(delete_l2_table_entry_in, in, table_index, index); | |
c4f287c4 | 192 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
073bb189 SM |
193 | } |
194 | ||
195 | static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix) | |
196 | { | |
197 | int err = 0; | |
198 | ||
199 | *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size); | |
200 | if (*ix >= l2_table->size) | |
201 | err = -ENOSPC; | |
202 | else | |
203 | __set_bit(*ix, l2_table->bitmap); | |
204 | ||
205 | return err; | |
206 | } | |
207 | ||
208 | static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix) | |
209 | { | |
210 | __clear_bit(ix, l2_table->bitmap); | |
211 | } | |
212 | ||
213 | static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac, | |
214 | u8 vlan_valid, u16 vlan, | |
215 | u32 *index) | |
216 | { | |
217 | struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table; | |
218 | int err; | |
219 | ||
220 | err = alloc_l2_table_index(l2_table, index); | |
221 | if (err) | |
222 | return err; | |
223 | ||
224 | err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan); | |
225 | if (err) | |
226 | free_l2_table_index(l2_table, *index); | |
227 | ||
228 | return err; | |
229 | } | |
230 | ||
231 | static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index) | |
232 | { | |
233 | struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table; | |
234 | ||
235 | del_l2_table_entry_cmd(dev, index); | |
236 | free_l2_table_index(l2_table, index); | |
237 | } | |
238 | ||
81848731 | 239 | /* E-Switch FDB */ |
74491de9 | 240 | static struct mlx5_flow_handle * |
a35f71f2 | 241 | __esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule, |
78a9199b | 242 | u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN]) |
81848731 | 243 | { |
78a9199b MHY |
244 | int match_header = (is_zero_ether_addr(mac_c) ? 0 : |
245 | MLX5_MATCH_OUTER_HEADERS); | |
74491de9 | 246 | struct mlx5_flow_handle *flow_rule = NULL; |
66958ed9 | 247 | struct mlx5_flow_act flow_act = {0}; |
78a9199b | 248 | struct mlx5_flow_destination dest; |
c5bb1730 | 249 | struct mlx5_flow_spec *spec; |
a35f71f2 MHY |
250 | void *mv_misc = NULL; |
251 | void *mc_misc = NULL; | |
78a9199b MHY |
252 | u8 *dmac_v = NULL; |
253 | u8 *dmac_c = NULL; | |
81848731 | 254 | |
a35f71f2 MHY |
255 | if (rx_rule) |
256 | match_header |= MLX5_MATCH_MISC_PARAMETERS; | |
c5bb1730 MG |
257 | |
258 | spec = mlx5_vzalloc(sizeof(*spec)); | |
259 | if (!spec) { | |
2974ab6e | 260 | esw_warn(esw->dev, "FDB: Failed to alloc match parameters\n"); |
c5bb1730 | 261 | return NULL; |
81848731 | 262 | } |
c5bb1730 | 263 | dmac_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, |
81848731 | 264 | outer_headers.dmac_47_16); |
c5bb1730 | 265 | dmac_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
81848731 SM |
266 | outer_headers.dmac_47_16); |
267 | ||
a35f71f2 | 268 | if (match_header & MLX5_MATCH_OUTER_HEADERS) { |
78a9199b MHY |
269 | ether_addr_copy(dmac_v, mac_v); |
270 | ether_addr_copy(dmac_c, mac_c); | |
271 | } | |
81848731 | 272 | |
a35f71f2 | 273 | if (match_header & MLX5_MATCH_MISC_PARAMETERS) { |
c5bb1730 MG |
274 | mv_misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, |
275 | misc_parameters); | |
276 | mc_misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
277 | misc_parameters); | |
a35f71f2 MHY |
278 | MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT); |
279 | MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port); | |
280 | } | |
281 | ||
81848731 SM |
282 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; |
283 | dest.vport_num = vport; | |
284 | ||
285 | esw_debug(esw->dev, | |
286 | "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n", | |
287 | dmac_v, dmac_c, vport); | |
c5bb1730 | 288 | spec->match_criteria_enable = match_header; |
66958ed9 | 289 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
81848731 | 290 | flow_rule = |
74491de9 | 291 | mlx5_add_flow_rules(esw->fdb_table.fdb, spec, |
66958ed9 | 292 | &flow_act, &dest, 1); |
3f42ac66 | 293 | if (IS_ERR(flow_rule)) { |
2974ab6e SM |
294 | esw_warn(esw->dev, |
295 | "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n", | |
81848731 SM |
296 | dmac_v, dmac_c, vport, PTR_ERR(flow_rule)); |
297 | flow_rule = NULL; | |
298 | } | |
c5bb1730 MG |
299 | |
300 | kvfree(spec); | |
81848731 SM |
301 | return flow_rule; |
302 | } | |
303 | ||
74491de9 | 304 | static struct mlx5_flow_handle * |
78a9199b MHY |
305 | esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport) |
306 | { | |
307 | u8 mac_c[ETH_ALEN]; | |
308 | ||
309 | eth_broadcast_addr(mac_c); | |
a35f71f2 MHY |
310 | return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac); |
311 | } | |
312 | ||
74491de9 | 313 | static struct mlx5_flow_handle * |
a35f71f2 MHY |
314 | esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport) |
315 | { | |
316 | u8 mac_c[ETH_ALEN]; | |
317 | u8 mac_v[ETH_ALEN]; | |
318 | ||
319 | eth_zero_addr(mac_c); | |
320 | eth_zero_addr(mac_v); | |
321 | mac_c[0] = 0x01; | |
322 | mac_v[0] = 0x01; | |
323 | return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v); | |
324 | } | |
325 | ||
74491de9 | 326 | static struct mlx5_flow_handle * |
a35f71f2 MHY |
327 | esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport) |
328 | { | |
329 | u8 mac_c[ETH_ALEN]; | |
330 | u8 mac_v[ETH_ALEN]; | |
331 | ||
332 | eth_zero_addr(mac_c); | |
333 | eth_zero_addr(mac_v); | |
334 | return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v); | |
78a9199b MHY |
335 | } |
336 | ||
6ab36e35 | 337 | static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports) |
81848731 | 338 | { |
86d722ad | 339 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); |
81848731 | 340 | struct mlx5_core_dev *dev = esw->dev; |
86d722ad | 341 | struct mlx5_flow_namespace *root_ns; |
81848731 | 342 | struct mlx5_flow_table *fdb; |
86d722ad MG |
343 | struct mlx5_flow_group *g; |
344 | void *match_criteria; | |
345 | int table_size; | |
346 | u32 *flow_group_in; | |
81848731 | 347 | u8 *dmac; |
86d722ad | 348 | int err = 0; |
81848731 SM |
349 | |
350 | esw_debug(dev, "Create FDB log_max_size(%d)\n", | |
351 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); | |
352 | ||
86d722ad MG |
353 | root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB); |
354 | if (!root_ns) { | |
355 | esw_warn(dev, "Failed to get FDB flow namespace\n"); | |
eff596da | 356 | return -EOPNOTSUPP; |
86d722ad | 357 | } |
81848731 | 358 | |
86d722ad MG |
359 | flow_group_in = mlx5_vzalloc(inlen); |
360 | if (!flow_group_in) | |
361 | return -ENOMEM; | |
362 | memset(flow_group_in, 0, inlen); | |
363 | ||
364 | table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); | |
c9f1b073 | 365 | fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0, 0); |
3f42ac66 | 366 | if (IS_ERR(fdb)) { |
86d722ad MG |
367 | err = PTR_ERR(fdb); |
368 | esw_warn(dev, "Failed to create FDB Table err %d\n", err); | |
369 | goto out; | |
370 | } | |
78a9199b | 371 | esw->fdb_table.fdb = fdb; |
81848731 | 372 | |
78a9199b | 373 | /* Addresses group : Full match unicast/multicast addresses */ |
86d722ad MG |
374 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
375 | MLX5_MATCH_OUTER_HEADERS); | |
376 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); | |
377 | dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16); | |
378 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
78a9199b MHY |
379 | /* Preserve 2 entries for allmulti and promisc rules*/ |
380 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3); | |
86d722ad | 381 | eth_broadcast_addr(dmac); |
86d722ad | 382 | g = mlx5_create_flow_group(fdb, flow_group_in); |
3f42ac66 | 383 | if (IS_ERR(g)) { |
86d722ad MG |
384 | err = PTR_ERR(g); |
385 | esw_warn(dev, "Failed to create flow group err(%d)\n", err); | |
386 | goto out; | |
387 | } | |
6ab36e35 | 388 | esw->fdb_table.legacy.addr_grp = g; |
78a9199b MHY |
389 | |
390 | /* Allmulti group : One rule that forwards any mcast traffic */ | |
391 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
392 | MLX5_MATCH_OUTER_HEADERS); | |
393 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2); | |
394 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2); | |
395 | eth_zero_addr(dmac); | |
396 | dmac[0] = 0x01; | |
397 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
3f42ac66 | 398 | if (IS_ERR(g)) { |
78a9199b MHY |
399 | err = PTR_ERR(g); |
400 | esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err); | |
401 | goto out; | |
402 | } | |
6ab36e35 | 403 | esw->fdb_table.legacy.allmulti_grp = g; |
78a9199b MHY |
404 | |
405 | /* Promiscuous group : | |
406 | * One rule that forward all unmatched traffic from previous groups | |
407 | */ | |
408 | eth_zero_addr(dmac); | |
409 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
410 | MLX5_MATCH_MISC_PARAMETERS); | |
411 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port); | |
412 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1); | |
413 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1); | |
414 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
3f42ac66 | 415 | if (IS_ERR(g)) { |
78a9199b MHY |
416 | err = PTR_ERR(g); |
417 | esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err); | |
418 | goto out; | |
419 | } | |
6ab36e35 | 420 | esw->fdb_table.legacy.promisc_grp = g; |
78a9199b | 421 | |
86d722ad | 422 | out: |
78a9199b | 423 | if (err) { |
6ab36e35 OG |
424 | if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) { |
425 | mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp); | |
426 | esw->fdb_table.legacy.allmulti_grp = NULL; | |
78a9199b | 427 | } |
6ab36e35 OG |
428 | if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) { |
429 | mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp); | |
430 | esw->fdb_table.legacy.addr_grp = NULL; | |
78a9199b MHY |
431 | } |
432 | if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) { | |
433 | mlx5_destroy_flow_table(esw->fdb_table.fdb); | |
434 | esw->fdb_table.fdb = NULL; | |
435 | } | |
436 | } | |
437 | ||
3fe3d819 | 438 | kvfree(flow_group_in); |
86d722ad | 439 | return err; |
81848731 SM |
440 | } |
441 | ||
6ab36e35 | 442 | static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw) |
81848731 SM |
443 | { |
444 | if (!esw->fdb_table.fdb) | |
445 | return; | |
446 | ||
86d722ad | 447 | esw_debug(esw->dev, "Destroy FDB Table\n"); |
6ab36e35 OG |
448 | mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp); |
449 | mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp); | |
450 | mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp); | |
81848731 SM |
451 | mlx5_destroy_flow_table(esw->fdb_table.fdb); |
452 | esw->fdb_table.fdb = NULL; | |
6ab36e35 OG |
453 | esw->fdb_table.legacy.addr_grp = NULL; |
454 | esw->fdb_table.legacy.allmulti_grp = NULL; | |
455 | esw->fdb_table.legacy.promisc_grp = NULL; | |
81848731 SM |
456 | } |
457 | ||
458 | /* E-Switch vport UC/MC lists management */ | |
459 | typedef int (*vport_addr_action)(struct mlx5_eswitch *esw, | |
460 | struct vport_addr *vaddr); | |
461 | ||
462 | static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
463 | { | |
464 | struct hlist_head *hash = esw->l2_table.l2_hash; | |
465 | struct esw_uc_addr *esw_uc; | |
466 | u8 *mac = vaddr->node.addr; | |
467 | u32 vport = vaddr->vport; | |
468 | int err; | |
469 | ||
470 | esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr); | |
471 | if (esw_uc) { | |
073bb189 SM |
472 | esw_warn(esw->dev, |
473 | "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n", | |
81848731 | 474 | mac, vport, esw_uc->vport); |
073bb189 SM |
475 | return -EEXIST; |
476 | } | |
477 | ||
81848731 SM |
478 | esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL); |
479 | if (!esw_uc) | |
073bb189 | 480 | return -ENOMEM; |
81848731 | 481 | esw_uc->vport = vport; |
073bb189 | 482 | |
81848731 | 483 | err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index); |
073bb189 | 484 | if (err) |
81848731 SM |
485 | goto abort; |
486 | ||
69697b6e OG |
487 | /* SRIOV is enabled: Forward UC MAC to vport */ |
488 | if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY) | |
81848731 SM |
489 | vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport); |
490 | ||
491 | esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n", | |
492 | vport, mac, esw_uc->table_index, vaddr->flow_rule); | |
493 | return err; | |
494 | abort: | |
495 | l2addr_hash_del(esw_uc); | |
073bb189 SM |
496 | return err; |
497 | } | |
498 | ||
81848731 | 499 | static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) |
073bb189 | 500 | { |
81848731 SM |
501 | struct hlist_head *hash = esw->l2_table.l2_hash; |
502 | struct esw_uc_addr *esw_uc; | |
503 | u8 *mac = vaddr->node.addr; | |
504 | u32 vport = vaddr->vport; | |
505 | ||
506 | esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr); | |
507 | if (!esw_uc || esw_uc->vport != vport) { | |
508 | esw_debug(esw->dev, | |
509 | "MAC(%pM) doesn't belong to vport (%d)\n", | |
510 | mac, vport); | |
511 | return -EINVAL; | |
512 | } | |
513 | esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n", | |
514 | vport, mac, esw_uc->table_index, vaddr->flow_rule); | |
515 | ||
516 | del_l2_table_entry(esw->dev, esw_uc->table_index); | |
517 | ||
518 | if (vaddr->flow_rule) | |
74491de9 | 519 | mlx5_del_flow_rules(vaddr->flow_rule); |
81848731 SM |
520 | vaddr->flow_rule = NULL; |
521 | ||
522 | l2addr_hash_del(esw_uc); | |
523 | return 0; | |
524 | } | |
525 | ||
a35f71f2 MHY |
526 | static void update_allmulti_vports(struct mlx5_eswitch *esw, |
527 | struct vport_addr *vaddr, | |
528 | struct esw_mc_addr *esw_mc) | |
529 | { | |
530 | u8 *mac = vaddr->node.addr; | |
531 | u32 vport_idx = 0; | |
532 | ||
533 | for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) { | |
534 | struct mlx5_vport *vport = &esw->vports[vport_idx]; | |
535 | struct hlist_head *vport_hash = vport->mc_list; | |
536 | struct vport_addr *iter_vaddr = | |
537 | l2addr_hash_find(vport_hash, | |
538 | mac, | |
539 | struct vport_addr); | |
540 | if (IS_ERR_OR_NULL(vport->allmulti_rule) || | |
541 | vaddr->vport == vport_idx) | |
542 | continue; | |
543 | switch (vaddr->action) { | |
544 | case MLX5_ACTION_ADD: | |
545 | if (iter_vaddr) | |
546 | continue; | |
547 | iter_vaddr = l2addr_hash_add(vport_hash, mac, | |
548 | struct vport_addr, | |
549 | GFP_KERNEL); | |
550 | if (!iter_vaddr) { | |
551 | esw_warn(esw->dev, | |
552 | "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n", | |
553 | mac, vport_idx); | |
554 | continue; | |
555 | } | |
556 | iter_vaddr->vport = vport_idx; | |
557 | iter_vaddr->flow_rule = | |
558 | esw_fdb_set_vport_rule(esw, | |
559 | mac, | |
560 | vport_idx); | |
62e3c24a | 561 | iter_vaddr->mc_promisc = true; |
a35f71f2 MHY |
562 | break; |
563 | case MLX5_ACTION_DEL: | |
564 | if (!iter_vaddr) | |
565 | continue; | |
74491de9 | 566 | mlx5_del_flow_rules(iter_vaddr->flow_rule); |
a35f71f2 MHY |
567 | l2addr_hash_del(iter_vaddr); |
568 | break; | |
569 | } | |
570 | } | |
571 | } | |
572 | ||
81848731 SM |
573 | static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) |
574 | { | |
575 | struct hlist_head *hash = esw->mc_table; | |
576 | struct esw_mc_addr *esw_mc; | |
577 | u8 *mac = vaddr->node.addr; | |
578 | u32 vport = vaddr->vport; | |
579 | ||
580 | if (!esw->fdb_table.fdb) | |
581 | return 0; | |
582 | ||
583 | esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr); | |
584 | if (esw_mc) | |
585 | goto add; | |
586 | ||
587 | esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL); | |
588 | if (!esw_mc) | |
589 | return -ENOMEM; | |
590 | ||
591 | esw_mc->uplink_rule = /* Forward MC MAC to Uplink */ | |
592 | esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT); | |
a35f71f2 MHY |
593 | |
594 | /* Add this multicast mac to all the mc promiscuous vports */ | |
595 | update_allmulti_vports(esw, vaddr, esw_mc); | |
596 | ||
81848731 | 597 | add: |
a35f71f2 MHY |
598 | /* If the multicast mac is added as a result of mc promiscuous vport, |
599 | * don't increment the multicast ref count | |
600 | */ | |
601 | if (!vaddr->mc_promisc) | |
602 | esw_mc->refcnt++; | |
603 | ||
81848731 SM |
604 | /* Forward MC MAC to vport */ |
605 | vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport); | |
606 | esw_debug(esw->dev, | |
607 | "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n", | |
608 | vport, mac, vaddr->flow_rule, | |
609 | esw_mc->refcnt, esw_mc->uplink_rule); | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
614 | { | |
615 | struct hlist_head *hash = esw->mc_table; | |
616 | struct esw_mc_addr *esw_mc; | |
617 | u8 *mac = vaddr->node.addr; | |
618 | u32 vport = vaddr->vport; | |
073bb189 | 619 | |
81848731 SM |
620 | if (!esw->fdb_table.fdb) |
621 | return 0; | |
622 | ||
623 | esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr); | |
624 | if (!esw_mc) { | |
625 | esw_warn(esw->dev, | |
626 | "Failed to find eswitch MC addr for MAC(%pM) vport(%d)", | |
073bb189 SM |
627 | mac, vport); |
628 | return -EINVAL; | |
629 | } | |
81848731 SM |
630 | esw_debug(esw->dev, |
631 | "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n", | |
632 | vport, mac, vaddr->flow_rule, esw_mc->refcnt, | |
633 | esw_mc->uplink_rule); | |
634 | ||
635 | if (vaddr->flow_rule) | |
74491de9 | 636 | mlx5_del_flow_rules(vaddr->flow_rule); |
81848731 SM |
637 | vaddr->flow_rule = NULL; |
638 | ||
a35f71f2 MHY |
639 | /* If the multicast mac is added as a result of mc promiscuous vport, |
640 | * don't decrement the multicast ref count. | |
641 | */ | |
642 | if (vaddr->mc_promisc || (--esw_mc->refcnt > 0)) | |
81848731 | 643 | return 0; |
073bb189 | 644 | |
a35f71f2 MHY |
645 | /* Remove this multicast mac from all the mc promiscuous vports */ |
646 | update_allmulti_vports(esw, vaddr, esw_mc); | |
647 | ||
81848731 | 648 | if (esw_mc->uplink_rule) |
74491de9 | 649 | mlx5_del_flow_rules(esw_mc->uplink_rule); |
81848731 SM |
650 | |
651 | l2addr_hash_del(esw_mc); | |
073bb189 SM |
652 | return 0; |
653 | } | |
654 | ||
81848731 SM |
655 | /* Apply vport UC/MC list to HW l2 table and FDB table */ |
656 | static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw, | |
657 | u32 vport_num, int list_type) | |
073bb189 SM |
658 | { |
659 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
81848731 SM |
660 | bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC; |
661 | vport_addr_action vport_addr_add; | |
662 | vport_addr_action vport_addr_del; | |
663 | struct vport_addr *addr; | |
073bb189 SM |
664 | struct l2addr_node *node; |
665 | struct hlist_head *hash; | |
666 | struct hlist_node *tmp; | |
667 | int hi; | |
668 | ||
81848731 SM |
669 | vport_addr_add = is_uc ? esw_add_uc_addr : |
670 | esw_add_mc_addr; | |
671 | vport_addr_del = is_uc ? esw_del_uc_addr : | |
672 | esw_del_mc_addr; | |
673 | ||
674 | hash = is_uc ? vport->uc_list : vport->mc_list; | |
073bb189 | 675 | for_each_l2hash_node(node, tmp, hash, hi) { |
81848731 | 676 | addr = container_of(node, struct vport_addr, node); |
073bb189 SM |
677 | switch (addr->action) { |
678 | case MLX5_ACTION_ADD: | |
81848731 | 679 | vport_addr_add(esw, addr); |
073bb189 SM |
680 | addr->action = MLX5_ACTION_NONE; |
681 | break; | |
682 | case MLX5_ACTION_DEL: | |
81848731 | 683 | vport_addr_del(esw, addr); |
073bb189 SM |
684 | l2addr_hash_del(addr); |
685 | break; | |
686 | } | |
687 | } | |
688 | } | |
689 | ||
81848731 SM |
690 | /* Sync vport UC/MC list from vport context */ |
691 | static void esw_update_vport_addr_list(struct mlx5_eswitch *esw, | |
692 | u32 vport_num, int list_type) | |
073bb189 SM |
693 | { |
694 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
81848731 | 695 | bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC; |
073bb189 | 696 | u8 (*mac_list)[ETH_ALEN]; |
81848731 SM |
697 | struct l2addr_node *node; |
698 | struct vport_addr *addr; | |
073bb189 SM |
699 | struct hlist_head *hash; |
700 | struct hlist_node *tmp; | |
701 | int size; | |
702 | int err; | |
703 | int hi; | |
704 | int i; | |
705 | ||
81848731 SM |
706 | size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) : |
707 | MLX5_MAX_MC_PER_VPORT(esw->dev); | |
073bb189 SM |
708 | |
709 | mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL); | |
710 | if (!mac_list) | |
711 | return; | |
712 | ||
81848731 | 713 | hash = is_uc ? vport->uc_list : vport->mc_list; |
073bb189 SM |
714 | |
715 | for_each_l2hash_node(node, tmp, hash, hi) { | |
81848731 | 716 | addr = container_of(node, struct vport_addr, node); |
073bb189 SM |
717 | addr->action = MLX5_ACTION_DEL; |
718 | } | |
719 | ||
586cfa7f MHY |
720 | if (!vport->enabled) |
721 | goto out; | |
722 | ||
81848731 | 723 | err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type, |
073bb189 SM |
724 | mac_list, &size); |
725 | if (err) | |
761e205b | 726 | goto out; |
81848731 SM |
727 | esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n", |
728 | vport_num, is_uc ? "UC" : "MC", size); | |
073bb189 SM |
729 | |
730 | for (i = 0; i < size; i++) { | |
81848731 | 731 | if (is_uc && !is_valid_ether_addr(mac_list[i])) |
073bb189 SM |
732 | continue; |
733 | ||
81848731 SM |
734 | if (!is_uc && !is_multicast_ether_addr(mac_list[i])) |
735 | continue; | |
736 | ||
737 | addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr); | |
073bb189 SM |
738 | if (addr) { |
739 | addr->action = MLX5_ACTION_NONE; | |
a35f71f2 MHY |
740 | /* If this mac was previously added because of allmulti |
741 | * promiscuous rx mode, its now converted to be original | |
742 | * vport mac. | |
743 | */ | |
744 | if (addr->mc_promisc) { | |
745 | struct esw_mc_addr *esw_mc = | |
746 | l2addr_hash_find(esw->mc_table, | |
747 | mac_list[i], | |
748 | struct esw_mc_addr); | |
749 | if (!esw_mc) { | |
750 | esw_warn(esw->dev, | |
751 | "Failed to MAC(%pM) in mcast DB\n", | |
752 | mac_list[i]); | |
753 | continue; | |
754 | } | |
755 | esw_mc->refcnt++; | |
756 | addr->mc_promisc = false; | |
757 | } | |
073bb189 SM |
758 | continue; |
759 | } | |
760 | ||
81848731 | 761 | addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr, |
073bb189 SM |
762 | GFP_KERNEL); |
763 | if (!addr) { | |
764 | esw_warn(esw->dev, | |
765 | "Failed to add MAC(%pM) to vport[%d] DB\n", | |
766 | mac_list[i], vport_num); | |
767 | continue; | |
768 | } | |
81848731 | 769 | addr->vport = vport_num; |
073bb189 SM |
770 | addr->action = MLX5_ACTION_ADD; |
771 | } | |
761e205b | 772 | out: |
073bb189 SM |
773 | kfree(mac_list); |
774 | } | |
775 | ||
a35f71f2 MHY |
776 | /* Sync vport UC/MC list from vport context |
777 | * Must be called after esw_update_vport_addr_list | |
778 | */ | |
779 | static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num) | |
780 | { | |
781 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
782 | struct l2addr_node *node; | |
783 | struct vport_addr *addr; | |
784 | struct hlist_head *hash; | |
785 | struct hlist_node *tmp; | |
786 | int hi; | |
787 | ||
788 | hash = vport->mc_list; | |
789 | ||
790 | for_each_l2hash_node(node, tmp, esw->mc_table, hi) { | |
791 | u8 *mac = node->addr; | |
792 | ||
793 | addr = l2addr_hash_find(hash, mac, struct vport_addr); | |
794 | if (addr) { | |
795 | if (addr->action == MLX5_ACTION_DEL) | |
796 | addr->action = MLX5_ACTION_NONE; | |
797 | continue; | |
798 | } | |
799 | addr = l2addr_hash_add(hash, mac, struct vport_addr, | |
800 | GFP_KERNEL); | |
801 | if (!addr) { | |
802 | esw_warn(esw->dev, | |
803 | "Failed to add allmulti MAC(%pM) to vport[%d] DB\n", | |
804 | mac, vport_num); | |
805 | continue; | |
806 | } | |
807 | addr->vport = vport_num; | |
808 | addr->action = MLX5_ACTION_ADD; | |
809 | addr->mc_promisc = true; | |
810 | } | |
811 | } | |
812 | ||
813 | /* Apply vport rx mode to HW FDB table */ | |
814 | static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num, | |
815 | bool promisc, bool mc_promisc) | |
816 | { | |
817 | struct esw_mc_addr *allmulti_addr = esw->mc_promisc; | |
818 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
819 | ||
820 | if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc) | |
821 | goto promisc; | |
822 | ||
823 | if (mc_promisc) { | |
824 | vport->allmulti_rule = | |
825 | esw_fdb_set_vport_allmulti_rule(esw, vport_num); | |
826 | if (!allmulti_addr->uplink_rule) | |
827 | allmulti_addr->uplink_rule = | |
828 | esw_fdb_set_vport_allmulti_rule(esw, | |
829 | UPLINK_VPORT); | |
830 | allmulti_addr->refcnt++; | |
831 | } else if (vport->allmulti_rule) { | |
74491de9 | 832 | mlx5_del_flow_rules(vport->allmulti_rule); |
a35f71f2 MHY |
833 | vport->allmulti_rule = NULL; |
834 | ||
835 | if (--allmulti_addr->refcnt > 0) | |
836 | goto promisc; | |
837 | ||
838 | if (allmulti_addr->uplink_rule) | |
74491de9 | 839 | mlx5_del_flow_rules(allmulti_addr->uplink_rule); |
a35f71f2 MHY |
840 | allmulti_addr->uplink_rule = NULL; |
841 | } | |
842 | ||
843 | promisc: | |
844 | if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc) | |
845 | return; | |
846 | ||
847 | if (promisc) { | |
848 | vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw, | |
849 | vport_num); | |
850 | } else if (vport->promisc_rule) { | |
74491de9 | 851 | mlx5_del_flow_rules(vport->promisc_rule); |
a35f71f2 MHY |
852 | vport->promisc_rule = NULL; |
853 | } | |
854 | } | |
855 | ||
856 | /* Sync vport rx mode from vport context */ | |
857 | static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num) | |
858 | { | |
859 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
860 | int promisc_all = 0; | |
861 | int promisc_uc = 0; | |
862 | int promisc_mc = 0; | |
863 | int err; | |
864 | ||
865 | err = mlx5_query_nic_vport_promisc(esw->dev, | |
866 | vport_num, | |
867 | &promisc_uc, | |
868 | &promisc_mc, | |
869 | &promisc_all); | |
870 | if (err) | |
871 | return; | |
872 | esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n", | |
873 | vport_num, promisc_all, promisc_mc); | |
874 | ||
1ab2068a | 875 | if (!vport->info.trusted || !vport->enabled) { |
a35f71f2 MHY |
876 | promisc_uc = 0; |
877 | promisc_mc = 0; | |
878 | promisc_all = 0; | |
879 | } | |
880 | ||
881 | esw_apply_vport_rx_mode(esw, vport_num, promisc_all, | |
882 | (promisc_all || promisc_mc)); | |
883 | } | |
884 | ||
1edc57e2 | 885 | static void esw_vport_change_handle_locked(struct mlx5_vport *vport) |
073bb189 | 886 | { |
073bb189 | 887 | struct mlx5_core_dev *dev = vport->dev; |
81848731 | 888 | struct mlx5_eswitch *esw = dev->priv.eswitch; |
073bb189 SM |
889 | u8 mac[ETH_ALEN]; |
890 | ||
891 | mlx5_query_nic_vport_mac_address(dev, vport->vport, mac); | |
81848731 SM |
892 | esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n", |
893 | vport->vport, mac); | |
894 | ||
895 | if (vport->enabled_events & UC_ADDR_CHANGE) { | |
896 | esw_update_vport_addr_list(esw, vport->vport, | |
897 | MLX5_NVPRT_LIST_TYPE_UC); | |
898 | esw_apply_vport_addr_list(esw, vport->vport, | |
899 | MLX5_NVPRT_LIST_TYPE_UC); | |
900 | } | |
073bb189 | 901 | |
81848731 SM |
902 | if (vport->enabled_events & MC_ADDR_CHANGE) { |
903 | esw_update_vport_addr_list(esw, vport->vport, | |
904 | MLX5_NVPRT_LIST_TYPE_MC); | |
a35f71f2 MHY |
905 | } |
906 | ||
907 | if (vport->enabled_events & PROMISC_CHANGE) { | |
908 | esw_update_vport_rx_mode(esw, vport->vport); | |
909 | if (!IS_ERR_OR_NULL(vport->allmulti_rule)) | |
910 | esw_update_vport_mc_promisc(esw, vport->vport); | |
911 | } | |
912 | ||
913 | if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) { | |
81848731 SM |
914 | esw_apply_vport_addr_list(esw, vport->vport, |
915 | MLX5_NVPRT_LIST_TYPE_MC); | |
916 | } | |
073bb189 | 917 | |
81848731 | 918 | esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport); |
073bb189 SM |
919 | if (vport->enabled) |
920 | arm_vport_context_events_cmd(dev, vport->vport, | |
81848731 | 921 | vport->enabled_events); |
073bb189 SM |
922 | } |
923 | ||
1edc57e2 MHY |
924 | static void esw_vport_change_handler(struct work_struct *work) |
925 | { | |
926 | struct mlx5_vport *vport = | |
927 | container_of(work, struct mlx5_vport, vport_change_handler); | |
928 | struct mlx5_eswitch *esw = vport->dev->priv.eswitch; | |
929 | ||
930 | mutex_lock(&esw->state_lock); | |
931 | esw_vport_change_handle_locked(vport); | |
932 | mutex_unlock(&esw->state_lock); | |
933 | } | |
934 | ||
247f139c MHY |
935 | static int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw, |
936 | struct mlx5_vport *vport) | |
5742df0f MHY |
937 | { |
938 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
939 | struct mlx5_flow_group *vlan_grp = NULL; | |
940 | struct mlx5_flow_group *drop_grp = NULL; | |
941 | struct mlx5_core_dev *dev = esw->dev; | |
942 | struct mlx5_flow_namespace *root_ns; | |
943 | struct mlx5_flow_table *acl; | |
944 | void *match_criteria; | |
945 | u32 *flow_group_in; | |
946 | /* The egress acl table contains 2 rules: | |
947 | * 1)Allow traffic with vlan_tag=vst_vlan_id | |
948 | * 2)Drop all other traffic. | |
949 | */ | |
950 | int table_size = 2; | |
951 | int err = 0; | |
952 | ||
247f139c MHY |
953 | if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support)) |
954 | return -EOPNOTSUPP; | |
955 | ||
956 | if (!IS_ERR_OR_NULL(vport->egress.acl)) | |
957 | return 0; | |
5742df0f MHY |
958 | |
959 | esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n", | |
960 | vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size)); | |
961 | ||
962 | root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS); | |
963 | if (!root_ns) { | |
964 | esw_warn(dev, "Failed to get E-Switch egress flow namespace\n"); | |
eff596da | 965 | return -EOPNOTSUPP; |
5742df0f MHY |
966 | } |
967 | ||
968 | flow_group_in = mlx5_vzalloc(inlen); | |
969 | if (!flow_group_in) | |
247f139c | 970 | return -ENOMEM; |
5742df0f MHY |
971 | |
972 | acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport); | |
3f42ac66 | 973 | if (IS_ERR(acl)) { |
5742df0f MHY |
974 | err = PTR_ERR(acl); |
975 | esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n", | |
976 | vport->vport, err); | |
977 | goto out; | |
978 | } | |
979 | ||
980 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS); | |
981 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); | |
982 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag); | |
983 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid); | |
984 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
985 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0); | |
986 | ||
987 | vlan_grp = mlx5_create_flow_group(acl, flow_group_in); | |
3f42ac66 | 988 | if (IS_ERR(vlan_grp)) { |
5742df0f MHY |
989 | err = PTR_ERR(vlan_grp); |
990 | esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n", | |
991 | vport->vport, err); | |
992 | goto out; | |
993 | } | |
994 | ||
995 | memset(flow_group_in, 0, inlen); | |
996 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1); | |
997 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1); | |
998 | drop_grp = mlx5_create_flow_group(acl, flow_group_in); | |
3f42ac66 | 999 | if (IS_ERR(drop_grp)) { |
5742df0f MHY |
1000 | err = PTR_ERR(drop_grp); |
1001 | esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n", | |
1002 | vport->vport, err); | |
1003 | goto out; | |
1004 | } | |
1005 | ||
1006 | vport->egress.acl = acl; | |
1007 | vport->egress.drop_grp = drop_grp; | |
1008 | vport->egress.allowed_vlans_grp = vlan_grp; | |
1009 | out: | |
3fe3d819 | 1010 | kvfree(flow_group_in); |
5742df0f MHY |
1011 | if (err && !IS_ERR_OR_NULL(vlan_grp)) |
1012 | mlx5_destroy_flow_group(vlan_grp); | |
1013 | if (err && !IS_ERR_OR_NULL(acl)) | |
1014 | mlx5_destroy_flow_table(acl); | |
247f139c | 1015 | return err; |
5742df0f MHY |
1016 | } |
1017 | ||
dfcb1ed3 MHY |
1018 | static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw, |
1019 | struct mlx5_vport *vport) | |
1020 | { | |
1021 | if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan)) | |
74491de9 | 1022 | mlx5_del_flow_rules(vport->egress.allowed_vlan); |
dfcb1ed3 MHY |
1023 | |
1024 | if (!IS_ERR_OR_NULL(vport->egress.drop_rule)) | |
74491de9 | 1025 | mlx5_del_flow_rules(vport->egress.drop_rule); |
dfcb1ed3 MHY |
1026 | |
1027 | vport->egress.allowed_vlan = NULL; | |
1028 | vport->egress.drop_rule = NULL; | |
1029 | } | |
1030 | ||
5742df0f MHY |
1031 | static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw, |
1032 | struct mlx5_vport *vport) | |
1033 | { | |
1034 | if (IS_ERR_OR_NULL(vport->egress.acl)) | |
1035 | return; | |
1036 | ||
1037 | esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport); | |
1038 | ||
dfcb1ed3 | 1039 | esw_vport_cleanup_egress_rules(esw, vport); |
5742df0f MHY |
1040 | mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp); |
1041 | mlx5_destroy_flow_group(vport->egress.drop_grp); | |
1042 | mlx5_destroy_flow_table(vport->egress.acl); | |
1043 | vport->egress.allowed_vlans_grp = NULL; | |
1044 | vport->egress.drop_grp = NULL; | |
1045 | vport->egress.acl = NULL; | |
1046 | } | |
1047 | ||
247f139c MHY |
1048 | static int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw, |
1049 | struct mlx5_vport *vport) | |
5742df0f MHY |
1050 | { |
1051 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
1052 | struct mlx5_core_dev *dev = esw->dev; | |
1053 | struct mlx5_flow_namespace *root_ns; | |
1054 | struct mlx5_flow_table *acl; | |
1055 | struct mlx5_flow_group *g; | |
1056 | void *match_criteria; | |
1057 | u32 *flow_group_in; | |
1058 | /* The ingress acl table contains 4 groups | |
1059 | * (2 active rules at the same time - | |
1060 | * 1 allow rule from one of the first 3 groups. | |
1061 | * 1 drop rule from the last group): | |
1062 | * 1)Allow untagged traffic with smac=original mac. | |
1063 | * 2)Allow untagged traffic. | |
1064 | * 3)Allow traffic with smac=original mac. | |
1065 | * 4)Drop all other traffic. | |
1066 | */ | |
1067 | int table_size = 4; | |
1068 | int err = 0; | |
1069 | ||
247f139c MHY |
1070 | if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support)) |
1071 | return -EOPNOTSUPP; | |
1072 | ||
1073 | if (!IS_ERR_OR_NULL(vport->ingress.acl)) | |
1074 | return 0; | |
5742df0f MHY |
1075 | |
1076 | esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n", | |
1077 | vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size)); | |
1078 | ||
1079 | root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS); | |
1080 | if (!root_ns) { | |
1081 | esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n"); | |
eff596da | 1082 | return -EOPNOTSUPP; |
5742df0f MHY |
1083 | } |
1084 | ||
1085 | flow_group_in = mlx5_vzalloc(inlen); | |
1086 | if (!flow_group_in) | |
247f139c | 1087 | return -ENOMEM; |
5742df0f MHY |
1088 | |
1089 | acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport); | |
3f42ac66 | 1090 | if (IS_ERR(acl)) { |
5742df0f MHY |
1091 | err = PTR_ERR(acl); |
1092 | esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n", | |
1093 | vport->vport, err); | |
1094 | goto out; | |
1095 | } | |
1096 | vport->ingress.acl = acl; | |
1097 | ||
1098 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); | |
1099 | ||
1100 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS); | |
1101 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag); | |
1102 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16); | |
1103 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0); | |
1104 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
1105 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0); | |
1106 | ||
1107 | g = mlx5_create_flow_group(acl, flow_group_in); | |
3f42ac66 | 1108 | if (IS_ERR(g)) { |
5742df0f MHY |
1109 | err = PTR_ERR(g); |
1110 | esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n", | |
1111 | vport->vport, err); | |
1112 | goto out; | |
1113 | } | |
1114 | vport->ingress.allow_untagged_spoofchk_grp = g; | |
1115 | ||
1116 | memset(flow_group_in, 0, inlen); | |
1117 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS); | |
1118 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag); | |
1119 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1); | |
1120 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1); | |
1121 | ||
1122 | g = mlx5_create_flow_group(acl, flow_group_in); | |
3f42ac66 | 1123 | if (IS_ERR(g)) { |
5742df0f MHY |
1124 | err = PTR_ERR(g); |
1125 | esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n", | |
1126 | vport->vport, err); | |
1127 | goto out; | |
1128 | } | |
1129 | vport->ingress.allow_untagged_only_grp = g; | |
1130 | ||
1131 | memset(flow_group_in, 0, inlen); | |
1132 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS); | |
1133 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16); | |
1134 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0); | |
1135 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2); | |
1136 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2); | |
1137 | ||
1138 | g = mlx5_create_flow_group(acl, flow_group_in); | |
3f42ac66 | 1139 | if (IS_ERR(g)) { |
5742df0f MHY |
1140 | err = PTR_ERR(g); |
1141 | esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n", | |
1142 | vport->vport, err); | |
1143 | goto out; | |
1144 | } | |
1145 | vport->ingress.allow_spoofchk_only_grp = g; | |
1146 | ||
1147 | memset(flow_group_in, 0, inlen); | |
1148 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3); | |
1149 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3); | |
1150 | ||
1151 | g = mlx5_create_flow_group(acl, flow_group_in); | |
3f42ac66 | 1152 | if (IS_ERR(g)) { |
5742df0f MHY |
1153 | err = PTR_ERR(g); |
1154 | esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n", | |
1155 | vport->vport, err); | |
1156 | goto out; | |
1157 | } | |
1158 | vport->ingress.drop_grp = g; | |
1159 | ||
1160 | out: | |
1161 | if (err) { | |
1162 | if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp)) | |
1163 | mlx5_destroy_flow_group( | |
1164 | vport->ingress.allow_spoofchk_only_grp); | |
1165 | if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp)) | |
1166 | mlx5_destroy_flow_group( | |
1167 | vport->ingress.allow_untagged_only_grp); | |
1168 | if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp)) | |
1169 | mlx5_destroy_flow_group( | |
1170 | vport->ingress.allow_untagged_spoofchk_grp); | |
1171 | if (!IS_ERR_OR_NULL(vport->ingress.acl)) | |
1172 | mlx5_destroy_flow_table(vport->ingress.acl); | |
1173 | } | |
1174 | ||
3fe3d819 | 1175 | kvfree(flow_group_in); |
247f139c | 1176 | return err; |
5742df0f MHY |
1177 | } |
1178 | ||
dfcb1ed3 MHY |
1179 | static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw, |
1180 | struct mlx5_vport *vport) | |
1181 | { | |
1182 | if (!IS_ERR_OR_NULL(vport->ingress.drop_rule)) | |
74491de9 | 1183 | mlx5_del_flow_rules(vport->ingress.drop_rule); |
f942380c MHY |
1184 | |
1185 | if (!IS_ERR_OR_NULL(vport->ingress.allow_rule)) | |
74491de9 | 1186 | mlx5_del_flow_rules(vport->ingress.allow_rule); |
f942380c | 1187 | |
dfcb1ed3 | 1188 | vport->ingress.drop_rule = NULL; |
f942380c | 1189 | vport->ingress.allow_rule = NULL; |
dfcb1ed3 MHY |
1190 | } |
1191 | ||
5742df0f MHY |
1192 | static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw, |
1193 | struct mlx5_vport *vport) | |
1194 | { | |
1195 | if (IS_ERR_OR_NULL(vport->ingress.acl)) | |
1196 | return; | |
1197 | ||
1198 | esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport); | |
1199 | ||
dfcb1ed3 | 1200 | esw_vport_cleanup_ingress_rules(esw, vport); |
5742df0f MHY |
1201 | mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp); |
1202 | mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp); | |
1203 | mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp); | |
1204 | mlx5_destroy_flow_group(vport->ingress.drop_grp); | |
1205 | mlx5_destroy_flow_table(vport->ingress.acl); | |
1206 | vport->ingress.acl = NULL; | |
1207 | vport->ingress.drop_grp = NULL; | |
1208 | vport->ingress.allow_spoofchk_only_grp = NULL; | |
1209 | vport->ingress.allow_untagged_only_grp = NULL; | |
1210 | vport->ingress.allow_untagged_spoofchk_grp = NULL; | |
1211 | } | |
1212 | ||
dfcb1ed3 MHY |
1213 | static int esw_vport_ingress_config(struct mlx5_eswitch *esw, |
1214 | struct mlx5_vport *vport) | |
1215 | { | |
66958ed9 | 1216 | struct mlx5_flow_act flow_act = {0}; |
c5bb1730 | 1217 | struct mlx5_flow_spec *spec; |
dfcb1ed3 | 1218 | int err = 0; |
f942380c | 1219 | u8 *smac_v; |
dfcb1ed3 | 1220 | |
1ab2068a MHY |
1221 | if (vport->info.spoofchk && !is_valid_ether_addr(vport->info.mac)) { |
1222 | mlx5_core_warn(esw->dev, | |
1223 | "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n", | |
1224 | vport->vport); | |
1225 | return -EPERM; | |
f942380c | 1226 | |
f942380c MHY |
1227 | } |
1228 | ||
dfcb1ed3 MHY |
1229 | esw_vport_cleanup_ingress_rules(esw, vport); |
1230 | ||
1ab2068a | 1231 | if (!vport->info.vlan && !vport->info.qos && !vport->info.spoofchk) { |
01f51f22 | 1232 | esw_vport_disable_ingress_acl(esw, vport); |
dfcb1ed3 | 1233 | return 0; |
01f51f22 MHY |
1234 | } |
1235 | ||
247f139c MHY |
1236 | err = esw_vport_enable_ingress_acl(esw, vport); |
1237 | if (err) { | |
1238 | mlx5_core_warn(esw->dev, | |
1239 | "failed to enable ingress acl (%d) on vport[%d]\n", | |
1240 | err, vport->vport); | |
1241 | return err; | |
1242 | } | |
dfcb1ed3 MHY |
1243 | |
1244 | esw_debug(esw->dev, | |
1245 | "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n", | |
1ab2068a | 1246 | vport->vport, vport->info.vlan, vport->info.qos); |
dfcb1ed3 | 1247 | |
c5bb1730 MG |
1248 | spec = mlx5_vzalloc(sizeof(*spec)); |
1249 | if (!spec) { | |
dfcb1ed3 MHY |
1250 | err = -ENOMEM; |
1251 | esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n", | |
1252 | vport->vport, err); | |
1253 | goto out; | |
1254 | } | |
dfcb1ed3 | 1255 | |
1ab2068a | 1256 | if (vport->info.vlan || vport->info.qos) |
c5bb1730 | 1257 | MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag); |
f942380c | 1258 | |
1ab2068a | 1259 | if (vport->info.spoofchk) { |
c5bb1730 MG |
1260 | MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16); |
1261 | MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_15_0); | |
f942380c | 1262 | smac_v = MLX5_ADDR_OF(fte_match_param, |
c5bb1730 | 1263 | spec->match_value, |
f942380c | 1264 | outer_headers.smac_47_16); |
1ab2068a | 1265 | ether_addr_copy(smac_v, vport->info.mac); |
f942380c MHY |
1266 | } |
1267 | ||
c5bb1730 | 1268 | spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS; |
66958ed9 | 1269 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_ALLOW; |
f942380c | 1270 | vport->ingress.allow_rule = |
74491de9 | 1271 | mlx5_add_flow_rules(vport->ingress.acl, spec, |
66958ed9 | 1272 | &flow_act, NULL, 0); |
3f42ac66 | 1273 | if (IS_ERR(vport->ingress.allow_rule)) { |
f942380c | 1274 | err = PTR_ERR(vport->ingress.allow_rule); |
2974ab6e SM |
1275 | esw_warn(esw->dev, |
1276 | "vport[%d] configure ingress allow rule, err(%d)\n", | |
1277 | vport->vport, err); | |
f942380c MHY |
1278 | vport->ingress.allow_rule = NULL; |
1279 | goto out; | |
1280 | } | |
1281 | ||
c5bb1730 | 1282 | memset(spec, 0, sizeof(*spec)); |
66958ed9 | 1283 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; |
f942380c | 1284 | vport->ingress.drop_rule = |
74491de9 | 1285 | mlx5_add_flow_rules(vport->ingress.acl, spec, |
66958ed9 | 1286 | &flow_act, NULL, 0); |
3f42ac66 | 1287 | if (IS_ERR(vport->ingress.drop_rule)) { |
dfcb1ed3 | 1288 | err = PTR_ERR(vport->ingress.drop_rule); |
2974ab6e SM |
1289 | esw_warn(esw->dev, |
1290 | "vport[%d] configure ingress drop rule, err(%d)\n", | |
1291 | vport->vport, err); | |
dfcb1ed3 | 1292 | vport->ingress.drop_rule = NULL; |
f942380c | 1293 | goto out; |
dfcb1ed3 | 1294 | } |
f942380c | 1295 | |
dfcb1ed3 | 1296 | out: |
f942380c MHY |
1297 | if (err) |
1298 | esw_vport_cleanup_ingress_rules(esw, vport); | |
c5bb1730 | 1299 | kvfree(spec); |
dfcb1ed3 MHY |
1300 | return err; |
1301 | } | |
1302 | ||
1303 | static int esw_vport_egress_config(struct mlx5_eswitch *esw, | |
1304 | struct mlx5_vport *vport) | |
1305 | { | |
66958ed9 | 1306 | struct mlx5_flow_act flow_act = {0}; |
c5bb1730 | 1307 | struct mlx5_flow_spec *spec; |
dfcb1ed3 MHY |
1308 | int err = 0; |
1309 | ||
dfcb1ed3 MHY |
1310 | esw_vport_cleanup_egress_rules(esw, vport); |
1311 | ||
1ab2068a | 1312 | if (!vport->info.vlan && !vport->info.qos) { |
01f51f22 | 1313 | esw_vport_disable_egress_acl(esw, vport); |
dfcb1ed3 | 1314 | return 0; |
01f51f22 MHY |
1315 | } |
1316 | ||
247f139c MHY |
1317 | err = esw_vport_enable_egress_acl(esw, vport); |
1318 | if (err) { | |
1319 | mlx5_core_warn(esw->dev, | |
1320 | "failed to enable egress acl (%d) on vport[%d]\n", | |
1321 | err, vport->vport); | |
1322 | return err; | |
1323 | } | |
dfcb1ed3 MHY |
1324 | |
1325 | esw_debug(esw->dev, | |
1326 | "vport[%d] configure egress rules, vlan(%d) qos(%d)\n", | |
1ab2068a | 1327 | vport->vport, vport->info.vlan, vport->info.qos); |
dfcb1ed3 | 1328 | |
c5bb1730 MG |
1329 | spec = mlx5_vzalloc(sizeof(*spec)); |
1330 | if (!spec) { | |
dfcb1ed3 MHY |
1331 | err = -ENOMEM; |
1332 | esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n", | |
1333 | vport->vport, err); | |
1334 | goto out; | |
1335 | } | |
1336 | ||
1337 | /* Allowed vlan rule */ | |
c5bb1730 MG |
1338 | MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag); |
1339 | MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.vlan_tag); | |
1340 | MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid); | |
1ab2068a | 1341 | MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->info.vlan); |
dfcb1ed3 | 1342 | |
c5bb1730 | 1343 | spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS; |
66958ed9 | 1344 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_ALLOW; |
dfcb1ed3 | 1345 | vport->egress.allowed_vlan = |
74491de9 | 1346 | mlx5_add_flow_rules(vport->egress.acl, spec, |
66958ed9 | 1347 | &flow_act, NULL, 0); |
3f42ac66 | 1348 | if (IS_ERR(vport->egress.allowed_vlan)) { |
dfcb1ed3 | 1349 | err = PTR_ERR(vport->egress.allowed_vlan); |
2974ab6e SM |
1350 | esw_warn(esw->dev, |
1351 | "vport[%d] configure egress allowed vlan rule failed, err(%d)\n", | |
1352 | vport->vport, err); | |
dfcb1ed3 MHY |
1353 | vport->egress.allowed_vlan = NULL; |
1354 | goto out; | |
1355 | } | |
1356 | ||
1357 | /* Drop others rule (star rule) */ | |
c5bb1730 | 1358 | memset(spec, 0, sizeof(*spec)); |
66958ed9 | 1359 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; |
dfcb1ed3 | 1360 | vport->egress.drop_rule = |
74491de9 | 1361 | mlx5_add_flow_rules(vport->egress.acl, spec, |
66958ed9 | 1362 | &flow_act, NULL, 0); |
3f42ac66 | 1363 | if (IS_ERR(vport->egress.drop_rule)) { |
dfcb1ed3 | 1364 | err = PTR_ERR(vport->egress.drop_rule); |
2974ab6e SM |
1365 | esw_warn(esw->dev, |
1366 | "vport[%d] configure egress drop rule failed, err(%d)\n", | |
1367 | vport->vport, err); | |
dfcb1ed3 MHY |
1368 | vport->egress.drop_rule = NULL; |
1369 | } | |
1370 | out: | |
c5bb1730 | 1371 | kvfree(spec); |
dfcb1ed3 MHY |
1372 | return err; |
1373 | } | |
1374 | ||
1bd27b11 MHY |
1375 | /* Vport QoS management */ |
1376 | static int esw_create_tsar(struct mlx5_eswitch *esw) | |
1377 | { | |
1378 | u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; | |
1379 | struct mlx5_core_dev *dev = esw->dev; | |
1380 | int err; | |
1381 | ||
1382 | if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) | |
1383 | return 0; | |
1384 | ||
1385 | if (esw->qos.enabled) | |
1386 | return -EEXIST; | |
1387 | ||
1388 | err = mlx5_create_scheduling_element_cmd(dev, | |
1389 | SCHEDULING_HIERARCHY_E_SWITCH, | |
1390 | &tsar_ctx, | |
1391 | &esw->qos.root_tsar_id); | |
1392 | if (err) { | |
1393 | esw_warn(esw->dev, "E-Switch create TSAR failed (%d)\n", err); | |
1394 | return err; | |
1395 | } | |
1396 | ||
1397 | esw->qos.enabled = true; | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static void esw_destroy_tsar(struct mlx5_eswitch *esw) | |
1402 | { | |
1403 | int err; | |
1404 | ||
1405 | if (!esw->qos.enabled) | |
1406 | return; | |
1407 | ||
1408 | err = mlx5_destroy_scheduling_element_cmd(esw->dev, | |
1409 | SCHEDULING_HIERARCHY_E_SWITCH, | |
1410 | esw->qos.root_tsar_id); | |
1411 | if (err) | |
1412 | esw_warn(esw->dev, "E-Switch destroy TSAR failed (%d)\n", err); | |
1413 | ||
1414 | esw->qos.enabled = false; | |
1415 | } | |
1416 | ||
1417 | static int esw_vport_enable_qos(struct mlx5_eswitch *esw, int vport_num, | |
1418 | u32 initial_max_rate) | |
1419 | { | |
1420 | u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; | |
1421 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
1422 | struct mlx5_core_dev *dev = esw->dev; | |
1423 | void *vport_elem; | |
1424 | int err = 0; | |
1425 | ||
1426 | if (!esw->qos.enabled || !MLX5_CAP_GEN(dev, qos) || | |
1427 | !MLX5_CAP_QOS(dev, esw_scheduling)) | |
1428 | return 0; | |
1429 | ||
1430 | if (vport->qos.enabled) | |
1431 | return -EEXIST; | |
1432 | ||
1433 | MLX5_SET(scheduling_context, &sched_ctx, element_type, | |
1434 | SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); | |
1435 | vport_elem = MLX5_ADDR_OF(scheduling_context, &sched_ctx, | |
1436 | element_attributes); | |
1437 | MLX5_SET(vport_element, vport_elem, vport_number, vport_num); | |
1438 | MLX5_SET(scheduling_context, &sched_ctx, parent_element_id, | |
1439 | esw->qos.root_tsar_id); | |
1440 | MLX5_SET(scheduling_context, &sched_ctx, max_average_bw, | |
1441 | initial_max_rate); | |
1442 | ||
1443 | err = mlx5_create_scheduling_element_cmd(dev, | |
1444 | SCHEDULING_HIERARCHY_E_SWITCH, | |
1445 | &sched_ctx, | |
1446 | &vport->qos.esw_tsar_ix); | |
1447 | if (err) { | |
1448 | esw_warn(esw->dev, "E-Switch create TSAR vport element failed (vport=%d,err=%d)\n", | |
1449 | vport_num, err); | |
1450 | return err; | |
1451 | } | |
1452 | ||
1453 | vport->qos.enabled = true; | |
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | static void esw_vport_disable_qos(struct mlx5_eswitch *esw, int vport_num) | |
1458 | { | |
1459 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
1460 | int err = 0; | |
1461 | ||
1462 | if (!vport->qos.enabled) | |
1463 | return; | |
1464 | ||
1465 | err = mlx5_destroy_scheduling_element_cmd(esw->dev, | |
1466 | SCHEDULING_HIERARCHY_E_SWITCH, | |
1467 | vport->qos.esw_tsar_ix); | |
1468 | if (err) | |
1469 | esw_warn(esw->dev, "E-Switch destroy TSAR vport element failed (vport=%d,err=%d)\n", | |
1470 | vport_num, err); | |
1471 | ||
1472 | vport->qos.enabled = false; | |
1473 | } | |
1474 | ||
bd77bf1c MHY |
1475 | static int esw_vport_qos_config(struct mlx5_eswitch *esw, int vport_num, |
1476 | u32 max_rate) | |
1477 | { | |
1478 | u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; | |
1479 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
1480 | struct mlx5_core_dev *dev = esw->dev; | |
1481 | void *vport_elem; | |
1482 | u32 bitmask = 0; | |
1483 | int err = 0; | |
1484 | ||
1485 | if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) | |
1486 | return -EOPNOTSUPP; | |
1487 | ||
1488 | if (!vport->qos.enabled) | |
1489 | return -EIO; | |
1490 | ||
1491 | MLX5_SET(scheduling_context, &sched_ctx, element_type, | |
1492 | SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); | |
1493 | vport_elem = MLX5_ADDR_OF(scheduling_context, &sched_ctx, | |
1494 | element_attributes); | |
1495 | MLX5_SET(vport_element, vport_elem, vport_number, vport_num); | |
1496 | MLX5_SET(scheduling_context, &sched_ctx, parent_element_id, | |
1497 | esw->qos.root_tsar_id); | |
1498 | MLX5_SET(scheduling_context, &sched_ctx, max_average_bw, | |
1499 | max_rate); | |
1500 | bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW; | |
1501 | ||
1502 | err = mlx5_modify_scheduling_element_cmd(dev, | |
1503 | SCHEDULING_HIERARCHY_E_SWITCH, | |
1504 | &sched_ctx, | |
1505 | vport->qos.esw_tsar_ix, | |
1506 | bitmask); | |
1507 | if (err) { | |
1508 | esw_warn(esw->dev, "E-Switch modify TSAR vport element failed (vport=%d,err=%d)\n", | |
1509 | vport_num, err); | |
1510 | return err; | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
1ab2068a MHY |
1516 | static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN]) |
1517 | { | |
1518 | ((u8 *)node_guid)[7] = mac[0]; | |
1519 | ((u8 *)node_guid)[6] = mac[1]; | |
1520 | ((u8 *)node_guid)[5] = mac[2]; | |
1521 | ((u8 *)node_guid)[4] = 0xff; | |
1522 | ((u8 *)node_guid)[3] = 0xfe; | |
1523 | ((u8 *)node_guid)[2] = mac[3]; | |
1524 | ((u8 *)node_guid)[1] = mac[4]; | |
1525 | ((u8 *)node_guid)[0] = mac[5]; | |
1526 | } | |
1527 | ||
1528 | static void esw_apply_vport_conf(struct mlx5_eswitch *esw, | |
1529 | struct mlx5_vport *vport) | |
1530 | { | |
1531 | int vport_num = vport->vport; | |
1532 | ||
1533 | if (!vport_num) | |
1534 | return; | |
1535 | ||
1536 | mlx5_modify_vport_admin_state(esw->dev, | |
1537 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
1538 | vport_num, | |
1539 | vport->info.link_state); | |
1540 | mlx5_modify_nic_vport_mac_address(esw->dev, vport_num, vport->info.mac); | |
1541 | mlx5_modify_nic_vport_node_guid(esw->dev, vport_num, vport->info.node_guid); | |
1542 | modify_esw_vport_cvlan(esw->dev, vport_num, vport->info.vlan, vport->info.qos, | |
1543 | (vport->info.vlan || vport->info.qos)); | |
1544 | ||
1545 | /* Only legacy mode needs ACLs */ | |
1546 | if (esw->mode == SRIOV_LEGACY) { | |
1547 | esw_vport_ingress_config(esw, vport); | |
1548 | esw_vport_egress_config(esw, vport); | |
1549 | } | |
1550 | } | |
1bd27b11 | 1551 | |
81848731 SM |
1552 | static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num, |
1553 | int enable_events) | |
073bb189 SM |
1554 | { |
1555 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
073bb189 | 1556 | |
dfcb1ed3 | 1557 | mutex_lock(&esw->state_lock); |
81848731 SM |
1558 | WARN_ON(vport->enabled); |
1559 | ||
1560 | esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num); | |
5742df0f | 1561 | |
1ab2068a MHY |
1562 | /* Restore old vport configuration */ |
1563 | esw_apply_vport_conf(esw, vport); | |
81848731 | 1564 | |
1bd27b11 MHY |
1565 | /* Attach vport to the eswitch rate limiter */ |
1566 | if (esw_vport_enable_qos(esw, vport_num, vport->info.max_rate)) | |
1567 | esw_warn(esw->dev, "Failed to attach vport %d to eswitch rate limiter", vport_num); | |
1568 | ||
81848731 SM |
1569 | /* Sync with current vport context */ |
1570 | vport->enabled_events = enable_events; | |
073bb189 | 1571 | vport->enabled = true; |
073bb189 | 1572 | |
a35f71f2 | 1573 | /* only PF is trusted by default */ |
1ab2068a MHY |
1574 | if (!vport_num) |
1575 | vport->info.trusted = true; | |
1576 | ||
25fff58c | 1577 | esw_vport_change_handle_locked(vport); |
81848731 SM |
1578 | |
1579 | esw->enabled_vports++; | |
1580 | esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num); | |
dfcb1ed3 | 1581 | mutex_unlock(&esw->state_lock); |
81848731 SM |
1582 | } |
1583 | ||
073bb189 SM |
1584 | static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num) |
1585 | { | |
1586 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
073bb189 SM |
1587 | |
1588 | if (!vport->enabled) | |
1589 | return; | |
1590 | ||
81848731 | 1591 | esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num); |
073bb189 | 1592 | /* Mark this vport as disabled to discard new events */ |
073bb189 | 1593 | vport->enabled = false; |
831cae1d MHY |
1594 | |
1595 | synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC)); | |
073bb189 SM |
1596 | /* Wait for current already scheduled events to complete */ |
1597 | flush_workqueue(esw->work_queue); | |
073bb189 SM |
1598 | /* Disable events from this vport */ |
1599 | arm_vport_context_events_cmd(esw->dev, vport->vport, 0); | |
dfcb1ed3 | 1600 | mutex_lock(&esw->state_lock); |
586cfa7f MHY |
1601 | /* We don't assume VFs will cleanup after themselves. |
1602 | * Calling vport change handler while vport is disabled will cleanup | |
1603 | * the vport resources. | |
1604 | */ | |
1edc57e2 | 1605 | esw_vport_change_handle_locked(vport); |
586cfa7f | 1606 | vport->enabled_events = 0; |
1bd27b11 | 1607 | esw_vport_disable_qos(esw, vport_num); |
f96750f8 | 1608 | if (vport_num && esw->mode == SRIOV_LEGACY) { |
1ab2068a MHY |
1609 | mlx5_modify_vport_admin_state(esw->dev, |
1610 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
1611 | vport_num, | |
1612 | MLX5_ESW_VPORT_ADMIN_STATE_DOWN); | |
5742df0f MHY |
1613 | esw_vport_disable_egress_acl(esw, vport); |
1614 | esw_vport_disable_ingress_acl(esw, vport); | |
1615 | } | |
81848731 | 1616 | esw->enabled_vports--; |
dfcb1ed3 | 1617 | mutex_unlock(&esw->state_lock); |
073bb189 SM |
1618 | } |
1619 | ||
1620 | /* Public E-Switch API */ | |
6ab36e35 | 1621 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) |
81848731 SM |
1622 | { |
1623 | int err; | |
69697b6e | 1624 | int i, enabled_events; |
81848731 SM |
1625 | |
1626 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1627 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1628 | return 0; | |
1629 | ||
1630 | if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) || | |
1631 | !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) { | |
1632 | esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n"); | |
9eb78923 | 1633 | return -EOPNOTSUPP; |
81848731 SM |
1634 | } |
1635 | ||
5742df0f MHY |
1636 | if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support)) |
1637 | esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n"); | |
1638 | ||
1639 | if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support)) | |
1640 | esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n"); | |
1641 | ||
6ab36e35 | 1642 | esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode); |
6ab36e35 | 1643 | esw->mode = mode; |
81848731 SM |
1644 | esw_disable_vport(esw, 0); |
1645 | ||
69697b6e OG |
1646 | if (mode == SRIOV_LEGACY) |
1647 | err = esw_create_legacy_fdb_table(esw, nvfs + 1); | |
1648 | else | |
c930a3ad | 1649 | err = esw_offloads_init(esw, nvfs + 1); |
81848731 SM |
1650 | if (err) |
1651 | goto abort; | |
1652 | ||
1bd27b11 MHY |
1653 | err = esw_create_tsar(esw); |
1654 | if (err) | |
1655 | esw_warn(esw->dev, "Failed to create eswitch TSAR"); | |
1656 | ||
69697b6e | 1657 | enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE; |
81848731 | 1658 | for (i = 0; i <= nvfs; i++) |
69697b6e | 1659 | esw_enable_vport(esw, i, enabled_events); |
81848731 SM |
1660 | |
1661 | esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n", | |
1662 | esw->enabled_vports); | |
1663 | return 0; | |
1664 | ||
1665 | abort: | |
1666 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
4eea37d7 | 1667 | esw->mode = SRIOV_NONE; |
81848731 SM |
1668 | return err; |
1669 | } | |
1670 | ||
1671 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) | |
1672 | { | |
a35f71f2 | 1673 | struct esw_mc_addr *mc_promisc; |
c930a3ad | 1674 | int nvports; |
81848731 SM |
1675 | int i; |
1676 | ||
1677 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1678 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1679 | return; | |
1680 | ||
6ab36e35 OG |
1681 | esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n", |
1682 | esw->enabled_vports, esw->mode); | |
81848731 | 1683 | |
a35f71f2 | 1684 | mc_promisc = esw->mc_promisc; |
c930a3ad | 1685 | nvports = esw->enabled_vports; |
a35f71f2 | 1686 | |
81848731 SM |
1687 | for (i = 0; i < esw->total_vports; i++) |
1688 | esw_disable_vport(esw, i); | |
1689 | ||
a35f71f2 | 1690 | if (mc_promisc && mc_promisc->uplink_rule) |
74491de9 | 1691 | mlx5_del_flow_rules(mc_promisc->uplink_rule); |
a35f71f2 | 1692 | |
1bd27b11 | 1693 | esw_destroy_tsar(esw); |
a35f71f2 | 1694 | |
69697b6e OG |
1695 | if (esw->mode == SRIOV_LEGACY) |
1696 | esw_destroy_legacy_fdb_table(esw); | |
c930a3ad OG |
1697 | else if (esw->mode == SRIOV_OFFLOADS) |
1698 | esw_offloads_cleanup(esw, nvports); | |
81848731 | 1699 | |
6ab36e35 | 1700 | esw->mode = SRIOV_NONE; |
81848731 SM |
1701 | /* VPORT 0 (PF) must be enabled back with non-sriov configuration */ |
1702 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
1703 | } | |
1704 | ||
62a9b90a MHY |
1705 | void mlx5_eswitch_attach(struct mlx5_eswitch *esw) |
1706 | { | |
1707 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1708 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1709 | return; | |
1710 | ||
1711 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
1712 | /* VF Vports will be enabled when SRIOV is enabled */ | |
1713 | } | |
1714 | ||
1715 | void mlx5_eswitch_detach(struct mlx5_eswitch *esw) | |
1716 | { | |
1717 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1718 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1719 | return; | |
1720 | ||
1721 | esw_disable_vport(esw, 0); | |
1722 | } | |
1723 | ||
073bb189 SM |
1724 | int mlx5_eswitch_init(struct mlx5_core_dev *dev) |
1725 | { | |
1726 | int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table); | |
efdc810b | 1727 | int total_vports = MLX5_TOTAL_VPORTS(dev); |
a35f71f2 | 1728 | struct esw_mc_addr *mc_promisc; |
073bb189 SM |
1729 | struct mlx5_eswitch *esw; |
1730 | int vport_num; | |
1731 | int err; | |
1732 | ||
1733 | if (!MLX5_CAP_GEN(dev, vport_group_manager) || | |
1734 | MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1735 | return 0; | |
1736 | ||
1737 | esw_info(dev, | |
1738 | "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n", | |
1739 | total_vports, l2_table_size, | |
1740 | MLX5_MAX_UC_PER_VPORT(dev), | |
1741 | MLX5_MAX_MC_PER_VPORT(dev)); | |
1742 | ||
1743 | esw = kzalloc(sizeof(*esw), GFP_KERNEL); | |
1744 | if (!esw) | |
1745 | return -ENOMEM; | |
1746 | ||
1747 | esw->dev = dev; | |
1748 | ||
1749 | esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size), | |
1750 | sizeof(uintptr_t), GFP_KERNEL); | |
1751 | if (!esw->l2_table.bitmap) { | |
1752 | err = -ENOMEM; | |
1753 | goto abort; | |
1754 | } | |
1755 | esw->l2_table.size = l2_table_size; | |
1756 | ||
a35f71f2 MHY |
1757 | mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL); |
1758 | if (!mc_promisc) { | |
1759 | err = -ENOMEM; | |
1760 | goto abort; | |
1761 | } | |
1762 | esw->mc_promisc = mc_promisc; | |
1763 | ||
073bb189 SM |
1764 | esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq"); |
1765 | if (!esw->work_queue) { | |
1766 | err = -ENOMEM; | |
1767 | goto abort; | |
1768 | } | |
1769 | ||
1770 | esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport), | |
1771 | GFP_KERNEL); | |
1772 | if (!esw->vports) { | |
1773 | err = -ENOMEM; | |
1774 | goto abort; | |
1775 | } | |
1776 | ||
127ea380 HHZ |
1777 | esw->offloads.vport_reps = |
1778 | kzalloc(total_vports * sizeof(struct mlx5_eswitch_rep), | |
1779 | GFP_KERNEL); | |
1780 | if (!esw->offloads.vport_reps) { | |
1781 | err = -ENOMEM; | |
1782 | goto abort; | |
1783 | } | |
1784 | ||
a54e20b4 | 1785 | hash_init(esw->offloads.encap_tbl); |
dfcb1ed3 MHY |
1786 | mutex_init(&esw->state_lock); |
1787 | ||
073bb189 SM |
1788 | for (vport_num = 0; vport_num < total_vports; vport_num++) { |
1789 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
1790 | ||
1791 | vport->vport = vport_num; | |
1ab2068a | 1792 | vport->info.link_state = MLX5_ESW_VPORT_ADMIN_STATE_AUTO; |
073bb189 SM |
1793 | vport->dev = dev; |
1794 | INIT_WORK(&vport->vport_change_handler, | |
1795 | esw_vport_change_handler); | |
073bb189 SM |
1796 | } |
1797 | ||
81848731 SM |
1798 | esw->total_vports = total_vports; |
1799 | esw->enabled_vports = 0; | |
6ab36e35 | 1800 | esw->mode = SRIOV_NONE; |
bffaa916 | 1801 | esw->offloads.inline_mode = MLX5_INLINE_MODE_NONE; |
073bb189 | 1802 | |
81848731 | 1803 | dev->priv.eswitch = esw; |
073bb189 SM |
1804 | return 0; |
1805 | abort: | |
1806 | if (esw->work_queue) | |
1807 | destroy_workqueue(esw->work_queue); | |
1808 | kfree(esw->l2_table.bitmap); | |
1809 | kfree(esw->vports); | |
127ea380 | 1810 | kfree(esw->offloads.vport_reps); |
073bb189 SM |
1811 | kfree(esw); |
1812 | return err; | |
1813 | } | |
1814 | ||
1815 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) | |
1816 | { | |
1817 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1818 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1819 | return; | |
1820 | ||
1821 | esw_info(esw->dev, "cleanup\n"); | |
073bb189 SM |
1822 | |
1823 | esw->dev->priv.eswitch = NULL; | |
1824 | destroy_workqueue(esw->work_queue); | |
1825 | kfree(esw->l2_table.bitmap); | |
a35f71f2 | 1826 | kfree(esw->mc_promisc); |
127ea380 | 1827 | kfree(esw->offloads.vport_reps); |
073bb189 SM |
1828 | kfree(esw->vports); |
1829 | kfree(esw); | |
1830 | } | |
1831 | ||
1832 | void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) | |
1833 | { | |
1834 | struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change; | |
1835 | u16 vport_num = be16_to_cpu(vc_eqe->vport_num); | |
1836 | struct mlx5_vport *vport; | |
1837 | ||
1838 | if (!esw) { | |
1839 | pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n", | |
1840 | vport_num); | |
1841 | return; | |
1842 | } | |
1843 | ||
1844 | vport = &esw->vports[vport_num]; | |
073bb189 SM |
1845 | if (vport->enabled) |
1846 | queue_work(esw->work_queue, &vport->vport_change_handler); | |
073bb189 | 1847 | } |
77256579 SM |
1848 | |
1849 | /* Vport Administration */ | |
1850 | #define ESW_ALLOWED(esw) \ | |
1851 | (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev)) | |
1852 | #define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports) | |
1853 | ||
1854 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, | |
1855 | int vport, u8 mac[ETH_ALEN]) | |
1856 | { | |
f942380c | 1857 | struct mlx5_vport *evport; |
23898c76 NO |
1858 | u64 node_guid; |
1859 | int err = 0; | |
77256579 SM |
1860 | |
1861 | if (!ESW_ALLOWED(esw)) | |
1862 | return -EPERM; | |
ccce1700 | 1863 | if (!LEGAL_VPORT(esw, vport) || is_multicast_ether_addr(mac)) |
77256579 SM |
1864 | return -EINVAL; |
1865 | ||
1ab2068a | 1866 | mutex_lock(&esw->state_lock); |
f942380c MHY |
1867 | evport = &esw->vports[vport]; |
1868 | ||
1ab2068a | 1869 | if (evport->info.spoofchk && !is_valid_ether_addr(mac)) { |
f942380c MHY |
1870 | mlx5_core_warn(esw->dev, |
1871 | "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n", | |
1872 | vport); | |
1ab2068a MHY |
1873 | err = -EPERM; |
1874 | goto unlock; | |
f942380c MHY |
1875 | } |
1876 | ||
77256579 SM |
1877 | err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac); |
1878 | if (err) { | |
1879 | mlx5_core_warn(esw->dev, | |
1880 | "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n", | |
1881 | vport, err); | |
1ab2068a | 1882 | goto unlock; |
77256579 SM |
1883 | } |
1884 | ||
23898c76 NO |
1885 | node_guid_gen_from_mac(&node_guid, mac); |
1886 | err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid); | |
1887 | if (err) | |
1888 | mlx5_core_warn(esw->dev, | |
1889 | "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n", | |
1890 | vport, err); | |
1891 | ||
1ab2068a MHY |
1892 | ether_addr_copy(evport->info.mac, mac); |
1893 | evport->info.node_guid = node_guid; | |
f96750f8 | 1894 | if (evport->enabled && esw->mode == SRIOV_LEGACY) |
f942380c | 1895 | err = esw_vport_ingress_config(esw, evport); |
1ab2068a MHY |
1896 | |
1897 | unlock: | |
f942380c | 1898 | mutex_unlock(&esw->state_lock); |
77256579 SM |
1899 | return err; |
1900 | } | |
1901 | ||
1902 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
1903 | int vport, int link_state) | |
1904 | { | |
1ab2068a MHY |
1905 | struct mlx5_vport *evport; |
1906 | int err = 0; | |
1907 | ||
77256579 SM |
1908 | if (!ESW_ALLOWED(esw)) |
1909 | return -EPERM; | |
1910 | if (!LEGAL_VPORT(esw, vport)) | |
1911 | return -EINVAL; | |
1912 | ||
1ab2068a MHY |
1913 | mutex_lock(&esw->state_lock); |
1914 | evport = &esw->vports[vport]; | |
1915 | ||
1916 | err = mlx5_modify_vport_admin_state(esw->dev, | |
1917 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
1918 | vport, link_state); | |
1919 | if (err) { | |
1920 | mlx5_core_warn(esw->dev, | |
1921 | "Failed to set vport %d link state, err = %d", | |
1922 | vport, err); | |
1923 | goto unlock; | |
1924 | } | |
1925 | ||
1926 | evport->info.link_state = link_state; | |
1927 | ||
1928 | unlock: | |
1929 | mutex_unlock(&esw->state_lock); | |
1930 | return 0; | |
77256579 SM |
1931 | } |
1932 | ||
1933 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, | |
1934 | int vport, struct ifla_vf_info *ivi) | |
1935 | { | |
f942380c | 1936 | struct mlx5_vport *evport; |
9e7ea352 | 1937 | |
77256579 SM |
1938 | if (!ESW_ALLOWED(esw)) |
1939 | return -EPERM; | |
1940 | if (!LEGAL_VPORT(esw, vport)) | |
1941 | return -EINVAL; | |
1942 | ||
f942380c MHY |
1943 | evport = &esw->vports[vport]; |
1944 | ||
77256579 SM |
1945 | memset(ivi, 0, sizeof(*ivi)); |
1946 | ivi->vf = vport - 1; | |
1947 | ||
1ab2068a MHY |
1948 | mutex_lock(&esw->state_lock); |
1949 | ether_addr_copy(ivi->mac, evport->info.mac); | |
1950 | ivi->linkstate = evport->info.link_state; | |
1951 | ivi->vlan = evport->info.vlan; | |
1952 | ivi->qos = evport->info.qos; | |
1953 | ivi->spoofchk = evport->info.spoofchk; | |
1954 | ivi->trusted = evport->info.trusted; | |
bd77bf1c | 1955 | ivi->max_tx_rate = evport->info.max_rate; |
1ab2068a | 1956 | mutex_unlock(&esw->state_lock); |
77256579 SM |
1957 | |
1958 | return 0; | |
1959 | } | |
9e7ea352 | 1960 | |
e33dfe31 OG |
1961 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
1962 | int vport, u16 vlan, u8 qos, u8 set_flags) | |
9e7ea352 | 1963 | { |
dfcb1ed3 MHY |
1964 | struct mlx5_vport *evport; |
1965 | int err = 0; | |
9e7ea352 SM |
1966 | |
1967 | if (!ESW_ALLOWED(esw)) | |
1968 | return -EPERM; | |
1969 | if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7)) | |
1970 | return -EINVAL; | |
1971 | ||
1ab2068a | 1972 | mutex_lock(&esw->state_lock); |
dfcb1ed3 MHY |
1973 | evport = &esw->vports[vport]; |
1974 | ||
e33dfe31 | 1975 | err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set_flags); |
dfcb1ed3 | 1976 | if (err) |
1ab2068a | 1977 | goto unlock; |
dfcb1ed3 | 1978 | |
1ab2068a MHY |
1979 | evport->info.vlan = vlan; |
1980 | evport->info.qos = qos; | |
f96750f8 | 1981 | if (evport->enabled && esw->mode == SRIOV_LEGACY) { |
dfcb1ed3 MHY |
1982 | err = esw_vport_ingress_config(esw, evport); |
1983 | if (err) | |
1ab2068a | 1984 | goto unlock; |
dfcb1ed3 MHY |
1985 | err = esw_vport_egress_config(esw, evport); |
1986 | } | |
1987 | ||
1ab2068a | 1988 | unlock: |
dfcb1ed3 MHY |
1989 | mutex_unlock(&esw->state_lock); |
1990 | return err; | |
9e7ea352 | 1991 | } |
3b751a2a | 1992 | |
e33dfe31 OG |
1993 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
1994 | int vport, u16 vlan, u8 qos) | |
1995 | { | |
1996 | u8 set_flags = 0; | |
1997 | ||
1998 | if (vlan || qos) | |
1999 | set_flags = SET_VLAN_STRIP | SET_VLAN_INSERT; | |
2000 | ||
2001 | return __mlx5_eswitch_set_vport_vlan(esw, vport, vlan, qos, set_flags); | |
2002 | } | |
2003 | ||
f942380c MHY |
2004 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
2005 | int vport, bool spoofchk) | |
2006 | { | |
2007 | struct mlx5_vport *evport; | |
2008 | bool pschk; | |
2009 | int err = 0; | |
2010 | ||
2011 | if (!ESW_ALLOWED(esw)) | |
2012 | return -EPERM; | |
2013 | if (!LEGAL_VPORT(esw, vport)) | |
2014 | return -EINVAL; | |
2015 | ||
f942380c | 2016 | mutex_lock(&esw->state_lock); |
1ab2068a MHY |
2017 | evport = &esw->vports[vport]; |
2018 | pschk = evport->info.spoofchk; | |
2019 | evport->info.spoofchk = spoofchk; | |
2020 | if (evport->enabled && esw->mode == SRIOV_LEGACY) | |
f942380c | 2021 | err = esw_vport_ingress_config(esw, evport); |
1ab2068a MHY |
2022 | if (err) |
2023 | evport->info.spoofchk = pschk; | |
f942380c MHY |
2024 | mutex_unlock(&esw->state_lock); |
2025 | ||
2026 | return err; | |
2027 | } | |
2028 | ||
1edc57e2 MHY |
2029 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
2030 | int vport, bool setting) | |
2031 | { | |
2032 | struct mlx5_vport *evport; | |
2033 | ||
2034 | if (!ESW_ALLOWED(esw)) | |
2035 | return -EPERM; | |
2036 | if (!LEGAL_VPORT(esw, vport)) | |
2037 | return -EINVAL; | |
2038 | ||
1edc57e2 | 2039 | mutex_lock(&esw->state_lock); |
1ab2068a MHY |
2040 | evport = &esw->vports[vport]; |
2041 | evport->info.trusted = setting; | |
1edc57e2 MHY |
2042 | if (evport->enabled) |
2043 | esw_vport_change_handle_locked(evport); | |
2044 | mutex_unlock(&esw->state_lock); | |
2045 | ||
2046 | return 0; | |
2047 | } | |
2048 | ||
bd77bf1c MHY |
2049 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, |
2050 | int vport, u32 max_rate) | |
2051 | { | |
2052 | struct mlx5_vport *evport; | |
2053 | int err = 0; | |
2054 | ||
2055 | if (!ESW_ALLOWED(esw)) | |
2056 | return -EPERM; | |
2057 | if (!LEGAL_VPORT(esw, vport)) | |
2058 | return -EINVAL; | |
2059 | ||
2060 | mutex_lock(&esw->state_lock); | |
2061 | evport = &esw->vports[vport]; | |
2062 | err = esw_vport_qos_config(esw, vport, max_rate); | |
2063 | if (!err) | |
2064 | evport->info.max_rate = max_rate; | |
2065 | ||
2066 | mutex_unlock(&esw->state_lock); | |
2067 | return err; | |
2068 | } | |
2069 | ||
3b751a2a SM |
2070 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
2071 | int vport, | |
2072 | struct ifla_vf_stats *vf_stats) | |
2073 | { | |
2074 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
c4f287c4 | 2075 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; |
3b751a2a SM |
2076 | int err = 0; |
2077 | u32 *out; | |
2078 | ||
2079 | if (!ESW_ALLOWED(esw)) | |
2080 | return -EPERM; | |
2081 | if (!LEGAL_VPORT(esw, vport)) | |
2082 | return -EINVAL; | |
2083 | ||
2084 | out = mlx5_vzalloc(outlen); | |
2085 | if (!out) | |
2086 | return -ENOMEM; | |
2087 | ||
3b751a2a SM |
2088 | MLX5_SET(query_vport_counter_in, in, opcode, |
2089 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
2090 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
2091 | MLX5_SET(query_vport_counter_in, in, vport_number, vport); | |
2092 | if (vport) | |
2093 | MLX5_SET(query_vport_counter_in, in, other_vport, 1); | |
2094 | ||
2095 | memset(out, 0, outlen); | |
2096 | err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen); | |
2097 | if (err) | |
2098 | goto free_out; | |
2099 | ||
2100 | #define MLX5_GET_CTR(p, x) \ | |
2101 | MLX5_GET64(query_vport_counter_out, p, x) | |
2102 | ||
2103 | memset(vf_stats, 0, sizeof(*vf_stats)); | |
2104 | vf_stats->rx_packets = | |
2105 | MLX5_GET_CTR(out, received_eth_unicast.packets) + | |
2106 | MLX5_GET_CTR(out, received_eth_multicast.packets) + | |
2107 | MLX5_GET_CTR(out, received_eth_broadcast.packets); | |
2108 | ||
2109 | vf_stats->rx_bytes = | |
2110 | MLX5_GET_CTR(out, received_eth_unicast.octets) + | |
2111 | MLX5_GET_CTR(out, received_eth_multicast.octets) + | |
2112 | MLX5_GET_CTR(out, received_eth_broadcast.octets); | |
2113 | ||
2114 | vf_stats->tx_packets = | |
2115 | MLX5_GET_CTR(out, transmitted_eth_unicast.packets) + | |
2116 | MLX5_GET_CTR(out, transmitted_eth_multicast.packets) + | |
2117 | MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); | |
2118 | ||
2119 | vf_stats->tx_bytes = | |
2120 | MLX5_GET_CTR(out, transmitted_eth_unicast.octets) + | |
2121 | MLX5_GET_CTR(out, transmitted_eth_multicast.octets) + | |
2122 | MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); | |
2123 | ||
2124 | vf_stats->multicast = | |
2125 | MLX5_GET_CTR(out, received_eth_multicast.packets); | |
2126 | ||
2127 | vf_stats->broadcast = | |
2128 | MLX5_GET_CTR(out, received_eth_broadcast.packets); | |
2129 | ||
2130 | free_out: | |
2131 | kvfree(out); | |
2132 | return err; | |
2133 | } |