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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/mlx5/driver.h> | |
35 | #include <linux/mlx5/mlx5_ifc.h> | |
36 | #include <linux/mlx5/vport.h> | |
81848731 | 37 | #include <linux/mlx5/flow_table.h> |
073bb189 SM |
38 | #include "mlx5_core.h" |
39 | #include "eswitch.h" | |
40 | ||
81848731 SM |
41 | #define UPLINK_VPORT 0xFFFF |
42 | ||
073bb189 SM |
43 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
44 | ||
45 | #define esw_info(dev, format, ...) \ | |
46 | pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
47 | ||
48 | #define esw_warn(dev, format, ...) \ | |
49 | pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
50 | ||
51 | #define esw_debug(dev, format, ...) \ | |
52 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
53 | ||
54 | enum { | |
55 | MLX5_ACTION_NONE = 0, | |
56 | MLX5_ACTION_ADD = 1, | |
57 | MLX5_ACTION_DEL = 2, | |
58 | }; | |
59 | ||
81848731 SM |
60 | /* E-Switch UC L2 table hash node */ |
61 | struct esw_uc_addr { | |
073bb189 | 62 | struct l2addr_node node; |
073bb189 SM |
63 | u32 table_index; |
64 | u32 vport; | |
65 | }; | |
66 | ||
81848731 SM |
67 | /* E-Switch MC FDB table hash node */ |
68 | struct esw_mc_addr { /* SRIOV only */ | |
69 | struct l2addr_node node; | |
70 | struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */ | |
71 | u32 refcnt; | |
72 | }; | |
73 | ||
74 | /* Vport UC/MC hash node */ | |
75 | struct vport_addr { | |
76 | struct l2addr_node node; | |
77 | u8 action; | |
78 | u32 vport; | |
79 | struct mlx5_flow_rule *flow_rule; /* SRIOV only */ | |
073bb189 SM |
80 | }; |
81 | ||
82 | enum { | |
83 | UC_ADDR_CHANGE = BIT(0), | |
84 | MC_ADDR_CHANGE = BIT(1), | |
85 | }; | |
86 | ||
81848731 SM |
87 | /* Vport context events */ |
88 | #define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \ | |
89 | MC_ADDR_CHANGE) | |
90 | ||
91 | static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport, | |
073bb189 SM |
92 | u32 events_mask) |
93 | { | |
94 | int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)]; | |
95 | int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)]; | |
96 | void *nic_vport_ctx; | |
97 | int err; | |
98 | ||
99 | memset(out, 0, sizeof(out)); | |
100 | memset(in, 0, sizeof(in)); | |
101 | ||
102 | MLX5_SET(modify_nic_vport_context_in, in, | |
103 | opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT); | |
104 | MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1); | |
105 | MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport); | |
106 | if (vport) | |
107 | MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1); | |
108 | nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in, | |
109 | in, nic_vport_context); | |
110 | ||
111 | MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1); | |
112 | ||
113 | if (events_mask & UC_ADDR_CHANGE) | |
114 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
115 | event_on_uc_address_change, 1); | |
116 | if (events_mask & MC_ADDR_CHANGE) | |
117 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
118 | event_on_mc_address_change, 1); | |
119 | ||
120 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
121 | if (err) | |
122 | goto ex; | |
123 | err = mlx5_cmd_status_to_err_v2(out); | |
124 | if (err) | |
125 | goto ex; | |
126 | return 0; | |
127 | ex: | |
128 | return err; | |
129 | } | |
130 | ||
9e7ea352 SM |
131 | /* E-Switch vport context HW commands */ |
132 | static int query_esw_vport_context_cmd(struct mlx5_core_dev *mdev, u32 vport, | |
133 | u32 *out, int outlen) | |
134 | { | |
135 | u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)]; | |
136 | ||
137 | memset(in, 0, sizeof(in)); | |
138 | ||
139 | MLX5_SET(query_nic_vport_context_in, in, opcode, | |
140 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT); | |
141 | ||
142 | MLX5_SET(query_esw_vport_context_in, in, vport_number, vport); | |
143 | if (vport) | |
144 | MLX5_SET(query_esw_vport_context_in, in, other_vport, 1); | |
145 | ||
146 | return mlx5_cmd_exec_check_status(mdev, in, sizeof(in), out, outlen); | |
147 | } | |
148 | ||
149 | static int query_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport, | |
150 | u16 *vlan, u8 *qos) | |
151 | { | |
152 | u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)]; | |
153 | int err; | |
154 | bool cvlan_strip; | |
155 | bool cvlan_insert; | |
156 | ||
157 | memset(out, 0, sizeof(out)); | |
158 | ||
159 | *vlan = 0; | |
160 | *qos = 0; | |
161 | ||
162 | if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) || | |
163 | !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist)) | |
164 | return -ENOTSUPP; | |
165 | ||
166 | err = query_esw_vport_context_cmd(dev, vport, out, sizeof(out)); | |
167 | if (err) | |
168 | goto out; | |
169 | ||
170 | cvlan_strip = MLX5_GET(query_esw_vport_context_out, out, | |
171 | esw_vport_context.vport_cvlan_strip); | |
172 | ||
173 | cvlan_insert = MLX5_GET(query_esw_vport_context_out, out, | |
174 | esw_vport_context.vport_cvlan_insert); | |
175 | ||
176 | if (cvlan_strip || cvlan_insert) { | |
177 | *vlan = MLX5_GET(query_esw_vport_context_out, out, | |
178 | esw_vport_context.cvlan_id); | |
179 | *qos = MLX5_GET(query_esw_vport_context_out, out, | |
180 | esw_vport_context.cvlan_pcp); | |
181 | } | |
182 | ||
183 | esw_debug(dev, "Query Vport[%d] cvlan: VLAN %d qos=%d\n", | |
184 | vport, *vlan, *qos); | |
185 | out: | |
186 | return err; | |
187 | } | |
188 | ||
189 | static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport, | |
190 | void *in, int inlen) | |
191 | { | |
192 | u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)]; | |
193 | ||
194 | memset(out, 0, sizeof(out)); | |
195 | ||
196 | MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport); | |
197 | if (vport) | |
198 | MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1); | |
199 | ||
200 | MLX5_SET(modify_esw_vport_context_in, in, opcode, | |
201 | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT); | |
202 | ||
203 | return mlx5_cmd_exec_check_status(dev, in, inlen, | |
204 | out, sizeof(out)); | |
205 | } | |
206 | ||
207 | static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport, | |
208 | u16 vlan, u8 qos, bool set) | |
209 | { | |
210 | u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)]; | |
211 | ||
212 | memset(in, 0, sizeof(in)); | |
213 | ||
214 | if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) || | |
215 | !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist)) | |
216 | return -ENOTSUPP; | |
217 | ||
218 | esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%d\n", | |
219 | vport, vlan, qos, set); | |
220 | ||
221 | if (set) { | |
222 | MLX5_SET(modify_esw_vport_context_in, in, | |
223 | esw_vport_context.vport_cvlan_strip, 1); | |
224 | /* insert only if no vlan in packet */ | |
225 | MLX5_SET(modify_esw_vport_context_in, in, | |
226 | esw_vport_context.vport_cvlan_insert, 1); | |
227 | MLX5_SET(modify_esw_vport_context_in, in, | |
228 | esw_vport_context.cvlan_pcp, qos); | |
229 | MLX5_SET(modify_esw_vport_context_in, in, | |
230 | esw_vport_context.cvlan_id, vlan); | |
231 | } | |
232 | ||
233 | MLX5_SET(modify_esw_vport_context_in, in, | |
234 | field_select.vport_cvlan_strip, 1); | |
235 | MLX5_SET(modify_esw_vport_context_in, in, | |
236 | field_select.vport_cvlan_insert, 1); | |
237 | ||
238 | return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in)); | |
239 | } | |
240 | ||
073bb189 SM |
241 | /* HW L2 Table (MPFS) management */ |
242 | static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index, | |
243 | u8 *mac, u8 vlan_valid, u16 vlan) | |
244 | { | |
245 | u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)]; | |
246 | u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)]; | |
247 | u8 *in_mac_addr; | |
248 | ||
249 | memset(in, 0, sizeof(in)); | |
250 | memset(out, 0, sizeof(out)); | |
251 | ||
252 | MLX5_SET(set_l2_table_entry_in, in, opcode, | |
253 | MLX5_CMD_OP_SET_L2_TABLE_ENTRY); | |
254 | MLX5_SET(set_l2_table_entry_in, in, table_index, index); | |
255 | MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid); | |
256 | MLX5_SET(set_l2_table_entry_in, in, vlan, vlan); | |
257 | ||
258 | in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address); | |
259 | ether_addr_copy(&in_mac_addr[2], mac); | |
260 | ||
261 | return mlx5_cmd_exec_check_status(dev, in, sizeof(in), | |
262 | out, sizeof(out)); | |
263 | } | |
264 | ||
265 | static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index) | |
266 | { | |
267 | u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)]; | |
268 | u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)]; | |
269 | ||
270 | memset(in, 0, sizeof(in)); | |
271 | memset(out, 0, sizeof(out)); | |
272 | ||
273 | MLX5_SET(delete_l2_table_entry_in, in, opcode, | |
274 | MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY); | |
275 | MLX5_SET(delete_l2_table_entry_in, in, table_index, index); | |
276 | return mlx5_cmd_exec_check_status(dev, in, sizeof(in), | |
277 | out, sizeof(out)); | |
278 | } | |
279 | ||
280 | static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix) | |
281 | { | |
282 | int err = 0; | |
283 | ||
284 | *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size); | |
285 | if (*ix >= l2_table->size) | |
286 | err = -ENOSPC; | |
287 | else | |
288 | __set_bit(*ix, l2_table->bitmap); | |
289 | ||
290 | return err; | |
291 | } | |
292 | ||
293 | static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix) | |
294 | { | |
295 | __clear_bit(ix, l2_table->bitmap); | |
296 | } | |
297 | ||
298 | static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac, | |
299 | u8 vlan_valid, u16 vlan, | |
300 | u32 *index) | |
301 | { | |
302 | struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table; | |
303 | int err; | |
304 | ||
305 | err = alloc_l2_table_index(l2_table, index); | |
306 | if (err) | |
307 | return err; | |
308 | ||
309 | err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan); | |
310 | if (err) | |
311 | free_l2_table_index(l2_table, *index); | |
312 | ||
313 | return err; | |
314 | } | |
315 | ||
316 | static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index) | |
317 | { | |
318 | struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table; | |
319 | ||
320 | del_l2_table_entry_cmd(dev, index); | |
321 | free_l2_table_index(l2_table, index); | |
322 | } | |
323 | ||
81848731 SM |
324 | /* E-Switch FDB flow steering */ |
325 | struct dest_node { | |
326 | struct list_head list; | |
327 | struct mlx5_flow_destination dest; | |
328 | }; | |
329 | ||
330 | static int _mlx5_flow_rule_apply(struct mlx5_flow_rule *fr) | |
073bb189 | 331 | { |
81848731 SM |
332 | bool was_valid = fr->valid; |
333 | struct dest_node *dest_n; | |
334 | u32 dest_list_size = 0; | |
335 | void *in_match_value; | |
336 | u32 *flow_context; | |
337 | u32 flow_index; | |
338 | int err; | |
339 | int i; | |
340 | ||
341 | if (list_empty(&fr->dest_list)) { | |
342 | if (fr->valid) | |
343 | mlx5_del_flow_table_entry(fr->ft, fr->fi); | |
344 | fr->valid = false; | |
345 | return 0; | |
346 | } | |
347 | ||
348 | list_for_each_entry(dest_n, &fr->dest_list, list) | |
349 | dest_list_size++; | |
350 | ||
351 | flow_context = mlx5_vzalloc(MLX5_ST_SZ_BYTES(flow_context) + | |
352 | MLX5_ST_SZ_BYTES(dest_format_struct) * | |
353 | dest_list_size); | |
354 | if (!flow_context) | |
355 | return -ENOMEM; | |
356 | ||
357 | MLX5_SET(flow_context, flow_context, flow_tag, fr->flow_tag); | |
358 | MLX5_SET(flow_context, flow_context, action, fr->action); | |
359 | MLX5_SET(flow_context, flow_context, destination_list_size, | |
360 | dest_list_size); | |
361 | ||
362 | i = 0; | |
363 | list_for_each_entry(dest_n, &fr->dest_list, list) { | |
364 | void *dest_addr = MLX5_ADDR_OF(flow_context, flow_context, | |
365 | destination[i++]); | |
366 | ||
367 | MLX5_SET(dest_format_struct, dest_addr, destination_type, | |
368 | dest_n->dest.type); | |
369 | MLX5_SET(dest_format_struct, dest_addr, destination_id, | |
370 | dest_n->dest.vport_num); | |
371 | } | |
372 | ||
373 | in_match_value = MLX5_ADDR_OF(flow_context, flow_context, match_value); | |
374 | memcpy(in_match_value, fr->match_value, MLX5_ST_SZ_BYTES(fte_match_param)); | |
375 | ||
376 | err = mlx5_add_flow_table_entry(fr->ft, fr->match_criteria_enable, | |
377 | fr->match_criteria, flow_context, | |
378 | &flow_index); | |
379 | if (!err) { | |
380 | if (was_valid) | |
381 | mlx5_del_flow_table_entry(fr->ft, fr->fi); | |
382 | fr->fi = flow_index; | |
383 | fr->valid = true; | |
384 | } | |
385 | kfree(flow_context); | |
386 | return err; | |
387 | } | |
388 | ||
389 | static int mlx5_flow_rule_add_dest(struct mlx5_flow_rule *fr, | |
390 | struct mlx5_flow_destination *new_dest) | |
391 | { | |
392 | struct dest_node *dest_n; | |
393 | int err; | |
394 | ||
395 | dest_n = kzalloc(sizeof(*dest_n), GFP_KERNEL); | |
396 | if (!dest_n) | |
397 | return -ENOMEM; | |
398 | ||
399 | memcpy(&dest_n->dest, new_dest, sizeof(dest_n->dest)); | |
400 | mutex_lock(&fr->mutex); | |
401 | list_add(&dest_n->list, &fr->dest_list); | |
402 | err = _mlx5_flow_rule_apply(fr); | |
403 | if (err) { | |
404 | list_del(&dest_n->list); | |
405 | kfree(dest_n); | |
406 | } | |
407 | mutex_unlock(&fr->mutex); | |
408 | return err; | |
409 | } | |
410 | ||
411 | static int mlx5_flow_rule_del_dest(struct mlx5_flow_rule *fr, | |
412 | struct mlx5_flow_destination *dest) | |
413 | { | |
414 | struct dest_node *dest_n; | |
415 | struct dest_node *n; | |
416 | int err; | |
417 | ||
418 | mutex_lock(&fr->mutex); | |
419 | list_for_each_entry_safe(dest_n, n, &fr->dest_list, list) { | |
420 | if (dest->vport_num == dest_n->dest.vport_num) | |
421 | goto found; | |
422 | } | |
423 | mutex_unlock(&fr->mutex); | |
424 | return -ENOENT; | |
425 | ||
426 | found: | |
427 | list_del(&dest_n->list); | |
428 | err = _mlx5_flow_rule_apply(fr); | |
429 | mutex_unlock(&fr->mutex); | |
430 | kfree(dest_n); | |
431 | ||
432 | return err; | |
433 | } | |
434 | ||
435 | static struct mlx5_flow_rule *find_fr(struct mlx5_eswitch *esw, | |
436 | u8 match_criteria_enable, | |
437 | u32 *match_value) | |
438 | { | |
439 | struct hlist_head *hash = esw->mc_table; | |
440 | struct esw_mc_addr *esw_mc; | |
441 | u8 *dmac_v; | |
442 | ||
443 | dmac_v = MLX5_ADDR_OF(fte_match_param, match_value, | |
444 | outer_headers.dmac_47_16); | |
445 | ||
446 | /* UNICAST FULL MATCH */ | |
447 | if (!is_multicast_ether_addr(dmac_v)) | |
448 | return NULL; | |
449 | ||
450 | /* MULTICAST FULL MATCH */ | |
451 | esw_mc = l2addr_hash_find(hash, dmac_v, struct esw_mc_addr); | |
452 | ||
453 | return esw_mc ? esw_mc->uplink_rule : NULL; | |
454 | } | |
455 | ||
456 | static struct mlx5_flow_rule *alloc_fr(void *ft, | |
457 | u8 match_criteria_enable, | |
458 | u32 *match_criteria, | |
459 | u32 *match_value, | |
460 | u32 action, | |
461 | u32 flow_tag) | |
462 | { | |
463 | struct mlx5_flow_rule *fr = kzalloc(sizeof(*fr), GFP_KERNEL); | |
464 | ||
465 | if (!fr) | |
466 | return NULL; | |
467 | ||
468 | fr->match_criteria = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
469 | fr->match_value = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
470 | if (!fr->match_criteria || !fr->match_value) { | |
471 | kfree(fr->match_criteria); | |
472 | kfree(fr->match_value); | |
473 | kfree(fr); | |
474 | return NULL; | |
475 | } | |
476 | ||
477 | memcpy(fr->match_criteria, match_criteria, MLX5_ST_SZ_BYTES(fte_match_param)); | |
478 | memcpy(fr->match_value, match_value, MLX5_ST_SZ_BYTES(fte_match_param)); | |
479 | fr->match_criteria_enable = match_criteria_enable; | |
480 | fr->flow_tag = flow_tag; | |
481 | fr->action = action; | |
482 | ||
483 | mutex_init(&fr->mutex); | |
484 | INIT_LIST_HEAD(&fr->dest_list); | |
485 | atomic_set(&fr->refcount, 0); | |
486 | fr->ft = ft; | |
487 | return fr; | |
488 | } | |
489 | ||
490 | static void deref_fr(struct mlx5_flow_rule *fr) | |
491 | { | |
492 | if (!atomic_dec_and_test(&fr->refcount)) | |
493 | return; | |
494 | ||
495 | kfree(fr->match_criteria); | |
496 | kfree(fr->match_value); | |
497 | kfree(fr); | |
498 | } | |
499 | ||
500 | static struct mlx5_flow_rule * | |
501 | mlx5_add_flow_rule(struct mlx5_eswitch *esw, | |
502 | u8 match_criteria_enable, | |
503 | u32 *match_criteria, | |
504 | u32 *match_value, | |
505 | u32 action, | |
506 | u32 flow_tag, | |
507 | struct mlx5_flow_destination *dest) | |
508 | { | |
509 | struct mlx5_flow_rule *fr; | |
073bb189 SM |
510 | int err; |
511 | ||
81848731 SM |
512 | fr = find_fr(esw, match_criteria_enable, match_value); |
513 | fr = fr ? fr : alloc_fr(esw->fdb_table.fdb, match_criteria_enable, match_criteria, | |
514 | match_value, action, flow_tag); | |
515 | if (!fr) | |
516 | return NULL; | |
517 | ||
518 | atomic_inc(&fr->refcount); | |
519 | ||
520 | err = mlx5_flow_rule_add_dest(fr, dest); | |
521 | if (err) { | |
522 | deref_fr(fr); | |
523 | return NULL; | |
524 | } | |
525 | ||
526 | return fr; | |
527 | } | |
528 | ||
529 | static void mlx5_del_flow_rule(struct mlx5_flow_rule *fr, u32 vport) | |
530 | { | |
531 | struct mlx5_flow_destination dest; | |
532 | ||
533 | dest.vport_num = vport; | |
534 | mlx5_flow_rule_del_dest(fr, &dest); | |
535 | deref_fr(fr); | |
536 | } | |
537 | ||
538 | /* E-Switch FDB */ | |
539 | static struct mlx5_flow_rule * | |
540 | esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport) | |
541 | { | |
542 | int match_header = MLX5_MATCH_OUTER_HEADERS; | |
543 | struct mlx5_flow_destination dest; | |
544 | struct mlx5_flow_rule *flow_rule = NULL; | |
545 | u32 *match_v; | |
546 | u32 *match_c; | |
547 | u8 *dmac_v; | |
548 | u8 *dmac_c; | |
549 | ||
550 | match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
551 | match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
552 | if (!match_v || !match_c) { | |
553 | pr_warn("FDB: Failed to alloc match parameters\n"); | |
554 | goto out; | |
555 | } | |
556 | dmac_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
557 | outer_headers.dmac_47_16); | |
558 | dmac_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
559 | outer_headers.dmac_47_16); | |
560 | ||
561 | ether_addr_copy(dmac_v, mac); | |
562 | /* Match criteria mask */ | |
563 | memset(dmac_c, 0xff, 6); | |
564 | ||
565 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
566 | dest.vport_num = vport; | |
567 | ||
568 | esw_debug(esw->dev, | |
569 | "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n", | |
570 | dmac_v, dmac_c, vport); | |
571 | flow_rule = | |
572 | mlx5_add_flow_rule(esw, | |
573 | match_header, | |
574 | match_c, | |
575 | match_v, | |
576 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST, | |
577 | 0, &dest); | |
578 | if (IS_ERR_OR_NULL(flow_rule)) { | |
579 | pr_warn( | |
580 | "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n", | |
581 | dmac_v, dmac_c, vport, PTR_ERR(flow_rule)); | |
582 | flow_rule = NULL; | |
583 | } | |
584 | out: | |
585 | kfree(match_v); | |
586 | kfree(match_c); | |
587 | return flow_rule; | |
588 | } | |
589 | ||
590 | static int esw_create_fdb_table(struct mlx5_eswitch *esw, int nvports) | |
591 | { | |
592 | struct mlx5_core_dev *dev = esw->dev; | |
593 | struct mlx5_flow_table_group g; | |
594 | struct mlx5_flow_table *fdb; | |
595 | u8 *dmac; | |
596 | ||
597 | esw_debug(dev, "Create FDB log_max_size(%d)\n", | |
598 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); | |
599 | ||
600 | memset(&g, 0, sizeof(g)); | |
601 | /* UC MC Full match rules*/ | |
602 | g.log_sz = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size); | |
603 | g.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS; | |
604 | dmac = MLX5_ADDR_OF(fte_match_param, g.match_criteria, | |
605 | outer_headers.dmac_47_16); | |
606 | /* Match criteria mask */ | |
607 | memset(dmac, 0xff, 6); | |
608 | ||
609 | fdb = mlx5_create_flow_table(dev, 0, | |
610 | MLX5_FLOW_TABLE_TYPE_ESWITCH, | |
611 | 1, &g); | |
612 | if (fdb) | |
613 | esw_debug(dev, "ESW: FDB Table created fdb->id %d\n", mlx5_get_flow_table_id(fdb)); | |
614 | else | |
615 | esw_warn(dev, "ESW: Failed to create FDB Table\n"); | |
616 | ||
617 | esw->fdb_table.fdb = fdb; | |
618 | return fdb ? 0 : -ENOMEM; | |
619 | } | |
620 | ||
621 | static void esw_destroy_fdb_table(struct mlx5_eswitch *esw) | |
622 | { | |
623 | if (!esw->fdb_table.fdb) | |
624 | return; | |
625 | ||
626 | esw_debug(esw->dev, "Destroy FDB Table fdb(%d)\n", | |
627 | mlx5_get_flow_table_id(esw->fdb_table.fdb)); | |
628 | mlx5_destroy_flow_table(esw->fdb_table.fdb); | |
629 | esw->fdb_table.fdb = NULL; | |
630 | } | |
631 | ||
632 | /* E-Switch vport UC/MC lists management */ | |
633 | typedef int (*vport_addr_action)(struct mlx5_eswitch *esw, | |
634 | struct vport_addr *vaddr); | |
635 | ||
636 | static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
637 | { | |
638 | struct hlist_head *hash = esw->l2_table.l2_hash; | |
639 | struct esw_uc_addr *esw_uc; | |
640 | u8 *mac = vaddr->node.addr; | |
641 | u32 vport = vaddr->vport; | |
642 | int err; | |
643 | ||
644 | esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr); | |
645 | if (esw_uc) { | |
073bb189 SM |
646 | esw_warn(esw->dev, |
647 | "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n", | |
81848731 | 648 | mac, vport, esw_uc->vport); |
073bb189 SM |
649 | return -EEXIST; |
650 | } | |
651 | ||
81848731 SM |
652 | esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL); |
653 | if (!esw_uc) | |
073bb189 | 654 | return -ENOMEM; |
81848731 | 655 | esw_uc->vport = vport; |
073bb189 | 656 | |
81848731 | 657 | err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index); |
073bb189 | 658 | if (err) |
81848731 SM |
659 | goto abort; |
660 | ||
661 | if (esw->fdb_table.fdb) /* SRIOV is enabled: Forward UC MAC to vport */ | |
662 | vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport); | |
663 | ||
664 | esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n", | |
665 | vport, mac, esw_uc->table_index, vaddr->flow_rule); | |
666 | return err; | |
667 | abort: | |
668 | l2addr_hash_del(esw_uc); | |
073bb189 SM |
669 | return err; |
670 | } | |
671 | ||
81848731 | 672 | static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) |
073bb189 | 673 | { |
81848731 SM |
674 | struct hlist_head *hash = esw->l2_table.l2_hash; |
675 | struct esw_uc_addr *esw_uc; | |
676 | u8 *mac = vaddr->node.addr; | |
677 | u32 vport = vaddr->vport; | |
678 | ||
679 | esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr); | |
680 | if (!esw_uc || esw_uc->vport != vport) { | |
681 | esw_debug(esw->dev, | |
682 | "MAC(%pM) doesn't belong to vport (%d)\n", | |
683 | mac, vport); | |
684 | return -EINVAL; | |
685 | } | |
686 | esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n", | |
687 | vport, mac, esw_uc->table_index, vaddr->flow_rule); | |
688 | ||
689 | del_l2_table_entry(esw->dev, esw_uc->table_index); | |
690 | ||
691 | if (vaddr->flow_rule) | |
692 | mlx5_del_flow_rule(vaddr->flow_rule, vport); | |
693 | vaddr->flow_rule = NULL; | |
694 | ||
695 | l2addr_hash_del(esw_uc); | |
696 | return 0; | |
697 | } | |
698 | ||
699 | static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
700 | { | |
701 | struct hlist_head *hash = esw->mc_table; | |
702 | struct esw_mc_addr *esw_mc; | |
703 | u8 *mac = vaddr->node.addr; | |
704 | u32 vport = vaddr->vport; | |
705 | ||
706 | if (!esw->fdb_table.fdb) | |
707 | return 0; | |
708 | ||
709 | esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr); | |
710 | if (esw_mc) | |
711 | goto add; | |
712 | ||
713 | esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL); | |
714 | if (!esw_mc) | |
715 | return -ENOMEM; | |
716 | ||
717 | esw_mc->uplink_rule = /* Forward MC MAC to Uplink */ | |
718 | esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT); | |
719 | add: | |
720 | esw_mc->refcnt++; | |
721 | /* Forward MC MAC to vport */ | |
722 | vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport); | |
723 | esw_debug(esw->dev, | |
724 | "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n", | |
725 | vport, mac, vaddr->flow_rule, | |
726 | esw_mc->refcnt, esw_mc->uplink_rule); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
731 | { | |
732 | struct hlist_head *hash = esw->mc_table; | |
733 | struct esw_mc_addr *esw_mc; | |
734 | u8 *mac = vaddr->node.addr; | |
735 | u32 vport = vaddr->vport; | |
073bb189 | 736 | |
81848731 SM |
737 | if (!esw->fdb_table.fdb) |
738 | return 0; | |
739 | ||
740 | esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr); | |
741 | if (!esw_mc) { | |
742 | esw_warn(esw->dev, | |
743 | "Failed to find eswitch MC addr for MAC(%pM) vport(%d)", | |
073bb189 SM |
744 | mac, vport); |
745 | return -EINVAL; | |
746 | } | |
81848731 SM |
747 | esw_debug(esw->dev, |
748 | "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n", | |
749 | vport, mac, vaddr->flow_rule, esw_mc->refcnt, | |
750 | esw_mc->uplink_rule); | |
751 | ||
752 | if (vaddr->flow_rule) | |
753 | mlx5_del_flow_rule(vaddr->flow_rule, vport); | |
754 | vaddr->flow_rule = NULL; | |
755 | ||
756 | if (--esw_mc->refcnt) | |
757 | return 0; | |
073bb189 | 758 | |
81848731 SM |
759 | if (esw_mc->uplink_rule) |
760 | mlx5_del_flow_rule(esw_mc->uplink_rule, UPLINK_VPORT); | |
761 | ||
762 | l2addr_hash_del(esw_mc); | |
073bb189 SM |
763 | return 0; |
764 | } | |
765 | ||
81848731 SM |
766 | /* Apply vport UC/MC list to HW l2 table and FDB table */ |
767 | static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw, | |
768 | u32 vport_num, int list_type) | |
073bb189 SM |
769 | { |
770 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
81848731 SM |
771 | bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC; |
772 | vport_addr_action vport_addr_add; | |
773 | vport_addr_action vport_addr_del; | |
774 | struct vport_addr *addr; | |
073bb189 SM |
775 | struct l2addr_node *node; |
776 | struct hlist_head *hash; | |
777 | struct hlist_node *tmp; | |
778 | int hi; | |
779 | ||
81848731 SM |
780 | vport_addr_add = is_uc ? esw_add_uc_addr : |
781 | esw_add_mc_addr; | |
782 | vport_addr_del = is_uc ? esw_del_uc_addr : | |
783 | esw_del_mc_addr; | |
784 | ||
785 | hash = is_uc ? vport->uc_list : vport->mc_list; | |
073bb189 | 786 | for_each_l2hash_node(node, tmp, hash, hi) { |
81848731 | 787 | addr = container_of(node, struct vport_addr, node); |
073bb189 SM |
788 | switch (addr->action) { |
789 | case MLX5_ACTION_ADD: | |
81848731 | 790 | vport_addr_add(esw, addr); |
073bb189 SM |
791 | addr->action = MLX5_ACTION_NONE; |
792 | break; | |
793 | case MLX5_ACTION_DEL: | |
81848731 | 794 | vport_addr_del(esw, addr); |
073bb189 SM |
795 | l2addr_hash_del(addr); |
796 | break; | |
797 | } | |
798 | } | |
799 | } | |
800 | ||
81848731 SM |
801 | /* Sync vport UC/MC list from vport context */ |
802 | static void esw_update_vport_addr_list(struct mlx5_eswitch *esw, | |
803 | u32 vport_num, int list_type) | |
073bb189 SM |
804 | { |
805 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
81848731 | 806 | bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC; |
073bb189 | 807 | u8 (*mac_list)[ETH_ALEN]; |
81848731 SM |
808 | struct l2addr_node *node; |
809 | struct vport_addr *addr; | |
073bb189 SM |
810 | struct hlist_head *hash; |
811 | struct hlist_node *tmp; | |
812 | int size; | |
813 | int err; | |
814 | int hi; | |
815 | int i; | |
816 | ||
81848731 SM |
817 | size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) : |
818 | MLX5_MAX_MC_PER_VPORT(esw->dev); | |
073bb189 SM |
819 | |
820 | mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL); | |
821 | if (!mac_list) | |
822 | return; | |
823 | ||
81848731 | 824 | hash = is_uc ? vport->uc_list : vport->mc_list; |
073bb189 SM |
825 | |
826 | for_each_l2hash_node(node, tmp, hash, hi) { | |
81848731 | 827 | addr = container_of(node, struct vport_addr, node); |
073bb189 SM |
828 | addr->action = MLX5_ACTION_DEL; |
829 | } | |
830 | ||
81848731 | 831 | err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type, |
073bb189 SM |
832 | mac_list, &size); |
833 | if (err) | |
834 | return; | |
81848731 SM |
835 | esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n", |
836 | vport_num, is_uc ? "UC" : "MC", size); | |
073bb189 SM |
837 | |
838 | for (i = 0; i < size; i++) { | |
81848731 | 839 | if (is_uc && !is_valid_ether_addr(mac_list[i])) |
073bb189 SM |
840 | continue; |
841 | ||
81848731 SM |
842 | if (!is_uc && !is_multicast_ether_addr(mac_list[i])) |
843 | continue; | |
844 | ||
845 | addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr); | |
073bb189 SM |
846 | if (addr) { |
847 | addr->action = MLX5_ACTION_NONE; | |
848 | continue; | |
849 | } | |
850 | ||
81848731 | 851 | addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr, |
073bb189 SM |
852 | GFP_KERNEL); |
853 | if (!addr) { | |
854 | esw_warn(esw->dev, | |
855 | "Failed to add MAC(%pM) to vport[%d] DB\n", | |
856 | mac_list[i], vport_num); | |
857 | continue; | |
858 | } | |
81848731 | 859 | addr->vport = vport_num; |
073bb189 SM |
860 | addr->action = MLX5_ACTION_ADD; |
861 | } | |
862 | kfree(mac_list); | |
863 | } | |
864 | ||
865 | static void esw_vport_change_handler(struct work_struct *work) | |
866 | { | |
867 | struct mlx5_vport *vport = | |
868 | container_of(work, struct mlx5_vport, vport_change_handler); | |
869 | struct mlx5_core_dev *dev = vport->dev; | |
81848731 | 870 | struct mlx5_eswitch *esw = dev->priv.eswitch; |
073bb189 SM |
871 | u8 mac[ETH_ALEN]; |
872 | ||
873 | mlx5_query_nic_vport_mac_address(dev, vport->vport, mac); | |
81848731 SM |
874 | esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n", |
875 | vport->vport, mac); | |
876 | ||
877 | if (vport->enabled_events & UC_ADDR_CHANGE) { | |
878 | esw_update_vport_addr_list(esw, vport->vport, | |
879 | MLX5_NVPRT_LIST_TYPE_UC); | |
880 | esw_apply_vport_addr_list(esw, vport->vport, | |
881 | MLX5_NVPRT_LIST_TYPE_UC); | |
882 | } | |
073bb189 | 883 | |
81848731 SM |
884 | if (vport->enabled_events & MC_ADDR_CHANGE) { |
885 | esw_update_vport_addr_list(esw, vport->vport, | |
886 | MLX5_NVPRT_LIST_TYPE_MC); | |
887 | esw_apply_vport_addr_list(esw, vport->vport, | |
888 | MLX5_NVPRT_LIST_TYPE_MC); | |
889 | } | |
073bb189 | 890 | |
81848731 | 891 | esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport); |
073bb189 SM |
892 | if (vport->enabled) |
893 | arm_vport_context_events_cmd(dev, vport->vport, | |
81848731 | 894 | vport->enabled_events); |
073bb189 SM |
895 | } |
896 | ||
81848731 SM |
897 | static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num, |
898 | int enable_events) | |
073bb189 SM |
899 | { |
900 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
901 | unsigned long flags; | |
902 | ||
81848731 SM |
903 | WARN_ON(vport->enabled); |
904 | ||
905 | esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num); | |
906 | mlx5_modify_vport_admin_state(esw->dev, | |
907 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
908 | vport_num, | |
909 | MLX5_ESW_VPORT_ADMIN_STATE_AUTO); | |
910 | ||
911 | /* Sync with current vport context */ | |
912 | vport->enabled_events = enable_events; | |
913 | esw_vport_change_handler(&vport->vport_change_handler); | |
914 | ||
073bb189 SM |
915 | spin_lock_irqsave(&vport->lock, flags); |
916 | vport->enabled = true; | |
917 | spin_unlock_irqrestore(&vport->lock, flags); | |
918 | ||
81848731 SM |
919 | arm_vport_context_events_cmd(esw->dev, vport_num, enable_events); |
920 | ||
921 | esw->enabled_vports++; | |
922 | esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num); | |
923 | } | |
924 | ||
925 | static void esw_cleanup_vport(struct mlx5_eswitch *esw, u16 vport_num) | |
926 | { | |
927 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
928 | struct l2addr_node *node; | |
929 | struct vport_addr *addr; | |
930 | struct hlist_node *tmp; | |
931 | int hi; | |
932 | ||
933 | for_each_l2hash_node(node, tmp, vport->uc_list, hi) { | |
934 | addr = container_of(node, struct vport_addr, node); | |
935 | addr->action = MLX5_ACTION_DEL; | |
936 | } | |
937 | esw_apply_vport_addr_list(esw, vport_num, MLX5_NVPRT_LIST_TYPE_UC); | |
938 | ||
939 | for_each_l2hash_node(node, tmp, vport->mc_list, hi) { | |
940 | addr = container_of(node, struct vport_addr, node); | |
941 | addr->action = MLX5_ACTION_DEL; | |
942 | } | |
943 | esw_apply_vport_addr_list(esw, vport_num, MLX5_NVPRT_LIST_TYPE_MC); | |
073bb189 SM |
944 | } |
945 | ||
946 | static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num) | |
947 | { | |
948 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
949 | unsigned long flags; | |
950 | ||
951 | if (!vport->enabled) | |
952 | return; | |
953 | ||
81848731 | 954 | esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num); |
073bb189 SM |
955 | /* Mark this vport as disabled to discard new events */ |
956 | spin_lock_irqsave(&vport->lock, flags); | |
957 | vport->enabled = false; | |
81848731 | 958 | vport->enabled_events = 0; |
073bb189 SM |
959 | spin_unlock_irqrestore(&vport->lock, flags); |
960 | ||
81848731 SM |
961 | mlx5_modify_vport_admin_state(esw->dev, |
962 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
963 | vport_num, | |
964 | MLX5_ESW_VPORT_ADMIN_STATE_DOWN); | |
073bb189 SM |
965 | /* Wait for current already scheduled events to complete */ |
966 | flush_workqueue(esw->work_queue); | |
073bb189 SM |
967 | /* Disable events from this vport */ |
968 | arm_vport_context_events_cmd(esw->dev, vport->vport, 0); | |
81848731 SM |
969 | /* We don't assume VFs will cleanup after themselves */ |
970 | esw_cleanup_vport(esw, vport_num); | |
971 | esw->enabled_vports--; | |
073bb189 SM |
972 | } |
973 | ||
974 | /* Public E-Switch API */ | |
81848731 SM |
975 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs) |
976 | { | |
977 | int err; | |
978 | int i; | |
979 | ||
980 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
981 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
982 | return 0; | |
983 | ||
984 | if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) || | |
985 | !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) { | |
986 | esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n"); | |
987 | return -ENOTSUPP; | |
988 | } | |
989 | ||
990 | esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d)\n", nvfs); | |
991 | ||
992 | esw_disable_vport(esw, 0); | |
993 | ||
994 | err = esw_create_fdb_table(esw, nvfs + 1); | |
995 | if (err) | |
996 | goto abort; | |
997 | ||
998 | for (i = 0; i <= nvfs; i++) | |
999 | esw_enable_vport(esw, i, SRIOV_VPORT_EVENTS); | |
1000 | ||
1001 | esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n", | |
1002 | esw->enabled_vports); | |
1003 | return 0; | |
1004 | ||
1005 | abort: | |
1006 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
1007 | return err; | |
1008 | } | |
1009 | ||
1010 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) | |
1011 | { | |
1012 | int i; | |
1013 | ||
1014 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1015 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1016 | return; | |
1017 | ||
1018 | esw_info(esw->dev, "disable SRIOV: active vports(%d)\n", | |
1019 | esw->enabled_vports); | |
1020 | ||
1021 | for (i = 0; i < esw->total_vports; i++) | |
1022 | esw_disable_vport(esw, i); | |
1023 | ||
1024 | esw_destroy_fdb_table(esw); | |
1025 | ||
1026 | /* VPORT 0 (PF) must be enabled back with non-sriov configuration */ | |
1027 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
1028 | } | |
1029 | ||
073bb189 SM |
1030 | int mlx5_eswitch_init(struct mlx5_core_dev *dev) |
1031 | { | |
1032 | int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table); | |
1033 | int total_vports = 1 + pci_sriov_get_totalvfs(dev->pdev); | |
1034 | struct mlx5_eswitch *esw; | |
1035 | int vport_num; | |
1036 | int err; | |
1037 | ||
1038 | if (!MLX5_CAP_GEN(dev, vport_group_manager) || | |
1039 | MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1040 | return 0; | |
1041 | ||
1042 | esw_info(dev, | |
1043 | "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n", | |
1044 | total_vports, l2_table_size, | |
1045 | MLX5_MAX_UC_PER_VPORT(dev), | |
1046 | MLX5_MAX_MC_PER_VPORT(dev)); | |
1047 | ||
1048 | esw = kzalloc(sizeof(*esw), GFP_KERNEL); | |
1049 | if (!esw) | |
1050 | return -ENOMEM; | |
1051 | ||
1052 | esw->dev = dev; | |
1053 | ||
1054 | esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size), | |
1055 | sizeof(uintptr_t), GFP_KERNEL); | |
1056 | if (!esw->l2_table.bitmap) { | |
1057 | err = -ENOMEM; | |
1058 | goto abort; | |
1059 | } | |
1060 | esw->l2_table.size = l2_table_size; | |
1061 | ||
1062 | esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq"); | |
1063 | if (!esw->work_queue) { | |
1064 | err = -ENOMEM; | |
1065 | goto abort; | |
1066 | } | |
1067 | ||
1068 | esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport), | |
1069 | GFP_KERNEL); | |
1070 | if (!esw->vports) { | |
1071 | err = -ENOMEM; | |
1072 | goto abort; | |
1073 | } | |
1074 | ||
073bb189 SM |
1075 | for (vport_num = 0; vport_num < total_vports; vport_num++) { |
1076 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
1077 | ||
1078 | vport->vport = vport_num; | |
1079 | vport->dev = dev; | |
1080 | INIT_WORK(&vport->vport_change_handler, | |
1081 | esw_vport_change_handler); | |
1082 | spin_lock_init(&vport->lock); | |
1083 | } | |
1084 | ||
81848731 SM |
1085 | esw->total_vports = total_vports; |
1086 | esw->enabled_vports = 0; | |
073bb189 | 1087 | |
81848731 SM |
1088 | dev->priv.eswitch = esw; |
1089 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
073bb189 SM |
1090 | /* VF Vports will be enabled when SRIOV is enabled */ |
1091 | return 0; | |
1092 | abort: | |
1093 | if (esw->work_queue) | |
1094 | destroy_workqueue(esw->work_queue); | |
1095 | kfree(esw->l2_table.bitmap); | |
1096 | kfree(esw->vports); | |
1097 | kfree(esw); | |
1098 | return err; | |
1099 | } | |
1100 | ||
1101 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) | |
1102 | { | |
1103 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
1104 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
1105 | return; | |
1106 | ||
1107 | esw_info(esw->dev, "cleanup\n"); | |
1108 | esw_disable_vport(esw, 0); | |
1109 | ||
1110 | esw->dev->priv.eswitch = NULL; | |
1111 | destroy_workqueue(esw->work_queue); | |
1112 | kfree(esw->l2_table.bitmap); | |
1113 | kfree(esw->vports); | |
1114 | kfree(esw); | |
1115 | } | |
1116 | ||
1117 | void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) | |
1118 | { | |
1119 | struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change; | |
1120 | u16 vport_num = be16_to_cpu(vc_eqe->vport_num); | |
1121 | struct mlx5_vport *vport; | |
1122 | ||
1123 | if (!esw) { | |
1124 | pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n", | |
1125 | vport_num); | |
1126 | return; | |
1127 | } | |
1128 | ||
1129 | vport = &esw->vports[vport_num]; | |
1130 | spin_lock(&vport->lock); | |
1131 | if (vport->enabled) | |
1132 | queue_work(esw->work_queue, &vport->vport_change_handler); | |
1133 | spin_unlock(&vport->lock); | |
1134 | } | |
77256579 SM |
1135 | |
1136 | /* Vport Administration */ | |
1137 | #define ESW_ALLOWED(esw) \ | |
1138 | (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev)) | |
1139 | #define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports) | |
1140 | ||
1141 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, | |
1142 | int vport, u8 mac[ETH_ALEN]) | |
1143 | { | |
1144 | int err = 0; | |
1145 | ||
1146 | if (!ESW_ALLOWED(esw)) | |
1147 | return -EPERM; | |
1148 | if (!LEGAL_VPORT(esw, vport)) | |
1149 | return -EINVAL; | |
1150 | ||
1151 | err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac); | |
1152 | if (err) { | |
1153 | mlx5_core_warn(esw->dev, | |
1154 | "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n", | |
1155 | vport, err); | |
1156 | return err; | |
1157 | } | |
1158 | ||
1159 | return err; | |
1160 | } | |
1161 | ||
1162 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
1163 | int vport, int link_state) | |
1164 | { | |
1165 | if (!ESW_ALLOWED(esw)) | |
1166 | return -EPERM; | |
1167 | if (!LEGAL_VPORT(esw, vport)) | |
1168 | return -EINVAL; | |
1169 | ||
1170 | return mlx5_modify_vport_admin_state(esw->dev, | |
1171 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
1172 | vport, link_state); | |
1173 | } | |
1174 | ||
1175 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, | |
1176 | int vport, struct ifla_vf_info *ivi) | |
1177 | { | |
9e7ea352 SM |
1178 | u16 vlan; |
1179 | u8 qos; | |
1180 | ||
77256579 SM |
1181 | if (!ESW_ALLOWED(esw)) |
1182 | return -EPERM; | |
1183 | if (!LEGAL_VPORT(esw, vport)) | |
1184 | return -EINVAL; | |
1185 | ||
1186 | memset(ivi, 0, sizeof(*ivi)); | |
1187 | ivi->vf = vport - 1; | |
1188 | ||
1189 | mlx5_query_nic_vport_mac_address(esw->dev, vport, ivi->mac); | |
1190 | ivi->linkstate = mlx5_query_vport_admin_state(esw->dev, | |
1191 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
1192 | vport); | |
9e7ea352 SM |
1193 | query_esw_vport_cvlan(esw->dev, vport, &vlan, &qos); |
1194 | ivi->vlan = vlan; | |
1195 | ivi->qos = qos; | |
77256579 SM |
1196 | ivi->spoofchk = 0; |
1197 | ||
1198 | return 0; | |
1199 | } | |
9e7ea352 SM |
1200 | |
1201 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
1202 | int vport, u16 vlan, u8 qos) | |
1203 | { | |
1204 | int set = 0; | |
1205 | ||
1206 | if (!ESW_ALLOWED(esw)) | |
1207 | return -EPERM; | |
1208 | if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7)) | |
1209 | return -EINVAL; | |
1210 | ||
1211 | if (vlan || qos) | |
1212 | set = 1; | |
1213 | ||
1214 | return modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set); | |
1215 | } |