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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.c
CommitLineData
073bb189
SM		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
86d722ad 37#include <linux/mlx5/fs.h>
073bb189
SM		 38#include "mlx5_core.h"
39#include "eswitch.h"
40
81848731
SM		 41#define UPLINK_VPORT 0xFFFF
42
073bb189
SM		 43enum {
44 MLX5_ACTION_NONE = 0,
45 MLX5_ACTION_ADD = 1,
46 MLX5_ACTION_DEL = 2,
47};
48
81848731
SM		 49/* E-Switch UC L2 table hash node */
50struct esw_uc_addr {
073bb189 51 struct l2addr_node node;
073bb189
SM		 52 u32 table_index;
53 u32 vport;
54};
55
81848731
SM		 56/* Vport UC/MC hash node */
57struct vport_addr {
58 struct l2addr_node node;
59 u8 action;
60 u32 vport;
74491de9 61 struct mlx5_flow_handle *flow_rule; /* SRIOV only */
a35f71f2
MHY		 62 /* A flag indicating that mac was added due to mc promiscuous vport */
63 bool mc_promisc;
073bb189
SM		 64};
65
66enum {
67 UC_ADDR_CHANGE = BIT(0),
68 MC_ADDR_CHANGE = BIT(1),
a35f71f2 69 PROMISC_CHANGE = BIT(3),
073bb189
SM		 70};
71
81848731
SM		 72/* Vport context events */
73#define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
a35f71f2
MHY		 74 MC_ADDR_CHANGE | \
75 PROMISC_CHANGE)
81848731
SM		 76
77static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
073bb189
SM		 78 u32 events_mask)
79{
c4f287c4
SM		 80 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
81 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
073bb189 82 void *nic_vport_ctx;
073bb189
SM		 83
84 MLX5_SET(modify_nic_vport_context_in, in,
85 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
86 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
87 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
88 if (vport)
89 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
90 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
91 in, nic_vport_context);
92
93 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
94
95 if (events_mask & UC_ADDR_CHANGE)
96 MLX5_SET(nic_vport_context, nic_vport_ctx,
97 event_on_uc_address_change, 1);
98 if (events_mask & MC_ADDR_CHANGE)
99 MLX5_SET(nic_vport_context, nic_vport_ctx,
100 event_on_mc_address_change, 1);
a35f71f2
MHY		 101 if (events_mask & PROMISC_CHANGE)
102 MLX5_SET(nic_vport_context, nic_vport_ctx,
103 event_on_promisc_change, 1);
073bb189 104
c4f287c4 105 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 106}
107
9e7ea352 108/* E-Switch vport context HW commands */
9e7ea352
SM		 109static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
110 void *in, int inlen)
111{
c4f287c4 112 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
9e7ea352 113
c4f287c4
SM		 114 MLX5_SET(modify_esw_vport_context_in, in, opcode,
115 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
9e7ea352
SM		 116 MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
117 if (vport)
118 MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
c4f287c4 119 return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
9e7ea352
SM		 120}
121
122static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
e33dfe31 123 u16 vlan, u8 qos, u8 set_flags)
9e7ea352 124{
c4f287c4 125 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0};
9e7ea352
SM		 126
127 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
128 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
9eb78923 129 return -EOPNOTSUPP;
9e7ea352 130
e33dfe31
OG		 131 esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%x\n",
132 vport, vlan, qos, set_flags);
133
134 if (set_flags & SET_VLAN_STRIP)
9e7ea352
SM		 135 MLX5_SET(modify_esw_vport_context_in, in,
136 esw_vport_context.vport_cvlan_strip, 1);
e33dfe31
OG		 137
138 if (set_flags & SET_VLAN_INSERT) {
9e7ea352
SM		 139 /* insert only if no vlan in packet */
140 MLX5_SET(modify_esw_vport_context_in, in,
141 esw_vport_context.vport_cvlan_insert, 1);
e33dfe31 142
9e7ea352
SM		 143 MLX5_SET(modify_esw_vport_context_in, in,
144 esw_vport_context.cvlan_pcp, qos);
145 MLX5_SET(modify_esw_vport_context_in, in,
146 esw_vport_context.cvlan_id, vlan);
147 }
148
149 MLX5_SET(modify_esw_vport_context_in, in,
150 field_select.vport_cvlan_strip, 1);
151 MLX5_SET(modify_esw_vport_context_in, in,
152 field_select.vport_cvlan_insert, 1);
153
154 return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
155}
156
073bb189
SM		 157/* HW L2 Table (MPFS) management */
158static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
159 u8 *mac, u8 vlan_valid, u16 vlan)
160{
c4f287c4
SM		 161 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0};
162 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0};
073bb189
SM		 163 u8 *in_mac_addr;
164
073bb189
SM		 165 MLX5_SET(set_l2_table_entry_in, in, opcode,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
167 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
168 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
169 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
170
171 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
172 ether_addr_copy(&in_mac_addr[2], mac);
173
c4f287c4 174 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 175}
176
177static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
178{
c4f287c4
SM		 179 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0};
180 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0};
073bb189
SM		 181
182 MLX5_SET(delete_l2_table_entry_in, in, opcode,
183 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
184 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
c4f287c4 185 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 186}
187
188static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
189{
190 int err = 0;
191
192 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
193 if (*ix >= l2_table->size)
194 err = -ENOSPC;
195 else
196 __set_bit(*ix, l2_table->bitmap);
197
198 return err;
199}
200
201static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
202{
203 __clear_bit(ix, l2_table->bitmap);
204}
205
206static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
207 u8 vlan_valid, u16 vlan,
208 u32 *index)
209{
210 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
211 int err;
212
213 err = alloc_l2_table_index(l2_table, index);
214 if (err)
215 return err;
216
217 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
218 if (err)
219 free_l2_table_index(l2_table, *index);
220
221 return err;
222}
223
224static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
225{
226 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
227
228 del_l2_table_entry_cmd(dev, index);
229 free_l2_table_index(l2_table, index);
230}
231
81848731 232/* E-Switch FDB */
74491de9 233static struct mlx5_flow_handle *
a35f71f2 234__esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
78a9199b 235 u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
81848731 236{
78a9199b
MHY		 237 int match_header = (is_zero_ether_addr(mac_c) ? 0 :
238 MLX5_MATCH_OUTER_HEADERS);
74491de9 239 struct mlx5_flow_handle *flow_rule = NULL;
66958ed9 240 struct mlx5_flow_act flow_act = {0};
78a9199b 241 struct mlx5_flow_destination dest;
c5bb1730 242 struct mlx5_flow_spec *spec;
a35f71f2
MHY		 243 void *mv_misc = NULL;
244 void *mc_misc = NULL;
78a9199b
MHY		 245 u8 *dmac_v = NULL;
246 u8 *dmac_c = NULL;
81848731 247
a35f71f2
MHY		 248 if (rx_rule)
249 match_header |= MLX5_MATCH_MISC_PARAMETERS;
c5bb1730 250
1b9a07ee
LR		 251 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
252 if (!spec)
c5bb1730 253 return NULL;
1b9a07ee 254
c5bb1730 255 dmac_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
81848731 256 outer_headers.dmac_47_16);
c5bb1730 257 dmac_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
81848731
SM		 258 outer_headers.dmac_47_16);
259
a35f71f2 260 if (match_header & MLX5_MATCH_OUTER_HEADERS) {
78a9199b
MHY		 261 ether_addr_copy(dmac_v, mac_v);
262 ether_addr_copy(dmac_c, mac_c);
263 }
81848731 264
a35f71f2 265 if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
c5bb1730
MG		 266 mv_misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
267 misc_parameters);
268 mc_misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
269 misc_parameters);
a35f71f2
MHY		 270 MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
271 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
272 }
273
81848731
SM		 274 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
275 dest.vport_num = vport;
276
277 esw_debug(esw->dev,
278 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
279 dmac_v, dmac_c, vport);
c5bb1730 280 spec->match_criteria_enable = match_header;
66958ed9 281 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
81848731 282 flow_rule =
74491de9 283 mlx5_add_flow_rules(esw->fdb_table.fdb, spec,
66958ed9 284 &flow_act, &dest, 1);
3f42ac66 285 if (IS_ERR(flow_rule)) {
2974ab6e
SM		 286 esw_warn(esw->dev,
287 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
81848731
SM		 288 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
289 flow_rule = NULL;
290 }
c5bb1730
MG		 291
292 kvfree(spec);
81848731
SM		 293 return flow_rule;
294}
295
74491de9 296static struct mlx5_flow_handle *
78a9199b
MHY		 297esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
298{
299 u8 mac_c[ETH_ALEN];
300
301 eth_broadcast_addr(mac_c);
a35f71f2
MHY		 302 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
303}
304
74491de9 305static struct mlx5_flow_handle *
a35f71f2
MHY		 306esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
307{
308 u8 mac_c[ETH_ALEN];
309 u8 mac_v[ETH_ALEN];
310
311 eth_zero_addr(mac_c);
312 eth_zero_addr(mac_v);
313 mac_c[0] = 0x01;
314 mac_v[0] = 0x01;
315 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
316}
317
74491de9 318static struct mlx5_flow_handle *
a35f71f2
MHY		 319esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
320{
321 u8 mac_c[ETH_ALEN];
322 u8 mac_v[ETH_ALEN];
323
324 eth_zero_addr(mac_c);
325 eth_zero_addr(mac_v);
326 return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
78a9199b
MHY		 327}
328
6ab36e35 329static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports)
81848731 330{
86d722ad 331 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
b3ba5149 332 struct mlx5_flow_table_attr ft_attr = {};
81848731 333 struct mlx5_core_dev *dev = esw->dev;
86d722ad 334 struct mlx5_flow_namespace *root_ns;
81848731 335 struct mlx5_flow_table *fdb;
86d722ad
MG		 336 struct mlx5_flow_group *g;
337 void *match_criteria;
338 int table_size;
339 u32 *flow_group_in;
81848731 340 u8 *dmac;
86d722ad 341 int err = 0;
81848731
SM		 342
343 esw_debug(dev, "Create FDB log_max_size(%d)\n",
344 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
345
86d722ad
MG		 346 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
347 if (!root_ns) {
348 esw_warn(dev, "Failed to get FDB flow namespace\n");
eff596da 349 return -EOPNOTSUPP;
86d722ad 350 }
81848731 351
1b9a07ee 352 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
86d722ad
MG		 353 if (!flow_group_in)
354 return -ENOMEM;
86d722ad
MG		 355
356 table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
b3ba5149
ES		 357
358 ft_attr.max_fte = table_size;
359 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
3f42ac66 360 if (IS_ERR(fdb)) {
86d722ad
MG		 361 err = PTR_ERR(fdb);
362 esw_warn(dev, "Failed to create FDB Table err %d\n", err);
363 goto out;
364 }
78a9199b 365 esw->fdb_table.fdb = fdb;
81848731 366
78a9199b 367 /* Addresses group : Full match unicast/multicast addresses */
86d722ad
MG		 368 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
369 MLX5_MATCH_OUTER_HEADERS);
370 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
371 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
372 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
78a9199b
MHY		 373 /* Preserve 2 entries for allmulti and promisc rules*/
374 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
86d722ad 375 eth_broadcast_addr(dmac);
86d722ad 376 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 377 if (IS_ERR(g)) {
86d722ad
MG		 378 err = PTR_ERR(g);
379 esw_warn(dev, "Failed to create flow group err(%d)\n", err);
380 goto out;
381 }
6ab36e35 382 esw->fdb_table.legacy.addr_grp = g;
78a9199b
MHY		 383
384 /* Allmulti group : One rule that forwards any mcast traffic */
385 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
386 MLX5_MATCH_OUTER_HEADERS);
387 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
388 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
389 eth_zero_addr(dmac);
390 dmac[0] = 0x01;
391 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 392 if (IS_ERR(g)) {
78a9199b
MHY		 393 err = PTR_ERR(g);
394 esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
395 goto out;
396 }
6ab36e35 397 esw->fdb_table.legacy.allmulti_grp = g;
78a9199b
MHY		 398
399 /* Promiscuous group :
400 * One rule that forward all unmatched traffic from previous groups
401 */
402 eth_zero_addr(dmac);
403 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
404 MLX5_MATCH_MISC_PARAMETERS);
405 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
406 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
407 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
408 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 409 if (IS_ERR(g)) {
78a9199b
MHY		 410 err = PTR_ERR(g);
411 esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
412 goto out;
413 }
6ab36e35 414 esw->fdb_table.legacy.promisc_grp = g;
78a9199b 415
86d722ad 416out:
78a9199b 417 if (err) {
6ab36e35
OG		 418 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) {
419 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
420 esw->fdb_table.legacy.allmulti_grp = NULL;
78a9199b 421 }
6ab36e35
OG		 422 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) {
423 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
424 esw->fdb_table.legacy.addr_grp = NULL;
78a9199b
MHY		 425 }
426 if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
427 mlx5_destroy_flow_table(esw->fdb_table.fdb);
428 esw->fdb_table.fdb = NULL;
429 }
430 }
431
3fe3d819 432 kvfree(flow_group_in);
86d722ad 433 return err;
81848731
SM		 434}
435
6ab36e35 436static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw)
81848731
SM		 437{
438 if (!esw->fdb_table.fdb)
439 return;
440
86d722ad 441 esw_debug(esw->dev, "Destroy FDB Table\n");
6ab36e35
OG		 442 mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp);
443 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
444 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
81848731
SM		 445 mlx5_destroy_flow_table(esw->fdb_table.fdb);
446 esw->fdb_table.fdb = NULL;
6ab36e35
OG		 447 esw->fdb_table.legacy.addr_grp = NULL;
448 esw->fdb_table.legacy.allmulti_grp = NULL;
449 esw->fdb_table.legacy.promisc_grp = NULL;
81848731
SM		 450}
451
452/* E-Switch vport UC/MC lists management */
453typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
454 struct vport_addr *vaddr);
455
456static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
457{
458 struct hlist_head *hash = esw->l2_table.l2_hash;
459 struct esw_uc_addr *esw_uc;
460 u8 *mac = vaddr->node.addr;
461 u32 vport = vaddr->vport;
462 int err;
463
464 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
465 if (esw_uc) {
073bb189
SM		 466 esw_warn(esw->dev,
467 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
81848731 468 mac, vport, esw_uc->vport);
073bb189
SM		 469 return -EEXIST;
470 }
471
81848731
SM		 472 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
473 if (!esw_uc)
073bb189 474 return -ENOMEM;
81848731 475 esw_uc->vport = vport;
073bb189 476
81848731 477 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
073bb189 478 if (err)
81848731
SM		 479 goto abort;
480
69697b6e
OG		 481 /* SRIOV is enabled: Forward UC MAC to vport */
482 if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY)
81848731
SM		 483 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
484
485 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
486 vport, mac, esw_uc->table_index, vaddr->flow_rule);
487 return err;
488abort:
489 l2addr_hash_del(esw_uc);
073bb189
SM		 490 return err;
491}
492
81848731 493static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
073bb189 494{
81848731
SM		 495 struct hlist_head *hash = esw->l2_table.l2_hash;
496 struct esw_uc_addr *esw_uc;
497 u8 *mac = vaddr->node.addr;
498 u32 vport = vaddr->vport;
499
500 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
501 if (!esw_uc || esw_uc->vport != vport) {
502 esw_debug(esw->dev,
503 "MAC(%pM) doesn't belong to vport (%d)\n",
504 mac, vport);
505 return -EINVAL;
506 }
507 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
508 vport, mac, esw_uc->table_index, vaddr->flow_rule);
509
510 del_l2_table_entry(esw->dev, esw_uc->table_index);
511
512 if (vaddr->flow_rule)
74491de9 513 mlx5_del_flow_rules(vaddr->flow_rule);
81848731
SM		 514 vaddr->flow_rule = NULL;
515
516 l2addr_hash_del(esw_uc);
517 return 0;
518}
519
a35f71f2
MHY		 520static void update_allmulti_vports(struct mlx5_eswitch *esw,
521 struct vport_addr *vaddr,
522 struct esw_mc_addr *esw_mc)
523{
524 u8 *mac = vaddr->node.addr;
525 u32 vport_idx = 0;
526
527 for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
528 struct mlx5_vport *vport = &esw->vports[vport_idx];
529 struct hlist_head *vport_hash = vport->mc_list;
530 struct vport_addr *iter_vaddr =
531 l2addr_hash_find(vport_hash,
532 mac,
533 struct vport_addr);
534 if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
535 vaddr->vport == vport_idx)
536 continue;
537 switch (vaddr->action) {
538 case MLX5_ACTION_ADD:
539 if (iter_vaddr)
540 continue;
541 iter_vaddr = l2addr_hash_add(vport_hash, mac,
542 struct vport_addr,
543 GFP_KERNEL);
544 if (!iter_vaddr) {
545 esw_warn(esw->dev,
546 "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
547 mac, vport_idx);
548 continue;
549 }
550 iter_vaddr->vport = vport_idx;
551 iter_vaddr->flow_rule =
552 esw_fdb_set_vport_rule(esw,
553 mac,
554 vport_idx);
62e3c24a 555 iter_vaddr->mc_promisc = true;
a35f71f2
MHY		 556 break;
557 case MLX5_ACTION_DEL:
558 if (!iter_vaddr)
559 continue;
74491de9 560 mlx5_del_flow_rules(iter_vaddr->flow_rule);
a35f71f2
MHY		 561 l2addr_hash_del(iter_vaddr);
562 break;
563 }
564 }
565}
566
81848731
SM		 567static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
568{
569 struct hlist_head *hash = esw->mc_table;
570 struct esw_mc_addr *esw_mc;
571 u8 *mac = vaddr->node.addr;
572 u32 vport = vaddr->vport;
573
574 if (!esw->fdb_table.fdb)
575 return 0;
576
577 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
578 if (esw_mc)
579 goto add;
580
581 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
582 if (!esw_mc)
583 return -ENOMEM;
584
585 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
586 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
a35f71f2
MHY		 587
588 /* Add this multicast mac to all the mc promiscuous vports */
589 update_allmulti_vports(esw, vaddr, esw_mc);
590
81848731 591add:
a35f71f2
MHY		 592 /* If the multicast mac is added as a result of mc promiscuous vport,
593 * don't increment the multicast ref count
594 */
595 if (!vaddr->mc_promisc)
596 esw_mc->refcnt++;
597
81848731
SM		 598 /* Forward MC MAC to vport */
599 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
600 esw_debug(esw->dev,
601 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
602 vport, mac, vaddr->flow_rule,
603 esw_mc->refcnt, esw_mc->uplink_rule);
604 return 0;
605}
606
607static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
608{
609 struct hlist_head *hash = esw->mc_table;
610 struct esw_mc_addr *esw_mc;
611 u8 *mac = vaddr->node.addr;
612 u32 vport = vaddr->vport;
073bb189 613
81848731
SM		 614 if (!esw->fdb_table.fdb)
615 return 0;
616
617 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
618 if (!esw_mc) {
619 esw_warn(esw->dev,
620 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
073bb189
SM		 621 mac, vport);
622 return -EINVAL;
623 }
81848731
SM		 624 esw_debug(esw->dev,
625 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
626 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
627 esw_mc->uplink_rule);
628
629 if (vaddr->flow_rule)
74491de9 630 mlx5_del_flow_rules(vaddr->flow_rule);
81848731
SM		 631 vaddr->flow_rule = NULL;
632
a35f71f2
MHY		 633 /* If the multicast mac is added as a result of mc promiscuous vport,
634 * don't decrement the multicast ref count.
635 */
636 if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
81848731 637 return 0;
073bb189 638
a35f71f2
MHY		 639 /* Remove this multicast mac from all the mc promiscuous vports */
640 update_allmulti_vports(esw, vaddr, esw_mc);
641
81848731 642 if (esw_mc->uplink_rule)
74491de9 643 mlx5_del_flow_rules(esw_mc->uplink_rule);
81848731
SM		 644
645 l2addr_hash_del(esw_mc);
073bb189
SM		 646 return 0;
647}
648
81848731
SM		 649/* Apply vport UC/MC list to HW l2 table and FDB table */
650static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
651 u32 vport_num, int list_type)
073bb189
SM		 652{
653 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731
SM		 654 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
655 vport_addr_action vport_addr_add;
656 vport_addr_action vport_addr_del;
657 struct vport_addr *addr;
073bb189
SM		 658 struct l2addr_node *node;
659 struct hlist_head *hash;
660 struct hlist_node *tmp;
661 int hi;
662
81848731
SM		 663 vport_addr_add = is_uc ? esw_add_uc_addr :
664 esw_add_mc_addr;
665 vport_addr_del = is_uc ? esw_del_uc_addr :
666 esw_del_mc_addr;
667
668 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189 669 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 670 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 671 switch (addr->action) {
672 case MLX5_ACTION_ADD:
81848731 673 vport_addr_add(esw, addr);
073bb189
SM		 674 addr->action = MLX5_ACTION_NONE;
675 break;
676 case MLX5_ACTION_DEL:
81848731 677 vport_addr_del(esw, addr);
073bb189
SM		 678 l2addr_hash_del(addr);
679 break;
680 }
681 }
682}
683
81848731
SM		 684/* Sync vport UC/MC list from vport context */
685static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
686 u32 vport_num, int list_type)
073bb189
SM		 687{
688 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731 689 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
073bb189 690 u8 (*mac_list)[ETH_ALEN];
81848731
SM		 691 struct l2addr_node *node;
692 struct vport_addr *addr;
073bb189
SM		 693 struct hlist_head *hash;
694 struct hlist_node *tmp;
695 int size;
696 int err;
697 int hi;
698 int i;
699
81848731
SM		 700 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
701 MLX5_MAX_MC_PER_VPORT(esw->dev);
073bb189
SM		 702
703 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
704 if (!mac_list)
705 return;
706
81848731 707 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189
SM		 708
709 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 710 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 711 addr->action = MLX5_ACTION_DEL;
712 }
713
586cfa7f
MHY		 714 if (!vport->enabled)
715 goto out;
716
81848731 717 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
073bb189
SM		 718 mac_list, &size);
719 if (err)
761e205b 720 goto out;
81848731
SM		 721 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
722 vport_num, is_uc ? "UC" : "MC", size);
073bb189
SM		 723
724 for (i = 0; i < size; i++) {
81848731 725 if (is_uc && !is_valid_ether_addr(mac_list[i]))
073bb189
SM		 726 continue;
727
81848731
SM		 728 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
729 continue;
730
731 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
073bb189
SM		 732 if (addr) {
733 addr->action = MLX5_ACTION_NONE;
a35f71f2
MHY		 734 /* If this mac was previously added because of allmulti
735 * promiscuous rx mode, its now converted to be original
736 * vport mac.
737 */
738 if (addr->mc_promisc) {
739 struct esw_mc_addr *esw_mc =
740 l2addr_hash_find(esw->mc_table,
741 mac_list[i],
742 struct esw_mc_addr);
743 if (!esw_mc) {
744 esw_warn(esw->dev,
745 "Failed to MAC(%pM) in mcast DB\n",
746 mac_list[i]);
747 continue;
748 }
749 esw_mc->refcnt++;
750 addr->mc_promisc = false;
751 }
073bb189
SM		 752 continue;
753 }
754
81848731 755 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
073bb189
SM		 756 GFP_KERNEL);
757 if (!addr) {
758 esw_warn(esw->dev,
759 "Failed to add MAC(%pM) to vport[%d] DB\n",
760 mac_list[i], vport_num);
761 continue;
762 }
81848731 763 addr->vport = vport_num;
073bb189
SM		 764 addr->action = MLX5_ACTION_ADD;
765 }
761e205b 766out:
073bb189
SM		 767 kfree(mac_list);
768}
769
a35f71f2
MHY		 770/* Sync vport UC/MC list from vport context
771 * Must be called after esw_update_vport_addr_list
772 */
773static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
774{
775 struct mlx5_vport *vport = &esw->vports[vport_num];
776 struct l2addr_node *node;
777 struct vport_addr *addr;
778 struct hlist_head *hash;
779 struct hlist_node *tmp;
780 int hi;
781
782 hash = vport->mc_list;
783
784 for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
785 u8 *mac = node->addr;
786
787 addr = l2addr_hash_find(hash, mac, struct vport_addr);
788 if (addr) {
789 if (addr->action == MLX5_ACTION_DEL)
790 addr->action = MLX5_ACTION_NONE;
791 continue;
792 }
793 addr = l2addr_hash_add(hash, mac, struct vport_addr,
794 GFP_KERNEL);
795 if (!addr) {
796 esw_warn(esw->dev,
797 "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
798 mac, vport_num);
799 continue;
800 }
801 addr->vport = vport_num;
802 addr->action = MLX5_ACTION_ADD;
803 addr->mc_promisc = true;
804 }
805}
806
807/* Apply vport rx mode to HW FDB table */
808static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
809 bool promisc, bool mc_promisc)
810{
0a0ab1d2 811 struct esw_mc_addr *allmulti_addr = &esw->mc_promisc;
a35f71f2
MHY		 812 struct mlx5_vport *vport = &esw->vports[vport_num];
813
814 if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
815 goto promisc;
816
817 if (mc_promisc) {
818 vport->allmulti_rule =
819 esw_fdb_set_vport_allmulti_rule(esw, vport_num);
820 if (!allmulti_addr->uplink_rule)
821 allmulti_addr->uplink_rule =
822 esw_fdb_set_vport_allmulti_rule(esw,
823 UPLINK_VPORT);
824 allmulti_addr->refcnt++;
825 } else if (vport->allmulti_rule) {
74491de9 826 mlx5_del_flow_rules(vport->allmulti_rule);
a35f71f2
MHY		 827 vport->allmulti_rule = NULL;
828
829 if (--allmulti_addr->refcnt > 0)
830 goto promisc;
831
832 if (allmulti_addr->uplink_rule)
74491de9 833 mlx5_del_flow_rules(allmulti_addr->uplink_rule);
a35f71f2
MHY		 834 allmulti_addr->uplink_rule = NULL;
835 }
836
837promisc:
838 if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
839 return;
840
841 if (promisc) {
842 vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
843 vport_num);
844 } else if (vport->promisc_rule) {
74491de9 845 mlx5_del_flow_rules(vport->promisc_rule);
a35f71f2
MHY		 846 vport->promisc_rule = NULL;
847 }
848}
849
850/* Sync vport rx mode from vport context */
851static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
852{
853 struct mlx5_vport *vport = &esw->vports[vport_num];
854 int promisc_all = 0;
855 int promisc_uc = 0;
856 int promisc_mc = 0;
857 int err;
858
859 err = mlx5_query_nic_vport_promisc(esw->dev,
860 vport_num,
861 &promisc_uc,
862 &promisc_mc,
863 &promisc_all);
864 if (err)
865 return;
866 esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
867 vport_num, promisc_all, promisc_mc);
868
1ab2068a 869 if (!vport->info.trusted || !vport->enabled) {
a35f71f2
MHY		 870 promisc_uc = 0;
871 promisc_mc = 0;
872 promisc_all = 0;
873 }
874
875 esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
876 (promisc_all || promisc_mc));
877}
878
1edc57e2 879static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
073bb189 880{
073bb189 881 struct mlx5_core_dev *dev = vport->dev;
81848731 882 struct mlx5_eswitch *esw = dev->priv.eswitch;
073bb189
SM		 883 u8 mac[ETH_ALEN];
884
885 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
81848731
SM		 886 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
887 vport->vport, mac);
888
889 if (vport->enabled_events & UC_ADDR_CHANGE) {
890 esw_update_vport_addr_list(esw, vport->vport,
891 MLX5_NVPRT_LIST_TYPE_UC);
892 esw_apply_vport_addr_list(esw, vport->vport,
893 MLX5_NVPRT_LIST_TYPE_UC);
894 }
073bb189 895
81848731
SM		 896 if (vport->enabled_events & MC_ADDR_CHANGE) {
897 esw_update_vport_addr_list(esw, vport->vport,
898 MLX5_NVPRT_LIST_TYPE_MC);
a35f71f2
MHY		 899 }
900
901 if (vport->enabled_events & PROMISC_CHANGE) {
902 esw_update_vport_rx_mode(esw, vport->vport);
903 if (!IS_ERR_OR_NULL(vport->allmulti_rule))
904 esw_update_vport_mc_promisc(esw, vport->vport);
905 }
906
907 if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
81848731
SM		 908 esw_apply_vport_addr_list(esw, vport->vport,
909 MLX5_NVPRT_LIST_TYPE_MC);
910 }
073bb189 911
81848731 912 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
073bb189
SM		 913 if (vport->enabled)
914 arm_vport_context_events_cmd(dev, vport->vport,
81848731 915 vport->enabled_events);
073bb189
SM		 916}
917
1edc57e2
MHY		 918static void esw_vport_change_handler(struct work_struct *work)
919{
920 struct mlx5_vport *vport =
921 container_of(work, struct mlx5_vport, vport_change_handler);
922 struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
923
924 mutex_lock(&esw->state_lock);
925 esw_vport_change_handle_locked(vport);
926 mutex_unlock(&esw->state_lock);
927}
928
247f139c
MHY		 929static int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
930 struct mlx5_vport *vport)
5742df0f
MHY		 931{
932 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
933 struct mlx5_flow_group *vlan_grp = NULL;
934 struct mlx5_flow_group *drop_grp = NULL;
935 struct mlx5_core_dev *dev = esw->dev;
936 struct mlx5_flow_namespace *root_ns;
937 struct mlx5_flow_table *acl;
938 void *match_criteria;
939 u32 *flow_group_in;
940 /* The egress acl table contains 2 rules:
941 * 1)Allow traffic with vlan_tag=vst_vlan_id
942 * 2)Drop all other traffic.
943 */
944 int table_size = 2;
945 int err = 0;
946
247f139c
MHY		 947 if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support))
948 return -EOPNOTSUPP;
949
950 if (!IS_ERR_OR_NULL(vport->egress.acl))
951 return 0;
5742df0f
MHY		 952
953 esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
954 vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
955
956 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
957 if (!root_ns) {
958 esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
eff596da 959 return -EOPNOTSUPP;
5742df0f
MHY		 960 }
961
1b9a07ee 962 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
5742df0f 963 if (!flow_group_in)
247f139c 964 return -ENOMEM;
5742df0f
MHY		 965
966 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 967 if (IS_ERR(acl)) {
5742df0f
MHY		 968 err = PTR_ERR(acl);
969 esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
970 vport->vport, err);
971 goto out;
972 }
973
974 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
975 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
10543365 976 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);
5742df0f
MHY		 977 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
978 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
979 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
980
981 vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 982 if (IS_ERR(vlan_grp)) {
5742df0f
MHY		 983 err = PTR_ERR(vlan_grp);
984 esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
985 vport->vport, err);
986 goto out;
987 }
988
989 memset(flow_group_in, 0, inlen);
990 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
991 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
992 drop_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 993 if (IS_ERR(drop_grp)) {
5742df0f
MHY		 994 err = PTR_ERR(drop_grp);
995 esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
996 vport->vport, err);
997 goto out;
998 }
999
1000 vport->egress.acl = acl;
1001 vport->egress.drop_grp = drop_grp;
1002 vport->egress.allowed_vlans_grp = vlan_grp;
1003out:
3fe3d819 1004 kvfree(flow_group_in);
5742df0f
MHY		 1005 if (err && !IS_ERR_OR_NULL(vlan_grp))
1006 mlx5_destroy_flow_group(vlan_grp);
1007 if (err && !IS_ERR_OR_NULL(acl))
1008 mlx5_destroy_flow_table(acl);
247f139c 1009 return err;
5742df0f
MHY		 1010}
1011
dfcb1ed3
MHY		 1012static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
1013 struct mlx5_vport *vport)
1014{
1015 if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
74491de9 1016 mlx5_del_flow_rules(vport->egress.allowed_vlan);
dfcb1ed3
MHY		 1017
1018 if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
74491de9 1019 mlx5_del_flow_rules(vport->egress.drop_rule);
dfcb1ed3
MHY		 1020
1021 vport->egress.allowed_vlan = NULL;
1022 vport->egress.drop_rule = NULL;
1023}
1024
5742df0f
MHY		 1025static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
1026 struct mlx5_vport *vport)
1027{
1028 if (IS_ERR_OR_NULL(vport->egress.acl))
1029 return;
1030
1031 esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
1032
dfcb1ed3 1033 esw_vport_cleanup_egress_rules(esw, vport);
5742df0f
MHY		 1034 mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
1035 mlx5_destroy_flow_group(vport->egress.drop_grp);
1036 mlx5_destroy_flow_table(vport->egress.acl);
1037 vport->egress.allowed_vlans_grp = NULL;
1038 vport->egress.drop_grp = NULL;
1039 vport->egress.acl = NULL;
1040}
1041
247f139c
MHY		 1042static int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
1043 struct mlx5_vport *vport)
5742df0f
MHY		 1044{
1045 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1046 struct mlx5_core_dev *dev = esw->dev;
1047 struct mlx5_flow_namespace *root_ns;
1048 struct mlx5_flow_table *acl;
1049 struct mlx5_flow_group *g;
1050 void *match_criteria;
1051 u32 *flow_group_in;
1052 /* The ingress acl table contains 4 groups
1053 * (2 active rules at the same time -
1054 * 1 allow rule from one of the first 3 groups.
1055 * 1 drop rule from the last group):
1056 * 1)Allow untagged traffic with smac=original mac.
1057 * 2)Allow untagged traffic.
1058 * 3)Allow traffic with smac=original mac.
1059 * 4)Drop all other traffic.
1060 */
1061 int table_size = 4;
1062 int err = 0;
1063
247f139c
MHY		 1064 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support))
1065 return -EOPNOTSUPP;
1066
1067 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1068 return 0;
5742df0f
MHY		 1069
1070 esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
1071 vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
1072
1073 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
1074 if (!root_ns) {
1075 esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
eff596da 1076 return -EOPNOTSUPP;
5742df0f
MHY		 1077 }
1078
1b9a07ee 1079 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
5742df0f 1080 if (!flow_group_in)
247f139c 1081 return -ENOMEM;
5742df0f
MHY		 1082
1083 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1084 if (IS_ERR(acl)) {
5742df0f
MHY		 1085 err = PTR_ERR(acl);
1086 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
1087 vport->vport, err);
1088 goto out;
1089 }
1090 vport->ingress.acl = acl;
1091
1092 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1093
1094 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
10543365 1095 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);
5742df0f
MHY		 1096 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1097 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1098 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1099 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1100
1101 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1102 if (IS_ERR(g)) {
5742df0f
MHY		 1103 err = PTR_ERR(g);
1104 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
1105 vport->vport, err);
1106 goto out;
1107 }
1108 vport->ingress.allow_untagged_spoofchk_grp = g;
1109
1110 memset(flow_group_in, 0, inlen);
1111 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
10543365 1112 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);
5742df0f
MHY		 1113 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1114 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1115
1116 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1117 if (IS_ERR(g)) {
5742df0f
MHY		 1118 err = PTR_ERR(g);
1119 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
1120 vport->vport, err);
1121 goto out;
1122 }
1123 vport->ingress.allow_untagged_only_grp = g;
1124
1125 memset(flow_group_in, 0, inlen);
1126 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1127 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1128 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1129 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
1130 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
1131
1132 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1133 if (IS_ERR(g)) {
5742df0f
MHY		 1134 err = PTR_ERR(g);
1135 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
1136 vport->vport, err);
1137 goto out;
1138 }
1139 vport->ingress.allow_spoofchk_only_grp = g;
1140
1141 memset(flow_group_in, 0, inlen);
1142 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
1143 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
1144
1145 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1146 if (IS_ERR(g)) {
5742df0f
MHY		 1147 err = PTR_ERR(g);
1148 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
1149 vport->vport, err);
1150 goto out;
1151 }
1152 vport->ingress.drop_grp = g;
1153
1154out:
1155 if (err) {
1156 if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
1157 mlx5_destroy_flow_group(
1158 vport->ingress.allow_spoofchk_only_grp);
1159 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
1160 mlx5_destroy_flow_group(
1161 vport->ingress.allow_untagged_only_grp);
1162 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
1163 mlx5_destroy_flow_group(
1164 vport->ingress.allow_untagged_spoofchk_grp);
1165 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1166 mlx5_destroy_flow_table(vport->ingress.acl);
1167 }
1168
3fe3d819 1169 kvfree(flow_group_in);
247f139c 1170 return err;
5742df0f
MHY		 1171}
1172
dfcb1ed3
MHY		 1173static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
1174 struct mlx5_vport *vport)
1175{
1176 if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
74491de9 1177 mlx5_del_flow_rules(vport->ingress.drop_rule);
f942380c
MHY		 1178
1179 if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
74491de9 1180 mlx5_del_flow_rules(vport->ingress.allow_rule);
f942380c 1181
dfcb1ed3 1182 vport->ingress.drop_rule = NULL;
f942380c 1183 vport->ingress.allow_rule = NULL;
dfcb1ed3
MHY		 1184}
1185
5742df0f
MHY		 1186static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
1187 struct mlx5_vport *vport)
1188{
1189 if (IS_ERR_OR_NULL(vport->ingress.acl))
1190 return;
1191
1192 esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
1193
dfcb1ed3 1194 esw_vport_cleanup_ingress_rules(esw, vport);
5742df0f
MHY		 1195 mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
1196 mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
1197 mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
1198 mlx5_destroy_flow_group(vport->ingress.drop_grp);
1199 mlx5_destroy_flow_table(vport->ingress.acl);
1200 vport->ingress.acl = NULL;
1201 vport->ingress.drop_grp = NULL;
1202 vport->ingress.allow_spoofchk_only_grp = NULL;
1203 vport->ingress.allow_untagged_only_grp = NULL;
1204 vport->ingress.allow_untagged_spoofchk_grp = NULL;
1205}
1206
dfcb1ed3
MHY		 1207static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1208 struct mlx5_vport *vport)
1209{
66958ed9 1210 struct mlx5_flow_act flow_act = {0};
c5bb1730 1211 struct mlx5_flow_spec *spec;
dfcb1ed3 1212 int err = 0;
f942380c 1213 u8 *smac_v;
dfcb1ed3 1214
1ab2068a
MHY		 1215 if (vport->info.spoofchk && !is_valid_ether_addr(vport->info.mac)) {
1216 mlx5_core_warn(esw->dev,
1217 "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
1218 vport->vport);
1219 return -EPERM;
f942380c
MHY		 1220 }
1221
dfcb1ed3
MHY		 1222 esw_vport_cleanup_ingress_rules(esw, vport);
1223
1ab2068a 1224 if (!vport->info.vlan && !vport->info.qos && !vport->info.spoofchk) {
01f51f22 1225 esw_vport_disable_ingress_acl(esw, vport);
dfcb1ed3 1226 return 0;
01f51f22
MHY		 1227 }
1228
247f139c
MHY		 1229 err = esw_vport_enable_ingress_acl(esw, vport);
1230 if (err) {
1231 mlx5_core_warn(esw->dev,
1232 "failed to enable ingress acl (%d) on vport[%d]\n",
1233 err, vport->vport);
1234 return err;
1235 }
dfcb1ed3
MHY		 1236
1237 esw_debug(esw->dev,
1238 "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
1ab2068a 1239 vport->vport, vport->info.vlan, vport->info.qos);
dfcb1ed3 1240
1b9a07ee 1241 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1242 if (!spec) {
dfcb1ed3 1243 err = -ENOMEM;
dfcb1ed3
MHY		 1244 goto out;
1245 }
dfcb1ed3 1246
1ab2068a 1247 if (vport->info.vlan || vport->info.qos)
10543365 1248 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
f942380c 1249
1ab2068a 1250 if (vport->info.spoofchk) {
c5bb1730
MG		 1251 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16);
1252 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_15_0);
f942380c 1253 smac_v = MLX5_ADDR_OF(fte_match_param,
c5bb1730 1254 spec->match_value,
f942380c 1255 outer_headers.smac_47_16);
1ab2068a 1256 ether_addr_copy(smac_v, vport->info.mac);
f942380c
MHY		 1257 }
1258
c5bb1730 1259 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
66958ed9 1260 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_ALLOW;
f942380c 1261 vport->ingress.allow_rule =
74491de9 1262 mlx5_add_flow_rules(vport->ingress.acl, spec,
66958ed9 1263 &flow_act, NULL, 0);
3f42ac66 1264 if (IS_ERR(vport->ingress.allow_rule)) {
f942380c 1265 err = PTR_ERR(vport->ingress.allow_rule);
2974ab6e
SM		 1266 esw_warn(esw->dev,
1267 "vport[%d] configure ingress allow rule, err(%d)\n",
1268 vport->vport, err);
f942380c
MHY		 1269 vport->ingress.allow_rule = NULL;
1270 goto out;
1271 }
1272
c5bb1730 1273 memset(spec, 0, sizeof(*spec));
66958ed9 1274 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
f942380c 1275 vport->ingress.drop_rule =
74491de9 1276 mlx5_add_flow_rules(vport->ingress.acl, spec,
66958ed9 1277 &flow_act, NULL, 0);
3f42ac66 1278 if (IS_ERR(vport->ingress.drop_rule)) {
dfcb1ed3 1279 err = PTR_ERR(vport->ingress.drop_rule);
2974ab6e
SM		 1280 esw_warn(esw->dev,
1281 "vport[%d] configure ingress drop rule, err(%d)\n",
1282 vport->vport, err);
dfcb1ed3 1283 vport->ingress.drop_rule = NULL;
f942380c 1284 goto out;
dfcb1ed3 1285 }
f942380c 1286
dfcb1ed3 1287out:
f942380c
MHY		 1288 if (err)
1289 esw_vport_cleanup_ingress_rules(esw, vport);
c5bb1730 1290 kvfree(spec);
dfcb1ed3
MHY		 1291 return err;
1292}
1293
1294static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1295 struct mlx5_vport *vport)
1296{
66958ed9 1297 struct mlx5_flow_act flow_act = {0};
c5bb1730 1298 struct mlx5_flow_spec *spec;
dfcb1ed3
MHY		 1299 int err = 0;
1300
dfcb1ed3
MHY		 1301 esw_vport_cleanup_egress_rules(esw, vport);
1302
1ab2068a 1303 if (!vport->info.vlan && !vport->info.qos) {
01f51f22 1304 esw_vport_disable_egress_acl(esw, vport);
dfcb1ed3 1305 return 0;
01f51f22
MHY		 1306 }
1307
247f139c
MHY		 1308 err = esw_vport_enable_egress_acl(esw, vport);
1309 if (err) {
1310 mlx5_core_warn(esw->dev,
1311 "failed to enable egress acl (%d) on vport[%d]\n",
1312 err, vport->vport);
1313 return err;
1314 }
dfcb1ed3
MHY		 1315
1316 esw_debug(esw->dev,
1317 "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
1ab2068a 1318 vport->vport, vport->info.vlan, vport->info.qos);
dfcb1ed3 1319
1b9a07ee 1320 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1321 if (!spec) {
dfcb1ed3 1322 err = -ENOMEM;
dfcb1ed3
MHY		 1323 goto out;
1324 }
1325
1326 /* Allowed vlan rule */
10543365
MHY		 1327 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1328 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag);
c5bb1730 1329 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1ab2068a 1330 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->info.vlan);
dfcb1ed3 1331
c5bb1730 1332 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
66958ed9 1333 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_ALLOW;
dfcb1ed3 1334 vport->egress.allowed_vlan =
74491de9 1335 mlx5_add_flow_rules(vport->egress.acl, spec,
66958ed9 1336 &flow_act, NULL, 0);
3f42ac66 1337 if (IS_ERR(vport->egress.allowed_vlan)) {
dfcb1ed3 1338 err = PTR_ERR(vport->egress.allowed_vlan);
2974ab6e
SM		 1339 esw_warn(esw->dev,
1340 "vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
1341 vport->vport, err);
dfcb1ed3
MHY		 1342 vport->egress.allowed_vlan = NULL;
1343 goto out;
1344 }
1345
1346 /* Drop others rule (star rule) */
c5bb1730 1347 memset(spec, 0, sizeof(*spec));
66958ed9 1348 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
dfcb1ed3 1349 vport->egress.drop_rule =
74491de9 1350 mlx5_add_flow_rules(vport->egress.acl, spec,
66958ed9 1351 &flow_act, NULL, 0);
3f42ac66 1352 if (IS_ERR(vport->egress.drop_rule)) {
dfcb1ed3 1353 err = PTR_ERR(vport->egress.drop_rule);
2974ab6e
SM		 1354 esw_warn(esw->dev,
1355 "vport[%d] configure egress drop rule failed, err(%d)\n",
1356 vport->vport, err);
dfcb1ed3
MHY		 1357 vport->egress.drop_rule = NULL;
1358 }
1359out:
c5bb1730 1360 kvfree(spec);
dfcb1ed3
MHY		 1361 return err;
1362}
1363
1bd27b11
MHY		 1364/* Vport QoS management */
1365static int esw_create_tsar(struct mlx5_eswitch *esw)
1366{
1367 u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
1368 struct mlx5_core_dev *dev = esw->dev;
1369 int err;
1370
1371 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
1372 return 0;
1373
1374 if (esw->qos.enabled)
1375 return -EEXIST;
1376
1377 err = mlx5_create_scheduling_element_cmd(dev,
1378 SCHEDULING_HIERARCHY_E_SWITCH,
1379 &tsar_ctx,
1380 &esw->qos.root_tsar_id);
1381 if (err) {
1382 esw_warn(esw->dev, "E-Switch create TSAR failed (%d)\n", err);
1383 return err;
1384 }
1385
1386 esw->qos.enabled = true;
1387 return 0;
1388}
1389
1390static void esw_destroy_tsar(struct mlx5_eswitch *esw)
1391{
1392 int err;
1393
1394 if (!esw->qos.enabled)
1395 return;
1396
1397 err = mlx5_destroy_scheduling_element_cmd(esw->dev,
1398 SCHEDULING_HIERARCHY_E_SWITCH,
1399 esw->qos.root_tsar_id);
1400 if (err)
1401 esw_warn(esw->dev, "E-Switch destroy TSAR failed (%d)\n", err);
1402
1403 esw->qos.enabled = false;
1404}
1405
1406static int esw_vport_enable_qos(struct mlx5_eswitch *esw, int vport_num,
c9497c98 1407 u32 initial_max_rate, u32 initial_bw_share)
1bd27b11
MHY		 1408{
1409 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
1410 struct mlx5_vport *vport = &esw->vports[vport_num];
1411 struct mlx5_core_dev *dev = esw->dev;
1412 void *vport_elem;
1413 int err = 0;
1414
1415 if (!esw->qos.enabled || !MLX5_CAP_GEN(dev, qos) ||
1416 !MLX5_CAP_QOS(dev, esw_scheduling))
1417 return 0;
1418
1419 if (vport->qos.enabled)
1420 return -EEXIST;
1421
1422 MLX5_SET(scheduling_context, &sched_ctx, element_type,
1423 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT);
1424 vport_elem = MLX5_ADDR_OF(scheduling_context, &sched_ctx,
1425 element_attributes);
1426 MLX5_SET(vport_element, vport_elem, vport_number, vport_num);
1427 MLX5_SET(scheduling_context, &sched_ctx, parent_element_id,
1428 esw->qos.root_tsar_id);
1429 MLX5_SET(scheduling_context, &sched_ctx, max_average_bw,
1430 initial_max_rate);
c9497c98 1431 MLX5_SET(scheduling_context, &sched_ctx, bw_share, initial_bw_share);
1bd27b11
MHY		 1432
1433 err = mlx5_create_scheduling_element_cmd(dev,
1434 SCHEDULING_HIERARCHY_E_SWITCH,
1435 &sched_ctx,
1436 &vport->qos.esw_tsar_ix);
1437 if (err) {
1438 esw_warn(esw->dev, "E-Switch create TSAR vport element failed (vport=%d,err=%d)\n",
1439 vport_num, err);
1440 return err;
1441 }
1442
1443 vport->qos.enabled = true;
1444 return 0;
1445}
1446
1447static void esw_vport_disable_qos(struct mlx5_eswitch *esw, int vport_num)
1448{
1449 struct mlx5_vport *vport = &esw->vports[vport_num];
1450 int err = 0;
1451
1452 if (!vport->qos.enabled)
1453 return;
1454
1455 err = mlx5_destroy_scheduling_element_cmd(esw->dev,
1456 SCHEDULING_HIERARCHY_E_SWITCH,
1457 vport->qos.esw_tsar_ix);
1458 if (err)
1459 esw_warn(esw->dev, "E-Switch destroy TSAR vport element failed (vport=%d,err=%d)\n",
1460 vport_num, err);
1461
1462 vport->qos.enabled = false;
1463}
1464
bd77bf1c 1465static int esw_vport_qos_config(struct mlx5_eswitch *esw, int vport_num,
c9497c98 1466 u32 max_rate, u32 bw_share)
bd77bf1c
MHY		 1467{
1468 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
1469 struct mlx5_vport *vport = &esw->vports[vport_num];
1470 struct mlx5_core_dev *dev = esw->dev;
1471 void *vport_elem;
1472 u32 bitmask = 0;
1473 int err = 0;
1474
1475 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
1476 return -EOPNOTSUPP;
1477
1478 if (!vport->qos.enabled)
1479 return -EIO;
1480
1481 MLX5_SET(scheduling_context, &sched_ctx, element_type,
1482 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT);
1483 vport_elem = MLX5_ADDR_OF(scheduling_context, &sched_ctx,
1484 element_attributes);
1485 MLX5_SET(vport_element, vport_elem, vport_number, vport_num);
1486 MLX5_SET(scheduling_context, &sched_ctx, parent_element_id,
1487 esw->qos.root_tsar_id);
1488 MLX5_SET(scheduling_context, &sched_ctx, max_average_bw,
1489 max_rate);
c9497c98 1490 MLX5_SET(scheduling_context, &sched_ctx, bw_share, bw_share);
bd77bf1c 1491 bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW;
c9497c98 1492 bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE;
bd77bf1c
MHY		 1493
1494 err = mlx5_modify_scheduling_element_cmd(dev,
1495 SCHEDULING_HIERARCHY_E_SWITCH,
1496 &sched_ctx,
1497 vport->qos.esw_tsar_ix,
1498 bitmask);
1499 if (err) {
1500 esw_warn(esw->dev, "E-Switch modify TSAR vport element failed (vport=%d,err=%d)\n",
1501 vport_num, err);
1502 return err;
1503 }
1504
1505 return 0;
1506}
1507
1ab2068a
MHY		 1508static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
1509{
1510 ((u8 *)node_guid)[7] = mac[0];
1511 ((u8 *)node_guid)[6] = mac[1];
1512 ((u8 *)node_guid)[5] = mac[2];
1513 ((u8 *)node_guid)[4] = 0xff;
1514 ((u8 *)node_guid)[3] = 0xfe;
1515 ((u8 *)node_guid)[2] = mac[3];
1516 ((u8 *)node_guid)[1] = mac[4];
1517 ((u8 *)node_guid)[0] = mac[5];
1518}
1519
1520static void esw_apply_vport_conf(struct mlx5_eswitch *esw,
1521 struct mlx5_vport *vport)
1522{
1523 int vport_num = vport->vport;
1524
1525 if (!vport_num)
1526 return;
1527
1528 mlx5_modify_vport_admin_state(esw->dev,
1529 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1530 vport_num,
1531 vport->info.link_state);
1532 mlx5_modify_nic_vport_mac_address(esw->dev, vport_num, vport->info.mac);
1533 mlx5_modify_nic_vport_node_guid(esw->dev, vport_num, vport->info.node_guid);
1534 modify_esw_vport_cvlan(esw->dev, vport_num, vport->info.vlan, vport->info.qos,
1535 (vport->info.vlan || vport->info.qos));
1536
1537 /* Only legacy mode needs ACLs */
1538 if (esw->mode == SRIOV_LEGACY) {
1539 esw_vport_ingress_config(esw, vport);
1540 esw_vport_egress_config(esw, vport);
1541 }
1542}
1bd27b11 1543
81848731
SM		 1544static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
1545 int enable_events)
073bb189
SM		 1546{
1547 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189 1548
dfcb1ed3 1549 mutex_lock(&esw->state_lock);
81848731
SM		 1550 WARN_ON(vport->enabled);
1551
1552 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
5742df0f 1553
1ab2068a
MHY		 1554 /* Restore old vport configuration */
1555 esw_apply_vport_conf(esw, vport);
81848731 1556
1bd27b11 1557 /* Attach vport to the eswitch rate limiter */
c9497c98
MHY		 1558 if (esw_vport_enable_qos(esw, vport_num, vport->info.max_rate,
1559 vport->qos.bw_share))
1bd27b11
MHY		 1560 esw_warn(esw->dev, "Failed to attach vport %d to eswitch rate limiter", vport_num);
1561
81848731
SM		 1562 /* Sync with current vport context */
1563 vport->enabled_events = enable_events;
073bb189 1564 vport->enabled = true;
073bb189 1565
a35f71f2 1566 /* only PF is trusted by default */
1ab2068a
MHY		 1567 if (!vport_num)
1568 vport->info.trusted = true;
1569
25fff58c 1570 esw_vport_change_handle_locked(vport);
81848731
SM		 1571
1572 esw->enabled_vports++;
1573 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
dfcb1ed3 1574 mutex_unlock(&esw->state_lock);
81848731
SM		 1575}
1576
073bb189
SM		 1577static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
1578{
1579 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189
SM		 1580
1581 if (!vport->enabled)
1582 return;
1583
81848731 1584 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
073bb189 1585 /* Mark this vport as disabled to discard new events */
073bb189 1586 vport->enabled = false;
831cae1d
MHY		 1587
1588 synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
073bb189
SM		 1589 /* Wait for current already scheduled events to complete */
1590 flush_workqueue(esw->work_queue);
073bb189
SM		 1591 /* Disable events from this vport */
1592 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
dfcb1ed3 1593 mutex_lock(&esw->state_lock);
586cfa7f
MHY		 1594 /* We don't assume VFs will cleanup after themselves.
1595 * Calling vport change handler while vport is disabled will cleanup
1596 * the vport resources.
1597 */
1edc57e2 1598 esw_vport_change_handle_locked(vport);
586cfa7f 1599 vport->enabled_events = 0;
1bd27b11 1600 esw_vport_disable_qos(esw, vport_num);
f96750f8 1601 if (vport_num && esw->mode == SRIOV_LEGACY) {
1ab2068a
MHY		 1602 mlx5_modify_vport_admin_state(esw->dev,
1603 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1604 vport_num,
1605 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
5742df0f
MHY		 1606 esw_vport_disable_egress_acl(esw, vport);
1607 esw_vport_disable_ingress_acl(esw, vport);
1608 }
81848731 1609 esw->enabled_vports--;
dfcb1ed3 1610 mutex_unlock(&esw->state_lock);
073bb189
SM		 1611}
1612
1613/* Public E-Switch API */
6ab36e35 1614int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode)
81848731
SM		 1615{
1616 int err;
69697b6e 1617 int i, enabled_events;
81848731
SM		 1618
1619 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1620 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1621 return 0;
1622
1623 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
1624 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
1625 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
9eb78923 1626 return -EOPNOTSUPP;
81848731
SM		 1627 }
1628
5742df0f
MHY		 1629 if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
1630 esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
1631
1632 if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
1633 esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
1634
6ab36e35 1635 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode);
6ab36e35 1636 esw->mode = mode;
81848731
SM		 1637 esw_disable_vport(esw, 0);
1638
69697b6e
OG		 1639 if (mode == SRIOV_LEGACY)
1640 err = esw_create_legacy_fdb_table(esw, nvfs + 1);
1641 else
c930a3ad 1642 err = esw_offloads_init(esw, nvfs + 1);
81848731
SM		 1643 if (err)
1644 goto abort;
1645
1bd27b11
MHY		 1646 err = esw_create_tsar(esw);
1647 if (err)
1648 esw_warn(esw->dev, "Failed to create eswitch TSAR");
1649
69697b6e 1650 enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE;
81848731 1651 for (i = 0; i <= nvfs; i++)
69697b6e 1652 esw_enable_vport(esw, i, enabled_events);
81848731
SM		 1653
1654 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
1655 esw->enabled_vports);
1656 return 0;
1657
1658abort:
1659 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
4eea37d7 1660 esw->mode = SRIOV_NONE;
81848731
SM		 1661 return err;
1662}
1663
1664void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
1665{
a35f71f2 1666 struct esw_mc_addr *mc_promisc;
c930a3ad 1667 int nvports;
81848731
SM		 1668 int i;
1669
1670 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
079adf05
EBE		 1671 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH ||
1672 esw->mode == SRIOV_NONE)
81848731
SM		 1673 return;
1674
6ab36e35
OG		 1675 esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
1676 esw->enabled_vports, esw->mode);
81848731 1677
0a0ab1d2 1678 mc_promisc = &esw->mc_promisc;
c930a3ad 1679 nvports = esw->enabled_vports;
a35f71f2 1680
81848731
SM		 1681 for (i = 0; i < esw->total_vports; i++)
1682 esw_disable_vport(esw, i);
1683
a35f71f2 1684 if (mc_promisc && mc_promisc->uplink_rule)
74491de9 1685 mlx5_del_flow_rules(mc_promisc->uplink_rule);
a35f71f2 1686
1bd27b11 1687 esw_destroy_tsar(esw);
a35f71f2 1688
69697b6e
OG		 1689 if (esw->mode == SRIOV_LEGACY)
1690 esw_destroy_legacy_fdb_table(esw);
c930a3ad
OG		 1691 else if (esw->mode == SRIOV_OFFLOADS)
1692 esw_offloads_cleanup(esw, nvports);
81848731 1693
6ab36e35 1694 esw->mode = SRIOV_NONE;
81848731
SM		 1695 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
1696 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1697}
1698
62a9b90a
MHY		 1699void mlx5_eswitch_attach(struct mlx5_eswitch *esw)
1700{
1701 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1702 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1703 return;
1704
1705 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1706 /* VF Vports will be enabled when SRIOV is enabled */
1707}
1708
1709void mlx5_eswitch_detach(struct mlx5_eswitch *esw)
1710{
1711 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1712 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1713 return;
1714
1715 esw_disable_vport(esw, 0);
1716}
1717
073bb189
SM		 1718int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1719{
1720 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
efdc810b 1721 int total_vports = MLX5_TOTAL_VPORTS(dev);
073bb189
SM		 1722 struct mlx5_eswitch *esw;
1723 int vport_num;
1724 int err;
1725
1726 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
1727 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1728 return 0;
1729
1730 esw_info(dev,
1731 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
1732 total_vports, l2_table_size,
1733 MLX5_MAX_UC_PER_VPORT(dev),
1734 MLX5_MAX_MC_PER_VPORT(dev));
1735
1736 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
1737 if (!esw)
1738 return -ENOMEM;
1739
1740 esw->dev = dev;
1741
1742 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
1743 sizeof(uintptr_t), GFP_KERNEL);
1744 if (!esw->l2_table.bitmap) {
1745 err = -ENOMEM;
1746 goto abort;
1747 }
1748 esw->l2_table.size = l2_table_size;
1749
1750 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
1751 if (!esw->work_queue) {
1752 err = -ENOMEM;
1753 goto abort;
1754 }
1755
1756 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
1757 GFP_KERNEL);
1758 if (!esw->vports) {
1759 err = -ENOMEM;
1760 goto abort;
1761 }
1762
127ea380
HHZ		 1763 esw->offloads.vport_reps =
1764 kzalloc(total_vports * sizeof(struct mlx5_eswitch_rep),
1765 GFP_KERNEL);
1766 if (!esw->offloads.vport_reps) {
1767 err = -ENOMEM;
1768 goto abort;
1769 }
1770
a54e20b4 1771 hash_init(esw->offloads.encap_tbl);
11c9c548 1772 hash_init(esw->offloads.mod_hdr_tbl);
dfcb1ed3
MHY		 1773 mutex_init(&esw->state_lock);
1774
073bb189
SM		 1775 for (vport_num = 0; vport_num < total_vports; vport_num++) {
1776 struct mlx5_vport *vport = &esw->vports[vport_num];
1777
1778 vport->vport = vport_num;
1ab2068a 1779 vport->info.link_state = MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
073bb189
SM		 1780 vport->dev = dev;
1781 INIT_WORK(&vport->vport_change_handler,
1782 esw_vport_change_handler);
073bb189
SM		 1783 }
1784
81848731
SM		 1785 esw->total_vports = total_vports;
1786 esw->enabled_vports = 0;
6ab36e35 1787 esw->mode = SRIOV_NONE;
bffaa916 1788 esw->offloads.inline_mode = MLX5_INLINE_MODE_NONE;
7768d197
RD		 1789 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, encap) &&
1790 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))
1791 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
1792 else
1793 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
073bb189 1794
81848731 1795 dev->priv.eswitch = esw;
073bb189
SM		 1796 return 0;
1797abort:
1798 if (esw->work_queue)
1799 destroy_workqueue(esw->work_queue);
1800 kfree(esw->l2_table.bitmap);
1801 kfree(esw->vports);
127ea380 1802 kfree(esw->offloads.vport_reps);
073bb189
SM		 1803 kfree(esw);
1804 return err;
1805}
1806
1807void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
1808{
1809 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1810 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1811 return;
1812
1813 esw_info(esw->dev, "cleanup\n");
073bb189
SM		 1814
1815 esw->dev->priv.eswitch = NULL;
1816 destroy_workqueue(esw->work_queue);
1817 kfree(esw->l2_table.bitmap);
127ea380 1818 kfree(esw->offloads.vport_reps);
073bb189
SM		 1819 kfree(esw->vports);
1820 kfree(esw);
1821}
1822
1823void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1824{
1825 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1826 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1827 struct mlx5_vport *vport;
1828
1829 if (!esw) {
1830 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1831 vport_num);
1832 return;
1833 }
1834
1835 vport = &esw->vports[vport_num];
073bb189
SM		 1836 if (vport->enabled)
1837 queue_work(esw->work_queue, &vport->vport_change_handler);
073bb189 1838}
77256579
SM		 1839
1840/* Vport Administration */
1841#define ESW_ALLOWED(esw) \
1842 (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
1843#define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
1844
1845int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
1846 int vport, u8 mac[ETH_ALEN])
1847{
f942380c 1848 struct mlx5_vport *evport;
23898c76
NO		 1849 u64 node_guid;
1850 int err = 0;
77256579
SM		 1851
1852 if (!ESW_ALLOWED(esw))
1853 return -EPERM;
ccce1700 1854 if (!LEGAL_VPORT(esw, vport) || is_multicast_ether_addr(mac))
77256579
SM		 1855 return -EINVAL;
1856
1ab2068a 1857 mutex_lock(&esw->state_lock);
f942380c
MHY		 1858 evport = &esw->vports[vport];
1859
1ab2068a 1860 if (evport->info.spoofchk && !is_valid_ether_addr(mac)) {
f942380c
MHY		 1861 mlx5_core_warn(esw->dev,
1862 "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
1863 vport);
1ab2068a
MHY		 1864 err = -EPERM;
1865 goto unlock;
f942380c
MHY		 1866 }
1867
77256579
SM		 1868 err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
1869 if (err) {
1870 mlx5_core_warn(esw->dev,
1871 "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
1872 vport, err);
1ab2068a 1873 goto unlock;
77256579
SM		 1874 }
1875
23898c76
NO		 1876 node_guid_gen_from_mac(&node_guid, mac);
1877 err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
1878 if (err)
1879 mlx5_core_warn(esw->dev,
1880 "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
1881 vport, err);
1882
1ab2068a
MHY		 1883 ether_addr_copy(evport->info.mac, mac);
1884 evport->info.node_guid = node_guid;
f96750f8 1885 if (evport->enabled && esw->mode == SRIOV_LEGACY)
f942380c 1886 err = esw_vport_ingress_config(esw, evport);
1ab2068a
MHY		 1887
1888unlock:
f942380c 1889 mutex_unlock(&esw->state_lock);
77256579
SM		 1890 return err;
1891}
1892
1893int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
1894 int vport, int link_state)
1895{
1ab2068a
MHY		 1896 struct mlx5_vport *evport;
1897 int err = 0;
1898
77256579
SM		 1899 if (!ESW_ALLOWED(esw))
1900 return -EPERM;
1901 if (!LEGAL_VPORT(esw, vport))
1902 return -EINVAL;
1903
1ab2068a
MHY		 1904 mutex_lock(&esw->state_lock);
1905 evport = &esw->vports[vport];
1906
1907 err = mlx5_modify_vport_admin_state(esw->dev,
1908 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1909 vport, link_state);
1910 if (err) {
1911 mlx5_core_warn(esw->dev,
1912 "Failed to set vport %d link state, err = %d",
1913 vport, err);
1914 goto unlock;
1915 }
1916
1917 evport->info.link_state = link_state;
1918
1919unlock:
1920 mutex_unlock(&esw->state_lock);
1921 return 0;
77256579
SM		 1922}
1923
1924int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
1925 int vport, struct ifla_vf_info *ivi)
1926{
f942380c 1927 struct mlx5_vport *evport;
9e7ea352 1928
77256579
SM		 1929 if (!ESW_ALLOWED(esw))
1930 return -EPERM;
1931 if (!LEGAL_VPORT(esw, vport))
1932 return -EINVAL;
1933
f942380c
MHY		 1934 evport = &esw->vports[vport];
1935
77256579
SM		 1936 memset(ivi, 0, sizeof(*ivi));
1937 ivi->vf = vport - 1;
1938
1ab2068a
MHY		 1939 mutex_lock(&esw->state_lock);
1940 ether_addr_copy(ivi->mac, evport->info.mac);
1941 ivi->linkstate = evport->info.link_state;
1942 ivi->vlan = evport->info.vlan;
1943 ivi->qos = evport->info.qos;
1944 ivi->spoofchk = evport->info.spoofchk;
1945 ivi->trusted = evport->info.trusted;
c9497c98 1946 ivi->min_tx_rate = evport->info.min_rate;
bd77bf1c 1947 ivi->max_tx_rate = evport->info.max_rate;
1ab2068a 1948 mutex_unlock(&esw->state_lock);
77256579
SM		 1949
1950 return 0;
1951}
9e7ea352 1952
e33dfe31
OG		 1953int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1954 int vport, u16 vlan, u8 qos, u8 set_flags)
9e7ea352 1955{
dfcb1ed3
MHY		 1956 struct mlx5_vport *evport;
1957 int err = 0;
9e7ea352
SM		 1958
1959 if (!ESW_ALLOWED(esw))
1960 return -EPERM;
1961 if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
1962 return -EINVAL;
1963
1ab2068a 1964 mutex_lock(&esw->state_lock);
dfcb1ed3
MHY		 1965 evport = &esw->vports[vport];
1966
e33dfe31 1967 err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set_flags);
dfcb1ed3 1968 if (err)
1ab2068a 1969 goto unlock;
dfcb1ed3 1970
1ab2068a
MHY		 1971 evport->info.vlan = vlan;
1972 evport->info.qos = qos;
f96750f8 1973 if (evport->enabled && esw->mode == SRIOV_LEGACY) {
dfcb1ed3
MHY		 1974 err = esw_vport_ingress_config(esw, evport);
1975 if (err)
1ab2068a 1976 goto unlock;
dfcb1ed3
MHY		 1977 err = esw_vport_egress_config(esw, evport);
1978 }
1979
1ab2068a 1980unlock:
dfcb1ed3
MHY		 1981 mutex_unlock(&esw->state_lock);
1982 return err;
9e7ea352 1983}
3b751a2a 1984
e33dfe31
OG		 1985int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1986 int vport, u16 vlan, u8 qos)
1987{
1988 u8 set_flags = 0;
1989
1990 if (vlan || qos)
1991 set_flags = SET_VLAN_STRIP | SET_VLAN_INSERT;
1992
1993 return __mlx5_eswitch_set_vport_vlan(esw, vport, vlan, qos, set_flags);
1994}
1995
f942380c
MHY		 1996int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
1997 int vport, bool spoofchk)
1998{
1999 struct mlx5_vport *evport;
2000 bool pschk;
2001 int err = 0;
2002
2003 if (!ESW_ALLOWED(esw))
2004 return -EPERM;
2005 if (!LEGAL_VPORT(esw, vport))
2006 return -EINVAL;
2007
f942380c 2008 mutex_lock(&esw->state_lock);
1ab2068a
MHY		 2009 evport = &esw->vports[vport];
2010 pschk = evport->info.spoofchk;
2011 evport->info.spoofchk = spoofchk;
2012 if (evport->enabled && esw->mode == SRIOV_LEGACY)
f942380c 2013 err = esw_vport_ingress_config(esw, evport);
1ab2068a
MHY		 2014 if (err)
2015 evport->info.spoofchk = pschk;
f942380c
MHY		 2016 mutex_unlock(&esw->state_lock);
2017
2018 return err;
2019}
2020
1edc57e2
MHY		 2021int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
2022 int vport, bool setting)
2023{
2024 struct mlx5_vport *evport;
2025
2026 if (!ESW_ALLOWED(esw))
2027 return -EPERM;
2028 if (!LEGAL_VPORT(esw, vport))
2029 return -EINVAL;
2030
1edc57e2 2031 mutex_lock(&esw->state_lock);
1ab2068a
MHY		 2032 evport = &esw->vports[vport];
2033 evport->info.trusted = setting;
1edc57e2
MHY		 2034 if (evport->enabled)
2035 esw_vport_change_handle_locked(evport);
2036 mutex_unlock(&esw->state_lock);
2037
2038 return 0;
2039}
2040
c9497c98 2041static u32 calculate_vports_min_rate_divider(struct mlx5_eswitch *esw)
bd77bf1c 2042{
c9497c98 2043 u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share);
bd77bf1c 2044 struct mlx5_vport *evport;
c9497c98
MHY		 2045 u32 max_guarantee = 0;
2046 int i;
2047
2048 for (i = 0; i <= esw->total_vports; i++) {
2049 evport = &esw->vports[i];
2050 if (!evport->enabled || evport->info.min_rate < max_guarantee)
2051 continue;
2052 max_guarantee = evport->info.min_rate;
2053 }
2054
2055 return max_t(u32, max_guarantee / fw_max_bw_share, 1);
2056}
2057
2058static int normalize_vports_min_rate(struct mlx5_eswitch *esw, u32 divider)
2059{
2060 u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share);
2061 struct mlx5_vport *evport;
2062 u32 vport_max_rate;
2063 u32 vport_min_rate;
2064 u32 bw_share;
2065 int err;
2066 int i;
2067
2068 for (i = 0; i <= esw->total_vports; i++) {
2069 evport = &esw->vports[i];
2070 if (!evport->enabled)
2071 continue;
2072 vport_min_rate = evport->info.min_rate;
2073 vport_max_rate = evport->info.max_rate;
2074 bw_share = MLX5_MIN_BW_SHARE;
2075
2076 if (vport_min_rate)
2077 bw_share = MLX5_RATE_TO_BW_SHARE(vport_min_rate,
2078 divider,
2079 fw_max_bw_share);
2080
2081 if (bw_share == evport->qos.bw_share)
2082 continue;
2083
2084 err = esw_vport_qos_config(esw, i, vport_max_rate,
2085 bw_share);
2086 if (!err)
2087 evport->qos.bw_share = bw_share;
2088 else
2089 return err;
2090 }
2091
2092 return 0;
2093}
2094
2095int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
2096 u32 max_rate, u32 min_rate)
2097{
2098 u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share);
2099 bool min_rate_supported = MLX5_CAP_QOS(esw->dev, esw_bw_share) &&
2100 fw_max_bw_share >= MLX5_MIN_BW_SHARE;
2101 bool max_rate_supported = MLX5_CAP_QOS(esw->dev, esw_rate_limit);
2102 struct mlx5_vport *evport;
2103 u32 previous_min_rate;
2104 u32 divider;
bd77bf1c
MHY		 2105 int err = 0;
2106
2107 if (!ESW_ALLOWED(esw))
2108 return -EPERM;
2109 if (!LEGAL_VPORT(esw, vport))
2110 return -EINVAL;
c9497c98
MHY		 2111 if ((min_rate && !min_rate_supported) || (max_rate && !max_rate_supported))
2112 return -EOPNOTSUPP;
bd77bf1c
MHY		 2113
2114 mutex_lock(&esw->state_lock);
2115 evport = &esw->vports[vport];
c9497c98
MHY		 2116
2117 if (min_rate == evport->info.min_rate)
2118 goto set_max_rate;
2119
2120 previous_min_rate = evport->info.min_rate;
2121 evport->info.min_rate = min_rate;
2122 divider = calculate_vports_min_rate_divider(esw);
2123 err = normalize_vports_min_rate(esw, divider);
2124 if (err) {
2125 evport->info.min_rate = previous_min_rate;
2126 goto unlock;
2127 }
2128
2129set_max_rate:
2130 if (max_rate == evport->info.max_rate)
2131 goto unlock;
2132
2133 err = esw_vport_qos_config(esw, vport, max_rate, evport->qos.bw_share);
bd77bf1c
MHY		 2134 if (!err)
2135 evport->info.max_rate = max_rate;
2136
c9497c98 2137unlock:
bd77bf1c
MHY		 2138 mutex_unlock(&esw->state_lock);
2139 return err;
2140}
2141
3b751a2a
SM		 2142int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
2143 int vport,
2144 struct ifla_vf_stats *vf_stats)
2145{
2146 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
c4f287c4 2147 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
3b751a2a
SM		 2148 int err = 0;
2149 u32 *out;
2150
2151 if (!ESW_ALLOWED(esw))
2152 return -EPERM;
2153 if (!LEGAL_VPORT(esw, vport))
2154 return -EINVAL;
2155
1b9a07ee 2156 out = kvzalloc(outlen, GFP_KERNEL);
3b751a2a
SM		 2157 if (!out)
2158 return -ENOMEM;
2159
3b751a2a
SM		 2160 MLX5_SET(query_vport_counter_in, in, opcode,
2161 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
2162 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
2163 MLX5_SET(query_vport_counter_in, in, vport_number, vport);
2164 if (vport)
2165 MLX5_SET(query_vport_counter_in, in, other_vport, 1);
2166
2167 memset(out, 0, outlen);
2168 err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
2169 if (err)
2170 goto free_out;
2171
2172 #define MLX5_GET_CTR(p, x) \
2173 MLX5_GET64(query_vport_counter_out, p, x)
2174
2175 memset(vf_stats, 0, sizeof(*vf_stats));
2176 vf_stats->rx_packets =
2177 MLX5_GET_CTR(out, received_eth_unicast.packets) +
2178 MLX5_GET_CTR(out, received_eth_multicast.packets) +
2179 MLX5_GET_CTR(out, received_eth_broadcast.packets);
2180
2181 vf_stats->rx_bytes =
2182 MLX5_GET_CTR(out, received_eth_unicast.octets) +
2183 MLX5_GET_CTR(out, received_eth_multicast.octets) +
2184 MLX5_GET_CTR(out, received_eth_broadcast.octets);
2185
2186 vf_stats->tx_packets =
2187 MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
2188 MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
2189 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
2190
2191 vf_stats->tx_bytes =
2192 MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
2193 MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
2194 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
2195
2196 vf_stats->multicast =
2197 MLX5_GET_CTR(out, received_eth_multicast.packets);
2198
2199 vf_stats->broadcast =
2200 MLX5_GET_CTR(out, received_eth_broadcast.packets);
2201
2202free_out:
2203 kvfree(out);
2204 return err;
2205}
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