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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/mlx5/driver.h> | |
35 | #include <linux/mlx5/mlx5_ifc.h> | |
36 | #include <linux/mlx5/vport.h> | |
86d722ad | 37 | #include <linux/mlx5/fs.h> |
073bb189 SM |
38 | #include "mlx5_core.h" |
39 | #include "eswitch.h" | |
40 | ||
81848731 SM |
41 | #define UPLINK_VPORT 0xFFFF |
42 | ||
073bb189 SM |
43 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
44 | ||
45 | #define esw_info(dev, format, ...) \ | |
46 | pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
47 | ||
48 | #define esw_warn(dev, format, ...) \ | |
49 | pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
50 | ||
51 | #define esw_debug(dev, format, ...) \ | |
52 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
53 | ||
54 | enum { | |
55 | MLX5_ACTION_NONE = 0, | |
56 | MLX5_ACTION_ADD = 1, | |
57 | MLX5_ACTION_DEL = 2, | |
58 | }; | |
59 | ||
81848731 SM |
60 | /* E-Switch UC L2 table hash node */ |
61 | struct esw_uc_addr { | |
073bb189 | 62 | struct l2addr_node node; |
073bb189 SM |
63 | u32 table_index; |
64 | u32 vport; | |
65 | }; | |
66 | ||
81848731 SM |
67 | /* E-Switch MC FDB table hash node */ |
68 | struct esw_mc_addr { /* SRIOV only */ | |
69 | struct l2addr_node node; | |
70 | struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */ | |
71 | u32 refcnt; | |
72 | }; | |
73 | ||
74 | /* Vport UC/MC hash node */ | |
75 | struct vport_addr { | |
76 | struct l2addr_node node; | |
77 | u8 action; | |
78 | u32 vport; | |
79 | struct mlx5_flow_rule *flow_rule; /* SRIOV only */ | |
073bb189 SM |
80 | }; |
81 | ||
82 | enum { | |
83 | UC_ADDR_CHANGE = BIT(0), | |
84 | MC_ADDR_CHANGE = BIT(1), | |
85 | }; | |
86 | ||
81848731 SM |
87 | /* Vport context events */ |
88 | #define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \ | |
89 | MC_ADDR_CHANGE) | |
90 | ||
91 | static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport, | |
073bb189 SM |
92 | u32 events_mask) |
93 | { | |
94 | int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)]; | |
95 | int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)]; | |
96 | void *nic_vport_ctx; | |
97 | int err; | |
98 | ||
99 | memset(out, 0, sizeof(out)); | |
100 | memset(in, 0, sizeof(in)); | |
101 | ||
102 | MLX5_SET(modify_nic_vport_context_in, in, | |
103 | opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT); | |
104 | MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1); | |
105 | MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport); | |
106 | if (vport) | |
107 | MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1); | |
108 | nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in, | |
109 | in, nic_vport_context); | |
110 | ||
111 | MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1); | |
112 | ||
113 | if (events_mask & UC_ADDR_CHANGE) | |
114 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
115 | event_on_uc_address_change, 1); | |
116 | if (events_mask & MC_ADDR_CHANGE) | |
117 | MLX5_SET(nic_vport_context, nic_vport_ctx, | |
118 | event_on_mc_address_change, 1); | |
119 | ||
120 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
121 | if (err) | |
122 | goto ex; | |
123 | err = mlx5_cmd_status_to_err_v2(out); | |
124 | if (err) | |
125 | goto ex; | |
126 | return 0; | |
127 | ex: | |
128 | return err; | |
129 | } | |
130 | ||
9e7ea352 SM |
131 | /* E-Switch vport context HW commands */ |
132 | static int query_esw_vport_context_cmd(struct mlx5_core_dev *mdev, u32 vport, | |
133 | u32 *out, int outlen) | |
134 | { | |
135 | u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)]; | |
136 | ||
137 | memset(in, 0, sizeof(in)); | |
138 | ||
139 | MLX5_SET(query_nic_vport_context_in, in, opcode, | |
140 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT); | |
141 | ||
142 | MLX5_SET(query_esw_vport_context_in, in, vport_number, vport); | |
143 | if (vport) | |
144 | MLX5_SET(query_esw_vport_context_in, in, other_vport, 1); | |
145 | ||
146 | return mlx5_cmd_exec_check_status(mdev, in, sizeof(in), out, outlen); | |
147 | } | |
148 | ||
149 | static int query_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport, | |
150 | u16 *vlan, u8 *qos) | |
151 | { | |
152 | u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)]; | |
153 | int err; | |
154 | bool cvlan_strip; | |
155 | bool cvlan_insert; | |
156 | ||
157 | memset(out, 0, sizeof(out)); | |
158 | ||
159 | *vlan = 0; | |
160 | *qos = 0; | |
161 | ||
162 | if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) || | |
163 | !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist)) | |
164 | return -ENOTSUPP; | |
165 | ||
166 | err = query_esw_vport_context_cmd(dev, vport, out, sizeof(out)); | |
167 | if (err) | |
168 | goto out; | |
169 | ||
170 | cvlan_strip = MLX5_GET(query_esw_vport_context_out, out, | |
171 | esw_vport_context.vport_cvlan_strip); | |
172 | ||
173 | cvlan_insert = MLX5_GET(query_esw_vport_context_out, out, | |
174 | esw_vport_context.vport_cvlan_insert); | |
175 | ||
176 | if (cvlan_strip || cvlan_insert) { | |
177 | *vlan = MLX5_GET(query_esw_vport_context_out, out, | |
178 | esw_vport_context.cvlan_id); | |
179 | *qos = MLX5_GET(query_esw_vport_context_out, out, | |
180 | esw_vport_context.cvlan_pcp); | |
181 | } | |
182 | ||
183 | esw_debug(dev, "Query Vport[%d] cvlan: VLAN %d qos=%d\n", | |
184 | vport, *vlan, *qos); | |
185 | out: | |
186 | return err; | |
187 | } | |
188 | ||
189 | static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport, | |
190 | void *in, int inlen) | |
191 | { | |
192 | u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)]; | |
193 | ||
194 | memset(out, 0, sizeof(out)); | |
195 | ||
196 | MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport); | |
197 | if (vport) | |
198 | MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1); | |
199 | ||
200 | MLX5_SET(modify_esw_vport_context_in, in, opcode, | |
201 | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT); | |
202 | ||
203 | return mlx5_cmd_exec_check_status(dev, in, inlen, | |
204 | out, sizeof(out)); | |
205 | } | |
206 | ||
207 | static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport, | |
208 | u16 vlan, u8 qos, bool set) | |
209 | { | |
210 | u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)]; | |
211 | ||
212 | memset(in, 0, sizeof(in)); | |
213 | ||
214 | if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) || | |
215 | !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist)) | |
216 | return -ENOTSUPP; | |
217 | ||
218 | esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%d\n", | |
219 | vport, vlan, qos, set); | |
220 | ||
221 | if (set) { | |
222 | MLX5_SET(modify_esw_vport_context_in, in, | |
223 | esw_vport_context.vport_cvlan_strip, 1); | |
224 | /* insert only if no vlan in packet */ | |
225 | MLX5_SET(modify_esw_vport_context_in, in, | |
226 | esw_vport_context.vport_cvlan_insert, 1); | |
227 | MLX5_SET(modify_esw_vport_context_in, in, | |
228 | esw_vport_context.cvlan_pcp, qos); | |
229 | MLX5_SET(modify_esw_vport_context_in, in, | |
230 | esw_vport_context.cvlan_id, vlan); | |
231 | } | |
232 | ||
233 | MLX5_SET(modify_esw_vport_context_in, in, | |
234 | field_select.vport_cvlan_strip, 1); | |
235 | MLX5_SET(modify_esw_vport_context_in, in, | |
236 | field_select.vport_cvlan_insert, 1); | |
237 | ||
238 | return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in)); | |
239 | } | |
240 | ||
073bb189 SM |
241 | /* HW L2 Table (MPFS) management */ |
242 | static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index, | |
243 | u8 *mac, u8 vlan_valid, u16 vlan) | |
244 | { | |
245 | u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)]; | |
246 | u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)]; | |
247 | u8 *in_mac_addr; | |
248 | ||
249 | memset(in, 0, sizeof(in)); | |
250 | memset(out, 0, sizeof(out)); | |
251 | ||
252 | MLX5_SET(set_l2_table_entry_in, in, opcode, | |
253 | MLX5_CMD_OP_SET_L2_TABLE_ENTRY); | |
254 | MLX5_SET(set_l2_table_entry_in, in, table_index, index); | |
255 | MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid); | |
256 | MLX5_SET(set_l2_table_entry_in, in, vlan, vlan); | |
257 | ||
258 | in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address); | |
259 | ether_addr_copy(&in_mac_addr[2], mac); | |
260 | ||
261 | return mlx5_cmd_exec_check_status(dev, in, sizeof(in), | |
262 | out, sizeof(out)); | |
263 | } | |
264 | ||
265 | static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index) | |
266 | { | |
267 | u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)]; | |
268 | u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)]; | |
269 | ||
270 | memset(in, 0, sizeof(in)); | |
271 | memset(out, 0, sizeof(out)); | |
272 | ||
273 | MLX5_SET(delete_l2_table_entry_in, in, opcode, | |
274 | MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY); | |
275 | MLX5_SET(delete_l2_table_entry_in, in, table_index, index); | |
276 | return mlx5_cmd_exec_check_status(dev, in, sizeof(in), | |
277 | out, sizeof(out)); | |
278 | } | |
279 | ||
280 | static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix) | |
281 | { | |
282 | int err = 0; | |
283 | ||
284 | *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size); | |
285 | if (*ix >= l2_table->size) | |
286 | err = -ENOSPC; | |
287 | else | |
288 | __set_bit(*ix, l2_table->bitmap); | |
289 | ||
290 | return err; | |
291 | } | |
292 | ||
293 | static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix) | |
294 | { | |
295 | __clear_bit(ix, l2_table->bitmap); | |
296 | } | |
297 | ||
298 | static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac, | |
299 | u8 vlan_valid, u16 vlan, | |
300 | u32 *index) | |
301 | { | |
302 | struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table; | |
303 | int err; | |
304 | ||
305 | err = alloc_l2_table_index(l2_table, index); | |
306 | if (err) | |
307 | return err; | |
308 | ||
309 | err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan); | |
310 | if (err) | |
311 | free_l2_table_index(l2_table, *index); | |
312 | ||
313 | return err; | |
314 | } | |
315 | ||
316 | static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index) | |
317 | { | |
318 | struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table; | |
319 | ||
320 | del_l2_table_entry_cmd(dev, index); | |
321 | free_l2_table_index(l2_table, index); | |
322 | } | |
323 | ||
81848731 SM |
324 | /* E-Switch FDB */ |
325 | static struct mlx5_flow_rule * | |
326 | esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport) | |
327 | { | |
328 | int match_header = MLX5_MATCH_OUTER_HEADERS; | |
329 | struct mlx5_flow_destination dest; | |
330 | struct mlx5_flow_rule *flow_rule = NULL; | |
331 | u32 *match_v; | |
332 | u32 *match_c; | |
333 | u8 *dmac_v; | |
334 | u8 *dmac_c; | |
335 | ||
336 | match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
337 | match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
338 | if (!match_v || !match_c) { | |
339 | pr_warn("FDB: Failed to alloc match parameters\n"); | |
340 | goto out; | |
341 | } | |
342 | dmac_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
343 | outer_headers.dmac_47_16); | |
344 | dmac_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
345 | outer_headers.dmac_47_16); | |
346 | ||
347 | ether_addr_copy(dmac_v, mac); | |
348 | /* Match criteria mask */ | |
349 | memset(dmac_c, 0xff, 6); | |
350 | ||
351 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
352 | dest.vport_num = vport; | |
353 | ||
354 | esw_debug(esw->dev, | |
355 | "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n", | |
356 | dmac_v, dmac_c, vport); | |
357 | flow_rule = | |
86d722ad | 358 | mlx5_add_flow_rule(esw->fdb_table.fdb, |
81848731 SM |
359 | match_header, |
360 | match_c, | |
361 | match_v, | |
362 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST, | |
363 | 0, &dest); | |
364 | if (IS_ERR_OR_NULL(flow_rule)) { | |
365 | pr_warn( | |
366 | "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n", | |
367 | dmac_v, dmac_c, vport, PTR_ERR(flow_rule)); | |
368 | flow_rule = NULL; | |
369 | } | |
370 | out: | |
371 | kfree(match_v); | |
372 | kfree(match_c); | |
373 | return flow_rule; | |
374 | } | |
375 | ||
376 | static int esw_create_fdb_table(struct mlx5_eswitch *esw, int nvports) | |
377 | { | |
86d722ad | 378 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); |
81848731 | 379 | struct mlx5_core_dev *dev = esw->dev; |
86d722ad | 380 | struct mlx5_flow_namespace *root_ns; |
81848731 | 381 | struct mlx5_flow_table *fdb; |
86d722ad MG |
382 | struct mlx5_flow_group *g; |
383 | void *match_criteria; | |
384 | int table_size; | |
385 | u32 *flow_group_in; | |
81848731 | 386 | u8 *dmac; |
86d722ad | 387 | int err = 0; |
81848731 SM |
388 | |
389 | esw_debug(dev, "Create FDB log_max_size(%d)\n", | |
390 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); | |
391 | ||
86d722ad MG |
392 | root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB); |
393 | if (!root_ns) { | |
394 | esw_warn(dev, "Failed to get FDB flow namespace\n"); | |
395 | return -ENOMEM; | |
396 | } | |
81848731 | 397 | |
86d722ad MG |
398 | flow_group_in = mlx5_vzalloc(inlen); |
399 | if (!flow_group_in) | |
400 | return -ENOMEM; | |
401 | memset(flow_group_in, 0, inlen); | |
402 | ||
403 | table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size)); | |
d63cd286 | 404 | fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0); |
86d722ad MG |
405 | if (IS_ERR_OR_NULL(fdb)) { |
406 | err = PTR_ERR(fdb); | |
407 | esw_warn(dev, "Failed to create FDB Table err %d\n", err); | |
408 | goto out; | |
409 | } | |
81848731 | 410 | |
86d722ad MG |
411 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
412 | MLX5_MATCH_OUTER_HEADERS); | |
413 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); | |
414 | dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16); | |
415 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
416 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1); | |
417 | eth_broadcast_addr(dmac); | |
418 | ||
419 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
420 | if (IS_ERR_OR_NULL(g)) { | |
421 | err = PTR_ERR(g); | |
422 | esw_warn(dev, "Failed to create flow group err(%d)\n", err); | |
423 | goto out; | |
424 | } | |
425 | ||
426 | esw->fdb_table.addr_grp = g; | |
81848731 | 427 | esw->fdb_table.fdb = fdb; |
86d722ad MG |
428 | out: |
429 | kfree(flow_group_in); | |
430 | if (err && !IS_ERR_OR_NULL(fdb)) | |
431 | mlx5_destroy_flow_table(fdb); | |
432 | return err; | |
81848731 SM |
433 | } |
434 | ||
435 | static void esw_destroy_fdb_table(struct mlx5_eswitch *esw) | |
436 | { | |
437 | if (!esw->fdb_table.fdb) | |
438 | return; | |
439 | ||
86d722ad MG |
440 | esw_debug(esw->dev, "Destroy FDB Table\n"); |
441 | mlx5_destroy_flow_group(esw->fdb_table.addr_grp); | |
81848731 SM |
442 | mlx5_destroy_flow_table(esw->fdb_table.fdb); |
443 | esw->fdb_table.fdb = NULL; | |
86d722ad | 444 | esw->fdb_table.addr_grp = NULL; |
81848731 SM |
445 | } |
446 | ||
447 | /* E-Switch vport UC/MC lists management */ | |
448 | typedef int (*vport_addr_action)(struct mlx5_eswitch *esw, | |
449 | struct vport_addr *vaddr); | |
450 | ||
451 | static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
452 | { | |
453 | struct hlist_head *hash = esw->l2_table.l2_hash; | |
454 | struct esw_uc_addr *esw_uc; | |
455 | u8 *mac = vaddr->node.addr; | |
456 | u32 vport = vaddr->vport; | |
457 | int err; | |
458 | ||
459 | esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr); | |
460 | if (esw_uc) { | |
073bb189 SM |
461 | esw_warn(esw->dev, |
462 | "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n", | |
81848731 | 463 | mac, vport, esw_uc->vport); |
073bb189 SM |
464 | return -EEXIST; |
465 | } | |
466 | ||
81848731 SM |
467 | esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL); |
468 | if (!esw_uc) | |
073bb189 | 469 | return -ENOMEM; |
81848731 | 470 | esw_uc->vport = vport; |
073bb189 | 471 | |
81848731 | 472 | err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index); |
073bb189 | 473 | if (err) |
81848731 SM |
474 | goto abort; |
475 | ||
476 | if (esw->fdb_table.fdb) /* SRIOV is enabled: Forward UC MAC to vport */ | |
477 | vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport); | |
478 | ||
479 | esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n", | |
480 | vport, mac, esw_uc->table_index, vaddr->flow_rule); | |
481 | return err; | |
482 | abort: | |
483 | l2addr_hash_del(esw_uc); | |
073bb189 SM |
484 | return err; |
485 | } | |
486 | ||
81848731 | 487 | static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) |
073bb189 | 488 | { |
81848731 SM |
489 | struct hlist_head *hash = esw->l2_table.l2_hash; |
490 | struct esw_uc_addr *esw_uc; | |
491 | u8 *mac = vaddr->node.addr; | |
492 | u32 vport = vaddr->vport; | |
493 | ||
494 | esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr); | |
495 | if (!esw_uc || esw_uc->vport != vport) { | |
496 | esw_debug(esw->dev, | |
497 | "MAC(%pM) doesn't belong to vport (%d)\n", | |
498 | mac, vport); | |
499 | return -EINVAL; | |
500 | } | |
501 | esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n", | |
502 | vport, mac, esw_uc->table_index, vaddr->flow_rule); | |
503 | ||
504 | del_l2_table_entry(esw->dev, esw_uc->table_index); | |
505 | ||
506 | if (vaddr->flow_rule) | |
86d722ad | 507 | mlx5_del_flow_rule(vaddr->flow_rule); |
81848731 SM |
508 | vaddr->flow_rule = NULL; |
509 | ||
510 | l2addr_hash_del(esw_uc); | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
515 | { | |
516 | struct hlist_head *hash = esw->mc_table; | |
517 | struct esw_mc_addr *esw_mc; | |
518 | u8 *mac = vaddr->node.addr; | |
519 | u32 vport = vaddr->vport; | |
520 | ||
521 | if (!esw->fdb_table.fdb) | |
522 | return 0; | |
523 | ||
524 | esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr); | |
525 | if (esw_mc) | |
526 | goto add; | |
527 | ||
528 | esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL); | |
529 | if (!esw_mc) | |
530 | return -ENOMEM; | |
531 | ||
532 | esw_mc->uplink_rule = /* Forward MC MAC to Uplink */ | |
533 | esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT); | |
534 | add: | |
535 | esw_mc->refcnt++; | |
536 | /* Forward MC MAC to vport */ | |
537 | vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport); | |
538 | esw_debug(esw->dev, | |
539 | "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n", | |
540 | vport, mac, vaddr->flow_rule, | |
541 | esw_mc->refcnt, esw_mc->uplink_rule); | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr) | |
546 | { | |
547 | struct hlist_head *hash = esw->mc_table; | |
548 | struct esw_mc_addr *esw_mc; | |
549 | u8 *mac = vaddr->node.addr; | |
550 | u32 vport = vaddr->vport; | |
073bb189 | 551 | |
81848731 SM |
552 | if (!esw->fdb_table.fdb) |
553 | return 0; | |
554 | ||
555 | esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr); | |
556 | if (!esw_mc) { | |
557 | esw_warn(esw->dev, | |
558 | "Failed to find eswitch MC addr for MAC(%pM) vport(%d)", | |
073bb189 SM |
559 | mac, vport); |
560 | return -EINVAL; | |
561 | } | |
81848731 SM |
562 | esw_debug(esw->dev, |
563 | "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n", | |
564 | vport, mac, vaddr->flow_rule, esw_mc->refcnt, | |
565 | esw_mc->uplink_rule); | |
566 | ||
567 | if (vaddr->flow_rule) | |
86d722ad | 568 | mlx5_del_flow_rule(vaddr->flow_rule); |
81848731 SM |
569 | vaddr->flow_rule = NULL; |
570 | ||
571 | if (--esw_mc->refcnt) | |
572 | return 0; | |
073bb189 | 573 | |
81848731 | 574 | if (esw_mc->uplink_rule) |
86d722ad | 575 | mlx5_del_flow_rule(esw_mc->uplink_rule); |
81848731 SM |
576 | |
577 | l2addr_hash_del(esw_mc); | |
073bb189 SM |
578 | return 0; |
579 | } | |
580 | ||
81848731 SM |
581 | /* Apply vport UC/MC list to HW l2 table and FDB table */ |
582 | static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw, | |
583 | u32 vport_num, int list_type) | |
073bb189 SM |
584 | { |
585 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
81848731 SM |
586 | bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC; |
587 | vport_addr_action vport_addr_add; | |
588 | vport_addr_action vport_addr_del; | |
589 | struct vport_addr *addr; | |
073bb189 SM |
590 | struct l2addr_node *node; |
591 | struct hlist_head *hash; | |
592 | struct hlist_node *tmp; | |
593 | int hi; | |
594 | ||
81848731 SM |
595 | vport_addr_add = is_uc ? esw_add_uc_addr : |
596 | esw_add_mc_addr; | |
597 | vport_addr_del = is_uc ? esw_del_uc_addr : | |
598 | esw_del_mc_addr; | |
599 | ||
600 | hash = is_uc ? vport->uc_list : vport->mc_list; | |
073bb189 | 601 | for_each_l2hash_node(node, tmp, hash, hi) { |
81848731 | 602 | addr = container_of(node, struct vport_addr, node); |
073bb189 SM |
603 | switch (addr->action) { |
604 | case MLX5_ACTION_ADD: | |
81848731 | 605 | vport_addr_add(esw, addr); |
073bb189 SM |
606 | addr->action = MLX5_ACTION_NONE; |
607 | break; | |
608 | case MLX5_ACTION_DEL: | |
81848731 | 609 | vport_addr_del(esw, addr); |
073bb189 SM |
610 | l2addr_hash_del(addr); |
611 | break; | |
612 | } | |
613 | } | |
614 | } | |
615 | ||
81848731 SM |
616 | /* Sync vport UC/MC list from vport context */ |
617 | static void esw_update_vport_addr_list(struct mlx5_eswitch *esw, | |
618 | u32 vport_num, int list_type) | |
073bb189 SM |
619 | { |
620 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
81848731 | 621 | bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC; |
073bb189 | 622 | u8 (*mac_list)[ETH_ALEN]; |
81848731 SM |
623 | struct l2addr_node *node; |
624 | struct vport_addr *addr; | |
073bb189 SM |
625 | struct hlist_head *hash; |
626 | struct hlist_node *tmp; | |
627 | int size; | |
628 | int err; | |
629 | int hi; | |
630 | int i; | |
631 | ||
81848731 SM |
632 | size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) : |
633 | MLX5_MAX_MC_PER_VPORT(esw->dev); | |
073bb189 SM |
634 | |
635 | mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL); | |
636 | if (!mac_list) | |
637 | return; | |
638 | ||
81848731 | 639 | hash = is_uc ? vport->uc_list : vport->mc_list; |
073bb189 SM |
640 | |
641 | for_each_l2hash_node(node, tmp, hash, hi) { | |
81848731 | 642 | addr = container_of(node, struct vport_addr, node); |
073bb189 SM |
643 | addr->action = MLX5_ACTION_DEL; |
644 | } | |
645 | ||
81848731 | 646 | err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type, |
073bb189 SM |
647 | mac_list, &size); |
648 | if (err) | |
649 | return; | |
81848731 SM |
650 | esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n", |
651 | vport_num, is_uc ? "UC" : "MC", size); | |
073bb189 SM |
652 | |
653 | for (i = 0; i < size; i++) { | |
81848731 | 654 | if (is_uc && !is_valid_ether_addr(mac_list[i])) |
073bb189 SM |
655 | continue; |
656 | ||
81848731 SM |
657 | if (!is_uc && !is_multicast_ether_addr(mac_list[i])) |
658 | continue; | |
659 | ||
660 | addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr); | |
073bb189 SM |
661 | if (addr) { |
662 | addr->action = MLX5_ACTION_NONE; | |
663 | continue; | |
664 | } | |
665 | ||
81848731 | 666 | addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr, |
073bb189 SM |
667 | GFP_KERNEL); |
668 | if (!addr) { | |
669 | esw_warn(esw->dev, | |
670 | "Failed to add MAC(%pM) to vport[%d] DB\n", | |
671 | mac_list[i], vport_num); | |
672 | continue; | |
673 | } | |
81848731 | 674 | addr->vport = vport_num; |
073bb189 SM |
675 | addr->action = MLX5_ACTION_ADD; |
676 | } | |
677 | kfree(mac_list); | |
678 | } | |
679 | ||
680 | static void esw_vport_change_handler(struct work_struct *work) | |
681 | { | |
682 | struct mlx5_vport *vport = | |
683 | container_of(work, struct mlx5_vport, vport_change_handler); | |
684 | struct mlx5_core_dev *dev = vport->dev; | |
81848731 | 685 | struct mlx5_eswitch *esw = dev->priv.eswitch; |
073bb189 SM |
686 | u8 mac[ETH_ALEN]; |
687 | ||
688 | mlx5_query_nic_vport_mac_address(dev, vport->vport, mac); | |
81848731 SM |
689 | esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n", |
690 | vport->vport, mac); | |
691 | ||
692 | if (vport->enabled_events & UC_ADDR_CHANGE) { | |
693 | esw_update_vport_addr_list(esw, vport->vport, | |
694 | MLX5_NVPRT_LIST_TYPE_UC); | |
695 | esw_apply_vport_addr_list(esw, vport->vport, | |
696 | MLX5_NVPRT_LIST_TYPE_UC); | |
697 | } | |
073bb189 | 698 | |
81848731 SM |
699 | if (vport->enabled_events & MC_ADDR_CHANGE) { |
700 | esw_update_vport_addr_list(esw, vport->vport, | |
701 | MLX5_NVPRT_LIST_TYPE_MC); | |
702 | esw_apply_vport_addr_list(esw, vport->vport, | |
703 | MLX5_NVPRT_LIST_TYPE_MC); | |
704 | } | |
073bb189 | 705 | |
81848731 | 706 | esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport); |
073bb189 SM |
707 | if (vport->enabled) |
708 | arm_vport_context_events_cmd(dev, vport->vport, | |
81848731 | 709 | vport->enabled_events); |
073bb189 SM |
710 | } |
711 | ||
81848731 SM |
712 | static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num, |
713 | int enable_events) | |
073bb189 SM |
714 | { |
715 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
716 | unsigned long flags; | |
717 | ||
81848731 SM |
718 | WARN_ON(vport->enabled); |
719 | ||
720 | esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num); | |
721 | mlx5_modify_vport_admin_state(esw->dev, | |
722 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
723 | vport_num, | |
724 | MLX5_ESW_VPORT_ADMIN_STATE_AUTO); | |
725 | ||
726 | /* Sync with current vport context */ | |
727 | vport->enabled_events = enable_events; | |
728 | esw_vport_change_handler(&vport->vport_change_handler); | |
729 | ||
073bb189 SM |
730 | spin_lock_irqsave(&vport->lock, flags); |
731 | vport->enabled = true; | |
732 | spin_unlock_irqrestore(&vport->lock, flags); | |
733 | ||
81848731 SM |
734 | arm_vport_context_events_cmd(esw->dev, vport_num, enable_events); |
735 | ||
736 | esw->enabled_vports++; | |
737 | esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num); | |
738 | } | |
739 | ||
740 | static void esw_cleanup_vport(struct mlx5_eswitch *esw, u16 vport_num) | |
741 | { | |
742 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
743 | struct l2addr_node *node; | |
744 | struct vport_addr *addr; | |
745 | struct hlist_node *tmp; | |
746 | int hi; | |
747 | ||
748 | for_each_l2hash_node(node, tmp, vport->uc_list, hi) { | |
749 | addr = container_of(node, struct vport_addr, node); | |
750 | addr->action = MLX5_ACTION_DEL; | |
751 | } | |
752 | esw_apply_vport_addr_list(esw, vport_num, MLX5_NVPRT_LIST_TYPE_UC); | |
753 | ||
754 | for_each_l2hash_node(node, tmp, vport->mc_list, hi) { | |
755 | addr = container_of(node, struct vport_addr, node); | |
756 | addr->action = MLX5_ACTION_DEL; | |
757 | } | |
758 | esw_apply_vport_addr_list(esw, vport_num, MLX5_NVPRT_LIST_TYPE_MC); | |
073bb189 SM |
759 | } |
760 | ||
761 | static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num) | |
762 | { | |
763 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
764 | unsigned long flags; | |
765 | ||
766 | if (!vport->enabled) | |
767 | return; | |
768 | ||
81848731 | 769 | esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num); |
073bb189 SM |
770 | /* Mark this vport as disabled to discard new events */ |
771 | spin_lock_irqsave(&vport->lock, flags); | |
772 | vport->enabled = false; | |
81848731 | 773 | vport->enabled_events = 0; |
073bb189 SM |
774 | spin_unlock_irqrestore(&vport->lock, flags); |
775 | ||
81848731 SM |
776 | mlx5_modify_vport_admin_state(esw->dev, |
777 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
778 | vport_num, | |
779 | MLX5_ESW_VPORT_ADMIN_STATE_DOWN); | |
073bb189 SM |
780 | /* Wait for current already scheduled events to complete */ |
781 | flush_workqueue(esw->work_queue); | |
073bb189 SM |
782 | /* Disable events from this vport */ |
783 | arm_vport_context_events_cmd(esw->dev, vport->vport, 0); | |
81848731 SM |
784 | /* We don't assume VFs will cleanup after themselves */ |
785 | esw_cleanup_vport(esw, vport_num); | |
786 | esw->enabled_vports--; | |
073bb189 SM |
787 | } |
788 | ||
789 | /* Public E-Switch API */ | |
81848731 SM |
790 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs) |
791 | { | |
792 | int err; | |
793 | int i; | |
794 | ||
795 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
796 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
797 | return 0; | |
798 | ||
799 | if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) || | |
800 | !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) { | |
801 | esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n"); | |
802 | return -ENOTSUPP; | |
803 | } | |
804 | ||
805 | esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d)\n", nvfs); | |
806 | ||
807 | esw_disable_vport(esw, 0); | |
808 | ||
809 | err = esw_create_fdb_table(esw, nvfs + 1); | |
810 | if (err) | |
811 | goto abort; | |
812 | ||
813 | for (i = 0; i <= nvfs; i++) | |
814 | esw_enable_vport(esw, i, SRIOV_VPORT_EVENTS); | |
815 | ||
816 | esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n", | |
817 | esw->enabled_vports); | |
818 | return 0; | |
819 | ||
820 | abort: | |
821 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
822 | return err; | |
823 | } | |
824 | ||
825 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) | |
826 | { | |
827 | int i; | |
828 | ||
829 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
830 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
831 | return; | |
832 | ||
833 | esw_info(esw->dev, "disable SRIOV: active vports(%d)\n", | |
834 | esw->enabled_vports); | |
835 | ||
836 | for (i = 0; i < esw->total_vports; i++) | |
837 | esw_disable_vport(esw, i); | |
838 | ||
839 | esw_destroy_fdb_table(esw); | |
840 | ||
841 | /* VPORT 0 (PF) must be enabled back with non-sriov configuration */ | |
842 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
843 | } | |
844 | ||
073bb189 SM |
845 | int mlx5_eswitch_init(struct mlx5_core_dev *dev) |
846 | { | |
847 | int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table); | |
848 | int total_vports = 1 + pci_sriov_get_totalvfs(dev->pdev); | |
849 | struct mlx5_eswitch *esw; | |
850 | int vport_num; | |
851 | int err; | |
852 | ||
853 | if (!MLX5_CAP_GEN(dev, vport_group_manager) || | |
854 | MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
855 | return 0; | |
856 | ||
857 | esw_info(dev, | |
858 | "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n", | |
859 | total_vports, l2_table_size, | |
860 | MLX5_MAX_UC_PER_VPORT(dev), | |
861 | MLX5_MAX_MC_PER_VPORT(dev)); | |
862 | ||
863 | esw = kzalloc(sizeof(*esw), GFP_KERNEL); | |
864 | if (!esw) | |
865 | return -ENOMEM; | |
866 | ||
867 | esw->dev = dev; | |
868 | ||
869 | esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size), | |
870 | sizeof(uintptr_t), GFP_KERNEL); | |
871 | if (!esw->l2_table.bitmap) { | |
872 | err = -ENOMEM; | |
873 | goto abort; | |
874 | } | |
875 | esw->l2_table.size = l2_table_size; | |
876 | ||
877 | esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq"); | |
878 | if (!esw->work_queue) { | |
879 | err = -ENOMEM; | |
880 | goto abort; | |
881 | } | |
882 | ||
883 | esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport), | |
884 | GFP_KERNEL); | |
885 | if (!esw->vports) { | |
886 | err = -ENOMEM; | |
887 | goto abort; | |
888 | } | |
889 | ||
073bb189 SM |
890 | for (vport_num = 0; vport_num < total_vports; vport_num++) { |
891 | struct mlx5_vport *vport = &esw->vports[vport_num]; | |
892 | ||
893 | vport->vport = vport_num; | |
894 | vport->dev = dev; | |
895 | INIT_WORK(&vport->vport_change_handler, | |
896 | esw_vport_change_handler); | |
897 | spin_lock_init(&vport->lock); | |
898 | } | |
899 | ||
81848731 SM |
900 | esw->total_vports = total_vports; |
901 | esw->enabled_vports = 0; | |
073bb189 | 902 | |
81848731 SM |
903 | dev->priv.eswitch = esw; |
904 | esw_enable_vport(esw, 0, UC_ADDR_CHANGE); | |
073bb189 SM |
905 | /* VF Vports will be enabled when SRIOV is enabled */ |
906 | return 0; | |
907 | abort: | |
908 | if (esw->work_queue) | |
909 | destroy_workqueue(esw->work_queue); | |
910 | kfree(esw->l2_table.bitmap); | |
911 | kfree(esw->vports); | |
912 | kfree(esw); | |
913 | return err; | |
914 | } | |
915 | ||
916 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) | |
917 | { | |
918 | if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) || | |
919 | MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
920 | return; | |
921 | ||
922 | esw_info(esw->dev, "cleanup\n"); | |
923 | esw_disable_vport(esw, 0); | |
924 | ||
925 | esw->dev->priv.eswitch = NULL; | |
926 | destroy_workqueue(esw->work_queue); | |
927 | kfree(esw->l2_table.bitmap); | |
928 | kfree(esw->vports); | |
929 | kfree(esw); | |
930 | } | |
931 | ||
932 | void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) | |
933 | { | |
934 | struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change; | |
935 | u16 vport_num = be16_to_cpu(vc_eqe->vport_num); | |
936 | struct mlx5_vport *vport; | |
937 | ||
938 | if (!esw) { | |
939 | pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n", | |
940 | vport_num); | |
941 | return; | |
942 | } | |
943 | ||
944 | vport = &esw->vports[vport_num]; | |
945 | spin_lock(&vport->lock); | |
946 | if (vport->enabled) | |
947 | queue_work(esw->work_queue, &vport->vport_change_handler); | |
948 | spin_unlock(&vport->lock); | |
949 | } | |
77256579 SM |
950 | |
951 | /* Vport Administration */ | |
952 | #define ESW_ALLOWED(esw) \ | |
953 | (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev)) | |
954 | #define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports) | |
955 | ||
956 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, | |
957 | int vport, u8 mac[ETH_ALEN]) | |
958 | { | |
959 | int err = 0; | |
960 | ||
961 | if (!ESW_ALLOWED(esw)) | |
962 | return -EPERM; | |
963 | if (!LEGAL_VPORT(esw, vport)) | |
964 | return -EINVAL; | |
965 | ||
966 | err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac); | |
967 | if (err) { | |
968 | mlx5_core_warn(esw->dev, | |
969 | "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n", | |
970 | vport, err); | |
971 | return err; | |
972 | } | |
973 | ||
974 | return err; | |
975 | } | |
976 | ||
977 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
978 | int vport, int link_state) | |
979 | { | |
980 | if (!ESW_ALLOWED(esw)) | |
981 | return -EPERM; | |
982 | if (!LEGAL_VPORT(esw, vport)) | |
983 | return -EINVAL; | |
984 | ||
985 | return mlx5_modify_vport_admin_state(esw->dev, | |
986 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
987 | vport, link_state); | |
988 | } | |
989 | ||
990 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, | |
991 | int vport, struct ifla_vf_info *ivi) | |
992 | { | |
9e7ea352 SM |
993 | u16 vlan; |
994 | u8 qos; | |
995 | ||
77256579 SM |
996 | if (!ESW_ALLOWED(esw)) |
997 | return -EPERM; | |
998 | if (!LEGAL_VPORT(esw, vport)) | |
999 | return -EINVAL; | |
1000 | ||
1001 | memset(ivi, 0, sizeof(*ivi)); | |
1002 | ivi->vf = vport - 1; | |
1003 | ||
1004 | mlx5_query_nic_vport_mac_address(esw->dev, vport, ivi->mac); | |
1005 | ivi->linkstate = mlx5_query_vport_admin_state(esw->dev, | |
1006 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT, | |
1007 | vport); | |
9e7ea352 SM |
1008 | query_esw_vport_cvlan(esw->dev, vport, &vlan, &qos); |
1009 | ivi->vlan = vlan; | |
1010 | ivi->qos = qos; | |
77256579 SM |
1011 | ivi->spoofchk = 0; |
1012 | ||
1013 | return 0; | |
1014 | } | |
9e7ea352 SM |
1015 | |
1016 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
1017 | int vport, u16 vlan, u8 qos) | |
1018 | { | |
1019 | int set = 0; | |
1020 | ||
1021 | if (!ESW_ALLOWED(esw)) | |
1022 | return -EPERM; | |
1023 | if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7)) | |
1024 | return -EINVAL; | |
1025 | ||
1026 | if (vlan || qos) | |
1027 | set = 1; | |
1028 | ||
1029 | return modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set); | |
1030 | } | |
3b751a2a SM |
1031 | |
1032 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, | |
1033 | int vport, | |
1034 | struct ifla_vf_stats *vf_stats) | |
1035 | { | |
1036 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
1037 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; | |
1038 | int err = 0; | |
1039 | u32 *out; | |
1040 | ||
1041 | if (!ESW_ALLOWED(esw)) | |
1042 | return -EPERM; | |
1043 | if (!LEGAL_VPORT(esw, vport)) | |
1044 | return -EINVAL; | |
1045 | ||
1046 | out = mlx5_vzalloc(outlen); | |
1047 | if (!out) | |
1048 | return -ENOMEM; | |
1049 | ||
1050 | memset(in, 0, sizeof(in)); | |
1051 | ||
1052 | MLX5_SET(query_vport_counter_in, in, opcode, | |
1053 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
1054 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
1055 | MLX5_SET(query_vport_counter_in, in, vport_number, vport); | |
1056 | if (vport) | |
1057 | MLX5_SET(query_vport_counter_in, in, other_vport, 1); | |
1058 | ||
1059 | memset(out, 0, outlen); | |
1060 | err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen); | |
1061 | if (err) | |
1062 | goto free_out; | |
1063 | ||
1064 | #define MLX5_GET_CTR(p, x) \ | |
1065 | MLX5_GET64(query_vport_counter_out, p, x) | |
1066 | ||
1067 | memset(vf_stats, 0, sizeof(*vf_stats)); | |
1068 | vf_stats->rx_packets = | |
1069 | MLX5_GET_CTR(out, received_eth_unicast.packets) + | |
1070 | MLX5_GET_CTR(out, received_eth_multicast.packets) + | |
1071 | MLX5_GET_CTR(out, received_eth_broadcast.packets); | |
1072 | ||
1073 | vf_stats->rx_bytes = | |
1074 | MLX5_GET_CTR(out, received_eth_unicast.octets) + | |
1075 | MLX5_GET_CTR(out, received_eth_multicast.octets) + | |
1076 | MLX5_GET_CTR(out, received_eth_broadcast.octets); | |
1077 | ||
1078 | vf_stats->tx_packets = | |
1079 | MLX5_GET_CTR(out, transmitted_eth_unicast.packets) + | |
1080 | MLX5_GET_CTR(out, transmitted_eth_multicast.packets) + | |
1081 | MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); | |
1082 | ||
1083 | vf_stats->tx_bytes = | |
1084 | MLX5_GET_CTR(out, transmitted_eth_unicast.octets) + | |
1085 | MLX5_GET_CTR(out, transmitted_eth_multicast.octets) + | |
1086 | MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); | |
1087 | ||
1088 | vf_stats->multicast = | |
1089 | MLX5_GET_CTR(out, received_eth_multicast.packets); | |
1090 | ||
1091 | vf_stats->broadcast = | |
1092 | MLX5_GET_CTR(out, received_eth_broadcast.packets); | |
1093 | ||
1094 | free_out: | |
1095 | kvfree(out); | |
1096 | return err; | |
1097 | } |