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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
feae9087 | 39 | #include <net/devlink.h> |
073bb189 | 40 | #include <linux/mlx5/device.h> |
57cbd893 | 41 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 42 | #include <linux/mlx5/vport.h> |
cc495188 | 43 | #include <linux/mlx5/fs.h> |
eeb66cdb | 44 | #include "lib/mpfs.h" |
073bb189 | 45 | |
e80541ec SM |
46 | #ifdef CONFIG_MLX5_ESWITCH |
47 | ||
073bb189 SM |
48 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
49 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
50 | ||
51 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
52 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
53 | ||
c9497c98 MHY |
54 | #define MLX5_MIN_BW_SHARE 1 |
55 | ||
56 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
57 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
58 | ||
a842dd04 CM |
59 | #define mlx5_esw_has_fwd_fdb(dev) \ |
60 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
61 | ||
328edb49 | 62 | #define FDB_MAX_CHAIN 3 |
c92a0b94 | 63 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
64 | #define FDB_MAX_PRIO 16 |
65 | ||
5742df0f MHY |
66 | struct vport_ingress { |
67 | struct mlx5_flow_table *acl; | |
10652f39 | 68 | struct mlx5_flow_handle *allow_rule; |
853b5352 | 69 | struct { |
10652f39 PP |
70 | struct mlx5_flow_group *allow_spoofchk_only_grp; |
71 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
72 | struct mlx5_flow_group *allow_untagged_only_grp; | |
73 | struct mlx5_flow_group *drop_grp; | |
853b5352 PP |
74 | struct mlx5_flow_handle *drop_rule; |
75 | struct mlx5_fc *drop_counter; | |
76 | } legacy; | |
d68316b5 | 77 | struct { |
10652f39 | 78 | struct mlx5_flow_group *metadata_grp; |
d68316b5 PP |
79 | struct mlx5_modify_hdr *modify_metadata; |
80 | struct mlx5_flow_handle *modify_metadata_rule; | |
81 | } offloads; | |
5742df0f MHY |
82 | }; |
83 | ||
84 | struct vport_egress { | |
85 | struct mlx5_flow_table *acl; | |
86 | struct mlx5_flow_group *allowed_vlans_grp; | |
87 | struct mlx5_flow_group *drop_grp; | |
74491de9 | 88 | struct mlx5_flow_handle *allowed_vlan; |
853b5352 PP |
89 | struct { |
90 | struct mlx5_flow_handle *drop_rule; | |
91 | struct mlx5_fc *drop_counter; | |
92 | } legacy; | |
b8a0dbe3 EE |
93 | }; |
94 | ||
95 | struct mlx5_vport_drop_stats { | |
96 | u64 rx_dropped; | |
97 | u64 tx_dropped; | |
5742df0f MHY |
98 | }; |
99 | ||
1ab2068a MHY |
100 | struct mlx5_vport_info { |
101 | u8 mac[ETH_ALEN]; | |
102 | u16 vlan; | |
103 | u8 qos; | |
104 | u64 node_guid; | |
105 | int link_state; | |
c9497c98 | 106 | u32 min_rate; |
1bd27b11 | 107 | u32 max_rate; |
1ab2068a MHY |
108 | bool spoofchk; |
109 | bool trusted; | |
110 | }; | |
111 | ||
5019833d PP |
112 | /* Vport context events */ |
113 | enum mlx5_eswitch_vport_event { | |
114 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
115 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
116 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
117 | }; | |
118 | ||
073bb189 SM |
119 | struct mlx5_vport { |
120 | struct mlx5_core_dev *dev; | |
121 | int vport; | |
122 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 123 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
124 | struct mlx5_flow_handle *promisc_rule; |
125 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
126 | struct work_struct vport_change_handler; |
127 | ||
5742df0f MHY |
128 | struct vport_ingress ingress; |
129 | struct vport_egress egress; | |
130 | ||
1ab2068a MHY |
131 | struct mlx5_vport_info info; |
132 | ||
1bd27b11 MHY |
133 | struct { |
134 | bool enabled; | |
135 | u32 esw_tsar_ix; | |
c9497c98 | 136 | u32 bw_share; |
1bd27b11 MHY |
137 | } qos; |
138 | ||
073bb189 | 139 | bool enabled; |
5019833d | 140 | enum mlx5_eswitch_vport_event enabled_events; |
073bb189 SM |
141 | }; |
142 | ||
e52c2802 PB |
143 | enum offloads_fdb_flags { |
144 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
145 | }; | |
146 | ||
147 | extern const unsigned int ESW_POOLS[4]; | |
148 | ||
149 | #define PRIO_LEVELS 2 | |
81848731 | 150 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
151 | union { |
152 | struct legacy_fdb { | |
52fff327 | 153 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
154 | struct mlx5_flow_group *addr_grp; |
155 | struct mlx5_flow_group *allmulti_grp; | |
156 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
157 | struct mlx5_flow_table *vepa_fdb; |
158 | struct mlx5_flow_handle *vepa_uplink_rule; | |
159 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 160 | } legacy; |
69697b6e OG |
161 | |
162 | struct offloads_fdb { | |
8463daf1 | 163 | struct mlx5_flow_namespace *ns; |
52fff327 | 164 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 165 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
166 | struct mlx5_flow_group *peer_miss_grp; |
167 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 168 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
169 | struct mlx5_flow_handle *miss_rule_uni; |
170 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 171 | int vlan_push_pop_refcount; |
e52c2802 PB |
172 | |
173 | struct { | |
174 | struct mlx5_flow_table *fdb; | |
175 | u32 num_rules; | |
176 | } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; | |
177 | /* Protects fdb_prio table */ | |
178 | struct mutex fdb_prio_lock; | |
179 | ||
180 | int fdb_left[ARRAY_SIZE(ESW_POOLS)]; | |
69697b6e | 181 | } offloads; |
6ab36e35 | 182 | }; |
e52c2802 | 183 | u32 flags; |
6ab36e35 OG |
184 | }; |
185 | ||
c116c6ee OG |
186 | struct mlx5_esw_offload { |
187 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 188 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 189 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
190 | struct list_head peer_flows; |
191 | struct mutex peer_mutex; | |
61086f39 | 192 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 193 | DECLARE_HASHTABLE(encap_tbl, 8); |
dd58edc3 | 194 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
195 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
196 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
8693115a | 197 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 198 | u8 inline_mode; |
525e84be | 199 | atomic64_t num_flows; |
98fdbea5 | 200 | enum devlink_eswitch_encap_mode encap; |
c116c6ee OG |
201 | }; |
202 | ||
0a0ab1d2 EC |
203 | /* E-Switch MC FDB table hash node */ |
204 | struct esw_mc_addr { /* SRIOV only */ | |
205 | struct l2addr_node node; | |
206 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
207 | u32 refcnt; | |
208 | }; | |
209 | ||
a3888f33 BW |
210 | struct mlx5_host_work { |
211 | struct work_struct work; | |
212 | struct mlx5_eswitch *esw; | |
213 | }; | |
214 | ||
cd56f929 | 215 | struct mlx5_esw_functions { |
a3888f33 BW |
216 | struct mlx5_nb nb; |
217 | u16 num_vfs; | |
218 | }; | |
219 | ||
7445cfb1 JL |
220 | enum { |
221 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
222 | }; | |
223 | ||
073bb189 SM |
224 | struct mlx5_eswitch { |
225 | struct mlx5_core_dev *dev; | |
6933a937 | 226 | struct mlx5_nb nb; |
81848731 | 227 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 228 | /* legacy data structures */ |
81848731 | 229 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
230 | struct esw_mc_addr mc_promisc; |
231 | /* end of legacy */ | |
073bb189 SM |
232 | struct workqueue_struct *work_queue; |
233 | struct mlx5_vport *vports; | |
7445cfb1 | 234 | u32 flags; |
073bb189 | 235 | int total_vports; |
81848731 | 236 | int enabled_vports; |
dfcb1ed3 MHY |
237 | /* Synchronize between vport change events |
238 | * and async SRIOV admin state changes | |
239 | */ | |
240 | struct mutex state_lock; | |
1bd27b11 MHY |
241 | |
242 | struct { | |
243 | bool enabled; | |
244 | u32 root_tsar_id; | |
245 | } qos; | |
246 | ||
c116c6ee | 247 | struct mlx5_esw_offload offloads; |
6ab36e35 | 248 | int mode; |
e52c2802 | 249 | int nvports; |
a1b3839a | 250 | u16 manager_vport; |
411ec9e0 | 251 | u16 first_host_vport; |
cd56f929 | 252 | struct mlx5_esw_functions esw_funcs; |
073bb189 SM |
253 | }; |
254 | ||
5896b972 PP |
255 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
256 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
e8d31c4d MB |
257 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
258 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
18486737 EB |
259 | void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw, |
260 | struct mlx5_vport *vport); | |
10652f39 PP |
261 | int esw_vport_create_ingress_acl_table(struct mlx5_eswitch *esw, |
262 | struct mlx5_vport *vport, | |
263 | int table_size); | |
264 | void esw_vport_destroy_ingress_acl_table(struct mlx5_vport *vport); | |
18486737 EB |
265 | void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw, |
266 | struct mlx5_vport *vport); | |
267 | int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw, | |
268 | struct mlx5_vport *vport); | |
269 | void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw, | |
270 | struct mlx5_vport *vport); | |
fcb64c0f EC |
271 | int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, |
272 | u32 rate_mbps); | |
766a0e97 | 273 | |
073bb189 SM |
274 | /* E-Switch API */ |
275 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
276 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
062f4bf4 | 277 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode); |
f6455de0 | 278 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw); |
77256579 | 279 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
02f3afd9 | 280 | u16 vport, u8 mac[ETH_ALEN]); |
77256579 | 281 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 282 | u16 vport, int link_state); |
9e7ea352 | 283 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 284 | u16 vport, u16 vlan, u8 qos); |
f942380c | 285 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 286 | u16 vport, bool spoofchk); |
1edc57e2 | 287 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
288 | u16 vport_num, bool setting); |
289 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 290 | u32 max_rate, u32 min_rate); |
8da202b2 HN |
291 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
292 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 293 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 294 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 295 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 296 | u16 vport, |
3b751a2a | 297 | struct ifla_vf_stats *vf_stats); |
159fe639 | 298 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 299 | |
57843868 JL |
300 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport, |
301 | void *in, int inlen); | |
302 | int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport, | |
303 | void *out, int outlen); | |
304 | ||
3d80d1a2 | 305 | struct mlx5_flow_spec; |
776b12b6 | 306 | struct mlx5_esw_flow_attr; |
10caabda OS |
307 | struct mlx5_termtbl_handle; |
308 | ||
309 | bool | |
310 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
311 | struct mlx5_flow_act *flow_act, | |
312 | struct mlx5_flow_spec *spec); | |
313 | ||
314 | struct mlx5_flow_handle * | |
315 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
316 | struct mlx5_flow_table *ft, | |
317 | struct mlx5_flow_spec *spec, | |
318 | struct mlx5_esw_flow_attr *attr, | |
319 | struct mlx5_flow_act *flow_act, | |
320 | struct mlx5_flow_destination *dest, | |
321 | int num_dest); | |
322 | ||
323 | void | |
324 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
325 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 326 | |
74491de9 | 327 | struct mlx5_flow_handle * |
3d80d1a2 OG |
328 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
329 | struct mlx5_flow_spec *spec, | |
776b12b6 | 330 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
331 | struct mlx5_flow_handle * |
332 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
333 | struct mlx5_flow_spec *spec, | |
334 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
335 | void |
336 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
337 | struct mlx5_flow_handle *rule, | |
338 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
339 | void |
340 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
341 | struct mlx5_flow_handle *rule, | |
342 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 343 | |
e52c2802 PB |
344 | bool |
345 | mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); | |
346 | ||
347 | u16 | |
348 | mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); | |
349 | ||
350 | u32 | |
351 | mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); | |
352 | ||
74491de9 | 353 | struct mlx5_flow_handle * |
02f3afd9 | 354 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 355 | struct mlx5_flow_destination *dest); |
fed9ce22 | 356 | |
e33dfe31 OG |
357 | enum { |
358 | SET_VLAN_STRIP = BIT(0), | |
359 | SET_VLAN_INSERT = BIT(1) | |
360 | }; | |
361 | ||
d708f902 OG |
362 | enum mlx5_flow_match_level { |
363 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
364 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
365 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
366 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
367 | }; | |
368 | ||
592d3651 CM |
369 | /* current maximum for flow based vport multicasting */ |
370 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
371 | ||
f493f155 EB |
372 | enum { |
373 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 374 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
375 | }; |
376 | ||
776b12b6 OG |
377 | struct mlx5_esw_flow_attr { |
378 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 379 | struct mlx5_core_dev *in_mdev; |
f9392795 | 380 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 381 | |
e85e02ba | 382 | int split_count; |
592d3651 CM |
383 | int out_count; |
384 | ||
776b12b6 | 385 | int action; |
cc495188 JL |
386 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
387 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
388 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
389 | u8 total_vlan; | |
f5f82476 | 390 | bool vlan_handled; |
df65a573 | 391 | struct { |
f493f155 | 392 | u32 flags; |
df65a573 | 393 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 394 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 395 | struct mlx5_core_dev *mdev; |
10caabda | 396 | struct mlx5_termtbl_handle *termtbl; |
df65a573 | 397 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
2b688ea5 | 398 | struct mlx5_modify_hdr *modify_hdr; |
93b3586e HN |
399 | u8 inner_match_level; |
400 | u8 outer_match_level; | |
b8aee822 | 401 | struct mlx5_fc *counter; |
e52c2802 PB |
402 | u32 chain; |
403 | u16 prio; | |
404 | u32 dest_chain; | |
232c0013 | 405 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
406 | }; |
407 | ||
db7ff19e EB |
408 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
409 | struct netlink_ext_ack *extack); | |
feae9087 | 410 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
411 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
412 | struct netlink_ext_ack *extack); | |
bffaa916 | 413 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
062f4bf4 | 414 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode); |
98fdbea5 LR |
415 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
416 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 417 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
418 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
419 | enum devlink_eswitch_encap_mode *encap); | |
a4b97ab4 | 420 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 421 | |
f5f82476 OG |
422 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
423 | struct mlx5_esw_flow_attr *attr); | |
424 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
425 | struct mlx5_esw_flow_attr *attr); | |
426 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
02f3afd9 | 427 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 428 | |
fdde49e0 PP |
429 | int mlx5_esw_create_vport_egress_acl_vlan(struct mlx5_eswitch *esw, |
430 | struct mlx5_vport *vport, | |
431 | u16 vlan_id, u32 flow_action); | |
432 | ||
cc495188 JL |
433 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
434 | u8 vlan_depth) | |
6acfbf38 | 435 | { |
cc495188 JL |
436 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
437 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
438 | ||
439 | if (vlan_depth == 1) | |
440 | return ret; | |
441 | ||
442 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
443 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
444 | } |
445 | ||
eff849b2 RL |
446 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
447 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
448 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
449 | struct mlx5_core_dev *dev1); | |
eff849b2 | 450 | |
dd28087c | 451 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 452 | |
69697b6e OG |
453 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
454 | ||
27b942fb PP |
455 | #define esw_info(__dev, format, ...) \ |
456 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 457 | |
27b942fb PP |
458 | #define esw_warn(__dev, format, ...) \ |
459 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
460 | |
461 | #define esw_debug(dev, format, ...) \ | |
462 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
463 | |
464 | /* The returned number is valid only when the dev is eswitch manager. */ | |
465 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
466 | { | |
467 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
468 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
469 | } | |
470 | ||
ea2300e0 PP |
471 | static inline bool |
472 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
473 | { | |
474 | return esw->manager_vport == vport_num; | |
475 | } | |
476 | ||
411ec9e0 BW |
477 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
478 | { | |
479 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
480 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
481 | } | |
482 | ||
6706a3b9 VP |
483 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) |
484 | { | |
485 | /* Ideally device should have the functions changed supported | |
486 | * capability regardless of it being ECPF or PF wherever such | |
487 | * event should be processed such as on eswitch manager device. | |
488 | * However, some ECPF based device might not have this capability | |
489 | * set. Hence OR for ECPF check to cover such device. | |
490 | */ | |
491 | return MLX5_CAP_ESW(dev, esw_functions_changed) || | |
492 | mlx5_core_is_ecpf_esw_manager(dev); | |
493 | } | |
494 | ||
5ae51620 BW |
495 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
496 | { | |
497 | /* Uplink always locate at the last element of the array.*/ | |
498 | return esw->total_vports - 1; | |
499 | } | |
500 | ||
81cd229c BW |
501 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
502 | { | |
503 | return esw->total_vports - 2; | |
504 | } | |
505 | ||
5ae51620 BW |
506 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
507 | u16 vport_num) | |
508 | { | |
81cd229c BW |
509 | if (vport_num == MLX5_VPORT_ECPF) { |
510 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
511 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
512 | return mlx5_eswitch_ecpf_idx(esw); | |
513 | } | |
514 | ||
5ae51620 BW |
515 | if (vport_num == MLX5_VPORT_UPLINK) |
516 | return mlx5_eswitch_uplink_idx(esw); | |
517 | ||
518 | return vport_num; | |
519 | } | |
520 | ||
02f3afd9 | 521 | static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, |
5ae51620 BW |
522 | int index) |
523 | { | |
81cd229c BW |
524 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
525 | mlx5_ecpf_vport_exists(esw->dev)) | |
526 | return MLX5_VPORT_ECPF; | |
527 | ||
5ae51620 BW |
528 | if (index == mlx5_eswitch_uplink_idx(esw)) |
529 | return MLX5_VPORT_UPLINK; | |
530 | ||
531 | return index; | |
532 | } | |
533 | ||
ee576ec1 SM |
534 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
535 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
536 | ||
786ef904 PP |
537 | /* The vport getter/iterator are only valid after esw->total_vports |
538 | * and vport->vport are initialized in mlx5_eswitch_init. | |
539 | */ | |
540 | #define mlx5_esw_for_all_vports(esw, i, vport) \ | |
541 | for ((i) = MLX5_VPORT_PF; \ | |
542 | (vport) = &(esw)->vports[i], \ | |
543 | (i) < (esw)->total_vports; (i)++) | |
544 | ||
5019833d PP |
545 | #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \ |
546 | for ((i) = (esw)->total_vports - 1; \ | |
547 | (vport) = &(esw)->vports[i], \ | |
548 | (i) >= MLX5_VPORT_PF; (i)--) | |
549 | ||
786ef904 PP |
550 | #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \ |
551 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
552 | (vport) = &(esw)->vports[(i)], \ | |
553 | (i) <= (nvfs); (i)++) | |
554 | ||
555 | #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \ | |
556 | for ((i) = (nvfs); \ | |
557 | (vport) = &(esw)->vports[(i)], \ | |
558 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
559 | ||
560 | /* The rep getter/iterator are only valid after esw->total_vports | |
561 | * and vport->vport are initialized in mlx5_eswitch_init. | |
562 | */ | |
563 | #define mlx5_esw_for_all_reps(esw, i, rep) \ | |
564 | for ((i) = MLX5_VPORT_PF; \ | |
565 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
566 | (i) < (esw)->total_vports; (i)++) | |
567 | ||
568 | #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \ | |
569 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
570 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
571 | (i) <= (nvfs); (i)++) | |
572 | ||
573 | #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \ | |
574 | for ((i) = (nvfs); \ | |
575 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
576 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
577 | ||
578 | #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \ | |
579 | for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++) | |
580 | ||
581 | #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \ | |
582 | for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--) | |
583 | ||
411ec9e0 BW |
584 | /* Includes host PF (vport 0) if it's not esw manager. */ |
585 | #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \ | |
586 | for ((i) = (esw)->first_host_vport; \ | |
587 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
588 | (i) <= (nvfs); (i)++) | |
589 | ||
590 | #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \ | |
591 | for ((i) = (nvfs); \ | |
592 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
593 | (i) >= (esw)->first_host_vport; (i)--) | |
594 | ||
595 | #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \ | |
596 | for ((vport) = (esw)->first_host_vport; \ | |
597 | (vport) <= (nvfs); (vport)++) | |
598 | ||
599 | #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \ | |
600 | for ((vport) = (nvfs); \ | |
601 | (vport) >= (esw)->first_host_vport; (vport)--) | |
602 | ||
5d9986a3 BW |
603 | struct mlx5_vport *__must_check |
604 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
605 | ||
91d6291c PP |
606 | bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num); |
607 | ||
062f4bf4 | 608 | void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs); |
16fff98a | 609 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 610 | |
925a6acc | 611 | int |
5019833d PP |
612 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, |
613 | enum mlx5_eswitch_vport_event enabled_events); | |
614 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
615 | ||
748da30b VP |
616 | int |
617 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, | |
618 | struct mlx5_vport *vport); | |
619 | void | |
620 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, | |
621 | struct mlx5_vport *vport); | |
622 | ||
e80541ec SM |
623 | #else /* CONFIG_MLX5_ESWITCH */ |
624 | /* eswitch API stubs */ | |
625 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
626 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
062f4bf4 | 627 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; } |
f6455de0 | 628 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} |
eff849b2 | 629 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 630 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
dd28087c | 631 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 632 | { |
dd28087c | 633 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 634 | } |
328edb49 | 635 | |
062f4bf4 BW |
636 | static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {} |
637 | ||
328edb49 | 638 | #define FDB_MAX_CHAIN 1 |
c92a0b94 | 639 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
640 | #define FDB_MAX_PRIO 1 |
641 | ||
e80541ec SM |
642 | #endif /* CONFIG_MLX5_ESWITCH */ |
643 | ||
073bb189 | 644 | #endif /* __MLX5_ESWITCH_H__ */ |