[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.h

/*
 * Copyright (c) 2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_ESWITCH_H__
#define __MLX5_ESWITCH_H__

#include <linux/if_ether.h>
#include <linux/if_link.h>
#include <net/devlink.h>
#include <linux/mlx5/device.h>
#include <linux/mlx5/eswitch.h>
#include <linux/mlx5/fs.h>
#include "lib/mpfs.h"

#ifdef CONFIG_MLX5_ESWITCH

#define MLX5_MAX_UC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))

#define MLX5_MAX_MC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))

#define FDB_UPLINK_VPORT 0xffff

#define MLX5_MIN_BW_SHARE 1

#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)

#define mlx5_esw_has_fwd_fdb(dev) \
	MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)

#define FDB_MAX_CHAIN 3
#define FDB_MAX_PRIO 16

struct vport_ingress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	struct mlx5_flow_group *allow_spoofchk_only_grp;
	struct mlx5_flow_group *allow_untagged_only_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allow_rule;
	struct mlx5_flow_handle  *drop_rule;
	struct mlx5_fc           *drop_counter;
};

struct vport_egress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allowed_vlans_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allowed_vlan;
	struct mlx5_flow_handle  *drop_rule;
	struct mlx5_fc           *drop_counter;
};

struct mlx5_vport_drop_stats {
	u64 rx_dropped;
	u64 tx_dropped;
};

struct mlx5_vport_info {
	u8                      mac[ETH_ALEN];
	u16                     vlan;
	u8                      qos;
	u64                     node_guid;
	int                     link_state;
	u32                     min_rate;
	u32                     max_rate;
	bool                    spoofchk;
	bool                    trusted;
};

struct mlx5_vport {
	struct mlx5_core_dev    *dev;
	int                     vport;
	struct hlist_head       uc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct hlist_head       mc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct mlx5_flow_handle *promisc_rule;
	struct mlx5_flow_handle *allmulti_rule;
	struct work_struct      vport_change_handler;

	struct vport_ingress    ingress;
	struct vport_egress     egress;

	struct mlx5_vport_info  info;

	struct {
		bool            enabled;
		u32             esw_tsar_ix;
		u32             bw_share;
	} qos;

	bool                    enabled;
	u16                     enabled_events;
};

struct mlx5_eswitch_fdb {
	union {
		struct legacy_fdb {
			struct mlx5_flow_table *fdb;
			struct mlx5_flow_group *addr_grp;
			struct mlx5_flow_group *allmulti_grp;
			struct mlx5_flow_group *promisc_grp;
		} legacy;

		struct offloads_fdb {
			struct mlx5_flow_table *fast_fdb;
			struct mlx5_flow_table *fwd_fdb;
			struct mlx5_flow_table *slow_fdb;
			struct mlx5_flow_group *send_to_vport_grp;
			struct mlx5_flow_group *miss_grp;
			struct mlx5_flow_handle *miss_rule_uni;
			struct mlx5_flow_handle *miss_rule_multi;
			int vlan_push_pop_refcount;
		} offloads;
	};
};

struct mlx5_esw_offload {
	struct mlx5_flow_table *ft_offloads;
	struct mlx5_flow_group *vport_rx_group;
	struct mlx5_eswitch_rep *vport_reps;
	DECLARE_HASHTABLE(encap_tbl, 8);
	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
	u8 inline_mode;
	u64 num_flows;
	u8 encap;
};

/* E-Switch MC FDB table hash node */
struct esw_mc_addr { /* SRIOV only */
	struct l2addr_node     node;
	struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
	u32                    refcnt;
};

struct mlx5_eswitch {
	struct mlx5_core_dev    *dev;
	struct mlx5_eswitch_fdb fdb_table;
	struct hlist_head       mc_table[MLX5_L2_ADDR_HASH_SIZE];
	struct workqueue_struct *work_queue;
	struct mlx5_vport       *vports;
	int                     total_vports;
	int                     enabled_vports;
	/* Synchronize between vport change events
	 * and async SRIOV admin state changes
	 */
	struct mutex            state_lock;
	struct esw_mc_addr	mc_promisc;

	struct {
		bool            enabled;
		u32             root_tsar_id;
	} qos;

	struct mlx5_esw_offload offloads;
	int                     mode;
};

void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
int esw_offloads_init_reps(struct mlx5_eswitch *esw);

/* E-Switch API */
int mlx5_eswitch_init(struct mlx5_core_dev *dev);
void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe);
int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
			       int vport, u8 mac[ETH_ALEN]);
int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
				 int vport, int link_state);
int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				int vport, u16 vlan, u8 qos);
int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
				    int vport, bool spoofchk);
int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
				 int vport_num, bool setting);
int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
				u32 max_rate, u32 min_rate);
int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
				  int vport, struct ifla_vf_info *ivi);
int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
				 int vport,
				 struct ifla_vf_stats *vf_stats);
void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);

struct mlx5_flow_spec;
struct mlx5_esw_flow_attr;

struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_spec *spec,
				struct mlx5_esw_flow_attr *attr);
struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_spec *spec,
			  struct mlx5_esw_flow_attr *attr);
void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_handle *rule,
				struct mlx5_esw_flow_attr *attr);

struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
				  struct mlx5_flow_destination *dest);

enum {
	SET_VLAN_STRIP	= BIT(0),
	SET_VLAN_INSERT	= BIT(1)
};

enum mlx5_flow_match_level {
	MLX5_MATCH_NONE	= MLX5_INLINE_MODE_NONE,
	MLX5_MATCH_L2	= MLX5_INLINE_MODE_L2,
	MLX5_MATCH_L3	= MLX5_INLINE_MODE_IP,
	MLX5_MATCH_L4	= MLX5_INLINE_MODE_TCP_UDP,
};

/* current maximum for flow based vport multicasting */
#define MLX5_MAX_FLOW_FWD_VPORTS 2

struct mlx5_esw_flow_attr {
	struct mlx5_eswitch_rep *in_rep;
	struct mlx5_eswitch_rep *out_rep[MLX5_MAX_FLOW_FWD_VPORTS];
	struct mlx5_core_dev	*out_mdev[MLX5_MAX_FLOW_FWD_VPORTS];
	struct mlx5_core_dev	*in_mdev;

	int mirror_count;
	int out_count;

	int	action;
	__be16	vlan_proto[MLX5_FS_VLAN_DEPTH];
	u16	vlan_vid[MLX5_FS_VLAN_DEPTH];
	u8	vlan_prio[MLX5_FS_VLAN_DEPTH];
	u8	total_vlan;
	bool	vlan_handled;
	u32	encap_id;
	u32	mod_hdr_id;
	u8	match_level;
	struct mlx5_fc *counter;
	struct mlx5e_tc_flow_parse_attr *parse_attr;
};

int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
				  struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
					 struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
					struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);

int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				  int vport, u16 vlan, u8 qos, u8 set_flags);

static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
						       u8 vlan_depth)
{
	bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
		   MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);

	if (vlan_depth == 1)
		return ret;

	return  ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
		MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
}

#define MLX5_DEBUG_ESWITCH_MASK BIT(3)

#define esw_info(dev, format, ...)				\
	pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)

#define esw_warn(dev, format, ...)				\
	pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)

#define esw_debug(dev, format, ...)				\
	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
#else  /* CONFIG_MLX5_ESWITCH */
/* eswitch API stubs */
static inline int  mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
static inline void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) {}
static inline int  mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}

#define FDB_MAX_CHAIN 1
#define FDB_MAX_PRIO 1

#endif /* CONFIG_MLX5_ESWITCH */

#endif /* __MLX5_ESWITCH_H__ */
Commit	Line	Data
073bb189 SM	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_ESWITCH_H__
	34	#define __MLX5_ESWITCH_H__
	35
77256579 SM	36	#include <linux/if_ether.h>
77256579 SM	37	#include <linux/if_link.h>
feae9087	38	#include <net/devlink.h>
073bb189	39	#include <linux/mlx5/device.h>
57cbd893	40	#include <linux/mlx5/eswitch.h>
cc495188	41	#include <linux/mlx5/fs.h>
eeb66cdb	42	#include "lib/mpfs.h"
073bb189	43
e80541ec SM	44	#ifdef CONFIG_MLX5_ESWITCH
e80541ec SM	45
073bb189 SM	46	#define MLX5_MAX_UC_PER_VPORT(dev) \
	47	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
	48
	49	#define MLX5_MAX_MC_PER_VPORT(dev) \
	50	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
	51
cb67b832 HHZ	52	#define FDB_UPLINK_VPORT 0xffff
cb67b832 HHZ	53
c9497c98 MHY	54	#define MLX5_MIN_BW_SHARE 1
	55
	56	#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	57	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
	58
a842dd04 CM	59	#define mlx5_esw_has_fwd_fdb(dev) \
	60	MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
	61
328edb49 PB	62	#define FDB_MAX_CHAIN 3
	63	#define FDB_MAX_PRIO 16
	64
5742df0f MHY	65	struct vport_ingress {
	66	struct mlx5_flow_table *acl;
	67	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	68	struct mlx5_flow_group *allow_spoofchk_only_grp;
	69	struct mlx5_flow_group *allow_untagged_only_grp;
	70	struct mlx5_flow_group *drop_grp;
74491de9 MB	71	struct mlx5_flow_handle *allow_rule;
74491de9 MB	72	struct mlx5_flow_handle *drop_rule;
b8a0dbe3	73	struct mlx5_fc *drop_counter;
5742df0f MHY	74	};
	75
	76	struct vport_egress {
	77	struct mlx5_flow_table *acl;
	78	struct mlx5_flow_group *allowed_vlans_grp;
	79	struct mlx5_flow_group *drop_grp;
74491de9 MB	80	struct mlx5_flow_handle *allowed_vlan;
74491de9 MB	81	struct mlx5_flow_handle *drop_rule;
b8a0dbe3 EE	82	struct mlx5_fc *drop_counter;
	83	};
	84
	85	struct mlx5_vport_drop_stats {
	86	u64 rx_dropped;
	87	u64 tx_dropped;
5742df0f MHY	88	};
5742df0f MHY	89
1ab2068a MHY	90	struct mlx5_vport_info {
	91	u8 mac[ETH_ALEN];
	92	u16 vlan;
	93	u8 qos;
	94	u64 node_guid;
	95	int link_state;
c9497c98	96	u32 min_rate;
1bd27b11	97	u32 max_rate;
1ab2068a MHY	98	bool spoofchk;
	99	bool trusted;
	100	};
	101
073bb189 SM	102	struct mlx5_vport {
	103	struct mlx5_core_dev *dev;
	104	int vport;
	105	struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
81848731	106	struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
74491de9 MB	107	struct mlx5_flow_handle *promisc_rule;
74491de9 MB	108	struct mlx5_flow_handle *allmulti_rule;
073bb189 SM	109	struct work_struct vport_change_handler;
073bb189 SM	110
5742df0f MHY	111	struct vport_ingress ingress;
	112	struct vport_egress egress;
	113
1ab2068a MHY	114	struct mlx5_vport_info info;
1ab2068a MHY	115
1bd27b11 MHY	116	struct {
	117	bool enabled;
	118	u32 esw_tsar_ix;
c9497c98	119	u32 bw_share;
1bd27b11 MHY	120	} qos;
1bd27b11 MHY	121
073bb189	122	bool enabled;
81848731	123	u16 enabled_events;
073bb189 SM	124	};
073bb189 SM	125
81848731	126	struct mlx5_eswitch_fdb {
6ab36e35 OG	127	union {
6ab36e35 OG	128	struct legacy_fdb {
52fff327	129	struct mlx5_flow_table *fdb;
6ab36e35 OG	130	struct mlx5_flow_group *addr_grp;
	131	struct mlx5_flow_group *allmulti_grp;
	132	struct mlx5_flow_group *promisc_grp;
	133	} legacy;
69697b6e OG	134
69697b6e OG	135	struct offloads_fdb {
52fff327	136	struct mlx5_flow_table *fast_fdb;
a842dd04	137	struct mlx5_flow_table *fwd_fdb;
52fff327	138	struct mlx5_flow_table *slow_fdb;
69697b6e OG	139	struct mlx5_flow_group *send_to_vport_grp;
69697b6e OG	140	struct mlx5_flow_group *miss_grp;
f80be543 MB	141	struct mlx5_flow_handle *miss_rule_uni;
f80be543 MB	142	struct mlx5_flow_handle *miss_rule_multi;
f5f82476	143	int vlan_push_pop_refcount;
69697b6e	144	} offloads;
6ab36e35 OG	145	};
	146	};
	147
c116c6ee OG	148	struct mlx5_esw_offload {
c116c6ee OG	149	struct mlx5_flow_table *ft_offloads;
fed9ce22	150	struct mlx5_flow_group *vport_rx_group;
127ea380	151	struct mlx5_eswitch_rep *vport_reps;
a54e20b4	152	DECLARE_HASHTABLE(encap_tbl, 8);
11c9c548	153	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
bffaa916	154	u8 inline_mode;
375f51e2	155	u64 num_flows;
7768d197	156	u8 encap;
c116c6ee OG	157	};
c116c6ee OG	158
0a0ab1d2 EC	159	/* E-Switch MC FDB table hash node */
	160	struct esw_mc_addr { /* SRIOV only */
	161	struct l2addr_node node;
	162	struct mlx5_flow_handle uplink_rule; / Forward to uplink rule */
	163	u32 refcnt;
	164	};
	165
073bb189 SM	166	struct mlx5_eswitch {
073bb189 SM	167	struct mlx5_core_dev *dev;
81848731 SM	168	struct mlx5_eswitch_fdb fdb_table;
81848731 SM	169	struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
073bb189 SM	170	struct workqueue_struct *work_queue;
	171	struct mlx5_vport *vports;
	172	int total_vports;
81848731	173	int enabled_vports;
dfcb1ed3 MHY	174	/* Synchronize between vport change events
	175	* and async SRIOV admin state changes
	176	*/
	177	struct mutex state_lock;
0a0ab1d2	178	struct esw_mc_addr mc_promisc;
1bd27b11 MHY	179
	180	struct {
	181	bool enabled;
	182	u32 root_tsar_id;
	183	} qos;
	184
c116c6ee	185	struct mlx5_esw_offload offloads;
6ab36e35	186	int mode;
073bb189 SM	187	};
073bb189 SM	188
766a0e97 BX	189	void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
766a0e97 BX	190	int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
e8d31c4d MB	191	void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
e8d31c4d MB	192	int esw_offloads_init_reps(struct mlx5_eswitch *esw);
766a0e97	193
073bb189 SM	194	/* E-Switch API */
	195	int mlx5_eswitch_init(struct mlx5_core_dev *dev);
	196	void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
	197	void mlx5_eswitch_vport_event(struct mlx5_eswitch esw, struct mlx5_eqe eqe);
6ab36e35	198	int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
81848731	199	void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
77256579 SM	200	int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
	201	int vport, u8 mac[ETH_ALEN]);
	202	int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
	203	int vport, int link_state);
9e7ea352 SM	204	int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
9e7ea352 SM	205	int vport, u16 vlan, u8 qos);
f942380c MHY	206	int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
f942380c MHY	207	int vport, bool spoofchk);
1edc57e2 MHY	208	int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1edc57e2 MHY	209	int vport_num, bool setting);
c9497c98 MHY	210	int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
c9497c98 MHY	211	u32 max_rate, u32 min_rate);
77256579 SM	212	int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
77256579 SM	213	int vport, struct ifla_vf_info *ivi);
3b751a2a SM	214	int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
	215	int vport,
	216	struct ifla_vf_stats *vf_stats);
159fe639	217	void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
073bb189	218
3d80d1a2	219	struct mlx5_flow_spec;
776b12b6	220	struct mlx5_esw_flow_attr;
3d80d1a2	221
74491de9	222	struct mlx5_flow_handle *
3d80d1a2 OG	223	mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
3d80d1a2 OG	224	struct mlx5_flow_spec *spec,
776b12b6	225	struct mlx5_esw_flow_attr *attr);
e4ad91f2 CM	226	struct mlx5_flow_handle *
	227	mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
	228	struct mlx5_flow_spec *spec,
	229	struct mlx5_esw_flow_attr *attr);
d85cdccb OG	230	void
	231	mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
	232	struct mlx5_flow_handle *rule,
	233	struct mlx5_esw_flow_attr *attr);
	234
74491de9	235	struct mlx5_flow_handle *
c966f7d5 GT	236	mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
c966f7d5 GT	237	struct mlx5_flow_destination *dest);
fed9ce22	238
e33dfe31 OG	239	enum {
	240	SET_VLAN_STRIP = BIT(0),
	241	SET_VLAN_INSERT = BIT(1)
	242	};
	243
d708f902 OG	244	enum mlx5_flow_match_level {
	245	MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
	246	MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
	247	MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
	248	MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
	249	};
	250
592d3651 CM	251	/* current maximum for flow based vport multicasting */
	252	#define MLX5_MAX_FLOW_FWD_VPORTS 2
	253
776b12b6 OG	254	struct mlx5_esw_flow_attr {
776b12b6 OG	255	struct mlx5_eswitch_rep *in_rep;
592d3651 CM	256	struct mlx5_eswitch_rep *out_rep[MLX5_MAX_FLOW_FWD_VPORTS];
592d3651 CM	257	struct mlx5_core_dev *out_mdev[MLX5_MAX_FLOW_FWD_VPORTS];
10ff5359	258	struct mlx5_core_dev *in_mdev;
776b12b6	259
592d3651 CM	260	int mirror_count;
	261	int out_count;
	262
776b12b6	263	int action;
cc495188 JL	264	__be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
	265	u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
	266	u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
	267	u8 total_vlan;
f5f82476	268	bool vlan_handled;
45247bf2	269	u32 encap_id;
d7e75a32	270	u32 mod_hdr_id;
38aa51c1	271	u8 match_level;
b8aee822	272	struct mlx5_fc *counter;
232c0013	273	struct mlx5e_tc_flow_parse_attr *parse_attr;
776b12b6 OG	274	};
776b12b6 OG	275
db7ff19e EB	276	int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
db7ff19e EB	277	struct netlink_ext_ack *extack);
feae9087	278	int mlx5_devlink_eswitch_mode_get(struct devlink devlink, u16 mode);
db7ff19e EB	279	int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
db7ff19e EB	280	struct netlink_ext_ack *extack);
bffaa916 RD	281	int mlx5_devlink_eswitch_inline_mode_get(struct devlink devlink, u8 mode);
bffaa916 RD	282	int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch esw, int nvfs, u8 mode);
db7ff19e EB	283	int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
db7ff19e EB	284	struct netlink_ext_ack *extack);
7768d197	285	int mlx5_devlink_eswitch_encap_mode_get(struct devlink devlink, u8 encap);
a4b97ab4	286	void mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch esw, u8 rep_type);
feae9087	287
f5f82476 OG	288	int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
	289	struct mlx5_esw_flow_attr *attr);
	290	int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
	291	struct mlx5_esw_flow_attr *attr);
	292	int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
	293	int vport, u16 vlan, u8 qos, u8 set_flags);
	294
cc495188 JL	295	static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
cc495188 JL	296	u8 vlan_depth)
6acfbf38	297	{
cc495188 JL	298	bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
	299	MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
	300
	301	if (vlan_depth == 1)
	302	return ret;
	303
	304	return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
	305	MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
6acfbf38 OG	306	}
6acfbf38 OG	307
69697b6e OG	308	#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
	309
	310	#define esw_info(dev, format, ...) \
	311	pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
	312
	313	#define esw_warn(dev, format, ...) \
	314	pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
	315
	316	#define esw_debug(dev, format, ...) \
	317	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
e80541ec SM	318	#else /* CONFIG_MLX5_ESWITCH */
	319	/* eswitch API stubs */
	320	static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
	321	static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
	322	static inline void mlx5_eswitch_vport_event(struct mlx5_eswitch esw, struct mlx5_eqe eqe) {}
	323	static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
	324	static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
328edb49 PB	325
	326	#define FDB_MAX_CHAIN 1
	327	#define FDB_MAX_PRIO 1
	328
e80541ec SM	329	#endif /* CONFIG_MLX5_ESWITCH */
e80541ec SM	330
073bb189	331	#endif /* __MLX5_ESWITCH_H__ */