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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
feae9087 | 39 | #include <net/devlink.h> |
073bb189 | 40 | #include <linux/mlx5/device.h> |
57cbd893 | 41 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 42 | #include <linux/mlx5/vport.h> |
cc495188 | 43 | #include <linux/mlx5/fs.h> |
eeb66cdb | 44 | #include "lib/mpfs.h" |
ae430332 | 45 | #include "lib/fs_chains.h" |
4c3844d9 | 46 | #include "en/tc_ct.h" |
073bb189 | 47 | |
e80541ec SM |
48 | #ifdef CONFIG_MLX5_ESWITCH |
49 | ||
87dac697 JL |
50 | #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 |
51 | ||
073bb189 SM |
52 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
53 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
54 | ||
55 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
56 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
57 | ||
c9497c98 MHY |
58 | #define MLX5_MIN_BW_SHARE 1 |
59 | ||
60 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
61 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
62 | ||
a842dd04 CM |
63 | #define mlx5_esw_has_fwd_fdb(dev) \ |
64 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
65 | ||
ae430332 AL |
66 | #define esw_chains(esw) \ |
67 | ((esw)->fdb_table.offloads.esw_chains_priv) | |
68 | ||
5742df0f MHY |
69 | struct vport_ingress { |
70 | struct mlx5_flow_table *acl; | |
10652f39 | 71 | struct mlx5_flow_handle *allow_rule; |
853b5352 | 72 | struct { |
10652f39 PP |
73 | struct mlx5_flow_group *allow_spoofchk_only_grp; |
74 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
75 | struct mlx5_flow_group *allow_untagged_only_grp; | |
76 | struct mlx5_flow_group *drop_grp; | |
853b5352 PP |
77 | struct mlx5_flow_handle *drop_rule; |
78 | struct mlx5_fc *drop_counter; | |
79 | } legacy; | |
d68316b5 | 80 | struct { |
b7826076 PP |
81 | /* Optional group to add an FTE to do internal priority |
82 | * tagging on ingress packets. | |
83 | */ | |
84 | struct mlx5_flow_group *metadata_prio_tag_grp; | |
85 | /* Group to add default match-all FTE entry to tag ingress | |
86 | * packet with metadata. | |
87 | */ | |
88 | struct mlx5_flow_group *metadata_allmatch_grp; | |
d68316b5 PP |
89 | struct mlx5_modify_hdr *modify_metadata; |
90 | struct mlx5_flow_handle *modify_metadata_rule; | |
91 | } offloads; | |
5742df0f MHY |
92 | }; |
93 | ||
94 | struct vport_egress { | |
95 | struct mlx5_flow_table *acl; | |
74491de9 | 96 | struct mlx5_flow_handle *allowed_vlan; |
ea651a86 | 97 | struct mlx5_flow_group *vlan_grp; |
bf773dc0 VP |
98 | union { |
99 | struct { | |
100 | struct mlx5_flow_group *drop_grp; | |
101 | struct mlx5_flow_handle *drop_rule; | |
102 | struct mlx5_fc *drop_counter; | |
103 | } legacy; | |
104 | struct { | |
105 | struct mlx5_flow_group *fwd_grp; | |
106 | struct mlx5_flow_handle *fwd_rule; | |
107 | } offloads; | |
108 | }; | |
b8a0dbe3 EE |
109 | }; |
110 | ||
111 | struct mlx5_vport_drop_stats { | |
112 | u64 rx_dropped; | |
113 | u64 tx_dropped; | |
5742df0f MHY |
114 | }; |
115 | ||
1ab2068a MHY |
116 | struct mlx5_vport_info { |
117 | u8 mac[ETH_ALEN]; | |
118 | u16 vlan; | |
119 | u8 qos; | |
120 | u64 node_guid; | |
121 | int link_state; | |
c9497c98 | 122 | u32 min_rate; |
1bd27b11 | 123 | u32 max_rate; |
1ab2068a MHY |
124 | bool spoofchk; |
125 | bool trusted; | |
126 | }; | |
127 | ||
5019833d PP |
128 | /* Vport context events */ |
129 | enum mlx5_eswitch_vport_event { | |
130 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
131 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
132 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
133 | }; | |
134 | ||
073bb189 SM |
135 | struct mlx5_vport { |
136 | struct mlx5_core_dev *dev; | |
137 | int vport; | |
138 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 139 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
140 | struct mlx5_flow_handle *promisc_rule; |
141 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
142 | struct work_struct vport_change_handler; |
143 | ||
5742df0f MHY |
144 | struct vport_ingress ingress; |
145 | struct vport_egress egress; | |
133dcfc5 VP |
146 | u32 default_metadata; |
147 | u32 metadata; | |
5742df0f | 148 | |
1ab2068a MHY |
149 | struct mlx5_vport_info info; |
150 | ||
1bd27b11 MHY |
151 | struct { |
152 | bool enabled; | |
153 | u32 esw_tsar_ix; | |
c9497c98 | 154 | u32 bw_share; |
1bd27b11 MHY |
155 | } qos; |
156 | ||
073bb189 | 157 | bool enabled; |
5019833d | 158 | enum mlx5_eswitch_vport_event enabled_events; |
073bb189 SM |
159 | }; |
160 | ||
81848731 | 161 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
162 | union { |
163 | struct legacy_fdb { | |
52fff327 | 164 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
165 | struct mlx5_flow_group *addr_grp; |
166 | struct mlx5_flow_group *allmulti_grp; | |
167 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
168 | struct mlx5_flow_table *vepa_fdb; |
169 | struct mlx5_flow_handle *vepa_uplink_rule; | |
170 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 171 | } legacy; |
69697b6e OG |
172 | |
173 | struct offloads_fdb { | |
8463daf1 | 174 | struct mlx5_flow_namespace *ns; |
52fff327 | 175 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 176 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
177 | struct mlx5_flow_group *peer_miss_grp; |
178 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 179 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
180 | struct mlx5_flow_handle *miss_rule_uni; |
181 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 182 | int vlan_push_pop_refcount; |
e52c2802 | 183 | |
ae430332 | 184 | struct mlx5_fs_chains *esw_chains_priv; |
96e32687 EC |
185 | struct { |
186 | DECLARE_HASHTABLE(table, 8); | |
187 | /* Protects vports.table */ | |
188 | struct mutex lock; | |
189 | } vports; | |
190 | ||
69697b6e | 191 | } offloads; |
6ab36e35 | 192 | }; |
e52c2802 | 193 | u32 flags; |
6ab36e35 OG |
194 | }; |
195 | ||
c116c6ee | 196 | struct mlx5_esw_offload { |
11b717d6 PB |
197 | struct mlx5_flow_table *ft_offloads_restore; |
198 | struct mlx5_flow_group *restore_group; | |
6724e66b | 199 | struct mlx5_modify_hdr *restore_copy_hdr_id; |
11b717d6 | 200 | |
c116c6ee | 201 | struct mlx5_flow_table *ft_offloads; |
fed9ce22 | 202 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 203 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
204 | struct list_head peer_flows; |
205 | struct mutex peer_mutex; | |
61086f39 | 206 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 207 | DECLARE_HASHTABLE(encap_tbl, 8); |
14e6b038 EC |
208 | struct mutex decap_tbl_lock; /* protects decap_tbl */ |
209 | DECLARE_HASHTABLE(decap_tbl, 8); | |
dd58edc3 | 210 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
211 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
212 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
8693115a | 213 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 214 | u8 inline_mode; |
525e84be | 215 | atomic64_t num_flows; |
98fdbea5 | 216 | enum devlink_eswitch_encap_mode encap; |
133dcfc5 | 217 | struct ida vport_metadata_ida; |
a53cf949 | 218 | unsigned int host_number; /* ECPF supports one external host */ |
c116c6ee OG |
219 | }; |
220 | ||
0a0ab1d2 EC |
221 | /* E-Switch MC FDB table hash node */ |
222 | struct esw_mc_addr { /* SRIOV only */ | |
223 | struct l2addr_node node; | |
224 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
225 | u32 refcnt; | |
226 | }; | |
227 | ||
a3888f33 BW |
228 | struct mlx5_host_work { |
229 | struct work_struct work; | |
230 | struct mlx5_eswitch *esw; | |
231 | }; | |
232 | ||
cd56f929 | 233 | struct mlx5_esw_functions { |
a3888f33 BW |
234 | struct mlx5_nb nb; |
235 | u16 num_vfs; | |
236 | }; | |
237 | ||
7445cfb1 JL |
238 | enum { |
239 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
5b7cb745 | 240 | MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), |
7445cfb1 JL |
241 | }; |
242 | ||
073bb189 SM |
243 | struct mlx5_eswitch { |
244 | struct mlx5_core_dev *dev; | |
6933a937 | 245 | struct mlx5_nb nb; |
81848731 | 246 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 247 | /* legacy data structures */ |
81848731 | 248 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
249 | struct esw_mc_addr mc_promisc; |
250 | /* end of legacy */ | |
073bb189 SM |
251 | struct workqueue_struct *work_queue; |
252 | struct mlx5_vport *vports; | |
7445cfb1 | 253 | u32 flags; |
073bb189 | 254 | int total_vports; |
81848731 | 255 | int enabled_vports; |
dfcb1ed3 MHY |
256 | /* Synchronize between vport change events |
257 | * and async SRIOV admin state changes | |
258 | */ | |
259 | struct mutex state_lock; | |
1bd27b11 | 260 | |
8e0aa4bc PP |
261 | /* Protects eswitch mode change that occurs via one or more |
262 | * user commands, i.e. sriov state change, devlink commands. | |
263 | */ | |
264 | struct mutex mode_lock; | |
265 | ||
1bd27b11 MHY |
266 | struct { |
267 | bool enabled; | |
268 | u32 root_tsar_id; | |
269 | } qos; | |
270 | ||
c116c6ee | 271 | struct mlx5_esw_offload offloads; |
6ab36e35 | 272 | int mode; |
a1b3839a | 273 | u16 manager_vport; |
411ec9e0 | 274 | u16 first_host_vport; |
cd56f929 | 275 | struct mlx5_esw_functions esw_funcs; |
87dac697 JL |
276 | struct { |
277 | u32 large_group_num; | |
278 | } params; | |
073bb189 SM |
279 | }; |
280 | ||
5896b972 PP |
281 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
282 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
e8d31c4d MB |
283 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
284 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
ea651a86 | 285 | |
133dcfc5 VP |
286 | u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); |
287 | void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); | |
288 | ||
fcb64c0f EC |
289 | int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, |
290 | u32 rate_mbps); | |
766a0e97 | 291 | |
073bb189 SM |
292 | /* E-Switch API */ |
293 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
294 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
ebf77bb8 PP |
295 | |
296 | #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) | |
8e0aa4bc PP |
297 | int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs); |
298 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); | |
299 | void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw, bool clear_vf); | |
556b9d16 | 300 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf); |
77256579 | 301 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
fa997825 | 302 | u16 vport, const u8 *mac); |
77256579 | 303 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 304 | u16 vport, int link_state); |
9e7ea352 | 305 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 306 | u16 vport, u16 vlan, u8 qos); |
f942380c | 307 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 308 | u16 vport, bool spoofchk); |
1edc57e2 | 309 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
310 | u16 vport_num, bool setting); |
311 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 312 | u32 max_rate, u32 min_rate); |
8da202b2 HN |
313 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
314 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 315 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 316 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 317 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 318 | u16 vport, |
3b751a2a | 319 | struct ifla_vf_stats *vf_stats); |
159fe639 | 320 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 321 | |
238302fa | 322 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, |
e08a6832 | 323 | bool other_vport, void *in); |
57843868 | 324 | |
3d80d1a2 | 325 | struct mlx5_flow_spec; |
776b12b6 | 326 | struct mlx5_esw_flow_attr; |
10caabda OS |
327 | struct mlx5_termtbl_handle; |
328 | ||
329 | bool | |
330 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
c620b772 | 331 | struct mlx5_flow_attr *attr, |
10caabda OS |
332 | struct mlx5_flow_act *flow_act, |
333 | struct mlx5_flow_spec *spec); | |
334 | ||
335 | struct mlx5_flow_handle * | |
336 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
337 | struct mlx5_flow_table *ft, | |
338 | struct mlx5_flow_spec *spec, | |
339 | struct mlx5_esw_flow_attr *attr, | |
340 | struct mlx5_flow_act *flow_act, | |
341 | struct mlx5_flow_destination *dest, | |
342 | int num_dest); | |
343 | ||
344 | void | |
345 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
346 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 347 | |
74491de9 | 348 | struct mlx5_flow_handle * |
3d80d1a2 OG |
349 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
350 | struct mlx5_flow_spec *spec, | |
c620b772 | 351 | struct mlx5_flow_attr *attr); |
e4ad91f2 CM |
352 | struct mlx5_flow_handle * |
353 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
354 | struct mlx5_flow_spec *spec, | |
c620b772 | 355 | struct mlx5_flow_attr *attr); |
d85cdccb OG |
356 | void |
357 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
358 | struct mlx5_flow_handle *rule, | |
c620b772 | 359 | struct mlx5_flow_attr *attr); |
48265006 OG |
360 | void |
361 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
362 | struct mlx5_flow_handle *rule, | |
c620b772 | 363 | struct mlx5_flow_attr *attr); |
d85cdccb | 364 | |
74491de9 | 365 | struct mlx5_flow_handle * |
02f3afd9 | 366 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 367 | struct mlx5_flow_destination *dest); |
fed9ce22 | 368 | |
e33dfe31 OG |
369 | enum { |
370 | SET_VLAN_STRIP = BIT(0), | |
371 | SET_VLAN_INSERT = BIT(1) | |
372 | }; | |
373 | ||
d708f902 OG |
374 | enum mlx5_flow_match_level { |
375 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
376 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
377 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
378 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
379 | }; | |
380 | ||
592d3651 CM |
381 | /* current maximum for flow based vport multicasting */ |
382 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
383 | ||
f493f155 EB |
384 | enum { |
385 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 386 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
387 | }; |
388 | ||
39ac237c PB |
389 | enum { |
390 | MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0), | |
391 | MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1), | |
6fb0701a | 392 | MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2), |
39ac237c PB |
393 | }; |
394 | ||
776b12b6 OG |
395 | struct mlx5_esw_flow_attr { |
396 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 397 | struct mlx5_core_dev *in_mdev; |
f9392795 | 398 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 399 | |
e85e02ba | 400 | int split_count; |
592d3651 CM |
401 | int out_count; |
402 | ||
cc495188 JL |
403 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
404 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
405 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
406 | u8 total_vlan; | |
df65a573 | 407 | struct { |
f493f155 | 408 | u32 flags; |
df65a573 | 409 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 410 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 411 | struct mlx5_core_dev *mdev; |
10caabda | 412 | struct mlx5_termtbl_handle *termtbl; |
df65a573 | 413 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
14e6b038 | 414 | struct mlx5_pkt_reformat *decap_pkt_reformat; |
776b12b6 OG |
415 | }; |
416 | ||
db7ff19e EB |
417 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
418 | struct netlink_ext_ack *extack); | |
feae9087 | 419 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
420 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
421 | struct netlink_ext_ack *extack); | |
bffaa916 | 422 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
98fdbea5 LR |
423 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
424 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 425 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
426 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
427 | enum devlink_eswitch_encap_mode *encap); | |
f099fde1 PP |
428 | int mlx5_devlink_port_function_hw_addr_get(struct devlink *devlink, |
429 | struct devlink_port *port, | |
430 | u8 *hw_addr, int *hw_addr_len, | |
431 | struct netlink_ext_ack *extack); | |
330077d1 PP |
432 | int mlx5_devlink_port_function_hw_addr_set(struct devlink *devlink, |
433 | struct devlink_port *port, | |
434 | const u8 *hw_addr, int hw_addr_len, | |
435 | struct netlink_ext_ack *extack); | |
f099fde1 | 436 | |
a4b97ab4 | 437 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 438 | |
f5f82476 | 439 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
c620b772 | 440 | struct mlx5_flow_attr *attr); |
f5f82476 | 441 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, |
c620b772 | 442 | struct mlx5_flow_attr *attr); |
f5f82476 | 443 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 444 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 445 | |
b5f814cc EC |
446 | static inline bool mlx5_esw_qos_enabled(struct mlx5_eswitch *esw) |
447 | { | |
448 | return esw->qos.enabled; | |
449 | } | |
450 | ||
cc495188 JL |
451 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
452 | u8 vlan_depth) | |
6acfbf38 | 453 | { |
cc495188 JL |
454 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
455 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
456 | ||
457 | if (vlan_depth == 1) | |
458 | return ret; | |
459 | ||
460 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
461 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
462 | } |
463 | ||
eff849b2 RL |
464 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
465 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
466 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
467 | struct mlx5_core_dev *dev1); | |
eff849b2 | 468 | |
dd28087c | 469 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 470 | |
69697b6e OG |
471 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
472 | ||
27b942fb PP |
473 | #define esw_info(__dev, format, ...) \ |
474 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 475 | |
27b942fb PP |
476 | #define esw_warn(__dev, format, ...) \ |
477 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
478 | |
479 | #define esw_debug(dev, format, ...) \ | |
480 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
481 | |
482 | /* The returned number is valid only when the dev is eswitch manager. */ | |
483 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
484 | { | |
485 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
486 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
487 | } | |
488 | ||
ea2300e0 PP |
489 | static inline bool |
490 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
491 | { | |
492 | return esw->manager_vport == vport_num; | |
493 | } | |
494 | ||
411ec9e0 BW |
495 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
496 | { | |
497 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
498 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
499 | } | |
500 | ||
3d5f41ca | 501 | static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) |
6706a3b9 | 502 | { |
3d5f41ca | 503 | return mlx5_core_is_ecpf_esw_manager(dev); |
6706a3b9 VP |
504 | } |
505 | ||
5ae51620 BW |
506 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
507 | { | |
508 | /* Uplink always locate at the last element of the array.*/ | |
509 | return esw->total_vports - 1; | |
510 | } | |
511 | ||
81cd229c BW |
512 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
513 | { | |
514 | return esw->total_vports - 2; | |
515 | } | |
516 | ||
5ae51620 BW |
517 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
518 | u16 vport_num) | |
519 | { | |
81cd229c BW |
520 | if (vport_num == MLX5_VPORT_ECPF) { |
521 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
522 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
523 | return mlx5_eswitch_ecpf_idx(esw); | |
524 | } | |
525 | ||
5ae51620 BW |
526 | if (vport_num == MLX5_VPORT_UPLINK) |
527 | return mlx5_eswitch_uplink_idx(esw); | |
528 | ||
529 | return vport_num; | |
530 | } | |
531 | ||
02f3afd9 | 532 | static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, |
5ae51620 BW |
533 | int index) |
534 | { | |
81cd229c BW |
535 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
536 | mlx5_ecpf_vport_exists(esw->dev)) | |
537 | return MLX5_VPORT_ECPF; | |
538 | ||
5ae51620 BW |
539 | if (index == mlx5_eswitch_uplink_idx(esw)) |
540 | return MLX5_VPORT_UPLINK; | |
541 | ||
542 | return index; | |
543 | } | |
544 | ||
443bf36e PP |
545 | static inline unsigned int |
546 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
547 | u16 vport_num) | |
548 | { | |
549 | return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; | |
550 | } | |
551 | ||
f099fde1 PP |
552 | static inline u16 |
553 | mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) | |
554 | { | |
555 | return dl_port_index & 0xffff; | |
556 | } | |
557 | ||
ee576ec1 SM |
558 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
559 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
560 | ||
786ef904 PP |
561 | /* The vport getter/iterator are only valid after esw->total_vports |
562 | * and vport->vport are initialized in mlx5_eswitch_init. | |
563 | */ | |
564 | #define mlx5_esw_for_all_vports(esw, i, vport) \ | |
565 | for ((i) = MLX5_VPORT_PF; \ | |
566 | (vport) = &(esw)->vports[i], \ | |
567 | (i) < (esw)->total_vports; (i)++) | |
568 | ||
5019833d PP |
569 | #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \ |
570 | for ((i) = (esw)->total_vports - 1; \ | |
571 | (vport) = &(esw)->vports[i], \ | |
572 | (i) >= MLX5_VPORT_PF; (i)--) | |
573 | ||
786ef904 PP |
574 | #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \ |
575 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
576 | (vport) = &(esw)->vports[(i)], \ | |
577 | (i) <= (nvfs); (i)++) | |
578 | ||
579 | #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \ | |
580 | for ((i) = (nvfs); \ | |
581 | (vport) = &(esw)->vports[(i)], \ | |
582 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
583 | ||
584 | /* The rep getter/iterator are only valid after esw->total_vports | |
585 | * and vport->vport are initialized in mlx5_eswitch_init. | |
586 | */ | |
587 | #define mlx5_esw_for_all_reps(esw, i, rep) \ | |
588 | for ((i) = MLX5_VPORT_PF; \ | |
589 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
590 | (i) < (esw)->total_vports; (i)++) | |
591 | ||
592 | #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \ | |
593 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
594 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
595 | (i) <= (nvfs); (i)++) | |
596 | ||
597 | #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \ | |
598 | for ((i) = (nvfs); \ | |
599 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
600 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
601 | ||
602 | #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \ | |
603 | for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++) | |
604 | ||
605 | #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \ | |
606 | for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--) | |
607 | ||
411ec9e0 BW |
608 | /* Includes host PF (vport 0) if it's not esw manager. */ |
609 | #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \ | |
610 | for ((i) = (esw)->first_host_vport; \ | |
611 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
612 | (i) <= (nvfs); (i)++) | |
613 | ||
614 | #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \ | |
615 | for ((i) = (nvfs); \ | |
616 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
617 | (i) >= (esw)->first_host_vport; (i)--) | |
618 | ||
619 | #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \ | |
620 | for ((vport) = (esw)->first_host_vport; \ | |
621 | (vport) <= (nvfs); (vport)++) | |
622 | ||
623 | #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \ | |
624 | for ((vport) = (nvfs); \ | |
625 | (vport) >= (esw)->first_host_vport; (vport)--) | |
626 | ||
bd939753 | 627 | struct mlx5_eswitch *mlx5_devlink_eswitch_get(struct devlink *devlink); |
5d9986a3 BW |
628 | struct mlx5_vport *__must_check |
629 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
630 | ||
91d6291c PP |
631 | bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num); |
632 | ||
16fff98a | 633 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 634 | |
925a6acc | 635 | int |
5019833d PP |
636 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, |
637 | enum mlx5_eswitch_vport_event enabled_events); | |
638 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
639 | ||
748da30b VP |
640 | int |
641 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, | |
642 | struct mlx5_vport *vport); | |
643 | void | |
644 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, | |
645 | struct mlx5_vport *vport); | |
646 | ||
96e32687 EC |
647 | int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw); |
648 | void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw); | |
649 | ||
11b717d6 PB |
650 | struct mlx5_flow_handle * |
651 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); | |
652 | u32 | |
653 | esw_get_max_restore_tag(struct mlx5_eswitch *esw); | |
654 | ||
c2d7712c BW |
655 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num); |
656 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num); | |
657 | ||
23bb50cf BW |
658 | int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num, |
659 | enum mlx5_eswitch_vport_event enabled_events); | |
660 | void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
661 | ||
662 | int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, | |
663 | enum mlx5_eswitch_vport_event enabled_events); | |
664 | void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); | |
665 | ||
e80541ec SM |
666 | #else /* CONFIG_MLX5_ESWITCH */ |
667 | /* eswitch API stubs */ | |
668 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
669 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
8e0aa4bc | 670 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } |
556b9d16 | 671 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf) {} |
eff849b2 | 672 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 673 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
7d0314b1 RD |
674 | static inline |
675 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } | |
dd28087c | 676 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 677 | { |
dd28087c | 678 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 679 | } |
328edb49 | 680 | |
9d3faa51 | 681 | static inline struct mlx5_flow_handle * |
11b717d6 PB |
682 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) |
683 | { | |
684 | return ERR_PTR(-EOPNOTSUPP); | |
685 | } | |
e80541ec SM |
686 | #endif /* CONFIG_MLX5_ESWITCH */ |
687 | ||
073bb189 | 688 | #endif /* __MLX5_ESWITCH_H__ */ |