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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
feae9087 | 38 | #include <net/devlink.h> |
073bb189 | 39 | #include <linux/mlx5/device.h> |
57cbd893 | 40 | #include <linux/mlx5/eswitch.h> |
cc495188 | 41 | #include <linux/mlx5/fs.h> |
eeb66cdb | 42 | #include "lib/mpfs.h" |
073bb189 | 43 | |
e80541ec SM |
44 | #ifdef CONFIG_MLX5_ESWITCH |
45 | ||
073bb189 SM |
46 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
47 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
48 | ||
49 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
50 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
51 | ||
cb67b832 HHZ |
52 | #define FDB_UPLINK_VPORT 0xffff |
53 | ||
c9497c98 MHY |
54 | #define MLX5_MIN_BW_SHARE 1 |
55 | ||
56 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
57 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
58 | ||
a842dd04 CM |
59 | #define mlx5_esw_has_fwd_fdb(dev) \ |
60 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
61 | ||
328edb49 | 62 | #define FDB_MAX_CHAIN 3 |
c92a0b94 | 63 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
64 | #define FDB_MAX_PRIO 16 |
65 | ||
5742df0f MHY |
66 | struct vport_ingress { |
67 | struct mlx5_flow_table *acl; | |
68 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
69 | struct mlx5_flow_group *allow_spoofchk_only_grp; | |
70 | struct mlx5_flow_group *allow_untagged_only_grp; | |
71 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
72 | struct mlx5_flow_handle *allow_rule; |
73 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 | 74 | struct mlx5_fc *drop_counter; |
5742df0f MHY |
75 | }; |
76 | ||
77 | struct vport_egress { | |
78 | struct mlx5_flow_table *acl; | |
79 | struct mlx5_flow_group *allowed_vlans_grp; | |
80 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
81 | struct mlx5_flow_handle *allowed_vlan; |
82 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 EE |
83 | struct mlx5_fc *drop_counter; |
84 | }; | |
85 | ||
86 | struct mlx5_vport_drop_stats { | |
87 | u64 rx_dropped; | |
88 | u64 tx_dropped; | |
5742df0f MHY |
89 | }; |
90 | ||
1ab2068a MHY |
91 | struct mlx5_vport_info { |
92 | u8 mac[ETH_ALEN]; | |
93 | u16 vlan; | |
94 | u8 qos; | |
95 | u64 node_guid; | |
96 | int link_state; | |
c9497c98 | 97 | u32 min_rate; |
1bd27b11 | 98 | u32 max_rate; |
1ab2068a MHY |
99 | bool spoofchk; |
100 | bool trusted; | |
101 | }; | |
102 | ||
073bb189 SM |
103 | struct mlx5_vport { |
104 | struct mlx5_core_dev *dev; | |
105 | int vport; | |
106 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 107 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
108 | struct mlx5_flow_handle *promisc_rule; |
109 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
110 | struct work_struct vport_change_handler; |
111 | ||
5742df0f MHY |
112 | struct vport_ingress ingress; |
113 | struct vport_egress egress; | |
114 | ||
1ab2068a MHY |
115 | struct mlx5_vport_info info; |
116 | ||
1bd27b11 MHY |
117 | struct { |
118 | bool enabled; | |
119 | u32 esw_tsar_ix; | |
c9497c98 | 120 | u32 bw_share; |
1bd27b11 MHY |
121 | } qos; |
122 | ||
073bb189 | 123 | bool enabled; |
81848731 | 124 | u16 enabled_events; |
073bb189 SM |
125 | }; |
126 | ||
e52c2802 PB |
127 | enum offloads_fdb_flags { |
128 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
129 | }; | |
130 | ||
131 | extern const unsigned int ESW_POOLS[4]; | |
132 | ||
133 | #define PRIO_LEVELS 2 | |
81848731 | 134 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
135 | union { |
136 | struct legacy_fdb { | |
52fff327 | 137 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
138 | struct mlx5_flow_group *addr_grp; |
139 | struct mlx5_flow_group *allmulti_grp; | |
140 | struct mlx5_flow_group *promisc_grp; | |
141 | } legacy; | |
69697b6e OG |
142 | |
143 | struct offloads_fdb { | |
52fff327 | 144 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 145 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
146 | struct mlx5_flow_group *peer_miss_grp; |
147 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 148 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
149 | struct mlx5_flow_handle *miss_rule_uni; |
150 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 151 | int vlan_push_pop_refcount; |
e52c2802 PB |
152 | |
153 | struct { | |
154 | struct mlx5_flow_table *fdb; | |
155 | u32 num_rules; | |
156 | } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; | |
157 | /* Protects fdb_prio table */ | |
158 | struct mutex fdb_prio_lock; | |
159 | ||
160 | int fdb_left[ARRAY_SIZE(ESW_POOLS)]; | |
69697b6e | 161 | } offloads; |
6ab36e35 | 162 | }; |
e52c2802 | 163 | u32 flags; |
6ab36e35 OG |
164 | }; |
165 | ||
c116c6ee OG |
166 | struct mlx5_esw_offload { |
167 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 168 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 169 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
170 | struct list_head peer_flows; |
171 | struct mutex peer_mutex; | |
a54e20b4 | 172 | DECLARE_HASHTABLE(encap_tbl, 8); |
11c9c548 | 173 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); |
bffaa916 | 174 | u8 inline_mode; |
375f51e2 | 175 | u64 num_flows; |
7768d197 | 176 | u8 encap; |
c116c6ee OG |
177 | }; |
178 | ||
0a0ab1d2 EC |
179 | /* E-Switch MC FDB table hash node */ |
180 | struct esw_mc_addr { /* SRIOV only */ | |
181 | struct l2addr_node node; | |
182 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
183 | u32 refcnt; | |
184 | }; | |
185 | ||
073bb189 SM |
186 | struct mlx5_eswitch { |
187 | struct mlx5_core_dev *dev; | |
6933a937 | 188 | struct mlx5_nb nb; |
81848731 SM |
189 | struct mlx5_eswitch_fdb fdb_table; |
190 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; | |
073bb189 SM |
191 | struct workqueue_struct *work_queue; |
192 | struct mlx5_vport *vports; | |
193 | int total_vports; | |
81848731 | 194 | int enabled_vports; |
dfcb1ed3 MHY |
195 | /* Synchronize between vport change events |
196 | * and async SRIOV admin state changes | |
197 | */ | |
198 | struct mutex state_lock; | |
0a0ab1d2 | 199 | struct esw_mc_addr mc_promisc; |
1bd27b11 MHY |
200 | |
201 | struct { | |
202 | bool enabled; | |
203 | u32 root_tsar_id; | |
204 | } qos; | |
205 | ||
c116c6ee | 206 | struct mlx5_esw_offload offloads; |
6ab36e35 | 207 | int mode; |
e52c2802 | 208 | int nvports; |
073bb189 SM |
209 | }; |
210 | ||
766a0e97 BX |
211 | void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports); |
212 | int esw_offloads_init(struct mlx5_eswitch *esw, int nvports); | |
e8d31c4d MB |
213 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
214 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
766a0e97 | 215 | |
073bb189 SM |
216 | /* E-Switch API */ |
217 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
218 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
6ab36e35 | 219 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode); |
81848731 | 220 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw); |
77256579 SM |
221 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
222 | int vport, u8 mac[ETH_ALEN]); | |
223 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
224 | int vport, int link_state); | |
9e7ea352 SM |
225 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
226 | int vport, u16 vlan, u8 qos); | |
f942380c MHY |
227 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
228 | int vport, bool spoofchk); | |
1edc57e2 MHY |
229 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
230 | int vport_num, bool setting); | |
c9497c98 MHY |
231 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport, |
232 | u32 max_rate, u32 min_rate); | |
77256579 SM |
233 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
234 | int vport, struct ifla_vf_info *ivi); | |
3b751a2a SM |
235 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
236 | int vport, | |
237 | struct ifla_vf_stats *vf_stats); | |
159fe639 | 238 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 239 | |
3d80d1a2 | 240 | struct mlx5_flow_spec; |
776b12b6 | 241 | struct mlx5_esw_flow_attr; |
3d80d1a2 | 242 | |
74491de9 | 243 | struct mlx5_flow_handle * |
3d80d1a2 OG |
244 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
245 | struct mlx5_flow_spec *spec, | |
776b12b6 | 246 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
247 | struct mlx5_flow_handle * |
248 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
249 | struct mlx5_flow_spec *spec, | |
250 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
251 | void |
252 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
253 | struct mlx5_flow_handle *rule, | |
254 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
255 | void |
256 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
257 | struct mlx5_flow_handle *rule, | |
258 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 259 | |
e52c2802 PB |
260 | bool |
261 | mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); | |
262 | ||
263 | u16 | |
264 | mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); | |
265 | ||
266 | u32 | |
267 | mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); | |
268 | ||
74491de9 | 269 | struct mlx5_flow_handle * |
c966f7d5 GT |
270 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, |
271 | struct mlx5_flow_destination *dest); | |
fed9ce22 | 272 | |
e33dfe31 OG |
273 | enum { |
274 | SET_VLAN_STRIP = BIT(0), | |
275 | SET_VLAN_INSERT = BIT(1) | |
276 | }; | |
277 | ||
d708f902 OG |
278 | enum mlx5_flow_match_level { |
279 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
280 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
281 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
282 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
283 | }; | |
284 | ||
592d3651 CM |
285 | /* current maximum for flow based vport multicasting */ |
286 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
287 | ||
f493f155 EB |
288 | enum { |
289 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 290 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
291 | }; |
292 | ||
776b12b6 OG |
293 | struct mlx5_esw_flow_attr { |
294 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 295 | struct mlx5_core_dev *in_mdev; |
f9392795 | 296 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 297 | |
e85e02ba | 298 | int split_count; |
592d3651 CM |
299 | int out_count; |
300 | ||
776b12b6 | 301 | int action; |
cc495188 JL |
302 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
303 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
304 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
305 | u8 total_vlan; | |
f5f82476 | 306 | bool vlan_handled; |
df65a573 | 307 | struct { |
f493f155 | 308 | u32 flags; |
df65a573 EB |
309 | struct mlx5_eswitch_rep *rep; |
310 | struct mlx5_core_dev *mdev; | |
8c4dc42b | 311 | u32 encap_id; |
df65a573 | 312 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
d7e75a32 | 313 | u32 mod_hdr_id; |
38aa51c1 | 314 | u8 match_level; |
6363651d | 315 | u8 tunnel_match_level; |
b8aee822 | 316 | struct mlx5_fc *counter; |
e52c2802 PB |
317 | u32 chain; |
318 | u16 prio; | |
319 | u32 dest_chain; | |
232c0013 | 320 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
321 | }; |
322 | ||
db7ff19e EB |
323 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
324 | struct netlink_ext_ack *extack); | |
feae9087 | 325 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
326 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
327 | struct netlink_ext_ack *extack); | |
bffaa916 RD |
328 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
329 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode); | |
db7ff19e EB |
330 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap, |
331 | struct netlink_ext_ack *extack); | |
7768d197 | 332 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap); |
a4b97ab4 | 333 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 334 | |
f5f82476 OG |
335 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
336 | struct mlx5_esw_flow_attr *attr); | |
337 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
338 | struct mlx5_esw_flow_attr *attr); | |
339 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
340 | int vport, u16 vlan, u8 qos, u8 set_flags); | |
341 | ||
cc495188 JL |
342 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
343 | u8 vlan_depth) | |
6acfbf38 | 344 | { |
cc495188 JL |
345 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
346 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
347 | ||
348 | if (vlan_depth == 1) | |
349 | return ret; | |
350 | ||
351 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
352 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
353 | } |
354 | ||
eff849b2 RL |
355 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
356 | struct mlx5_core_dev *dev1); | |
357 | ||
69697b6e OG |
358 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
359 | ||
360 | #define esw_info(dev, format, ...) \ | |
361 | pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
362 | ||
363 | #define esw_warn(dev, format, ...) \ | |
364 | pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
365 | ||
366 | #define esw_debug(dev, format, ...) \ | |
367 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
e80541ec SM |
368 | #else /* CONFIG_MLX5_ESWITCH */ |
369 | /* eswitch API stubs */ | |
370 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
371 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
e80541ec SM |
372 | static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; } |
373 | static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {} | |
eff849b2 | 374 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
328edb49 PB |
375 | |
376 | #define FDB_MAX_CHAIN 1 | |
c92a0b94 | 377 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
378 | #define FDB_MAX_PRIO 1 |
379 | ||
e80541ec SM |
380 | #endif /* CONFIG_MLX5_ESWITCH */ |
381 | ||
073bb189 | 382 | #endif /* __MLX5_ESWITCH_H__ */ |