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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
feae9087 | 38 | #include <net/devlink.h> |
073bb189 | 39 | #include <linux/mlx5/device.h> |
57cbd893 | 40 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 41 | #include <linux/mlx5/vport.h> |
cc495188 | 42 | #include <linux/mlx5/fs.h> |
eeb66cdb | 43 | #include "lib/mpfs.h" |
073bb189 | 44 | |
e80541ec SM |
45 | #ifdef CONFIG_MLX5_ESWITCH |
46 | ||
073bb189 SM |
47 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
48 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
49 | ||
50 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
51 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
52 | ||
c9497c98 MHY |
53 | #define MLX5_MIN_BW_SHARE 1 |
54 | ||
55 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
56 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
57 | ||
a842dd04 CM |
58 | #define mlx5_esw_has_fwd_fdb(dev) \ |
59 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
60 | ||
328edb49 | 61 | #define FDB_MAX_CHAIN 3 |
c92a0b94 | 62 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
63 | #define FDB_MAX_PRIO 16 |
64 | ||
5742df0f MHY |
65 | struct vport_ingress { |
66 | struct mlx5_flow_table *acl; | |
67 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
68 | struct mlx5_flow_group *allow_spoofchk_only_grp; | |
69 | struct mlx5_flow_group *allow_untagged_only_grp; | |
70 | struct mlx5_flow_group *drop_grp; | |
7445cfb1 JL |
71 | int modify_metadata_id; |
72 | struct mlx5_flow_handle *modify_metadata_rule; | |
74491de9 MB |
73 | struct mlx5_flow_handle *allow_rule; |
74 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 | 75 | struct mlx5_fc *drop_counter; |
5742df0f MHY |
76 | }; |
77 | ||
78 | struct vport_egress { | |
79 | struct mlx5_flow_table *acl; | |
80 | struct mlx5_flow_group *allowed_vlans_grp; | |
81 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
82 | struct mlx5_flow_handle *allowed_vlan; |
83 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 EE |
84 | struct mlx5_fc *drop_counter; |
85 | }; | |
86 | ||
87 | struct mlx5_vport_drop_stats { | |
88 | u64 rx_dropped; | |
89 | u64 tx_dropped; | |
5742df0f MHY |
90 | }; |
91 | ||
1ab2068a MHY |
92 | struct mlx5_vport_info { |
93 | u8 mac[ETH_ALEN]; | |
94 | u16 vlan; | |
95 | u8 qos; | |
96 | u64 node_guid; | |
97 | int link_state; | |
c9497c98 | 98 | u32 min_rate; |
1bd27b11 | 99 | u32 max_rate; |
1ab2068a MHY |
100 | bool spoofchk; |
101 | bool trusted; | |
102 | }; | |
103 | ||
073bb189 SM |
104 | struct mlx5_vport { |
105 | struct mlx5_core_dev *dev; | |
106 | int vport; | |
107 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 108 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
109 | struct mlx5_flow_handle *promisc_rule; |
110 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
111 | struct work_struct vport_change_handler; |
112 | ||
5742df0f MHY |
113 | struct vport_ingress ingress; |
114 | struct vport_egress egress; | |
115 | ||
1ab2068a MHY |
116 | struct mlx5_vport_info info; |
117 | ||
1bd27b11 MHY |
118 | struct { |
119 | bool enabled; | |
120 | u32 esw_tsar_ix; | |
c9497c98 | 121 | u32 bw_share; |
1bd27b11 MHY |
122 | } qos; |
123 | ||
073bb189 | 124 | bool enabled; |
81848731 | 125 | u16 enabled_events; |
073bb189 SM |
126 | }; |
127 | ||
e52c2802 PB |
128 | enum offloads_fdb_flags { |
129 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
130 | }; | |
131 | ||
132 | extern const unsigned int ESW_POOLS[4]; | |
133 | ||
134 | #define PRIO_LEVELS 2 | |
81848731 | 135 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
136 | union { |
137 | struct legacy_fdb { | |
52fff327 | 138 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
139 | struct mlx5_flow_group *addr_grp; |
140 | struct mlx5_flow_group *allmulti_grp; | |
141 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
142 | struct mlx5_flow_table *vepa_fdb; |
143 | struct mlx5_flow_handle *vepa_uplink_rule; | |
144 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 145 | } legacy; |
69697b6e OG |
146 | |
147 | struct offloads_fdb { | |
52fff327 | 148 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 149 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
150 | struct mlx5_flow_group *peer_miss_grp; |
151 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 152 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
153 | struct mlx5_flow_handle *miss_rule_uni; |
154 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 155 | int vlan_push_pop_refcount; |
e52c2802 PB |
156 | |
157 | struct { | |
158 | struct mlx5_flow_table *fdb; | |
159 | u32 num_rules; | |
160 | } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; | |
161 | /* Protects fdb_prio table */ | |
162 | struct mutex fdb_prio_lock; | |
163 | ||
164 | int fdb_left[ARRAY_SIZE(ESW_POOLS)]; | |
69697b6e | 165 | } offloads; |
6ab36e35 | 166 | }; |
e52c2802 | 167 | u32 flags; |
6ab36e35 OG |
168 | }; |
169 | ||
c116c6ee OG |
170 | struct mlx5_esw_offload { |
171 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 172 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 173 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
174 | struct list_head peer_flows; |
175 | struct mutex peer_mutex; | |
a54e20b4 | 176 | DECLARE_HASHTABLE(encap_tbl, 8); |
11c9c548 | 177 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); |
10caabda OS |
178 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
179 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
8693115a | 180 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 181 | u8 inline_mode; |
375f51e2 | 182 | u64 num_flows; |
98fdbea5 | 183 | enum devlink_eswitch_encap_mode encap; |
c116c6ee OG |
184 | }; |
185 | ||
0a0ab1d2 EC |
186 | /* E-Switch MC FDB table hash node */ |
187 | struct esw_mc_addr { /* SRIOV only */ | |
188 | struct l2addr_node node; | |
189 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
190 | u32 refcnt; | |
191 | }; | |
192 | ||
a3888f33 BW |
193 | struct mlx5_host_work { |
194 | struct work_struct work; | |
195 | struct mlx5_eswitch *esw; | |
196 | }; | |
197 | ||
cd56f929 | 198 | struct mlx5_esw_functions { |
a3888f33 BW |
199 | struct mlx5_nb nb; |
200 | u16 num_vfs; | |
201 | }; | |
202 | ||
7445cfb1 JL |
203 | enum { |
204 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
205 | }; | |
206 | ||
073bb189 SM |
207 | struct mlx5_eswitch { |
208 | struct mlx5_core_dev *dev; | |
6933a937 | 209 | struct mlx5_nb nb; |
81848731 SM |
210 | struct mlx5_eswitch_fdb fdb_table; |
211 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; | |
073bb189 SM |
212 | struct workqueue_struct *work_queue; |
213 | struct mlx5_vport *vports; | |
7445cfb1 | 214 | u32 flags; |
073bb189 | 215 | int total_vports; |
81848731 | 216 | int enabled_vports; |
dfcb1ed3 MHY |
217 | /* Synchronize between vport change events |
218 | * and async SRIOV admin state changes | |
219 | */ | |
220 | struct mutex state_lock; | |
0a0ab1d2 | 221 | struct esw_mc_addr mc_promisc; |
1bd27b11 MHY |
222 | |
223 | struct { | |
224 | bool enabled; | |
225 | u32 root_tsar_id; | |
226 | } qos; | |
227 | ||
c116c6ee | 228 | struct mlx5_esw_offload offloads; |
6ab36e35 | 229 | int mode; |
e52c2802 | 230 | int nvports; |
a1b3839a | 231 | u16 manager_vport; |
411ec9e0 | 232 | u16 first_host_vport; |
cd56f929 | 233 | struct mlx5_esw_functions esw_funcs; |
073bb189 SM |
234 | }; |
235 | ||
c9b99abc | 236 | void esw_offloads_cleanup(struct mlx5_eswitch *esw); |
062f4bf4 | 237 | int esw_offloads_init(struct mlx5_eswitch *esw); |
e8d31c4d MB |
238 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
239 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
18486737 EB |
240 | void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw, |
241 | struct mlx5_vport *vport); | |
242 | int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw, | |
243 | struct mlx5_vport *vport); | |
244 | void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw, | |
245 | struct mlx5_vport *vport); | |
246 | int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw, | |
247 | struct mlx5_vport *vport); | |
248 | void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw, | |
249 | struct mlx5_vport *vport); | |
250 | void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw, | |
251 | struct mlx5_vport *vport); | |
7445cfb1 JL |
252 | void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw, |
253 | struct mlx5_vport *vport); | |
766a0e97 | 254 | |
073bb189 SM |
255 | /* E-Switch API */ |
256 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
257 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
062f4bf4 | 258 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode); |
f6455de0 | 259 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw); |
77256579 | 260 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
02f3afd9 | 261 | u16 vport, u8 mac[ETH_ALEN]); |
77256579 | 262 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 263 | u16 vport, int link_state); |
9e7ea352 | 264 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 265 | u16 vport, u16 vlan, u8 qos); |
f942380c | 266 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 267 | u16 vport, bool spoofchk); |
1edc57e2 | 268 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
269 | u16 vport_num, bool setting); |
270 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 271 | u32 max_rate, u32 min_rate); |
8da202b2 HN |
272 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
273 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 274 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 275 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 276 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 277 | u16 vport, |
3b751a2a | 278 | struct ifla_vf_stats *vf_stats); |
159fe639 | 279 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 280 | |
57843868 JL |
281 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport, |
282 | void *in, int inlen); | |
283 | int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport, | |
284 | void *out, int outlen); | |
285 | ||
3d80d1a2 | 286 | struct mlx5_flow_spec; |
776b12b6 | 287 | struct mlx5_esw_flow_attr; |
10caabda OS |
288 | struct mlx5_termtbl_handle; |
289 | ||
290 | bool | |
291 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
292 | struct mlx5_flow_act *flow_act, | |
293 | struct mlx5_flow_spec *spec); | |
294 | ||
295 | struct mlx5_flow_handle * | |
296 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
297 | struct mlx5_flow_table *ft, | |
298 | struct mlx5_flow_spec *spec, | |
299 | struct mlx5_esw_flow_attr *attr, | |
300 | struct mlx5_flow_act *flow_act, | |
301 | struct mlx5_flow_destination *dest, | |
302 | int num_dest); | |
303 | ||
304 | void | |
305 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
306 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 307 | |
74491de9 | 308 | struct mlx5_flow_handle * |
3d80d1a2 OG |
309 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
310 | struct mlx5_flow_spec *spec, | |
776b12b6 | 311 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
312 | struct mlx5_flow_handle * |
313 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
314 | struct mlx5_flow_spec *spec, | |
315 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
316 | void |
317 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
318 | struct mlx5_flow_handle *rule, | |
319 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
320 | void |
321 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
322 | struct mlx5_flow_handle *rule, | |
323 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 324 | |
e52c2802 PB |
325 | bool |
326 | mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); | |
327 | ||
328 | u16 | |
329 | mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); | |
330 | ||
331 | u32 | |
332 | mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); | |
333 | ||
74491de9 | 334 | struct mlx5_flow_handle * |
02f3afd9 | 335 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 336 | struct mlx5_flow_destination *dest); |
fed9ce22 | 337 | |
e33dfe31 OG |
338 | enum { |
339 | SET_VLAN_STRIP = BIT(0), | |
340 | SET_VLAN_INSERT = BIT(1) | |
341 | }; | |
342 | ||
d708f902 OG |
343 | enum mlx5_flow_match_level { |
344 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
345 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
346 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
347 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
348 | }; | |
349 | ||
592d3651 CM |
350 | /* current maximum for flow based vport multicasting */ |
351 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
352 | ||
f493f155 EB |
353 | enum { |
354 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 355 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
356 | }; |
357 | ||
776b12b6 OG |
358 | struct mlx5_esw_flow_attr { |
359 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 360 | struct mlx5_core_dev *in_mdev; |
f9392795 | 361 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 362 | |
e85e02ba | 363 | int split_count; |
592d3651 CM |
364 | int out_count; |
365 | ||
776b12b6 | 366 | int action; |
cc495188 JL |
367 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
368 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
369 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
370 | u8 total_vlan; | |
f5f82476 | 371 | bool vlan_handled; |
df65a573 | 372 | struct { |
f493f155 | 373 | u32 flags; |
df65a573 EB |
374 | struct mlx5_eswitch_rep *rep; |
375 | struct mlx5_core_dev *mdev; | |
8c4dc42b | 376 | u32 encap_id; |
10caabda | 377 | struct mlx5_termtbl_handle *termtbl; |
df65a573 | 378 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
d7e75a32 | 379 | u32 mod_hdr_id; |
38aa51c1 | 380 | u8 match_level; |
6363651d | 381 | u8 tunnel_match_level; |
b8aee822 | 382 | struct mlx5_fc *counter; |
e52c2802 PB |
383 | u32 chain; |
384 | u16 prio; | |
385 | u32 dest_chain; | |
232c0013 | 386 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
387 | }; |
388 | ||
db7ff19e EB |
389 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
390 | struct netlink_ext_ack *extack); | |
feae9087 | 391 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
392 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
393 | struct netlink_ext_ack *extack); | |
bffaa916 | 394 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
062f4bf4 | 395 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode); |
98fdbea5 LR |
396 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
397 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 398 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
399 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
400 | enum devlink_eswitch_encap_mode *encap); | |
a4b97ab4 | 401 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 402 | |
f5f82476 OG |
403 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
404 | struct mlx5_esw_flow_attr *attr); | |
405 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
406 | struct mlx5_esw_flow_attr *attr); | |
407 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
02f3afd9 | 408 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 409 | |
cc495188 JL |
410 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
411 | u8 vlan_depth) | |
6acfbf38 | 412 | { |
cc495188 JL |
413 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
414 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
415 | ||
416 | if (vlan_depth == 1) | |
417 | return ret; | |
418 | ||
419 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
420 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
421 | } |
422 | ||
eff849b2 RL |
423 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
424 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
425 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
426 | struct mlx5_core_dev *dev1); | |
eff849b2 | 427 | |
dd28087c | 428 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 429 | |
69697b6e OG |
430 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
431 | ||
27b942fb PP |
432 | #define esw_info(__dev, format, ...) \ |
433 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 434 | |
27b942fb PP |
435 | #define esw_warn(__dev, format, ...) \ |
436 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
437 | |
438 | #define esw_debug(dev, format, ...) \ | |
439 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
440 | |
441 | /* The returned number is valid only when the dev is eswitch manager. */ | |
442 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
443 | { | |
444 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
445 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
446 | } | |
447 | ||
411ec9e0 BW |
448 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
449 | { | |
450 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
451 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
452 | } | |
453 | ||
6706a3b9 VP |
454 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) |
455 | { | |
456 | /* Ideally device should have the functions changed supported | |
457 | * capability regardless of it being ECPF or PF wherever such | |
458 | * event should be processed such as on eswitch manager device. | |
459 | * However, some ECPF based device might not have this capability | |
460 | * set. Hence OR for ECPF check to cover such device. | |
461 | */ | |
462 | return MLX5_CAP_ESW(dev, esw_functions_changed) || | |
463 | mlx5_core_is_ecpf_esw_manager(dev); | |
464 | } | |
465 | ||
5ae51620 BW |
466 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
467 | { | |
468 | /* Uplink always locate at the last element of the array.*/ | |
469 | return esw->total_vports - 1; | |
470 | } | |
471 | ||
81cd229c BW |
472 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
473 | { | |
474 | return esw->total_vports - 2; | |
475 | } | |
476 | ||
5ae51620 BW |
477 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
478 | u16 vport_num) | |
479 | { | |
81cd229c BW |
480 | if (vport_num == MLX5_VPORT_ECPF) { |
481 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
482 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
483 | return mlx5_eswitch_ecpf_idx(esw); | |
484 | } | |
485 | ||
5ae51620 BW |
486 | if (vport_num == MLX5_VPORT_UPLINK) |
487 | return mlx5_eswitch_uplink_idx(esw); | |
488 | ||
489 | return vport_num; | |
490 | } | |
491 | ||
02f3afd9 | 492 | static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, |
5ae51620 BW |
493 | int index) |
494 | { | |
81cd229c BW |
495 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
496 | mlx5_ecpf_vport_exists(esw->dev)) | |
497 | return MLX5_VPORT_ECPF; | |
498 | ||
5ae51620 BW |
499 | if (index == mlx5_eswitch_uplink_idx(esw)) |
500 | return MLX5_VPORT_UPLINK; | |
501 | ||
502 | return index; | |
503 | } | |
504 | ||
ee576ec1 SM |
505 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
506 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
507 | ||
786ef904 PP |
508 | /* The vport getter/iterator are only valid after esw->total_vports |
509 | * and vport->vport are initialized in mlx5_eswitch_init. | |
510 | */ | |
511 | #define mlx5_esw_for_all_vports(esw, i, vport) \ | |
512 | for ((i) = MLX5_VPORT_PF; \ | |
513 | (vport) = &(esw)->vports[i], \ | |
514 | (i) < (esw)->total_vports; (i)++) | |
515 | ||
516 | #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \ | |
517 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
518 | (vport) = &(esw)->vports[(i)], \ | |
519 | (i) <= (nvfs); (i)++) | |
520 | ||
521 | #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \ | |
522 | for ((i) = (nvfs); \ | |
523 | (vport) = &(esw)->vports[(i)], \ | |
524 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
525 | ||
526 | /* The rep getter/iterator are only valid after esw->total_vports | |
527 | * and vport->vport are initialized in mlx5_eswitch_init. | |
528 | */ | |
529 | #define mlx5_esw_for_all_reps(esw, i, rep) \ | |
530 | for ((i) = MLX5_VPORT_PF; \ | |
531 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
532 | (i) < (esw)->total_vports; (i)++) | |
533 | ||
534 | #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \ | |
535 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
536 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
537 | (i) <= (nvfs); (i)++) | |
538 | ||
539 | #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \ | |
540 | for ((i) = (nvfs); \ | |
541 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
542 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
543 | ||
544 | #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \ | |
545 | for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++) | |
546 | ||
547 | #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \ | |
548 | for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--) | |
549 | ||
411ec9e0 BW |
550 | /* Includes host PF (vport 0) if it's not esw manager. */ |
551 | #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \ | |
552 | for ((i) = (esw)->first_host_vport; \ | |
553 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
554 | (i) <= (nvfs); (i)++) | |
555 | ||
556 | #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \ | |
557 | for ((i) = (nvfs); \ | |
558 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
559 | (i) >= (esw)->first_host_vport; (i)--) | |
560 | ||
561 | #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \ | |
562 | for ((vport) = (esw)->first_host_vport; \ | |
563 | (vport) <= (nvfs); (vport)++) | |
564 | ||
565 | #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \ | |
566 | for ((vport) = (nvfs); \ | |
567 | (vport) >= (esw)->first_host_vport; (vport)--) | |
568 | ||
5d9986a3 BW |
569 | struct mlx5_vport *__must_check |
570 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
571 | ||
91d6291c PP |
572 | bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num); |
573 | ||
062f4bf4 | 574 | void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs); |
16fff98a | 575 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 576 | |
e80541ec SM |
577 | #else /* CONFIG_MLX5_ESWITCH */ |
578 | /* eswitch API stubs */ | |
579 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
580 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
062f4bf4 | 581 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; } |
f6455de0 | 582 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} |
eff849b2 | 583 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 584 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
dd28087c | 585 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 586 | { |
dd28087c | 587 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 588 | } |
328edb49 | 589 | |
062f4bf4 BW |
590 | static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {} |
591 | ||
328edb49 | 592 | #define FDB_MAX_CHAIN 1 |
c92a0b94 | 593 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
594 | #define FDB_MAX_PRIO 1 |
595 | ||
e80541ec SM |
596 | #endif /* CONFIG_MLX5_ESWITCH */ |
597 | ||
073bb189 | 598 | #endif /* __MLX5_ESWITCH_H__ */ |