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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
feae9087 | 38 | #include <net/devlink.h> |
073bb189 | 39 | #include <linux/mlx5/device.h> |
57cbd893 | 40 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 41 | #include <linux/mlx5/vport.h> |
cc495188 | 42 | #include <linux/mlx5/fs.h> |
eeb66cdb | 43 | #include "lib/mpfs.h" |
073bb189 | 44 | |
e80541ec SM |
45 | #ifdef CONFIG_MLX5_ESWITCH |
46 | ||
073bb189 SM |
47 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
48 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
49 | ||
50 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
51 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
52 | ||
c9497c98 MHY |
53 | #define MLX5_MIN_BW_SHARE 1 |
54 | ||
55 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
56 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
57 | ||
a842dd04 CM |
58 | #define mlx5_esw_has_fwd_fdb(dev) \ |
59 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
60 | ||
328edb49 | 61 | #define FDB_MAX_CHAIN 3 |
c92a0b94 | 62 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
63 | #define FDB_MAX_PRIO 16 |
64 | ||
5742df0f MHY |
65 | struct vport_ingress { |
66 | struct mlx5_flow_table *acl; | |
67 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
68 | struct mlx5_flow_group *allow_spoofchk_only_grp; | |
69 | struct mlx5_flow_group *allow_untagged_only_grp; | |
70 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
71 | struct mlx5_flow_handle *allow_rule; |
72 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 | 73 | struct mlx5_fc *drop_counter; |
5742df0f MHY |
74 | }; |
75 | ||
76 | struct vport_egress { | |
77 | struct mlx5_flow_table *acl; | |
78 | struct mlx5_flow_group *allowed_vlans_grp; | |
79 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
80 | struct mlx5_flow_handle *allowed_vlan; |
81 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 EE |
82 | struct mlx5_fc *drop_counter; |
83 | }; | |
84 | ||
85 | struct mlx5_vport_drop_stats { | |
86 | u64 rx_dropped; | |
87 | u64 tx_dropped; | |
5742df0f MHY |
88 | }; |
89 | ||
1ab2068a MHY |
90 | struct mlx5_vport_info { |
91 | u8 mac[ETH_ALEN]; | |
92 | u16 vlan; | |
93 | u8 qos; | |
94 | u64 node_guid; | |
95 | int link_state; | |
c9497c98 | 96 | u32 min_rate; |
1bd27b11 | 97 | u32 max_rate; |
1ab2068a MHY |
98 | bool spoofchk; |
99 | bool trusted; | |
100 | }; | |
101 | ||
073bb189 SM |
102 | struct mlx5_vport { |
103 | struct mlx5_core_dev *dev; | |
104 | int vport; | |
105 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 106 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
107 | struct mlx5_flow_handle *promisc_rule; |
108 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
109 | struct work_struct vport_change_handler; |
110 | ||
5742df0f MHY |
111 | struct vport_ingress ingress; |
112 | struct vport_egress egress; | |
113 | ||
1ab2068a MHY |
114 | struct mlx5_vport_info info; |
115 | ||
1bd27b11 MHY |
116 | struct { |
117 | bool enabled; | |
118 | u32 esw_tsar_ix; | |
c9497c98 | 119 | u32 bw_share; |
1bd27b11 MHY |
120 | } qos; |
121 | ||
073bb189 | 122 | bool enabled; |
81848731 | 123 | u16 enabled_events; |
073bb189 SM |
124 | }; |
125 | ||
e52c2802 PB |
126 | enum offloads_fdb_flags { |
127 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
128 | }; | |
129 | ||
130 | extern const unsigned int ESW_POOLS[4]; | |
131 | ||
132 | #define PRIO_LEVELS 2 | |
81848731 | 133 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
134 | union { |
135 | struct legacy_fdb { | |
52fff327 | 136 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
137 | struct mlx5_flow_group *addr_grp; |
138 | struct mlx5_flow_group *allmulti_grp; | |
139 | struct mlx5_flow_group *promisc_grp; | |
140 | } legacy; | |
69697b6e OG |
141 | |
142 | struct offloads_fdb { | |
52fff327 | 143 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 144 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
145 | struct mlx5_flow_group *peer_miss_grp; |
146 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 147 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
148 | struct mlx5_flow_handle *miss_rule_uni; |
149 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 150 | int vlan_push_pop_refcount; |
e52c2802 PB |
151 | |
152 | struct { | |
153 | struct mlx5_flow_table *fdb; | |
154 | u32 num_rules; | |
155 | } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; | |
156 | /* Protects fdb_prio table */ | |
157 | struct mutex fdb_prio_lock; | |
158 | ||
159 | int fdb_left[ARRAY_SIZE(ESW_POOLS)]; | |
69697b6e | 160 | } offloads; |
6ab36e35 | 161 | }; |
e52c2802 | 162 | u32 flags; |
6ab36e35 OG |
163 | }; |
164 | ||
c116c6ee OG |
165 | struct mlx5_esw_offload { |
166 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 167 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 168 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
169 | struct list_head peer_flows; |
170 | struct mutex peer_mutex; | |
a54e20b4 | 171 | DECLARE_HASHTABLE(encap_tbl, 8); |
11c9c548 | 172 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); |
bffaa916 | 173 | u8 inline_mode; |
375f51e2 | 174 | u64 num_flows; |
7768d197 | 175 | u8 encap; |
c116c6ee OG |
176 | }; |
177 | ||
0a0ab1d2 EC |
178 | /* E-Switch MC FDB table hash node */ |
179 | struct esw_mc_addr { /* SRIOV only */ | |
180 | struct l2addr_node node; | |
181 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
182 | u32 refcnt; | |
183 | }; | |
184 | ||
073bb189 SM |
185 | struct mlx5_eswitch { |
186 | struct mlx5_core_dev *dev; | |
6933a937 | 187 | struct mlx5_nb nb; |
81848731 SM |
188 | struct mlx5_eswitch_fdb fdb_table; |
189 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; | |
073bb189 SM |
190 | struct workqueue_struct *work_queue; |
191 | struct mlx5_vport *vports; | |
192 | int total_vports; | |
81848731 | 193 | int enabled_vports; |
dfcb1ed3 MHY |
194 | /* Synchronize between vport change events |
195 | * and async SRIOV admin state changes | |
196 | */ | |
197 | struct mutex state_lock; | |
0a0ab1d2 | 198 | struct esw_mc_addr mc_promisc; |
1bd27b11 MHY |
199 | |
200 | struct { | |
201 | bool enabled; | |
202 | u32 root_tsar_id; | |
203 | } qos; | |
204 | ||
c116c6ee | 205 | struct mlx5_esw_offload offloads; |
6ab36e35 | 206 | int mode; |
e52c2802 | 207 | int nvports; |
a1b3839a | 208 | u16 manager_vport; |
073bb189 SM |
209 | }; |
210 | ||
c9b99abc BW |
211 | void esw_offloads_cleanup(struct mlx5_eswitch *esw); |
212 | int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports, | |
213 | int total_nvports); | |
e8d31c4d MB |
214 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
215 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
766a0e97 | 216 | |
073bb189 SM |
217 | /* E-Switch API */ |
218 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
219 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
6ab36e35 | 220 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode); |
81848731 | 221 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw); |
77256579 SM |
222 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
223 | int vport, u8 mac[ETH_ALEN]); | |
224 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
225 | int vport, int link_state); | |
9e7ea352 SM |
226 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
227 | int vport, u16 vlan, u8 qos); | |
f942380c MHY |
228 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
229 | int vport, bool spoofchk); | |
1edc57e2 MHY |
230 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
231 | int vport_num, bool setting); | |
c9497c98 MHY |
232 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport, |
233 | u32 max_rate, u32 min_rate); | |
77256579 SM |
234 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
235 | int vport, struct ifla_vf_info *ivi); | |
3b751a2a SM |
236 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
237 | int vport, | |
238 | struct ifla_vf_stats *vf_stats); | |
159fe639 | 239 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 240 | |
3d80d1a2 | 241 | struct mlx5_flow_spec; |
776b12b6 | 242 | struct mlx5_esw_flow_attr; |
3d80d1a2 | 243 | |
74491de9 | 244 | struct mlx5_flow_handle * |
3d80d1a2 OG |
245 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
246 | struct mlx5_flow_spec *spec, | |
776b12b6 | 247 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
248 | struct mlx5_flow_handle * |
249 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
250 | struct mlx5_flow_spec *spec, | |
251 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
252 | void |
253 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
254 | struct mlx5_flow_handle *rule, | |
255 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
256 | void |
257 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
258 | struct mlx5_flow_handle *rule, | |
259 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 260 | |
e52c2802 PB |
261 | bool |
262 | mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); | |
263 | ||
264 | u16 | |
265 | mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); | |
266 | ||
267 | u32 | |
268 | mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); | |
269 | ||
74491de9 | 270 | struct mlx5_flow_handle * |
c966f7d5 GT |
271 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, |
272 | struct mlx5_flow_destination *dest); | |
fed9ce22 | 273 | |
e33dfe31 OG |
274 | enum { |
275 | SET_VLAN_STRIP = BIT(0), | |
276 | SET_VLAN_INSERT = BIT(1) | |
277 | }; | |
278 | ||
d708f902 OG |
279 | enum mlx5_flow_match_level { |
280 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
281 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
282 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
283 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
284 | }; | |
285 | ||
592d3651 CM |
286 | /* current maximum for flow based vport multicasting */ |
287 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
288 | ||
f493f155 EB |
289 | enum { |
290 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 291 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
292 | }; |
293 | ||
776b12b6 OG |
294 | struct mlx5_esw_flow_attr { |
295 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 296 | struct mlx5_core_dev *in_mdev; |
f9392795 | 297 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 298 | |
e85e02ba | 299 | int split_count; |
592d3651 CM |
300 | int out_count; |
301 | ||
776b12b6 | 302 | int action; |
cc495188 JL |
303 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
304 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
305 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
306 | u8 total_vlan; | |
f5f82476 | 307 | bool vlan_handled; |
df65a573 | 308 | struct { |
f493f155 | 309 | u32 flags; |
df65a573 EB |
310 | struct mlx5_eswitch_rep *rep; |
311 | struct mlx5_core_dev *mdev; | |
8c4dc42b | 312 | u32 encap_id; |
df65a573 | 313 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
d7e75a32 | 314 | u32 mod_hdr_id; |
38aa51c1 | 315 | u8 match_level; |
6363651d | 316 | u8 tunnel_match_level; |
b8aee822 | 317 | struct mlx5_fc *counter; |
e52c2802 PB |
318 | u32 chain; |
319 | u16 prio; | |
320 | u32 dest_chain; | |
232c0013 | 321 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
322 | }; |
323 | ||
db7ff19e EB |
324 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
325 | struct netlink_ext_ack *extack); | |
feae9087 | 326 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
327 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
328 | struct netlink_ext_ack *extack); | |
bffaa916 RD |
329 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
330 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode); | |
db7ff19e EB |
331 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap, |
332 | struct netlink_ext_ack *extack); | |
7768d197 | 333 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap); |
a4b97ab4 | 334 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 335 | |
f5f82476 OG |
336 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
337 | struct mlx5_esw_flow_attr *attr); | |
338 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
339 | struct mlx5_esw_flow_attr *attr); | |
340 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
341 | int vport, u16 vlan, u8 qos, u8 set_flags); | |
342 | ||
cc495188 JL |
343 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
344 | u8 vlan_depth) | |
6acfbf38 | 345 | { |
cc495188 JL |
346 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
347 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
348 | ||
349 | if (vlan_depth == 1) | |
350 | return ret; | |
351 | ||
352 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
353 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
354 | } |
355 | ||
eff849b2 RL |
356 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
357 | struct mlx5_core_dev *dev1); | |
358 | ||
69697b6e OG |
359 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
360 | ||
361 | #define esw_info(dev, format, ...) \ | |
362 | pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
363 | ||
364 | #define esw_warn(dev, format, ...) \ | |
365 | pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
366 | ||
367 | #define esw_debug(dev, format, ...) \ | |
368 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
369 | |
370 | /* The returned number is valid only when the dev is eswitch manager. */ | |
371 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
372 | { | |
373 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
374 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
375 | } | |
376 | ||
5ae51620 BW |
377 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
378 | { | |
379 | /* Uplink always locate at the last element of the array.*/ | |
380 | return esw->total_vports - 1; | |
381 | } | |
382 | ||
81cd229c BW |
383 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
384 | { | |
385 | return esw->total_vports - 2; | |
386 | } | |
387 | ||
5ae51620 BW |
388 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
389 | u16 vport_num) | |
390 | { | |
81cd229c BW |
391 | if (vport_num == MLX5_VPORT_ECPF) { |
392 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
393 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
394 | return mlx5_eswitch_ecpf_idx(esw); | |
395 | } | |
396 | ||
5ae51620 BW |
397 | if (vport_num == MLX5_VPORT_UPLINK) |
398 | return mlx5_eswitch_uplink_idx(esw); | |
399 | ||
400 | return vport_num; | |
401 | } | |
402 | ||
403 | static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, | |
404 | int index) | |
405 | { | |
81cd229c BW |
406 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
407 | mlx5_ecpf_vport_exists(esw->dev)) | |
408 | return MLX5_VPORT_ECPF; | |
409 | ||
5ae51620 BW |
410 | if (index == mlx5_eswitch_uplink_idx(esw)) |
411 | return MLX5_VPORT_UPLINK; | |
412 | ||
413 | return index; | |
414 | } | |
415 | ||
e80541ec SM |
416 | #else /* CONFIG_MLX5_ESWITCH */ |
417 | /* eswitch API stubs */ | |
418 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
419 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
e80541ec SM |
420 | static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; } |
421 | static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {} | |
eff849b2 | 422 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
328edb49 PB |
423 | |
424 | #define FDB_MAX_CHAIN 1 | |
c92a0b94 | 425 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
426 | #define FDB_MAX_PRIO 1 |
427 | ||
e80541ec SM |
428 | #endif /* CONFIG_MLX5_ESWITCH */ |
429 | ||
073bb189 | 430 | #endif /* __MLX5_ESWITCH_H__ */ |