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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
feae9087 | 38 | #include <net/devlink.h> |
073bb189 | 39 | #include <linux/mlx5/device.h> |
57cbd893 | 40 | #include <linux/mlx5/eswitch.h> |
cc495188 | 41 | #include <linux/mlx5/fs.h> |
eeb66cdb | 42 | #include "lib/mpfs.h" |
073bb189 | 43 | |
e80541ec SM |
44 | #ifdef CONFIG_MLX5_ESWITCH |
45 | ||
073bb189 SM |
46 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
47 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
48 | ||
49 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
50 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
51 | ||
cb67b832 HHZ |
52 | #define FDB_UPLINK_VPORT 0xffff |
53 | ||
c9497c98 MHY |
54 | #define MLX5_MIN_BW_SHARE 1 |
55 | ||
56 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
57 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
58 | ||
a842dd04 CM |
59 | #define mlx5_esw_has_fwd_fdb(dev) \ |
60 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
61 | ||
5742df0f MHY |
62 | struct vport_ingress { |
63 | struct mlx5_flow_table *acl; | |
64 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
65 | struct mlx5_flow_group *allow_spoofchk_only_grp; | |
66 | struct mlx5_flow_group *allow_untagged_only_grp; | |
67 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
68 | struct mlx5_flow_handle *allow_rule; |
69 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 | 70 | struct mlx5_fc *drop_counter; |
5742df0f MHY |
71 | }; |
72 | ||
73 | struct vport_egress { | |
74 | struct mlx5_flow_table *acl; | |
75 | struct mlx5_flow_group *allowed_vlans_grp; | |
76 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
77 | struct mlx5_flow_handle *allowed_vlan; |
78 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 EE |
79 | struct mlx5_fc *drop_counter; |
80 | }; | |
81 | ||
82 | struct mlx5_vport_drop_stats { | |
83 | u64 rx_dropped; | |
84 | u64 tx_dropped; | |
5742df0f MHY |
85 | }; |
86 | ||
1ab2068a MHY |
87 | struct mlx5_vport_info { |
88 | u8 mac[ETH_ALEN]; | |
89 | u16 vlan; | |
90 | u8 qos; | |
91 | u64 node_guid; | |
92 | int link_state; | |
c9497c98 | 93 | u32 min_rate; |
1bd27b11 | 94 | u32 max_rate; |
1ab2068a MHY |
95 | bool spoofchk; |
96 | bool trusted; | |
97 | }; | |
98 | ||
073bb189 SM |
99 | struct mlx5_vport { |
100 | struct mlx5_core_dev *dev; | |
101 | int vport; | |
102 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 103 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
104 | struct mlx5_flow_handle *promisc_rule; |
105 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
106 | struct work_struct vport_change_handler; |
107 | ||
5742df0f MHY |
108 | struct vport_ingress ingress; |
109 | struct vport_egress egress; | |
110 | ||
1ab2068a MHY |
111 | struct mlx5_vport_info info; |
112 | ||
1bd27b11 MHY |
113 | struct { |
114 | bool enabled; | |
115 | u32 esw_tsar_ix; | |
c9497c98 | 116 | u32 bw_share; |
1bd27b11 MHY |
117 | } qos; |
118 | ||
073bb189 | 119 | bool enabled; |
81848731 | 120 | u16 enabled_events; |
073bb189 SM |
121 | }; |
122 | ||
81848731 | 123 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
124 | union { |
125 | struct legacy_fdb { | |
52fff327 | 126 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
127 | struct mlx5_flow_group *addr_grp; |
128 | struct mlx5_flow_group *allmulti_grp; | |
129 | struct mlx5_flow_group *promisc_grp; | |
130 | } legacy; | |
69697b6e OG |
131 | |
132 | struct offloads_fdb { | |
52fff327 | 133 | struct mlx5_flow_table *fast_fdb; |
a842dd04 | 134 | struct mlx5_flow_table *fwd_fdb; |
52fff327 | 135 | struct mlx5_flow_table *slow_fdb; |
69697b6e OG |
136 | struct mlx5_flow_group *send_to_vport_grp; |
137 | struct mlx5_flow_group *miss_grp; | |
f80be543 MB |
138 | struct mlx5_flow_handle *miss_rule_uni; |
139 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 140 | int vlan_push_pop_refcount; |
69697b6e | 141 | } offloads; |
6ab36e35 OG |
142 | }; |
143 | }; | |
144 | ||
c116c6ee OG |
145 | struct mlx5_esw_offload { |
146 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 147 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 148 | struct mlx5_eswitch_rep *vport_reps; |
a54e20b4 | 149 | DECLARE_HASHTABLE(encap_tbl, 8); |
11c9c548 | 150 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); |
bffaa916 | 151 | u8 inline_mode; |
375f51e2 | 152 | u64 num_flows; |
7768d197 | 153 | u8 encap; |
c116c6ee OG |
154 | }; |
155 | ||
0a0ab1d2 EC |
156 | /* E-Switch MC FDB table hash node */ |
157 | struct esw_mc_addr { /* SRIOV only */ | |
158 | struct l2addr_node node; | |
159 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
160 | u32 refcnt; | |
161 | }; | |
162 | ||
073bb189 SM |
163 | struct mlx5_eswitch { |
164 | struct mlx5_core_dev *dev; | |
81848731 SM |
165 | struct mlx5_eswitch_fdb fdb_table; |
166 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; | |
073bb189 SM |
167 | struct workqueue_struct *work_queue; |
168 | struct mlx5_vport *vports; | |
169 | int total_vports; | |
81848731 | 170 | int enabled_vports; |
dfcb1ed3 MHY |
171 | /* Synchronize between vport change events |
172 | * and async SRIOV admin state changes | |
173 | */ | |
174 | struct mutex state_lock; | |
0a0ab1d2 | 175 | struct esw_mc_addr mc_promisc; |
1bd27b11 MHY |
176 | |
177 | struct { | |
178 | bool enabled; | |
179 | u32 root_tsar_id; | |
180 | } qos; | |
181 | ||
c116c6ee | 182 | struct mlx5_esw_offload offloads; |
6ab36e35 | 183 | int mode; |
073bb189 SM |
184 | }; |
185 | ||
766a0e97 BX |
186 | void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports); |
187 | int esw_offloads_init(struct mlx5_eswitch *esw, int nvports); | |
e8d31c4d MB |
188 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
189 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
766a0e97 | 190 | |
073bb189 SM |
191 | /* E-Switch API */ |
192 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
193 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
194 | void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe); | |
6ab36e35 | 195 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode); |
81848731 | 196 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw); |
77256579 SM |
197 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
198 | int vport, u8 mac[ETH_ALEN]); | |
199 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
200 | int vport, int link_state); | |
9e7ea352 SM |
201 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
202 | int vport, u16 vlan, u8 qos); | |
f942380c MHY |
203 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
204 | int vport, bool spoofchk); | |
1edc57e2 MHY |
205 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
206 | int vport_num, bool setting); | |
c9497c98 MHY |
207 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport, |
208 | u32 max_rate, u32 min_rate); | |
77256579 SM |
209 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
210 | int vport, struct ifla_vf_info *ivi); | |
3b751a2a SM |
211 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
212 | int vport, | |
213 | struct ifla_vf_stats *vf_stats); | |
159fe639 | 214 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 215 | |
3d80d1a2 | 216 | struct mlx5_flow_spec; |
776b12b6 | 217 | struct mlx5_esw_flow_attr; |
3d80d1a2 | 218 | |
74491de9 | 219 | struct mlx5_flow_handle * |
3d80d1a2 OG |
220 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
221 | struct mlx5_flow_spec *spec, | |
776b12b6 | 222 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
223 | struct mlx5_flow_handle * |
224 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
225 | struct mlx5_flow_spec *spec, | |
226 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
227 | void |
228 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
229 | struct mlx5_flow_handle *rule, | |
230 | struct mlx5_esw_flow_attr *attr); | |
231 | ||
74491de9 | 232 | struct mlx5_flow_handle * |
c966f7d5 GT |
233 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, |
234 | struct mlx5_flow_destination *dest); | |
fed9ce22 | 235 | |
e33dfe31 OG |
236 | enum { |
237 | SET_VLAN_STRIP = BIT(0), | |
238 | SET_VLAN_INSERT = BIT(1) | |
239 | }; | |
240 | ||
d708f902 OG |
241 | enum mlx5_flow_match_level { |
242 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
243 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
244 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
245 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
246 | }; | |
247 | ||
592d3651 CM |
248 | /* current maximum for flow based vport multicasting */ |
249 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
250 | ||
776b12b6 OG |
251 | struct mlx5_esw_flow_attr { |
252 | struct mlx5_eswitch_rep *in_rep; | |
592d3651 CM |
253 | struct mlx5_eswitch_rep *out_rep[MLX5_MAX_FLOW_FWD_VPORTS]; |
254 | struct mlx5_core_dev *out_mdev[MLX5_MAX_FLOW_FWD_VPORTS]; | |
10ff5359 | 255 | struct mlx5_core_dev *in_mdev; |
776b12b6 | 256 | |
592d3651 CM |
257 | int mirror_count; |
258 | int out_count; | |
259 | ||
776b12b6 | 260 | int action; |
cc495188 JL |
261 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
262 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
263 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
264 | u8 total_vlan; | |
f5f82476 | 265 | bool vlan_handled; |
45247bf2 | 266 | u32 encap_id; |
d7e75a32 | 267 | u32 mod_hdr_id; |
38aa51c1 | 268 | u8 match_level; |
b8aee822 | 269 | struct mlx5_fc *counter; |
232c0013 | 270 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
271 | }; |
272 | ||
db7ff19e EB |
273 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
274 | struct netlink_ext_ack *extack); | |
feae9087 | 275 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
276 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
277 | struct netlink_ext_ack *extack); | |
bffaa916 RD |
278 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
279 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode); | |
db7ff19e EB |
280 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap, |
281 | struct netlink_ext_ack *extack); | |
7768d197 | 282 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap); |
a4b97ab4 | 283 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 284 | |
f5f82476 OG |
285 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
286 | struct mlx5_esw_flow_attr *attr); | |
287 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
288 | struct mlx5_esw_flow_attr *attr); | |
289 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
290 | int vport, u16 vlan, u8 qos, u8 set_flags); | |
291 | ||
cc495188 JL |
292 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
293 | u8 vlan_depth) | |
6acfbf38 | 294 | { |
cc495188 JL |
295 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
296 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
297 | ||
298 | if (vlan_depth == 1) | |
299 | return ret; | |
300 | ||
301 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
302 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
303 | } |
304 | ||
69697b6e OG |
305 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
306 | ||
307 | #define esw_info(dev, format, ...) \ | |
308 | pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
309 | ||
310 | #define esw_warn(dev, format, ...) \ | |
311 | pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__) | |
312 | ||
313 | #define esw_debug(dev, format, ...) \ | |
314 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
e80541ec SM |
315 | #else /* CONFIG_MLX5_ESWITCH */ |
316 | /* eswitch API stubs */ | |
317 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
318 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
319 | static inline void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) {} | |
320 | static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; } | |
321 | static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {} | |
322 | #endif /* CONFIG_MLX5_ESWITCH */ | |
323 | ||
073bb189 | 324 | #endif /* __MLX5_ESWITCH_H__ */ |