]>
Commit | Line | Data |
---|---|---|
073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
feae9087 | 38 | #include <net/devlink.h> |
073bb189 | 39 | #include <linux/mlx5/device.h> |
57cbd893 | 40 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 41 | #include <linux/mlx5/vport.h> |
cc495188 | 42 | #include <linux/mlx5/fs.h> |
eeb66cdb | 43 | #include "lib/mpfs.h" |
073bb189 | 44 | |
e80541ec SM |
45 | #ifdef CONFIG_MLX5_ESWITCH |
46 | ||
073bb189 SM |
47 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
48 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
49 | ||
50 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
51 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
52 | ||
c9497c98 MHY |
53 | #define MLX5_MIN_BW_SHARE 1 |
54 | ||
55 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
56 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
57 | ||
a842dd04 CM |
58 | #define mlx5_esw_has_fwd_fdb(dev) \ |
59 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
60 | ||
328edb49 | 61 | #define FDB_MAX_CHAIN 3 |
c92a0b94 | 62 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
63 | #define FDB_MAX_PRIO 16 |
64 | ||
5742df0f MHY |
65 | struct vport_ingress { |
66 | struct mlx5_flow_table *acl; | |
67 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
68 | struct mlx5_flow_group *allow_spoofchk_only_grp; | |
69 | struct mlx5_flow_group *allow_untagged_only_grp; | |
70 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
71 | struct mlx5_flow_handle *allow_rule; |
72 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 | 73 | struct mlx5_fc *drop_counter; |
5742df0f MHY |
74 | }; |
75 | ||
76 | struct vport_egress { | |
77 | struct mlx5_flow_table *acl; | |
78 | struct mlx5_flow_group *allowed_vlans_grp; | |
79 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
80 | struct mlx5_flow_handle *allowed_vlan; |
81 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 EE |
82 | struct mlx5_fc *drop_counter; |
83 | }; | |
84 | ||
85 | struct mlx5_vport_drop_stats { | |
86 | u64 rx_dropped; | |
87 | u64 tx_dropped; | |
5742df0f MHY |
88 | }; |
89 | ||
1ab2068a MHY |
90 | struct mlx5_vport_info { |
91 | u8 mac[ETH_ALEN]; | |
92 | u16 vlan; | |
93 | u8 qos; | |
94 | u64 node_guid; | |
95 | int link_state; | |
c9497c98 | 96 | u32 min_rate; |
1bd27b11 | 97 | u32 max_rate; |
1ab2068a MHY |
98 | bool spoofchk; |
99 | bool trusted; | |
100 | }; | |
101 | ||
073bb189 SM |
102 | struct mlx5_vport { |
103 | struct mlx5_core_dev *dev; | |
104 | int vport; | |
105 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 106 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
107 | struct mlx5_flow_handle *promisc_rule; |
108 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
109 | struct work_struct vport_change_handler; |
110 | ||
5742df0f MHY |
111 | struct vport_ingress ingress; |
112 | struct vport_egress egress; | |
113 | ||
1ab2068a MHY |
114 | struct mlx5_vport_info info; |
115 | ||
1bd27b11 MHY |
116 | struct { |
117 | bool enabled; | |
118 | u32 esw_tsar_ix; | |
c9497c98 | 119 | u32 bw_share; |
1bd27b11 MHY |
120 | } qos; |
121 | ||
073bb189 | 122 | bool enabled; |
81848731 | 123 | u16 enabled_events; |
073bb189 SM |
124 | }; |
125 | ||
e52c2802 PB |
126 | enum offloads_fdb_flags { |
127 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
128 | }; | |
129 | ||
130 | extern const unsigned int ESW_POOLS[4]; | |
131 | ||
132 | #define PRIO_LEVELS 2 | |
81848731 | 133 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
134 | union { |
135 | struct legacy_fdb { | |
52fff327 | 136 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
137 | struct mlx5_flow_group *addr_grp; |
138 | struct mlx5_flow_group *allmulti_grp; | |
139 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
140 | struct mlx5_flow_table *vepa_fdb; |
141 | struct mlx5_flow_handle *vepa_uplink_rule; | |
142 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 143 | } legacy; |
69697b6e OG |
144 | |
145 | struct offloads_fdb { | |
52fff327 | 146 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 147 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
148 | struct mlx5_flow_group *peer_miss_grp; |
149 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 150 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
151 | struct mlx5_flow_handle *miss_rule_uni; |
152 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 153 | int vlan_push_pop_refcount; |
e52c2802 PB |
154 | |
155 | struct { | |
156 | struct mlx5_flow_table *fdb; | |
157 | u32 num_rules; | |
158 | } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; | |
159 | /* Protects fdb_prio table */ | |
160 | struct mutex fdb_prio_lock; | |
161 | ||
162 | int fdb_left[ARRAY_SIZE(ESW_POOLS)]; | |
69697b6e | 163 | } offloads; |
6ab36e35 | 164 | }; |
e52c2802 | 165 | u32 flags; |
6ab36e35 OG |
166 | }; |
167 | ||
c116c6ee OG |
168 | struct mlx5_esw_offload { |
169 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 170 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 171 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
172 | struct list_head peer_flows; |
173 | struct mutex peer_mutex; | |
a54e20b4 | 174 | DECLARE_HASHTABLE(encap_tbl, 8); |
11c9c548 | 175 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); |
8693115a | 176 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 177 | u8 inline_mode; |
375f51e2 | 178 | u64 num_flows; |
98fdbea5 | 179 | enum devlink_eswitch_encap_mode encap; |
c116c6ee OG |
180 | }; |
181 | ||
0a0ab1d2 EC |
182 | /* E-Switch MC FDB table hash node */ |
183 | struct esw_mc_addr { /* SRIOV only */ | |
184 | struct l2addr_node node; | |
185 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
186 | u32 refcnt; | |
187 | }; | |
188 | ||
a3888f33 BW |
189 | struct mlx5_host_work { |
190 | struct work_struct work; | |
191 | struct mlx5_eswitch *esw; | |
192 | }; | |
193 | ||
cd56f929 | 194 | struct mlx5_esw_functions { |
a3888f33 BW |
195 | struct mlx5_nb nb; |
196 | u16 num_vfs; | |
197 | }; | |
198 | ||
073bb189 SM |
199 | struct mlx5_eswitch { |
200 | struct mlx5_core_dev *dev; | |
6933a937 | 201 | struct mlx5_nb nb; |
81848731 SM |
202 | struct mlx5_eswitch_fdb fdb_table; |
203 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; | |
073bb189 SM |
204 | struct workqueue_struct *work_queue; |
205 | struct mlx5_vport *vports; | |
206 | int total_vports; | |
81848731 | 207 | int enabled_vports; |
dfcb1ed3 MHY |
208 | /* Synchronize between vport change events |
209 | * and async SRIOV admin state changes | |
210 | */ | |
211 | struct mutex state_lock; | |
0a0ab1d2 | 212 | struct esw_mc_addr mc_promisc; |
1bd27b11 MHY |
213 | |
214 | struct { | |
215 | bool enabled; | |
216 | u32 root_tsar_id; | |
217 | } qos; | |
218 | ||
c116c6ee | 219 | struct mlx5_esw_offload offloads; |
6ab36e35 | 220 | int mode; |
e52c2802 | 221 | int nvports; |
a1b3839a | 222 | u16 manager_vport; |
cd56f929 | 223 | struct mlx5_esw_functions esw_funcs; |
073bb189 SM |
224 | }; |
225 | ||
c9b99abc BW |
226 | void esw_offloads_cleanup(struct mlx5_eswitch *esw); |
227 | int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports, | |
228 | int total_nvports); | |
e8d31c4d MB |
229 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
230 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
18486737 EB |
231 | void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw, |
232 | struct mlx5_vport *vport); | |
233 | int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw, | |
234 | struct mlx5_vport *vport); | |
235 | void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw, | |
236 | struct mlx5_vport *vport); | |
237 | int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw, | |
238 | struct mlx5_vport *vport); | |
239 | void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw, | |
240 | struct mlx5_vport *vport); | |
241 | void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw, | |
242 | struct mlx5_vport *vport); | |
766a0e97 | 243 | |
073bb189 SM |
244 | /* E-Switch API */ |
245 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
246 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
6ab36e35 | 247 | int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode); |
81848731 | 248 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw); |
77256579 SM |
249 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
250 | int vport, u8 mac[ETH_ALEN]); | |
251 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, | |
252 | int vport, int link_state); | |
9e7ea352 SM |
253 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
254 | int vport, u16 vlan, u8 qos); | |
f942380c MHY |
255 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
256 | int vport, bool spoofchk); | |
1edc57e2 MHY |
257 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
258 | int vport_num, bool setting); | |
c9497c98 MHY |
259 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport, |
260 | u32 max_rate, u32 min_rate); | |
8da202b2 HN |
261 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
262 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 SM |
263 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
264 | int vport, struct ifla_vf_info *ivi); | |
3b751a2a SM |
265 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
266 | int vport, | |
267 | struct ifla_vf_stats *vf_stats); | |
159fe639 | 268 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 269 | |
3d80d1a2 | 270 | struct mlx5_flow_spec; |
776b12b6 | 271 | struct mlx5_esw_flow_attr; |
3d80d1a2 | 272 | |
74491de9 | 273 | struct mlx5_flow_handle * |
3d80d1a2 OG |
274 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
275 | struct mlx5_flow_spec *spec, | |
776b12b6 | 276 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
277 | struct mlx5_flow_handle * |
278 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
279 | struct mlx5_flow_spec *spec, | |
280 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
281 | void |
282 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
283 | struct mlx5_flow_handle *rule, | |
284 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
285 | void |
286 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
287 | struct mlx5_flow_handle *rule, | |
288 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 289 | |
e52c2802 PB |
290 | bool |
291 | mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); | |
292 | ||
293 | u16 | |
294 | mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); | |
295 | ||
296 | u32 | |
297 | mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); | |
298 | ||
74491de9 | 299 | struct mlx5_flow_handle * |
c966f7d5 GT |
300 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, |
301 | struct mlx5_flow_destination *dest); | |
fed9ce22 | 302 | |
e33dfe31 OG |
303 | enum { |
304 | SET_VLAN_STRIP = BIT(0), | |
305 | SET_VLAN_INSERT = BIT(1) | |
306 | }; | |
307 | ||
d708f902 OG |
308 | enum mlx5_flow_match_level { |
309 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
310 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
311 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
312 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
313 | }; | |
314 | ||
592d3651 CM |
315 | /* current maximum for flow based vport multicasting */ |
316 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
317 | ||
f493f155 EB |
318 | enum { |
319 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 320 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
321 | }; |
322 | ||
776b12b6 OG |
323 | struct mlx5_esw_flow_attr { |
324 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 325 | struct mlx5_core_dev *in_mdev; |
f9392795 | 326 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 327 | |
e85e02ba | 328 | int split_count; |
592d3651 CM |
329 | int out_count; |
330 | ||
776b12b6 | 331 | int action; |
cc495188 JL |
332 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
333 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
334 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
335 | u8 total_vlan; | |
f5f82476 | 336 | bool vlan_handled; |
df65a573 | 337 | struct { |
f493f155 | 338 | u32 flags; |
df65a573 EB |
339 | struct mlx5_eswitch_rep *rep; |
340 | struct mlx5_core_dev *mdev; | |
8c4dc42b | 341 | u32 encap_id; |
df65a573 | 342 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
d7e75a32 | 343 | u32 mod_hdr_id; |
38aa51c1 | 344 | u8 match_level; |
6363651d | 345 | u8 tunnel_match_level; |
b8aee822 | 346 | struct mlx5_fc *counter; |
e52c2802 PB |
347 | u32 chain; |
348 | u16 prio; | |
349 | u32 dest_chain; | |
232c0013 | 350 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
351 | }; |
352 | ||
db7ff19e EB |
353 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
354 | struct netlink_ext_ack *extack); | |
feae9087 | 355 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
356 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
357 | struct netlink_ext_ack *extack); | |
bffaa916 RD |
358 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
359 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode); | |
98fdbea5 LR |
360 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
361 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 362 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
363 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
364 | enum devlink_eswitch_encap_mode *encap); | |
a4b97ab4 | 365 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 366 | |
f5f82476 OG |
367 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
368 | struct mlx5_esw_flow_attr *attr); | |
369 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
370 | struct mlx5_esw_flow_attr *attr); | |
371 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
372 | int vport, u16 vlan, u8 qos, u8 set_flags); | |
373 | ||
cc495188 JL |
374 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
375 | u8 vlan_depth) | |
6acfbf38 | 376 | { |
cc495188 JL |
377 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
378 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
379 | ||
380 | if (vlan_depth == 1) | |
381 | return ret; | |
382 | ||
383 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
384 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
385 | } |
386 | ||
eff849b2 RL |
387 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
388 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
389 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
390 | struct mlx5_core_dev *dev1); | |
eff849b2 | 391 | |
10ee82ce | 392 | int mlx5_esw_query_functions(struct mlx5_core_dev *dev, u32 *out, int outlen); |
cd56f929 | 393 | |
69697b6e OG |
394 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
395 | ||
27b942fb PP |
396 | #define esw_info(__dev, format, ...) \ |
397 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 398 | |
27b942fb PP |
399 | #define esw_warn(__dev, format, ...) \ |
400 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
401 | |
402 | #define esw_debug(dev, format, ...) \ | |
403 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
404 | |
405 | /* The returned number is valid only when the dev is eswitch manager. */ | |
406 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
407 | { | |
408 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
409 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
410 | } | |
411 | ||
6706a3b9 VP |
412 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) |
413 | { | |
414 | /* Ideally device should have the functions changed supported | |
415 | * capability regardless of it being ECPF or PF wherever such | |
416 | * event should be processed such as on eswitch manager device. | |
417 | * However, some ECPF based device might not have this capability | |
418 | * set. Hence OR for ECPF check to cover such device. | |
419 | */ | |
420 | return MLX5_CAP_ESW(dev, esw_functions_changed) || | |
421 | mlx5_core_is_ecpf_esw_manager(dev); | |
422 | } | |
423 | ||
5ae51620 BW |
424 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
425 | { | |
426 | /* Uplink always locate at the last element of the array.*/ | |
427 | return esw->total_vports - 1; | |
428 | } | |
429 | ||
81cd229c BW |
430 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
431 | { | |
432 | return esw->total_vports - 2; | |
433 | } | |
434 | ||
5ae51620 BW |
435 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
436 | u16 vport_num) | |
437 | { | |
81cd229c BW |
438 | if (vport_num == MLX5_VPORT_ECPF) { |
439 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
440 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
441 | return mlx5_eswitch_ecpf_idx(esw); | |
442 | } | |
443 | ||
5ae51620 BW |
444 | if (vport_num == MLX5_VPORT_UPLINK) |
445 | return mlx5_eswitch_uplink_idx(esw); | |
446 | ||
447 | return vport_num; | |
448 | } | |
449 | ||
450 | static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, | |
451 | int index) | |
452 | { | |
81cd229c BW |
453 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
454 | mlx5_ecpf_vport_exists(esw->dev)) | |
455 | return MLX5_VPORT_ECPF; | |
456 | ||
5ae51620 BW |
457 | if (index == mlx5_eswitch_uplink_idx(esw)) |
458 | return MLX5_VPORT_UPLINK; | |
459 | ||
460 | return index; | |
461 | } | |
462 | ||
ee576ec1 SM |
463 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
464 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
465 | ||
786ef904 PP |
466 | /* The vport getter/iterator are only valid after esw->total_vports |
467 | * and vport->vport are initialized in mlx5_eswitch_init. | |
468 | */ | |
469 | #define mlx5_esw_for_all_vports(esw, i, vport) \ | |
470 | for ((i) = MLX5_VPORT_PF; \ | |
471 | (vport) = &(esw)->vports[i], \ | |
472 | (i) < (esw)->total_vports; (i)++) | |
473 | ||
474 | #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \ | |
475 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
476 | (vport) = &(esw)->vports[(i)], \ | |
477 | (i) <= (nvfs); (i)++) | |
478 | ||
479 | #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \ | |
480 | for ((i) = (nvfs); \ | |
481 | (vport) = &(esw)->vports[(i)], \ | |
482 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
483 | ||
484 | /* The rep getter/iterator are only valid after esw->total_vports | |
485 | * and vport->vport are initialized in mlx5_eswitch_init. | |
486 | */ | |
487 | #define mlx5_esw_for_all_reps(esw, i, rep) \ | |
488 | for ((i) = MLX5_VPORT_PF; \ | |
489 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
490 | (i) < (esw)->total_vports; (i)++) | |
491 | ||
492 | #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \ | |
493 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
494 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
495 | (i) <= (nvfs); (i)++) | |
496 | ||
497 | #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \ | |
498 | for ((i) = (nvfs); \ | |
499 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
500 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
501 | ||
502 | #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \ | |
503 | for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++) | |
504 | ||
505 | #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \ | |
506 | for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--) | |
507 | ||
5d9986a3 BW |
508 | struct mlx5_vport *__must_check |
509 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
510 | ||
91d6291c PP |
511 | bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num); |
512 | ||
e80541ec SM |
513 | #else /* CONFIG_MLX5_ESWITCH */ |
514 | /* eswitch API stubs */ | |
515 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
516 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
e80541ec SM |
517 | static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; } |
518 | static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {} | |
eff849b2 | 519 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 520 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
10ee82ce BW |
521 | static inline int |
522 | mlx5_esw_query_functions(struct mlx5_core_dev *dev, u32 *out, int outlen) | |
523 | { | |
524 | return -EOPNOTSUPP; | |
525 | } | |
328edb49 PB |
526 | |
527 | #define FDB_MAX_CHAIN 1 | |
c92a0b94 | 528 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
529 | #define FDB_MAX_PRIO 1 |
530 | ||
e80541ec SM |
531 | #endif /* CONFIG_MLX5_ESWITCH */ |
532 | ||
073bb189 | 533 | #endif /* __MLX5_ESWITCH_H__ */ |