[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.h

/*
 * Copyright (c) 2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_ESWITCH_H__
#define __MLX5_ESWITCH_H__

#include <linux/if_ether.h>
#include <linux/if_link.h>
#include <net/devlink.h>
#include <linux/mlx5/device.h>
#include "lib/mpfs.h"

enum {
	SRIOV_NONE,
	SRIOV_LEGACY,
	SRIOV_OFFLOADS
};

enum {
	REP_ETH,
	NUM_REP_TYPES,
};

#ifdef CONFIG_MLX5_ESWITCH

#define MLX5_MAX_UC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))

#define MLX5_MAX_MC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))

#define FDB_UPLINK_VPORT 0xffff

#define MLX5_MIN_BW_SHARE 1

#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)

struct vport_ingress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	struct mlx5_flow_group *allow_spoofchk_only_grp;
	struct mlx5_flow_group *allow_untagged_only_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allow_rule;
	struct mlx5_flow_handle  *drop_rule;
};

struct vport_egress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allowed_vlans_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allowed_vlan;
	struct mlx5_flow_handle  *drop_rule;
};

struct mlx5_vport_info {
	u8                      mac[ETH_ALEN];
	u16                     vlan;
	u8                      qos;
	u64                     node_guid;
	int                     link_state;
	u32                     min_rate;
	u32                     max_rate;
	bool                    spoofchk;
	bool                    trusted;
};

struct mlx5_vport {
	struct mlx5_core_dev    *dev;
	int                     vport;
	struct hlist_head       uc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct hlist_head       mc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct mlx5_flow_handle *promisc_rule;
	struct mlx5_flow_handle *allmulti_rule;
	struct work_struct      vport_change_handler;

	struct vport_ingress    ingress;
	struct vport_egress     egress;

	struct mlx5_vport_info  info;

	struct {
		bool            enabled;
		u32             esw_tsar_ix;
		u32             bw_share;
	} qos;

	bool                    enabled;
	u16                     enabled_events;
};

struct mlx5_eswitch_fdb {
	void *fdb;
	union {
		struct legacy_fdb {
			struct mlx5_flow_group *addr_grp;
			struct mlx5_flow_group *allmulti_grp;
			struct mlx5_flow_group *promisc_grp;
		} legacy;

		struct offloads_fdb {
			struct mlx5_flow_table *fdb;
			struct mlx5_flow_group *send_to_vport_grp;
			struct mlx5_flow_group *miss_grp;
			struct mlx5_flow_handle *miss_rule;
			int vlan_push_pop_refcount;
		} offloads;
	};
};

struct mlx5_eswitch_rep;
struct mlx5_eswitch_rep_if {
	int		       (*load)(struct mlx5_core_dev *dev,
				       struct mlx5_eswitch_rep *rep);
	void		       (*unload)(struct mlx5_eswitch_rep *rep);
	void			*priv;
	bool		       valid;
};

struct mlx5_eswitch_rep {
	struct mlx5_eswitch_rep_if rep_if[NUM_REP_TYPES];
	u16		       vport;
	u8		       hw_id[ETH_ALEN];
	u16		       vlan;
	u32		       vlan_refcount;
};

struct mlx5_esw_offload {
	struct mlx5_flow_table *ft_offloads;
	struct mlx5_flow_group *vport_rx_group;
	struct mlx5_eswitch_rep *vport_reps;
	DECLARE_HASHTABLE(encap_tbl, 8);
	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
	u8 inline_mode;
	u64 num_flows;
	u8 encap;
};

/* E-Switch MC FDB table hash node */
struct esw_mc_addr { /* SRIOV only */
	struct l2addr_node     node;
	struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
	u32                    refcnt;
};

struct mlx5_eswitch {
	struct mlx5_core_dev    *dev;
	struct mlx5_eswitch_fdb fdb_table;
	struct hlist_head       mc_table[MLX5_L2_ADDR_HASH_SIZE];
	struct workqueue_struct *work_queue;
	struct mlx5_vport       *vports;
	int                     total_vports;
	int                     enabled_vports;
	/* Synchronize between vport change events
	 * and async SRIOV admin state changes
	 */
	struct mutex            state_lock;
	struct esw_mc_addr	mc_promisc;

	struct {
		bool            enabled;
		u32             root_tsar_id;
	} qos;

	struct mlx5_esw_offload offloads;
	int                     mode;
};

void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
int esw_offloads_init_reps(struct mlx5_eswitch *esw);

/* E-Switch API */
int mlx5_eswitch_init(struct mlx5_core_dev *dev);
void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe);
int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
			       int vport, u8 mac[ETH_ALEN]);
int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
				 int vport, int link_state);
int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				int vport, u16 vlan, u8 qos);
int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
				    int vport, bool spoofchk);
int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
				 int vport_num, bool setting);
int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
				u32 max_rate, u32 min_rate);
int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
				  int vport, struct ifla_vf_info *ivi);
int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
				 int vport,
				 struct ifla_vf_stats *vf_stats);
struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport,
				    u32 sqn);
void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);

struct mlx5_flow_spec;
struct mlx5_esw_flow_attr;

struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_spec *spec,
				struct mlx5_esw_flow_attr *attr);
void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_handle *rule,
				struct mlx5_esw_flow_attr *attr);

struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);

enum {
	SET_VLAN_STRIP	= BIT(0),
	SET_VLAN_INSERT	= BIT(1)
};

#define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  0x4000
#define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x8000

struct mlx5_esw_flow_attr {
	struct mlx5_eswitch_rep *in_rep;
	struct mlx5_eswitch_rep *out_rep;

	int	action;
	u16	vlan;
	bool	vlan_handled;
	u32	encap_id;
	u32	mod_hdr_id;
	struct mlx5e_tc_flow_parse_attr *parse_attr;
};

int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode);
int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode);
int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap);
int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
				     int vport_index,
				     struct mlx5_eswitch_rep_if *rep_if,
				     u8 rep_type);
void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
				       int vport_index,
				       u8 rep_type);
void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);

int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				  int vport, u16 vlan, u8 qos, u8 set_flags);

#define MLX5_DEBUG_ESWITCH_MASK BIT(3)

#define esw_info(dev, format, ...)				\
	pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)

#define esw_warn(dev, format, ...)				\
	pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)

#define esw_debug(dev, format, ...)				\
	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
#else  /* CONFIG_MLX5_ESWITCH */
/* eswitch API stubs */
static inline int  mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
static inline void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) {}
static inline int  mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
#endif /* CONFIG_MLX5_ESWITCH */

#endif /* __MLX5_ESWITCH_H__ */
Commit	Line	Data
073bb189 SM	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_ESWITCH_H__
	34	#define __MLX5_ESWITCH_H__
	35
77256579 SM	36	#include <linux/if_ether.h>
77256579 SM	37	#include <linux/if_link.h>
feae9087	38	#include <net/devlink.h>
073bb189	39	#include <linux/mlx5/device.h>
eeb66cdb	40	#include "lib/mpfs.h"
073bb189	41
e80541ec SM	42	enum {
	43	SRIOV_NONE,
	44	SRIOV_LEGACY,
	45	SRIOV_OFFLOADS
	46	};
	47
a4b97ab4 MB	48	enum {
	49	REP_ETH,
	50	NUM_REP_TYPES,
	51	};
	52
e80541ec SM	53	#ifdef CONFIG_MLX5_ESWITCH
e80541ec SM	54
073bb189 SM	55	#define MLX5_MAX_UC_PER_VPORT(dev) \
	56	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
	57
	58	#define MLX5_MAX_MC_PER_VPORT(dev) \
	59	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
	60
cb67b832 HHZ	61	#define FDB_UPLINK_VPORT 0xffff
cb67b832 HHZ	62
c9497c98 MHY	63	#define MLX5_MIN_BW_SHARE 1
	64
	65	#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	66	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
	67
5742df0f MHY	68	struct vport_ingress {
	69	struct mlx5_flow_table *acl;
	70	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	71	struct mlx5_flow_group *allow_spoofchk_only_grp;
	72	struct mlx5_flow_group *allow_untagged_only_grp;
	73	struct mlx5_flow_group *drop_grp;
74491de9 MB	74	struct mlx5_flow_handle *allow_rule;
74491de9 MB	75	struct mlx5_flow_handle *drop_rule;
5742df0f MHY	76	};
	77
	78	struct vport_egress {
	79	struct mlx5_flow_table *acl;
	80	struct mlx5_flow_group *allowed_vlans_grp;
	81	struct mlx5_flow_group *drop_grp;
74491de9 MB	82	struct mlx5_flow_handle *allowed_vlan;
74491de9 MB	83	struct mlx5_flow_handle *drop_rule;
5742df0f MHY	84	};
5742df0f MHY	85
1ab2068a MHY	86	struct mlx5_vport_info {
	87	u8 mac[ETH_ALEN];
	88	u16 vlan;
	89	u8 qos;
	90	u64 node_guid;
	91	int link_state;
c9497c98	92	u32 min_rate;
1bd27b11	93	u32 max_rate;
1ab2068a MHY	94	bool spoofchk;
	95	bool trusted;
	96	};
	97
073bb189 SM	98	struct mlx5_vport {
	99	struct mlx5_core_dev *dev;
	100	int vport;
	101	struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
81848731	102	struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
74491de9 MB	103	struct mlx5_flow_handle *promisc_rule;
74491de9 MB	104	struct mlx5_flow_handle *allmulti_rule;
073bb189 SM	105	struct work_struct vport_change_handler;
073bb189 SM	106
5742df0f MHY	107	struct vport_ingress ingress;
	108	struct vport_egress egress;
	109
1ab2068a MHY	110	struct mlx5_vport_info info;
1ab2068a MHY	111
1bd27b11 MHY	112	struct {
	113	bool enabled;
	114	u32 esw_tsar_ix;
c9497c98	115	u32 bw_share;
1bd27b11 MHY	116	} qos;
1bd27b11 MHY	117
073bb189	118	bool enabled;
81848731	119	u16 enabled_events;
073bb189 SM	120	};
073bb189 SM	121
81848731 SM	122	struct mlx5_eswitch_fdb {
81848731 SM	123	void *fdb;
6ab36e35 OG	124	union {
	125	struct legacy_fdb {
	126	struct mlx5_flow_group *addr_grp;
	127	struct mlx5_flow_group *allmulti_grp;
	128	struct mlx5_flow_group *promisc_grp;
	129	} legacy;
69697b6e OG	130
69697b6e OG	131	struct offloads_fdb {
1033665e	132	struct mlx5_flow_table *fdb;
69697b6e OG	133	struct mlx5_flow_group *send_to_vport_grp;
69697b6e OG	134	struct mlx5_flow_group *miss_grp;
74491de9	135	struct mlx5_flow_handle *miss_rule;
f5f82476	136	int vlan_push_pop_refcount;
69697b6e	137	} offloads;
6ab36e35 OG	138	};
	139	};
	140
a4b97ab4 MB	141	struct mlx5_eswitch_rep;
a4b97ab4 MB	142	struct mlx5_eswitch_rep_if {
4c66df01	143	int (load)(struct mlx5_core_dev dev,
cb67b832	144	struct mlx5_eswitch_rep *rep);
4c66df01	145	void (unload)(struct mlx5_eswitch_rep rep);
5ed99fb4	146	void *priv;
a4b97ab4 MB	147	bool valid;
	148	};
	149
	150	struct mlx5_eswitch_rep {
	151	struct mlx5_eswitch_rep_if rep_if[NUM_REP_TYPES];
127ea380	152	u16 vport;
bac9b6aa	153	u8 hw_id[ETH_ALEN];
f5f82476 OG	154	u16 vlan;
f5f82476 OG	155	u32 vlan_refcount;
127ea380 HHZ	156	};
127ea380 HHZ	157
c116c6ee OG	158	struct mlx5_esw_offload {
c116c6ee OG	159	struct mlx5_flow_table *ft_offloads;
fed9ce22	160	struct mlx5_flow_group *vport_rx_group;
127ea380	161	struct mlx5_eswitch_rep *vport_reps;
a54e20b4	162	DECLARE_HASHTABLE(encap_tbl, 8);
11c9c548	163	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
bffaa916	164	u8 inline_mode;
375f51e2	165	u64 num_flows;
7768d197	166	u8 encap;
c116c6ee OG	167	};
c116c6ee OG	168
0a0ab1d2 EC	169	/* E-Switch MC FDB table hash node */
	170	struct esw_mc_addr { /* SRIOV only */
	171	struct l2addr_node node;
	172	struct mlx5_flow_handle uplink_rule; / Forward to uplink rule */
	173	u32 refcnt;
	174	};
	175
073bb189 SM	176	struct mlx5_eswitch {
073bb189 SM	177	struct mlx5_core_dev *dev;
81848731 SM	178	struct mlx5_eswitch_fdb fdb_table;
81848731 SM	179	struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
073bb189 SM	180	struct workqueue_struct *work_queue;
	181	struct mlx5_vport *vports;
	182	int total_vports;
81848731	183	int enabled_vports;
dfcb1ed3 MHY	184	/* Synchronize between vport change events
	185	* and async SRIOV admin state changes
	186	*/
	187	struct mutex state_lock;
0a0ab1d2	188	struct esw_mc_addr mc_promisc;
1bd27b11 MHY	189
	190	struct {
	191	bool enabled;
	192	u32 root_tsar_id;
	193	} qos;
	194
c116c6ee	195	struct mlx5_esw_offload offloads;
6ab36e35	196	int mode;
073bb189 SM	197	};
073bb189 SM	198
766a0e97 BX	199	void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
766a0e97 BX	200	int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
e8d31c4d MB	201	void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
e8d31c4d MB	202	int esw_offloads_init_reps(struct mlx5_eswitch *esw);
766a0e97	203
073bb189 SM	204	/* E-Switch API */
	205	int mlx5_eswitch_init(struct mlx5_core_dev *dev);
	206	void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
	207	void mlx5_eswitch_vport_event(struct mlx5_eswitch esw, struct mlx5_eqe eqe);
6ab36e35	208	int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
81848731	209	void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
77256579 SM	210	int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
	211	int vport, u8 mac[ETH_ALEN]);
	212	int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
	213	int vport, int link_state);
9e7ea352 SM	214	int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
9e7ea352 SM	215	int vport, u16 vlan, u8 qos);
f942380c MHY	216	int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
f942380c MHY	217	int vport, bool spoofchk);
1edc57e2 MHY	218	int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1edc57e2 MHY	219	int vport_num, bool setting);
c9497c98 MHY	220	int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
c9497c98 MHY	221	u32 max_rate, u32 min_rate);
77256579 SM	222	int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
77256579 SM	223	int vport, struct ifla_vf_info *ivi);
3b751a2a SM	224	int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
	225	int vport,
	226	struct ifla_vf_stats *vf_stats);
f7a68945 MB	227	struct mlx5_flow_handle *
	228	mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport,
	229	u32 sqn);
159fe639	230	void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
073bb189	231
3d80d1a2	232	struct mlx5_flow_spec;
776b12b6	233	struct mlx5_esw_flow_attr;
3d80d1a2	234
74491de9	235	struct mlx5_flow_handle *
3d80d1a2 OG	236	mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
3d80d1a2 OG	237	struct mlx5_flow_spec *spec,
776b12b6	238	struct mlx5_esw_flow_attr *attr);
d85cdccb OG	239	void
	240	mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
	241	struct mlx5_flow_handle *rule,
	242	struct mlx5_esw_flow_attr *attr);
	243
74491de9	244	struct mlx5_flow_handle *
fed9ce22 OG	245	mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);
fed9ce22 OG	246
e33dfe31 OG	247	enum {
	248	SET_VLAN_STRIP = BIT(0),
	249	SET_VLAN_INSERT = BIT(1)
	250	};
	251
2a69cb9f OG	252	#define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP 0x4000
2a69cb9f OG	253	#define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x8000
f5f82476	254
776b12b6 OG	255	struct mlx5_esw_flow_attr {
	256	struct mlx5_eswitch_rep *in_rep;
	257	struct mlx5_eswitch_rep *out_rep;
	258
	259	int action;
f5f82476 OG	260	u16 vlan;
f5f82476 OG	261	bool vlan_handled;
45247bf2	262	u32 encap_id;
d7e75a32	263	u32 mod_hdr_id;
232c0013	264	struct mlx5e_tc_flow_parse_attr *parse_attr;
776b12b6 OG	265	};
776b12b6 OG	266
feae9087 OG	267	int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode);
feae9087 OG	268	int mlx5_devlink_eswitch_mode_get(struct devlink devlink, u16 mode);
bffaa916 RD	269	int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode);
	270	int mlx5_devlink_eswitch_inline_mode_get(struct devlink devlink, u8 mode);
	271	int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch esw, int nvfs, u8 mode);
7768d197 RD	272	int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap);
7768d197 RD	273	int mlx5_devlink_eswitch_encap_mode_get(struct devlink devlink, u8 encap);
127ea380	274	void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
9deb2241	275	int vport_index,
a4b97ab4 MB	276	struct mlx5_eswitch_rep_if *rep_if,
a4b97ab4 MB	277	u8 rep_type);
127ea380	278	void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
a4b97ab4 MB	279	int vport_index,
	280	u8 rep_type);
	281	void mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch esw, u8 rep_type);
feae9087	282
f5f82476 OG	283	int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
	284	struct mlx5_esw_flow_attr *attr);
	285	int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
	286	struct mlx5_esw_flow_attr *attr);
	287	int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
	288	int vport, u16 vlan, u8 qos, u8 set_flags);
	289
69697b6e OG	290	#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
	291
	292	#define esw_info(dev, format, ...) \
	293	pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
	294
	295	#define esw_warn(dev, format, ...) \
	296	pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
	297
	298	#define esw_debug(dev, format, ...) \
	299	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
e80541ec SM	300	#else /* CONFIG_MLX5_ESWITCH */
	301	/* eswitch API stubs */
	302	static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
	303	static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
	304	static inline void mlx5_eswitch_vport_event(struct mlx5_eswitch esw, struct mlx5_eqe eqe) {}
	305	static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
	306	static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
	307	#endif /* CONFIG_MLX5_ESWITCH */
	308
073bb189	309	#endif /* __MLX5_ESWITCH_H__ */